Interrupt stack frame (ISF). More...

#include <cpu.h>

Data Fields
uint64_t	x0

uint64_t	register_lr_original

uint64_t	register_lr

uint64_t	x1

uint64_t	x2

uint64_t	x3

uint64_t	x4

uint64_t	x5

uint64_t	x6

uint64_t	x7

uint64_t	x8

uint64_t	x9

uint64_t	x10

uint64_t	x11

uint64_t	x12

uint64_t	x13

uint64_t	x14

uint64_t	x15

uint64_t	x16

uint64_t	x17

uint64_t	x18

uint64_t	x19

uint64_t	x20

uint64_t	x21

uint64_t	register_elr

uint64_t	register_spsr

uint64_t	register_fpsr

uint64_t	register_fpcr

uint32_t	reserved [3]

uint32_t	isr_vector

uint32_t	ebx

uint32_t	ebp

uint32_t	esp

uint32_t	edx

uint32_t	ecx

uint32_t	eax

uint32_t	eip

uint32_t	cs

uint32_t	eflags

uint32_t	vecnum

__MIPS_REGISTER_TYPE	r0

__MIPS_REGISTER_TYPE	at

__MIPS_REGISTER_TYPE	v0

__MIPS_REGISTER_TYPE	v1

__MIPS_REGISTER_TYPE	a0

__MIPS_REGISTER_TYPE	a1

__MIPS_REGISTER_TYPE	a2

__MIPS_REGISTER_TYPE	a3

__MIPS_REGISTER_TYPE	t0

__MIPS_REGISTER_TYPE	t1

__MIPS_REGISTER_TYPE	t2

__MIPS_REGISTER_TYPE	t3

__MIPS_REGISTER_TYPE	t4

__MIPS_REGISTER_TYPE	t5

__MIPS_REGISTER_TYPE	t6

__MIPS_REGISTER_TYPE	t7

__MIPS_REGISTER_TYPE	s0

__MIPS_REGISTER_TYPE	s1

__MIPS_REGISTER_TYPE	s2

__MIPS_REGISTER_TYPE	s3

__MIPS_REGISTER_TYPE	s4

__MIPS_REGISTER_TYPE	s5

__MIPS_REGISTER_TYPE	s6

__MIPS_REGISTER_TYPE	s7

__MIPS_REGISTER_TYPE	t8

__MIPS_REGISTER_TYPE	t9

__MIPS_REGISTER_TYPE	k0

__MIPS_REGISTER_TYPE	k1

__MIPS_REGISTER_TYPE	gp

__MIPS_REGISTER_TYPE	sp

__MIPS_REGISTER_TYPE	fp

__MIPS_REGISTER_TYPE	ra

__MIPS_REGISTER_TYPE	c0_sr

__MIPS_REGISTER_TYPE	mdlo

__MIPS_REGISTER_TYPE	mdhi

__MIPS_REGISTER_TYPE	badvaddr

__MIPS_REGISTER_TYPE	cause

__MIPS_REGISTER_TYPE	epc

__MIPS_FPU_REGISTER_TYPE	f0

__MIPS_FPU_REGISTER_TYPE	f1

__MIPS_FPU_REGISTER_TYPE	f2

__MIPS_FPU_REGISTER_TYPE	f3

__MIPS_FPU_REGISTER_TYPE	f4

__MIPS_FPU_REGISTER_TYPE	f5

__MIPS_FPU_REGISTER_TYPE	f6

__MIPS_FPU_REGISTER_TYPE	f7

__MIPS_FPU_REGISTER_TYPE	f8

__MIPS_FPU_REGISTER_TYPE	f9

__MIPS_FPU_REGISTER_TYPE	f10

__MIPS_FPU_REGISTER_TYPE	f11

__MIPS_FPU_REGISTER_TYPE	f12

__MIPS_FPU_REGISTER_TYPE	f13

__MIPS_FPU_REGISTER_TYPE	f14

__MIPS_FPU_REGISTER_TYPE	f15

__MIPS_FPU_REGISTER_TYPE	f16

__MIPS_FPU_REGISTER_TYPE	f17

__MIPS_FPU_REGISTER_TYPE	f18

__MIPS_FPU_REGISTER_TYPE	f19

__MIPS_FPU_REGISTER_TYPE	f20

__MIPS_FPU_REGISTER_TYPE	f21

__MIPS_FPU_REGISTER_TYPE	f22

__MIPS_FPU_REGISTER_TYPE	f23

__MIPS_FPU_REGISTER_TYPE	f24

__MIPS_FPU_REGISTER_TYPE	f25

__MIPS_FPU_REGISTER_TYPE	f26

__MIPS_FPU_REGISTER_TYPE	f27

__MIPS_FPU_REGISTER_TYPE	f28

__MIPS_FPU_REGISTER_TYPE	f29

__MIPS_FPU_REGISTER_TYPE	f30

__MIPS_FPU_REGISTER_TYPE	f31

__MIPS_REGISTER_TYPE	fcsr

__MIPS_REGISTER_TYPE	feir

__MIPS_REGISTER_TYPE	tlbhi

__MIPS_REGISTER_TYPE	inx

__MIPS_REGISTER_TYPE	rand

__MIPS_REGISTER_TYPE	ctxt

__MIPS_REGISTER_TYPE	exctype

__MIPS_REGISTER_TYPE	mode

__MIPS_REGISTER_TYPE	prid

__MIPS_REGISTER_TYPE	tar

uint32_t	special_interrupt_register

uintptr_t	FRAME_SP

uintptr_t	FRAME_LR

uintptr_t	EXC_SRR0

uintptr_t	EXC_SRR1

uint32_t	RESERVED_FOR_ALIGNMENT_0

uint32_t	EXC_INTERRUPT_ENTRY_INSTANT

uint32_t	EXC_CR

uint32_t	EXC_XER

uintptr_t	EXC_CTR

uintptr_t	EXC_LR

uintptr_t	EXC_INTERRUPT_FRAME

PPC_GPR_TYPE	GPR0

PPC_GPR_TYPE	GPR1

PPC_GPR_TYPE	GPR2

PPC_GPR_TYPE	GPR3

PPC_GPR_TYPE	GPR4

PPC_GPR_TYPE	GPR5

PPC_GPR_TYPE	GPR6

PPC_GPR_TYPE	GPR7

PPC_GPR_TYPE	GPR8

PPC_GPR_TYPE	GPR9

PPC_GPR_TYPE	GPR10

PPC_GPR_TYPE	GPR11

PPC_GPR_TYPE	GPR12

SPARC_Minimum_stack_frame	Stack_frame

uint32_t	psr

uint32_t	pc

uint32_t	npc

uint32_t	g1

uint32_t	g2

uint32_t	g3

uint32_t	g4

uint32_t	g5

uint32_t	reserved_for_alignment

uint32_t	g7

uint32_t	i0

uint32_t	i1

uint32_t	i2

uint32_t	i3

uint32_t	i4

uint32_t	i5

uint32_t	i6_fp

uint32_t	i7

uint32_t	y

uint32_t	tpc

uint64_t	error_code

uint64_t	rip

uint64_t	cs

uint64_t	rflags

uint64_t	rsp

uint64_t	ss

uint64_t	rdi

uint64_t	rbp

uint64_t	rbx

uint8_t	sse_state [512]

uint64_t	rax

uint64_t	rcx

uint64_t	rdx

uint64_t	rsi

uint64_t	r8

uint64_t	r9

uint64_t	r10

uint64_t	r11

uint64_t	saved_rsp

uint8_t	padding [8]

Detailed Description

Interrupt stack frame (ISF).

Context saved on stack for an interrupt.

NOTE: The PSR, PC, and NPC are only saved in this structure for the benefit of the user's handler.

Field Documentation

◆ g1

uint32_t CPU_Interrupt_frame::g1

This is the offset of the g1 register on an ISF.

◆ g2

uint32_t CPU_Interrupt_frame::g2

This is the offset of the g2 register on an ISF.

◆ g3

uint32_t CPU_Interrupt_frame::g3

This is the offset of the g3 register on an ISF.

◆ g4

uint32_t CPU_Interrupt_frame::g4

This is the offset of the g4 register on an ISF.

◆ g5

uint32_t CPU_Interrupt_frame::g5

This is the offset of the g5 register on an ISF.

◆ g7

uint32_t CPU_Interrupt_frame::g7

This is the offset of the g7 register on an ISF.

◆ i0

uint32_t CPU_Interrupt_frame::i0

This is the offset of the i0 register on an ISF.

◆ i1

uint32_t CPU_Interrupt_frame::i1

This is the offset of the i1 register on an ISF.

◆ i2

uint32_t CPU_Interrupt_frame::i2

This is the offset of the i2 register on an ISF.

◆ i3

uint32_t CPU_Interrupt_frame::i3

This is the offset of the i3 register on an ISF.

◆ i4

uint32_t CPU_Interrupt_frame::i4

This is the offset of the i4 register on an ISF.

◆ i5

uint32_t CPU_Interrupt_frame::i5

This is the offset of the i5 register on an ISF.

◆ i6_fp

uint32_t CPU_Interrupt_frame::i6_fp

This is the offset of the i6 register on an ISF.

◆ i7

uint32_t CPU_Interrupt_frame::i7

This is the offset of the i7 register on an ISF.

◆ npc

uint32_t CPU_Interrupt_frame::npc

This is the offset of the XXX on an ISF.

◆ padding

uint8_t CPU_Interrupt_frame::padding[8]

The caller-saved registers needs to start in a 16-byte aligned position on the stack for the FXSAVE instruction. Therefore, we have 8 extra bytes in case the interrupt handler needs to align it.

◆ pc

uint32_t CPU_Interrupt_frame::pc

This is the offset of the XXX on an ISF.

◆ psr

uint32_t CPU_Interrupt_frame::psr

This is the offset of the PSR on an ISF.

◆ reserved_for_alignment

uint32_t CPU_Interrupt_frame::reserved_for_alignment

This is the offset is reserved for alignment on an ISF.

◆ special_interrupt_register

uint32_t CPU_Interrupt_frame::special_interrupt_register

This field is a hint that a port will have a number of integer registers that need to be saved when an interrupt occurs or when a context switch occurs at the end of an ISR.

◆ Stack_frame

SPARC_Minimum_stack_frame CPU_Interrupt_frame::Stack_frame

On an interrupt, we must save the minimum stack frame.

◆ tpc

uint32_t CPU_Interrupt_frame::tpc

This is the offset of the tpc register on an ISF.

◆ y

uint32_t CPU_Interrupt_frame::y

This is the offset of the y register on an ISF.

The documentation for this struct was generated from the following files:

cpukit/score/cpu/aarch64/include/rtems/score/cpuimpl.h
cpukit/score/cpu/i386/include/rtems/score/cpu.h
cpukit/score/cpu/m68k/include/rtems/score/cpu.h
cpukit/score/cpu/mips/include/rtems/score/cpu.h
cpukit/score/cpu/moxie/include/rtems/score/cpu.h
cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h
cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h
cpukit/score/cpu/sparc/include/rtems/score/cpu.h
cpukit/score/cpu/x86_64/include/rtems/score/cpu.h

Data Fields