RTEMS
7.0-rc1
Loading...
Searching...
No Matches
bsps
arm
stm32u5
include
stm32u5xx.h
Go to the documentation of this file.
1
37
#ifndef STM32U5xx_H
38
#define STM32U5xx_H
39
40
#ifdef __cplusplus
41
extern
"C"
{
42
#endif
/* __cplusplus */
43
#ifdef __rtems__
44
#ifndef USE_FULL_LL_DRIVER
45
#define USE_FULL_LL_DRIVER
46
#endif
47
#endif
/* __rtems__ */
48
56
#if !defined (STM32U5)
57
#define STM32U5
58
#endif
/* STM32U5 */
59
60
/* Uncomment the line below according to the target STM32U5 device used in your
61
application
62
*/
63
64
#if !defined (STM32U575xx) && !defined (STM32U585xx) \
65
&& !defined (STM32U595xx) && !defined (STM32U599xx) \
66
&& !defined (STM32U5A5xx) && !defined (STM32U5A9xx) \
67
&& !defined (STM32U5F7xx) && !defined (STM32U5G7xx) \
68
&& !defined (STM32U5F9xx) && !defined (STM32U5G9xx) \
69
&& !defined (STM32U535xx) && !defined (STM32U545xx) \
70
/* #define STM32U575xx */
71
/* #define STM32U585xx */
72
/* #define STM32U595xx */
73
/* #define STM32U599xx */
74
/* #define STM32U5A5xx */
75
/* #define STM32U5A9xx */
76
/* #define STM32U5F7xx */
77
/* #define STM32U5G7xx */
78
/* #define STM32U5F9xx */
79
#define STM32U5G9xx
80
/* #define STM32U535xx */
81
/* #define STM32U545xx */
82
#endif
83
84
/* Tip: To avoid modifying this file each time you need to switch between these
85
devices, you can define the device in your toolchain compiler preprocessor.
86
*/
87
#if !defined (USE_HAL_DRIVER)
93
/*#define USE_HAL_DRIVER */
94
#endif
/* USE_HAL_DRIVER */
95
99
#define __STM32U5_CMSIS_VERSION_MAIN (0x01)
100
#define __STM32U5_CMSIS_VERSION_SUB1 (0x04)
101
#define __STM32U5_CMSIS_VERSION_SUB2 (0x00)
102
#define __STM32U5_CMSIS_VERSION_RC (0x00)
103
#define __STM32U5_CMSIS_VERSION ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\
104
|(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\
105
|(__STM32U5_CMSIS_VERSION_SUB2 << 8U )\
106
|(__STM32U5_CMSIS_VERSION_RC))
107
116
#if defined(STM32U575xx)
117
#include "stm32u575xx.h"
118
#elif defined(STM32U585xx)
119
#include "stm32u585xx.h"
120
#elif defined(STM32U595xx)
121
#include "stm32u595xx.h"
122
#elif defined(STM32U599xx)
123
#include "stm32u599xx.h"
124
#elif defined(STM32U5A5xx)
125
#include "stm32u5a5xx.h"
126
#elif defined(STM32U5A9xx)
127
#include "stm32u5a9xx.h"
128
#elif defined(STM32U5F9xx)
129
#include "stm32u5f9xx.h"
130
#elif defined(STM32U5G9xx)
131
#include "
stm32u5g9xx.h
"
132
#elif defined(STM32U5F7xx)
133
#include "stm32u5f7xx.h"
134
#elif defined(STM32U5G7xx)
135
#include "stm32u5g7xx.h"
136
#elif defined(STM32U535xx)
137
#include "stm32u535xx.h"
138
#elif defined(STM32U545xx)
139
#include "stm32u545xx.h"
140
#else
141
#error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)"
142
#endif
143
151
typedef
enum
152
{
153
RESET = 0,
154
SET = !RESET
155
} FlagStatus, ITStatus;
156
157
typedef
enum
158
{
159
DISABLE = 0,
160
ENABLE = !DISABLE
161
} FunctionalState;
162
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
163
164
typedef
enum
165
{
166
SUCCESS = 0,
167
ERROR = !SUCCESS
168
} ErrorStatus;
169
178
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
179
180
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
181
182
#define READ_BIT(REG, BIT) ((REG) & (BIT))
183
184
#define CLEAR_REG(REG) ((REG) = (0x0))
185
186
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
187
188
#define READ_REG(REG) ((REG))
189
190
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
191
192
/* Use of CMSIS compiler intrinsics for register exclusive access */
193
/* Atomic 32-bit register access macro to set one or several bits */
194
#define ATOMIC_SET_BIT(REG, BIT) \
195
do { \
196
uint32_t val; \
197
do { \
198
val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \
199
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
200
} while(0)
201
202
/* Atomic 32-bit register access macro to clear one or several bits */
203
#define ATOMIC_CLEAR_BIT(REG, BIT) \
204
do { \
205
uint32_t val; \
206
do { \
207
val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \
208
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
209
} while(0)
210
211
/* Atomic 32-bit register access macro to clear and set one or several bits */
212
#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \
213
do { \
214
uint32_t val; \
215
do { \
216
val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
217
} while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \
218
} while(0)
219
220
/* Atomic 16-bit register access macro to set one or several bits */
221
#define ATOMIC_SETH_BIT(REG, BIT) \
222
do { \
223
uint16_t val; \
224
do { \
225
val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \
226
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
227
} while(0)
228
229
/* Atomic 16-bit register access macro to clear one or several bits */
230
#define ATOMIC_CLEARH_BIT(REG, BIT) \
231
do { \
232
uint16_t val; \
233
do { \
234
val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \
235
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
236
} while(0)
237
238
/* Atomic 16-bit register access macro to clear and set one or several bits */
239
#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \
240
do { \
241
uint16_t val; \
242
do { \
243
val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \
244
} while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \
245
} while(0)
246
247
#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
248
249
254
#if defined (USE_HAL_DRIVER)
255
#include "stm32u5xx_hal.h"
256
#endif
/* USE_HAL_DRIVER */
257
258
#ifdef __cplusplus
259
}
260
#endif
/* __cplusplus */
261
262
#endif
/* STM32U5xx_H */
stm32u5g9xx.h
CMSIS STM32U5G9xx Device Peripheral Access Layer Header File.
Generated by
1.9.6
1.9.6