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RTEMS 7.0-rc1
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RTEMS 7.0-rc1
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CMSIS STM32U5G9xx Device Peripheral Access Layer Header File. More...
Go to the source code of this file.
Data Structures | |
| struct | CRC_TypeDef |
| CRC calculation unit. More... | |
| struct | I2C_TypeDef |
| Inter-integrated Circuit Interface. More... | |
| struct | DAC_TypeDef |
| DAC. More... | |
| struct | CRS_TypeDef |
| Clock Recovery System. More... | |
| struct | AES_TypeDef |
| AES hardware accelerator. More... | |
| struct | HASH_TypeDef |
| HASH. More... | |
| struct | HASH_DIGEST_TypeDef |
| HASH_DIGEST. More... | |
| struct | RNG_TypeDef |
| RNG. More... | |
| struct | DBGMCU_TypeDef |
| Debug MCU. More... | |
| struct | DCMI_TypeDef |
| DCMI. More... | |
| struct | DMA_TypeDef |
| DMA Controller. More... | |
| struct | DMA_Channel_TypeDef |
| struct | DMA2D_TypeDef |
| DMA2D Controller. More... | |
| struct | DSI_TypeDef |
| DSI Controller. More... | |
| struct | EXTI_TypeDef |
| Asynch Interrupt/Event Controller (EXTI) More... | |
| struct | FLASH_TypeDef |
| FLASH Registers. More... | |
| struct | FMAC_TypeDef |
| FMAC. More... | |
| struct | GFXMMU_TypeDef |
| GFXMMU registers. More... | |
| struct | GPIO_TypeDef |
| General Purpose I/O. More... | |
| struct | GTZC_TZSC_TypeDef |
| Global TrustZone Controller. More... | |
| struct | GTZC_MPCBB_TypeDef |
| struct | GTZC_TZIC_TypeDef |
| struct | GFXTIM_TypeDef |
| GFXTIM. More... | |
| struct | JPEG_TypeDef |
| JPEG Codec. More... | |
| struct | LTDC_TypeDef |
| LCD-TFT Display Controller. More... | |
| struct | LTDC_Layer_TypeDef |
| LCD-TFT Display layer x Controller. More... | |
| struct | ICACHE_TypeDef |
| Instruction Cache. More... | |
| struct | DCACHE_TypeDef |
| Data Cache. More... | |
| struct | PSSI_TypeDef |
| PSSI. More... | |
| struct | TIM_TypeDef |
| TIM. More... | |
| struct | LPTIM_TypeDef |
| LPTIMER. More... | |
| struct | COMP_TypeDef |
| Comparator. More... | |
| struct | COMP_Common_TypeDef |
| struct | OPAMP_TypeDef |
| Operational Amplifier (OPAMP) More... | |
| struct | OPAMP_Common_TypeDef |
| struct | MDF_TypeDef |
| MDF/ADF. More... | |
| struct | MDF_Filter_TypeDef |
| MDF/ADF filter. More... | |
| struct | XSPI_TypeDef |
| HEXA and OCTO Serial Peripheral Interface. More... | |
| struct | OTFDEC_Region_TypeDef |
| OTFDEC register. More... | |
| struct | OTFDEC_TypeDef |
| struct | XSPIM_TypeDef |
| Serial Peripheral Interface IO Manager. More... | |
| struct | PWR_TypeDef |
| Power Control. More... | |
| struct | RAMCFG_TypeDef |
| SRAMs configuration controller. More... | |
| struct | RCC_TypeDef |
| Reset and Clock Control. More... | |
| struct | PKA_TypeDef |
| PKA. More... | |
| struct | RTC_TypeDef |
| Real-Time Clock. More... | |
| struct | TAMP_TypeDef |
| Tamper and backup registers. More... | |
| struct | USART_TypeDef |
| Universal Synchronous Asynchronous Receiver Transmitter. More... | |
| struct | SAI_TypeDef |
| Serial Audio Interface. More... | |
| struct | SAI_Block_TypeDef |
| struct | SYSCFG_TypeDef |
| System configuration controller. More... | |
| struct | SDMMC_TypeDef |
| Secure digital input/output Interface. More... | |
| struct | DLYB_TypeDef |
| Delay Block DLYB. More... | |
| struct | UCPD_TypeDef |
| UCPD. More... | |
| struct | USB_OTG_GlobalTypeDef |
| USB_OTG_Core_register. More... | |
| struct | USB_OTG_DeviceTypeDef |
| USB_OTG_device_Registers. More... | |
| struct | USB_OTG_INEndpointTypeDef |
| USB_OTG_IN_Endpoint-Specific_Register. More... | |
| struct | USB_OTG_OUTEndpointTypeDef |
| USB_OTG_OUT_Endpoint-Specific_Registers. More... | |
| struct | USB_OTG_HostTypeDef |
| USB_OTG_Host_Mode_Register_Structures. More... | |
| struct | USB_OTG_HostChannelTypeDef |
| USB_OTG_Host_Channel_Specific_Registers. More... | |
| struct | FDCAN_GlobalTypeDef |
| FD Controller Area Network. More... | |
| struct | FDCAN_Config_TypeDef |
| FD Controller Area Network Configuration. More... | |
| struct | FMC_Bank1_TypeDef |
| Flexible Memory Controller. More... | |
| struct | FMC_Bank1E_TypeDef |
| Flexible Memory Controller Bank1E. More... | |
| struct | FMC_Bank3_TypeDef |
| Flexible Memory Controller Bank3. More... | |
| struct | VREFBUF_TypeDef |
| VREFBUF. More... | |
| struct | ADC_TypeDef |
| ADC. More... | |
| struct | ADC_Common_TypeDef |
| struct | CORDIC_TypeDef |
| CORDIC. More... | |
| struct | IWDG_TypeDef |
| IWDG. More... | |
| struct | SPI_TypeDef |
| SPI. More... | |
| struct | TSC_TypeDef |
| Touch Sensing Controller (TSC) More... | |
| struct | WWDG_TypeDef |
| WWDG. More... | |
| struct | NSC_pFuncTypeDef |
| RSSLib non-secure callable function pointer structure. More... | |
| struct | S_pFuncTypeDef |
| RSSLib secure callable function pointer structure. More... | |
| struct | RSSLIB_pFunc_TypeDef |
| RSSLib function pointer structure. More... | |
Macros | |
| #define | __CM33_REV 0x0000U /* Core revision r0p1 */ |
| #define | __SAUREGION_PRESENT 1U /* SAU regions present */ |
| #define | __MPU_PRESENT 1U /* MPU present */ |
| #define | __VTOR_PRESENT 1U /* VTOR present */ |
| #define | __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ |
| #define | __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ |
| #define | __FPU_PRESENT 1U /* FPU present */ |
| #define | __DSP_PRESENT 1U /* DSP extension present */ |
| #define | __ICACHE_PRESENT 1U /* ICACHE present */ |
| #define | __DCACHE_PRESENT 1U /* DCACHE present */ |
| #define | RTC_BKP_NB 32U |
| #define | RTC_TAMP_NB 8U |
| #define | PW PWRR |
| #define | SRAM1_SIZE (0xC0000UL) |
| #define | SRAM2_SIZE (0x10000UL) |
| #define | SRAM3_SIZE (0xD0000UL) |
| #define | SRAM4_SIZE (0x04000UL) |
| #define | SRAM5_SIZE (0xD0000UL) |
| #define | SRAM6_SIZE (0x80000UL) |
| #define | FMC_BASE (0x60000000UL) |
| #define | OCTOSPI2_BASE (0x70000000UL) |
| #define | OCTOSPI1_BASE (0x90000000UL) |
| #define | HSPI1_BASE (0xA0000000UL) |
| #define | FMC_BANK1 FMC_BASE |
| #define | FMC_BANK1_1 FMC_BANK1 |
| #define | FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) |
| #define | FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) |
| #define | FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) |
| #define | FMC_BANK3 (FMC_BASE + 0x20000000UL) |
| #define | FLASH_BASE_NS (0x08000000UL) |
| #define | SRAM1_BASE_NS (0x20000000UL) |
| #define | SRAM2_BASE_NS (0x200C0000UL) |
| #define | SRAM3_BASE_NS (0x200D0000UL) |
| #define | SRAM4_BASE_NS (0x28000000UL) |
| #define | SRAM5_BASE_NS (0x201A0000UL) |
| #define | SRAM6_BASE_NS (0x20270000UL) |
| #define | PERIPH_BASE_NS (0x40000000UL) |
| #define | APB1PERIPH_BASE_NS PERIPH_BASE_NS |
| #define | APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) |
| #define | AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) |
| #define | AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) |
| #define | APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) |
| #define | AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) |
| #define | TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) |
| #define | TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) |
| #define | TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) |
| #define | TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) |
| #define | TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) |
| #define | TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) |
| #define | WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) |
| #define | IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) |
| #define | SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) |
| #define | USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) |
| #define | USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) |
| #define | UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) |
| #define | UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) |
| #define | I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) |
| #define | I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) |
| #define | CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) |
| #define | USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) |
| #define | I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) |
| #define | LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) |
| #define | I2C5_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL) |
| #define | I2C6_BASE_NS (APB1PERIPH_BASE_NS + 0x9C00UL) |
| #define | FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) |
| #define | FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) |
| #define | SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) |
| #define | UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) |
| #define | TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) |
| #define | SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) |
| #define | TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) |
| #define | USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) |
| #define | TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) |
| #define | TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) |
| #define | TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) |
| #define | SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) |
| #define | SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) |
| #define | SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) |
| #define | SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) |
| #define | SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) |
| #define | SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) |
| #define | LTDC_BASE_NS (APB2PERIPH_BASE_NS + 0x6800UL) |
| #define | LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0084UL) |
| #define | LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0104UL) |
| #define | GFXTIM_BASE_NS (APB2PERIPH_BASE_NS + 0x6400UL) |
| #define | DSI_BASE_NS (APB2PERIPH_BASE_NS + 0x6C00UL) |
| #define | REFBIAS_BASE_NS (DSI_BASE_NS + 0x800UL) |
| #define | DPHY_BASE_NS (DSI_BASE_NS + 0xC00UL) |
| #define | SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) |
| #define | SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) |
| #define | LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) |
| #define | I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) |
| #define | LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) |
| #define | LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) |
| #define | LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) |
| #define | OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) |
| #define | OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) |
| #define | OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) |
| #define | COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) |
| #define | COMP1_BASE_NS (COMP12_BASE_NS) |
| #define | COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) |
| #define | VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) |
| #define | RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) |
| #define | TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) |
| #define | GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) |
| #define | GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) |
| #define | GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) |
| #define | GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) |
| #define | GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) |
| #define | GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) |
| #define | GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) |
| #define | GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) |
| #define | GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) |
| #define | GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) |
| #define | GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) |
| #define | GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) |
| #define | GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) |
| #define | GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) |
| #define | GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) |
| #define | GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) |
| #define | GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) |
| #define | CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) |
| #define | FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) |
| #define | FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) |
| #define | CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) |
| #define | TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) |
| #define | MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) |
| #define | MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) |
| #define | MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) |
| #define | MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) |
| #define | MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) |
| #define | MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) |
| #define | MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) |
| #define | RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) |
| #define | RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) |
| #define | RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) |
| #define | RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) |
| #define | RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) |
| #define | RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) |
| #define | RAMCFG_SRAM5_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) |
| #define | RAMCFG_SRAM6_BASE_NS (RAMCFG_BASE_NS + 0x0180UL) |
| #define | JPEG_BASE_NS (AHB1PERIPH_BASE_NS + 0x0A000UL) |
| #define | DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) |
| #define | GFXMMU_BASE_NS (AHB1PERIPH_BASE_NS + 0x0C000UL) |
| #define | GPU2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0F000UL) |
| #define | ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) |
| #define | DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) |
| #define | DCACHE2_BASE_NS (AHB1PERIPH_BASE_NS + 0x11800UL) |
| #define | GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) |
| #define | GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) |
| #define | GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) |
| #define | GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) |
| #define | GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) |
| #define | GTZC_MPCBB5_BASE_NS (AHB1PERIPH_BASE_NS + 0x13800UL) |
| #define | GTZC_MPCBB6_BASE_NS (AHB1PERIPH_BASE_NS + 0x13C00UL) |
| #define | BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) |
| #define | GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) |
| #define | GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) |
| #define | GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) |
| #define | GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) |
| #define | GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) |
| #define | GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) |
| #define | GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) |
| #define | GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) |
| #define | GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) |
| #define | GPIOJ_BASE_NS (AHB2PERIPH_BASE_NS + 0x02400UL) |
| #define | ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) |
| #define | ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) |
| #define | ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) |
| #define | DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) |
| #define | PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) |
| #define | USB_OTG_HS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) |
| #define | AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) |
| #define | HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) |
| #define | HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) |
| #define | RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) |
| #define | SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) |
| #define | PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) |
| #define | PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) |
| #define | OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) |
| #define | OTFDEC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5000UL) |
| #define | OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) |
| #define | OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) |
| #define | OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) |
| #define | OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) |
| #define | OTFDEC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5400UL) |
| #define | OTFDEC2_REGION1_BASE_NS (OTFDEC2_BASE_NS + 0x20UL) |
| #define | OTFDEC2_REGION2_BASE_NS (OTFDEC2_BASE_NS + 0x50UL) |
| #define | OTFDEC2_REGION3_BASE_NS (OTFDEC2_BASE_NS + 0x80UL) |
| #define | OTFDEC2_REGION4_BASE_NS (OTFDEC2_BASE_NS + 0xB0UL) |
| #define | SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) |
| #define | SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) |
| #define | DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) |
| #define | DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) |
| #define | DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) |
| #define | DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) |
| #define | FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) |
| #define | FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) |
| #define | FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) |
| #define | FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) |
| #define | OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) |
| #define | OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) |
| #define | HSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB3400UL) |
| #define | LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) |
| #define | PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) |
| #define | RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) |
| #define | ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) |
| #define | ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1300UL) |
| #define | DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) |
| #define | EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) |
| #define | GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) |
| #define | GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) |
| #define | GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) |
| #define | ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) |
| #define | ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) |
| #define | LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) |
| #define | LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) |
| #define | LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) |
| #define | LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) |
| #define | LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) |
| #define | GFXMMU_VIRTUAL_BUFFERS_BASE_NS (0x24000000UL) |
| #define | GFXMMU_VIRTUAL_BUFFER0_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS) |
| #define | GFXMMU_VIRTUAL_BUFFER1_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x400000UL) |
| #define | GFXMMU_VIRTUAL_BUFFER2_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x800000UL) |
| #define | GFXMMU_VIRTUAL_BUFFER3_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0xC00000UL) |
| #define | FLASH_BASE_S (0x0C000000UL) |
| #define | SRAM1_BASE_S (0x30000000UL) |
| #define | SRAM2_BASE_S (0x300C0000UL) |
| #define | SRAM3_BASE_S (0x300D0000UL) |
| #define | SRAM4_BASE_S (0x38000000UL) |
| #define | SRAM5_BASE_S (0x301A0000UL) |
| #define | PERIPH_BASE_S (0x50000000UL) |
| #define | SRAM6_BASE_S (0x30270000UL) |
| #define | APB1PERIPH_BASE_S PERIPH_BASE_S |
| #define | APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) |
| #define | AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) |
| #define | AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) |
| #define | APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) |
| #define | AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) |
| #define | TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) |
| #define | TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) |
| #define | TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) |
| #define | TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) |
| #define | TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) |
| #define | TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) |
| #define | WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) |
| #define | IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) |
| #define | SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) |
| #define | USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) |
| #define | USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) |
| #define | UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) |
| #define | UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) |
| #define | I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) |
| #define | I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) |
| #define | USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) |
| #define | I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) |
| #define | CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) |
| #define | LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) |
| #define | I2C5_BASE_S (APB1PERIPH_BASE_S + 0x9800UL) |
| #define | I2C6_BASE_S (APB1PERIPH_BASE_S + 0x9C00UL) |
| #define | FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) |
| #define | FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) |
| #define | SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) |
| #define | UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) |
| #define | TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) |
| #define | SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) |
| #define | TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) |
| #define | USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) |
| #define | TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) |
| #define | TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) |
| #define | TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) |
| #define | SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) |
| #define | SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) |
| #define | SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) |
| #define | SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) |
| #define | SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) |
| #define | SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) |
| #define | GFXTIM_BASE_S (APB2PERIPH_BASE_S + 0x6400UL) |
| #define | LTDC_BASE_S (APB2PERIPH_BASE_S + 0x6800UL) |
| #define | LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0084UL) |
| #define | LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0104UL) |
| #define | DSI_BASE_S (APB2PERIPH_BASE_S + 0x6C00UL) |
| #define | REFBIAS_BASE_S (DSI_BASE_S + 0x800UL) |
| #define | DPHY_BASE_S (DSI_BASE_S + 0xC00UL) |
| #define | SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) |
| #define | SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) |
| #define | LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) |
| #define | I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) |
| #define | LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) |
| #define | LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) |
| #define | LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) |
| #define | OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) |
| #define | OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) |
| #define | OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) |
| #define | COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) |
| #define | COMP1_BASE_S (COMP12_BASE_S) |
| #define | COMP2_BASE_S (COMP12_BASE_S + 0x04UL) |
| #define | VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) |
| #define | RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) |
| #define | TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) |
| #define | GPDMA1_BASE_S (AHB1PERIPH_BASE_S) |
| #define | GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) |
| #define | GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) |
| #define | GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) |
| #define | GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) |
| #define | GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) |
| #define | GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) |
| #define | GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) |
| #define | GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) |
| #define | GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) |
| #define | GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) |
| #define | GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) |
| #define | GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) |
| #define | GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) |
| #define | GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) |
| #define | GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) |
| #define | GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) |
| #define | CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) |
| #define | FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) |
| #define | FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) |
| #define | CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) |
| #define | TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) |
| #define | MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) |
| #define | MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) |
| #define | MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) |
| #define | MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) |
| #define | MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) |
| #define | MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) |
| #define | MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) |
| #define | RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) |
| #define | RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) |
| #define | RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) |
| #define | RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) |
| #define | RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) |
| #define | RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) |
| #define | RAMCFG_SRAM5_BASE_S (RAMCFG_BASE_S + 0x0140UL) |
| #define | RAMCFG_SRAM6_BASE_S (RAMCFG_BASE_S + 0x0180UL) |
| #define | JPEG_BASE_S (AHB1PERIPH_BASE_S + 0x0A00UL) |
| #define | DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) |
| #define | GFXMMU_BASE_S (AHB1PERIPH_BASE_S + 0x0C000UL) |
| #define | GPU2D_BASE_S (AHB1PERIPH_BASE_S + 0x0F000UL) |
| #define | ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) |
| #define | DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) |
| #define | DCACHE2_BASE_S (AHB1PERIPH_BASE_S + 0x11800UL) |
| #define | GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) |
| #define | GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) |
| #define | GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) |
| #define | GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) |
| #define | GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) |
| #define | GTZC_MPCBB5_BASE_S (AHB1PERIPH_BASE_S + 0x13800UL) |
| #define | GTZC_MPCBB6_BASE_S (AHB1PERIPH_BASE_S + 0x13C00UL) |
| #define | BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) |
| #define | GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) |
| #define | GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) |
| #define | GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) |
| #define | GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) |
| #define | GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) |
| #define | GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) |
| #define | GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) |
| #define | GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) |
| #define | GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) |
| #define | GPIOJ_BASE_S (AHB2PERIPH_BASE_S + 0x02400UL) |
| #define | ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) |
| #define | ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) |
| #define | ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) |
| #define | DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) |
| #define | PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) |
| #define | USB_OTG_HS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) |
| #define | AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) |
| #define | HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) |
| #define | HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) |
| #define | RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) |
| #define | SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) |
| #define | PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) |
| #define | PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) |
| #define | OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL) |
| #define | OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) |
| #define | OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) |
| #define | OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) |
| #define | OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) |
| #define | OTFDEC2_BASE_S (AHB2PERIPH_BASE_S + 0xA5400UL) |
| #define | OTFDEC2_REGION1_BASE_S (OTFDEC2_BASE_S + 0x20UL) |
| #define | OTFDEC2_REGION2_BASE_S (OTFDEC2_BASE_S + 0x50UL) |
| #define | OTFDEC2_REGION3_BASE_S (OTFDEC2_BASE_S + 0x80UL) |
| #define | OTFDEC2_REGION4_BASE_S (OTFDEC2_BASE_S + 0xB0UL) |
| #define | OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) |
| #define | SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) |
| #define | SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) |
| #define | DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) |
| #define | DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) |
| #define | DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) |
| #define | DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) |
| #define | FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) |
| #define | HSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB3400UL) |
| #define | FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) |
| #define | FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) |
| #define | FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) |
| #define | OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) |
| #define | OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) |
| #define | LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) |
| #define | PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) |
| #define | RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) |
| #define | ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) |
| #define | ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1300UL) |
| #define | DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) |
| #define | EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) |
| #define | GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) |
| #define | GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) |
| #define | GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) |
| #define | ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) |
| #define | ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) |
| #define | LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) |
| #define | LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) |
| #define | LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) |
| #define | LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) |
| #define | LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) |
| #define | GFXMMU_VIRTUAL_BUFFERS_BASE_S (0x34000000UL) |
| #define | GFXMMU_VIRTUAL_BUFFER0_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S) |
| #define | GFXMMU_VIRTUAL_BUFFER1_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x400000UL) |
| #define | GFXMMU_VIRTUAL_BUFFER2_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x800000UL) |
| #define | GFXMMU_VIRTUAL_BUFFER3_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0xC00000UL) |
| #define | DBGMCU_BASE (0xE0044000UL) |
| #define | PACKAGE_BASE (0x0BFA0500UL) |
| #define | UID_BASE (0x0BFA0700UL) |
| #define | FLASHSIZE_BASE (0x0BFA07A0UL) |
| #define | FLASH_OTP_BASE (0x0BFA0000UL) |
| #define | FLASH_OTP_SIZE (0x200U) |
| #define | USB_OTG_GLOBAL_BASE (0x0000UL) |
| #define | USB_OTG_DEVICE_BASE (0x0800UL) |
| #define | USB_OTG_IN_ENDPOINT_BASE (0x0900UL) |
| #define | USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) |
| #define | USB_OTG_EP_REG_SIZE (0x0020UL) |
| #define | USB_OTG_HOST_BASE (0x0400UL) |
| #define | USB_OTG_HOST_PORT_BASE (0x0440UL) |
| #define | USB_OTG_HOST_CHANNEL_BASE (0x0500UL) |
| #define | USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) |
| #define | USB_OTG_PCGCCTL_BASE (0x0E00UL) |
| #define | USB_OTG_FIFO_BASE (0x1000UL) |
| #define | USB_OTG_FIFO_SIZE (0x1000UL) |
| #define | RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) |
| #define | RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) |
| #define | RSSLIB_ERROR (0xF5F5F5F5UL) |
| #define | RSSLIB_SUCCESS (0xEAEAEAEAUL) |
| #define | RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START |
| #define | RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) |
| #define | RSSLIB_HDP_AREA_Pos (0U) |
| #define | RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) |
| #define | RSSLIB_HDP_AREA1_Pos (0U) |
| #define | RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) |
| #define | RSSLIB_HDP_AREA2_Pos (1U) |
| #define | RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) |
| #define | TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) |
| #define | TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) |
| #define | TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) |
| #define | TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) |
| #define | TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) |
| #define | TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) |
| #define | WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) |
| #define | IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) |
| #define | SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) |
| #define | USART2_NS ((USART_TypeDef *) USART2_BASE_NS) |
| #define | USART3_NS ((USART_TypeDef *) USART3_BASE_NS) |
| #define | UART4_NS ((USART_TypeDef *) UART4_BASE_NS) |
| #define | UART5_NS ((USART_TypeDef *) UART5_BASE_NS) |
| #define | I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) |
| #define | I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) |
| #define | CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) |
| #define | USART6_NS ((USART_TypeDef *) USART6_BASE_NS) |
| #define | I2C5_NS ((I2C_TypeDef *) I2C5_BASE_NS) |
| #define | I2C6_NS ((I2C_TypeDef *) I2C6_BASE_NS) |
| #define | I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) |
| #define | LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) |
| #define | FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) |
| #define | FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) |
| #define | UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) |
| #define | TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) |
| #define | SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) |
| #define | TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) |
| #define | USART1_NS ((USART_TypeDef *) USART1_BASE_NS) |
| #define | TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) |
| #define | TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) |
| #define | TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) |
| #define | SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) |
| #define | SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) |
| #define | SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) |
| #define | SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) |
| #define | SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) |
| #define | SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) |
| #define | LTDC_NS ((LTDC_TypeDef *) LTDC_BASE_NS) |
| #define | LTDC_Layer1_NS ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_NS) |
| #define | LTDC_Layer2_NS ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_NS) |
| #define | DSI_NS ((DSI_TypeDef *) DSI_BASE_NS) |
| #define | REFBIAS_NS ((REFBIAS_TypeDef *) REFBIAS_BASE_NS) |
| #define | DPHY_NS ((DPHY_TypeDef *) DPHY_BASE_NS) |
| #define | GFXTIM_NS ((GFXTIM_TypeDef *) GFXTIM_BASE_NS) |
| #define | SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) |
| #define | SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) |
| #define | LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) |
| #define | I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) |
| #define | LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) |
| #define | LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) |
| #define | LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) |
| #define | OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) |
| #define | OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) |
| #define | OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) |
| #define | OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) |
| #define | COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) |
| #define | COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) |
| #define | COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) |
| #define | COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) |
| #define | VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) |
| #define | RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) |
| #define | TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) |
| #define | GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) |
| #define | GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) |
| #define | GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) |
| #define | GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) |
| #define | GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) |
| #define | GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) |
| #define | GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) |
| #define | GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) |
| #define | GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) |
| #define | GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) |
| #define | GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) |
| #define | GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) |
| #define | GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) |
| #define | GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) |
| #define | GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) |
| #define | GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) |
| #define | GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) |
| #define | CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) |
| #define | FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) |
| #define | FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) |
| #define | CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) |
| #define | TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) |
| #define | MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) |
| #define | MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) |
| #define | MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) |
| #define | MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) |
| #define | MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) |
| #define | MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) |
| #define | MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) |
| #define | RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) |
| #define | RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) |
| #define | RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) |
| #define | RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) |
| #define | RAMCFG_SRAM5_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_NS) |
| #define | RAMCFG_SRAM6_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_NS) |
| #define | JPEG_NS ((JPEG_TypeDef *) JPEG_BASE_NS) |
| #define | RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) |
| #define | DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) |
| #define | ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) |
| #define | DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) |
| #define | DCACHE2_NS ((DCACHE_TypeDef *) DCACHE2_BASE_NS) |
| #define | GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) |
| #define | GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) |
| #define | GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) |
| #define | GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) |
| #define | GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) |
| #define | GTZC_MPCBB5_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_NS) |
| #define | GTZC_MPCBB6_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_NS) |
| #define | GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS) |
| #define | GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) |
| #define | GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) |
| #define | GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) |
| #define | GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) |
| #define | GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) |
| #define | GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) |
| #define | GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) |
| #define | GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) |
| #define | GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) |
| #define | GPIOJ_NS ((GPIO_TypeDef *) GPIOJ_BASE_NS) |
| #define | ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) |
| #define | ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) |
| #define | ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) |
| #define | DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) |
| #define | PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) |
| #define | USB_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS) |
| #define | AES_NS ((AES_TypeDef *) AES_BASE_NS) |
| #define | HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) |
| #define | HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) |
| #define | RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) |
| #define | SAES_NS ((AES_TypeDef *) SAES_BASE_NS) |
| #define | PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) |
| #define | OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) |
| #define | OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) |
| #define | OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) |
| #define | OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) |
| #define | OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) |
| #define | OTFDEC2_NS ((OTFDEC_TypeDef *) OTFDEC2_BASE_NS) |
| #define | OTFDEC2_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_NS) |
| #define | OTFDEC2_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_NS) |
| #define | OTFDEC2_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_NS) |
| #define | OTFDEC2_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_NS) |
| #define | SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) |
| #define | SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) |
| #define | DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) |
| #define | DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) |
| #define | DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) |
| #define | DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) |
| #define | FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) |
| #define | FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) |
| #define | FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) |
| #define | OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) |
| #define | OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) |
| #define | OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) |
| #define | HSPI1_NS ((HSPI_TypeDef *) HSPI1_R_BASE_NS) |
| #define | LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) |
| #define | PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) |
| #define | RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) |
| #define | ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) |
| #define | ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) |
| #define | DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) |
| #define | EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) |
| #define | GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) |
| #define | GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) |
| #define | GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) |
| #define | ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) |
| #define | ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) |
| #define | LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) |
| #define | LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) |
| #define | LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) |
| #define | LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) |
| #define | LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) |
| #define | TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) |
| #define | TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) |
| #define | TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) |
| #define | TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) |
| #define | TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) |
| #define | TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) |
| #define | WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) |
| #define | IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) |
| #define | SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) |
| #define | USART2_S ((USART_TypeDef *) USART2_BASE_S) |
| #define | USART3_S ((USART_TypeDef *) USART3_BASE_S) |
| #define | UART4_S ((USART_TypeDef *) UART4_BASE_S) |
| #define | UART5_S ((USART_TypeDef *) UART5_BASE_S) |
| #define | I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) |
| #define | I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) |
| #define | CRS_S ((CRS_TypeDef *) CRS_BASE_S) |
| #define | USART6_S ((USART_TypeDef *) USART6_BASE_S) |
| #define | I2C5_S ((I2C_TypeDef *) I2C5_BASE_S) |
| #define | I2C6_S ((I2C_TypeDef *) I2C6_BASE_S) |
| #define | I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) |
| #define | LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) |
| #define | FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) |
| #define | FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) |
| #define | UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) |
| #define | TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) |
| #define | SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) |
| #define | TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) |
| #define | USART1_S ((USART_TypeDef *) USART1_BASE_S) |
| #define | TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) |
| #define | TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) |
| #define | TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) |
| #define | SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) |
| #define | SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) |
| #define | SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) |
| #define | SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) |
| #define | SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) |
| #define | SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) |
| #define | LTDC_S ((LTDC_TypeDef *) LTDC_BASE_S) |
| #define | LTDC_Layer1_S ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_S) |
| #define | LTDC_Layer2_S ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_S) |
| #define | DSI_S ((DSI_TypeDef *) DSI_BASE_S) |
| #define | REFBIAS_S ((REFBIAS_TypeDef *) REFBIAS_BASE_S) |
| #define | DPHY_S ((DPHY_TypeDef *) DPHY_BASE_S) |
| #define | GFXTIM_S ((GFXTIM_TypeDef *) GFXTIM_BASE_S) |
| #define | SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) |
| #define | SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) |
| #define | LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) |
| #define | I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) |
| #define | LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) |
| #define | LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) |
| #define | LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) |
| #define | OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) |
| #define | OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) |
| #define | OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) |
| #define | OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) |
| #define | COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) |
| #define | COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) |
| #define | COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) |
| #define | COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) |
| #define | VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) |
| #define | RTC_S ((RTC_TypeDef *) RTC_BASE_S) |
| #define | TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) |
| #define | GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) |
| #define | GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) |
| #define | GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) |
| #define | GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) |
| #define | GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) |
| #define | GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) |
| #define | GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) |
| #define | GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) |
| #define | GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) |
| #define | GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) |
| #define | GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) |
| #define | GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) |
| #define | GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) |
| #define | GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) |
| #define | GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) |
| #define | GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) |
| #define | GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) |
| #define | CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) |
| #define | FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) |
| #define | FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) |
| #define | CRC_S ((CRC_TypeDef *) CRC_BASE_S) |
| #define | TSC_S ((TSC_TypeDef *) TSC_BASE_S) |
| #define | MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) |
| #define | MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) |
| #define | MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) |
| #define | MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) |
| #define | MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) |
| #define | MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) |
| #define | MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) |
| #define | RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) |
| #define | RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) |
| #define | RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) |
| #define | RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) |
| #define | RAMCFG_SRAM5_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_S) |
| #define | RAMCFG_SRAM6_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_S) |
| #define | JPEG_S ((JPEG_TypeDef *) JPEG_BASE_S) |
| #define | RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) |
| #define | DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) |
| #define | ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) |
| #define | DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) |
| #define | DCACHE2_S ((DCACHE_TypeDef *) DCACHE2_BASE_S) |
| #define | GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) |
| #define | GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) |
| #define | GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) |
| #define | GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) |
| #define | GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) |
| #define | GTZC_MPCBB5_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_S) |
| #define | GTZC_MPCBB6_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_S) |
| #define | GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S) |
| #define | GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) |
| #define | GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) |
| #define | GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) |
| #define | GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) |
| #define | GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) |
| #define | GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) |
| #define | GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) |
| #define | GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) |
| #define | GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) |
| #define | GPIOJ_S ((GPIO_TypeDef *) GPIOJ_BASE_S) |
| #define | ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) |
| #define | ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) |
| #define | ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) |
| #define | DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) |
| #define | PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) |
| #define | USB_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S) |
| #define | AES_S ((AES_TypeDef *) AES_BASE_S) |
| #define | HASH_S ((HASH_TypeDef *) HASH_BASE_S) |
| #define | HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) |
| #define | RNG_S ((RNG_TypeDef *) RNG_BASE_S) |
| #define | SAES_S ((AES_TypeDef *) SAES_BASE_S) |
| #define | PKA_S ((PKA_TypeDef *) PKA_BASE_S) |
| #define | OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) |
| #define | OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) |
| #define | OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) |
| #define | OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) |
| #define | OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) |
| #define | OTFDEC2_S ((OTFDEC_TypeDef *) OTFDEC2_BASE_S) |
| #define | OTFDEC2_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_S) |
| #define | OTFDEC2_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_S) |
| #define | OTFDEC2_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_S) |
| #define | OTFDEC2_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_S) |
| #define | SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) |
| #define | SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) |
| #define | DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) |
| #define | DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) |
| #define | DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) |
| #define | DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) |
| #define | FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) |
| #define | FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) |
| #define | FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) |
| #define | OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) |
| #define | OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) |
| #define | OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) |
| #define | HSPI1_S ((HSPI_TypeDef *) HSPI1_R_BASE_S) |
| #define | LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) |
| #define | PWR_S ((PWR_TypeDef *) PWR_BASE_S) |
| #define | RCC_S ((RCC_TypeDef *) RCC_BASE_S) |
| #define | ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) |
| #define | ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) |
| #define | DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) |
| #define | EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) |
| #define | GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) |
| #define | GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) |
| #define | GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) |
| #define | ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) |
| #define | ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) |
| #define | LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) |
| #define | LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) |
| #define | LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) |
| #define | LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) |
| #define | LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) |
| #define | DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
| #define | FLASH_BASE FLASH_BASE_NS |
| #define | SRAM1_BASE SRAM1_BASE_NS |
| #define | SRAM2_BASE SRAM2_BASE_NS |
| #define | SRAM3_BASE SRAM3_BASE_NS |
| #define | SRAM4_BASE SRAM4_BASE_NS |
| #define | SRAM5_BASE SRAM5_BASE_NS |
| #define | BKPSRAM_BASE BKPSRAM_BASE_NS |
| #define | SRAM6_BASE SRAM6_BASE_NS |
| #define | PERIPH_BASE PERIPH_BASE_NS |
| #define | APB1PERIPH_BASE APB1PERIPH_BASE_NS |
| #define | APB2PERIPH_BASE APB2PERIPH_BASE_NS |
| #define | AHB1PERIPH_BASE AHB1PERIPH_BASE_NS |
| #define | AHB2PERIPH_BASE AHB2PERIPH_BASE_NS |
| #define | CORDIC CORDIC_NS |
| #define | CORDIC_BASE CORDIC_BASE_NS |
| #define | RCC RCC_NS |
| #define | RCC_BASE RCC_BASE_NS |
| #define | DMA2D DMA2D_NS |
| #define | DMA2D_BASE DMA2D_BASE_NS |
| #define | DCMI DCMI_NS |
| #define | DCMI_BASE DCMI_BASE_NS |
| #define | PSSI PSSI_NS |
| #define | PSSI_BASE PSSI_BASE_NS |
| #define | FLASH FLASH_NS |
| #define | FLASH_R_BASE FLASH_R_BASE_NS |
| #define | FMAC FMAC_NS |
| #define | FMAC_BASE FMAC_BASE_NS |
| #define | GPDMA1 GPDMA1_NS |
| #define | GPDMA1_BASE GPDMA1_BASE_NS |
| #define | GPDMA1_Channel0 GPDMA1_Channel0_NS |
| #define | GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS |
| #define | GPDMA1_Channel1 GPDMA1_Channel1_NS |
| #define | GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS |
| #define | GPDMA1_Channel2 GPDMA1_Channel2_NS |
| #define | GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS |
| #define | GPDMA1_Channel3 GPDMA1_Channel3_NS |
| #define | GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS |
| #define | GPDMA1_Channel4 GPDMA1_Channel4_NS |
| #define | GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS |
| #define | GPDMA1_Channel5 GPDMA1_Channel5_NS |
| #define | GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS |
| #define | GPDMA1_Channel6 GPDMA1_Channel6_NS |
| #define | GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS |
| #define | GPDMA1_Channel7 GPDMA1_Channel7_NS |
| #define | GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS |
| #define | GPDMA1_Channel8 GPDMA1_Channel8_NS |
| #define | GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS |
| #define | GPDMA1_Channel9 GPDMA1_Channel9_NS |
| #define | GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS |
| #define | GPDMA1_Channel10 GPDMA1_Channel10_NS |
| #define | GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS |
| #define | GPDMA1_Channel11 GPDMA1_Channel11_NS |
| #define | GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS |
| #define | GPDMA1_Channel12 GPDMA1_Channel12_NS |
| #define | GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS |
| #define | GPDMA1_Channel13 GPDMA1_Channel13_NS |
| #define | GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS |
| #define | GPDMA1_Channel14 GPDMA1_Channel14_NS |
| #define | GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS |
| #define | GPDMA1_Channel15 GPDMA1_Channel15_NS |
| #define | GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS |
| #define | LPDMA1 LPDMA1_NS |
| #define | LPDMA1_BASE LPDMA1_BASE_NS |
| #define | LPDMA1_Channel0 LPDMA1_Channel0_NS |
| #define | LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS |
| #define | LPDMA1_Channel1 LPDMA1_Channel1_NS |
| #define | LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS |
| #define | LPDMA1_Channel2 LPDMA1_Channel2_NS |
| #define | LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS |
| #define | LPDMA1_Channel3 LPDMA1_Channel3_NS |
| #define | LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS |
| #define | GPIOA GPIOA_NS |
| #define | GPIOA_BASE GPIOA_BASE_NS |
| #define | GPIOB GPIOB_NS |
| #define | GPIOB_BASE GPIOB_BASE_NS |
| #define | GPIOC GPIOC_NS |
| #define | GPIOC_BASE GPIOC_BASE_NS |
| #define | GPIOD GPIOD_NS |
| #define | GPIOD_BASE GPIOD_BASE_NS |
| #define | GPIOE GPIOE_NS |
| #define | GPIOE_BASE GPIOE_BASE_NS |
| #define | GPIOF GPIOF_NS |
| #define | GPIOF_BASE GPIOF_BASE_NS |
| #define | GPIOG GPIOG_NS |
| #define | GPIOG_BASE GPIOG_BASE_NS |
| #define | GPIOH GPIOH_NS |
| #define | GPIOH_BASE GPIOH_BASE_NS |
| #define | GPIOI GPIOI_NS |
| #define | GPIOI_BASE GPIOI_BASE_NS |
| #define | GPIOJ GPIOJ_NS |
| #define | GPIOJ_BASE GPIOJ_BASE_NS |
| #define | LPGPIO1 LPGPIO1_NS |
| #define | LPGPIO1_BASE LPGPIO1_BASE_NS |
| #define | PWR PWR_NS |
| #define | PWR_BASE PWR_BASE_NS |
| #define | RAMCFG_SRAM1 RAMCFG_SRAM1_NS |
| #define | RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS |
| #define | RAMCFG_SRAM2 RAMCFG_SRAM2_NS |
| #define | RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS |
| #define | RAMCFG_SRAM3 RAMCFG_SRAM3_NS |
| #define | RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS |
| #define | RAMCFG_SRAM4 RAMCFG_SRAM4_NS |
| #define | RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS |
| #define | RAMCFG_SRAM5 RAMCFG_SRAM5_NS |
| #define | RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_NS |
| #define | RAMCFG_BKPRAM RAMCFG_BKPRAM_NS |
| #define | RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS |
| #define | RAMCFG_SRAM6 RAMCFG_SRAM6_NS |
| #define | RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_NS |
| #define | EXTI EXTI_NS |
| #define | EXTI_BASE EXTI_BASE_NS |
| #define | ICACHE ICACHE_NS |
| #define | ICACHE_BASE ICACHE_BASE_NS |
| #define | DCACHE1 DCACHE1_NS |
| #define | DCACHE1_BASE DCACHE1_BASE_NS |
| #define | DCACHE2 DCACHE2_NS |
| #define | DCACHE2_BASE DCACHE2_BASE_NS |
| #define | GTZC_TZSC1 GTZC_TZSC1_NS |
| #define | GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS |
| #define | GTZC_TZSC2 GTZC_TZSC2_NS |
| #define | GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS |
| #define | GTZC_TZIC1 GTZC_TZIC1_NS |
| #define | GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS |
| #define | GTZC_TZIC2 GTZC_TZIC2_NS |
| #define | GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS |
| #define | GTZC_MPCBB1 GTZC_MPCBB1_NS |
| #define | GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS |
| #define | GTZC_MPCBB2 GTZC_MPCBB2_NS |
| #define | GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS |
| #define | GTZC_MPCBB3 GTZC_MPCBB3_NS |
| #define | GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS |
| #define | GTZC_MPCBB4 GTZC_MPCBB4_NS |
| #define | GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS |
| #define | GTZC_MPCBB5 GTZC_MPCBB5_NS |
| #define | GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_NS |
| #define | GTZC_MPCBB6 GTZC_MPCBB6_NS |
| #define | GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_NS |
| #define | RTC RTC_NS |
| #define | RTC_BASE RTC_BASE_NS |
| #define | TAMP TAMP_NS |
| #define | TAMP_BASE TAMP_BASE_NS |
| #define | TIM1 TIM1_NS |
| #define | TIM1_BASE TIM1_BASE_NS |
| #define | TIM2 TIM2_NS |
| #define | TIM2_BASE TIM2_BASE_NS |
| #define | TIM3 TIM3_NS |
| #define | TIM3_BASE TIM3_BASE_NS |
| #define | TIM4 TIM4_NS |
| #define | TIM4_BASE TIM4_BASE_NS |
| #define | TIM5 TIM5_NS |
| #define | TIM5_BASE TIM5_BASE_NS |
| #define | TIM6 TIM6_NS |
| #define | TIM6_BASE TIM6_BASE_NS |
| #define | TIM7 TIM7_NS |
| #define | TIM7_BASE TIM7_BASE_NS |
| #define | TIM8 TIM8_NS |
| #define | TIM8_BASE TIM8_BASE_NS |
| #define | TIM15 TIM15_NS |
| #define | TIM15_BASE TIM15_BASE_NS |
| #define | TIM16 TIM16_NS |
| #define | TIM16_BASE TIM16_BASE_NS |
| #define | TIM17 TIM17_NS |
| #define | TIM17_BASE TIM17_BASE_NS |
| #define | WWDG WWDG_NS |
| #define | WWDG_BASE WWDG_BASE_NS |
| #define | IWDG IWDG_NS |
| #define | IWDG_BASE IWDG_BASE_NS |
| #define | SPI1 SPI1_NS |
| #define | SPI1_BASE SPI1_BASE_NS |
| #define | SPI2 SPI2_NS |
| #define | SPI2_BASE SPI2_BASE_NS |
| #define | SPI3 SPI3_NS |
| #define | SPI3_BASE SPI3_BASE_NS |
| #define | USART1 USART1_NS |
| #define | USART1_BASE USART1_BASE_NS |
| #define | USART2 USART2_NS |
| #define | USART2_BASE USART2_BASE_NS |
| #define | USART3 USART3_NS |
| #define | USART3_BASE USART3_BASE_NS |
| #define | UART4 UART4_NS |
| #define | UART4_BASE UART4_BASE_NS |
| #define | UART5 UART5_NS |
| #define | UART5_BASE UART5_BASE_NS |
| #define | USART6 USART6_NS |
| #define | USART6_BASE USART6_BASE_NS |
| #define | I2C1 I2C1_NS |
| #define | I2C1_BASE I2C1_BASE_NS |
| #define | I2C2 I2C2_NS |
| #define | I2C2_BASE I2C2_BASE_NS |
| #define | I2C3 I2C3_NS |
| #define | I2C3_BASE I2C3_BASE_NS |
| #define | I2C4 I2C4_NS |
| #define | I2C4_BASE I2C4_BASE_NS |
| #define | I2C5 I2C5_NS |
| #define | I2C5_BASE I2C5_BASE_NS |
| #define | I2C6 I2C6_NS |
| #define | I2C6_BASE I2C6_BASE_NS |
| #define | CRS CRS_NS |
| #define | CRS_BASE CRS_BASE_NS |
| #define | FDCAN1 FDCAN1_NS |
| #define | FDCAN1_BASE FDCAN1_BASE_NS |
| #define | FDCAN_CONFIG FDCAN_CONFIG_NS |
| #define | FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS |
| #define | SRAMCAN_BASE SRAMCAN_BASE_NS |
| #define | DAC1 DAC1_NS |
| #define | DAC1_BASE DAC1_BASE_NS |
| #define | OPAMP OPAMP_NS |
| #define | OPAMP_BASE OPAMP_BASE_NS |
| #define | OPAMP1 OPAMP1_NS |
| #define | OPAMP1_BASE OPAMP1_BASE_NS |
| #define | OPAMP2 OPAMP2_NS |
| #define | OPAMP2_BASE OPAMP2_BASE_NS |
| #define | OPAMP12_COMMON OPAMP12_COMMON_NS |
| #define | OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS |
| #define | LPTIM1 LPTIM1_NS |
| #define | LPTIM1_BASE LPTIM1_BASE_NS |
| #define | LPTIM2 LPTIM2_NS |
| #define | LPTIM2_BASE LPTIM2_BASE_NS |
| #define | LPTIM3 LPTIM3_NS |
| #define | LPTIM3_BASE LPTIM3_BASE_NS |
| #define | LPTIM4 LPTIM4_NS |
| #define | LPTIM4_BASE LPTIM4_BASE_NS |
| #define | LPUART1 LPUART1_NS |
| #define | LPUART1_BASE LPUART1_BASE_NS |
| #define | UCPD1 UCPD1_NS |
| #define | UCPD1_BASE UCPD1_BASE_NS |
| #define | SYSCFG SYSCFG_NS |
| #define | SYSCFG_BASE SYSCFG_BASE_NS |
| #define | VREFBUF VREFBUF_NS |
| #define | VREFBUF_BASE VREFBUF_BASE_NS |
| #define | COMP12 COMP12_NS |
| #define | COMP12_BASE COMP12_BASE_NS |
| #define | COMP1 COMP1_NS |
| #define | COMP1_BASE COMP1_BASE_NS |
| #define | COMP2 COMP2_NS |
| #define | COMP2_BASE COMP2_BASE_NS |
| #define | COMP12_COMMON COMP12_COMMON_NS |
| #define | COMP12_COMMON_BASE COMP1_BASE_NS |
| #define | SAI1 SAI1_NS |
| #define | SAI1_BASE SAI1_BASE_NS |
| #define | SAI1_Block_A SAI1_Block_A_NS |
| #define | SAI1_Block_A_BASE SAI1_Block_A_BASE_NS |
| #define | SAI1_Block_B SAI1_Block_B_NS |
| #define | SAI1_Block_B_BASE SAI1_Block_B_BASE_NS |
| #define | SAI2 SAI2_NS |
| #define | SAI2_BASE SAI2_BASE_NS |
| #define | SAI2_Block_A SAI2_Block_A_NS |
| #define | SAI2_Block_A_BASE SAI2_Block_A_BASE_NS |
| #define | SAI2_Block_B SAI2_Block_B_NS |
| #define | SAI2_Block_B_BASE SAI2_Block_B_BASE_NS |
| #define | CRC CRC_NS |
| #define | CRC_BASE CRC_BASE_NS |
| #define | TSC TSC_NS |
| #define | TSC_BASE TSC_BASE_NS |
| #define | ADC1 ADC1_NS |
| #define | ADC1_BASE ADC1_BASE_NS |
| #define | ADC2 ADC2_NS |
| #define | ADC2_BASE ADC2_BASE_NS |
| #define | ADC12_COMMON ADC12_COMMON_NS |
| #define | ADC12_COMMON_BASE ADC12_COMMON_BASE_NS |
| #define | ADC4 ADC4_NS |
| #define | ADC4_BASE ADC4_BASE_NS |
| #define | ADC4_COMMON ADC4_COMMON_NS |
| #define | ADC4_COMMON_BASE ADC4_COMMON_BASE_NS |
| #define | HASH HASH_NS |
| #define | HASH_BASE HASH_BASE_NS |
| #define | HASH_DIGEST HASH_DIGEST_NS |
| #define | HASH_DIGEST_BASE HASH_DIGEST_BASE_NS |
| #define | AES AES_NS |
| #define | AES_BASE AES_BASE_NS |
| #define | RNG RNG_NS |
| #define | RNG_BASE RNG_BASE_NS |
| #define | SAES SAES_NS |
| #define | SAES_BASE SAES_BASE_NS |
| #define | PKA PKA_NS |
| #define | PKA_BASE PKA_BASE_NS |
| #define | PKA_RAM_BASE PKA_RAM_BASE_NS |
| #define | OTFDEC1 OTFDEC1_NS |
| #define | OTFDEC1_BASE OTFDEC1_BASE_NS |
| #define | OTFDEC1_REGION1 OTFDEC1_REGION1_NS |
| #define | OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS |
| #define | OTFDEC1_REGION2 OTFDEC1_REGION2_NS |
| #define | OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS |
| #define | OTFDEC1_REGION3 OTFDEC1_REGION3_NS |
| #define | OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS |
| #define | OTFDEC1_REGION4 OTFDEC1_REGION4_NS |
| #define | OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS |
| #define | OTFDEC2 OTFDEC2_NS |
| #define | OTFDEC2_BASE OTFDEC2_BASE_NS |
| #define | OTFDEC2_REGION1 OTFDEC2_REGION1_NS |
| #define | OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_NS |
| #define | OTFDEC2_REGION2 OTFDEC2_REGION2_NS |
| #define | OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_NS |
| #define | OTFDEC2_REGION3 OTFDEC2_REGION3_NS |
| #define | OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_NS |
| #define | OTFDEC2_REGION4 OTFDEC2_REGION4_NS |
| #define | OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_NS |
| #define | SDMMC1 SDMMC1_NS |
| #define | SDMMC1_BASE SDMMC1_BASE_NS |
| #define | SDMMC2 SDMMC2_NS |
| #define | SDMMC2_BASE SDMMC2_BASE_NS |
| #define | FMC_Bank1_R FMC_Bank1_R_NS |
| #define | FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS |
| #define | FMC_Bank1E_R FMC_Bank1E_R_NS |
| #define | FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS |
| #define | FMC_Bank3_R FMC_Bank3_R_NS |
| #define | FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS |
| #define | OCTOSPI1 OCTOSPI1_NS |
| #define | OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS |
| #define | OCTOSPI2 OCTOSPI2_NS |
| #define | OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS |
| #define | OCTOSPIM OCTOSPIM_NS |
| #define | OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS |
| #define | DLYB_SDMMC1 DLYB_SDMMC1_NS |
| #define | DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS |
| #define | DLYB_SDMMC2 DLYB_SDMMC2_NS |
| #define | DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS |
| #define | DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS |
| #define | DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS |
| #define | DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS |
| #define | DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS |
| #define | HSPI1 HSPI1_NS |
| #define | HSPI1_R_BASE HSPI1_R_BASE_NS |
| #define | USB_OTG_HS USB_OTG_HS_NS |
| #define | USB_OTG_HS_BASE USB_OTG_HS_BASE_NS |
| #define | MDF1 MDF1_NS |
| #define | MDF1_BASE MDF1_BASE_NS |
| #define | MDF1_Filter0 MDF1_Filter0_NS |
| #define | MDF1_Filter0_BASE MDF1_Filter0_BASE_NS |
| #define | MDF1_Filter1 MDF1_Filter1_NS |
| #define | MDF1_Filter1_BASE MDF1_Filter1_BASE_NS |
| #define | MDF1_Filter2 MDF1_Filter2_NS |
| #define | MDF1_Filter2_BASE MDF1_Filter2_BASE_NS |
| #define | MDF1_Filter3 MDF1_Filter3_NS |
| #define | MDF1_Filter3_BASE MDF1_Filter3_BASE_NS |
| #define | MDF1_Filter4 MDF1_Filter4_NS |
| #define | MDF1_Filter4_BASE MDF1_Filter4_BASE_NS |
| #define | MDF1_Filter5 MDF1_Filter5_NS |
| #define | MDF1_Filter5_BASE MDF1_Filter5_BASE_NS |
| #define | ADF1 ADF1_NS |
| #define | ADF1_BASE ADF1_BASE_NS |
| #define | ADF1_Filter0 ADF1_Filter0_NS |
| #define | ADF1_Filter0_BASE ADF1_Filter0_BASE_NS |
| #define | GFXMMU GFXMMU_NS |
| #define | GFXMMU_BASE GFXMMU_BASE_NS |
| #define | GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_NS |
| #define | GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS |
| #define | GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS |
| #define | GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS |
| #define | GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS |
| #define | GPU2D GPU2D_BASE_NS |
| #define | LTDC LTDC_NS |
| #define | LTDC_BASE LTDC_BASE_NS |
| #define | LTDC_Layer1 LTDC_Layer1_NS |
| #define | LTDC_Layer1_BASE LTDC_Layer1_BASE_NS |
| #define | LTDC_Layer2 LTDC_Layer2_NS |
| #define | LTDC_Layer2_BASE LTDC_Layer2_BASE_NS |
| #define | DSI DSI_NS |
| #define | DSI_BASE DSI_BASE_NS |
| #define | REFBIAS REFBIAS_NS |
| #define | REFBIAS_BASE REFBIAS_BASE_NS |
| #define | DPHY DPHY_NS |
| #define | DPHY_BASE DPHY_BASE_NS |
| #define | JPEG JPEG_NS |
| #define | JPEG_BASE JPEG_BASE_NS |
| #define | GFXTIM GFXTIM_NS |
| #define | GFXTIM_BASE GFXTIM_BASE_NS |
| #define | LSI_STARTUP_TIME 260U |
| #define | ADC_VER_V5_X |
| #define | ADC_MULTIMODE_SUPPORT |
| #define | ADC_ISR_ADRDY_Pos (0U) |
| #define | ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) |
| #define | ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk |
| #define | ADC_ISR_EOSMP_Pos (1U) |
| #define | ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) |
| #define | ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk |
| #define | ADC_ISR_EOC_Pos (2U) |
| #define | ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) |
| #define | ADC_ISR_EOC ADC_ISR_EOC_Msk |
| #define | ADC_ISR_EOS_Pos (3U) |
| #define | ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) |
| #define | ADC_ISR_EOS ADC_ISR_EOS_Msk |
| #define | ADC_ISR_OVR_Pos (4U) |
| #define | ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) |
| #define | ADC_ISR_OVR ADC_ISR_OVR_Msk |
| #define | ADC_ISR_JEOC_Pos (5U) |
| #define | ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) |
| #define | ADC_ISR_JEOC ADC_ISR_JEOC_Msk |
| #define | ADC_ISR_JEOS_Pos (6U) |
| #define | ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) |
| #define | ADC_ISR_JEOS ADC_ISR_JEOS_Msk |
| #define | ADC_ISR_AWD1_Pos (7U) |
| #define | ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) |
| #define | ADC_ISR_AWD1 ADC_ISR_AWD1_Msk |
| #define | ADC_ISR_AWD2_Pos (8U) |
| #define | ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) |
| #define | ADC_ISR_AWD2 ADC_ISR_AWD2_Msk |
| #define | ADC_ISR_AWD3_Pos (9U) |
| #define | ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) |
| #define | ADC_ISR_AWD3 ADC_ISR_AWD3_Msk |
| #define | ADC_ISR_JQOVF_Pos (10U) |
| #define | ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) |
| #define | ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk |
| #define | ADC_ISR_EOCAL_Pos (11U) |
| #define | ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) |
| #define | ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk |
| #define | ADC_ISR_LDORDY_Pos (12U) |
| #define | ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) |
| #define | ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk |
| #define | ADC_IER_ADRDYIE_Pos (0U) |
| #define | ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) |
| #define | ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk |
| #define | ADC_IER_EOSMPIE_Pos (1U) |
| #define | ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) |
| #define | ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk |
| #define | ADC_IER_EOCIE_Pos (2U) |
| #define | ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) |
| #define | ADC_IER_EOCIE ADC_IER_EOCIE_Msk |
| #define | ADC_IER_EOSIE_Pos (3U) |
| #define | ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) |
| #define | ADC_IER_EOSIE ADC_IER_EOSIE_Msk |
| #define | ADC_IER_OVRIE_Pos (4U) |
| #define | ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) |
| #define | ADC_IER_OVRIE ADC_IER_OVRIE_Msk |
| #define | ADC_IER_JEOCIE_Pos (5U) |
| #define | ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) |
| #define | ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk |
| #define | ADC_IER_JEOSIE_Pos (6U) |
| #define | ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) |
| #define | ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk |
| #define | ADC_IER_AWD1IE_Pos (7U) |
| #define | ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) |
| #define | ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk |
| #define | ADC_IER_AWD2IE_Pos (8U) |
| #define | ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) |
| #define | ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk |
| #define | ADC_IER_AWD3IE_Pos (9U) |
| #define | ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) |
| #define | ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk |
| #define | ADC_IER_JQOVFIE_Pos (10U) |
| #define | ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) |
| #define | ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk |
| #define | ADC_IER_EOCALIE_Pos (11U) |
| #define | ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) |
| #define | ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk |
| #define | ADC_IER_LDORDYIE_Pos (12U) |
| #define | ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) |
| #define | ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk |
| #define | ADC_CR_ADEN_Pos (0U) |
| #define | ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) |
| #define | ADC_CR_ADEN ADC_CR_ADEN_Msk |
| #define | ADC_CR_ADDIS_Pos (1U) |
| #define | ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) |
| #define | ADC_CR_ADDIS ADC_CR_ADDIS_Msk |
| #define | ADC_CR_ADSTART_Pos (2U) |
| #define | ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) |
| #define | ADC_CR_ADSTART ADC_CR_ADSTART_Msk |
| #define | ADC_CR_JADSTART_Pos (3U) |
| #define | ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) |
| #define | ADC_CR_JADSTART ADC_CR_JADSTART_Msk |
| #define | ADC_CR_ADSTP_Pos (4U) |
| #define | ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) |
| #define | ADC_CR_ADSTP ADC_CR_ADSTP_Msk |
| #define | ADC_CR_JADSTP_Pos (5U) |
| #define | ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) |
| #define | ADC_CR_JADSTP ADC_CR_JADSTP_Msk |
| #define | ADC_CR_ADCALLIN_Pos (16U) |
| #define | ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) |
| #define | ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk |
| #define | ADC_CR_CALINDEX_Pos (24U) |
| #define | ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) |
| #define | ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk |
| #define | ADC_CR_CALINDEX0_Pos (24U) |
| #define | ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) |
| #define | ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk |
| #define | ADC_CR_CALINDEX1_Pos (25U) |
| #define | ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) |
| #define | ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk |
| #define | ADC_CR_CALINDEX2_Pos (26U) |
| #define | ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) |
| #define | ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk |
| #define | ADC_CR_CALINDEX3_Pos (27U) |
| #define | ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) |
| #define | ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk |
| #define | ADC_CR_ADVREGEN_Pos (28U) |
| #define | ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) |
| #define | ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk |
| #define | ADC_CR_DEEPPWD_Pos (29U) |
| #define | ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) |
| #define | ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk |
| #define | ADC_CR_ADCAL_Pos (31U) |
| #define | ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) |
| #define | ADC_CR_ADCAL ADC_CR_ADCAL_Msk |
| #define | ADC_CFGR1_DMNGT_Pos (0U) |
| #define | ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) |
| #define | ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk |
| #define | ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) |
| #define | ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) |
| #define | ADC_CFGR1_RES_Pos (2U) |
| #define | ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) |
| #define | ADC_CFGR1_RES ADC_CFGR1_RES_Msk |
| #define | ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) |
| #define | ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) |
| #define | ADC4_CFGR1_DMAEN_Pos (0U) |
| #define | ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) |
| #define | ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk |
| #define | ADC4_CFGR1_DMACFG_Pos (1U) |
| #define | ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) |
| #define | ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk |
| #define | ADC4_CFGR1_SCANDIR_Pos (4U) |
| #define | ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) |
| #define | ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk |
| #define | ADC4_CFGR1_ALIGN_Pos (5U) |
| #define | ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) |
| #define | ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk |
| #define | ADC_CFGR1_EXTSEL_Pos (5U) |
| #define | ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) |
| #define | ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk |
| #define | ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) |
| #define | ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) |
| #define | ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) |
| #define | ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) |
| #define | ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) |
| #define | ADC_CFGR1_EXTEN_Pos (10U) |
| #define | ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) |
| #define | ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk |
| #define | ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) |
| #define | ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) |
| #define | ADC_CFGR1_OVRMOD_Pos (12U) |
| #define | ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) |
| #define | ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk |
| #define | ADC_CFGR1_CONT_Pos (13U) |
| #define | ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) |
| #define | ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk |
| #define | ADC_CFGR1_AUTDLY_Pos (14U) |
| #define | ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) |
| #define | ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk |
| #define | ADC4_CFGR1_WAIT_Pos (14U) |
| #define | ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) |
| #define | ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk |
| #define | ADC_CFGR1_DISCEN_Pos (16U) |
| #define | ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) |
| #define | ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk |
| #define | ADC_CFGR1_DISCNUM_Pos (17U) |
| #define | ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) |
| #define | ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk |
| #define | ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) |
| #define | ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) |
| #define | ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) |
| #define | ADC_CFGR1_JDISCEN_Pos (20U) |
| #define | ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) |
| #define | ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk |
| #define | ADC_CFGR1_AWD1SGL_Pos (22U) |
| #define | ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) |
| #define | ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk |
| #define | ADC_CFGR1_AWD1EN_Pos (23U) |
| #define | ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) |
| #define | ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk |
| #define | ADC_CFGR1_JAWD1EN_Pos (24U) |
| #define | ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) |
| #define | ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk |
| #define | ADC_CFGR1_JAUTO_Pos (25U) |
| #define | ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) |
| #define | ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk |
| #define | ADC4_CFGR1_EXTSEL_Pos (6U) |
| #define | ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) |
| #define | ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk |
| #define | ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) |
| #define | ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) |
| #define | ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) |
| #define | ADC4_CFGR1_CHSELRMOD_Pos (21U) |
| #define | ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) |
| #define | ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk |
| #define | ADC_CFGR1_AWD1CH_Pos (26U) |
| #define | ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) |
| #define | ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk |
| #define | ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) |
| #define | ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) |
| #define | ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) |
| #define | ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) |
| #define | ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) |
| #define | ADC_CFGR2_ROVSE_Pos (0U) |
| #define | ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) |
| #define | ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk |
| #define | ADC_CFGR2_JOVSE_Pos (1U) |
| #define | ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) |
| #define | ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk |
| #define | ADC_CFGR2_OVSS_Pos (5U) |
| #define | ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) |
| #define | ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk |
| #define | ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) |
| #define | ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) |
| #define | ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) |
| #define | ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) |
| #define | ADC_CFGR2_TROVS_Pos (9U) |
| #define | ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) |
| #define | ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk |
| #define | ADC_CFGR2_ROVSM_Pos (10U) |
| #define | ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) |
| #define | ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk |
| #define | ADC_CFGR2_OVSR_Pos (16U) |
| #define | ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) |
| #define | ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk |
| #define | ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) |
| #define | ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) |
| #define | ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) |
| #define | ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) |
| #define | ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) |
| #define | ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) |
| #define | ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) |
| #define | ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) |
| #define | ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) |
| #define | ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) |
| #define | ADC_CFGR2_BULB_Pos (13U) |
| #define | ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) |
| #define | ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk |
| #define | ADC_CFGR2_SWTRIG_Pos (14U) |
| #define | ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) |
| #define | ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk |
| #define | ADC_CFGR2_SMPTRIG_Pos (15U) |
| #define | ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) |
| #define | ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk |
| #define | ADC_CFGR2_LFTRIG_Pos (27U) |
| #define | ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) |
| #define | ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk |
| #define | ADC_CFGR2_LSHIFT_Pos (28U) |
| #define | ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) |
| #define | ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk |
| #define | ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) |
| #define | ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) |
| #define | ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) |
| #define | ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) |
| #define | ADC4_CFGR2_OVSR_Pos (2U) |
| #define | ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) |
| #define | ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk |
| #define | ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) |
| #define | ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) |
| #define | ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) |
| #define | ADC4_CFGR2_LFTRIG_Pos (29U) |
| #define | ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) |
| #define | ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk |
| #define | ADC_SMPR1_SMP0_Pos (0U) |
| #define | ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) |
| #define | ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk |
| #define | ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) |
| #define | ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) |
| #define | ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) |
| #define | ADC_SMPR1_SMP1_Pos (3U) |
| #define | ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) |
| #define | ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk |
| #define | ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) |
| #define | ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) |
| #define | ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) |
| #define | ADC_SMPR1_SMP2_Pos (6U) |
| #define | ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) |
| #define | ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk |
| #define | ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) |
| #define | ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) |
| #define | ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) |
| #define | ADC_SMPR1_SMP3_Pos (9U) |
| #define | ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) |
| #define | ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk |
| #define | ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) |
| #define | ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) |
| #define | ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) |
| #define | ADC_SMPR1_SMP4_Pos (12U) |
| #define | ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) |
| #define | ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk |
| #define | ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) |
| #define | ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) |
| #define | ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) |
| #define | ADC_SMPR1_SMP5_Pos (15U) |
| #define | ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) |
| #define | ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk |
| #define | ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) |
| #define | ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) |
| #define | ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) |
| #define | ADC_SMPR1_SMP6_Pos (18U) |
| #define | ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) |
| #define | ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk |
| #define | ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) |
| #define | ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) |
| #define | ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) |
| #define | ADC_SMPR1_SMP7_Pos (21U) |
| #define | ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) |
| #define | ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk |
| #define | ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) |
| #define | ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) |
| #define | ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) |
| #define | ADC_SMPR1_SMP8_Pos (24U) |
| #define | ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) |
| #define | ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk |
| #define | ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) |
| #define | ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) |
| #define | ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) |
| #define | ADC_SMPR1_SMP9_Pos (27U) |
| #define | ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) |
| #define | ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk |
| #define | ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) |
| #define | ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) |
| #define | ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) |
| #define | ADC4_SMPR_SMP1_Pos (0U) |
| #define | ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) |
| #define | ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk |
| #define | ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) |
| #define | ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) |
| #define | ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) |
| #define | ADC4_SMPR_SMP2_Pos (4U) |
| #define | ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) |
| #define | ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk |
| #define | ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) |
| #define | ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) |
| #define | ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) |
| #define | ADC4_SMPR_SMPSEL_Pos (8U) |
| #define | ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) |
| #define | ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk |
| #define | ADC4_SMPR_SMPSEL0_Pos (8U) |
| #define | ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) |
| #define | ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk |
| #define | ADC4_SMPR_SMPSEL1_Pos (9U) |
| #define | ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) |
| #define | ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk |
| #define | ADC4_SMPR_SMPSEL2_Pos (10U) |
| #define | ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) |
| #define | ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk |
| #define | ADC4_SMPR_SMPSEL3_Pos (11U) |
| #define | ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) |
| #define | ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk |
| #define | ADC4_SMPR_SMPSEL4_Pos (12U) |
| #define | ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) |
| #define | ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk |
| #define | ADC4_SMPR_SMPSEL5_Pos (13U) |
| #define | ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) |
| #define | ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk |
| #define | ADC4_SMPR_SMPSEL6_Pos (14U) |
| #define | ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) |
| #define | ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk |
| #define | ADC4_SMPR_SMPSEL7_Pos (15U) |
| #define | ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) |
| #define | ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk |
| #define | ADC4_SMPR_SMPSEL8_Pos (16U) |
| #define | ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) |
| #define | ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk |
| #define | ADC4_SMPR_SMPSEL9_Pos (17U) |
| #define | ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) |
| #define | ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk |
| #define | ADC4_SMPR_SMPSEL10_Pos (18U) |
| #define | ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) |
| #define | ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk |
| #define | ADC4_SMPR_SMPSEL11_Pos (19U) |
| #define | ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) |
| #define | ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk |
| #define | ADC4_SMPR_SMPSEL12_Pos (20U) |
| #define | ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) |
| #define | ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk |
| #define | ADC4_SMPR_SMPSEL13_Pos (21U) |
| #define | ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) |
| #define | ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk |
| #define | ADC4_SMPR_SMPSEL14_Pos (22U) |
| #define | ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) |
| #define | ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk |
| #define | ADC4_SMPR_SMPSEL15_Pos (23U) |
| #define | ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) |
| #define | ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk |
| #define | ADC4_SMPR_SMPSEL16_Pos (24U) |
| #define | ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) |
| #define | ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk |
| #define | ADC4_SMPR_SMPSEL17_Pos (25U) |
| #define | ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) |
| #define | ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk |
| #define | ADC4_SMPR_SMPSEL18_Pos (26U) |
| #define | ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) |
| #define | ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk |
| #define | ADC4_SMPR_SMPSEL19_Pos (27U) |
| #define | ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) |
| #define | ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk |
| #define | ADC4_SMPR_SMPSEL20_Pos (26U) |
| #define | ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) |
| #define | ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk |
| #define | ADC4_SMPR_SMPSEL21_Pos (26U) |
| #define | ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) |
| #define | ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk |
| #define | ADC4_SMPR_SMPSEL22_Pos (30U) |
| #define | ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) |
| #define | ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk |
| #define | ADC4_SMPR_SMPSEL23_Pos (31U) |
| #define | ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) |
| #define | ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk |
| #define | ADC_SMPR2_SMP10_Pos (0U) |
| #define | ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) |
| #define | ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk |
| #define | ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) |
| #define | ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) |
| #define | ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) |
| #define | ADC_SMPR2_SMP11_Pos (3U) |
| #define | ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) |
| #define | ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk |
| #define | ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) |
| #define | ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) |
| #define | ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) |
| #define | ADC_SMPR2_SMP12_Pos (6U) |
| #define | ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) |
| #define | ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk |
| #define | ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) |
| #define | ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) |
| #define | ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) |
| #define | ADC_SMPR2_SMP13_Pos (9U) |
| #define | ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) |
| #define | ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk |
| #define | ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) |
| #define | ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) |
| #define | ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) |
| #define | ADC_SMPR2_SMP14_Pos (12U) |
| #define | ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) |
| #define | ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk |
| #define | ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) |
| #define | ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) |
| #define | ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) |
| #define | ADC_SMPR2_SMP15_Pos (15U) |
| #define | ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) |
| #define | ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk |
| #define | ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) |
| #define | ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) |
| #define | ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) |
| #define | ADC_SMPR2_SMP16_Pos (18U) |
| #define | ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) |
| #define | ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk |
| #define | ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) |
| #define | ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) |
| #define | ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) |
| #define | ADC_SMPR2_SMP17_Pos (21U) |
| #define | ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) |
| #define | ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk |
| #define | ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) |
| #define | ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) |
| #define | ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) |
| #define | ADC_SMPR2_SMP18_Pos (24U) |
| #define | ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) |
| #define | ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk |
| #define | ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) |
| #define | ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) |
| #define | ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) |
| #define | ADC_SMPR2_SMP19_Pos (27U) |
| #define | ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) |
| #define | ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk |
| #define | ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) |
| #define | ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) |
| #define | ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) |
| #define | ADC_PCSEL_PCSEL_Pos (0U) |
| #define | ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk |
| #define | ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) |
| #define | ADC_LTR_LT_Pos (0U) |
| #define | ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) |
| #define | ADC_LTR_LT ADC_LTR_LT_Msk |
| #define | ADC_HTR_HT_Pos (0U) |
| #define | ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) |
| #define | ADC_HTR_HT ADC_HTR_HT_Msk |
| #define | ADC_HTR_AWDFILT_Pos (29U) |
| #define | ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) |
| #define | ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk |
| #define | ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) |
| #define | ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) |
| #define | ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) |
| #define | ADC_SQR1_L_Pos (0U) |
| #define | ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) |
| #define | ADC_SQR1_L ADC_SQR1_L_Msk |
| #define | ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) |
| #define | ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) |
| #define | ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) |
| #define | ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) |
| #define | ADC_SQR1_SQ1_Pos (6U) |
| #define | ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) |
| #define | ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk |
| #define | ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) |
| #define | ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) |
| #define | ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) |
| #define | ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) |
| #define | ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) |
| #define | ADC_SQR1_SQ2_Pos (12U) |
| #define | ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) |
| #define | ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk |
| #define | ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) |
| #define | ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) |
| #define | ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) |
| #define | ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) |
| #define | ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) |
| #define | ADC_SQR1_SQ3_Pos (18U) |
| #define | ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) |
| #define | ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk |
| #define | ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) |
| #define | ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) |
| #define | ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) |
| #define | ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) |
| #define | ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) |
| #define | ADC_SQR1_SQ4_Pos (24U) |
| #define | ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) |
| #define | ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk |
| #define | ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) |
| #define | ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) |
| #define | ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) |
| #define | ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) |
| #define | ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) |
| #define | ADC_SQR2_SQ5_Pos (0U) |
| #define | ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) |
| #define | ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk |
| #define | ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) |
| #define | ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) |
| #define | ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) |
| #define | ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) |
| #define | ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) |
| #define | ADC_SQR2_SQ6_Pos (6U) |
| #define | ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) |
| #define | ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk |
| #define | ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) |
| #define | ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) |
| #define | ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) |
| #define | ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) |
| #define | ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) |
| #define | ADC_SQR2_SQ7_Pos (12U) |
| #define | ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) |
| #define | ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk |
| #define | ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) |
| #define | ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) |
| #define | ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) |
| #define | ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) |
| #define | ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) |
| #define | ADC_SQR2_SQ8_Pos (18U) |
| #define | ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) |
| #define | ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk |
| #define | ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) |
| #define | ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) |
| #define | ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) |
| #define | ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) |
| #define | ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) |
| #define | ADC_SQR2_SQ9_Pos (24U) |
| #define | ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) |
| #define | ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk |
| #define | ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) |
| #define | ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) |
| #define | ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) |
| #define | ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) |
| #define | ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) |
| #define | ADC_SQR3_SQ10_Pos (0U) |
| #define | ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) |
| #define | ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk |
| #define | ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) |
| #define | ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) |
| #define | ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) |
| #define | ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) |
| #define | ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) |
| #define | ADC_SQR3_SQ11_Pos (6U) |
| #define | ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) |
| #define | ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk |
| #define | ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) |
| #define | ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) |
| #define | ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) |
| #define | ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) |
| #define | ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) |
| #define | ADC_SQR3_SQ12_Pos (12U) |
| #define | ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) |
| #define | ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk |
| #define | ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) |
| #define | ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) |
| #define | ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) |
| #define | ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) |
| #define | ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) |
| #define | ADC_SQR3_SQ13_Pos (18U) |
| #define | ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) |
| #define | ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk |
| #define | ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) |
| #define | ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) |
| #define | ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) |
| #define | ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) |
| #define | ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) |
| #define | ADC_SQR3_SQ14_Pos (24U) |
| #define | ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) |
| #define | ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk |
| #define | ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) |
| #define | ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) |
| #define | ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) |
| #define | ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) |
| #define | ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) |
| #define | ADC_SQR4_SQ15_Pos (0U) |
| #define | ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) |
| #define | ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk |
| #define | ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) |
| #define | ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) |
| #define | ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) |
| #define | ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) |
| #define | ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) |
| #define | ADC_SQR4_SQ16_Pos (6U) |
| #define | ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) |
| #define | ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk |
| #define | ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) |
| #define | ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) |
| #define | ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) |
| #define | ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) |
| #define | ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) |
| #define | ADC_DR_RDATA_Pos (0U) |
| #define | ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) |
| #define | ADC_DR_RDATA ADC_DR_RDATA_Msk |
| #define | ADC4_PWRR_AUTOFF_Pos (0U) |
| #define | ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) |
| #define | ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk |
| #define | ADC4_PWRR_DPD_Pos (1U) |
| #define | ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) |
| #define | ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk |
| #define | ADC4_PWRR_VREFPROT_Pos (2U) |
| #define | ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) |
| #define | ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk |
| #define | ADC4_PWRR_VREFSECSMP_Pos (3U) |
| #define | ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) |
| #define | ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk |
| #define | ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos |
| #define | ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk |
| #define | ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF |
| #define | ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos |
| #define | ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk |
| #define | ADC4_PW_DPD ADC4_PWRR_DPD |
| #define | ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos |
| #define | ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk |
| #define | ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT |
| #define | ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos |
| #define | ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk |
| #define | ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP |
| #define | ADC_JSQR_JL_Pos (0U) |
| #define | ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) |
| #define | ADC_JSQR_JL ADC_JSQR_JL_Msk |
| #define | ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) |
| #define | ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) |
| #define | ADC_JSQR_JEXTSEL_Pos (2U) |
| #define | ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) |
| #define | ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk |
| #define | ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) |
| #define | ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) |
| #define | ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) |
| #define | ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) |
| #define | ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) |
| #define | ADC_JSQR_JEXTEN_Pos (7U) |
| #define | ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) |
| #define | ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk |
| #define | ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) |
| #define | ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) |
| #define | ADC_JSQR_JSQ1_Pos (9U) |
| #define | ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) |
| #define | ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk |
| #define | ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) |
| #define | ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) |
| #define | ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) |
| #define | ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) |
| #define | ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) |
| #define | ADC_JSQR_JSQ2_Pos (15U) |
| #define | ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) |
| #define | ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk |
| #define | ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) |
| #define | ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) |
| #define | ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) |
| #define | ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) |
| #define | ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) |
| #define | ADC_JSQR_JSQ3_Pos (21U) |
| #define | ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) |
| #define | ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk |
| #define | ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) |
| #define | ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) |
| #define | ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) |
| #define | ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) |
| #define | ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) |
| #define | ADC_JSQR_JSQ4_Pos (27U) |
| #define | ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) |
| #define | ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk |
| #define | ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) |
| #define | ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) |
| #define | ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) |
| #define | ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) |
| #define | ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) |
| #define | ADC_OFR1_OFFSET1_Pos (0U) |
| #define | ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk |
| #define | ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) |
| #define | ADC_OFR1_OFFSETPOS_Pos (24U) |
| #define | ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) |
| #define | ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk |
| #define | ADC_OFR1_USAT_Pos (25U) |
| #define | ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) |
| #define | ADC_OFR1_USAT ADC_OFR1_USAT_Msk |
| #define | ADC_OFR1_SSAT_Pos (26U) |
| #define | ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) |
| #define | ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk |
| #define | ADC_OFR1_OFFSET1_CH_Pos (27U) |
| #define | ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) |
| #define | ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk |
| #define | ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) |
| #define | ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) |
| #define | ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) |
| #define | ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) |
| #define | ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) |
| #define | ADC_OFR2_OFFSET2_Pos (0U) |
| #define | ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk |
| #define | ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) |
| #define | ADC_OFR2_OFFSETPOS_Pos (24U) |
| #define | ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) |
| #define | ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk |
| #define | ADC_OFR2_USAT_Pos (25U) |
| #define | ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) |
| #define | ADC_OFR2_USAT ADC_OFR2_USAT_Msk |
| #define | ADC_OFR2_SSAT_Pos (26U) |
| #define | ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) |
| #define | ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk |
| #define | ADC_OFR2_OFFSET2_CH_Pos (27U) |
| #define | ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) |
| #define | ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk |
| #define | ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) |
| #define | ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) |
| #define | ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) |
| #define | ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) |
| #define | ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) |
| #define | ADC_OFR3_OFFSET3_Pos (0U) |
| #define | ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk |
| #define | ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) |
| #define | ADC_OFR3_OFFSETPOS_Pos (24U) |
| #define | ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) |
| #define | ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk |
| #define | ADC_OFR3_USAT_Pos (25U) |
| #define | ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) |
| #define | ADC_OFR3_USAT ADC_OFR3_USAT_Msk |
| #define | ADC_OFR3_SSAT_Pos (26U) |
| #define | ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) |
| #define | ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk |
| #define | ADC_OFR3_OFFSET3_CH_Pos (27U) |
| #define | ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) |
| #define | ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk |
| #define | ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) |
| #define | ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) |
| #define | ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) |
| #define | ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) |
| #define | ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) |
| #define | ADC_OFR4_OFFSET4_Pos (0U) |
| #define | ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk |
| #define | ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) |
| #define | ADC_OFR4_OFFSETPOS_Pos (24U) |
| #define | ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) |
| #define | ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk |
| #define | ADC_OFR4_USAT_Pos (25U) |
| #define | ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) |
| #define | ADC_OFR4_USAT ADC_OFR4_USAT_Msk |
| #define | ADC_OFR4_SSAT_Pos (26U) |
| #define | ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) |
| #define | ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk |
| #define | ADC_OFR4_OFFSET4_CH_Pos (27U) |
| #define | ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) |
| #define | ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk |
| #define | ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) |
| #define | ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) |
| #define | ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) |
| #define | ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) |
| #define | ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) |
| #define | ADC_GCOMP_GCOMPCOEFF_Pos (0U) |
| #define | ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos) |
| #define | ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk |
| #define | ADC_GCOMP_GCOMP_Pos (31U) |
| #define | ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) |
| #define | ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk |
| #define | ADC_JDR1_JDATA_Pos (0U) |
| #define | ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk |
| #define | ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_Pos (0U) |
| #define | ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk |
| #define | ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_Pos (0U) |
| #define | ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk |
| #define | ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_Pos (0U) |
| #define | ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk |
| #define | ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) |
| #define | ADC_AWD2CR_AWD2CH_Pos (0U) |
| #define | ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk |
| #define | ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) |
| #define | ADC_AWD1TR_LT1_Pos (0U) |
| #define | ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) |
| #define | ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk |
| #define | ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) |
| #define | ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) |
| #define | ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) |
| #define | ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) |
| #define | ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) |
| #define | ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) |
| #define | ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) |
| #define | ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) |
| #define | ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) |
| #define | ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) |
| #define | ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) |
| #define | ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) |
| #define | ADC_AWD1TR_HT1_Pos (16U) |
| #define | ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) |
| #define | ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk |
| #define | ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) |
| #define | ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) |
| #define | ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) |
| #define | ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) |
| #define | ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) |
| #define | ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) |
| #define | ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) |
| #define | ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) |
| #define | ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) |
| #define | ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) |
| #define | ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) |
| #define | ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) |
| #define | ADC_AWD2TR_LT2_Pos (0U) |
| #define | ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) |
| #define | ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk |
| #define | ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) |
| #define | ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) |
| #define | ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) |
| #define | ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) |
| #define | ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) |
| #define | ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) |
| #define | ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) |
| #define | ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) |
| #define | ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) |
| #define | ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) |
| #define | ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) |
| #define | ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) |
| #define | ADC_AWD2TR_HT2_Pos (16U) |
| #define | ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) |
| #define | ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk |
| #define | ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) |
| #define | ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) |
| #define | ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) |
| #define | ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) |
| #define | ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) |
| #define | ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) |
| #define | ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) |
| #define | ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) |
| #define | ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) |
| #define | ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) |
| #define | ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) |
| #define | ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) |
| #define | ADC_CHSELR_CHSEL_Pos (0U) |
| #define | ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) |
| #define | ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk |
| #define | ADC_CHSELR_CHSEL0_Pos (0U) |
| #define | ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) |
| #define | ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk |
| #define | ADC_CHSELR_CHSEL1_Pos (1U) |
| #define | ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) |
| #define | ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk |
| #define | ADC_CHSELR_CHSEL2_Pos (2U) |
| #define | ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) |
| #define | ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk |
| #define | ADC_CHSELR_CHSEL3_Pos (3U) |
| #define | ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) |
| #define | ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk |
| #define | ADC_CHSELR_CHSEL4_Pos (4U) |
| #define | ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) |
| #define | ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk |
| #define | ADC_CHSELR_CHSEL5_Pos (5U) |
| #define | ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) |
| #define | ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk |
| #define | ADC_CHSELR_CHSEL6_Pos (6U) |
| #define | ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) |
| #define | ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk |
| #define | ADC_CHSELR_CHSEL7_Pos (7U) |
| #define | ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) |
| #define | ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk |
| #define | ADC_CHSELR_CHSEL8_Pos (8U) |
| #define | ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) |
| #define | ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk |
| #define | ADC_CHSELR_CHSEL9_Pos (9U) |
| #define | ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) |
| #define | ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk |
| #define | ADC_CHSELR_CHSEL10_Pos (10U) |
| #define | ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) |
| #define | ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk |
| #define | ADC_CHSELR_CHSEL11_Pos (11U) |
| #define | ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) |
| #define | ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk |
| #define | ADC_CHSELR_CHSEL12_Pos (12U) |
| #define | ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) |
| #define | ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk |
| #define | ADC_CHSELR_CHSEL13_Pos (13U) |
| #define | ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) |
| #define | ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk |
| #define | ADC_CHSELR_CHSEL14_Pos (14U) |
| #define | ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) |
| #define | ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk |
| #define | ADC_CHSELR_CHSEL15_Pos (15U) |
| #define | ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) |
| #define | ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk |
| #define | ADC_CHSELR_CHSEL16_Pos (16U) |
| #define | ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) |
| #define | ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk |
| #define | ADC_CHSELR_CHSEL17_Pos (17U) |
| #define | ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) |
| #define | ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk |
| #define | ADC_CHSELR_CHSEL18_Pos (18U) |
| #define | ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) |
| #define | ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk |
| #define | ADC_CHSELR_CHSEL19_Pos (19U) |
| #define | ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) |
| #define | ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk |
| #define | ADC_CHSELR_CHSEL20_Pos (20U) |
| #define | ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) |
| #define | ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk |
| #define | ADC_CHSELR_CHSEL21_Pos (21U) |
| #define | ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) |
| #define | ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk |
| #define | ADC_CHSELR_CHSEL22_Pos (22U) |
| #define | ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) |
| #define | ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk |
| #define | ADC_CHSELR_CHSEL23_Pos (23U) |
| #define | ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) |
| #define | ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk |
| #define | ADC_CHSELR_SQ_ALL_Pos (0U) |
| #define | ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) |
| #define | ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk |
| #define | ADC_CHSELR_SQ1_Pos (0U) |
| #define | ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) |
| #define | ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk |
| #define | ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) |
| #define | ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) |
| #define | ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) |
| #define | ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) |
| #define | ADC_CHSELR_SQ2_Pos (4U) |
| #define | ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) |
| #define | ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk |
| #define | ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) |
| #define | ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) |
| #define | ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) |
| #define | ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) |
| #define | ADC_CHSELR_SQ3_Pos (8U) |
| #define | ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) |
| #define | ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk |
| #define | ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) |
| #define | ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) |
| #define | ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) |
| #define | ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) |
| #define | ADC_CHSELR_SQ4_Pos (12U) |
| #define | ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) |
| #define | ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk |
| #define | ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) |
| #define | ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) |
| #define | ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) |
| #define | ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) |
| #define | ADC_CHSELR_SQ5_Pos (16U) |
| #define | ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) |
| #define | ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk |
| #define | ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) |
| #define | ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) |
| #define | ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) |
| #define | ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) |
| #define | ADC_CHSELR_SQ6_Pos (20U) |
| #define | ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) |
| #define | ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk |
| #define | ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) |
| #define | ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) |
| #define | ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) |
| #define | ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) |
| #define | ADC_CHSELR_SQ7_Pos (24U) |
| #define | ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) |
| #define | ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk |
| #define | ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) |
| #define | ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) |
| #define | ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) |
| #define | ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) |
| #define | ADC_CHSELR_SQ8_Pos (28U) |
| #define | ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) |
| #define | ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk |
| #define | ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) |
| #define | ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) |
| #define | ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) |
| #define | ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) |
| #define | ADC_AWD3TR_LT3_Pos (0U) |
| #define | ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) |
| #define | ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk |
| #define | ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) |
| #define | ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) |
| #define | ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) |
| #define | ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) |
| #define | ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) |
| #define | ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) |
| #define | ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) |
| #define | ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) |
| #define | ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) |
| #define | ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) |
| #define | ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) |
| #define | ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) |
| #define | ADC_AWD3TR_HT3_Pos (16U) |
| #define | ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) |
| #define | ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk |
| #define | ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) |
| #define | ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) |
| #define | ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) |
| #define | ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) |
| #define | ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) |
| #define | ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) |
| #define | ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) |
| #define | ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) |
| #define | ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) |
| #define | ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) |
| #define | ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) |
| #define | ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) |
| #define | ADC_AWD3CR_AWD3CH_Pos (0U) |
| #define | ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk |
| #define | ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) |
| #define | ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) |
| #define | ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) |
| #define | ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) |
| #define | ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) |
| #define | ADC_DIFSEL_DIFSEL_Pos (0U) |
| #define | ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk |
| #define | ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) |
| #define | ADC_CALFACT_I_APB_ADDR_Pos (0U) |
| #define | ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) |
| #define | ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk |
| #define | ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) |
| #define | ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) |
| #define | ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) |
| #define | ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) |
| #define | ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) |
| #define | ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) |
| #define | ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) |
| #define | ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) |
| #define | ADC_CALFACT_I_APB_DATA_Pos (08U) |
| #define | ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) |
| #define | ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk |
| #define | ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) |
| #define | ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) |
| #define | ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) |
| #define | ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) |
| #define | ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) |
| #define | ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) |
| #define | ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) |
| #define | ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) |
| #define | ADC_CALFACT_VALIDITY_Pos (16U) |
| #define | ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) |
| #define | ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk |
| #define | ADC_CALFACT_LATCH_COEF_Pos (24U) |
| #define | ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) |
| #define | ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk |
| #define | ADC_CALFACT_CAPTURE_COEF_Pos (25U) |
| #define | ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) |
| #define | ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk |
| #define | ADC4_CALFACT_CALFACT_Pos (0U) |
| #define | ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) |
| #define | ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk |
| #define | ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) |
| #define | ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) |
| #define | ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) |
| #define | ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) |
| #define | ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) |
| #define | ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) |
| #define | ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_Pos (0U) |
| #define | ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk |
| #define | ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) |
| #define | ADC_OR_CHN0SEL_Pos (0U) |
| #define | ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) |
| #define | ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk |
| #define | ADC_CSR_ADRDY_MST_Pos (0U) |
| #define | ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) |
| #define | ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk |
| #define | ADC_CSR_EOSMP_MST_Pos (1U) |
| #define | ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) |
| #define | ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk |
| #define | ADC_CSR_EOC_MST_Pos (2U) |
| #define | ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) |
| #define | ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk |
| #define | ADC_CSR_EOS_MST_Pos (3U) |
| #define | ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) |
| #define | ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk |
| #define | ADC_CSR_OVR_MST_Pos (4U) |
| #define | ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) |
| #define | ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk |
| #define | ADC_CSR_JEOC_MST_Pos (5U) |
| #define | ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) |
| #define | ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk |
| #define | ADC_CSR_JEOS_MST_Pos (6U) |
| #define | ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) |
| #define | ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk |
| #define | ADC_CSR_AWD1_MST_Pos (7U) |
| #define | ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) |
| #define | ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk |
| #define | ADC_CSR_AWD2_MST_Pos (8U) |
| #define | ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) |
| #define | ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk |
| #define | ADC_CSR_AWD3_MST_Pos (9U) |
| #define | ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) |
| #define | ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk |
| #define | ADC_CSR_JQOVF_MST_Pos (10U) |
| #define | ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) |
| #define | ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk |
| #define | ADC_CSR_LDORDY_MST_Pos (12U) |
| #define | ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) |
| #define | ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk |
| #define | ADC_CSR_ADRDY_SLV_Pos (16U) |
| #define | ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) |
| #define | ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk |
| #define | ADC_CSR_EOSMP_SLV_Pos (17U) |
| #define | ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) |
| #define | ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk |
| #define | ADC_CSR_EOC_SLV_Pos (18U) |
| #define | ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) |
| #define | ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk |
| #define | ADC_CSR_EOS_SLV_Pos (19U) |
| #define | ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) |
| #define | ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk |
| #define | ADC_CSR_OVR_SLV_Pos (20U) |
| #define | ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) |
| #define | ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk |
| #define | ADC_CSR_JEOC_SLV_Pos (21U) |
| #define | ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) |
| #define | ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk |
| #define | ADC_CSR_JEOS_SLV_Pos (22U) |
| #define | ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) |
| #define | ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk |
| #define | ADC_CSR_AWD1_SLV_Pos (23U) |
| #define | ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) |
| #define | ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk |
| #define | ADC_CSR_AWD2_SLV_Pos (24U) |
| #define | ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) |
| #define | ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk |
| #define | ADC_CSR_AWD3_SLV_Pos (25U) |
| #define | ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) |
| #define | ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk |
| #define | ADC_CSR_JQOVF_SLV_Pos (26U) |
| #define | ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) |
| #define | ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk |
| #define | ADC_CSR_LDORDY_SLV_Pos (28U) |
| #define | ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) |
| #define | ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk |
| #define | ADC_CCR_DUAL_Pos (0U) |
| #define | ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) |
| #define | ADC_CCR_DUAL ADC_CCR_DUAL_Msk |
| #define | ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) |
| #define | ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) |
| #define | ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) |
| #define | ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) |
| #define | ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) |
| #define | ADC_CCR_DELAY_Pos (8U) |
| #define | ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) |
| #define | ADC_CCR_DELAY ADC_CCR_DELAY_Msk |
| #define | ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) |
| #define | ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) |
| #define | ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) |
| #define | ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) |
| #define | ADC_CCR_DAMDF_Pos (14U) |
| #define | ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) |
| #define | ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk |
| #define | ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) |
| #define | ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) |
| #define | ADC_CCR_PRESC_Pos (18U) |
| #define | ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) |
| #define | ADC_CCR_PRESC ADC_CCR_PRESC_Msk |
| #define | ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) |
| #define | ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) |
| #define | ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) |
| #define | ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) |
| #define | ADC_CCR_VREFEN_Pos (22U) |
| #define | ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) |
| #define | ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk |
| #define | ADC_CCR_VSENSEEN_Pos (23U) |
| #define | ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) |
| #define | ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk |
| #define | ADC_CCR_VBATEN_Pos (24U) |
| #define | ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) |
| #define | ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk |
| #define | ADC_CCR_LFMEN_Pos (25U) |
| #define | ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) |
| #define | ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk |
| #define | ADC_CCR_VDDCOREN_Pos (26U) |
| #define | ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) |
| #define | ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk |
| #define | ADC_CDR_RDATA_MST_Pos (0U) |
| #define | ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) |
| #define | ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk |
| #define | ADC_CDR_RDATA_SLV_Pos (16U) |
| #define | ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) |
| #define | ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk |
| #define | ADC_CDR2_RDATA_ALT_Pos (0U) |
| #define | ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) |
| #define | ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk |
| #define | CORDIC_CSR_FUNC_Pos (0U) |
| #define | CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) |
| #define | CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk |
| #define | CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) |
| #define | CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) |
| #define | CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) |
| #define | CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) |
| #define | CORDIC_CSR_PRECISION_Pos (4U) |
| #define | CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) |
| #define | CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk |
| #define | CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) |
| #define | CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) |
| #define | CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) |
| #define | CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) |
| #define | CORDIC_CSR_SCALE_Pos (8U) |
| #define | CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) |
| #define | CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk |
| #define | CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) |
| #define | CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) |
| #define | CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) |
| #define | CORDIC_CSR_IEN_Pos (16U) |
| #define | CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) |
| #define | CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk |
| #define | CORDIC_CSR_DMAREN_Pos (17U) |
| #define | CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) |
| #define | CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk |
| #define | CORDIC_CSR_DMAWEN_Pos (18U) |
| #define | CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) |
| #define | CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk |
| #define | CORDIC_CSR_NRES_Pos (19U) |
| #define | CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) |
| #define | CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk |
| #define | CORDIC_CSR_NARGS_Pos (20U) |
| #define | CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) |
| #define | CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk |
| #define | CORDIC_CSR_RESSIZE_Pos (21U) |
| #define | CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) |
| #define | CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk |
| #define | CORDIC_CSR_ARGSIZE_Pos (22U) |
| #define | CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) |
| #define | CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk |
| #define | CORDIC_CSR_RRDY_Pos (31U) |
| #define | CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) |
| #define | CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk |
| #define | CORDIC_WDATA_ARG_Pos (0U) |
| #define | CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) |
| #define | CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk |
| #define | CORDIC_RDATA_RES_Pos (0U) |
| #define | CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) |
| #define | CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk |
| #define | CRC_DR_DR_Pos (0U) |
| #define | CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) |
| #define | CRC_DR_DR CRC_DR_DR_Msk |
| #define | CRC_IDR_IDR_Pos (0U) |
| #define | CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) |
| #define | CRC_IDR_IDR CRC_IDR_IDR_Msk |
| #define | CRC_CR_RESET_Pos (0U) |
| #define | CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) |
| #define | CRC_CR_RESET CRC_CR_RESET_Msk |
| #define | CRC_CR_POLYSIZE_Pos (3U) |
| #define | CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) |
| #define | CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk |
| #define | CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) |
| #define | CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) |
| #define | CRC_CR_REV_IN_Pos (5U) |
| #define | CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) |
| #define | CRC_CR_REV_IN CRC_CR_REV_IN_Msk |
| #define | CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) |
| #define | CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) |
| #define | CRC_CR_REV_OUT_Pos (7U) |
| #define | CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) |
| #define | CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk |
| #define | CRC_INIT_INIT_Pos (0U) |
| #define | CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) |
| #define | CRC_INIT_INIT CRC_INIT_INIT_Msk |
| #define | CRC_POL_POL_Pos (0U) |
| #define | CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) |
| #define | CRC_POL_POL CRC_POL_POL_Msk |
| #define | CRS_CR_SYNCOKIE_Pos (0U) |
| #define | CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) |
| #define | CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk |
| #define | CRS_CR_SYNCWARNIE_Pos (1U) |
| #define | CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) |
| #define | CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk |
| #define | CRS_CR_ERRIE_Pos (2U) |
| #define | CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) |
| #define | CRS_CR_ERRIE CRS_CR_ERRIE_Msk |
| #define | CRS_CR_ESYNCIE_Pos (3U) |
| #define | CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) |
| #define | CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk |
| #define | CRS_CR_CEN_Pos (5U) |
| #define | CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) |
| #define | CRS_CR_CEN CRS_CR_CEN_Msk |
| #define | CRS_CR_AUTOTRIMEN_Pos (6U) |
| #define | CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) |
| #define | CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk |
| #define | CRS_CR_SWSYNC_Pos (7U) |
| #define | CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) |
| #define | CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk |
| #define | CRS_CR_TRIM_Pos (8U) |
| #define | CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) |
| #define | CRS_CR_TRIM CRS_CR_TRIM_Msk |
| #define | CRS_CFGR_RELOAD_Pos (0U) |
| #define | CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) |
| #define | CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk |
| #define | CRS_CFGR_FELIM_Pos (16U) |
| #define | CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) |
| #define | CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk |
| #define | CRS_CFGR_SYNCDIV_Pos (24U) |
| #define | CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) |
| #define | CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk |
| #define | CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) |
| #define | CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) |
| #define | CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) |
| #define | CRS_CFGR_SYNCSRC_Pos (28U) |
| #define | CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) |
| #define | CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk |
| #define | CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) |
| #define | CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) |
| #define | CRS_CFGR_SYNCPOL_Pos (31U) |
| #define | CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) |
| #define | CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk |
| #define | CRS_ISR_SYNCOKF_Pos (0U) |
| #define | CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) |
| #define | CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk |
| #define | CRS_ISR_SYNCWARNF_Pos (1U) |
| #define | CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) |
| #define | CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk |
| #define | CRS_ISR_ERRF_Pos (2U) |
| #define | CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) |
| #define | CRS_ISR_ERRF CRS_ISR_ERRF_Msk |
| #define | CRS_ISR_ESYNCF_Pos (3U) |
| #define | CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) |
| #define | CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk |
| #define | CRS_ISR_SYNCERR_Pos (8U) |
| #define | CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) |
| #define | CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk |
| #define | CRS_ISR_SYNCMISS_Pos (9U) |
| #define | CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) |
| #define | CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk |
| #define | CRS_ISR_TRIMOVF_Pos (10U) |
| #define | CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) |
| #define | CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk |
| #define | CRS_ISR_FEDIR_Pos (15U) |
| #define | CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) |
| #define | CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk |
| #define | CRS_ISR_FECAP_Pos (16U) |
| #define | CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) |
| #define | CRS_ISR_FECAP CRS_ISR_FECAP_Msk |
| #define | CRS_ICR_SYNCOKC_Pos (0U) |
| #define | CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) |
| #define | CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk |
| #define | CRS_ICR_SYNCWARNC_Pos (1U) |
| #define | CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) |
| #define | CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk |
| #define | CRS_ICR_ERRC_Pos (2U) |
| #define | CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) |
| #define | CRS_ICR_ERRC CRS_ICR_ERRC_Msk |
| #define | CRS_ICR_ESYNCC_Pos (3U) |
| #define | CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) |
| #define | CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk |
| #define | RNG_CR_RNGEN_Pos (2U) |
| #define | RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) |
| #define | RNG_CR_RNGEN RNG_CR_RNGEN_Msk |
| #define | RNG_CR_IE_Pos (3U) |
| #define | RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) |
| #define | RNG_CR_IE RNG_CR_IE_Msk |
| #define | RNG_CR_CED_Pos (5U) |
| #define | RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) |
| #define | RNG_CR_CED RNG_CR_CED_Msk |
| #define | RNG_CR_ARDIS_Pos (7U) |
| #define | RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) |
| #define | RNG_CR_ARDIS RNG_CR_ARDIS_Msk |
| #define | RNG_CR_RNG_CONFIG3_Pos (8U) |
| #define | RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) |
| #define | RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk |
| #define | RNG_CR_NISTC_Pos (12U) |
| #define | RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) |
| #define | RNG_CR_NISTC RNG_CR_NISTC_Msk |
| #define | RNG_CR_RNG_CONFIG2_Pos (13U) |
| #define | RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) |
| #define | RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk |
| #define | RNG_CR_CLKDIV_Pos (16U) |
| #define | RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) |
| #define | RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk |
| #define | RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) |
| #define | RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) |
| #define | RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) |
| #define | RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) |
| #define | RNG_CR_RNG_CONFIG1_Pos (20U) |
| #define | RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) |
| #define | RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk |
| #define | RNG_CR_CONDRST_Pos (30U) |
| #define | RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) |
| #define | RNG_CR_CONDRST RNG_CR_CONDRST_Msk |
| #define | RNG_CR_CONFIGLOCK_Pos (31U) |
| #define | RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) |
| #define | RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk |
| #define | RNG_SR_DRDY_Pos (0U) |
| #define | RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) |
| #define | RNG_SR_DRDY RNG_SR_DRDY_Msk |
| #define | RNG_SR_CECS_Pos (1U) |
| #define | RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) |
| #define | RNG_SR_CECS RNG_SR_CECS_Msk |
| #define | RNG_SR_SECS_Pos (2U) |
| #define | RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) |
| #define | RNG_SR_SECS RNG_SR_SECS_Msk |
| #define | RNG_SR_CEIS_Pos (5U) |
| #define | RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) |
| #define | RNG_SR_CEIS RNG_SR_CEIS_Msk |
| #define | RNG_SR_SEIS_Pos (6U) |
| #define | RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) |
| #define | RNG_SR_SEIS RNG_SR_SEIS_Msk |
| #define | RNG_NSCR_EN_OSC1_Pos (0U) |
| #define | RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) |
| #define | RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk |
| #define | RNG_NSCR_EN_OSC2_Pos (3U) |
| #define | RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) |
| #define | RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk |
| #define | RNG_NSCR_EN_OSC3_Pos (6U) |
| #define | RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) |
| #define | RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk |
| #define | RNG_NSCR_EN_OSC4_Pos (9U) |
| #define | RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) |
| #define | RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk |
| #define | RNG_NSCR_EN_OSC5_Pos (12U) |
| #define | RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) |
| #define | RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk |
| #define | RNG_NSCR_EN_OSC6_Pos (15U) |
| #define | RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) |
| #define | RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk |
| #define | RNG_HTCR_HTCFG_Pos (0U) |
| #define | RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) |
| #define | RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk |
| #define | DAC_CHANNEL2_SUPPORT |
| #define | DAC_CR_EN1_Pos (0U) |
| #define | DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) |
| #define | DAC_CR_EN1 DAC_CR_EN1_Msk |
| #define | DAC_CR_TEN1_Pos (1U) |
| #define | DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) |
| #define | DAC_CR_TEN1 DAC_CR_TEN1_Msk |
| #define | DAC_CR_TSEL1_Pos (2U) |
| #define | DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) |
| #define | DAC_CR_TSEL1 DAC_CR_TSEL1_Msk |
| #define | DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) |
| #define | DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) |
| #define | DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) |
| #define | DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) |
| #define | DAC_CR_WAVE1_Pos (6U) |
| #define | DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) |
| #define | DAC_CR_WAVE1 DAC_CR_WAVE1_Msk |
| #define | DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) |
| #define | DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) |
| #define | DAC_CR_MAMP1_Pos (8U) |
| #define | DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) |
| #define | DAC_CR_MAMP1 DAC_CR_MAMP1_Msk |
| #define | DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) |
| #define | DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) |
| #define | DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) |
| #define | DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) |
| #define | DAC_CR_DMAEN1_Pos (12U) |
| #define | DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) |
| #define | DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk |
| #define | DAC_CR_DMAUDRIE1_Pos (13U) |
| #define | DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) |
| #define | DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk |
| #define | DAC_CR_CEN1_Pos (14U) |
| #define | DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) |
| #define | DAC_CR_CEN1 DAC_CR_CEN1_Msk |
| #define | DAC_CR_EN2_Pos (16U) |
| #define | DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) |
| #define | DAC_CR_EN2 DAC_CR_EN2_Msk |
| #define | DAC_CR_TEN2_Pos (17U) |
| #define | DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) |
| #define | DAC_CR_TEN2 DAC_CR_TEN2_Msk |
| #define | DAC_CR_TSEL2_Pos (18U) |
| #define | DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) |
| #define | DAC_CR_TSEL2 DAC_CR_TSEL2_Msk |
| #define | DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) |
| #define | DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) |
| #define | DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) |
| #define | DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) |
| #define | DAC_CR_WAVE2_Pos (22U) |
| #define | DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) |
| #define | DAC_CR_WAVE2 DAC_CR_WAVE2_Msk |
| #define | DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) |
| #define | DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) |
| #define | DAC_CR_MAMP2_Pos (24U) |
| #define | DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) |
| #define | DAC_CR_MAMP2 DAC_CR_MAMP2_Msk |
| #define | DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) |
| #define | DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) |
| #define | DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) |
| #define | DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) |
| #define | DAC_CR_DMAEN2_Pos (28U) |
| #define | DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) |
| #define | DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk |
| #define | DAC_CR_DMAUDRIE2_Pos (29U) |
| #define | DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) |
| #define | DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk |
| #define | DAC_CR_CEN2_Pos (30U) |
| #define | DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) |
| #define | DAC_CR_CEN2 DAC_CR_CEN2_Msk |
| #define | DAC_SWTRIGR_SWTRIG1_Pos (0U) |
| #define | DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) |
| #define | DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk |
| #define | DAC_SWTRIGR_SWTRIG2_Pos (1U) |
| #define | DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) |
| #define | DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk |
| #define | DAC_SWTRIGR_SWTRIGB1_Pos (16U) |
| #define | DAC_SWTRIGR_SWTRIGB1_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB1_Pos) |
| #define | DAC_SWTRIGR_SWTRIGB1 DAC_SWTRIGR_SWTRIGB1_Msk |
| #define | DAC_SWTRIGR_SWTRIGB2_Pos (17U) |
| #define | DAC_SWTRIGR_SWTRIGB2_Msk (0x1UL << DAC_SWTRIGR_SWTRIGB2_Pos) |
| #define | DAC_SWTRIGR_SWTRIGB2 DAC_SWTRIGR_SWTRIGB2_Msk |
| #define | DAC_DHR12R1_DACC1DHR_Pos (0U) |
| #define | DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) |
| #define | DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk |
| #define | DAC_DHR12R1_DACC1DHRB_Pos (16U) |
| #define | DAC_DHR12R1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHRB_Pos) |
| #define | DAC_DHR12R1_DACC1DHRB DAC_DHR12R1_DACC1DHRB_Msk |
| #define | DAC_DHR12L1_DACC1DHR_Pos (4U) |
| #define | DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) |
| #define | DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk |
| #define | DAC_DHR12L1_DACC1DHRB_Pos (20U) |
| #define | DAC_DHR12L1_DACC1DHRB_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHRB_Pos) |
| #define | DAC_DHR12L1_DACC1DHRB DAC_DHR12L1_DACC1DHRB_Msk |
| #define | DAC_DHR8R1_DACC1DHR_Pos (0U) |
| #define | DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) |
| #define | DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk |
| #define | DAC_DHR8R1_DACC1DHRB_Pos (8U) |
| #define | DAC_DHR8R1_DACC1DHRB_Msk (0xFFUL << DAC_DHR8R1_DACC1DHRB_Pos) |
| #define | DAC_DHR8R1_DACC1DHRB DAC_DHR8R1_DACC1DHRB_Msk |
| #define | DAC_DHR12R2_DACC2DHR_Pos (0U) |
| #define | DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) |
| #define | DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk |
| #define | DAC_DHR12R2_DACC2DHRB_Pos (16U) |
| #define | DAC_DHR12R2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHRB_Pos) |
| #define | DAC_DHR12R2_DACC2DHRB DAC_DHR12R2_DACC2DHRB_Msk |
| #define | DAC_DHR12L2_DACC2DHR_Pos (4U) |
| #define | DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) |
| #define | DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk |
| #define | DAC_DHR12L2_DACC2DHRB_Pos (20U) |
| #define | DAC_DHR12L2_DACC2DHRB_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHRB_Pos) |
| #define | DAC_DHR12L2_DACC2DHRB DAC_DHR12L2_DACC2DHRB_Msk |
| #define | DAC_DHR8R2_DACC2DHR_Pos (0U) |
| #define | DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) |
| #define | DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk |
| #define | DAC_DHR8R2_DACC2DHRB_Pos (8U) |
| #define | DAC_DHR8R2_DACC2DHRB_Msk (0xFFUL << DAC_DHR8R2_DACC2DHRB_Pos) |
| #define | DAC_DHR8R2_DACC2DHRB DAC_DHR8R2_DACC2DHRB_Msk |
| #define | DAC_DHR12RD_DACC1DHR_Pos (0U) |
| #define | DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) |
| #define | DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk |
| #define | DAC_DHR12RD_DACC2DHR_Pos (16U) |
| #define | DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) |
| #define | DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk |
| #define | DAC_DHR12LD_DACC1DHR_Pos (4U) |
| #define | DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) |
| #define | DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk |
| #define | DAC_DHR12LD_DACC2DHR_Pos (20U) |
| #define | DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) |
| #define | DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk |
| #define | DAC_DHR8RD_DACC1DHR_Pos (0U) |
| #define | DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) |
| #define | DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk |
| #define | DAC_DHR8RD_DACC2DHR_Pos (8U) |
| #define | DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) |
| #define | DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk |
| #define | DAC_DOR1_DACC1DOR_Pos (0U) |
| #define | DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) |
| #define | DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk |
| #define | DAC_DOR1_DACC1DORB_Pos (16U) |
| #define | DAC_DOR1_DACC1DORB_Msk (0xFFFUL << DAC_DOR1_DACC1DORB_Pos) |
| #define | DAC_DOR1_DACC1DORB DAC_DOR1_DACC1DORB_Msk |
| #define | DAC_DOR2_DACC2DOR_Pos (0U) |
| #define | DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) |
| #define | DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk |
| #define | DAC_DOR2_DACC2DORB_Pos (16U) |
| #define | DAC_DOR2_DACC2DORB_Msk (0xFFFUL << DAC_DOR2_DACC2DORB_Pos) |
| #define | DAC_DOR2_DACC2DORB DAC_DOR2_DACC2DORB_Msk |
| #define | DAC_SR_DAC1RDY_Pos (11U) |
| #define | DAC_SR_DAC1RDY_Msk (0x1UL << DAC_SR_DAC1RDY_Pos) |
| #define | DAC_SR_DAC1RDY DAC_SR_DAC1RDY_Msk |
| #define | DAC_SR_DORSTAT1_Pos (12U) |
| #define | DAC_SR_DORSTAT1_Msk (0x1UL << DAC_SR_DORSTAT1_Pos) |
| #define | DAC_SR_DORSTAT1 DAC_SR_DORSTAT1_Msk |
| #define | DAC_SR_DMAUDR1_Pos (13U) |
| #define | DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) |
| #define | DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk |
| #define | DAC_SR_CAL_FLAG1_Pos (14U) |
| #define | DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) |
| #define | DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk |
| #define | DAC_SR_BWST1_Pos (15U) |
| #define | DAC_SR_BWST1_Msk (0x1UL << DAC_SR_BWST1_Pos) |
| #define | DAC_SR_BWST1 DAC_SR_BWST1_Msk |
| #define | DAC_SR_DAC2RDY_Pos (27U) |
| #define | DAC_SR_DAC2RDY_Msk (0x1UL << DAC_SR_DAC2RDY_Pos) |
| #define | DAC_SR_DAC2RDY DAC_SR_DAC2RDY_Msk |
| #define | DAC_SR_DORSTAT2_Pos (28U) |
| #define | DAC_SR_DORSTAT2_Msk (0x1UL << DAC_SR_DORSTAT2_Pos) |
| #define | DAC_SR_DORSTAT2 DAC_SR_DORSTAT2_Msk |
| #define | DAC_SR_DMAUDR2_Pos (29U) |
| #define | DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) |
| #define | DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk |
| #define | DAC_SR_CAL_FLAG2_Pos (30U) |
| #define | DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) |
| #define | DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk |
| #define | DAC_SR_BWST2_Pos (31U) |
| #define | DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) |
| #define | DAC_SR_BWST2 DAC_SR_BWST2_Msk |
| #define | DAC_CCR_OTRIM1_Pos (0U) |
| #define | DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) |
| #define | DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk |
| #define | DAC_CCR_OTRIM2_Pos (16U) |
| #define | DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) |
| #define | DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk |
| #define | DAC_MCR_MODE1_Pos (0U) |
| #define | DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) |
| #define | DAC_MCR_MODE1 DAC_MCR_MODE1_Msk |
| #define | DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) |
| #define | DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) |
| #define | DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) |
| #define | DAC_MCR_DMADOUBLE1_Pos (8U) |
| #define | DAC_MCR_DMADOUBLE1_Msk (0x1UL << DAC_MCR_DMADOUBLE1_Pos) |
| #define | DAC_MCR_DMADOUBLE1 DAC_MCR_DMADOUBLE1_Msk |
| #define | DAC_MCR_SINFORMAT1_Pos (9U) |
| #define | DAC_MCR_SINFORMAT1_Msk (0x1UL << DAC_MCR_SINFORMAT1_Pos) |
| #define | DAC_MCR_SINFORMAT1 DAC_MCR_SINFORMAT1_Msk |
| #define | DAC_MCR_HFSEL_Pos (14U) |
| #define | DAC_MCR_HFSEL_Msk (0x3UL << DAC_MCR_HFSEL_Pos) |
| #define | DAC_MCR_HFSEL DAC_MCR_HFSEL_Msk |
| #define | DAC_MCR_HFSEL_0 (0x1UL << DAC_MCR_HFSEL_Pos) |
| #define | DAC_MCR_HFSEL_1 (0x2UL << DAC_MCR_HFSEL_Pos) |
| #define | DAC_MCR_MODE2_Pos (16U) |
| #define | DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) |
| #define | DAC_MCR_MODE2 DAC_MCR_MODE2_Msk |
| #define | DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) |
| #define | DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) |
| #define | DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) |
| #define | DAC_MCR_DMADOUBLE2_Pos (24U) |
| #define | DAC_MCR_DMADOUBLE2_Msk (0x1UL << DAC_MCR_DMADOUBLE2_Pos) |
| #define | DAC_MCR_DMADOUBLE2 DAC_MCR_DMADOUBLE2_Msk |
| #define | DAC_MCR_SINFORMAT2_Pos (25U) |
| #define | DAC_MCR_SINFORMAT2_Msk (0x1UL << DAC_MCR_SINFORMAT2_Pos) |
| #define | DAC_MCR_SINFORMAT2 DAC_MCR_SINFORMAT2_Msk |
| #define | DAC_SHSR1_TSAMPLE1_Pos (0U) |
| #define | DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) |
| #define | DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk |
| #define | DAC_SHSR2_TSAMPLE2_Pos (0U) |
| #define | DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) |
| #define | DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk |
| #define | DAC_SHHR_THOLD1_Pos (0U) |
| #define | DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) |
| #define | DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk |
| #define | DAC_SHHR_THOLD2_Pos (16U) |
| #define | DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) |
| #define | DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk |
| #define | DAC_SHRR_TREFRESH1_Pos (0U) |
| #define | DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) |
| #define | DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk |
| #define | DAC_SHRR_TREFRESH2_Pos (16U) |
| #define | DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) |
| #define | DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk |
| #define | DAC_AUTOCR_AUTOMODE_Pos (22U) |
| #define | DAC_AUTOCR_AUTOMODE_Msk (0x1UL << DAC_AUTOCR_AUTOMODE_Pos) |
| #define | DAC_AUTOCR_AUTOMODE DAC_AUTOCR_AUTOMODE_Msk |
| #define | AES_CR_EN_Pos (0U) |
| #define | AES_CR_EN_Msk (0x1UL << AES_CR_EN_Pos) |
| #define | AES_CR_EN AES_CR_EN_Msk |
| #define | AES_CR_DATATYPE_Pos (1U) |
| #define | AES_CR_DATATYPE_Msk (0x3UL << AES_CR_DATATYPE_Pos) |
| #define | AES_CR_DATATYPE AES_CR_DATATYPE_Msk |
| #define | AES_CR_DATATYPE_0 (0x1UL << AES_CR_DATATYPE_Pos) |
| #define | AES_CR_DATATYPE_1 (0x2UL << AES_CR_DATATYPE_Pos) |
| #define | AES_CR_MODE_Pos (3U) |
| #define | AES_CR_MODE_Msk (0x3UL << AES_CR_MODE_Pos) |
| #define | AES_CR_MODE AES_CR_MODE_Msk |
| #define | AES_CR_MODE_0 (0x1UL << AES_CR_MODE_Pos) |
| #define | AES_CR_MODE_1 (0x2UL << AES_CR_MODE_Pos) |
| #define | AES_CR_CHMOD_Pos (5U) |
| #define | AES_CR_CHMOD_Msk (0x803UL << AES_CR_CHMOD_Pos) |
| #define | AES_CR_CHMOD AES_CR_CHMOD_Msk |
| #define | AES_CR_CHMOD_0 (0x001UL << AES_CR_CHMOD_Pos) |
| #define | AES_CR_CHMOD_1 (0x002UL << AES_CR_CHMOD_Pos) |
| #define | AES_CR_CHMOD_2 (0x800UL << AES_CR_CHMOD_Pos) |
| #define | AES_CR_DMAINEN_Pos (11U) |
| #define | AES_CR_DMAINEN_Msk (0x1UL << AES_CR_DMAINEN_Pos) |
| #define | AES_CR_DMAINEN AES_CR_DMAINEN_Msk |
| #define | AES_CR_DMAOUTEN_Pos (12U) |
| #define | AES_CR_DMAOUTEN_Msk (0x1UL << AES_CR_DMAOUTEN_Pos) |
| #define | AES_CR_DMAOUTEN AES_CR_DMAOUTEN_Msk |
| #define | AES_CR_GCMPH_Pos (13U) |
| #define | AES_CR_GCMPH_Msk (0x3UL << AES_CR_GCMPH_Pos) |
| #define | AES_CR_GCMPH AES_CR_GCMPH_Msk |
| #define | AES_CR_GCMPH_0 (0x1UL << AES_CR_GCMPH_Pos) |
| #define | AES_CR_GCMPH_1 (0x2UL << AES_CR_GCMPH_Pos) |
| #define | AES_CR_KEYSIZE_Pos (18U) |
| #define | AES_CR_KEYSIZE_Msk (0x1UL << AES_CR_KEYSIZE_Pos) |
| #define | AES_CR_KEYSIZE AES_CR_KEYSIZE_Msk |
| #define | AES_CR_KEYPROT_Pos (19U) |
| #define | AES_CR_KEYPROT_Msk (0x1UL << AES_CR_KEYPROT_Pos) |
| #define | AES_CR_KEYPROT AES_CR_KEYPROT_Msk |
| #define | AES_CR_NPBLB_Pos (20U) |
| #define | AES_CR_NPBLB_Msk (0xFUL << AES_CR_NPBLB_Pos) |
| #define | AES_CR_NPBLB AES_CR_NPBLB_Msk |
| #define | AES_CR_NPBLB_0 (0x1UL << AES_CR_NPBLB_Pos) |
| #define | AES_CR_NPBLB_1 (0x2UL << AES_CR_NPBLB_Pos) |
| #define | AES_CR_NPBLB_2 (0x4UL << AES_CR_NPBLB_Pos) |
| #define | AES_CR_NPBLB_3 (0x8UL << AES_CR_NPBLB_Pos) |
| #define | AES_CR_KMOD_Pos (24U) |
| #define | AES_CR_KMOD_Msk (0x3UL << AES_CR_KMOD_Pos) |
| #define | AES_CR_KMOD AES_CR_KMOD_Msk |
| #define | AES_CR_KMOD_0 (0x1UL << AES_CR_KMOD_Pos) |
| #define | AES_CR_KMOD_1 (0x2UL << AES_CR_KMOD_Pos) |
| #define | AES_CR_KSHAREID_Pos (26U) |
| #define | AES_CR_KSHAREID_Msk (0x3UL << AES_CR_KSHAREID_Pos) |
| #define | AES_CR_KSHAREID AES_CR_KSHAREID_Msk |
| #define | AES_CR_KEYSEL_Pos (28U) |
| #define | AES_CR_KEYSEL_Msk (0x7UL << AES_CR_KEYSEL_Pos) |
| #define | AES_CR_KEYSEL AES_CR_KEYSEL_Msk |
| #define | AES_CR_KEYSEL_0 (0x1UL << AES_CR_KEYSEL_Pos) |
| #define | AES_CR_KEYSEL_1 (0x2UL << AES_CR_KEYSEL_Pos) |
| #define | AES_CR_KEYSEL_2 (0x4UL << AES_CR_KEYSEL_Pos) |
| #define | AES_CR_IPRST_Pos (31U) |
| #define | AES_CR_IPRST_Msk (0x1UL << AES_CR_IPRST_Pos) |
| #define | AES_CR_IPRST AES_CR_IPRST_Msk |
| #define | AES_SR_CCF_Pos (0U) |
| #define | AES_SR_CCF_Msk (0x1UL << AES_SR_CCF_Pos) |
| #define | AES_SR_CCF AES_SR_CCF_Msk |
| #define | AES_SR_RDERR_Pos (1U) |
| #define | AES_SR_RDERR_Msk (0x1UL << AES_SR_RDERR_Pos) |
| #define | AES_SR_RDERR AES_SR_RDERR_Msk |
| #define | AES_SR_WRERR_Pos (2U) |
| #define | AES_SR_WRERR_Msk (0x1UL << AES_SR_WRERR_Pos) |
| #define | AES_SR_WRERR AES_SR_WRERR_Msk |
| #define | AES_SR_BUSY_Pos (3U) |
| #define | AES_SR_BUSY_Msk (0x1UL << AES_SR_BUSY_Pos) |
| #define | AES_SR_BUSY AES_SR_BUSY_Msk |
| #define | AES_SR_KEYVALID_Pos (7U) |
| #define | AES_SR_KEYVALID_Msk (0x1UL << AES_SR_KEYVALID_Pos) |
| #define | AES_SR_KEYVALID AES_SR_KEYVALID_Msk |
| #define | AES_DINR_Pos (0U) |
| #define | AES_DINR_Msk (0xFFFFFFFFUL << AES_DINR_Pos) |
| #define | AES_DINR AES_DINR_Msk |
| #define | AES_DOUTR_Pos (0U) |
| #define | AES_DOUTR_Msk (0xFFFFFFFFUL << AES_DOUTR_Pos) |
| #define | AES_DOUTR AES_DOUTR_Msk |
| #define | AES_KEYR0_Pos (0U) |
| #define | AES_KEYR0_Msk (0xFFFFFFFFUL << AES_KEYR0_Pos) |
| #define | AES_KEYR0 AES_KEYR0_Msk |
| #define | AES_KEYR1_Pos (0U) |
| #define | AES_KEYR1_Msk (0xFFFFFFFFUL << AES_KEYR1_Pos) |
| #define | AES_KEYR1 AES_KEYR1_Msk |
| #define | AES_KEYR2_Pos (0U) |
| #define | AES_KEYR2_Msk (0xFFFFFFFFUL << AES_KEYR2_Pos) |
| #define | AES_KEYR2 AES_KEYR2_Msk |
| #define | AES_KEYR3_Pos (0U) |
| #define | AES_KEYR3_Msk (0xFFFFFFFFUL << AES_KEYR3_Pos) |
| #define | AES_KEYR3 AES_KEYR3_Msk |
| #define | AES_KEYR4_Pos (0U) |
| #define | AES_KEYR4_Msk (0xFFFFFFFFUL << AES_KEYR4_Pos) |
| #define | AES_KEYR4 AES_KEYR4_Msk |
| #define | AES_KEYR5_Pos (0U) |
| #define | AES_KEYR5_Msk (0xFFFFFFFFUL << AES_KEYR5_Pos) |
| #define | AES_KEYR5 AES_KEYR5_Msk |
| #define | AES_KEYR6_Pos (0U) |
| #define | AES_KEYR6_Msk (0xFFFFFFFFUL << AES_KEYR6_Pos) |
| #define | AES_KEYR6 AES_KEYR6_Msk |
| #define | AES_KEYR7_Pos (0U) |
| #define | AES_KEYR7_Msk (0xFFFFFFFFUL << AES_KEYR7_Pos) |
| #define | AES_KEYR7 AES_KEYR7_Msk |
| #define | AES_IVR0_Pos (0U) |
| #define | AES_IVR0_Msk (0xFFFFFFFFUL << AES_IVR0_Pos) |
| #define | AES_IVR0 AES_IVR0_Msk |
| #define | AES_IVR1_Pos (0U) |
| #define | AES_IVR1_Msk (0xFFFFFFFFUL << AES_IVR1_Pos) |
| #define | AES_IVR1 AES_IVR1_Msk |
| #define | AES_IVR2_Pos (0U) |
| #define | AES_IVR2_Msk (0xFFFFFFFFUL << AES_IVR2_Pos) |
| #define | AES_IVR2 AES_IVR2_Msk |
| #define | AES_IVR3_Pos (0U) |
| #define | AES_IVR3_Msk (0xFFFFFFFFUL << AES_IVR3_Pos) |
| #define | AES_IVR3 AES_IVR3_Msk |
| #define | AES_SUSP0R_Pos (0U) |
| #define | AES_SUSP0R_Msk (0xFFFFFFFFUL << AES_SUSP0R_Pos) |
| #define | AES_SUSP0R AES_SUSP0R_Msk |
| #define | AES_SUSP1R_Pos (0U) |
| #define | AES_SUSP1R_Msk (0xFFFFFFFFUL << AES_SUSP1R_Pos) |
| #define | AES_SUSP1R AES_SUSP1R_Msk |
| #define | AES_SUSP2R_Pos (0U) |
| #define | AES_SUSP2R_Msk (0xFFFFFFFFUL << AES_SUSP2R_Pos) |
| #define | AES_SUSP2R AES_SUSP2R_Msk |
| #define | AES_SUSP3R_Pos (0U) |
| #define | AES_SUSP3R_Msk (0xFFFFFFFFUL << AES_SUSP3R_Pos) |
| #define | AES_SUSP3R AES_SUSP3R_Msk |
| #define | AES_SUSP4R_Pos (0U) |
| #define | AES_SUSP4R_Msk (0xFFFFFFFFUL << AES_SUSP4R_Pos) |
| #define | AES_SUSP4R AES_SUSP4R_Msk |
| #define | AES_SUSP5R_Pos (0U) |
| #define | AES_SUSP5R_Msk (0xFFFFFFFFUL << AES_SUSP5R_Pos) |
| #define | AES_SUSP5R AES_SUSP5R_Msk |
| #define | AES_SUSP6R_Pos (0U) |
| #define | AES_SUSP6R_Msk (0xFFFFFFFFUL << AES_SUSP6R_Pos) |
| #define | AES_SUSP6R AES_SUSP6R_Msk |
| #define | AES_SUSP7R_Pos (0U) |
| #define | AES_SUSP7R_Msk (0xFFFFFFFFUL << AES_SUSP7R_Pos) |
| #define | AES_SUSP7R AES_SUSP7R_Msk |
| #define | AES_IER_CCFIE_Pos (0U) |
| #define | AES_IER_CCFIE_Msk (0x1UL << AES_IER_CCFIE_Pos) |
| #define | AES_IER_CCFIE AES_IER_CCFIE_Msk |
| #define | AES_IER_RWEIE_Pos (1U) |
| #define | AES_IER_RWEIE_Msk (0x1UL << AES_IER_RWEIE_Pos) |
| #define | AES_IER_RWEIE AES_IER_RWEIE_Msk |
| #define | AES_IER_KEIE_Pos (2U) |
| #define | AES_IER_KEIE_Msk (0x1UL << AES_IER_KEIE_Pos) |
| #define | AES_IER_KEIE AES_IER_KEIE_Msk |
| #define | AES_IER_RNGEIE_Pos (3U) |
| #define | AES_IER_RNGEIE_Msk (0x1UL << AES_IER_RNGEIE_Pos) |
| #define | AES_IER_RNGEIE AES_IER_RNGEIE_Msk |
| #define | AES_ISR_CCF_Pos (0U) |
| #define | AES_ISR_CCF_Msk (0x1UL << AES_ISR_CCF_Pos) |
| #define | AES_ISR_CCF AES_ISR_CCF_Msk |
| #define | AES_ISR_RWEIF_Pos (1U) |
| #define | AES_ISR_RWEIF_Msk (0x1UL << AES_ISR_RWEIF_Pos) |
| #define | AES_ISR_RWEIF AES_ISR_RWEIF_Msk |
| #define | AES_ISR_KEIF_Pos (2U) |
| #define | AES_ISR_KEIF_Msk (0x1UL << AES_ISR_KEIF_Pos) |
| #define | AES_ISR_KEIF AES_ISR_KEIF_Msk |
| #define | AES_ISR_RNGEIF_Pos (3U) |
| #define | AES_ISR_RNGEIF_Msk (0x1UL << AES_ISR_RNGEIF_Pos) |
| #define | AES_ISR_RNGEIF AES_ISR_RNGEIF_Msk |
| #define | AES_ICR_CCF_Pos (0U) |
| #define | AES_ICR_CCF_Msk (0x1UL << AES_ICR_CCF_Pos) |
| #define | AES_ICR_CCF AES_ICR_CCF_Msk |
| #define | AES_ICR_RWEIF_Pos (1U) |
| #define | AES_ICR_RWEIF_Msk (0x1UL << AES_ICR_RWEIF_Pos) |
| #define | AES_ICR_RWEIF AES_ICR_RWEIF_Msk |
| #define | AES_ICR_KEIF_Pos (2U) |
| #define | AES_ICR_KEIF_Msk (0x1UL << AES_ICR_KEIF_Pos) |
| #define | AES_ICR_KEIF AES_ICR_KEIF_Msk |
| #define | AES_ICR_RNGEIF_Pos (3U) |
| #define | AES_ICR_RNGEIF_Msk (0x1UL << AES_ICR_RNGEIF_Pos) |
| #define | AES_ICR_RNGEIF AES_ICR_RNGEIF_Msk |
| #define | HASH_CR_INIT_Pos (2U) |
| #define | HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) |
| #define | HASH_CR_INIT HASH_CR_INIT_Msk |
| #define | HASH_CR_DMAE_Pos (3U) |
| #define | HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) |
| #define | HASH_CR_DMAE HASH_CR_DMAE_Msk |
| #define | HASH_CR_DATATYPE_Pos (4U) |
| #define | HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) |
| #define | HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk |
| #define | HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) |
| #define | HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) |
| #define | HASH_CR_MODE_Pos (6U) |
| #define | HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) |
| #define | HASH_CR_MODE HASH_CR_MODE_Msk |
| #define | HASH_CR_NBW_Pos (8U) |
| #define | HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) |
| #define | HASH_CR_NBW HASH_CR_NBW_Msk |
| #define | HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) |
| #define | HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) |
| #define | HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) |
| #define | HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) |
| #define | HASH_CR_DINNE_Pos (12U) |
| #define | HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) |
| #define | HASH_CR_DINNE HASH_CR_DINNE_Msk |
| #define | HASH_CR_MDMAT_Pos (13U) |
| #define | HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) |
| #define | HASH_CR_MDMAT HASH_CR_MDMAT_Msk |
| #define | HASH_CR_LKEY_Pos (16U) |
| #define | HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) |
| #define | HASH_CR_LKEY HASH_CR_LKEY_Msk |
| #define | HASH_CR_ALGO_Pos (17U) |
| #define | HASH_CR_ALGO_Msk (0x3UL << HASH_CR_ALGO_Pos) |
| #define | HASH_CR_ALGO HASH_CR_ALGO_Msk |
| #define | HASH_CR_ALGO_0 (0x1UL << HASH_CR_ALGO_Pos) |
| #define | HASH_CR_ALGO_1 (0x2UL << HASH_CR_ALGO_Pos) |
| #define | HASH_STR_NBLW_Pos (0U) |
| #define | HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) |
| #define | HASH_STR_NBLW HASH_STR_NBLW_Msk |
| #define | HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos) |
| #define | HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos) |
| #define | HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos) |
| #define | HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos) |
| #define | HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) |
| #define | HASH_STR_DCAL_Pos (8U) |
| #define | HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) |
| #define | HASH_STR_DCAL HASH_STR_DCAL_Msk |
| #define | HASH_IMR_DINIE_Pos (0U) |
| #define | HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) |
| #define | HASH_IMR_DINIE HASH_IMR_DINIE_Msk |
| #define | HASH_IMR_DCIE_Pos (1U) |
| #define | HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) |
| #define | HASH_IMR_DCIE HASH_IMR_DCIE_Msk |
| #define | HASH_SR_DINIS_Pos (0U) |
| #define | HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) |
| #define | HASH_SR_DINIS HASH_SR_DINIS_Msk |
| #define | HASH_SR_DCIS_Pos (1U) |
| #define | HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) |
| #define | HASH_SR_DCIS HASH_SR_DCIS_Msk |
| #define | HASH_SR_DMAS_Pos (2U) |
| #define | HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) |
| #define | HASH_SR_DMAS HASH_SR_DMAS_Msk |
| #define | HASH_SR_BUSY_Pos (3U) |
| #define | HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) |
| #define | HASH_SR_BUSY HASH_SR_BUSY_Msk |
| #define | HASH_SR_NBWE_Pos (16U) |
| #define | HASH_SR_NBWE_Msk (0xFUL << HASH_SR_NBWE_Pos) |
| #define | HASH_SR_NBWE HASH_SR_NBWE_Msk |
| #define | HASH_SR_NBWE_0 (0x01UL << HASH_SR_NBWE_Pos) |
| #define | HASH_SR_NBWE_1 (0x02UL << HASH_SR_NBWE_Pos) |
| #define | HASH_SR_NBWE_2 (0x04UL << HASH_SR_NBWE_Pos) |
| #define | HASH_SR_NBWE_3 (0x08UL << HASH_SR_NBWE_Pos) |
| #define | HASH_SR_DINNE_Pos (15U) |
| #define | HASH_SR_DINNE_Msk (0x1UL << HASH_SR_DINNE_Pos) |
| #define | HASH_SR_DINNE HASH_SR_DINNE_Msk |
| #define | HASH_SR_NBWP_Pos (9U) |
| #define | HASH_SR_NBWP_Msk (0xFUL << HASH_SR_NBWP_Pos) |
| #define | HASH_SR_NBWP HASH_SR_NBWP_Msk |
| #define | HASH_SR_NBWP_0 (0x01UL << HASH_SR_NBWP_Pos) |
| #define | HASH_SR_NBWP_1 (0x02UL << HASH_SR_NBWP_Pos) |
| #define | HASH_SR_NBWP_2 (0x04UL << HASH_SR_NBWP_Pos) |
| #define | HASH_SR_NBWP_3 (0x08UL << HASH_SR_NBWP_Pos) |
| #define | DBGMCU_IDCODE_DEV_ID_Pos (0U) |
| #define | DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) |
| #define | DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk |
| #define | DBGMCU_IDCODE_REV_ID_Pos (16U) |
| #define | DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) |
| #define | DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk |
| #define | DBGMCU_CR_DBG_STOP_Pos (1U) |
| #define | DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) |
| #define | DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk |
| #define | DBGMCU_CR_DBG_STANDBY_Pos (2U) |
| #define | DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) |
| #define | DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk |
| #define | DBGMCU_CR_TRACE_IOEN_Pos (4U) |
| #define | DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) |
| #define | DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk |
| #define | DBGMCU_CR_TRACE_CLKEN_Pos (5U) |
| #define | DBGMCU_CR_TRACE_CLKEN_Msk (0x1UL << DBGMCU_CR_TRACE_CLKEN_Pos) |
| #define | DBGMCU_CR_TRACE_CLKEN DBGMCU_CR_TRACE_CLKEN_Msk |
| #define | DBGMCU_CR_TRACE_MODE_Pos (6U) |
| #define | DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) |
| #define | DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk |
| #define | DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) |
| #define | DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) |
| #define | DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos (0U) |
| #define | DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM2_STOP_Pos) |
| #define | DBGMCU_APB1FZR1_DBG_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP_Msk |
| #define | DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos (1U) |
| #define | DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM3_STOP_Pos) |
| #define | DBGMCU_APB1FZR1_DBG_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP_Msk |
| #define | DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos (2U) |
| #define | DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM4_STOP_Pos) |
| #define | DBGMCU_APB1FZR1_DBG_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP_Msk |
| #define | DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos (3U) |
| #define | DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM5_STOP_Pos) |
| #define | DBGMCU_APB1FZR1_DBG_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP_Msk |
| #define | DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos (4U) |
| #define | DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM6_STOP_Pos) |
| #define | DBGMCU_APB1FZR1_DBG_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP_Msk |
| #define | DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos (5U) |
| #define | DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_TIM7_STOP_Pos) |
| #define | DBGMCU_APB1FZR1_DBG_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP_Msk |
| #define | DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos (11U) |
| #define | DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_WWDG_STOP_Pos) |
| #define | DBGMCU_APB1FZR1_DBG_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP_Msk |
| #define | DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos (12U) |
| #define | DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_IWDG_STOP_Pos) |
| #define | DBGMCU_APB1FZR1_DBG_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP_Msk |
| #define | DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos (21U) |
| #define | DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C1_STOP_Pos) |
| #define | DBGMCU_APB1FZR1_DBG_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP_Msk |
| #define | DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos (22U) |
| #define | DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk (0x1UL << DBGMCU_APB1FZR1_DBG_I2C2_STOP_Pos) |
| #define | DBGMCU_APB1FZR1_DBG_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP_Msk |
| #define | DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos (1U) |
| #define | DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_I2C4_STOP_Pos) |
| #define | DBGMCU_APB1FZR2_DBG_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP_Msk |
| #define | DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos (5U) |
| #define | DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Pos) |
| #define | DBGMCU_APB1FZR2_DBG_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP_Msk |
| #define | DBGMCU_APB1FZR2_DBG_I2C5_STOP_Pos (6U) |
| #define | DBGMCU_APB1FZR2_DBG_I2C5_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_I2C5_STOP_Pos) |
| #define | DBGMCU_APB1FZR2_DBG_I2C5_STOP DBGMCU_APB1FZR2_DBG_I2C5_STOP_Msk |
| #define | DBGMCU_APB1FZR2_DBG_I2C6_STOP_Pos (7U) |
| #define | DBGMCU_APB1FZR2_DBG_I2C6_STOP_Msk (0x1UL << DBGMCU_APB1FZR2_DBG_I2C6_STOP_Pos) |
| #define | DBGMCU_APB1FZR2_DBG_I2C6_STOP DBGMCU_APB1FZR2_DBG_I2C6_STOP_Msk |
| #define | DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos (11U) |
| #define | DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM1_STOP_Pos) |
| #define | DBGMCU_APB2FZR_DBG_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP_Msk |
| #define | DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos (13U) |
| #define | DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM8_STOP_Pos) |
| #define | DBGMCU_APB2FZR_DBG_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP_Msk |
| #define | DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos (16U) |
| #define | DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM15_STOP_Pos) |
| #define | DBGMCU_APB2FZR_DBG_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP_Msk |
| #define | DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos (17U) |
| #define | DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM16_STOP_Pos) |
| #define | DBGMCU_APB2FZR_DBG_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP_Msk |
| #define | DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos (18U) |
| #define | DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB2FZR_DBG_TIM17_STOP_Pos) |
| #define | DBGMCU_APB2FZR_DBG_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP_Msk |
| #define | DBGMCU_APB3FZR_DBG_I2C3_STOP_Pos (10U) |
| #define | DBGMCU_APB3FZR_DBG_I2C3_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_I2C3_STOP_Pos) |
| #define | DBGMCU_APB3FZR_DBG_I2C3_STOP DBGMCU_APB3FZR_DBG_I2C3_STOP_Msk |
| #define | DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos (17U) |
| #define | DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Pos) |
| #define | DBGMCU_APB3FZR_DBG_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP_Msk |
| #define | DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Pos (18U) |
| #define | DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Pos) |
| #define | DBGMCU_APB3FZR_DBG_LPTIM3_STOP DBGMCU_APB3FZR_DBG_LPTIM3_STOP_Msk |
| #define | DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Pos (19U) |
| #define | DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Pos) |
| #define | DBGMCU_APB3FZR_DBG_LPTIM4_STOP DBGMCU_APB3FZR_DBG_LPTIM4_STOP_Msk |
| #define | DBGMCU_APB3FZR_DBG_RTC_STOP_Pos (30U) |
| #define | DBGMCU_APB3FZR_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB3FZR_DBG_RTC_STOP_Pos) |
| #define | DBGMCU_APB3FZR_DBG_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA0_STOP_Pos (0U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA0_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA0_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA0_STOP DBGMCU_AHB1FZR_DBG_GPDMA0_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA1_STOP_Pos (1U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA1_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA1_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA1_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA2_STOP_Pos (2U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA2_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA2_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA2_STOP DBGMCU_AHB1FZR_DBG_GPDMA2_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA3_STOP_Pos (3U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA3_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA3_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA3_STOP DBGMCU_AHB1FZR_DBG_GPDMA3_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA4_STOP_Pos (4U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA4_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA4_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA4_STOP DBGMCU_AHB1FZR_DBG_GPDMA4_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA5_STOP_Pos (5U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA5_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA5_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA5_STOP DBGMCU_AHB1FZR_DBG_GPDMA5_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA6_STOP_Pos (6U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA6_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA6_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA6_STOP DBGMCU_AHB1FZR_DBG_GPDMA6_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA7_STOP_Pos (7U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA7_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA7_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA7_STOP DBGMCU_AHB1FZR_DBG_GPDMA7_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA8_STOP_Pos (8U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA8_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA8_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA8_STOP DBGMCU_AHB1FZR_DBG_GPDMA8_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA9_STOP_Pos (9U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA9_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA9_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA9_STOP DBGMCU_AHB1FZR_DBG_GPDMA9_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA10_STOP_Pos (10U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA10_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA10_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA10_STOP DBGMCU_AHB1FZR_DBG_GPDMA10_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA11_STOP_Pos (11U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA11_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA11_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA11_STOP DBGMCU_AHB1FZR_DBG_GPDMA11_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA12_STOP_Pos (12U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA12_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA12_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA12_STOP DBGMCU_AHB1FZR_DBG_GPDMA12_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA13_STOP_Pos (13U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA13_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA13_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA13_STOP DBGMCU_AHB1FZR_DBG_GPDMA13_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA14_STOP_Pos (14U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA14_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA14_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA14_STOP DBGMCU_AHB1FZR_DBG_GPDMA14_STOP_Msk |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA15_STOP_Pos (15U) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA15_STOP_Msk (0x1UL << DBGMCU_AHB1FZR_DBG_GPDMA15_STOP_Pos) |
| #define | DBGMCU_AHB1FZR_DBG_GPDMA15_STOP DBGMCU_AHB1FZR_DBG_GPDMA15_STOP_Msk |
| #define | DBGMCU_AHB3FZR_DBG_LPDMA0_STOP_Pos (0U) |
| #define | DBGMCU_AHB3FZR_DBG_LPDMA0_STOP_Msk (0x1UL << DBGMCU_AHB3FZR_DBG_LPDMA0_STOP_Pos) |
| #define | DBGMCU_AHB3FZR_DBG_LPDMA0_STOP DBGMCU_AHB3FZR_DBG_LPDMA0_STOP_Msk |
| #define | DBGMCU_AHB3FZR_DBG_LPDMA1_STOP_Pos (1U) |
| #define | DBGMCU_AHB3FZR_DBG_LPDMA1_STOP_Msk (0x1UL << DBGMCU_AHB3FZR_DBG_LPDMA1_STOP_Pos) |
| #define | DBGMCU_AHB3FZR_DBG_LPDMA1_STOP DBGMCU_AHB3FZR_DBG_LPDMA1_STOP_Msk |
| #define | DBGMCU_AHB3FZR_DBG_LPDMA2_STOP_Pos (2U) |
| #define | DBGMCU_AHB3FZR_DBG_LPDMA2_STOP_Msk (0x1UL << DBGMCU_AHB3FZR_DBG_LPDMA2_STOP_Pos) |
| #define | DBGMCU_AHB3FZR_DBG_LPDMA2_STOP DBGMCU_AHB3FZR_DBG_LPDMA2_STOP_Msk |
| #define | DBGMCU_AHB3FZR_DBG_LPDMA3_STOP_Pos (3U) |
| #define | DBGMCU_AHB3FZR_DBG_LPDMA3_STOP_Msk (0x1UL << DBGMCU_AHB3FZR_DBG_LPDMA3_STOP_Pos) |
| #define | DBGMCU_AHB3FZR_DBG_LPDMA3_STOP DBGMCU_AHB3FZR_DBG_LPDMA3_STOP_Msk |
| #define | DCMI_CR_CAPTURE_Pos (0U) |
| #define | DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) |
| #define | DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk |
| #define | DCMI_CR_CM_Pos (1U) |
| #define | DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) |
| #define | DCMI_CR_CM DCMI_CR_CM_Msk |
| #define | DCMI_CR_CROP_Pos (2U) |
| #define | DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) |
| #define | DCMI_CR_CROP DCMI_CR_CROP_Msk |
| #define | DCMI_CR_JPEG_Pos (3U) |
| #define | DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) |
| #define | DCMI_CR_JPEG DCMI_CR_JPEG_Msk |
| #define | DCMI_CR_ESS_Pos (4U) |
| #define | DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) |
| #define | DCMI_CR_ESS DCMI_CR_ESS_Msk |
| #define | DCMI_CR_PCKPOL_Pos (5U) |
| #define | DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) |
| #define | DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk |
| #define | DCMI_CR_HSPOL_Pos (6U) |
| #define | DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) |
| #define | DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk |
| #define | DCMI_CR_VSPOL_Pos (7U) |
| #define | DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) |
| #define | DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk |
| #define | DCMI_CR_FCRC_Pos (8U) |
| #define | DCMI_CR_FCRC_Msk (0x3UL << DCMI_CR_FCRC_Pos) |
| #define | DCMI_CR_FCRC DCMI_CR_FCRC_Msk |
| #define | DCMI_CR_FCRC_0 (0x1UL << DCMI_CR_FCRC_Pos) |
| #define | DCMI_CR_FCRC_1 (0x2UL << DCMI_CR_FCRC_Pos) |
| #define | DCMI_CR_EDM_Pos (10U) |
| #define | DCMI_CR_EDM_Msk (0x3UL << DCMI_CR_EDM_Pos) |
| #define | DCMI_CR_EDM DCMI_CR_EDM_Msk |
| #define | DCMI_CR_EDM_0 (0x1UL << DCMI_CR_EDM_Pos) |
| #define | DCMI_CR_EDM_1 (0x2UL << DCMI_CR_EDM_Pos) |
| #define | DCMI_CR_ENABLE_Pos (14U) |
| #define | DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) |
| #define | DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk |
| #define | DCMI_CR_BSM_Pos (16U) |
| #define | DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) |
| #define | DCMI_CR_BSM DCMI_CR_BSM_Msk |
| #define | DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) |
| #define | DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) |
| #define | DCMI_CR_OEBS_Pos (18U) |
| #define | DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) |
| #define | DCMI_CR_OEBS DCMI_CR_OEBS_Msk |
| #define | DCMI_CR_LSM_Pos (19U) |
| #define | DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) |
| #define | DCMI_CR_LSM DCMI_CR_LSM_Msk |
| #define | DCMI_CR_OELS_Pos (20U) |
| #define | DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) |
| #define | DCMI_CR_OELS DCMI_CR_OELS_Msk |
| #define | DCMI_CR_PSDM_Pos (31U) |
| #define | DCMI_CR_PSDM_Msk (0x0UL << DCMI_CR_PSDM_Pos) |
| #define | DCMI_CR_PSDM DCMI_CR_PSDM_Msk /*PSDM: Parallel Synchronous raw Data Mode (PSDM = 0)*/ |
| #define | DCMI_SR_HSYNC_Pos (0U) |
| #define | DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) |
| #define | DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk |
| #define | DCMI_SR_VSYNC_Pos (1U) |
| #define | DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) |
| #define | DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk |
| #define | DCMI_SR_FNE_Pos (2U) |
| #define | DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) |
| #define | DCMI_SR_FNE DCMI_SR_FNE_Msk |
| #define | DCMI_RIS_FRAME_RIS_Pos (0U) |
| #define | DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) |
| #define | DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk |
| #define | DCMI_RIS_OVR_RIS_Pos (1U) |
| #define | DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) |
| #define | DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk |
| #define | DCMI_RIS_ERR_RIS_Pos (2U) |
| #define | DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) |
| #define | DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk |
| #define | DCMI_RIS_VSYNC_RIS_Pos (3U) |
| #define | DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) |
| #define | DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk |
| #define | DCMI_RIS_LINE_RIS_Pos (4U) |
| #define | DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) |
| #define | DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk |
| #define | DCMI_IER_FRAME_IE_Pos (0U) |
| #define | DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) |
| #define | DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk |
| #define | DCMI_IER_OVR_IE_Pos (1U) |
| #define | DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) |
| #define | DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk |
| #define | DCMI_IER_ERR_IE_Pos (2U) |
| #define | DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) |
| #define | DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk |
| #define | DCMI_IER_VSYNC_IE_Pos (3U) |
| #define | DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) |
| #define | DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk |
| #define | DCMI_IER_LINE_IE_Pos (4U) |
| #define | DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) |
| #define | DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk |
| #define | DCMI_MIS_FRAME_MIS_Pos (0U) |
| #define | DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) |
| #define | DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk |
| #define | DCMI_MIS_OVR_MIS_Pos (1U) |
| #define | DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) |
| #define | DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk |
| #define | DCMI_MIS_ERR_MIS_Pos (2U) |
| #define | DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) |
| #define | DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk |
| #define | DCMI_MIS_VSYNC_MIS_Pos (3U) |
| #define | DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) |
| #define | DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk |
| #define | DCMI_MIS_LINE_MIS_Pos (4U) |
| #define | DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) |
| #define | DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk |
| #define | DCMI_ICR_FRAME_ISC_Pos (0U) |
| #define | DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) |
| #define | DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk |
| #define | DCMI_ICR_OVR_ISC_Pos (1U) |
| #define | DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) |
| #define | DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk |
| #define | DCMI_ICR_ERR_ISC_Pos (2U) |
| #define | DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) |
| #define | DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk |
| #define | DCMI_ICR_VSYNC_ISC_Pos (3U) |
| #define | DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) |
| #define | DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk |
| #define | DCMI_ICR_LINE_ISC_Pos (4U) |
| #define | DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) |
| #define | DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk |
| #define | DCMI_ESCR_FSC_Pos (0U) |
| #define | DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) |
| #define | DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk |
| #define | DCMI_ESCR_LSC_Pos (8U) |
| #define | DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) |
| #define | DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk |
| #define | DCMI_ESCR_LEC_Pos (16U) |
| #define | DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) |
| #define | DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk |
| #define | DCMI_ESCR_FEC_Pos (24U) |
| #define | DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) |
| #define | DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk |
| #define | DCMI_ESUR_FSU_Pos (0U) |
| #define | DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) |
| #define | DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk |
| #define | DCMI_ESUR_LSU_Pos (8U) |
| #define | DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) |
| #define | DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk |
| #define | DCMI_ESUR_LEU_Pos (16U) |
| #define | DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) |
| #define | DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk |
| #define | DCMI_ESUR_FEU_Pos (24U) |
| #define | DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) |
| #define | DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk |
| #define | DCMI_CWSTRT_HOFFCNT_Pos (0U) |
| #define | DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) |
| #define | DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk |
| #define | DCMI_CWSTRT_VST_Pos (16U) |
| #define | DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) |
| #define | DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk |
| #define | DCMI_CWSIZE_CAPCNT_Pos (0U) |
| #define | DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) |
| #define | DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk |
| #define | DCMI_CWSIZE_VLINE_Pos (16U) |
| #define | DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) |
| #define | DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk |
| #define | DCMI_DR_BYTE0_Pos (0U) |
| #define | DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) |
| #define | DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk |
| #define | DCMI_DR_BYTE1_Pos (8U) |
| #define | DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) |
| #define | DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk |
| #define | DCMI_DR_BYTE2_Pos (16U) |
| #define | DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) |
| #define | DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk |
| #define | DCMI_DR_BYTE3_Pos (24U) |
| #define | DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) |
| #define | DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk |
| #define | TIM3_TRGO_TRIGGER_SUPPORT /* TIM3 TRGO HW signal support */ |
| #define | TIM4_TRGO_TRIGGER_SUPPORT /* TIM4 TRGO HW signal support */ |
| #define | TIM5_TRGO_TRIGGER_SUPPORT /* TIM5 TRGO HW signal support */ |
| #define | DMA2D_TRIGGER_SUPPORT /* DMA2D TRGO HW signal support */ |
| #define | DMA_SECCFGR_SEC0_Pos (0U) |
| #define | DMA_SECCFGR_SEC0_Msk (0x1UL << DMA_SECCFGR_SEC0_Pos) |
| #define | DMA_SECCFGR_SEC0 DMA_SECCFGR_SEC0_Msk |
| #define | DMA_SECCFGR_SEC1_Pos (1U) |
| #define | DMA_SECCFGR_SEC1_Msk (0x1UL << DMA_SECCFGR_SEC1_Pos) |
| #define | DMA_SECCFGR_SEC1 DMA_SECCFGR_SEC1_Msk |
| #define | DMA_SECCFGR_SEC2_Pos (2U) |
| #define | DMA_SECCFGR_SEC2_Msk (0x1UL << DMA_SECCFGR_SEC2_Pos) |
| #define | DMA_SECCFGR_SEC2 DMA_SECCFGR_SEC2_Msk |
| #define | DMA_SECCFGR_SEC3_Pos (3U) |
| #define | DMA_SECCFGR_SEC3_Msk (0x1UL << DMA_SECCFGR_SEC3_Pos) |
| #define | DMA_SECCFGR_SEC3 DMA_SECCFGR_SEC3_Msk |
| #define | DMA_SECCFGR_SEC4_Pos (4U) |
| #define | DMA_SECCFGR_SEC4_Msk (0x1UL << DMA_SECCFGR_SEC4_Pos) |
| #define | DMA_SECCFGR_SEC4 DMA_SECCFGR_SEC4_Msk |
| #define | DMA_SECCFGR_SEC5_Pos (5U) |
| #define | DMA_SECCFGR_SEC5_Msk (0x1UL << DMA_SECCFGR_SEC5_Pos) |
| #define | DMA_SECCFGR_SEC5 DMA_SECCFGR_SEC5_Msk |
| #define | DMA_SECCFGR_SEC6_Pos (6U) |
| #define | DMA_SECCFGR_SEC6_Msk (0x1UL << DMA_SECCFGR_SEC6_Pos) |
| #define | DMA_SECCFGR_SEC6 DMA_SECCFGR_SEC6_Msk |
| #define | DMA_SECCFGR_SEC7_Pos (7U) |
| #define | DMA_SECCFGR_SEC7_Msk (0x1UL << DMA_SECCFGR_SEC7_Pos) |
| #define | DMA_SECCFGR_SEC7 DMA_SECCFGR_SEC7_Msk |
| #define | DMA_SECCFGR_SEC8_Pos (8U) |
| #define | DMA_SECCFGR_SEC8_Msk (0x1UL << DMA_SECCFGR_SEC8_Pos) |
| #define | DMA_SECCFGR_SEC8 DMA_SECCFGR_SEC8_Msk |
| #define | DMA_SECCFGR_SEC9_Pos (9U) |
| #define | DMA_SECCFGR_SEC9_Msk (0x1UL << DMA_SECCFGR_SEC9_Pos) |
| #define | DMA_SECCFGR_SEC9 DMA_SECCFGR_SEC9_Msk |
| #define | DMA_SECCFGR_SEC10_Pos (10U) |
| #define | DMA_SECCFGR_SEC10_Msk (0x1UL << DMA_SECCFGR_SEC10_Pos) |
| #define | DMA_SECCFGR_SEC10 DMA_SECCFGR_SEC10_Msk |
| #define | DMA_SECCFGR_SEC11_Pos (11U) |
| #define | DMA_SECCFGR_SEC11_Msk (0x1UL << DMA_SECCFGR_SEC11_Pos) |
| #define | DMA_SECCFGR_SEC11 DMA_SECCFGR_SEC11_Msk |
| #define | DMA_SECCFGR_SEC12_Pos (12U) |
| #define | DMA_SECCFGR_SEC12_Msk (0x1UL << DMA_SECCFGR_SEC12_Pos) |
| #define | DMA_SECCFGR_SEC12 DMA_SECCFGR_SEC12_Msk |
| #define | DMA_SECCFGR_SEC13_Pos (13U) |
| #define | DMA_SECCFGR_SEC13_Msk (0x1UL << DMA_SECCFGR_SEC13_Pos) |
| #define | DMA_SECCFGR_SEC13 DMA_SECCFGR_SEC13_Msk |
| #define | DMA_SECCFGR_SEC14_Pos (14U) |
| #define | DMA_SECCFGR_SEC14_Msk (0x1UL << DMA_SECCFGR_SEC14_Pos) |
| #define | DMA_SECCFGR_SEC14 DMA_SECCFGR_SEC14_Msk |
| #define | DMA_SECCFGR_SEC15_Pos (15U) |
| #define | DMA_SECCFGR_SEC15_Msk (0x1UL << DMA_SECCFGR_SEC15_Pos) |
| #define | DMA_SECCFGR_SEC15 DMA_SECCFGR_SEC15_Msk |
| #define | DMA_PRIVCFGR_PRIV0_Pos (0U) |
| #define | DMA_PRIVCFGR_PRIV0_Msk (0x1UL << DMA_PRIVCFGR_PRIV0_Pos) |
| #define | DMA_PRIVCFGR_PRIV0 DMA_PRIVCFGR_PRIV0_Msk |
| #define | DMA_PRIVCFGR_PRIV1_Pos (1U) |
| #define | DMA_PRIVCFGR_PRIV1_Msk (0x1UL << DMA_PRIVCFGR_PRIV1_Pos) |
| #define | DMA_PRIVCFGR_PRIV1 DMA_PRIVCFGR_PRIV1_Msk |
| #define | DMA_PRIVCFGR_PRIV2_Pos (2U) |
| #define | DMA_PRIVCFGR_PRIV2_Msk (0x1UL << DMA_PRIVCFGR_PRIV2_Pos) |
| #define | DMA_PRIVCFGR_PRIV2 DMA_PRIVCFGR_PRIV2_Msk |
| #define | DMA_PRIVCFGR_PRIV3_Pos (3U) |
| #define | DMA_PRIVCFGR_PRIV3_Msk (0x1UL << DMA_PRIVCFGR_PRIV3_Pos) |
| #define | DMA_PRIVCFGR_PRIV3 DMA_PRIVCFGR_PRIV3_Msk |
| #define | DMA_PRIVCFGR_PRIV4_Pos (4U) |
| #define | DMA_PRIVCFGR_PRIV4_Msk (0x1UL << DMA_PRIVCFGR_PRIV4_Pos) |
| #define | DMA_PRIVCFGR_PRIV4 DMA_PRIVCFGR_PRIV4_Msk |
| #define | DMA_PRIVCFGR_PRIV5_Pos (5U) |
| #define | DMA_PRIVCFGR_PRIV5_Msk (0x1UL << DMA_PRIVCFGR_PRIV5_Pos) |
| #define | DMA_PRIVCFGR_PRIV5 DMA_PRIVCFGR_PRIV5_Msk |
| #define | DMA_PRIVCFGR_PRIV6_Pos (6U) |
| #define | DMA_PRIVCFGR_PRIV6_Msk (0x1UL << DMA_PRIVCFGR_PRIV6_Pos) |
| #define | DMA_PRIVCFGR_PRIV6 DMA_PRIVCFGR_PRIV6_Msk |
| #define | DMA_PRIVCFGR_PRIV7_Pos (7U) |
| #define | DMA_PRIVCFGR_PRIV7_Msk (0x1UL << DMA_PRIVCFGR_PRIV7_Pos) |
| #define | DMA_PRIVCFGR_PRIV7 DMA_PRIVCFGR_PRIV7_Msk |
| #define | DMA_PRIVCFGR_PRIV8_Pos (8U) |
| #define | DMA_PRIVCFGR_PRIV8_Msk (0x1UL << DMA_PRIVCFGR_PRIV8_Pos) |
| #define | DMA_PRIVCFGR_PRIV8 DMA_PRIVCFGR_PRIV8_Msk |
| #define | DMA_PRIVCFGR_PRIV9_Pos (9U) |
| #define | DMA_PRIVCFGR_PRIV9_Msk (0x1UL << DMA_PRIVCFGR_PRIV9_Pos) |
| #define | DMA_PRIVCFGR_PRIV9 DMA_PRIVCFGR_PRIV9_Msk |
| #define | DMA_PRIVCFGR_PRIV10_Pos (10U) |
| #define | DMA_PRIVCFGR_PRIV10_Msk (0x1UL << DMA_PRIVCFGR_PRIV10_Pos) |
| #define | DMA_PRIVCFGR_PRIV10 DMA_PRIVCFGR_PRIV10_Msk |
| #define | DMA_PRIVCFGR_PRIV11_Pos (11U) |
| #define | DMA_PRIVCFGR_PRIV11_Msk (0x1UL << DMA_PRIVCFGR_PRIV11_Pos) |
| #define | DMA_PRIVCFGR_PRIV11 DMA_PRIVCFGR_PRIV11_Msk |
| #define | DMA_PRIVCFGR_PRIV12_Pos (12U) |
| #define | DMA_PRIVCFGR_PRIV12_Msk (0x1UL << DMA_PRIVCFGR_PRIV12_Pos) |
| #define | DMA_PRIVCFGR_PRIV12 DMA_PRIVCFGR_PRIV12_Msk |
| #define | DMA_PRIVCFGR_PRIV13_Pos (13U) |
| #define | DMA_PRIVCFGR_PRIV13_Msk (0x1UL << DMA_PRIVCFGR_PRIV13_Pos) |
| #define | DMA_PRIVCFGR_PRIV13 DMA_PRIVCFGR_PRIV13_Msk |
| #define | DMA_PRIVCFGR_PRIV14_Pos (14U) |
| #define | DMA_PRIVCFGR_PRIV14_Msk (0x1UL << DMA_PRIVCFGR_PRIV14_Pos) |
| #define | DMA_PRIVCFGR_PRIV14 DMA_PRIVCFGR_PRIV14_Msk |
| #define | DMA_PRIVCFGR_PRIV15_Pos (15U) |
| #define | DMA_PRIVCFGR_PRIV15_Msk (0x1UL << DMA_PRIVCFGR_PRIV15_Pos) |
| #define | DMA_PRIVCFGR_PRIV15 DMA_PRIVCFGR_PRIV15_Msk |
| #define | DMA_RCFGLOCKR_LOCK0_Pos (0U) |
| #define | DMA_RCFGLOCKR_LOCK0_Msk (0x1UL << DMA_RCFGLOCKR_LOCK0_Pos) |
| #define | DMA_RCFGLOCKR_LOCK0 DMA_RCFGLOCKR_LOCK0_Msk |
| #define | DMA_RCFGLOCKR_LOCK1_Pos (1U) |
| #define | DMA_RCFGLOCKR_LOCK1_Msk (0x1UL << DMA_RCFGLOCKR_LOCK1_Pos) |
| #define | DMA_RCFGLOCKR_LOCK1 DMA_RCFGLOCKR_LOCK1_Msk |
| #define | DMA_RCFGLOCKR_LOCK2_Pos (2U) |
| #define | DMA_RCFGLOCKR_LOCK2_Msk (0x1UL << DMA_RCFGLOCKR_LOCK2_Pos) |
| #define | DMA_RCFGLOCKR_LOCK2 DMA_RCFGLOCKR_LOCK2_Msk |
| #define | DMA_RCFGLOCKR_LOCK3_Pos (3U) |
| #define | DMA_RCFGLOCKR_LOCK3_Msk (0x1UL << DMA_RCFGLOCKR_LOCK3_Pos) |
| #define | DMA_RCFGLOCKR_LOCK3 DMA_RCFGLOCKR_LOCK3_Msk |
| #define | DMA_RCFGLOCKR_LOCK4_Pos (4U) |
| #define | DMA_RCFGLOCKR_LOCK4_Msk (0x1UL << DMA_RCFGLOCKR_LOCK4_Pos) |
| #define | DMA_RCFGLOCKR_LOCK4 DMA_RCFGLOCKR_LOCK4_Msk |
| #define | DMA_RCFGLOCKR_LOCK5_Pos (5U) |
| #define | DMA_RCFGLOCKR_LOCK5_Msk (0x1UL << DMA_RCFGLOCKR_LOCK5_Pos) |
| #define | DMA_RCFGLOCKR_LOCK5 DMA_RCFGLOCKR_LOCK5_Msk |
| #define | DMA_RCFGLOCKR_LOCK6_Pos (6U) |
| #define | DMA_RCFGLOCKR_LOCK6_Msk (0x1UL << DMA_RCFGLOCKR_LOCK6_Pos) |
| #define | DMA_RCFGLOCKR_LOCK6 DMA_RCFGLOCKR_LOCK6_Msk |
| #define | DMA_RCFGLOCKR_LOCK7_Pos (7U) |
| #define | DMA_RCFGLOCKR_LOCK7_Msk (0x1UL << DMA_RCFGLOCKR_LOCK7_Pos) |
| #define | DMA_RCFGLOCKR_LOCK7 DMA_RCFGLOCKR_LOCK7_Msk |
| #define | DMA_RCFGLOCKR_LOCK8_Pos (8U) |
| #define | DMA_RCFGLOCKR_LOCK8_Msk (0x1UL << DMA_RCFGLOCKR_LOCK8_Pos) |
| #define | DMA_RCFGLOCKR_LOCK8 DMA_RCFGLOCKR_LOCK8_Msk |
| #define | DMA_RCFGLOCKR_LOCK9_Pos (9U) |
| #define | DMA_RCFGLOCKR_LOCK9_Msk (0x1UL << DMA_RCFGLOCKR_LOCK9_Pos) |
| #define | DMA_RCFGLOCKR_LOCK9 DMA_RCFGLOCKR_LOCK9_Msk |
| #define | DMA_RCFGLOCKR_LOCK10_Pos (10U) |
| #define | DMA_RCFGLOCKR_LOCK10_Msk (0x1UL << DMA_RCFGLOCKR_LOCK10_Pos) |
| #define | DMA_RCFGLOCKR_LOCK10 DMA_RCFGLOCKR_LOCK10_Msk |
| #define | DMA_RCFGLOCKR_LOCK11_Pos (11U) |
| #define | DMA_RCFGLOCKR_LOCK11_Msk (0x1UL << DMA_RCFGLOCKR_LOCK11_Pos) |
| #define | DMA_RCFGLOCKR_LOCK11 DMA_RCFGLOCKR_LOCK11_Msk |
| #define | DMA_RCFGLOCKR_LOCK12_Pos (12U) |
| #define | DMA_RCFGLOCKR_LOCK12_Msk (0x1UL << DMA_RCFGLOCKR_LOCK12_Pos) |
| #define | DMA_RCFGLOCKR_LOCK12 DMA_RCFGLOCKR_LOCK12_Msk |
| #define | DMA_RCFGLOCKR_LOCK13_Pos (13U) |
| #define | DMA_RCFGLOCKR_LOCK13_Msk (0x1UL << DMA_RCFGLOCKR_LOCK13_Pos) |
| #define | DMA_RCFGLOCKR_LOCK13 DMA_RCFGLOCKR_LOCK13_Msk |
| #define | DMA_RCFGLOCKR_LOCK14_Pos (14U) |
| #define | DMA_RCFGLOCKR_LOCK14_Msk (0x1UL << DMA_RCFGLOCKR_LOCK14_Pos) |
| #define | DMA_RCFGLOCKR_LOCK14 DMA_RCFGLOCKR_LOCK14_Msk |
| #define | DMA_RCFGLOCKR_LOCK15_Pos (15U) |
| #define | DMA_RCFGLOCKR_LOCK15_Msk (0x1UL << DMA_RCFGLOCKR_LOCK15_Pos) |
| #define | DMA_RCFGLOCKR_LOCK15 DMA_RCFGLOCKR_LOCK15_Msk |
| #define | DMA_MISR_MIS0_Pos (0U) |
| #define | DMA_MISR_MIS0_Msk (0x1UL << DMA_MISR_MIS0_Pos) |
| #define | DMA_MISR_MIS0 DMA_MISR_MIS0_Msk |
| #define | DMA_MISR_MIS1_Pos (1U) |
| #define | DMA_MISR_MIS1_Msk (0x1UL << DMA_MISR_MIS1_Pos) |
| #define | DMA_MISR_MIS1 DMA_MISR_MIS1_Msk |
| #define | DMA_MISR_MIS2_Pos (2U) |
| #define | DMA_MISR_MIS2_Msk (0x1UL << DMA_MISR_MIS2_Pos) |
| #define | DMA_MISR_MIS2 DMA_MISR_MIS2_Msk |
| #define | DMA_MISR_MIS3_Pos (3U) |
| #define | DMA_MISR_MIS3_Msk (0x1UL << DMA_MISR_MIS3_Pos) |
| #define | DMA_MISR_MIS3 DMA_MISR_MIS3_Msk |
| #define | DMA_MISR_MIS4_Pos (4U) |
| #define | DMA_MISR_MIS4_Msk (0x1UL << DMA_MISR_MIS4_Pos) |
| #define | DMA_MISR_MIS4 DMA_MISR_MIS4_Msk |
| #define | DMA_MISR_MIS5_Pos (5U) |
| #define | DMA_MISR_MIS5_Msk (0x1UL << DMA_MISR_MIS5_Pos) |
| #define | DMA_MISR_MIS5 DMA_MISR_MIS5_Msk |
| #define | DMA_MISR_MIS6_Pos (6U) |
| #define | DMA_MISR_MIS6_Msk (0x1UL << DMA_MISR_MIS6_Pos) |
| #define | DMA_MISR_MIS6 DMA_MISR_MIS6_Msk |
| #define | DMA_MISR_MIS7_Pos (7U) |
| #define | DMA_MISR_MIS7_Msk (0x1UL << DMA_MISR_MIS7_Pos) |
| #define | DMA_MISR_MIS7 DMA_MISR_MIS7_Msk |
| #define | DMA_MISR_MIS8_Pos (8U) |
| #define | DMA_MISR_MIS8_Msk (0x1UL << DMA_MISR_MIS8_Pos) |
| #define | DMA_MISR_MIS8 DMA_MISR_MIS8_Msk |
| #define | DMA_MISR_MIS9_Pos (9U) |
| #define | DMA_MISR_MIS9_Msk (0x1UL << DMA_MISR_MIS9_Pos) |
| #define | DMA_MISR_MIS9 DMA_MISR_MIS9_Msk |
| #define | DMA_MISR_MIS10_Pos (10U) |
| #define | DMA_MISR_MIS10_Msk (0x1UL << DMA_MISR_MIS10_Pos) |
| #define | DMA_MISR_MIS10 DMA_MISR_MIS10_Msk |
| #define | DMA_MISR_MIS11_Pos (11U) |
| #define | DMA_MISR_MIS11_Msk (0x1UL << DMA_MISR_MIS11_Pos) |
| #define | DMA_MISR_MIS11 DMA_MISR_MIS11_Msk |
| #define | DMA_MISR_MIS12_Pos (12U) |
| #define | DMA_MISR_MIS12_Msk (0x1UL << DMA_MISR_MIS12_Pos) |
| #define | DMA_MISR_MIS12 DMA_MISR_MIS12_Msk |
| #define | DMA_MISR_MIS13_Pos (13U) |
| #define | DMA_MISR_MIS13_Msk (0x1UL << DMA_MISR_MIS13_Pos) |
| #define | DMA_MISR_MIS13 DMA_MISR_MIS13_Msk |
| #define | DMA_MISR_MIS14_Pos (14U) |
| #define | DMA_MISR_MIS14_Msk (0x1UL << DMA_MISR_MIS14_Pos) |
| #define | DMA_MISR_MIS14 DMA_MISR_MIS14_Msk |
| #define | DMA_MISR_MIS15_Pos (15U) |
| #define | DMA_MISR_MIS15_Msk (0x1UL << DMA_MISR_MIS15_Pos) |
| #define | DMA_MISR_MIS15 DMA_MISR_MIS14_Msk |
| #define | DMA_SMISR_MIS0_Pos (0U) |
| #define | DMA_SMISR_MIS0_Msk (0x1UL << DMA_SMISR_MIS0_Pos) |
| #define | DMA_SMISR_MIS0 DMA_SMISR_MIS0_Msk |
| #define | DMA_SMISR_MIS1_Pos (1U) |
| #define | DMA_SMISR_MIS1_Msk (0x1UL << DMA_SMISR_MIS1_Pos) |
| #define | DMA_SMISR_MIS1 DMA_SMISR_MIS1_Msk |
| #define | DMA_SMISR_MIS2_Pos (2U) |
| #define | DMA_SMISR_MIS2_Msk (0x1UL << DMA_SMISR_MIS2_Pos) |
| #define | DMA_SMISR_MIS2 DMA_SMISR_MIS2_Msk |
| #define | DMA_SMISR_MIS3_Pos (3U) |
| #define | DMA_SMISR_MIS3_Msk (0x1UL << DMA_SMISR_MIS3_Pos) |
| #define | DMA_SMISR_MIS3 DMA_SMISR_MIS3_Msk |
| #define | DMA_SMISR_MIS4_Pos (4U) |
| #define | DMA_SMISR_MIS4_Msk (0x1UL << DMA_SMISR_MIS4_Pos) |
| #define | DMA_SMISR_MIS4 DMA_SMISR_MIS4_Msk |
| #define | DMA_SMISR_MIS5_Pos (5U) |
| #define | DMA_SMISR_MIS5_Msk (0x1UL << DMA_SMISR_MIS5_Pos) |
| #define | DMA_SMISR_MIS5 DMA_SMISR_MIS5_Msk |
| #define | DMA_SMISR_MIS6_Pos (6U) |
| #define | DMA_SMISR_MIS6_Msk (0x1UL << DMA_SMISR_MIS6_Pos) |
| #define | DMA_SMISR_MIS6 DMA_SMISR_MIS6_Msk |
| #define | DMA_SMISR_MIS7_Pos (7U) |
| #define | DMA_SMISR_MIS7_Msk (0x1UL << DMA_SMISR_MIS7_Pos) |
| #define | DMA_SMISR_MIS7 DMA_SMISR_MIS7_Msk |
| #define | DMA_SMISR_MIS8_Pos (8U) |
| #define | DMA_SMISR_MIS8_Msk (0x1UL << DMA_SMISR_MIS8_Pos) |
| #define | DMA_SMISR_MIS8 DMA_SMISR_MIS8_Msk |
| #define | DMA_SMISR_MIS9_Pos (9U) |
| #define | DMA_SMISR_MIS9_Msk (0x1UL << DMA_SMISR_MIS9_Pos) |
| #define | DMA_SMISR_MIS9 DMA_SMISR_MIS9_Msk |
| #define | DMA_SMISR_MIS10_Pos (10U) |
| #define | DMA_SMISR_MIS10_Msk (0x1UL << DMA_SMISR_MIS10_Pos) |
| #define | DMA_SMISR_MIS10 DMA_SMISR_MIS10_Msk |
| #define | DMA_SMISR_MIS11_Pos (11U) |
| #define | DMA_SMISR_MIS11_Msk (0x1UL << DMA_SMISR_MIS11_Pos) |
| #define | DMA_SMISR_MIS11 DMA_SMISR_MIS11_Msk |
| #define | DMA_SMISR_MIS12_Pos (12U) |
| #define | DMA_SMISR_MIS12_Msk (0x1UL << DMA_SMISR_MIS12_Pos) |
| #define | DMA_SMISR_MIS12 DMA_SMISR_MIS12_Msk |
| #define | DMA_SMISR_MIS13_Pos (13U) |
| #define | DMA_SMISR_MIS13_Msk (0x1UL << DMA_SMISR_MIS13_Pos) |
| #define | DMA_SMISR_MIS13 DMA_SMISR_MIS13_Msk |
| #define | DMA_SMISR_MIS14_Pos (14U) |
| #define | DMA_SMISR_MIS14_Msk (0x1UL << DMA_SMISR_MIS14_Pos) |
| #define | DMA_SMISR_MIS14 DMA_SMISR_MIS14_Msk |
| #define | DMA_SMISR_MIS15_Pos (15U) |
| #define | DMA_SMISR_MIS15_Msk (0x1UL << DMA_SMISR_MIS15_Pos) |
| #define | DMA_SMISR_MIS15 DMA_SMISR_MIS14_Msk |
| #define | DMA_CLBAR_LBA_Pos (16U) |
| #define | DMA_CLBAR_LBA_Msk (0xFFFFUL << DMA_CLBAR_LBA_Pos) |
| #define | DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk |
| #define | DMA_CFCR_TCF_Pos (8U) |
| #define | DMA_CFCR_TCF_Msk (0x1UL << DMA_CFCR_TCF_Pos) |
| #define | DMA_CFCR_TCF DMA_CFCR_TCF_Msk |
| #define | DMA_CFCR_HTF_Pos (9U) |
| #define | DMA_CFCR_HTF_Msk (0x1UL << DMA_CFCR_HTF_Pos) |
| #define | DMA_CFCR_HTF DMA_CFCR_HTF_Msk |
| #define | DMA_CFCR_DTEF_Pos (10U) |
| #define | DMA_CFCR_DTEF_Msk (0x1UL << DMA_CFCR_DTEF_Pos) |
| #define | DMA_CFCR_DTEF DMA_CFCR_DTEF_Msk |
| #define | DMA_CFCR_ULEF_Pos (11U) |
| #define | DMA_CFCR_ULEF_Msk (0x1UL << DMA_CFCR_ULEF_Pos) |
| #define | DMA_CFCR_ULEF DMA_CFCR_ULEF_Msk |
| #define | DMA_CFCR_USEF_Pos (12U) |
| #define | DMA_CFCR_USEF_Msk (0x1UL << DMA_CFCR_USEF_Pos) |
| #define | DMA_CFCR_USEF DMA_CFCR_USEF_Msk |
| #define | DMA_CFCR_SUSPF_Pos (13U) |
| #define | DMA_CFCR_SUSPF_Msk (0x1UL << DMA_CFCR_SUSPF_Pos) |
| #define | DMA_CFCR_SUSPF DMA_CFCR_SUSPF_Msk |
| #define | DMA_CFCR_TOF_Pos (14U) |
| #define | DMA_CFCR_TOF_Msk (0x1UL << DMA_CFCR_TOF_Pos) |
| #define | DMA_CFCR_TOF DMA_CFCR_TOF_Msk |
| #define | DMA_CSR_IDLEF_Pos (0U) |
| #define | DMA_CSR_IDLEF_Msk (0x1UL << DMA_CSR_IDLEF_Pos) |
| #define | DMA_CSR_IDLEF DMA_CSR_IDLEF_Msk |
| #define | DMA_CSR_TCF_Pos (8U) |
| #define | DMA_CSR_TCF_Msk (0x1UL << DMA_CSR_TCF_Pos) |
| #define | DMA_CSR_TCF DMA_CSR_TCF_Msk |
| #define | DMA_CSR_HTF_Pos (9U) |
| #define | DMA_CSR_HTF_Msk (0x1UL << DMA_CSR_HTF_Pos) |
| #define | DMA_CSR_HTF DMA_CSR_HTF_Msk |
| #define | DMA_CSR_DTEF_Pos (10U) |
| #define | DMA_CSR_DTEF_Msk (0x1UL << DMA_CSR_DTEF_Pos) |
| #define | DMA_CSR_DTEF DMA_CSR_DTEF_Msk |
| #define | DMA_CSR_ULEF_Pos (11U) |
| #define | DMA_CSR_ULEF_Msk (0x1UL << DMA_CSR_ULEF_Pos) |
| #define | DMA_CSR_ULEF DMA_CSR_ULEF_Msk |
| #define | DMA_CSR_USEF_Pos (12U) |
| #define | DMA_CSR_USEF_Msk (0x1UL << DMA_CSR_USEF_Pos) |
| #define | DMA_CSR_USEF DMA_CSR_USEF_Msk |
| #define | DMA_CSR_SUSPF_Pos (13U) |
| #define | DMA_CSR_SUSPF_Msk (0x1UL << DMA_CSR_SUSPF_Pos) |
| #define | DMA_CSR_SUSPF DMA_CSR_SUSPF_Msk |
| #define | DMA_CSR_TOF_Pos (14U) |
| #define | DMA_CSR_TOF_Msk (0x1UL << DMA_CSR_TOF_Pos) |
| #define | DMA_CSR_TOF DMA_CSR_TOF_Msk |
| #define | DMA_CSR_FIFOL_Pos (16U) |
| #define | DMA_CSR_FIFOL_Msk (0xFFUL << DMA_CSR_FIFOL_Pos) |
| #define | DMA_CSR_FIFOL DMA_CSR_FIFOL_Msk |
| #define | DMA_CCR_EN_Pos (0U) |
| #define | DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) |
| #define | DMA_CCR_EN DMA_CCR_EN_Msk |
| #define | DMA_CCR_RESET_Pos (1U) |
| #define | DMA_CCR_RESET_Msk (0x1UL << DMA_CCR_RESET_Pos) |
| #define | DMA_CCR_RESET DMA_CCR_RESET_Msk |
| #define | DMA_CCR_SUSP_Pos (2U) |
| #define | DMA_CCR_SUSP_Msk (0x1UL << DMA_CCR_SUSP_Pos) |
| #define | DMA_CCR_SUSP DMA_CCR_SUSP_Msk |
| #define | DMA_CCR_TCIE_Pos (8U) |
| #define | DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) |
| #define | DMA_CCR_TCIE DMA_CCR_TCIE_Msk |
| #define | DMA_CCR_HTIE_Pos (9U) |
| #define | DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) |
| #define | DMA_CCR_HTIE DMA_CCR_HTIE_Msk |
| #define | DMA_CCR_DTEIE_Pos (10U) |
| #define | DMA_CCR_DTEIE_Msk (0x1UL << DMA_CCR_DTEIE_Pos) |
| #define | DMA_CCR_DTEIE DMA_CCR_DTEIE_Msk |
| #define | DMA_CCR_ULEIE_Pos (11U) |
| #define | DMA_CCR_ULEIE_Msk (0x1UL << DMA_CCR_ULEIE_Pos) |
| #define | DMA_CCR_ULEIE DMA_CCR_ULEIE_Msk |
| #define | DMA_CCR_USEIE_Pos (12U) |
| #define | DMA_CCR_USEIE_Msk (0x1UL << DMA_CCR_USEIE_Pos) |
| #define | DMA_CCR_USEIE DMA_CCR_USEIE_Msk |
| #define | DMA_CCR_SUSPIE_Pos (13U) |
| #define | DMA_CCR_SUSPIE_Msk (0x1UL << DMA_CCR_SUSPIE_Pos) |
| #define | DMA_CCR_SUSPIE DMA_CCR_SUSPIE_Msk |
| #define | DMA_CCR_TOIE_Pos (14U) |
| #define | DMA_CCR_TOIE_Msk (0x1UL << DMA_CCR_TOIE_Pos) |
| #define | DMA_CCR_TOIE DMA_CCR_TOIE_Msk |
| #define | DMA_CCR_LSM_Pos (16U) |
| #define | DMA_CCR_LSM_Msk (0x1UL << DMA_CCR_LSM_Pos) |
| #define | DMA_CCR_LSM DMA_CCR_LSM_Msk |
| #define | DMA_CCR_LAP_Pos (17U) |
| #define | DMA_CCR_LAP_Msk (0x1UL << DMA_CCR_LAP_Pos) |
| #define | DMA_CCR_LAP DMA_CCR_LAP_Msk |
| #define | DMA_CCR_PRIO_Pos (22U) |
| #define | DMA_CCR_PRIO_Msk (0x3UL << DMA_CCR_PRIO_Pos) |
| #define | DMA_CCR_PRIO DMA_CCR_PRIO_Msk |
| #define | DMA_CCR_PRIO_0 (0x1UL << DMA_CCR_PRIO_Pos) |
| #define | DMA_CCR_PRIO_1 (0x2UL << DMA_CCR_PRIO_Pos) |
| #define | DMA_CTR1_SDW_LOG2_Pos (0U) |
| #define | DMA_CTR1_SDW_LOG2_Msk (0x3UL << DMA_CTR1_SDW_LOG2_Pos) |
| #define | DMA_CTR1_SDW_LOG2 DMA_CTR1_SDW_LOG2_Msk |
| #define | DMA_CTR1_SDW_LOG2_0 (0x1UL << DMA_CTR1_SDW_LOG2_Pos) |
| #define | DMA_CTR1_SDW_LOG2_1 (0x2UL << DMA_CTR1_SDW_LOG2_Pos) |
| #define | DMA_CTR1_SINC_Pos (3U) |
| #define | DMA_CTR1_SINC_Msk (0x1UL << DMA_CTR1_SINC_Pos) |
| #define | DMA_CTR1_SINC DMA_CTR1_SINC_Msk |
| #define | DMA_CTR1_SBL_1_Pos (4U) |
| #define | DMA_CTR1_SBL_1_Msk (0x3FUL << DMA_CTR1_SBL_1_Pos) |
| #define | DMA_CTR1_SBL_1 DMA_CTR1_SBL_1_Msk |
| #define | DMA_CTR1_PAM_Pos (11U) |
| #define | DMA_CTR1_PAM_Msk (0x3UL << DMA_CTR1_PAM_Pos) |
| #define | DMA_CTR1_PAM DMA_CTR1_PAM_Msk |
| #define | DMA_CTR1_PAM_0 (0x1UL << DMA_CTR1_PAM_Pos) |
| #define | DMA_CTR1_PAM_1 (0x2UL << DMA_CTR1_PAM_Pos) |
| #define | DMA_CTR1_SBX_Pos (13U) |
| #define | DMA_CTR1_SBX_Msk (0x1UL << DMA_CTR1_SBX_Pos) |
| #define | DMA_CTR1_SBX DMA_CTR1_SBX_Msk |
| #define | DMA_CTR1_SAP_Pos (14U) |
| #define | DMA_CTR1_SAP_Msk (0x1UL << DMA_CTR1_SAP_Pos) |
| #define | DMA_CTR1_SAP DMA_CTR1_SAP_Msk |
| #define | DMA_CTR1_SSEC_Pos (15U) |
| #define | DMA_CTR1_SSEC_Msk (0x1UL << DMA_CTR1_SSEC_Pos) |
| #define | DMA_CTR1_SSEC DMA_CTR1_SSEC_Msk |
| #define | DMA_CTR1_DDW_LOG2_Pos (16U) |
| #define | DMA_CTR1_DDW_LOG2_Msk (0x3UL << DMA_CTR1_DDW_LOG2_Pos) |
| #define | DMA_CTR1_DDW_LOG2 DMA_CTR1_DDW_LOG2_Msk |
| #define | DMA_CTR1_DDW_LOG2_0 (0x1UL << DMA_CTR1_DDW_LOG2_Pos) |
| #define | DMA_CTR1_DDW_LOG2_1 (0x2UL << DMA_CTR1_DDW_LOG2_Pos) |
| #define | DMA_CTR1_DINC_Pos (19U) |
| #define | DMA_CTR1_DINC_Msk (0x1UL << DMA_CTR1_DINC_Pos) |
| #define | DMA_CTR1_DINC DMA_CTR1_DINC_Msk |
| #define | DMA_CTR1_DBL_1_Pos (20U) |
| #define | DMA_CTR1_DBL_1_Msk (0x3FUL << DMA_CTR1_DBL_1_Pos) |
| #define | DMA_CTR1_DBL_1 DMA_CTR1_DBL_1_Msk |
| #define | DMA_CTR1_DBX_Pos (26U) |
| #define | DMA_CTR1_DBX_Msk (0x1UL << DMA_CTR1_DBX_Pos) |
| #define | DMA_CTR1_DBX DMA_CTR1_DBX_Msk |
| #define | DMA_CTR1_DHX_Pos (27U) |
| #define | DMA_CTR1_DHX_Msk (0x1UL << DMA_CTR1_DHX_Pos) |
| #define | DMA_CTR1_DHX DMA_CTR1_DHX_Msk |
| #define | DMA_CTR1_DAP_Pos (30U) |
| #define | DMA_CTR1_DAP_Msk (0x1UL << DMA_CTR1_DAP_Pos) |
| #define | DMA_CTR1_DAP DMA_CTR1_DAP_Msk |
| #define | DMA_CTR1_DSEC_Pos (31U) |
| #define | DMA_CTR1_DSEC_Msk (0x1UL << DMA_CTR1_DSEC_Pos) |
| #define | DMA_CTR1_DSEC DMA_CTR1_DSEC_Msk |
| #define | DMA_CTR2_REQSEL_Pos (0U) |
| #define | DMA_CTR2_REQSEL_Msk (0x7FUL << DMA_CTR2_REQSEL_Pos) |
| #define | DMA_CTR2_REQSEL DMA_CTR2_REQSEL_Msk |
| #define | DMA_CTR2_SWREQ_Pos (9U) |
| #define | DMA_CTR2_SWREQ_Msk (0x1UL << DMA_CTR2_SWREQ_Pos) |
| #define | DMA_CTR2_SWREQ DMA_CTR2_SWREQ_Msk |
| #define | DMA_CTR2_DREQ_Pos (10U) |
| #define | DMA_CTR2_DREQ_Msk (0x1UL << DMA_CTR2_DREQ_Pos) |
| #define | DMA_CTR2_DREQ DMA_CTR2_DREQ_Msk |
| #define | DMA_CTR2_BREQ_Pos (11U) |
| #define | DMA_CTR2_BREQ_Msk (0x1UL << DMA_CTR2_BREQ_Pos) |
| #define | DMA_CTR2_BREQ DMA_CTR2_BREQ_Msk |
| #define | DMA_CTR2_TRIGM_Pos (14U) |
| #define | DMA_CTR2_TRIGM_Msk (0x3UL << DMA_CTR2_TRIGM_Pos) |
| #define | DMA_CTR2_TRIGM DMA_CTR2_TRIGM_Msk |
| #define | DMA_CTR2_TRIGM_0 (0x1UL << DMA_CTR2_TRIGM_Pos) |
| #define | DMA_CTR2_TRIGM_1 (0x2UL << DMA_CTR2_TRIGM_Pos) |
| #define | DMA_CTR2_TRIGSEL_Pos (16U) |
| #define | DMA_CTR2_TRIGSEL_Msk (0x7FUL << DMA_CTR2_TRIGSEL_Pos) |
| #define | DMA_CTR2_TRIGSEL DMA_CTR2_TRIGSEL_Msk |
| #define | DMA_CTR2_TRIGPOL_Pos (24U) |
| #define | DMA_CTR2_TRIGPOL_Msk (0x3UL << DMA_CTR2_TRIGPOL_Pos) |
| #define | DMA_CTR2_TRIGPOL DMA_CTR2_TRIGPOL_Msk |
| #define | DMA_CTR2_TRIGPOL_0 (0x1UL << DMA_CTR2_TRIGPOL_Pos) |
| #define | DMA_CTR2_TRIGPOL_1 (0x2UL << DMA_CTR2_TRIGPOL_Pos) |
| #define | DMA_CTR2_TCEM_Pos (30U) |
| #define | DMA_CTR2_TCEM_Msk (0x3UL << DMA_CTR2_TCEM_Pos) |
| #define | DMA_CTR2_TCEM DMA_CTR2_TCEM_Msk |
| #define | DMA_CTR2_TCEM_0 (0x1UL << DMA_CTR2_TCEM_Pos) |
| #define | DMA_CTR2_TCEM_1 (0x2UL << DMA_CTR2_TCEM_Pos) |
| #define | DMA_CBR1_BNDT_Pos (0U) |
| #define | DMA_CBR1_BNDT_Msk (0xFFFFUL << DMA_CBR1_BNDT_Pos) |
| #define | DMA_CBR1_BNDT DMA_CBR1_BNDT_Msk |
| #define | DMA_CBR1_BRC_Pos (16U) |
| #define | DMA_CBR1_BRC_Msk (0x7FFUL << DMA_CBR1_BRC_Pos) |
| #define | DMA_CBR1_BRC DMA_CBR1_BRC_Msk |
| #define | DMA_CBR1_SDEC_Pos (28U) |
| #define | DMA_CBR1_SDEC_Msk (0x1UL << DMA_CBR1_SDEC_Pos) |
| #define | DMA_CBR1_SDEC DMA_CBR1_SDEC_Msk |
| #define | DMA_CBR1_DDEC_Pos (29U) |
| #define | DMA_CBR1_DDEC_Msk (0x1UL << DMA_CBR1_DDEC_Pos) |
| #define | DMA_CBR1_DDEC DMA_CBR1_DDEC_Msk |
| #define | DMA_CBR1_BRSDEC_Pos (30U) |
| #define | DMA_CBR1_BRSDEC_Msk (0x1UL << DMA_CBR1_BRSDEC_Pos) |
| #define | DMA_CBR1_BRSDEC DMA_CBR1_BRSDEC_Msk |
| #define | DMA_CBR1_BRDDEC_Pos (31U) |
| #define | DMA_CBR1_BRDDEC_Msk (0x1UL << DMA_CBR1_BRDDEC_Pos) |
| #define | DMA_CBR1_BRDDEC DMA_CBR1_BRDDEC_Msk |
| #define | DMA_CSAR_SA_Pos (0U) |
| #define | DMA_CSAR_SA_Msk (0xFFFFFFFFUL << DMA_CSAR_SA_Pos) |
| #define | DMA_CSAR_SA DMA_CSAR_SA_Msk |
| #define | DMA_CDAR_DA_Pos (0U) |
| #define | DMA_CDAR_DA_Msk (0xFFFFFFFFUL << DMA_CDAR_DA_Pos) |
| #define | DMA_CDAR_DA DMA_CDAR_DA_Msk |
| #define | DMA_CTR3_SAO_Pos (0U) |
| #define | DMA_CTR3_SAO_Msk (0x1FFFUL << DMA_CTR3_SAO_Pos) |
| #define | DMA_CTR3_SAO DMA_CTR3_SAO_Msk |
| #define | DMA_CTR3_DAO_Pos (16U) |
| #define | DMA_CTR3_DAO_Msk (0x1FFFUL << DMA_CTR3_DAO_Pos) |
| #define | DMA_CTR3_DAO DMA_CTR3_DAO_Msk |
| #define | DMA_CBR2_BRSAO_Pos (0U) |
| #define | DMA_CBR2_BRSAO_Msk (0xFFFFUL << DMA_CBR2_BRSAO_Pos) |
| #define | DMA_CBR2_BRSAO DMA_CBR2_BRSAO_Msk |
| #define | DMA_CBR2_BRDAO_Pos (16U) |
| #define | DMA_CBR2_BRDAO_Msk (0xFFFFUL << DMA_CBR2_BRDAO_Pos) |
| #define | DMA_CBR2_BRDAO DMA_CBR2_BRDAO_Msk |
| #define | DMA_CLLR_LA_Pos (2U) |
| #define | DMA_CLLR_LA_Msk (0x3FFFUL << DMA_CLLR_LA_Pos) |
| #define | DMA_CLLR_LA DMA_CLLR_LA_Msk |
| #define | DMA_CLLR_ULL_Pos (16U) |
| #define | DMA_CLLR_ULL_Msk (0x1UL << DMA_CLLR_ULL_Pos) |
| #define | DMA_CLLR_ULL DMA_CLLR_ULL_Msk |
| #define | DMA_CLLR_UB2_Pos (25U) |
| #define | DMA_CLLR_UB2_Msk (0x1UL << DMA_CLLR_UB2_Pos) |
| #define | DMA_CLLR_UB2 DMA_CLLR_UB2_Msk |
| #define | DMA_CLLR_UT3_Pos (26U) |
| #define | DMA_CLLR_UT3_Msk (0x1UL << DMA_CLLR_UT3_Pos) |
| #define | DMA_CLLR_UT3 DMA_CLLR_UT3_Msk |
| #define | DMA_CLLR_UDA_Pos (27U) |
| #define | DMA_CLLR_UDA_Msk (0x1UL << DMA_CLLR_UDA_Pos) |
| #define | DMA_CLLR_UDA DMA_CLLR_UDA_Msk |
| #define | DMA_CLLR_USA_Pos (28U) |
| #define | DMA_CLLR_USA_Msk (0x1UL << DMA_CLLR_USA_Pos) |
| #define | DMA_CLLR_USA DMA_CLLR_USA_Msk |
| #define | DMA_CLLR_UB1_Pos (29U) |
| #define | DMA_CLLR_UB1_Msk (0x1UL << DMA_CLLR_UB1_Pos) |
| #define | DMA_CLLR_UB1 DMA_CLLR_UB1_Msk |
| #define | DMA_CLLR_UT2_Pos (30U) |
| #define | DMA_CLLR_UT2_Msk (0x1UL << DMA_CLLR_UT2_Pos) |
| #define | DMA_CLLR_UT2 DMA_CLLR_UT2_Msk |
| #define | DMA_CLLR_UT1_Pos (31U) |
| #define | DMA_CLLR_UT1_Msk (0x1UL << DMA_CLLR_UT1_Pos) |
| #define | DMA_CLLR_UT1 DMA_CLLR_UT1_Msk |
| #define | DMA2D_CR_START_Pos (0U) |
| #define | DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) |
| #define | DMA2D_CR_START DMA2D_CR_START_Msk |
| #define | DMA2D_CR_SUSP_Pos (1U) |
| #define | DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) |
| #define | DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk |
| #define | DMA2D_CR_ABORT_Pos (2U) |
| #define | DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) |
| #define | DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk |
| #define | DMA2D_CR_LOM_Pos (6U) |
| #define | DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos) |
| #define | DMA2D_CR_LOM DMA2D_CR_LOM_Msk |
| #define | DMA2D_CR_TEIE_Pos (8U) |
| #define | DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) |
| #define | DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk |
| #define | DMA2D_CR_TCIE_Pos (9U) |
| #define | DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) |
| #define | DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk |
| #define | DMA2D_CR_TWIE_Pos (10U) |
| #define | DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) |
| #define | DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk |
| #define | DMA2D_CR_CAEIE_Pos (11U) |
| #define | DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) |
| #define | DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk |
| #define | DMA2D_CR_CTCIE_Pos (12U) |
| #define | DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) |
| #define | DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk |
| #define | DMA2D_CR_CEIE_Pos (13U) |
| #define | DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) |
| #define | DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk |
| #define | DMA2D_CR_MODE_Pos (16U) |
| #define | DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos) |
| #define | DMA2D_CR_MODE DMA2D_CR_MODE_Msk |
| #define | DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) |
| #define | DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) |
| #define | DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos) |
| #define | DMA2D_ISR_TEIF_Pos (0U) |
| #define | DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) |
| #define | DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk |
| #define | DMA2D_ISR_TCIF_Pos (1U) |
| #define | DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) |
| #define | DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk |
| #define | DMA2D_ISR_TWIF_Pos (2U) |
| #define | DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) |
| #define | DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk |
| #define | DMA2D_ISR_CAEIF_Pos (3U) |
| #define | DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) |
| #define | DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk |
| #define | DMA2D_ISR_CTCIF_Pos (4U) |
| #define | DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) |
| #define | DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk |
| #define | DMA2D_ISR_CEIF_Pos (5U) |
| #define | DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) |
| #define | DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk |
| #define | DMA2D_IFCR_CTEIF_Pos (0U) |
| #define | DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) |
| #define | DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk |
| #define | DMA2D_IFCR_CTCIF_Pos (1U) |
| #define | DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) |
| #define | DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk |
| #define | DMA2D_IFCR_CTWIF_Pos (2U) |
| #define | DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) |
| #define | DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk |
| #define | DMA2D_IFCR_CAECIF_Pos (3U) |
| #define | DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) |
| #define | DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk |
| #define | DMA2D_IFCR_CCTCIF_Pos (4U) |
| #define | DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) |
| #define | DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk |
| #define | DMA2D_IFCR_CCEIF_Pos (5U) |
| #define | DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) |
| #define | DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk |
| #define | DMA2D_FGMAR_MA_Pos (0U) |
| #define | DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) |
| #define | DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk |
| #define | DMA2D_FGOR_LO_Pos (0U) |
| #define | DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos) |
| #define | DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk |
| #define | DMA2D_BGMAR_MA_Pos (0U) |
| #define | DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) |
| #define | DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk |
| #define | DMA2D_BGOR_LO_Pos (0U) |
| #define | DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos) |
| #define | DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk |
| #define | DMA2D_FGPFCCR_CM_Pos (0U) |
| #define | DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) |
| #define | DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk |
| #define | DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) |
| #define | DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) |
| #define | DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) |
| #define | DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) |
| #define | DMA2D_FGPFCCR_CCM_Pos (4U) |
| #define | DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) |
| #define | DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk |
| #define | DMA2D_FGPFCCR_START_Pos (5U) |
| #define | DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) |
| #define | DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk |
| #define | DMA2D_FGPFCCR_CS_Pos (8U) |
| #define | DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) |
| #define | DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk |
| #define | DMA2D_FGPFCCR_AM_Pos (16U) |
| #define | DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) |
| #define | DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk |
| #define | DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) |
| #define | DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) |
| #define | DMA2D_FGPFCCR_CSS_Pos (18U) |
| #define | DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) |
| #define | DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */ |
| #define | DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) |
| #define | DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) |
| #define | DMA2D_FGPFCCR_AI_Pos (20U) |
| #define | DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) |
| #define | DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk |
| #define | DMA2D_FGPFCCR_RBS_Pos (21U) |
| #define | DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) |
| #define | DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk |
| #define | DMA2D_FGPFCCR_ALPHA_Pos (24U) |
| #define | DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) |
| #define | DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk |
| #define | DMA2D_FGCOLR_BLUE_Pos (0U) |
| #define | DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) |
| #define | DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk |
| #define | DMA2D_FGCOLR_GREEN_Pos (8U) |
| #define | DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) |
| #define | DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk |
| #define | DMA2D_FGCOLR_RED_Pos (16U) |
| #define | DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) |
| #define | DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk |
| #define | DMA2D_BGPFCCR_CM_Pos (0U) |
| #define | DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) |
| #define | DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk |
| #define | DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) |
| #define | DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) |
| #define | DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) |
| #define | DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos) |
| #define | DMA2D_BGPFCCR_CCM_Pos (4U) |
| #define | DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) |
| #define | DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk |
| #define | DMA2D_BGPFCCR_START_Pos (5U) |
| #define | DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) |
| #define | DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk |
| #define | DMA2D_BGPFCCR_CS_Pos (8U) |
| #define | DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) |
| #define | DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk |
| #define | DMA2D_BGPFCCR_AM_Pos (16U) |
| #define | DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) |
| #define | DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk |
| #define | DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) |
| #define | DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) |
| #define | DMA2D_BGPFCCR_AI_Pos (20U) |
| #define | DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) |
| #define | DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk |
| #define | DMA2D_BGPFCCR_RBS_Pos (21U) |
| #define | DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) |
| #define | DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk |
| #define | DMA2D_BGPFCCR_ALPHA_Pos (24U) |
| #define | DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) |
| #define | DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk |
| #define | DMA2D_BGCOLR_BLUE_Pos (0U) |
| #define | DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) |
| #define | DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk |
| #define | DMA2D_BGCOLR_GREEN_Pos (8U) |
| #define | DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) |
| #define | DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk |
| #define | DMA2D_BGCOLR_RED_Pos (16U) |
| #define | DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) |
| #define | DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk |
| #define | DMA2D_FGCMAR_MA_Pos (0U) |
| #define | DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) |
| #define | DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk |
| #define | DMA2D_BGCMAR_MA_Pos (0U) |
| #define | DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) |
| #define | DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk |
| #define | DMA2D_OPFCCR_CM_Pos (0U) |
| #define | DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) |
| #define | DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk |
| #define | DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) |
| #define | DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) |
| #define | DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) |
| #define | DMA2D_OPFCCR_SB_Pos (8U) |
| #define | DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos) |
| #define | DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk |
| #define | DMA2D_OPFCCR_AI_Pos (20U) |
| #define | DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) |
| #define | DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk |
| #define | DMA2D_OPFCCR_RBS_Pos (21U) |
| #define | DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) |
| #define | DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk |
| #define | DMA2D_OCOLR_BLUE_1_Pos (0U) |
| #define | DMA2D_OCOLR_BLUE_1_Msk (0xFFUL << DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/ |
| #define | DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk |
| #define | DMA2D_OCOLR_GREEN_1_Pos (8U) |
| #define | DMA2D_OCOLR_GREEN_1_Msk (0xFFUL << DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/ |
| #define | DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk |
| #define | DMA2D_OCOLR_RED_1_Pos (16U) |
| #define | DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */ |
| #define | DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk |
| #define | DMA2D_OCOLR_ALPHA_1_Pos (24U) |
| #define | DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/ |
| #define | DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk |
| #define | DMA2D_OCOLR_BLUE_2_Pos (0U) |
| #define | DMA2D_OCOLR_BLUE_2_Msk (0x1FUL << DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/ |
| #define | DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk |
| #define | DMA2D_OCOLR_GREEN_2_Pos (5U) |
| #define | DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */ |
| #define | DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk |
| #define | DMA2D_OCOLR_RED_2_Pos (11U) |
| #define | DMA2D_OCOLR_RED_2_Msk (0xF8UL << DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/ |
| #define | DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk |
| #define | DMA2D_OCOLR_BLUE_3_Pos (0U) |
| #define | DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/ |
| #define | DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk |
| #define | DMA2D_OCOLR_GREEN_3_Pos (5U) |
| #define | DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/ |
| #define | DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk |
| #define | DMA2D_OCOLR_RED_3_Pos (10U) |
| #define | DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/ |
| #define | DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk |
| #define | DMA2D_OCOLR_ALPHA_3_Pos (15U) |
| #define | DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/ |
| #define | DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk |
| #define | DMA2D_OCOLR_BLUE_4_Pos (0U) |
| #define | DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/ |
| #define | DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk |
| #define | DMA2D_OCOLR_GREEN_4_Pos (4U) |
| #define | DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/ |
| #define | DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk |
| #define | DMA2D_OCOLR_RED_4_Pos (8U) |
| #define | DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/ |
| #define | DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk |
| #define | DMA2D_OCOLR_ALPHA_4_Pos (12U) |
| #define | DMA2D_OCOLR_ALPHA_4_Msk (0xF << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/ |
| #define | DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk |
| #define | DMA2D_OMAR_MA_Pos (0U) |
| #define | DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) |
| #define | DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk |
| #define | DMA2D_OOR_LO_Pos (0U) |
| #define | DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos) |
| #define | DMA2D_OOR_LO DMA2D_OOR_LO_Msk |
| #define | DMA2D_NLR_NL_Pos (0U) |
| #define | DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) |
| #define | DMA2D_NLR_NL DMA2D_NLR_NL_Msk |
| #define | DMA2D_NLR_PL_Pos (16U) |
| #define | DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) |
| #define | DMA2D_NLR_PL DMA2D_NLR_PL_Msk |
| #define | DMA2D_LWR_LW_Pos (0U) |
| #define | DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) |
| #define | DMA2D_LWR_LW DMA2D_LWR_LW_Msk |
| #define | DMA2D_AMTCR_EN_Pos (0U) |
| #define | DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) |
| #define | DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk |
| #define | DMA2D_AMTCR_DT_Pos (8U) |
| #define | DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) |
| #define | DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk |
| #define | DSI_VR_Pos (0U) |
| #define | DSI_VR_Msk (0xFFFFFFFFUL << DSI_VR_Pos) |
| #define | DSI_VR DSI_VR_Msk |
| #define | DSI_CR_EN_Pos (0U) |
| #define | DSI_CR_EN_Msk (0x1UL << DSI_CR_EN_Pos) |
| #define | DSI_CR_EN DSI_CR_EN_Msk |
| #define | DSI_CCR_TXECKDIV_Pos (0U) |
| #define | DSI_CCR_TXECKDIV_Msk (0xFFUL << DSI_CCR_TXECKDIV_Pos) |
| #define | DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk |
| #define | DSI_CCR_TXECKDIV0_Pos (0U) |
| #define | DSI_CCR_TXECKDIV0_Msk (0x1UL << DSI_CCR_TXECKDIV0_Pos) |
| #define | DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk |
| #define | DSI_CCR_TXECKDIV1_Pos (1U) |
| #define | DSI_CCR_TXECKDIV1_Msk (0x1UL << DSI_CCR_TXECKDIV1_Pos) |
| #define | DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk |
| #define | DSI_CCR_TXECKDIV2_Pos (2U) |
| #define | DSI_CCR_TXECKDIV2_Msk (0x1UL << DSI_CCR_TXECKDIV2_Pos) |
| #define | DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk |
| #define | DSI_CCR_TXECKDIV3_Pos (3U) |
| #define | DSI_CCR_TXECKDIV3_Msk (0x1UL << DSI_CCR_TXECKDIV3_Pos) |
| #define | DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk |
| #define | DSI_CCR_TXECKDIV4_Pos (4U) |
| #define | DSI_CCR_TXECKDIV4_Msk (0x1UL << DSI_CCR_TXECKDIV4_Pos) |
| #define | DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk |
| #define | DSI_CCR_TXECKDIV5_Pos (5U) |
| #define | DSI_CCR_TXECKDIV5_Msk (0x1UL << DSI_CCR_TXECKDIV5_Pos) |
| #define | DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk |
| #define | DSI_CCR_TXECKDIV6_Pos (6U) |
| #define | DSI_CCR_TXECKDIV6_Msk (0x1UL << DSI_CCR_TXECKDIV6_Pos) |
| #define | DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk |
| #define | DSI_CCR_TXECKDIV7_Pos (7U) |
| #define | DSI_CCR_TXECKDIV7_Msk (0x1UL << DSI_CCR_TXECKDIV7_Pos) |
| #define | DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk |
| #define | DSI_CCR_TOCKDIV_Pos (8U) |
| #define | DSI_CCR_TOCKDIV_Msk (0xFFUL << DSI_CCR_TOCKDIV_Pos) |
| #define | DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk |
| #define | DSI_CCR_TOCKDIV0_Pos (8U) |
| #define | DSI_CCR_TOCKDIV0_Msk (0x1UL << DSI_CCR_TOCKDIV0_Pos) |
| #define | DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk |
| #define | DSI_CCR_TOCKDIV1_Pos (9U) |
| #define | DSI_CCR_TOCKDIV1_Msk (0x1UL << DSI_CCR_TOCKDIV1_Pos) |
| #define | DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk |
| #define | DSI_CCR_TOCKDIV2_Pos (10U) |
| #define | DSI_CCR_TOCKDIV2_Msk (0x1UL << DSI_CCR_TOCKDIV2_Pos) |
| #define | DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk |
| #define | DSI_CCR_TOCKDIV3_Pos (11U) |
| #define | DSI_CCR_TOCKDIV3_Msk (0x1UL << DSI_CCR_TOCKDIV3_Pos) |
| #define | DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk |
| #define | DSI_CCR_TOCKDIV4_Pos (12U) |
| #define | DSI_CCR_TOCKDIV4_Msk (0x1UL << DSI_CCR_TOCKDIV4_Pos) |
| #define | DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk |
| #define | DSI_CCR_TOCKDIV5_Pos (13U) |
| #define | DSI_CCR_TOCKDIV5_Msk (0x1UL << DSI_CCR_TOCKDIV5_Pos) |
| #define | DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk |
| #define | DSI_CCR_TOCKDIV6_Pos (14U) |
| #define | DSI_CCR_TOCKDIV6_Msk (0x1UL << DSI_CCR_TOCKDIV6_Pos) |
| #define | DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk |
| #define | DSI_CCR_TOCKDIV7_Pos (15U) |
| #define | DSI_CCR_TOCKDIV7_Msk (0x1UL << DSI_CCR_TOCKDIV7_Pos) |
| #define | DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk |
| #define | DSI_LVCIDR_VCID_Pos (0U) |
| #define | DSI_LVCIDR_VCID_Msk (0x3UL << DSI_LVCIDR_VCID_Pos) |
| #define | DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk |
| #define | DSI_LVCIDR_VCID0_Pos (0U) |
| #define | DSI_LVCIDR_VCID0_Msk (0x1UL << DSI_LVCIDR_VCID0_Pos) |
| #define | DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk |
| #define | DSI_LVCIDR_VCID1_Pos (1U) |
| #define | DSI_LVCIDR_VCID1_Msk (0x1UL << DSI_LVCIDR_VCID1_Pos) |
| #define | DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk |
| #define | DSI_LCOLCR_COLC_Pos (0U) |
| #define | DSI_LCOLCR_COLC_Msk (0xFUL << DSI_LCOLCR_COLC_Pos) |
| #define | DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk |
| #define | DSI_LCOLCR_COLC0_Pos (0U) |
| #define | DSI_LCOLCR_COLC0_Msk (0x1UL << DSI_LCOLCR_COLC0_Pos) |
| #define | DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk |
| #define | DSI_LCOLCR_COLC1_Pos (1U) |
| #define | DSI_LCOLCR_COLC1_Msk (0x1UL << DSI_LCOLCR_COLC1_Pos) |
| #define | DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk |
| #define | DSI_LCOLCR_COLC2_Pos (2U) |
| #define | DSI_LCOLCR_COLC2_Msk (0x1UL << DSI_LCOLCR_COLC2_Pos) |
| #define | DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk |
| #define | DSI_LCOLCR_COLC3_Pos (3U) |
| #define | DSI_LCOLCR_COLC3_Msk (0x1UL << DSI_LCOLCR_COLC3_Pos) |
| #define | DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk |
| #define | DSI_LCOLCR_LPE_Pos (8U) |
| #define | DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos) |
| #define | DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk |
| #define | DSI_LPCR_DEP_Pos (0U) |
| #define | DSI_LPCR_DEP_Msk (0x1UL << DSI_LPCR_DEP_Pos) |
| #define | DSI_LPCR_DEP DSI_LPCR_DEP_Msk |
| #define | DSI_LPCR_VSP_Pos (1U) |
| #define | DSI_LPCR_VSP_Msk (0x1UL << DSI_LPCR_VSP_Pos) |
| #define | DSI_LPCR_VSP DSI_LPCR_VSP_Msk |
| #define | DSI_LPCR_HSP_Pos (2U) |
| #define | DSI_LPCR_HSP_Msk (0x1UL << DSI_LPCR_HSP_Pos) |
| #define | DSI_LPCR_HSP DSI_LPCR_HSP_Msk |
| #define | DSI_LPMCR_VLPSIZE_Pos (0U) |
| #define | DSI_LPMCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCR_VLPSIZE_Pos) |
| #define | DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk |
| #define | DSI_LPMCR_VLPSIZE0_Pos (0U) |
| #define | DSI_LPMCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCR_VLPSIZE0_Pos) |
| #define | DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk |
| #define | DSI_LPMCR_VLPSIZE1_Pos (1U) |
| #define | DSI_LPMCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCR_VLPSIZE1_Pos) |
| #define | DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk |
| #define | DSI_LPMCR_VLPSIZE2_Pos (2U) |
| #define | DSI_LPMCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCR_VLPSIZE2_Pos) |
| #define | DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk |
| #define | DSI_LPMCR_VLPSIZE3_Pos (3U) |
| #define | DSI_LPMCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCR_VLPSIZE3_Pos) |
| #define | DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk |
| #define | DSI_LPMCR_VLPSIZE4_Pos (4U) |
| #define | DSI_LPMCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCR_VLPSIZE4_Pos) |
| #define | DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk |
| #define | DSI_LPMCR_VLPSIZE5_Pos (5U) |
| #define | DSI_LPMCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCR_VLPSIZE5_Pos) |
| #define | DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk |
| #define | DSI_LPMCR_VLPSIZE6_Pos (6U) |
| #define | DSI_LPMCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCR_VLPSIZE6_Pos) |
| #define | DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk |
| #define | DSI_LPMCR_VLPSIZE7_Pos (7U) |
| #define | DSI_LPMCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCR_VLPSIZE7_Pos) |
| #define | DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk |
| #define | DSI_LPMCR_LPSIZE_Pos (16U) |
| #define | DSI_LPMCR_LPSIZE_Msk (0xFFUL << DSI_LPMCR_LPSIZE_Pos) |
| #define | DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk |
| #define | DSI_LPMCR_LPSIZE0_Pos (16U) |
| #define | DSI_LPMCR_LPSIZE0_Msk (0x1UL << DSI_LPMCR_LPSIZE0_Pos) |
| #define | DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk |
| #define | DSI_LPMCR_LPSIZE1_Pos (17U) |
| #define | DSI_LPMCR_LPSIZE1_Msk (0x1UL << DSI_LPMCR_LPSIZE1_Pos) |
| #define | DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk |
| #define | DSI_LPMCR_LPSIZE2_Pos (18U) |
| #define | DSI_LPMCR_LPSIZE2_Msk (0x1UL << DSI_LPMCR_LPSIZE2_Pos) |
| #define | DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk |
| #define | DSI_LPMCR_LPSIZE3_Pos (19U) |
| #define | DSI_LPMCR_LPSIZE3_Msk (0x1UL << DSI_LPMCR_LPSIZE3_Pos) |
| #define | DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk |
| #define | DSI_LPMCR_LPSIZE4_Pos (20U) |
| #define | DSI_LPMCR_LPSIZE4_Msk (0x1UL << DSI_LPMCR_LPSIZE4_Pos) |
| #define | DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk |
| #define | DSI_LPMCR_LPSIZE5_Pos (21U) |
| #define | DSI_LPMCR_LPSIZE5_Msk (0x1UL << DSI_LPMCR_LPSIZE5_Pos) |
| #define | DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk |
| #define | DSI_LPMCR_LPSIZE6_Pos (22U) |
| #define | DSI_LPMCR_LPSIZE6_Msk (0x1UL << DSI_LPMCR_LPSIZE6_Pos) |
| #define | DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk |
| #define | DSI_LPMCR_LPSIZE7_Pos (23U) |
| #define | DSI_LPMCR_LPSIZE7_Msk (0x1UL << DSI_LPMCR_LPSIZE7_Pos) |
| #define | DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk |
| #define | DSI_PCR_ETTXE_Pos (0U) |
| #define | DSI_PCR_ETTXE_Msk (0x1UL << DSI_PCR_ETTXE_Pos) |
| #define | DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk |
| #define | DSI_PCR_ETRXE_Pos (1U) |
| #define | DSI_PCR_ETRXE_Msk (0x1UL << DSI_PCR_ETRXE_Pos) |
| #define | DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk |
| #define | DSI_PCR_BTAE_Pos (2U) |
| #define | DSI_PCR_BTAE_Msk (0x1UL << DSI_PCR_BTAE_Pos) |
| #define | DSI_PCR_BTAE DSI_PCR_BTAE_Msk |
| #define | DSI_PCR_ECCRXE_Pos (3U) |
| #define | DSI_PCR_ECCRXE_Msk (0x1UL << DSI_PCR_ECCRXE_Pos) |
| #define | DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk |
| #define | DSI_PCR_CRCRXE_Pos (4U) |
| #define | DSI_PCR_CRCRXE_Msk (0x1UL << DSI_PCR_CRCRXE_Pos) |
| #define | DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk |
| #define | DSI_PCR_ETTXLPE_Pos (5U) |
| #define | DSI_PCR_ETTXLPE_Msk (0x1UL << DSI_PCR_ETTXLPE_Pos) |
| #define | DSI_PCR_ETTXLPE DSI_PCR_ETTXLPE_Msk |
| #define | DSI_GVCIDR_VCIDRX_Pos (0U) |
| #define | DSI_GVCIDR_VCIDRX_Msk (0x3UL << DSI_GVCIDR_VCIDRX_Pos) |
| #define | DSI_GVCIDR_VCIDRX DSI_GVCIDR_VCIDRX_Msk |
| #define | DSI_GVCIDR_VCIDRX0_Pos (0U) |
| #define | DSI_GVCIDR_VCIDRX0_Msk (0x1UL << DSI_GVCIDR_VCIDRX0_Pos) |
| #define | DSI_GVCIDR_VCIDRX0 DSI_GVCIDR_VCIDRX0_Msk |
| #define | DSI_GVCIDR_VCIDRX1_Pos (1U) |
| #define | DSI_GVCIDR_VCIDRX1_Msk (0x1UL << DSI_GVCIDR_VCIDRX1_Pos) |
| #define | DSI_GVCIDR_VCIDRX1 DSI_GVCIDR_VCIDRX1_Msk |
| #define | DSI_GVCIDR_VCIDTX_Pos (16U) |
| #define | DSI_GVCIDR_VCIDTX_Msk (0x3UL << DSI_GVCIDR_VCIDTX_Pos) |
| #define | DSI_GVCIDR_VCIDTX DSI_GVCIDR_VCIDTX_Msk |
| #define | DSI_GVCIDR_VCIDTX0_Pos (16U) |
| #define | DSI_GVCIDR_VCIDTX0_Msk (0x1UL << DSI_GVCIDR_VCIDTX0_Pos) |
| #define | DSI_GVCIDR_VCIDTX0 DSI_GVCIDR_VCIDTX0_Msk |
| #define | DSI_GVCIDR_VCIDTX1_Pos (17U) |
| #define | DSI_GVCIDR_VCIDTX1_Msk (0x1UL << DSI_GVCIDR_VCIDRT1_Pos) |
| #define | DSI_GVCIDR_VCIDTX1 DSI_GVCIDR_VCIDRT1_Msk |
| #define | DSI_MCR_CMDM_Pos (0U) |
| #define | DSI_MCR_CMDM_Msk (0x1UL << DSI_MCR_CMDM_Pos) |
| #define | DSI_MCR_CMDM DSI_MCR_CMDM_Msk |
| #define | DSI_VMCR_VMT_Pos (0U) |
| #define | DSI_VMCR_VMT_Msk (0x3UL << DSI_VMCR_VMT_Pos) |
| #define | DSI_VMCR_VMT DSI_VMCR_VMT_Msk |
| #define | DSI_VMCR_VMT0_Pos (0U) |
| #define | DSI_VMCR_VMT0_Msk (0x1UL << DSI_VMCR_VMT0_Pos) |
| #define | DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk |
| #define | DSI_VMCR_VMT1_Pos (1U) |
| #define | DSI_VMCR_VMT1_Msk (0x1UL << DSI_VMCR_VMT1_Pos) |
| #define | DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk |
| #define | DSI_VMCR_LPVSAE_Pos (8U) |
| #define | DSI_VMCR_LPVSAE_Msk (0x1UL << DSI_VMCR_LPVSAE_Pos) |
| #define | DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk |
| #define | DSI_VMCR_LPVBPE_Pos (9U) |
| #define | DSI_VMCR_LPVBPE_Msk (0x1UL << DSI_VMCR_LPVBPE_Pos) |
| #define | DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk |
| #define | DSI_VMCR_LPVFPE_Pos (10U) |
| #define | DSI_VMCR_LPVFPE_Msk (0x1UL << DSI_VMCR_LPVFPE_Pos) |
| #define | DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk |
| #define | DSI_VMCR_LPVAE_Pos (11U) |
| #define | DSI_VMCR_LPVAE_Msk (0x1UL << DSI_VMCR_LPVAE_Pos) |
| #define | DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk |
| #define | DSI_VMCR_LPHBPE_Pos (12U) |
| #define | DSI_VMCR_LPHBPE_Msk (0x1UL << DSI_VMCR_LPHBPE_Pos) |
| #define | DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk |
| #define | DSI_VMCR_LPHFPE_Pos (13U) |
| #define | DSI_VMCR_LPHFPE_Msk (0x1UL << DSI_VMCR_LPHFPE_Pos) |
| #define | DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk |
| #define | DSI_VMCR_FBTAAE_Pos (14U) |
| #define | DSI_VMCR_FBTAAE_Msk (0x1UL << DSI_VMCR_FBTAAE_Pos) |
| #define | DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk |
| #define | DSI_VMCR_LPCE_Pos (15U) |
| #define | DSI_VMCR_LPCE_Msk (0x1UL << DSI_VMCR_LPCE_Pos) |
| #define | DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk |
| #define | DSI_VMCR_PGE_Pos (16U) |
| #define | DSI_VMCR_PGE_Msk (0x1UL << DSI_VMCR_PGE_Pos) |
| #define | DSI_VMCR_PGE DSI_VMCR_PGE_Msk |
| #define | DSI_VMCR_PGM_Pos (20U) |
| #define | DSI_VMCR_PGM_Msk (0x1UL << DSI_VMCR_PGM_Pos) |
| #define | DSI_VMCR_PGM DSI_VMCR_PGM_Msk |
| #define | DSI_VMCR_PGO_Pos (24U) |
| #define | DSI_VMCR_PGO_Msk (0x1UL << DSI_VMCR_PGO_Pos) |
| #define | DSI_VMCR_PGO DSI_VMCR_PGO_Msk |
| #define | DSI_VPCR_VPSIZE_Pos (0U) |
| #define | DSI_VPCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCR_VPSIZE_Pos) |
| #define | DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk |
| #define | DSI_VPCR_VPSIZE0_Pos (0U) |
| #define | DSI_VPCR_VPSIZE0_Msk (0x1UL << DSI_VPCR_VPSIZE0_Pos) |
| #define | DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk |
| #define | DSI_VPCR_VPSIZE1_Pos (1U) |
| #define | DSI_VPCR_VPSIZE1_Msk (0x1UL << DSI_VPCR_VPSIZE1_Pos) |
| #define | DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk |
| #define | DSI_VPCR_VPSIZE2_Pos (2U) |
| #define | DSI_VPCR_VPSIZE2_Msk (0x1UL << DSI_VPCR_VPSIZE2_Pos) |
| #define | DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk |
| #define | DSI_VPCR_VPSIZE3_Pos (3U) |
| #define | DSI_VPCR_VPSIZE3_Msk (0x1UL << DSI_VPCR_VPSIZE3_Pos) |
| #define | DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk |
| #define | DSI_VPCR_VPSIZE4_Pos (4U) |
| #define | DSI_VPCR_VPSIZE4_Msk (0x1UL << DSI_VPCR_VPSIZE4_Pos) |
| #define | DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk |
| #define | DSI_VPCR_VPSIZE5_Pos (5U) |
| #define | DSI_VPCR_VPSIZE5_Msk (0x1UL << DSI_VPCR_VPSIZE5_Pos) |
| #define | DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk |
| #define | DSI_VPCR_VPSIZE6_Pos (6U) |
| #define | DSI_VPCR_VPSIZE6_Msk (0x1UL << DSI_VPCR_VPSIZE6_Pos) |
| #define | DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk |
| #define | DSI_VPCR_VPSIZE7_Pos (7U) |
| #define | DSI_VPCR_VPSIZE7_Msk (0x1UL << DSI_VPCR_VPSIZE7_Pos) |
| #define | DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk |
| #define | DSI_VPCR_VPSIZE8_Pos (8U) |
| #define | DSI_VPCR_VPSIZE8_Msk (0x1UL << DSI_VPCR_VPSIZE8_Pos) |
| #define | DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk |
| #define | DSI_VPCR_VPSIZE9_Pos (9U) |
| #define | DSI_VPCR_VPSIZE9_Msk (0x1UL << DSI_VPCR_VPSIZE9_Pos) |
| #define | DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk |
| #define | DSI_VPCR_VPSIZE10_Pos (10U) |
| #define | DSI_VPCR_VPSIZE10_Msk (0x1UL << DSI_VPCR_VPSIZE10_Pos) |
| #define | DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk |
| #define | DSI_VPCR_VPSIZE11_Pos (11U) |
| #define | DSI_VPCR_VPSIZE11_Msk (0x1UL << DSI_VPCR_VPSIZE11_Pos) |
| #define | DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk |
| #define | DSI_VPCR_VPSIZE12_Pos (12U) |
| #define | DSI_VPCR_VPSIZE12_Msk (0x1UL << DSI_VPCR_VPSIZE12_Pos) |
| #define | DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk |
| #define | DSI_VPCR_VPSIZE13_Pos (13U) |
| #define | DSI_VPCR_VPSIZE13_Msk (0x1UL << DSI_VPCR_VPSIZE13_Pos) |
| #define | DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk |
| #define | DSI_VCCR_NUMC_Pos (0U) |
| #define | DSI_VCCR_NUMC_Msk (0x1FFFUL << DSI_VCCR_NUMC_Pos) |
| #define | DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk |
| #define | DSI_VCCR_NUMC0_Pos (0U) |
| #define | DSI_VCCR_NUMC0_Msk (0x1UL << DSI_VCCR_NUMC0_Pos) |
| #define | DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk |
| #define | DSI_VCCR_NUMC1_Pos (1U) |
| #define | DSI_VCCR_NUMC1_Msk (0x1UL << DSI_VCCR_NUMC1_Pos) |
| #define | DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk |
| #define | DSI_VCCR_NUMC2_Pos (2U) |
| #define | DSI_VCCR_NUMC2_Msk (0x1UL << DSI_VCCR_NUMC2_Pos) |
| #define | DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk |
| #define | DSI_VCCR_NUMC3_Pos (3U) |
| #define | DSI_VCCR_NUMC3_Msk (0x1UL << DSI_VCCR_NUMC3_Pos) |
| #define | DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk |
| #define | DSI_VCCR_NUMC4_Pos (4U) |
| #define | DSI_VCCR_NUMC4_Msk (0x1UL << DSI_VCCR_NUMC4_Pos) |
| #define | DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk |
| #define | DSI_VCCR_NUMC5_Pos (5U) |
| #define | DSI_VCCR_NUMC5_Msk (0x1UL << DSI_VCCR_NUMC5_Pos) |
| #define | DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk |
| #define | DSI_VCCR_NUMC6_Pos (6U) |
| #define | DSI_VCCR_NUMC6_Msk (0x1UL << DSI_VCCR_NUMC6_Pos) |
| #define | DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk |
| #define | DSI_VCCR_NUMC7_Pos (7U) |
| #define | DSI_VCCR_NUMC7_Msk (0x1UL << DSI_VCCR_NUMC7_Pos) |
| #define | DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk |
| #define | DSI_VCCR_NUMC8_Pos (8U) |
| #define | DSI_VCCR_NUMC8_Msk (0x1UL << DSI_VCCR_NUMC8_Pos) |
| #define | DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk |
| #define | DSI_VCCR_NUMC9_Pos (9U) |
| #define | DSI_VCCR_NUMC9_Msk (0x1UL << DSI_VCCR_NUMC9_Pos) |
| #define | DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk |
| #define | DSI_VCCR_NUMC10_Pos (10U) |
| #define | DSI_VCCR_NUMC10_Msk (0x1UL << DSI_VCCR_NUMC10_Pos) |
| #define | DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk |
| #define | DSI_VCCR_NUMC11_Pos (11U) |
| #define | DSI_VCCR_NUMC11_Msk (0x1UL << DSI_VCCR_NUMC11_Pos) |
| #define | DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk |
| #define | DSI_VCCR_NUMC12_Pos (12U) |
| #define | DSI_VCCR_NUMC12_Msk (0x1UL << DSI_VCCR_NUMC12_Pos) |
| #define | DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk |
| #define | DSI_VNPCR_NPSIZE_Pos (0U) |
| #define | DSI_VNPCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCR_NPSIZE_Pos) |
| #define | DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk |
| #define | DSI_VNPCR_NPSIZE0_Pos (0U) |
| #define | DSI_VNPCR_NPSIZE0_Msk (0x1UL << DSI_VNPCR_NPSIZE0_Pos) |
| #define | DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk |
| #define | DSI_VNPCR_NPSIZE1_Pos (1U) |
| #define | DSI_VNPCR_NPSIZE1_Msk (0x1UL << DSI_VNPCR_NPSIZE1_Pos) |
| #define | DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk |
| #define | DSI_VNPCR_NPSIZE2_Pos (2U) |
| #define | DSI_VNPCR_NPSIZE2_Msk (0x1UL << DSI_VNPCR_NPSIZE2_Pos) |
| #define | DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk |
| #define | DSI_VNPCR_NPSIZE3_Pos (3U) |
| #define | DSI_VNPCR_NPSIZE3_Msk (0x1UL << DSI_VNPCR_NPSIZE3_Pos) |
| #define | DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk |
| #define | DSI_VNPCR_NPSIZE4_Pos (4U) |
| #define | DSI_VNPCR_NPSIZE4_Msk (0x1UL << DSI_VNPCR_NPSIZE4_Pos) |
| #define | DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk |
| #define | DSI_VNPCR_NPSIZE5_Pos (5U) |
| #define | DSI_VNPCR_NPSIZE5_Msk (0x1UL << DSI_VNPCR_NPSIZE5_Pos) |
| #define | DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk |
| #define | DSI_VNPCR_NPSIZE6_Pos (6U) |
| #define | DSI_VNPCR_NPSIZE6_Msk (0x1UL << DSI_VNPCR_NPSIZE6_Pos) |
| #define | DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk |
| #define | DSI_VNPCR_NPSIZE7_Pos (7U) |
| #define | DSI_VNPCR_NPSIZE7_Msk (0x1UL << DSI_VNPCR_NPSIZE7_Pos) |
| #define | DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk |
| #define | DSI_VNPCR_NPSIZE8_Pos (8U) |
| #define | DSI_VNPCR_NPSIZE8_Msk (0x1UL << DSI_VNPCR_NPSIZE8_Pos) |
| #define | DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk |
| #define | DSI_VNPCR_NPSIZE9_Pos (9U) |
| #define | DSI_VNPCR_NPSIZE9_Msk (0x1UL << DSI_VNPCR_NPSIZE9_Pos) |
| #define | DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk |
| #define | DSI_VNPCR_NPSIZE10_Pos (10U) |
| #define | DSI_VNPCR_NPSIZE10_Msk (0x1UL << DSI_VNPCR_NPSIZE10_Pos) |
| #define | DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk |
| #define | DSI_VNPCR_NPSIZE11_Pos (11U) |
| #define | DSI_VNPCR_NPSIZE11_Msk (0x1UL << DSI_VNPCR_NPSIZE11_Pos) |
| #define | DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk |
| #define | DSI_VNPCR_NPSIZE12_Pos (12U) |
| #define | DSI_VNPCR_NPSIZE12_Msk (0x1UL << DSI_VNPCR_NPSIZE12_Pos) |
| #define | DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk |
| #define | DSI_VHSACR_HSA_Pos (0U) |
| #define | DSI_VHSACR_HSA_Msk (0xFFFUL << DSI_VHSACR_HSA_Pos) |
| #define | DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk |
| #define | DSI_VHSACR_HSA0_Pos (0U) |
| #define | DSI_VHSACR_HSA0_Msk (0x1UL << DSI_VHSACR_HSA0_Pos) |
| #define | DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk |
| #define | DSI_VHSACR_HSA1_Pos (1U) |
| #define | DSI_VHSACR_HSA1_Msk (0x1UL << DSI_VHSACR_HSA1_Pos) |
| #define | DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk |
| #define | DSI_VHSACR_HSA2_Pos (2U) |
| #define | DSI_VHSACR_HSA2_Msk (0x1UL << DSI_VHSACR_HSA2_Pos) |
| #define | DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk |
| #define | DSI_VHSACR_HSA3_Pos (3U) |
| #define | DSI_VHSACR_HSA3_Msk (0x1UL << DSI_VHSACR_HSA3_Pos) |
| #define | DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk |
| #define | DSI_VHSACR_HSA4_Pos (4U) |
| #define | DSI_VHSACR_HSA4_Msk (0x1UL << DSI_VHSACR_HSA4_Pos) |
| #define | DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk |
| #define | DSI_VHSACR_HSA5_Pos (5U) |
| #define | DSI_VHSACR_HSA5_Msk (0x1UL << DSI_VHSACR_HSA5_Pos) |
| #define | DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk |
| #define | DSI_VHSACR_HSA6_Pos (6U) |
| #define | DSI_VHSACR_HSA6_Msk (0x1UL << DSI_VHSACR_HSA6_Pos) |
| #define | DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk |
| #define | DSI_VHSACR_HSA7_Pos (7U) |
| #define | DSI_VHSACR_HSA7_Msk (0x1UL << DSI_VHSACR_HSA7_Pos) |
| #define | DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk |
| #define | DSI_VHSACR_HSA8_Pos (8U) |
| #define | DSI_VHSACR_HSA8_Msk (0x1UL << DSI_VHSACR_HSA8_Pos) |
| #define | DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk |
| #define | DSI_VHSACR_HSA9_Pos (9U) |
| #define | DSI_VHSACR_HSA9_Msk (0x1UL << DSI_VHSACR_HSA9_Pos) |
| #define | DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk |
| #define | DSI_VHSACR_HSA10_Pos (10U) |
| #define | DSI_VHSACR_HSA10_Msk (0x1UL << DSI_VHSACR_HSA10_Pos) |
| #define | DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk |
| #define | DSI_VHSACR_HSA11_Pos (11U) |
| #define | DSI_VHSACR_HSA11_Msk (0x1UL << DSI_VHSACR_HSA11_Pos) |
| #define | DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk |
| #define | DSI_VHBPCR_HBP_Pos (0U) |
| #define | DSI_VHBPCR_HBP_Msk (0xFFFUL << DSI_VHBPCR_HBP_Pos) |
| #define | DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk |
| #define | DSI_VHBPCR_HBP0_Pos (0U) |
| #define | DSI_VHBPCR_HBP0_Msk (0x1UL << DSI_VHBPCR_HBP0_Pos) |
| #define | DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk |
| #define | DSI_VHBPCR_HBP1_Pos (1U) |
| #define | DSI_VHBPCR_HBP1_Msk (0x1UL << DSI_VHBPCR_HBP1_Pos) |
| #define | DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk |
| #define | DSI_VHBPCR_HBP2_Pos (2U) |
| #define | DSI_VHBPCR_HBP2_Msk (0x1UL << DSI_VHBPCR_HBP2_Pos) |
| #define | DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk |
| #define | DSI_VHBPCR_HBP3_Pos (3U) |
| #define | DSI_VHBPCR_HBP3_Msk (0x1UL << DSI_VHBPCR_HBP3_Pos) |
| #define | DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk |
| #define | DSI_VHBPCR_HBP4_Pos (4U) |
| #define | DSI_VHBPCR_HBP4_Msk (0x1UL << DSI_VHBPCR_HBP4_Pos) |
| #define | DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk |
| #define | DSI_VHBPCR_HBP5_Pos (5U) |
| #define | DSI_VHBPCR_HBP5_Msk (0x1UL << DSI_VHBPCR_HBP5_Pos) |
| #define | DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk |
| #define | DSI_VHBPCR_HBP6_Pos (6U) |
| #define | DSI_VHBPCR_HBP6_Msk (0x1UL << DSI_VHBPCR_HBP6_Pos) |
| #define | DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk |
| #define | DSI_VHBPCR_HBP7_Pos (7U) |
| #define | DSI_VHBPCR_HBP7_Msk (0x1UL << DSI_VHBPCR_HBP7_Pos) |
| #define | DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk |
| #define | DSI_VHBPCR_HBP8_Pos (8U) |
| #define | DSI_VHBPCR_HBP8_Msk (0x1UL << DSI_VHBPCR_HBP8_Pos) |
| #define | DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk |
| #define | DSI_VHBPCR_HBP9_Pos (9U) |
| #define | DSI_VHBPCR_HBP9_Msk (0x1UL << DSI_VHBPCR_HBP9_Pos) |
| #define | DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk |
| #define | DSI_VHBPCR_HBP10_Pos (10U) |
| #define | DSI_VHBPCR_HBP10_Msk (0x1UL << DSI_VHBPCR_HBP10_Pos) |
| #define | DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk |
| #define | DSI_VHBPCR_HBP11_Pos (11U) |
| #define | DSI_VHBPCR_HBP11_Msk (0x1UL << DSI_VHBPCR_HBP11_Pos) |
| #define | DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk |
| #define | DSI_VLCR_HLINE_Pos (0U) |
| #define | DSI_VLCR_HLINE_Msk (0x7FFFUL << DSI_VLCR_HLINE_Pos) |
| #define | DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk |
| #define | DSI_VLCR_HLINE0_Pos (0U) |
| #define | DSI_VLCR_HLINE0_Msk (0x1UL << DSI_VLCR_HLINE0_Pos) |
| #define | DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk |
| #define | DSI_VLCR_HLINE1_Pos (1U) |
| #define | DSI_VLCR_HLINE1_Msk (0x1UL << DSI_VLCR_HLINE1_Pos) |
| #define | DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk |
| #define | DSI_VLCR_HLINE2_Pos (2U) |
| #define | DSI_VLCR_HLINE2_Msk (0x1UL << DSI_VLCR_HLINE2_Pos) |
| #define | DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk |
| #define | DSI_VLCR_HLINE3_Pos (3U) |
| #define | DSI_VLCR_HLINE3_Msk (0x1UL << DSI_VLCR_HLINE3_Pos) |
| #define | DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk |
| #define | DSI_VLCR_HLINE4_Pos (4U) |
| #define | DSI_VLCR_HLINE4_Msk (0x1UL << DSI_VLCR_HLINE4_Pos) |
| #define | DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk |
| #define | DSI_VLCR_HLINE5_Pos (5U) |
| #define | DSI_VLCR_HLINE5_Msk (0x1UL << DSI_VLCR_HLINE5_Pos) |
| #define | DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk |
| #define | DSI_VLCR_HLINE6_Pos (6U) |
| #define | DSI_VLCR_HLINE6_Msk (0x1UL << DSI_VLCR_HLINE6_Pos) |
| #define | DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk |
| #define | DSI_VLCR_HLINE7_Pos (7U) |
| #define | DSI_VLCR_HLINE7_Msk (0x1UL << DSI_VLCR_HLINE7_Pos) |
| #define | DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk |
| #define | DSI_VLCR_HLINE8_Pos (8U) |
| #define | DSI_VLCR_HLINE8_Msk (0x1UL << DSI_VLCR_HLINE8_Pos) |
| #define | DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk |
| #define | DSI_VLCR_HLINE9_Pos (9U) |
| #define | DSI_VLCR_HLINE9_Msk (0x1UL << DSI_VLCR_HLINE9_Pos) |
| #define | DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk |
| #define | DSI_VLCR_HLINE10_Pos (10U) |
| #define | DSI_VLCR_HLINE10_Msk (0x1UL << DSI_VLCR_HLINE10_Pos) |
| #define | DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk |
| #define | DSI_VLCR_HLINE11_Pos (11U) |
| #define | DSI_VLCR_HLINE11_Msk (0x1UL << DSI_VLCR_HLINE11_Pos) |
| #define | DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk |
| #define | DSI_VLCR_HLINE12_Pos (12U) |
| #define | DSI_VLCR_HLINE12_Msk (0x1UL << DSI_VLCR_HLINE12_Pos) |
| #define | DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk |
| #define | DSI_VLCR_HLINE13_Pos (13U) |
| #define | DSI_VLCR_HLINE13_Msk (0x1UL << DSI_VLCR_HLINE13_Pos) |
| #define | DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk |
| #define | DSI_VLCR_HLINE14_Pos (14U) |
| #define | DSI_VLCR_HLINE14_Msk (0x1UL << DSI_VLCR_HLINE14_Pos) |
| #define | DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk |
| #define | DSI_VVSACR_VSA_Pos (0U) |
| #define | DSI_VVSACR_VSA_Msk (0x3FFUL << DSI_VVSACR_VSA_Pos) |
| #define | DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk |
| #define | DSI_VVSACR_VSA0_Pos (0U) |
| #define | DSI_VVSACR_VSA0_Msk (0x1UL << DSI_VVSACR_VSA0_Pos) |
| #define | DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk |
| #define | DSI_VVSACR_VSA1_Pos (1U) |
| #define | DSI_VVSACR_VSA1_Msk (0x1UL << DSI_VVSACR_VSA1_Pos) |
| #define | DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk |
| #define | DSI_VVSACR_VSA2_Pos (2U) |
| #define | DSI_VVSACR_VSA2_Msk (0x1UL << DSI_VVSACR_VSA2_Pos) |
| #define | DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk |
| #define | DSI_VVSACR_VSA3_Pos (3U) |
| #define | DSI_VVSACR_VSA3_Msk (0x1UL << DSI_VVSACR_VSA3_Pos) |
| #define | DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk |
| #define | DSI_VVSACR_VSA4_Pos (4U) |
| #define | DSI_VVSACR_VSA4_Msk (0x1UL << DSI_VVSACR_VSA4_Pos) |
| #define | DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk |
| #define | DSI_VVSACR_VSA5_Pos (5U) |
| #define | DSI_VVSACR_VSA5_Msk (0x1UL << DSI_VVSACR_VSA5_Pos) |
| #define | DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk |
| #define | DSI_VVSACR_VSA6_Pos (6U) |
| #define | DSI_VVSACR_VSA6_Msk (0x1UL << DSI_VVSACR_VSA6_Pos) |
| #define | DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk |
| #define | DSI_VVSACR_VSA7_Pos (7U) |
| #define | DSI_VVSACR_VSA7_Msk (0x1UL << DSI_VVSACR_VSA7_Pos) |
| #define | DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk |
| #define | DSI_VVSACR_VSA8_Pos (8U) |
| #define | DSI_VVSACR_VSA8_Msk (0x1UL << DSI_VVSACR_VSA8_Pos) |
| #define | DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk |
| #define | DSI_VVSACR_VSA9_Pos (9U) |
| #define | DSI_VVSACR_VSA9_Msk (0x1UL << DSI_VVSACR_VSA9_Pos) |
| #define | DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk |
| #define | DSI_VVBPCR_VBP_Pos (0U) |
| #define | DSI_VVBPCR_VBP_Msk (0x3FFUL << DSI_VVBPCR_VBP_Pos) |
| #define | DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk |
| #define | DSI_VVBPCR_VBP0_Pos (0U) |
| #define | DSI_VVBPCR_VBP0_Msk (0x1UL << DSI_VVBPCR_VBP0_Pos) |
| #define | DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk |
| #define | DSI_VVBPCR_VBP1_Pos (1U) |
| #define | DSI_VVBPCR_VBP1_Msk (0x1UL << DSI_VVBPCR_VBP1_Pos) |
| #define | DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk |
| #define | DSI_VVBPCR_VBP2_Pos (2U) |
| #define | DSI_VVBPCR_VBP2_Msk (0x1UL << DSI_VVBPCR_VBP2_Pos) |
| #define | DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk |
| #define | DSI_VVBPCR_VBP3_Pos (3U) |
| #define | DSI_VVBPCR_VBP3_Msk (0x1UL << DSI_VVBPCR_VBP3_Pos) |
| #define | DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk |
| #define | DSI_VVBPCR_VBP4_Pos (4U) |
| #define | DSI_VVBPCR_VBP4_Msk (0x1UL << DSI_VVBPCR_VBP4_Pos) |
| #define | DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk |
| #define | DSI_VVBPCR_VBP5_Pos (5U) |
| #define | DSI_VVBPCR_VBP5_Msk (0x1UL << DSI_VVBPCR_VBP5_Pos) |
| #define | DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk |
| #define | DSI_VVBPCR_VBP6_Pos (6U) |
| #define | DSI_VVBPCR_VBP6_Msk (0x1UL << DSI_VVBPCR_VBP6_Pos) |
| #define | DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk |
| #define | DSI_VVBPCR_VBP7_Pos (7U) |
| #define | DSI_VVBPCR_VBP7_Msk (0x1UL << DSI_VVBPCR_VBP7_Pos) |
| #define | DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk |
| #define | DSI_VVBPCR_VBP8_Pos (8U) |
| #define | DSI_VVBPCR_VBP8_Msk (0x1UL << DSI_VVBPCR_VBP8_Pos) |
| #define | DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk |
| #define | DSI_VVBPCR_VBP9_Pos (9U) |
| #define | DSI_VVBPCR_VBP9_Msk (0x1UL << DSI_VVBPCR_VBP9_Pos) |
| #define | DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk |
| #define | DSI_VVFPCR_VFP_Pos (0U) |
| #define | DSI_VVFPCR_VFP_Msk (0x3FFUL << DSI_VVFPCR_VFP_Pos) |
| #define | DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk |
| #define | DSI_VVFPCR_VFP0_Pos (0U) |
| #define | DSI_VVFPCR_VFP0_Msk (0x1UL << DSI_VVFPCR_VFP0_Pos) |
| #define | DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk |
| #define | DSI_VVFPCR_VFP1_Pos (1U) |
| #define | DSI_VVFPCR_VFP1_Msk (0x1UL << DSI_VVFPCR_VFP1_Pos) |
| #define | DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk |
| #define | DSI_VVFPCR_VFP2_Pos (2U) |
| #define | DSI_VVFPCR_VFP2_Msk (0x1UL << DSI_VVFPCR_VFP2_Pos) |
| #define | DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk |
| #define | DSI_VVFPCR_VFP3_Pos (3U) |
| #define | DSI_VVFPCR_VFP3_Msk (0x1UL << DSI_VVFPCR_VFP3_Pos) |
| #define | DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk |
| #define | DSI_VVFPCR_VFP4_Pos (4U) |
| #define | DSI_VVFPCR_VFP4_Msk (0x1UL << DSI_VVFPCR_VFP4_Pos) |
| #define | DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk |
| #define | DSI_VVFPCR_VFP5_Pos (5U) |
| #define | DSI_VVFPCR_VFP5_Msk (0x1UL << DSI_VVFPCR_VFP5_Pos) |
| #define | DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk |
| #define | DSI_VVFPCR_VFP6_Pos (6U) |
| #define | DSI_VVFPCR_VFP6_Msk (0x1UL << DSI_VVFPCR_VFP6_Pos) |
| #define | DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk |
| #define | DSI_VVFPCR_VFP7_Pos (7U) |
| #define | DSI_VVFPCR_VFP7_Msk (0x1UL << DSI_VVFPCR_VFP7_Pos) |
| #define | DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk |
| #define | DSI_VVFPCR_VFP8_Pos (8U) |
| #define | DSI_VVFPCR_VFP8_Msk (0x1UL << DSI_VVFPCR_VFP8_Pos) |
| #define | DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk |
| #define | DSI_VVFPCR_VFP9_Pos (9U) |
| #define | DSI_VVFPCR_VFP9_Msk (0x1UL << DSI_VVFPCR_VFP9_Pos) |
| #define | DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk |
| #define | DSI_VVACR_VA_Pos (0U) |
| #define | DSI_VVACR_VA_Msk (0x3FFFUL << DSI_VVACR_VA_Pos) |
| #define | DSI_VVACR_VA DSI_VVACR_VA_Msk |
| #define | DSI_VVACR_VA0_Pos (0U) |
| #define | DSI_VVACR_VA0_Msk (0x1UL << DSI_VVACR_VA0_Pos) |
| #define | DSI_VVACR_VA0 DSI_VVACR_VA0_Msk |
| #define | DSI_VVACR_VA1_Pos (1U) |
| #define | DSI_VVACR_VA1_Msk (0x1UL << DSI_VVACR_VA1_Pos) |
| #define | DSI_VVACR_VA1 DSI_VVACR_VA1_Msk |
| #define | DSI_VVACR_VA2_Pos (2U) |
| #define | DSI_VVACR_VA2_Msk (0x1UL << DSI_VVACR_VA2_Pos) |
| #define | DSI_VVACR_VA2 DSI_VVACR_VA2_Msk |
| #define | DSI_VVACR_VA3_Pos (3U) |
| #define | DSI_VVACR_VA3_Msk (0x1UL << DSI_VVACR_VA3_Pos) |
| #define | DSI_VVACR_VA3 DSI_VVACR_VA3_Msk |
| #define | DSI_VVACR_VA4_Pos (4U) |
| #define | DSI_VVACR_VA4_Msk (0x1UL << DSI_VVACR_VA4_Pos) |
| #define | DSI_VVACR_VA4 DSI_VVACR_VA4_Msk |
| #define | DSI_VVACR_VA5_Pos (5U) |
| #define | DSI_VVACR_VA5_Msk (0x1UL << DSI_VVACR_VA5_Pos) |
| #define | DSI_VVACR_VA5 DSI_VVACR_VA5_Msk |
| #define | DSI_VVACR_VA6_Pos (6U) |
| #define | DSI_VVACR_VA6_Msk (0x1UL << DSI_VVACR_VA6_Pos) |
| #define | DSI_VVACR_VA6 DSI_VVACR_VA6_Msk |
| #define | DSI_VVACR_VA7_Pos (7U) |
| #define | DSI_VVACR_VA7_Msk (0x1UL << DSI_VVACR_VA7_Pos) |
| #define | DSI_VVACR_VA7 DSI_VVACR_VA7_Msk |
| #define | DSI_VVACR_VA8_Pos (8U) |
| #define | DSI_VVACR_VA8_Msk (0x1UL << DSI_VVACR_VA8_Pos) |
| #define | DSI_VVACR_VA8 DSI_VVACR_VA8_Msk |
| #define | DSI_VVACR_VA9_Pos (9U) |
| #define | DSI_VVACR_VA9_Msk (0x1UL << DSI_VVACR_VA9_Pos) |
| #define | DSI_VVACR_VA9 DSI_VVACR_VA9_Msk |
| #define | DSI_VVACR_VA10_Pos (10U) |
| #define | DSI_VVACR_VA10_Msk (0x1UL << DSI_VVACR_VA10_Pos) |
| #define | DSI_VVACR_VA10 DSI_VVACR_VA10_Msk |
| #define | DSI_VVACR_VA11_Pos (11U) |
| #define | DSI_VVACR_VA11_Msk (0x1UL << DSI_VVACR_VA11_Pos) |
| #define | DSI_VVACR_VA11 DSI_VVACR_VA11_Msk |
| #define | DSI_VVACR_VA12_Pos (12U) |
| #define | DSI_VVACR_VA12_Msk (0x1UL << DSI_VVACR_VA12_Pos) |
| #define | DSI_VVACR_VA12 DSI_VVACR_VA12_Msk |
| #define | DSI_VVACR_VA13_Pos (13U) |
| #define | DSI_VVACR_VA13_Msk (0x1UL << DSI_VVACR_VA13_Pos) |
| #define | DSI_VVACR_VA13 DSI_VVACR_VA13_Msk |
| #define | DSI_LCCR_CMDSIZE_Pos (0U) |
| #define | DSI_LCCR_CMDSIZE_Msk (0xFFFFUL << DSI_LCCR_CMDSIZE_Pos) |
| #define | DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk |
| #define | DSI_LCCR_CMDSIZE0_Pos (0U) |
| #define | DSI_LCCR_CMDSIZE0_Msk (0x1UL << DSI_LCCR_CMDSIZE0_Pos) |
| #define | DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk |
| #define | DSI_LCCR_CMDSIZE1_Pos (1U) |
| #define | DSI_LCCR_CMDSIZE1_Msk (0x1UL << DSI_LCCR_CMDSIZE1_Pos) |
| #define | DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk |
| #define | DSI_LCCR_CMDSIZE2_Pos (2U) |
| #define | DSI_LCCR_CMDSIZE2_Msk (0x1UL << DSI_LCCR_CMDSIZE2_Pos) |
| #define | DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk |
| #define | DSI_LCCR_CMDSIZE3_Pos (3U) |
| #define | DSI_LCCR_CMDSIZE3_Msk (0x1UL << DSI_LCCR_CMDSIZE3_Pos) |
| #define | DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk |
| #define | DSI_LCCR_CMDSIZE4_Pos (4U) |
| #define | DSI_LCCR_CMDSIZE4_Msk (0x1UL << DSI_LCCR_CMDSIZE4_Pos) |
| #define | DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk |
| #define | DSI_LCCR_CMDSIZE5_Pos (5U) |
| #define | DSI_LCCR_CMDSIZE5_Msk (0x1UL << DSI_LCCR_CMDSIZE5_Pos) |
| #define | DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk |
| #define | DSI_LCCR_CMDSIZE6_Pos (6U) |
| #define | DSI_LCCR_CMDSIZE6_Msk (0x1UL << DSI_LCCR_CMDSIZE6_Pos) |
| #define | DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk |
| #define | DSI_LCCR_CMDSIZE7_Pos (7U) |
| #define | DSI_LCCR_CMDSIZE7_Msk (0x1UL << DSI_LCCR_CMDSIZE7_Pos) |
| #define | DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk |
| #define | DSI_LCCR_CMDSIZE8_Pos (8U) |
| #define | DSI_LCCR_CMDSIZE8_Msk (0x1UL << DSI_LCCR_CMDSIZE8_Pos) |
| #define | DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk |
| #define | DSI_LCCR_CMDSIZE9_Pos (9U) |
| #define | DSI_LCCR_CMDSIZE9_Msk (0x1UL << DSI_LCCR_CMDSIZE9_Pos) |
| #define | DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk |
| #define | DSI_LCCR_CMDSIZE10_Pos (10U) |
| #define | DSI_LCCR_CMDSIZE10_Msk (0x1UL << DSI_LCCR_CMDSIZE10_Pos) |
| #define | DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk |
| #define | DSI_LCCR_CMDSIZE11_Pos (11U) |
| #define | DSI_LCCR_CMDSIZE11_Msk (0x1UL << DSI_LCCR_CMDSIZE11_Pos) |
| #define | DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk |
| #define | DSI_LCCR_CMDSIZE12_Pos (12U) |
| #define | DSI_LCCR_CMDSIZE12_Msk (0x1UL << DSI_LCCR_CMDSIZE12_Pos) |
| #define | DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk |
| #define | DSI_LCCR_CMDSIZE13_Pos (13U) |
| #define | DSI_LCCR_CMDSIZE13_Msk (0x1UL << DSI_LCCR_CMDSIZE13_Pos) |
| #define | DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk |
| #define | DSI_LCCR_CMDSIZE14_Pos (14U) |
| #define | DSI_LCCR_CMDSIZE14_Msk (0x1UL << DSI_LCCR_CMDSIZE14_Pos) |
| #define | DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk |
| #define | DSI_LCCR_CMDSIZE15_Pos (15U) |
| #define | DSI_LCCR_CMDSIZE15_Msk (0x1UL << DSI_LCCR_CMDSIZE15_Pos) |
| #define | DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk |
| #define | DSI_CMCR_TEARE_Pos (0U) |
| #define | DSI_CMCR_TEARE_Msk (0x1UL << DSI_CMCR_TEARE_Pos) |
| #define | DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk |
| #define | DSI_CMCR_ARE_Pos (1U) |
| #define | DSI_CMCR_ARE_Msk (0x1UL << DSI_CMCR_ARE_Pos) |
| #define | DSI_CMCR_ARE DSI_CMCR_ARE_Msk |
| #define | DSI_CMCR_GSW0TX_Pos (8U) |
| #define | DSI_CMCR_GSW0TX_Msk (0x1UL << DSI_CMCR_GSW0TX_Pos) |
| #define | DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk |
| #define | DSI_CMCR_GSW1TX_Pos (9U) |
| #define | DSI_CMCR_GSW1TX_Msk (0x1UL << DSI_CMCR_GSW1TX_Pos) |
| #define | DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk |
| #define | DSI_CMCR_GSW2TX_Pos (10U) |
| #define | DSI_CMCR_GSW2TX_Msk (0x1UL << DSI_CMCR_GSW2TX_Pos) |
| #define | DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk |
| #define | DSI_CMCR_GSR0TX_Pos (11U) |
| #define | DSI_CMCR_GSR0TX_Msk (0x1UL << DSI_CMCR_GSR0TX_Pos) |
| #define | DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk |
| #define | DSI_CMCR_GSR1TX_Pos (12U) |
| #define | DSI_CMCR_GSR1TX_Msk (0x1UL << DSI_CMCR_GSR1TX_Pos) |
| #define | DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk |
| #define | DSI_CMCR_GSR2TX_Pos (13U) |
| #define | DSI_CMCR_GSR2TX_Msk (0x1UL << DSI_CMCR_GSR2TX_Pos) |
| #define | DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk |
| #define | DSI_CMCR_GLWTX_Pos (14U) |
| #define | DSI_CMCR_GLWTX_Msk (0x1UL << DSI_CMCR_GLWTX_Pos) |
| #define | DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk |
| #define | DSI_CMCR_DSW0TX_Pos (16U) |
| #define | DSI_CMCR_DSW0TX_Msk (0x1UL << DSI_CMCR_DSW0TX_Pos) |
| #define | DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk |
| #define | DSI_CMCR_DSW1TX_Pos (17U) |
| #define | DSI_CMCR_DSW1TX_Msk (0x1UL << DSI_CMCR_DSW1TX_Pos) |
| #define | DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk |
| #define | DSI_CMCR_DSR0TX_Pos (18U) |
| #define | DSI_CMCR_DSR0TX_Msk (0x1UL << DSI_CMCR_DSR0TX_Pos) |
| #define | DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk |
| #define | DSI_CMCR_DLWTX_Pos (19U) |
| #define | DSI_CMCR_DLWTX_Msk (0x1UL << DSI_CMCR_DLWTX_Pos) |
| #define | DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk |
| #define | DSI_CMCR_MRDPS_Pos (24U) |
| #define | DSI_CMCR_MRDPS_Msk (0x1UL << DSI_CMCR_MRDPS_Pos) |
| #define | DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk |
| #define | DSI_GHCR_DT_Pos (0U) |
| #define | DSI_GHCR_DT_Msk (0x3FUL << DSI_GHCR_DT_Pos) |
| #define | DSI_GHCR_DT DSI_GHCR_DT_Msk |
| #define | DSI_GHCR_DT0_Pos (0U) |
| #define | DSI_GHCR_DT0_Msk (0x1UL << DSI_GHCR_DT0_Pos) |
| #define | DSI_GHCR_DT0 DSI_GHCR_DT0_Msk |
| #define | DSI_GHCR_DT1_Pos (1U) |
| #define | DSI_GHCR_DT1_Msk (0x1UL << DSI_GHCR_DT1_Pos) |
| #define | DSI_GHCR_DT1 DSI_GHCR_DT1_Msk |
| #define | DSI_GHCR_DT2_Pos (2U) |
| #define | DSI_GHCR_DT2_Msk (0x1UL << DSI_GHCR_DT2_Pos) |
| #define | DSI_GHCR_DT2 DSI_GHCR_DT2_Msk |
| #define | DSI_GHCR_DT3_Pos (3U) |
| #define | DSI_GHCR_DT3_Msk (0x1UL << DSI_GHCR_DT3_Pos) |
| #define | DSI_GHCR_DT3 DSI_GHCR_DT3_Msk |
| #define | DSI_GHCR_DT4_Pos (4U) |
| #define | DSI_GHCR_DT4_Msk (0x1UL << DSI_GHCR_DT4_Pos) |
| #define | DSI_GHCR_DT4 DSI_GHCR_DT4_Msk |
| #define | DSI_GHCR_DT5_Pos (5U) |
| #define | DSI_GHCR_DT5_Msk (0x1UL << DSI_GHCR_DT5_Pos) |
| #define | DSI_GHCR_DT5 DSI_GHCR_DT5_Msk |
| #define | DSI_GHCR_VCID_Pos (6U) |
| #define | DSI_GHCR_VCID_Msk (0x3UL << DSI_GHCR_VCID_Pos) |
| #define | DSI_GHCR_VCID DSI_GHCR_VCID_Msk |
| #define | DSI_GHCR_VCID0_Pos (6U) |
| #define | DSI_GHCR_VCID0_Msk (0x1UL << DSI_GHCR_VCID0_Pos) |
| #define | DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk |
| #define | DSI_GHCR_VCID1_Pos (7U) |
| #define | DSI_GHCR_VCID1_Msk (0x1UL << DSI_GHCR_VCID1_Pos) |
| #define | DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk |
| #define | DSI_GHCR_WCLSB_Pos (8U) |
| #define | DSI_GHCR_WCLSB_Msk (0xFFUL << DSI_GHCR_WCLSB_Pos) |
| #define | DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk |
| #define | DSI_GHCR_WCLSB0_Pos (8U) |
| #define | DSI_GHCR_WCLSB0_Msk (0x1UL << DSI_GHCR_WCLSB0_Pos) |
| #define | DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk |
| #define | DSI_GHCR_WCLSB1_Pos (9U) |
| #define | DSI_GHCR_WCLSB1_Msk (0x1UL << DSI_GHCR_WCLSB1_Pos) |
| #define | DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk |
| #define | DSI_GHCR_WCLSB2_Pos (10U) |
| #define | DSI_GHCR_WCLSB2_Msk (0x1UL << DSI_GHCR_WCLSB2_Pos) |
| #define | DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk |
| #define | DSI_GHCR_WCLSB3_Pos (11U) |
| #define | DSI_GHCR_WCLSB3_Msk (0x1UL << DSI_GHCR_WCLSB3_Pos) |
| #define | DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk |
| #define | DSI_GHCR_WCLSB4_Pos (12U) |
| #define | DSI_GHCR_WCLSB4_Msk (0x1UL << DSI_GHCR_WCLSB4_Pos) |
| #define | DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk |
| #define | DSI_GHCR_WCLSB5_Pos (13U) |
| #define | DSI_GHCR_WCLSB5_Msk (0x1UL << DSI_GHCR_WCLSB5_Pos) |
| #define | DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk |
| #define | DSI_GHCR_WCLSB6_Pos (14U) |
| #define | DSI_GHCR_WCLSB6_Msk (0x1UL << DSI_GHCR_WCLSB6_Pos) |
| #define | DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk |
| #define | DSI_GHCR_WCLSB7_Pos (15U) |
| #define | DSI_GHCR_WCLSB7_Msk (0x1UL << DSI_GHCR_WCLSB7_Pos) |
| #define | DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk |
| #define | DSI_GHCR_WCMSB_Pos (16U) |
| #define | DSI_GHCR_WCMSB_Msk (0xFFUL << DSI_GHCR_WCMSB_Pos) |
| #define | DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk |
| #define | DSI_GHCR_WCMSB0_Pos (16U) |
| #define | DSI_GHCR_WCMSB0_Msk (0x1UL << DSI_GHCR_WCMSB0_Pos) |
| #define | DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk |
| #define | DSI_GHCR_WCMSB1_Pos (17U) |
| #define | DSI_GHCR_WCMSB1_Msk (0x1UL << DSI_GHCR_WCMSB1_Pos) |
| #define | DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk |
| #define | DSI_GHCR_WCMSB2_Pos (18U) |
| #define | DSI_GHCR_WCMSB2_Msk (0x1UL << DSI_GHCR_WCMSB2_Pos) |
| #define | DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk |
| #define | DSI_GHCR_WCMSB3_Pos (19U) |
| #define | DSI_GHCR_WCMSB3_Msk (0x1UL << DSI_GHCR_WCMSB3_Pos) |
| #define | DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk |
| #define | DSI_GHCR_WCMSB4_Pos (20U) |
| #define | DSI_GHCR_WCMSB4_Msk (0x1UL << DSI_GHCR_WCMSB4_Pos) |
| #define | DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk |
| #define | DSI_GHCR_WCMSB5_Pos (21U) |
| #define | DSI_GHCR_WCMSB5_Msk (0x1UL << DSI_GHCR_WCMSB5_Pos) |
| #define | DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk |
| #define | DSI_GHCR_WCMSB6_Pos (22U) |
| #define | DSI_GHCR_WCMSB6_Msk (0x1UL << DSI_GHCR_WCMSB6_Pos) |
| #define | DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk |
| #define | DSI_GHCR_WCMSB7_Pos (23U) |
| #define | DSI_GHCR_WCMSB7_Msk (0x1UL << DSI_GHCR_WCMSB7_Pos) |
| #define | DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk |
| #define | DSI_GPDR_DATA1_Pos (0U) |
| #define | DSI_GPDR_DATA1_Msk (0xFFUL << DSI_GPDR_DATA1_Pos) |
| #define | DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk |
| #define | DSI_GPDR_DATA1_0 (0x01UL << DSI_GPDR_DATA1_Pos) |
| #define | DSI_GPDR_DATA1_1 (0x02UL << DSI_GPDR_DATA1_Pos) |
| #define | DSI_GPDR_DATA1_2 (0x04UL << DSI_GPDR_DATA1_Pos) |
| #define | DSI_GPDR_DATA1_3 (0x08UL << DSI_GPDR_DATA1_Pos) |
| #define | DSI_GPDR_DATA1_4 (0x10UL << DSI_GPDR_DATA1_Pos) |
| #define | DSI_GPDR_DATA1_5 (0x20UL << DSI_GPDR_DATA1_Pos) |
| #define | DSI_GPDR_DATA1_6 (0x40UL << DSI_GPDR_DATA1_Pos) |
| #define | DSI_GPDR_DATA1_7 (0x80UL << DSI_GPDR_DATA1_Pos) |
| #define | DSI_GPDR_DATA2_Pos (8U) |
| #define | DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) |
| #define | DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk |
| #define | DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) |
| #define | DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) |
| #define | DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) |
| #define | DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) |
| #define | DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) |
| #define | DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) |
| #define | DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) |
| #define | DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) |
| #define | DSI_GPDR_DATA3_Pos (16U) |
| #define | DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) |
| #define | DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk |
| #define | DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) |
| #define | DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) |
| #define | DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) |
| #define | DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) |
| #define | DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) |
| #define | DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) |
| #define | DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) |
| #define | DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) |
| #define | DSI_GPDR_DATA4_Pos (24U) |
| #define | DSI_GPDR_DATA4_Msk (0xFFUL << DSI_GPDR_DATA4_Pos) |
| #define | DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk |
| #define | DSI_GPDR_DATA4_0 (0x01UL << DSI_GPDR_DATA4_Pos) |
| #define | DSI_GPDR_DATA4_1 (0x02UL << DSI_GPDR_DATA4_Pos) |
| #define | DSI_GPDR_DATA4_2 (0x04UL << DSI_GPDR_DATA4_Pos) |
| #define | DSI_GPDR_DATA4_3 (0x08UL << DSI_GPDR_DATA4_Pos) |
| #define | DSI_GPDR_DATA4_4 (0x10UL << DSI_GPDR_DATA4_Pos) |
| #define | DSI_GPDR_DATA4_5 (0x20UL << DSI_GPDR_DATA4_Pos) |
| #define | DSI_GPDR_DATA4_6 (0x40UL << DSI_GPDR_DATA4_Pos) |
| #define | DSI_GPDR_DATA4_7 (0x80UL << DSI_GPDR_DATA4_Pos) |
| #define | DSI_GPSR_CMDFE_Pos (0U) |
| #define | DSI_GPSR_CMDFE_Msk (0x1UL << DSI_GPSR_CMDFE_Pos) |
| #define | DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk |
| #define | DSI_GPSR_CMDFF_Pos (1U) |
| #define | DSI_GPSR_CMDFF_Msk (0x1UL << DSI_GPSR_CMDFF_Pos) |
| #define | DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk |
| #define | DSI_GPSR_PWRFE_Pos (2U) |
| #define | DSI_GPSR_PWRFE_Msk (0x1UL << DSI_GPSR_PWRFE_Pos) |
| #define | DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk |
| #define | DSI_GPSR_PWRFF_Pos (3U) |
| #define | DSI_GPSR_PWRFF_Msk (0x1UL << DSI_GPSR_PWRFF_Pos) |
| #define | DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk |
| #define | DSI_GPSR_PRDFE_Pos (4U) |
| #define | DSI_GPSR_PRDFE_Msk (0x1UL << DSI_GPSR_PRDFE_Pos) |
| #define | DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk |
| #define | DSI_GPSR_PRDFF_Pos (5U) |
| #define | DSI_GPSR_PRDFF_Msk (0x1UL << DSI_GPSR_PRDFF_Pos) |
| #define | DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk |
| #define | DSI_GPSR_RCB_Pos (6U) |
| #define | DSI_GPSR_RCB_Msk (0x1UL << DSI_GPSR_RCB_Pos) |
| #define | DSI_GPSR_RCB DSI_GPSR_RCB_Msk |
| #define | DSI_GPSR_CMDBE_Pos (16U) |
| #define | DSI_GPSR_CMDBE_Msk (0x1UL << DSI_GPSR_CMDBE_Pos) |
| #define | DSI_GPSR_CMDBE DSI_GPSR_CMDBE_Msk |
| #define | DSI_GPSR_CMDBF_Pos (17U) |
| #define | DSI_GPSR_CMDBF_Msk (0x1UL << DSI_GPSR_CMDBF_Pos) |
| #define | DSI_GPSR_CMDBF DSI_GPSR_CMDBF_Msk |
| #define | DSI_GPSR_PBE_Pos (18U) |
| #define | DSI_GPSR_PBE_Msk (0x1UL << DSI_GPSR_PBE_Pos) |
| #define | DSI_GPSR_PBE DSI_GPSR_PBE_Msk |
| #define | DSI_GPSR_PBF_Pos (19U) |
| #define | DSI_GPSR_PBF_Msk (0x1UL << DSI_GPSR_PBF_Pos) |
| #define | DSI_GPSR_PBF DSI_GPSR_PBF_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT_Pos (0U) |
| #define | DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_LPRX_TOCNT_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT0_Pos (0U) |
| #define | DSI_TCCR0_LPRX_TOCNT0_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT0_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT1_Pos (1U) |
| #define | DSI_TCCR0_LPRX_TOCNT1_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT1_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT2_Pos (2U) |
| #define | DSI_TCCR0_LPRX_TOCNT2_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT2_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT3_Pos (3U) |
| #define | DSI_TCCR0_LPRX_TOCNT3_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT3_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT4_Pos (4U) |
| #define | DSI_TCCR0_LPRX_TOCNT4_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT4_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT5_Pos (5U) |
| #define | DSI_TCCR0_LPRX_TOCNT5_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT5_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT6_Pos (6U) |
| #define | DSI_TCCR0_LPRX_TOCNT6_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT6_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT7_Pos (7U) |
| #define | DSI_TCCR0_LPRX_TOCNT7_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT7_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT8_Pos (8U) |
| #define | DSI_TCCR0_LPRX_TOCNT8_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT8_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT9_Pos (9U) |
| #define | DSI_TCCR0_LPRX_TOCNT9_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT9_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT10_Pos (10U) |
| #define | DSI_TCCR0_LPRX_TOCNT10_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT10_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT11_Pos (11U) |
| #define | DSI_TCCR0_LPRX_TOCNT11_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT11_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT12_Pos (12U) |
| #define | DSI_TCCR0_LPRX_TOCNT12_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT12_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT13_Pos (13U) |
| #define | DSI_TCCR0_LPRX_TOCNT13_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT13_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT14_Pos (14U) |
| #define | DSI_TCCR0_LPRX_TOCNT14_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT14_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk |
| #define | DSI_TCCR0_LPRX_TOCNT15_Pos (15U) |
| #define | DSI_TCCR0_LPRX_TOCNT15_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT15_Pos) |
| #define | DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT_Pos (16U) |
| #define | DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_HSTX_TOCNT_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT0_Pos (16U) |
| #define | DSI_TCCR0_HSTX_TOCNT0_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT0_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT1_Pos (17U) |
| #define | DSI_TCCR0_HSTX_TOCNT1_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT1_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT2_Pos (18U) |
| #define | DSI_TCCR0_HSTX_TOCNT2_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT2_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT3_Pos (19U) |
| #define | DSI_TCCR0_HSTX_TOCNT3_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT3_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT4_Pos (20U) |
| #define | DSI_TCCR0_HSTX_TOCNT4_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT4_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT5_Pos (21U) |
| #define | DSI_TCCR0_HSTX_TOCNT5_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT5_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT6_Pos (22U) |
| #define | DSI_TCCR0_HSTX_TOCNT6_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT6_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT7_Pos (23U) |
| #define | DSI_TCCR0_HSTX_TOCNT7_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT7_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT8_Pos (24U) |
| #define | DSI_TCCR0_HSTX_TOCNT8_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT8_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT9_Pos (25U) |
| #define | DSI_TCCR0_HSTX_TOCNT9_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT9_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT10_Pos (26U) |
| #define | DSI_TCCR0_HSTX_TOCNT10_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT10_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT11_Pos (27U) |
| #define | DSI_TCCR0_HSTX_TOCNT11_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT11_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT12_Pos (28U) |
| #define | DSI_TCCR0_HSTX_TOCNT12_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT12_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT13_Pos (29U) |
| #define | DSI_TCCR0_HSTX_TOCNT13_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT13_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT14_Pos (30U) |
| #define | DSI_TCCR0_HSTX_TOCNT14_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT14_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk |
| #define | DSI_TCCR0_HSTX_TOCNT15_Pos (31U) |
| #define | DSI_TCCR0_HSTX_TOCNT15_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT15_Pos) |
| #define | DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT_Pos (0U) |
| #define | DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR1_HSRD_TOCNT_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT0_Pos (0U) |
| #define | DSI_TCCR1_HSRD_TOCNT0_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT0_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT1_Pos (1U) |
| #define | DSI_TCCR1_HSRD_TOCNT1_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT1_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT2_Pos (2U) |
| #define | DSI_TCCR1_HSRD_TOCNT2_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT2_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT3_Pos (3U) |
| #define | DSI_TCCR1_HSRD_TOCNT3_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT3_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT4_Pos (4U) |
| #define | DSI_TCCR1_HSRD_TOCNT4_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT4_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT5_Pos (5U) |
| #define | DSI_TCCR1_HSRD_TOCNT5_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT5_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT6_Pos (6U) |
| #define | DSI_TCCR1_HSRD_TOCNT6_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT6_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT7_Pos (7U) |
| #define | DSI_TCCR1_HSRD_TOCNT7_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT7_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT8_Pos (8U) |
| #define | DSI_TCCR1_HSRD_TOCNT8_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT8_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT9_Pos (9U) |
| #define | DSI_TCCR1_HSRD_TOCNT9_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT9_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT10_Pos (10U) |
| #define | DSI_TCCR1_HSRD_TOCNT10_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT10_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT11_Pos (11U) |
| #define | DSI_TCCR1_HSRD_TOCNT11_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT11_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT12_Pos (12U) |
| #define | DSI_TCCR1_HSRD_TOCNT12_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT12_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT13_Pos (13U) |
| #define | DSI_TCCR1_HSRD_TOCNT13_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT13_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT14_Pos (14U) |
| #define | DSI_TCCR1_HSRD_TOCNT14_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT14_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk |
| #define | DSI_TCCR1_HSRD_TOCNT15_Pos (15U) |
| #define | DSI_TCCR1_HSRD_TOCNT15_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT15_Pos) |
| #define | DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT_Pos (0U) |
| #define | DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR2_LPRD_TOCNT_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT0_Pos (0U) |
| #define | DSI_TCCR2_LPRD_TOCNT0_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT0_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT1_Pos (1U) |
| #define | DSI_TCCR2_LPRD_TOCNT1_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT1_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT2_Pos (2U) |
| #define | DSI_TCCR2_LPRD_TOCNT2_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT2_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT3_Pos (3U) |
| #define | DSI_TCCR2_LPRD_TOCNT3_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT3_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT4_Pos (4U) |
| #define | DSI_TCCR2_LPRD_TOCNT4_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT4_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT5_Pos (5U) |
| #define | DSI_TCCR2_LPRD_TOCNT5_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT5_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT6_Pos (6U) |
| #define | DSI_TCCR2_LPRD_TOCNT6_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT6_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT7_Pos (7U) |
| #define | DSI_TCCR2_LPRD_TOCNT7_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT7_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT8_Pos (8U) |
| #define | DSI_TCCR2_LPRD_TOCNT8_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT8_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT9_Pos (9U) |
| #define | DSI_TCCR2_LPRD_TOCNT9_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT9_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT10_Pos (10U) |
| #define | DSI_TCCR2_LPRD_TOCNT10_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT10_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT11_Pos (11U) |
| #define | DSI_TCCR2_LPRD_TOCNT11_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT11_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT12_Pos (12U) |
| #define | DSI_TCCR2_LPRD_TOCNT12_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT12_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT13_Pos (13U) |
| #define | DSI_TCCR2_LPRD_TOCNT13_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT13_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT14_Pos (14U) |
| #define | DSI_TCCR2_LPRD_TOCNT14_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT14_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk |
| #define | DSI_TCCR2_LPRD_TOCNT15_Pos (15U) |
| #define | DSI_TCCR2_LPRD_TOCNT15_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT15_Pos) |
| #define | DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT_Pos (0U) |
| #define | DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR3_HSWR_TOCNT_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT0_Pos (0U) |
| #define | DSI_TCCR3_HSWR_TOCNT0_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT0_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT1_Pos (1U) |
| #define | DSI_TCCR3_HSWR_TOCNT1_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT1_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT2_Pos (2U) |
| #define | DSI_TCCR3_HSWR_TOCNT2_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT2_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT3_Pos (3U) |
| #define | DSI_TCCR3_HSWR_TOCNT3_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT3_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT4_Pos (4U) |
| #define | DSI_TCCR3_HSWR_TOCNT4_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT4_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT5_Pos (5U) |
| #define | DSI_TCCR3_HSWR_TOCNT5_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT5_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT6_Pos (6U) |
| #define | DSI_TCCR3_HSWR_TOCNT6_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT6_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT7_Pos (7U) |
| #define | DSI_TCCR3_HSWR_TOCNT7_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT7_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT8_Pos (8U) |
| #define | DSI_TCCR3_HSWR_TOCNT8_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT8_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT9_Pos (9U) |
| #define | DSI_TCCR3_HSWR_TOCNT9_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT9_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT10_Pos (10U) |
| #define | DSI_TCCR3_HSWR_TOCNT10_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT10_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT11_Pos (11U) |
| #define | DSI_TCCR3_HSWR_TOCNT11_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT11_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT12_Pos (12U) |
| #define | DSI_TCCR3_HSWR_TOCNT12_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT12_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT13_Pos (13U) |
| #define | DSI_TCCR3_HSWR_TOCNT13_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT13_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT14_Pos (14U) |
| #define | DSI_TCCR3_HSWR_TOCNT14_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT14_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk |
| #define | DSI_TCCR3_HSWR_TOCNT15_Pos (15U) |
| #define | DSI_TCCR3_HSWR_TOCNT15_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT15_Pos) |
| #define | DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk |
| #define | DSI_TCCR3_PM_Pos (24U) |
| #define | DSI_TCCR3_PM_Msk (0x1UL << DSI_TCCR3_PM_Pos) |
| #define | DSI_TCCR3_PM DSI_TCCR3_PM_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT_Pos (0U) |
| #define | DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR4_LPWR_TOCNT_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT0_Pos (0U) |
| #define | DSI_TCCR4_LPWR_TOCNT0_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT0_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT1_Pos (1U) |
| #define | DSI_TCCR4_LPWR_TOCNT1_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT1_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT2_Pos (2U) |
| #define | DSI_TCCR4_LPWR_TOCNT2_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT2_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT3_Pos (3U) |
| #define | DSI_TCCR4_LPWR_TOCNT3_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT3_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT4_Pos (4U) |
| #define | DSI_TCCR4_LPWR_TOCNT4_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT4_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT5_Pos (5U) |
| #define | DSI_TCCR4_LPWR_TOCNT5_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT5_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT6_Pos (6U) |
| #define | DSI_TCCR4_LPWR_TOCNT6_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT6_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT7_Pos (7U) |
| #define | DSI_TCCR4_LPWR_TOCNT7_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT7_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT8_Pos (8U) |
| #define | DSI_TCCR4_LPWR_TOCNT8_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT8_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT9_Pos (9U) |
| #define | DSI_TCCR4_LPWR_TOCNT9_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT9_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT10_Pos (10U) |
| #define | DSI_TCCR4_LPWR_TOCNT10_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT10_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT11_Pos (11U) |
| #define | DSI_TCCR4_LPWR_TOCNT11_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT11_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT12_Pos (12U) |
| #define | DSI_TCCR4_LPWR_TOCNT12_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT12_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT13_Pos (13U) |
| #define | DSI_TCCR4_LPWR_TOCNT13_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT13_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT14_Pos (14U) |
| #define | DSI_TCCR4_LPWR_TOCNT14_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT14_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk |
| #define | DSI_TCCR4_LPWR_TOCNT15_Pos (15U) |
| #define | DSI_TCCR4_LPWR_TOCNT15_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT15_Pos) |
| #define | DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk |
| #define | DSI_TCCR5_BTA_TOCNT_Pos (0U) |
| #define | DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFUL << DSI_TCCR5_BTA_TOCNT_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk |
| #define | DSI_TCCR5_BTA_TOCNT0_Pos (0U) |
| #define | DSI_TCCR5_BTA_TOCNT0_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT0_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk |
| #define | DSI_TCCR5_BTA_TOCNT1_Pos (1U) |
| #define | DSI_TCCR5_BTA_TOCNT1_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT1_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk |
| #define | DSI_TCCR5_BTA_TOCNT2_Pos (2U) |
| #define | DSI_TCCR5_BTA_TOCNT2_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT2_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk |
| #define | DSI_TCCR5_BTA_TOCNT3_Pos (3U) |
| #define | DSI_TCCR5_BTA_TOCNT3_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT3_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk |
| #define | DSI_TCCR5_BTA_TOCNT4_Pos (4U) |
| #define | DSI_TCCR5_BTA_TOCNT4_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT4_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk |
| #define | DSI_TCCR5_BTA_TOCNT5_Pos (5U) |
| #define | DSI_TCCR5_BTA_TOCNT5_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT5_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk |
| #define | DSI_TCCR5_BTA_TOCNT6_Pos (6U) |
| #define | DSI_TCCR5_BTA_TOCNT6_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT6_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk |
| #define | DSI_TCCR5_BTA_TOCNT7_Pos (7U) |
| #define | DSI_TCCR5_BTA_TOCNT7_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT7_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk |
| #define | DSI_TCCR5_BTA_TOCNT8_Pos (8U) |
| #define | DSI_TCCR5_BTA_TOCNT8_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT8_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk |
| #define | DSI_TCCR5_BTA_TOCNT9_Pos (9U) |
| #define | DSI_TCCR5_BTA_TOCNT9_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT9_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk |
| #define | DSI_TCCR5_BTA_TOCNT10_Pos (10U) |
| #define | DSI_TCCR5_BTA_TOCNT10_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT10_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk |
| #define | DSI_TCCR5_BTA_TOCNT11_Pos (11U) |
| #define | DSI_TCCR5_BTA_TOCNT11_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT11_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk |
| #define | DSI_TCCR5_BTA_TOCNT12_Pos (12U) |
| #define | DSI_TCCR5_BTA_TOCNT12_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT12_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk |
| #define | DSI_TCCR5_BTA_TOCNT13_Pos (13U) |
| #define | DSI_TCCR5_BTA_TOCNT13_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT13_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk |
| #define | DSI_TCCR5_BTA_TOCNT14_Pos (14U) |
| #define | DSI_TCCR5_BTA_TOCNT14_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT14_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk |
| #define | DSI_TCCR5_BTA_TOCNT15_Pos (15U) |
| #define | DSI_TCCR5_BTA_TOCNT15_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT15_Pos) |
| #define | DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk |
| #define | DSI_CLCR_DPCC_Pos (0U) |
| #define | DSI_CLCR_DPCC_Msk (0x1UL << DSI_CLCR_DPCC_Pos) |
| #define | DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk |
| #define | DSI_CLCR_ACR_Pos (1U) |
| #define | DSI_CLCR_ACR_Msk (0x1UL << DSI_CLCR_ACR_Pos) |
| #define | DSI_CLCR_ACR DSI_CLCR_ACR_Msk |
| #define | DSI_CLTCR_LP2HS_TIME_Pos (0U) |
| #define | DSI_CLTCR_LP2HS_TIME_Msk (0x3FFUL << DSI_CLTCR_LP2HS_TIME_Pos) |
| #define | DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk |
| #define | DSI_CLTCR_LP2HS_TIME0_Pos (0U) |
| #define | DSI_CLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME0_Pos) |
| #define | DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk |
| #define | DSI_CLTCR_LP2HS_TIME1_Pos (1U) |
| #define | DSI_CLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME1_Pos) |
| #define | DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk |
| #define | DSI_CLTCR_LP2HS_TIME2_Pos (2U) |
| #define | DSI_CLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME2_Pos) |
| #define | DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk |
| #define | DSI_CLTCR_LP2HS_TIME3_Pos (3U) |
| #define | DSI_CLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME3_Pos) |
| #define | DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk |
| #define | DSI_CLTCR_LP2HS_TIME4_Pos (4U) |
| #define | DSI_CLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME4_Pos) |
| #define | DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk |
| #define | DSI_CLTCR_LP2HS_TIME5_Pos (5U) |
| #define | DSI_CLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME5_Pos) |
| #define | DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk |
| #define | DSI_CLTCR_LP2HS_TIME6_Pos (6U) |
| #define | DSI_CLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME6_Pos) |
| #define | DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk |
| #define | DSI_CLTCR_LP2HS_TIME7_Pos (7U) |
| #define | DSI_CLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME7_Pos) |
| #define | DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk |
| #define | DSI_CLTCR_LP2HS_TIME8_Pos (8U) |
| #define | DSI_CLTCR_LP2HS_TIME8_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME8_Pos) |
| #define | DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk |
| #define | DSI_CLTCR_LP2HS_TIME9_Pos (9U) |
| #define | DSI_CLTCR_LP2HS_TIME9_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME9_Pos) |
| #define | DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk |
| #define | DSI_CLTCR_HS2LP_TIME_Pos (16U) |
| #define | DSI_CLTCR_HS2LP_TIME_Msk (0x3FFUL << DSI_CLTCR_HS2LP_TIME_Pos) |
| #define | DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk |
| #define | DSI_CLTCR_HS2LP_TIME0_Pos (16U) |
| #define | DSI_CLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME0_Pos) |
| #define | DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk |
| #define | DSI_CLTCR_HS2LP_TIME1_Pos (17U) |
| #define | DSI_CLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME1_Pos) |
| #define | DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk |
| #define | DSI_CLTCR_HS2LP_TIME2_Pos (18U) |
| #define | DSI_CLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME2_Pos) |
| #define | DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk |
| #define | DSI_CLTCR_HS2LP_TIME3_Pos (19U) |
| #define | DSI_CLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME3_Pos) |
| #define | DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk |
| #define | DSI_CLTCR_HS2LP_TIME4_Pos (20U) |
| #define | DSI_CLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME4_Pos) |
| #define | DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk |
| #define | DSI_CLTCR_HS2LP_TIME5_Pos (21U) |
| #define | DSI_CLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME5_Pos) |
| #define | DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk |
| #define | DSI_CLTCR_HS2LP_TIME6_Pos (22U) |
| #define | DSI_CLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME6_Pos) |
| #define | DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk |
| #define | DSI_CLTCR_HS2LP_TIME7_Pos (23U) |
| #define | DSI_CLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME7_Pos) |
| #define | DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk |
| #define | DSI_CLTCR_HS2LP_TIME8_Pos (24U) |
| #define | DSI_CLTCR_HS2LP_TIME8_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME8_Pos) |
| #define | DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk |
| #define | DSI_CLTCR_HS2LP_TIME9_Pos (25U) |
| #define | DSI_CLTCR_HS2LP_TIME9_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME9_Pos) |
| #define | DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk |
| #define | DSI_DLTCR_LP2HS_TIME_Pos (0U) |
| #define | DSI_DLTCR_LP2HS_TIME_Msk (0x3FFUL << DSI_DLTCR_LP2HS_TIME_Pos) |
| #define | DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk |
| #define | DSI_DLTCR_LP2HS_TIME0_Pos (0U) |
| #define | DSI_DLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME0_Pos) |
| #define | DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk |
| #define | DSI_DLTCR_LP2HS_TIME1_Pos (1U) |
| #define | DSI_DLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME1_Pos) |
| #define | DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk |
| #define | DSI_DLTCR_LP2HS_TIME2_Pos (2U) |
| #define | DSI_DLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME2_Pos) |
| #define | DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk |
| #define | DSI_DLTCR_LP2HS_TIME3_Pos (3U) |
| #define | DSI_DLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME3_Pos) |
| #define | DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk |
| #define | DSI_DLTCR_LP2HS_TIME4_Pos (4U) |
| #define | DSI_DLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME4_Pos) |
| #define | DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk |
| #define | DSI_DLTCR_LP2HS_TIME5_Pos (5U) |
| #define | DSI_DLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME5_Pos) |
| #define | DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk |
| #define | DSI_DLTCR_LP2HS_TIME6_Pos (6U) |
| #define | DSI_DLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME6_Pos) |
| #define | DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk |
| #define | DSI_DLTCR_LP2HS_TIME7_Pos (7U) |
| #define | DSI_DLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME7_Pos) |
| #define | DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk |
| #define | DSI_DLTCR_LP2HS_TIME8_Pos (8U) |
| #define | DSI_DLTCR_LP2HS_TIME8_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME8_Pos) |
| #define | DSI_DLTCR_LP2HS_TIME8 DSI_DLTCR_LP2HS_TIME8_Msk |
| #define | DSI_DLTCR_LP2HS_TIME9_Pos (9U) |
| #define | DSI_DLTCR_LP2HS_TIME9_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME9_Pos) |
| #define | DSI_DLTCR_LP2HS_TIME9 DSI_DLTCR_LP2HS_TIME9_Msk |
| #define | DSI_DLTCR_HS2LP_TIME_Pos (16U) |
| #define | DSI_DLTCR_HS2LP_TIME_Msk (0x3FFUL << DSI_DLTCR_HS2LP_TIME_Pos) |
| #define | DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk |
| #define | DSI_DLTCR_HS2LP_TIME0_Pos (16U) |
| #define | DSI_DLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME0_Pos) |
| #define | DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk |
| #define | DSI_DLTCR_HS2LP_TIME1_Pos (17U) |
| #define | DSI_DLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME1_Pos) |
| #define | DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk |
| #define | DSI_DLTCR_HS2LP_TIME2_Pos (18U) |
| #define | DSI_DLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME2_Pos) |
| #define | DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk |
| #define | DSI_DLTCR_HS2LP_TIME3_Pos (19U) |
| #define | DSI_DLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME3_Pos) |
| #define | DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk |
| #define | DSI_DLTCR_HS2LP_TIME4_Pos (20U) |
| #define | DSI_DLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME4_Pos) |
| #define | DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk |
| #define | DSI_DLTCR_HS2LP_TIME5_Pos (21U) |
| #define | DSI_DLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME5_Pos) |
| #define | DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk |
| #define | DSI_DLTCR_HS2LP_TIME6_Pos (22U) |
| #define | DSI_DLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME6_Pos) |
| #define | DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk |
| #define | DSI_DLTCR_HS2LP_TIME7_Pos (23U) |
| #define | DSI_DLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME7_Pos) |
| #define | DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk |
| #define | DSI_DLTCR_HS2LP_TIME8_Pos (24U) |
| #define | DSI_DLTCR_HS2LP_TIME8_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME8_Pos) |
| #define | DSI_DLTCR_HS2LP_TIME8 DSI_DLTCR_HS2LP_TIME8_Msk |
| #define | DSI_DLTCR_HS2LP_TIME9_Pos (25U) |
| #define | DSI_DLTCR_HS2LP_TIME9_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME9_Pos) |
| #define | DSI_DLTCR_HS2LP_TIME9 DSI_DLTCR_HS2LP_TIME9_Msk |
| #define | DSI_PCTLR_DEN_Pos (1U) |
| #define | DSI_PCTLR_DEN_Msk (0x1UL << DSI_PCTLR_DEN_Pos) |
| #define | DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk |
| #define | DSI_PCTLR_CKE_Pos (2U) |
| #define | DSI_PCTLR_CKE_Msk (0x1UL << DSI_PCTLR_CKE_Pos) |
| #define | DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk |
| #define | DSI_PCONFR_NL_Pos (0U) |
| #define | DSI_PCONFR_NL_Msk (0x3UL << DSI_PCONFR_NL_Pos) |
| #define | DSI_PCONFR_NL DSI_PCONFR_NL_Msk |
| #define | DSI_PCONFR_NL0_Pos (0U) |
| #define | DSI_PCONFR_NL0_Msk (0x1UL << DSI_PCONFR_NL0_Pos) |
| #define | DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk |
| #define | DSI_PCONFR_NL1_Pos (1U) |
| #define | DSI_PCONFR_NL1_Msk (0x1UL << DSI_PCONFR_NL1_Pos) |
| #define | DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk |
| #define | DSI_PCONFR_SW_TIME_Pos (8U) |
| #define | DSI_PCONFR_SW_TIME_Msk (0xFFUL << DSI_PCONFR_SW_TIME_Pos) |
| #define | DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk |
| #define | DSI_PCONFR_SW_TIME0_Pos (8U) |
| #define | DSI_PCONFR_SW_TIME0_Msk (0x1UL << DSI_PCONFR_SW_TIME0_Pos) |
| #define | DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk |
| #define | DSI_PCONFR_SW_TIME1_Pos (9U) |
| #define | DSI_PCONFR_SW_TIME1_Msk (0x1UL << DSI_PCONFR_SW_TIME1_Pos) |
| #define | DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk |
| #define | DSI_PCONFR_SW_TIME2_Pos (10U) |
| #define | DSI_PCONFR_SW_TIME2_Msk (0x1UL << DSI_PCONFR_SW_TIME2_Pos) |
| #define | DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk |
| #define | DSI_PCONFR_SW_TIME3_Pos (11U) |
| #define | DSI_PCONFR_SW_TIME3_Msk (0x1UL << DSI_PCONFR_SW_TIME3_Pos) |
| #define | DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk |
| #define | DSI_PCONFR_SW_TIME4_Pos (12U) |
| #define | DSI_PCONFR_SW_TIME4_Msk (0x1UL << DSI_PCONFR_SW_TIME4_Pos) |
| #define | DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk |
| #define | DSI_PCONFR_SW_TIME5_Pos (13U) |
| #define | DSI_PCONFR_SW_TIME5_Msk (0x1UL << DSI_PCONFR_SW_TIME5_Pos) |
| #define | DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk |
| #define | DSI_PCONFR_SW_TIME6_Pos (14U) |
| #define | DSI_PCONFR_SW_TIME6_Msk (0x1UL << DSI_PCONFR_SW_TIME6_Pos) |
| #define | DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk |
| #define | DSI_PCONFR_SW_TIME7_Pos (15U) |
| #define | DSI_PCONFR_SW_TIME7_Msk (0x1UL << DSI_PCONFR_SW_TIME7_Pos) |
| #define | DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk |
| #define | DSI_PUCR_URCL_Pos (0U) |
| #define | DSI_PUCR_URCL_Msk (0x1UL << DSI_PUCR_URCL_Pos) |
| #define | DSI_PUCR_URCL DSI_PUCR_URCL_Msk |
| #define | DSI_PUCR_UECL_Pos (1U) |
| #define | DSI_PUCR_UECL_Msk (0x1UL << DSI_PUCR_UECL_Pos) |
| #define | DSI_PUCR_UECL DSI_PUCR_UECL_Msk |
| #define | DSI_PUCR_URDL_Pos (2U) |
| #define | DSI_PUCR_URDL_Msk (0x1UL << DSI_PUCR_URDL_Pos) |
| #define | DSI_PUCR_URDL DSI_PUCR_URDL_Msk |
| #define | DSI_PUCR_UEDL_Pos (3U) |
| #define | DSI_PUCR_UEDL_Msk (0x1UL << DSI_PUCR_UEDL_Pos) |
| #define | DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk |
| #define | DSI_PTTCR_TX_TRIG_Pos (0U) |
| #define | DSI_PTTCR_TX_TRIG_Msk (0xFUL << DSI_PTTCR_TX_TRIG_Pos) |
| #define | DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk |
| #define | DSI_PTTCR_TX_TRIG0_Pos (0U) |
| #define | DSI_PTTCR_TX_TRIG0_Msk (0x1UL << DSI_PTTCR_TX_TRIG0_Pos) |
| #define | DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk |
| #define | DSI_PTTCR_TX_TRIG1_Pos (1U) |
| #define | DSI_PTTCR_TX_TRIG1_Msk (0x1UL << DSI_PTTCR_TX_TRIG1_Pos) |
| #define | DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk |
| #define | DSI_PTTCR_TX_TRIG2_Pos (2U) |
| #define | DSI_PTTCR_TX_TRIG2_Msk (0x1UL << DSI_PTTCR_TX_TRIG2_Pos) |
| #define | DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk |
| #define | DSI_PTTCR_TX_TRIG3_Pos (3U) |
| #define | DSI_PTTCR_TX_TRIG3_Msk (0x1UL << DSI_PTTCR_TX_TRIG3_Pos) |
| #define | DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk |
| #define | DSI_PSR_PD_Pos (1U) |
| #define | DSI_PSR_PD_Msk (0x1UL << DSI_PSR_PD_Pos) |
| #define | DSI_PSR_PD DSI_PSR_PD_Msk |
| #define | DSI_PSR_PSSC_Pos (2U) |
| #define | DSI_PSR_PSSC_Msk (0x1UL << DSI_PSR_PSSC_Pos) |
| #define | DSI_PSR_PSSC DSI_PSR_PSSC_Msk |
| #define | DSI_PSR_UANC_Pos (3U) |
| #define | DSI_PSR_UANC_Msk (0x1UL << DSI_PSR_UANC_Pos) |
| #define | DSI_PSR_UANC DSI_PSR_UANC_Msk |
| #define | DSI_PSR_PSS0_Pos (4U) |
| #define | DSI_PSR_PSS0_Msk (0x1UL << DSI_PSR_PSS0_Pos) |
| #define | DSI_PSR_PSS0 DSI_PSR_PSS0_Msk |
| #define | DSI_PSR_UAN0_Pos (5U) |
| #define | DSI_PSR_UAN0_Msk (0x1UL << DSI_PSR_UAN0_Pos) |
| #define | DSI_PSR_UAN0 DSI_PSR_UAN0_Msk |
| #define | DSI_PSR_RUE0_Pos (6U) |
| #define | DSI_PSR_RUE0_Msk (0x1UL << DSI_PSR_RUE0_Pos) |
| #define | DSI_PSR_RUE0 DSI_PSR_RUE0_Msk |
| #define | DSI_PSR_PSS1_Pos (7U) |
| #define | DSI_PSR_PSS1_Msk (0x1UL << DSI_PSR_PSS1_Pos) |
| #define | DSI_PSR_PSS1 DSI_PSR_PSS1_Msk |
| #define | DSI_PSR_UAN1_Pos (8U) |
| #define | DSI_PSR_UAN1_Msk (0x1UL << DSI_PSR_UAN1_Pos) |
| #define | DSI_PSR_UAN1 DSI_PSR_UAN1_Msk |
| #define | DSI_ISR0_AE0_Pos (0U) |
| #define | DSI_ISR0_AE0_Msk (0x1UL << DSI_ISR0_AE0_Pos) |
| #define | DSI_ISR0_AE0 DSI_ISR0_AE0_Msk |
| #define | DSI_ISR0_AE1_Pos (1U) |
| #define | DSI_ISR0_AE1_Msk (0x1UL << DSI_ISR0_AE1_Pos) |
| #define | DSI_ISR0_AE1 DSI_ISR0_AE1_Msk |
| #define | DSI_ISR0_AE2_Pos (2U) |
| #define | DSI_ISR0_AE2_Msk (0x1UL << DSI_ISR0_AE2_Pos) |
| #define | DSI_ISR0_AE2 DSI_ISR0_AE2_Msk |
| #define | DSI_ISR0_AE3_Pos (3U) |
| #define | DSI_ISR0_AE3_Msk (0x1UL << DSI_ISR0_AE3_Pos) |
| #define | DSI_ISR0_AE3 DSI_ISR0_AE3_Msk |
| #define | DSI_ISR0_AE4_Pos (4U) |
| #define | DSI_ISR0_AE4_Msk (0x1UL << DSI_ISR0_AE4_Pos) |
| #define | DSI_ISR0_AE4 DSI_ISR0_AE4_Msk |
| #define | DSI_ISR0_AE5_Pos (5U) |
| #define | DSI_ISR0_AE5_Msk (0x1UL << DSI_ISR0_AE5_Pos) |
| #define | DSI_ISR0_AE5 DSI_ISR0_AE5_Msk |
| #define | DSI_ISR0_AE6_Pos (6U) |
| #define | DSI_ISR0_AE6_Msk (0x1UL << DSI_ISR0_AE6_Pos) |
| #define | DSI_ISR0_AE6 DSI_ISR0_AE6_Msk |
| #define | DSI_ISR0_AE7_Pos (7U) |
| #define | DSI_ISR0_AE7_Msk (0x1UL << DSI_ISR0_AE7_Pos) |
| #define | DSI_ISR0_AE7 DSI_ISR0_AE7_Msk |
| #define | DSI_ISR0_AE8_Pos (8U) |
| #define | DSI_ISR0_AE8_Msk (0x1UL << DSI_ISR0_AE8_Pos) |
| #define | DSI_ISR0_AE8 DSI_ISR0_AE8_Msk |
| #define | DSI_ISR0_AE9_Pos (9U) |
| #define | DSI_ISR0_AE9_Msk (0x1UL << DSI_ISR0_AE9_Pos) |
| #define | DSI_ISR0_AE9 DSI_ISR0_AE9_Msk |
| #define | DSI_ISR0_AE10_Pos (10U) |
| #define | DSI_ISR0_AE10_Msk (0x1UL << DSI_ISR0_AE10_Pos) |
| #define | DSI_ISR0_AE10 DSI_ISR0_AE10_Msk |
| #define | DSI_ISR0_AE11_Pos (11U) |
| #define | DSI_ISR0_AE11_Msk (0x1UL << DSI_ISR0_AE11_Pos) |
| #define | DSI_ISR0_AE11 DSI_ISR0_AE11_Msk |
| #define | DSI_ISR0_AE12_Pos (12U) |
| #define | DSI_ISR0_AE12_Msk (0x1UL << DSI_ISR0_AE12_Pos) |
| #define | DSI_ISR0_AE12 DSI_ISR0_AE12_Msk |
| #define | DSI_ISR0_AE13_Pos (13U) |
| #define | DSI_ISR0_AE13_Msk (0x1UL << DSI_ISR0_AE13_Pos) |
| #define | DSI_ISR0_AE13 DSI_ISR0_AE13_Msk |
| #define | DSI_ISR0_AE14_Pos (14U) |
| #define | DSI_ISR0_AE14_Msk (0x1UL << DSI_ISR0_AE14_Pos) |
| #define | DSI_ISR0_AE14 DSI_ISR0_AE14_Msk |
| #define | DSI_ISR0_AE15_Pos (15U) |
| #define | DSI_ISR0_AE15_Msk (0x1UL << DSI_ISR0_AE15_Pos) |
| #define | DSI_ISR0_AE15 DSI_ISR0_AE15_Msk |
| #define | DSI_ISR0_PE0_Pos (16U) |
| #define | DSI_ISR0_PE0_Msk (0x1UL << DSI_ISR0_PE0_Pos) |
| #define | DSI_ISR0_PE0 DSI_ISR0_PE0_Msk |
| #define | DSI_ISR0_PE1_Pos (17U) |
| #define | DSI_ISR0_PE1_Msk (0x1UL << DSI_ISR0_PE1_Pos) |
| #define | DSI_ISR0_PE1 DSI_ISR0_PE1_Msk |
| #define | DSI_ISR0_PE2_Pos (18U) |
| #define | DSI_ISR0_PE2_Msk (0x1UL << DSI_ISR0_PE2_Pos) |
| #define | DSI_ISR0_PE2 DSI_ISR0_PE2_Msk |
| #define | DSI_ISR0_PE3_Pos (19U) |
| #define | DSI_ISR0_PE3_Msk (0x1UL << DSI_ISR0_PE3_Pos) |
| #define | DSI_ISR0_PE3 DSI_ISR0_PE3_Msk |
| #define | DSI_ISR0_PE4_Pos (20U) |
| #define | DSI_ISR0_PE4_Msk (0x1UL << DSI_ISR0_PE4_Pos) |
| #define | DSI_ISR0_PE4 DSI_ISR0_PE4_Msk |
| #define | DSI_ISR1_TOHSTX_Pos (0U) |
| #define | DSI_ISR1_TOHSTX_Msk (0x1UL << DSI_ISR1_TOHSTX_Pos) |
| #define | DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk |
| #define | DSI_ISR1_TOLPRX_Pos (1U) |
| #define | DSI_ISR1_TOLPRX_Msk (0x1UL << DSI_ISR1_TOLPRX_Pos) |
| #define | DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk |
| #define | DSI_ISR1_ECCSE_Pos (2U) |
| #define | DSI_ISR1_ECCSE_Msk (0x1UL << DSI_ISR1_ECCSE_Pos) |
| #define | DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk |
| #define | DSI_ISR1_ECCME_Pos (3U) |
| #define | DSI_ISR1_ECCME_Msk (0x1UL << DSI_ISR1_ECCME_Pos) |
| #define | DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk |
| #define | DSI_ISR1_CRCE_Pos (4U) |
| #define | DSI_ISR1_CRCE_Msk (0x1UL << DSI_ISR1_CRCE_Pos) |
| #define | DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk |
| #define | DSI_ISR1_PSE_Pos (5U) |
| #define | DSI_ISR1_PSE_Msk (0x1UL << DSI_ISR1_PSE_Pos) |
| #define | DSI_ISR1_PSE DSI_ISR1_PSE_Msk |
| #define | DSI_ISR1_EOTPE_Pos (6U) |
| #define | DSI_ISR1_EOTPE_Msk (0x1UL << DSI_ISR1_EOTPE_Pos) |
| #define | DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk |
| #define | DSI_ISR1_LPWRE_Pos (7U) |
| #define | DSI_ISR1_LPWRE_Msk (0x1UL << DSI_ISR1_LPWRE_Pos) |
| #define | DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk |
| #define | DSI_ISR1_GCWRE_Pos (8U) |
| #define | DSI_ISR1_GCWRE_Msk (0x1UL << DSI_ISR1_GCWRE_Pos) |
| #define | DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk |
| #define | DSI_ISR1_GPWRE_Pos (9U) |
| #define | DSI_ISR1_GPWRE_Msk (0x1UL << DSI_ISR1_GPWRE_Pos) |
| #define | DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk |
| #define | DSI_ISR1_GPTXE_Pos (10U) |
| #define | DSI_ISR1_GPTXE_Msk (0x1UL << DSI_ISR1_GPTXE_Pos) |
| #define | DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk |
| #define | DSI_ISR1_GPRDE_Pos (11U) |
| #define | DSI_ISR1_GPRDE_Msk (0x1UL << DSI_ISR1_GPRDE_Pos) |
| #define | DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk |
| #define | DSI_ISR1_GPRXE_Pos (12U) |
| #define | DSI_ISR1_GPRXE_Msk (0x1UL << DSI_ISR1_GPRXE_Pos) |
| #define | DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk |
| #define | DSI_ISR1_PBUE_Pos (19U) |
| #define | DSI_ISR1_PBUE_Msk (0x1UL << DSI_ISR1_PBUE_Pos) |
| #define | DSI_ISR1_PBUE DSI_ISR1_PBUE_Msk |
| #define | DSI_IER0_AE0IE_Pos (0U) |
| #define | DSI_IER0_AE0IE_Msk (0x1UL << DSI_IER0_AE0IE_Pos) |
| #define | DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk |
| #define | DSI_IER0_AE1IE_Pos (1U) |
| #define | DSI_IER0_AE1IE_Msk (0x1UL << DSI_IER0_AE1IE_Pos) |
| #define | DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk |
| #define | DSI_IER0_AE2IE_Pos (2U) |
| #define | DSI_IER0_AE2IE_Msk (0x1UL << DSI_IER0_AE2IE_Pos) |
| #define | DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk |
| #define | DSI_IER0_AE3IE_Pos (3U) |
| #define | DSI_IER0_AE3IE_Msk (0x1UL << DSI_IER0_AE3IE_Pos) |
| #define | DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk |
| #define | DSI_IER0_AE4IE_Pos (4U) |
| #define | DSI_IER0_AE4IE_Msk (0x1UL << DSI_IER0_AE4IE_Pos) |
| #define | DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk |
| #define | DSI_IER0_AE5IE_Pos (5U) |
| #define | DSI_IER0_AE5IE_Msk (0x1UL << DSI_IER0_AE5IE_Pos) |
| #define | DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk |
| #define | DSI_IER0_AE6IE_Pos (6U) |
| #define | DSI_IER0_AE6IE_Msk (0x1UL << DSI_IER0_AE6IE_Pos) |
| #define | DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk |
| #define | DSI_IER0_AE7IE_Pos (7U) |
| #define | DSI_IER0_AE7IE_Msk (0x1UL << DSI_IER0_AE7IE_Pos) |
| #define | DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk |
| #define | DSI_IER0_AE8IE_Pos (8U) |
| #define | DSI_IER0_AE8IE_Msk (0x1UL << DSI_IER0_AE8IE_Pos) |
| #define | DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk |
| #define | DSI_IER0_AE9IE_Pos (9U) |
| #define | DSI_IER0_AE9IE_Msk (0x1UL << DSI_IER0_AE9IE_Pos) |
| #define | DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk |
| #define | DSI_IER0_AE10IE_Pos (10U) |
| #define | DSI_IER0_AE10IE_Msk (0x1UL << DSI_IER0_AE10IE_Pos) |
| #define | DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk |
| #define | DSI_IER0_AE11IE_Pos (11U) |
| #define | DSI_IER0_AE11IE_Msk (0x1UL << DSI_IER0_AE11IE_Pos) |
| #define | DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk |
| #define | DSI_IER0_AE12IE_Pos (12U) |
| #define | DSI_IER0_AE12IE_Msk (0x1UL << DSI_IER0_AE12IE_Pos) |
| #define | DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk |
| #define | DSI_IER0_AE13IE_Pos (13U) |
| #define | DSI_IER0_AE13IE_Msk (0x1UL << DSI_IER0_AE13IE_Pos) |
| #define | DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk |
| #define | DSI_IER0_AE14IE_Pos (14U) |
| #define | DSI_IER0_AE14IE_Msk (0x1UL << DSI_IER0_AE14IE_Pos) |
| #define | DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk |
| #define | DSI_IER0_AE15IE_Pos (15U) |
| #define | DSI_IER0_AE15IE_Msk (0x1UL << DSI_IER0_AE15IE_Pos) |
| #define | DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk |
| #define | DSI_IER0_PE0IE_Pos (16U) |
| #define | DSI_IER0_PE0IE_Msk (0x1UL << DSI_IER0_PE0IE_Pos) |
| #define | DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk |
| #define | DSI_IER0_PE1IE_Pos (17U) |
| #define | DSI_IER0_PE1IE_Msk (0x1UL << DSI_IER0_PE1IE_Pos) |
| #define | DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk |
| #define | DSI_IER0_PE2IE_Pos (18U) |
| #define | DSI_IER0_PE2IE_Msk (0x1UL << DSI_IER0_PE2IE_Pos) |
| #define | DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk |
| #define | DSI_IER0_PE3IE_Pos (19U) |
| #define | DSI_IER0_PE3IE_Msk (0x1UL << DSI_IER0_PE3IE_Pos) |
| #define | DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk |
| #define | DSI_IER0_PE4IE_Pos (20U) |
| #define | DSI_IER0_PE4IE_Msk (0x1UL << DSI_IER0_PE4IE_Pos) |
| #define | DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk |
| #define | DSI_IER1_TOHSTXIE_Pos (0U) |
| #define | DSI_IER1_TOHSTXIE_Msk (0x1UL << DSI_IER1_TOHSTXIE_Pos) |
| #define | DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk |
| #define | DSI_IER1_TOLPRXIE_Pos (1U) |
| #define | DSI_IER1_TOLPRXIE_Msk (0x1UL << DSI_IER1_TOLPRXIE_Pos) |
| #define | DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk |
| #define | DSI_IER1_ECCSEIE_Pos (2U) |
| #define | DSI_IER1_ECCSEIE_Msk (0x1UL << DSI_IER1_ECCSEIE_Pos) |
| #define | DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk |
| #define | DSI_IER1_ECCMEIE_Pos (3U) |
| #define | DSI_IER1_ECCMEIE_Msk (0x1UL << DSI_IER1_ECCMEIE_Pos) |
| #define | DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk |
| #define | DSI_IER1_CRCEIE_Pos (4U) |
| #define | DSI_IER1_CRCEIE_Msk (0x1UL << DSI_IER1_CRCEIE_Pos) |
| #define | DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk |
| #define | DSI_IER1_PSEIE_Pos (5U) |
| #define | DSI_IER1_PSEIE_Msk (0x1UL << DSI_IER1_PSEIE_Pos) |
| #define | DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk |
| #define | DSI_IER1_EOTPEIE_Pos (6U) |
| #define | DSI_IER1_EOTPEIE_Msk (0x1UL << DSI_IER1_EOTPEIE_Pos) |
| #define | DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk |
| #define | DSI_IER1_LPWREIE_Pos (7U) |
| #define | DSI_IER1_LPWREIE_Msk (0x1UL << DSI_IER1_LPWREIE_Pos) |
| #define | DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk |
| #define | DSI_IER1_GCWREIE_Pos (8U) |
| #define | DSI_IER1_GCWREIE_Msk (0x1UL << DSI_IER1_GCWREIE_Pos) |
| #define | DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk |
| #define | DSI_IER1_GPWREIE_Pos (9U) |
| #define | DSI_IER1_GPWREIE_Msk (0x1UL << DSI_IER1_GPWREIE_Pos) |
| #define | DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk |
| #define | DSI_IER1_GPTXEIE_Pos (10U) |
| #define | DSI_IER1_GPTXEIE_Msk (0x1UL << DSI_IER1_GPTXEIE_Pos) |
| #define | DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk |
| #define | DSI_IER1_GPRDEIE_Pos (11U) |
| #define | DSI_IER1_GPRDEIE_Msk (0x1UL << DSI_IER1_GPRDEIE_Pos) |
| #define | DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk |
| #define | DSI_IER1_GPRXEIE_Pos (12U) |
| #define | DSI_IER1_GPRXEIE_Msk (0x1UL << DSI_IER1_GPRXEIE_Pos) |
| #define | DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk |
| #define | DSI_IER1_PBUEIE_Pos (19U) |
| #define | DSI_IER1_PBUEIE_Msk (0x1UL << DSI_IER1_PBUEIE_Pos) |
| #define | DSI_IER1_PBUEIE DSI_IER1_PBUEIE_Msk |
| #define | DSI_FIR0_FAE0_Pos (0U) |
| #define | DSI_FIR0_FAE0_Msk (0x1UL << DSI_FIR0_FAE0_Pos) |
| #define | DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk |
| #define | DSI_FIR0_FAE1_Pos (1U) |
| #define | DSI_FIR0_FAE1_Msk (0x1UL << DSI_FIR0_FAE1_Pos) |
| #define | DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk |
| #define | DSI_FIR0_FAE2_Pos (2U) |
| #define | DSI_FIR0_FAE2_Msk (0x1UL << DSI_FIR0_FAE2_Pos) |
| #define | DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk |
| #define | DSI_FIR0_FAE3_Pos (3U) |
| #define | DSI_FIR0_FAE3_Msk (0x1UL << DSI_FIR0_FAE3_Pos) |
| #define | DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk |
| #define | DSI_FIR0_FAE4_Pos (4U) |
| #define | DSI_FIR0_FAE4_Msk (0x1UL << DSI_FIR0_FAE4_Pos) |
| #define | DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk |
| #define | DSI_FIR0_FAE5_Pos (5U) |
| #define | DSI_FIR0_FAE5_Msk (0x1UL << DSI_FIR0_FAE5_Pos) |
| #define | DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk |
| #define | DSI_FIR0_FAE6_Pos (6U) |
| #define | DSI_FIR0_FAE6_Msk (0x1UL << DSI_FIR0_FAE6_Pos) |
| #define | DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk |
| #define | DSI_FIR0_FAE7_Pos (7U) |
| #define | DSI_FIR0_FAE7_Msk (0x1UL << DSI_FIR0_FAE7_Pos) |
| #define | DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk |
| #define | DSI_FIR0_FAE8_Pos (8U) |
| #define | DSI_FIR0_FAE8_Msk (0x1UL << DSI_FIR0_FAE8_Pos) |
| #define | DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk |
| #define | DSI_FIR0_FAE9_Pos (9U) |
| #define | DSI_FIR0_FAE9_Msk (0x1UL << DSI_FIR0_FAE9_Pos) |
| #define | DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk |
| #define | DSI_FIR0_FAE10_Pos (10U) |
| #define | DSI_FIR0_FAE10_Msk (0x1UL << DSI_FIR0_FAE10_Pos) |
| #define | DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk |
| #define | DSI_FIR0_FAE11_Pos (11U) |
| #define | DSI_FIR0_FAE11_Msk (0x1UL << DSI_FIR0_FAE11_Pos) |
| #define | DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk |
| #define | DSI_FIR0_FAE12_Pos (12U) |
| #define | DSI_FIR0_FAE12_Msk (0x1UL << DSI_FIR0_FAE12_Pos) |
| #define | DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk |
| #define | DSI_FIR0_FAE13_Pos (13U) |
| #define | DSI_FIR0_FAE13_Msk (0x1UL << DSI_FIR0_FAE13_Pos) |
| #define | DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk |
| #define | DSI_FIR0_FAE14_Pos (14U) |
| #define | DSI_FIR0_FAE14_Msk (0x1UL << DSI_FIR0_FAE14_Pos) |
| #define | DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk |
| #define | DSI_FIR0_FAE15_Pos (15U) |
| #define | DSI_FIR0_FAE15_Msk (0x1UL << DSI_FIR0_FAE15_Pos) |
| #define | DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk |
| #define | DSI_FIR0_FPE0_Pos (16U) |
| #define | DSI_FIR0_FPE0_Msk (0x1UL << DSI_FIR0_FPE0_Pos) |
| #define | DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk |
| #define | DSI_FIR0_FPE1_Pos (17U) |
| #define | DSI_FIR0_FPE1_Msk (0x1UL << DSI_FIR0_FPE1_Pos) |
| #define | DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk |
| #define | DSI_FIR0_FPE2_Pos (18U) |
| #define | DSI_FIR0_FPE2_Msk (0x1UL << DSI_FIR0_FPE2_Pos) |
| #define | DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk |
| #define | DSI_FIR0_FPE3_Pos (19U) |
| #define | DSI_FIR0_FPE3_Msk (0x1UL << DSI_FIR0_FPE3_Pos) |
| #define | DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk |
| #define | DSI_FIR0_FPE4_Pos (20U) |
| #define | DSI_FIR0_FPE4_Msk (0x1UL << DSI_FIR0_FPE4_Pos) |
| #define | DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk |
| #define | DSI_FIR1_FTOHSTX_Pos (0U) |
| #define | DSI_FIR1_FTOHSTX_Msk (0x1UL << DSI_FIR1_FTOHSTX_Pos) |
| #define | DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk |
| #define | DSI_FIR1_FTOLPRX_Pos (1U) |
| #define | DSI_FIR1_FTOLPRX_Msk (0x1UL << DSI_FIR1_FTOLPRX_Pos) |
| #define | DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk |
| #define | DSI_FIR1_FECCSE_Pos (2U) |
| #define | DSI_FIR1_FECCSE_Msk (0x1UL << DSI_FIR1_FECCSE_Pos) |
| #define | DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk |
| #define | DSI_FIR1_FECCME_Pos (3U) |
| #define | DSI_FIR1_FECCME_Msk (0x1UL << DSI_FIR1_FECCME_Pos) |
| #define | DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk |
| #define | DSI_FIR1_FCRCE_Pos (4U) |
| #define | DSI_FIR1_FCRCE_Msk (0x1UL << DSI_FIR1_FCRCE_Pos) |
| #define | DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk |
| #define | DSI_FIR1_FPSE_Pos (5U) |
| #define | DSI_FIR1_FPSE_Msk (0x1UL << DSI_FIR1_FPSE_Pos) |
| #define | DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk |
| #define | DSI_FIR1_FEOTPE_Pos (6U) |
| #define | DSI_FIR1_FEOTPE_Msk (0x1UL << DSI_FIR1_FEOTPE_Pos) |
| #define | DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk |
| #define | DSI_FIR1_FLPWRE_Pos (7U) |
| #define | DSI_FIR1_FLPWRE_Msk (0x1UL << DSI_FIR1_FLPWRE_Pos) |
| #define | DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk |
| #define | DSI_FIR1_FGCWRE_Pos (8U) |
| #define | DSI_FIR1_FGCWRE_Msk (0x1UL << DSI_FIR1_FGCWRE_Pos) |
| #define | DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk |
| #define | DSI_FIR1_FGPWRE_Pos (9U) |
| #define | DSI_FIR1_FGPWRE_Msk (0x1UL << DSI_FIR1_FGPWRE_Pos) |
| #define | DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk |
| #define | DSI_FIR1_FGPTXE_Pos (10U) |
| #define | DSI_FIR1_FGPTXE_Msk (0x1UL << DSI_FIR1_FGPTXE_Pos) |
| #define | DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk |
| #define | DSI_FIR1_FGPRDE_Pos (11U) |
| #define | DSI_FIR1_FGPRDE_Msk (0x1UL << DSI_FIR1_FGPRDE_Pos) |
| #define | DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk |
| #define | DSI_FIR1_FGPRXE_Pos (12U) |
| #define | DSI_FIR1_FGPRXE_Msk (0x1UL << DSI_FIR1_FGPRXE_Pos) |
| #define | DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk |
| #define | DSI_FIR1_FPBUE_Pos (19U) |
| #define | DSI_FIR1_FPBUE_Msk (0x1UL << DSI_FIR1_FPBUE_Pos) |
| #define | DSI_FIR1_FPBUE DSI_FIR1_FPBUE_Msk |
| #define | DSI_DLTRCR_MRD_TIME_Pos (0U) |
| #define | DSI_DLTRCR_MRD_TIME_Msk (0x7FFFUL << DSI_DLTRCR_MRD_TIME_Pos) |
| #define | DSI_DLTRCR_MRD_TIME DSI_DLTRCR_MRD_TIME_Msk |
| #define | DSI_DLTRCR_MRD_TIME0_Pos (0U) |
| #define | DSI_DLTRCR_MRD_TIME0_Msk (0x1UL << DSI_DLTRCR_MRD_TIME0_Pos) |
| #define | DSI_DLTRCR_MRD_TIME0 DSI_DLTRCR_MRD_TIME0_Msk |
| #define | DSI_DLTRCR_MRD_TIME1_Pos (1U) |
| #define | DSI_DLTRCR_MRD_TIME1_Msk (0x1UL << DSI_DLTRCR_MRD_TIME1_Pos) |
| #define | DSI_DLTRCR_MRD_TIME1 DSI_DLTRCR_MRD_TIME1_Msk |
| #define | DSI_DLTRCR_MRD_TIME2_Pos (2U) |
| #define | DSI_DLTRCR_MRD_TIME2_Msk (0x1UL << DSI_DLTRCR_MRD_TIME2_Pos) |
| #define | DSI_DLTRCR_MRD_TIME2 DSI_DLTRCR_MRD_TIME2_Msk |
| #define | DSI_DLTRCR_MRD_TIME3_Pos (3U) |
| #define | DSI_DLTRCR_MRD_TIME3_Msk (0x1UL << DSI_DLTRCR_MRD_TIME3_Pos) |
| #define | DSI_DLTRCR_MRD_TIME3 DSI_DLTRCR_MRD_TIME3_Msk |
| #define | DSI_DLTRCR_MRD_TIME4_Pos (4U) |
| #define | DSI_DLTRCR_MRD_TIME4_Msk (0x1UL << DSI_DLTRCR_MRD_TIME4_Pos) |
| #define | DSI_DLTRCR_MRD_TIME4 DSI_DLTRCR_MRD_TIME4_Msk |
| #define | DSI_DLTRCR_MRD_TIME5_Pos (5U) |
| #define | DSI_DLTRCR_MRD_TIME5_Msk (0x1UL << DSI_DLTRCR_MRD_TIME5_Pos) |
| #define | DSI_DLTRCR_MRD_TIME5 DSI_DLTRCR_MRD_TIME5_Msk |
| #define | DSI_DLTRCR_MRD_TIME6_Pos (6U) |
| #define | DSI_DLTRCR_MRD_TIME6_Msk (0x1UL << DSI_DLTRCR_MRD_TIME6_Pos) |
| #define | DSI_DLTRCR_MRD_TIME6 DSI_DLTRCR_MRD_TIME6_Msk |
| #define | DSI_DLTRCR_MRD_TIME7_Pos (7U) |
| #define | DSI_DLTRCR_MRD_TIME7_Msk (0x1UL << DSI_DLTRCR_MRD_TIME7_Pos) |
| #define | DSI_DLTRCR_MRD_TIME7 DSI_DLTRCR_MRD_TIME7_Msk |
| #define | DSI_DLTRCR_MRD_TIME8_Pos (8U) |
| #define | DSI_DLTRCR_MRD_TIME8_Msk (0x1UL << DSI_DLTRCR_MRD_TIME8_Pos) |
| #define | DSI_DLTRCR_MRD_TIME8 DSI_DLTRCR_MRD_TIME8_Msk |
| #define | DSI_DLTRCR_MRD_TIME9_Pos (9U) |
| #define | DSI_DLTRCR_MRD_TIME9_Msk (0x1UL << DSI_DLTRCR_MRD_TIME9_Pos) |
| #define | DSI_DLTRCR_MRD_TIME9 DSI_DLTRCR_MRD_TIME9_Msk |
| #define | DSI_DLTRCR_MRD_TIME10_Pos (10U) |
| #define | DSI_DLTRCR_MRD_TIME10_Msk (0x1UL << DSI_DLTRCR_MRD_TIME10_Pos) |
| #define | DSI_DLTRCR_MRD_TIME10 DSI_DLTRCR_MRD_TIME10_Msk |
| #define | DSI_DLTRCR_MRD_TIME11_Pos (11U) |
| #define | DSI_DLTRCR_MRD_TIME11_Msk (0x1UL << DSI_DLTRCR_MRD_TIME11_Pos) |
| #define | DSI_DLTRCR_MRD_TIME11 DSI_DLTRCR_MRD_TIME11_Msk |
| #define | DSI_DLTRCR_MRD_TIME12_Pos (12U) |
| #define | DSI_DLTRCR_MRD_TIME12_Msk (0x1UL << DSI_DLTRCR_MRD_TIME12_Pos) |
| #define | DSI_DLTRCR_MRD_TIME12 DSI_DLTRCR_MRD_TIME12_Msk |
| #define | DSI_DLTRCR_MRD_TIME13_Pos (13U) |
| #define | DSI_DLTRCR_MRD_TIME13_Msk (0x1UL << DSI_DLTRCR_MRD_TIME13_Pos) |
| #define | DSI_DLTRCR_MRD_TIME13 DSI_DLTRCR_MRD_TIME13_Msk |
| #define | DSI_DLTRCR_MRD_TIME14_Pos (14U) |
| #define | DSI_DLTRCR_MRD_TIME14_Msk (0x1UL << DSI_DLTRCR_MRD_TIME14_Pos) |
| #define | DSI_DLTRCR_MRD_TIME14 DSI_DLTRCR_MRD_TIME14_Msk |
| #define | DSI_VSCR_EN_Pos (0U) |
| #define | DSI_VSCR_EN_Msk (0x1UL << DSI_VSCR_EN_Pos) |
| #define | DSI_VSCR_EN DSI_VSCR_EN_Msk |
| #define | DSI_VSCR_UR_Pos (8U) |
| #define | DSI_VSCR_UR_Msk (0x1UL << DSI_VSCR_UR_Pos) |
| #define | DSI_VSCR_UR DSI_VSCR_UR_Msk |
| #define | DSI_LCVCIDR_VCID_Pos (0U) |
| #define | DSI_LCVCIDR_VCID_Msk (0x3UL << DSI_LCVCIDR_VCID_Pos) |
| #define | DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk |
| #define | DSI_LCVCIDR_VCID0_Pos (0U) |
| #define | DSI_LCVCIDR_VCID0_Msk (0x1UL << DSI_LCVCIDR_VCID0_Pos) |
| #define | DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk |
| #define | DSI_LCVCIDR_VCID1_Pos (1U) |
| #define | DSI_LCVCIDR_VCID1_Msk (0x1UL << DSI_LCVCIDR_VCID1_Pos) |
| #define | DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk |
| #define | DSI_LCCCR_COLC_Pos (0U) |
| #define | DSI_LCCCR_COLC_Msk (0xFUL << DSI_LCCCR_COLC_Pos) |
| #define | DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk |
| #define | DSI_LCCCR_COLC0_Pos (0U) |
| #define | DSI_LCCCR_COLC0_Msk (0x1UL << DSI_LCCCR_COLC0_Pos) |
| #define | DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk |
| #define | DSI_LCCCR_COLC1_Pos (1U) |
| #define | DSI_LCCCR_COLC1_Msk (0x1UL << DSI_LCCCR_COLC1_Pos) |
| #define | DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk |
| #define | DSI_LCCCR_COLC2_Pos (2U) |
| #define | DSI_LCCCR_COLC2_Msk (0x1UL << DSI_LCCCR_COLC2_Pos) |
| #define | DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk |
| #define | DSI_LCCCR_COLC3_Pos (3U) |
| #define | DSI_LCCCR_COLC3_Msk (0x1UL << DSI_LCCCR_COLC3_Pos) |
| #define | DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk |
| #define | DSI_LCCCR_LPE_Pos (8U) |
| #define | DSI_LCCCR_LPE_Msk (0x1UL << DSI_LCCCR_LPE_Pos) |
| #define | DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk |
| #define | DSI_LPMCCR_VLPSIZE_Pos (0U) |
| #define | DSI_LPMCCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCCR_VLPSIZE_Pos) |
| #define | DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk |
| #define | DSI_LPMCCR_VLPSIZE0_Pos (0U) |
| #define | DSI_LPMCCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCCR_VLPSIZE0_Pos) |
| #define | DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk |
| #define | DSI_LPMCCR_VLPSIZE1_Pos (1U) |
| #define | DSI_LPMCCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCCR_VLPSIZE1_Pos) |
| #define | DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk |
| #define | DSI_LPMCCR_VLPSIZE2_Pos (2U) |
| #define | DSI_LPMCCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCCR_VLPSIZE2_Pos) |
| #define | DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk |
| #define | DSI_LPMCCR_VLPSIZE3_Pos (3U) |
| #define | DSI_LPMCCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCCR_VLPSIZE3_Pos) |
| #define | DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk |
| #define | DSI_LPMCCR_VLPSIZE4_Pos (4U) |
| #define | DSI_LPMCCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCCR_VLPSIZE4_Pos) |
| #define | DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk |
| #define | DSI_LPMCCR_VLPSIZE5_Pos (5U) |
| #define | DSI_LPMCCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCCR_VLPSIZE5_Pos) |
| #define | DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk |
| #define | DSI_LPMCCR_VLPSIZE6_Pos (6U) |
| #define | DSI_LPMCCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCCR_VLPSIZE6_Pos) |
| #define | DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk |
| #define | DSI_LPMCCR_VLPSIZE7_Pos (7U) |
| #define | DSI_LPMCCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCCR_VLPSIZE7_Pos) |
| #define | DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk |
| #define | DSI_LPMCCR_LPSIZE_Pos (16U) |
| #define | DSI_LPMCCR_LPSIZE_Msk (0xFFUL << DSI_LPMCCR_LPSIZE_Pos) |
| #define | DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk |
| #define | DSI_LPMCCR_LPSIZE0_Pos (16U) |
| #define | DSI_LPMCCR_LPSIZE0_Msk (0x1UL << DSI_LPMCCR_LPSIZE0_Pos) |
| #define | DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk |
| #define | DSI_LPMCCR_LPSIZE1_Pos (17U) |
| #define | DSI_LPMCCR_LPSIZE1_Msk (0x1UL << DSI_LPMCCR_LPSIZE1_Pos) |
| #define | DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk |
| #define | DSI_LPMCCR_LPSIZE2_Pos (18U) |
| #define | DSI_LPMCCR_LPSIZE2_Msk (0x1UL << DSI_LPMCCR_LPSIZE2_Pos) |
| #define | DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk |
| #define | DSI_LPMCCR_LPSIZE3_Pos (19U) |
| #define | DSI_LPMCCR_LPSIZE3_Msk (0x1UL << DSI_LPMCCR_LPSIZE3_Pos) |
| #define | DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk |
| #define | DSI_LPMCCR_LPSIZE4_Pos (20U) |
| #define | DSI_LPMCCR_LPSIZE4_Msk (0x1UL << DSI_LPMCCR_LPSIZE4_Pos) |
| #define | DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk |
| #define | DSI_LPMCCR_LPSIZE5_Pos (21U) |
| #define | DSI_LPMCCR_LPSIZE5_Msk (0x1UL << DSI_LPMCCR_LPSIZE5_Pos) |
| #define | DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk |
| #define | DSI_LPMCCR_LPSIZE6_Pos (22U) |
| #define | DSI_LPMCCR_LPSIZE6_Msk (0x1UL << DSI_LPMCCR_LPSIZE6_Pos) |
| #define | DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk |
| #define | DSI_LPMCCR_LPSIZE7_Pos (23U) |
| #define | DSI_LPMCCR_LPSIZE7_Msk (0x1UL << DSI_LPMCCR_LPSIZE7_Pos) |
| #define | DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk |
| #define | DSI_VMCCR_VMT_Pos (0U) |
| #define | DSI_VMCCR_VMT_Msk (0x3UL << DSI_VMCCR_VMT_Pos) |
| #define | DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk |
| #define | DSI_VMCCR_VMT0_Pos (0U) |
| #define | DSI_VMCCR_VMT0_Msk (0x1UL << DSI_VMCCR_VMT0_Pos) |
| #define | DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk |
| #define | DSI_VMCCR_VMT1_Pos (1U) |
| #define | DSI_VMCCR_VMT1_Msk (0x1UL << DSI_VMCCR_VMT1_Pos) |
| #define | DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk |
| #define | DSI_VMCCR_LPVSAE_Pos (8U) |
| #define | DSI_VMCCR_LPVSAE_Msk (0x1UL << DSI_VMCCR_LPVSAE_Pos) |
| #define | DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk |
| #define | DSI_VMCCR_LPVBPE_Pos (9U) |
| #define | DSI_VMCCR_LPVBPE_Msk (0x1UL << DSI_VMCCR_LPVBPE_Pos) |
| #define | DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk |
| #define | DSI_VMCCR_LPVFPE_Pos (10U) |
| #define | DSI_VMCCR_LPVFPE_Msk (0x1UL << DSI_VMCCR_LPVFPE_Pos) |
| #define | DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk |
| #define | DSI_VMCCR_LPVAE_Pos (11U) |
| #define | DSI_VMCCR_LPVAE_Msk (0x1UL << DSI_VMCCR_LPVAE_Pos) |
| #define | DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk |
| #define | DSI_VMCCR_LPHBPE_Pos (12U) |
| #define | DSI_VMCCR_LPHBPE_Msk (0x1UL << DSI_VMCCR_LPHBPE_Pos) |
| #define | DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk |
| #define | DSI_VMCCR_LPHFE_Pos (13U) |
| #define | DSI_VMCCR_LPHFE_Msk (0x1UL << DSI_VMCCR_LPHFE_Pos) |
| #define | DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk |
| #define | DSI_VMCCR_FBTAAE_Pos (14U) |
| #define | DSI_VMCCR_FBTAAE_Msk (0x1UL << DSI_VMCCR_FBTAAE_Pos) |
| #define | DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk |
| #define | DSI_VMCCR_LPCE_Pos (15U) |
| #define | DSI_VMCCR_LPCE_Msk (0x1UL << DSI_VMCCR_LPCE_Pos) |
| #define | DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk |
| #define | DSI_VPCCR_VPSIZE_Pos (0U) |
| #define | DSI_VPCCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCCR_VPSIZE_Pos) |
| #define | DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk |
| #define | DSI_VPCCR_VPSIZE0_Pos (0U) |
| #define | DSI_VPCCR_VPSIZE0_Msk (0x1UL << DSI_VPCCR_VPSIZE0_Pos) |
| #define | DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk |
| #define | DSI_VPCCR_VPSIZE1_Pos (1U) |
| #define | DSI_VPCCR_VPSIZE1_Msk (0x1UL << DSI_VPCCR_VPSIZE1_Pos) |
| #define | DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk |
| #define | DSI_VPCCR_VPSIZE2_Pos (2U) |
| #define | DSI_VPCCR_VPSIZE2_Msk (0x1UL << DSI_VPCCR_VPSIZE2_Pos) |
| #define | DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk |
| #define | DSI_VPCCR_VPSIZE3_Pos (3U) |
| #define | DSI_VPCCR_VPSIZE3_Msk (0x1UL << DSI_VPCCR_VPSIZE3_Pos) |
| #define | DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk |
| #define | DSI_VPCCR_VPSIZE4_Pos (4U) |
| #define | DSI_VPCCR_VPSIZE4_Msk (0x1UL << DSI_VPCCR_VPSIZE4_Pos) |
| #define | DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk |
| #define | DSI_VPCCR_VPSIZE5_Pos (5U) |
| #define | DSI_VPCCR_VPSIZE5_Msk (0x1UL << DSI_VPCCR_VPSIZE5_Pos) |
| #define | DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk |
| #define | DSI_VPCCR_VPSIZE6_Pos (6U) |
| #define | DSI_VPCCR_VPSIZE6_Msk (0x1UL << DSI_VPCCR_VPSIZE6_Pos) |
| #define | DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk |
| #define | DSI_VPCCR_VPSIZE7_Pos (7U) |
| #define | DSI_VPCCR_VPSIZE7_Msk (0x1UL << DSI_VPCCR_VPSIZE7_Pos) |
| #define | DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk |
| #define | DSI_VPCCR_VPSIZE8_Pos (8U) |
| #define | DSI_VPCCR_VPSIZE8_Msk (0x1UL << DSI_VPCCR_VPSIZE8_Pos) |
| #define | DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk |
| #define | DSI_VPCCR_VPSIZE9_Pos (9U) |
| #define | DSI_VPCCR_VPSIZE9_Msk (0x1UL << DSI_VPCCR_VPSIZE9_Pos) |
| #define | DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk |
| #define | DSI_VPCCR_VPSIZE10_Pos (10U) |
| #define | DSI_VPCCR_VPSIZE10_Msk (0x1UL << DSI_VPCCR_VPSIZE10_Pos) |
| #define | DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk |
| #define | DSI_VPCCR_VPSIZE11_Pos (11U) |
| #define | DSI_VPCCR_VPSIZE11_Msk (0x1UL << DSI_VPCCR_VPSIZE11_Pos) |
| #define | DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk |
| #define | DSI_VPCCR_VPSIZE12_Pos (12U) |
| #define | DSI_VPCCR_VPSIZE12_Msk (0x1UL << DSI_VPCCR_VPSIZE12_Pos) |
| #define | DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk |
| #define | DSI_VPCCR_VPSIZE13_Pos (13U) |
| #define | DSI_VPCCR_VPSIZE13_Msk (0x1UL << DSI_VPCCR_VPSIZE13_Pos) |
| #define | DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk |
| #define | DSI_VCCCR_NUMC_Pos (0U) |
| #define | DSI_VCCCR_NUMC_Msk (0x1FFFUL << DSI_VCCCR_NUMC_Pos) |
| #define | DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk |
| #define | DSI_VCCCR_NUMC0_Pos (0U) |
| #define | DSI_VCCCR_NUMC0_Msk (0x1UL << DSI_VCCCR_NUMC0_Pos) |
| #define | DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk |
| #define | DSI_VCCCR_NUMC1_Pos (1U) |
| #define | DSI_VCCCR_NUMC1_Msk (0x1UL << DSI_VCCCR_NUMC1_Pos) |
| #define | DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk |
| #define | DSI_VCCCR_NUMC2_Pos (2U) |
| #define | DSI_VCCCR_NUMC2_Msk (0x1UL << DSI_VCCCR_NUMC2_Pos) |
| #define | DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk |
| #define | DSI_VCCCR_NUMC3_Pos (3U) |
| #define | DSI_VCCCR_NUMC3_Msk (0x1UL << DSI_VCCCR_NUMC3_Pos) |
| #define | DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk |
| #define | DSI_VCCCR_NUMC4_Pos (4U) |
| #define | DSI_VCCCR_NUMC4_Msk (0x1UL << DSI_VCCCR_NUMC4_Pos) |
| #define | DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk |
| #define | DSI_VCCCR_NUMC5_Pos (5U) |
| #define | DSI_VCCCR_NUMC5_Msk (0x1UL << DSI_VCCCR_NUMC5_Pos) |
| #define | DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk |
| #define | DSI_VCCCR_NUMC6_Pos (6U) |
| #define | DSI_VCCCR_NUMC6_Msk (0x1UL << DSI_VCCCR_NUMC6_Pos) |
| #define | DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk |
| #define | DSI_VCCCR_NUMC7_Pos (7U) |
| #define | DSI_VCCCR_NUMC7_Msk (0x1UL << DSI_VCCCR_NUMC7_Pos) |
| #define | DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk |
| #define | DSI_VCCCR_NUMC8_Pos (8U) |
| #define | DSI_VCCCR_NUMC8_Msk (0x1UL << DSI_VCCCR_NUMC8_Pos) |
| #define | DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk |
| #define | DSI_VCCCR_NUMC9_Pos (9U) |
| #define | DSI_VCCCR_NUMC9_Msk (0x1UL << DSI_VCCCR_NUMC9_Pos) |
| #define | DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk |
| #define | DSI_VCCCR_NUMC10_Pos (10U) |
| #define | DSI_VCCCR_NUMC10_Msk (0x1UL << DSI_VCCCR_NUMC10_Pos) |
| #define | DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk |
| #define | DSI_VCCCR_NUMC11_Pos (11U) |
| #define | DSI_VCCCR_NUMC11_Msk (0x1UL << DSI_VCCCR_NUMC11_Pos) |
| #define | DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk |
| #define | DSI_VCCCR_NUMC12_Pos (12U) |
| #define | DSI_VCCCR_NUMC12_Msk (0x1UL << DSI_VCCCR_NUMC12_Pos) |
| #define | DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk |
| #define | DSI_VNPCCR_NPSIZE_Pos (0U) |
| #define | DSI_VNPCCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCCR_NPSIZE_Pos) |
| #define | DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk |
| #define | DSI_VNPCCR_NPSIZE0_Pos (0U) |
| #define | DSI_VNPCCR_NPSIZE0_Msk (0x1UL << DSI_VNPCCR_NPSIZE0_Pos) |
| #define | DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk |
| #define | DSI_VNPCCR_NPSIZE1_Pos (1U) |
| #define | DSI_VNPCCR_NPSIZE1_Msk (0x1UL << DSI_VNPCCR_NPSIZE1_Pos) |
| #define | DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk |
| #define | DSI_VNPCCR_NPSIZE2_Pos (2U) |
| #define | DSI_VNPCCR_NPSIZE2_Msk (0x1UL << DSI_VNPCCR_NPSIZE2_Pos) |
| #define | DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk |
| #define | DSI_VNPCCR_NPSIZE3_Pos (3U) |
| #define | DSI_VNPCCR_NPSIZE3_Msk (0x1UL << DSI_VNPCCR_NPSIZE3_Pos) |
| #define | DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk |
| #define | DSI_VNPCCR_NPSIZE4_Pos (4U) |
| #define | DSI_VNPCCR_NPSIZE4_Msk (0x1UL << DSI_VNPCCR_NPSIZE4_Pos) |
| #define | DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk |
| #define | DSI_VNPCCR_NPSIZE5_Pos (5U) |
| #define | DSI_VNPCCR_NPSIZE5_Msk (0x1UL << DSI_VNPCCR_NPSIZE5_Pos) |
| #define | DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk |
| #define | DSI_VNPCCR_NPSIZE6_Pos (6U) |
| #define | DSI_VNPCCR_NPSIZE6_Msk (0x1UL << DSI_VNPCCR_NPSIZE6_Pos) |
| #define | DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk |
| #define | DSI_VNPCCR_NPSIZE7_Pos (7U) |
| #define | DSI_VNPCCR_NPSIZE7_Msk (0x1UL << DSI_VNPCCR_NPSIZE7_Pos) |
| #define | DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk |
| #define | DSI_VNPCCR_NPSIZE8_Pos (8U) |
| #define | DSI_VNPCCR_NPSIZE8_Msk (0x1UL << DSI_VNPCCR_NPSIZE8_Pos) |
| #define | DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk |
| #define | DSI_VNPCCR_NPSIZE9_Pos (9U) |
| #define | DSI_VNPCCR_NPSIZE9_Msk (0x1UL << DSI_VNPCCR_NPSIZE9_Pos) |
| #define | DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk |
| #define | DSI_VNPCCR_NPSIZE10_Pos (10U) |
| #define | DSI_VNPCCR_NPSIZE10_Msk (0x1UL << DSI_VNPCCR_NPSIZE10_Pos) |
| #define | DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk |
| #define | DSI_VNPCCR_NPSIZE11_Pos (11U) |
| #define | DSI_VNPCCR_NPSIZE11_Msk (0x1UL << DSI_VNPCCR_NPSIZE11_Pos) |
| #define | DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk |
| #define | DSI_VNPCCR_NPSIZE12_Pos (12U) |
| #define | DSI_VNPCCR_NPSIZE12_Msk (0x1UL << DSI_VNPCCR_NPSIZE12_Pos) |
| #define | DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk |
| #define | DSI_VHSACCR_HSA_Pos (0U) |
| #define | DSI_VHSACCR_HSA_Msk (0xFFFUL << DSI_VHSACCR_HSA_Pos) |
| #define | DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk |
| #define | DSI_VHSACCR_HSA0_Pos (0U) |
| #define | DSI_VHSACCR_HSA0_Msk (0x1UL << DSI_VHSACCR_HSA0_Pos) |
| #define | DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk |
| #define | DSI_VHSACCR_HSA1_Pos (1U) |
| #define | DSI_VHSACCR_HSA1_Msk (0x1UL << DSI_VHSACCR_HSA1_Pos) |
| #define | DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk |
| #define | DSI_VHSACCR_HSA2_Pos (2U) |
| #define | DSI_VHSACCR_HSA2_Msk (0x1UL << DSI_VHSACCR_HSA2_Pos) |
| #define | DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk |
| #define | DSI_VHSACCR_HSA3_Pos (3U) |
| #define | DSI_VHSACCR_HSA3_Msk (0x1UL << DSI_VHSACCR_HSA3_Pos) |
| #define | DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk |
| #define | DSI_VHSACCR_HSA4_Pos (4U) |
| #define | DSI_VHSACCR_HSA4_Msk (0x1UL << DSI_VHSACCR_HSA4_Pos) |
| #define | DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk |
| #define | DSI_VHSACCR_HSA5_Pos (5U) |
| #define | DSI_VHSACCR_HSA5_Msk (0x1UL << DSI_VHSACCR_HSA5_Pos) |
| #define | DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk |
| #define | DSI_VHSACCR_HSA6_Pos (6U) |
| #define | DSI_VHSACCR_HSA6_Msk (0x1UL << DSI_VHSACCR_HSA6_Pos) |
| #define | DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk |
| #define | DSI_VHSACCR_HSA7_Pos (7U) |
| #define | DSI_VHSACCR_HSA7_Msk (0x1UL << DSI_VHSACCR_HSA7_Pos) |
| #define | DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk |
| #define | DSI_VHSACCR_HSA8_Pos (8U) |
| #define | DSI_VHSACCR_HSA8_Msk (0x1UL << DSI_VHSACCR_HSA8_Pos) |
| #define | DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk |
| #define | DSI_VHSACCR_HSA9_Pos (9U) |
| #define | DSI_VHSACCR_HSA9_Msk (0x1UL << DSI_VHSACCR_HSA9_Pos) |
| #define | DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk |
| #define | DSI_VHSACCR_HSA10_Pos (10U) |
| #define | DSI_VHSACCR_HSA10_Msk (0x1UL << DSI_VHSACCR_HSA10_Pos) |
| #define | DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk |
| #define | DSI_VHSACCR_HSA11_Pos (11U) |
| #define | DSI_VHSACCR_HSA11_Msk (0x1UL << DSI_VHSACCR_HSA11_Pos) |
| #define | DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk |
| #define | DSI_VHBPCCR_HBP_Pos (0U) |
| #define | DSI_VHBPCCR_HBP_Msk (0xFFFUL << DSI_VHBPCCR_HBP_Pos) |
| #define | DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk |
| #define | DSI_VHBPCCR_HBP0_Pos (0U) |
| #define | DSI_VHBPCCR_HBP0_Msk (0x1UL << DSI_VHBPCCR_HBP0_Pos) |
| #define | DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk |
| #define | DSI_VHBPCCR_HBP1_Pos (1U) |
| #define | DSI_VHBPCCR_HBP1_Msk (0x1UL << DSI_VHBPCCR_HBP1_Pos) |
| #define | DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk |
| #define | DSI_VHBPCCR_HBP2_Pos (2U) |
| #define | DSI_VHBPCCR_HBP2_Msk (0x1UL << DSI_VHBPCCR_HBP2_Pos) |
| #define | DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk |
| #define | DSI_VHBPCCR_HBP3_Pos (3U) |
| #define | DSI_VHBPCCR_HBP3_Msk (0x1UL << DSI_VHBPCCR_HBP3_Pos) |
| #define | DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk |
| #define | DSI_VHBPCCR_HBP4_Pos (4U) |
| #define | DSI_VHBPCCR_HBP4_Msk (0x1UL << DSI_VHBPCCR_HBP4_Pos) |
| #define | DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk |
| #define | DSI_VHBPCCR_HBP5_Pos (5U) |
| #define | DSI_VHBPCCR_HBP5_Msk (0x1UL << DSI_VHBPCCR_HBP5_Pos) |
| #define | DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk |
| #define | DSI_VHBPCCR_HBP6_Pos (6U) |
| #define | DSI_VHBPCCR_HBP6_Msk (0x1UL << DSI_VHBPCCR_HBP6_Pos) |
| #define | DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk |
| #define | DSI_VHBPCCR_HBP7_Pos (7U) |
| #define | DSI_VHBPCCR_HBP7_Msk (0x1UL << DSI_VHBPCCR_HBP7_Pos) |
| #define | DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk |
| #define | DSI_VHBPCCR_HBP8_Pos (8U) |
| #define | DSI_VHBPCCR_HBP8_Msk (0x1UL << DSI_VHBPCCR_HBP8_Pos) |
| #define | DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk |
| #define | DSI_VHBPCCR_HBP9_Pos (9U) |
| #define | DSI_VHBPCCR_HBP9_Msk (0x1UL << DSI_VHBPCCR_HBP9_Pos) |
| #define | DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk |
| #define | DSI_VHBPCCR_HBP10_Pos (10U) |
| #define | DSI_VHBPCCR_HBP10_Msk (0x1UL << DSI_VHBPCCR_HBP10_Pos) |
| #define | DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk |
| #define | DSI_VHBPCCR_HBP11_Pos (11U) |
| #define | DSI_VHBPCCR_HBP11_Msk (0x1UL << DSI_VHBPCCR_HBP11_Pos) |
| #define | DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk |
| #define | DSI_VLCCR_HLINE_Pos (0U) |
| #define | DSI_VLCCR_HLINE_Msk (0x7FFFUL << DSI_VLCCR_HLINE_Pos) |
| #define | DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk |
| #define | DSI_VLCCR_HLINE0_Pos (0U) |
| #define | DSI_VLCCR_HLINE0_Msk (0x1UL << DSI_VLCCR_HLINE0_Pos) |
| #define | DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk |
| #define | DSI_VLCCR_HLINE1_Pos (1U) |
| #define | DSI_VLCCR_HLINE1_Msk (0x1UL << DSI_VLCCR_HLINE1_Pos) |
| #define | DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk |
| #define | DSI_VLCCR_HLINE2_Pos (2U) |
| #define | DSI_VLCCR_HLINE2_Msk (0x1UL << DSI_VLCCR_HLINE2_Pos) |
| #define | DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk |
| #define | DSI_VLCCR_HLINE3_Pos (3U) |
| #define | DSI_VLCCR_HLINE3_Msk (0x1UL << DSI_VLCCR_HLINE3_Pos) |
| #define | DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk |
| #define | DSI_VLCCR_HLINE4_Pos (4U) |
| #define | DSI_VLCCR_HLINE4_Msk (0x1UL << DSI_VLCCR_HLINE4_Pos) |
| #define | DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk |
| #define | DSI_VLCCR_HLINE5_Pos (5U) |
| #define | DSI_VLCCR_HLINE5_Msk (0x1UL << DSI_VLCCR_HLINE5_Pos) |
| #define | DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk |
| #define | DSI_VLCCR_HLINE6_Pos (6U) |
| #define | DSI_VLCCR_HLINE6_Msk (0x1UL << DSI_VLCCR_HLINE6_Pos) |
| #define | DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk |
| #define | DSI_VLCCR_HLINE7_Pos (7U) |
| #define | DSI_VLCCR_HLINE7_Msk (0x1UL << DSI_VLCCR_HLINE7_Pos) |
| #define | DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk |
| #define | DSI_VLCCR_HLINE8_Pos (8U) |
| #define | DSI_VLCCR_HLINE8_Msk (0x1UL << DSI_VLCCR_HLINE8_Pos) |
| #define | DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk |
| #define | DSI_VLCCR_HLINE9_Pos (9U) |
| #define | DSI_VLCCR_HLINE9_Msk (0x1UL << DSI_VLCCR_HLINE9_Pos) |
| #define | DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk |
| #define | DSI_VLCCR_HLINE10_Pos (10U) |
| #define | DSI_VLCCR_HLINE10_Msk (0x1UL << DSI_VLCCR_HLINE10_Pos) |
| #define | DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk |
| #define | DSI_VLCCR_HLINE11_Pos (11U) |
| #define | DSI_VLCCR_HLINE11_Msk (0x1UL << DSI_VLCCR_HLINE11_Pos) |
| #define | DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk |
| #define | DSI_VLCCR_HLINE12_Pos (12U) |
| #define | DSI_VLCCR_HLINE12_Msk (0x1UL << DSI_VLCCR_HLINE12_Pos) |
| #define | DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk |
| #define | DSI_VLCCR_HLINE13_Pos (13U) |
| #define | DSI_VLCCR_HLINE13_Msk (0x1UL << DSI_VLCCR_HLINE13_Pos) |
| #define | DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk |
| #define | DSI_VLCCR_HLINE14_Pos (14U) |
| #define | DSI_VLCCR_HLINE14_Msk (0x1UL << DSI_VLCCR_HLINE14_Pos) |
| #define | DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk |
| #define | DSI_VVSACCR_VSA_Pos (0U) |
| #define | DSI_VVSACCR_VSA_Msk (0x3FFUL << DSI_VVSACCR_VSA_Pos) |
| #define | DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk |
| #define | DSI_VVSACCR_VSA0_Pos (0U) |
| #define | DSI_VVSACCR_VSA0_Msk (0x1UL << DSI_VVSACCR_VSA0_Pos) |
| #define | DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk |
| #define | DSI_VVSACCR_VSA1_Pos (1U) |
| #define | DSI_VVSACCR_VSA1_Msk (0x1UL << DSI_VVSACCR_VSA1_Pos) |
| #define | DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk |
| #define | DSI_VVSACCR_VSA2_Pos (2U) |
| #define | DSI_VVSACCR_VSA2_Msk (0x1UL << DSI_VVSACCR_VSA2_Pos) |
| #define | DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk |
| #define | DSI_VVSACCR_VSA3_Pos (3U) |
| #define | DSI_VVSACCR_VSA3_Msk (0x1UL << DSI_VVSACCR_VSA3_Pos) |
| #define | DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk |
| #define | DSI_VVSACCR_VSA4_Pos (4U) |
| #define | DSI_VVSACCR_VSA4_Msk (0x1UL << DSI_VVSACCR_VSA4_Pos) |
| #define | DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk |
| #define | DSI_VVSACCR_VSA5_Pos (5U) |
| #define | DSI_VVSACCR_VSA5_Msk (0x1UL << DSI_VVSACCR_VSA5_Pos) |
| #define | DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk |
| #define | DSI_VVSACCR_VSA6_Pos (6U) |
| #define | DSI_VVSACCR_VSA6_Msk (0x1UL << DSI_VVSACCR_VSA6_Pos) |
| #define | DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk |
| #define | DSI_VVSACCR_VSA7_Pos (7U) |
| #define | DSI_VVSACCR_VSA7_Msk (0x1UL << DSI_VVSACCR_VSA7_Pos) |
| #define | DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk |
| #define | DSI_VVSACCR_VSA8_Pos (8U) |
| #define | DSI_VVSACCR_VSA8_Msk (0x1UL << DSI_VVSACCR_VSA8_Pos) |
| #define | DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk |
| #define | DSI_VVSACCR_VSA9_Pos (9U) |
| #define | DSI_VVSACCR_VSA9_Msk (0x1UL << DSI_VVSACCR_VSA9_Pos) |
| #define | DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk |
| #define | DSI_VVBPCCR_VBP_Pos (0U) |
| #define | DSI_VVBPCCR_VBP_Msk (0x3FFUL << DSI_VVBPCCR_VBP_Pos) |
| #define | DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk |
| #define | DSI_VVBPCCR_VBP0_Pos (0U) |
| #define | DSI_VVBPCCR_VBP0_Msk (0x1UL << DSI_VVBPCCR_VBP0_Pos) |
| #define | DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk |
| #define | DSI_VVBPCCR_VBP1_Pos (1U) |
| #define | DSI_VVBPCCR_VBP1_Msk (0x1UL << DSI_VVBPCCR_VBP1_Pos) |
| #define | DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk |
| #define | DSI_VVBPCCR_VBP2_Pos (2U) |
| #define | DSI_VVBPCCR_VBP2_Msk (0x1UL << DSI_VVBPCCR_VBP2_Pos) |
| #define | DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk |
| #define | DSI_VVBPCCR_VBP3_Pos (3U) |
| #define | DSI_VVBPCCR_VBP3_Msk (0x1UL << DSI_VVBPCCR_VBP3_Pos) |
| #define | DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk |
| #define | DSI_VVBPCCR_VBP4_Pos (4U) |
| #define | DSI_VVBPCCR_VBP4_Msk (0x1UL << DSI_VVBPCCR_VBP4_Pos) |
| #define | DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk |
| #define | DSI_VVBPCCR_VBP5_Pos (5U) |
| #define | DSI_VVBPCCR_VBP5_Msk (0x1UL << DSI_VVBPCCR_VBP5_Pos) |
| #define | DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk |
| #define | DSI_VVBPCCR_VBP6_Pos (6U) |
| #define | DSI_VVBPCCR_VBP6_Msk (0x1UL << DSI_VVBPCCR_VBP6_Pos) |
| #define | DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk |
| #define | DSI_VVBPCCR_VBP7_Pos (7U) |
| #define | DSI_VVBPCCR_VBP7_Msk (0x1UL << DSI_VVBPCCR_VBP7_Pos) |
| #define | DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk |
| #define | DSI_VVBPCCR_VBP8_Pos (8U) |
| #define | DSI_VVBPCCR_VBP8_Msk (0x1UL << DSI_VVBPCCR_VBP8_Pos) |
| #define | DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk |
| #define | DSI_VVBPCCR_VBP9_Pos (9U) |
| #define | DSI_VVBPCCR_VBP9_Msk (0x1UL << DSI_VVBPCCR_VBP9_Pos) |
| #define | DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk |
| #define | DSI_VVFPCCR_VFP_Pos (0U) |
| #define | DSI_VVFPCCR_VFP_Msk (0x3FFUL << DSI_VVFPCCR_VFP_Pos) |
| #define | DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk |
| #define | DSI_VVFPCCR_VFP0_Pos (0U) |
| #define | DSI_VVFPCCR_VFP0_Msk (0x1UL << DSI_VVFPCCR_VFP0_Pos) |
| #define | DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk |
| #define | DSI_VVFPCCR_VFP1_Pos (1U) |
| #define | DSI_VVFPCCR_VFP1_Msk (0x1UL << DSI_VVFPCCR_VFP1_Pos) |
| #define | DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk |
| #define | DSI_VVFPCCR_VFP2_Pos (2U) |
| #define | DSI_VVFPCCR_VFP2_Msk (0x1UL << DSI_VVFPCCR_VFP2_Pos) |
| #define | DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk |
| #define | DSI_VVFPCCR_VFP3_Pos (3U) |
| #define | DSI_VVFPCCR_VFP3_Msk (0x1UL << DSI_VVFPCCR_VFP3_Pos) |
| #define | DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk |
| #define | DSI_VVFPCCR_VFP4_Pos (4U) |
| #define | DSI_VVFPCCR_VFP4_Msk (0x1UL << DSI_VVFPCCR_VFP4_Pos) |
| #define | DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk |
| #define | DSI_VVFPCCR_VFP5_Pos (5U) |
| #define | DSI_VVFPCCR_VFP5_Msk (0x1UL << DSI_VVFPCCR_VFP5_Pos) |
| #define | DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk |
| #define | DSI_VVFPCCR_VFP6_Pos (6U) |
| #define | DSI_VVFPCCR_VFP6_Msk (0x1UL << DSI_VVFPCCR_VFP6_Pos) |
| #define | DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk |
| #define | DSI_VVFPCCR_VFP7_Pos (7U) |
| #define | DSI_VVFPCCR_VFP7_Msk (0x1UL << DSI_VVFPCCR_VFP7_Pos) |
| #define | DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk |
| #define | DSI_VVFPCCR_VFP8_Pos (8U) |
| #define | DSI_VVFPCCR_VFP8_Msk (0x1UL << DSI_VVFPCCR_VFP8_Pos) |
| #define | DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk |
| #define | DSI_VVFPCCR_VFP9_Pos (9U) |
| #define | DSI_VVFPCCR_VFP9_Msk (0x1UL << DSI_VVFPCCR_VFP9_Pos) |
| #define | DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk |
| #define | DSI_VVACCR_VA_Pos (0U) |
| #define | DSI_VVACCR_VA_Msk (0x3FFFUL << DSI_VVACCR_VA_Pos) |
| #define | DSI_VVACCR_VA DSI_VVACCR_VA_Msk |
| #define | DSI_VVACCR_VA0_Pos (0U) |
| #define | DSI_VVACCR_VA0_Msk (0x1UL << DSI_VVACCR_VA0_Pos) |
| #define | DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk |
| #define | DSI_VVACCR_VA1_Pos (1U) |
| #define | DSI_VVACCR_VA1_Msk (0x1UL << DSI_VVACCR_VA1_Pos) |
| #define | DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk |
| #define | DSI_VVACCR_VA2_Pos (2U) |
| #define | DSI_VVACCR_VA2_Msk (0x1UL << DSI_VVACCR_VA2_Pos) |
| #define | DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk |
| #define | DSI_VVACCR_VA3_Pos (3U) |
| #define | DSI_VVACCR_VA3_Msk (0x1UL << DSI_VVACCR_VA3_Pos) |
| #define | DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk |
| #define | DSI_VVACCR_VA4_Pos (4U) |
| #define | DSI_VVACCR_VA4_Msk (0x1UL << DSI_VVACCR_VA4_Pos) |
| #define | DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk |
| #define | DSI_VVACCR_VA5_Pos (5U) |
| #define | DSI_VVACCR_VA5_Msk (0x1UL << DSI_VVACCR_VA5_Pos) |
| #define | DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk |
| #define | DSI_VVACCR_VA6_Pos (6U) |
| #define | DSI_VVACCR_VA6_Msk (0x1UL << DSI_VVACCR_VA6_Pos) |
| #define | DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk |
| #define | DSI_VVACCR_VA7_Pos (7U) |
| #define | DSI_VVACCR_VA7_Msk (0x1UL << DSI_VVACCR_VA7_Pos) |
| #define | DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk |
| #define | DSI_VVACCR_VA8_Pos (8U) |
| #define | DSI_VVACCR_VA8_Msk (0x1UL << DSI_VVACCR_VA8_Pos) |
| #define | DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk |
| #define | DSI_VVACCR_VA9_Pos (9U) |
| #define | DSI_VVACCR_VA9_Msk (0x1UL << DSI_VVACCR_VA9_Pos) |
| #define | DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk |
| #define | DSI_VVACCR_VA10_Pos (10U) |
| #define | DSI_VVACCR_VA10_Msk (0x1UL << DSI_VVACCR_VA10_Pos) |
| #define | DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk |
| #define | DSI_VVACCR_VA11_Pos (11U) |
| #define | DSI_VVACCR_VA11_Msk (0x1UL << DSI_VVACCR_VA11_Pos) |
| #define | DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk |
| #define | DSI_VVACCR_VA12_Pos (12U) |
| #define | DSI_VVACCR_VA12_Msk (0x1UL << DSI_VVACCR_VA12_Pos) |
| #define | DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk |
| #define | DSI_VVACCR_VA13_Pos (13U) |
| #define | DSI_VVACCR_VA13_Msk (0x1UL << DSI_VVACCR_VA13_Pos) |
| #define | DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk |
| #define | DSI_FBSR_VCWFE_Pos (0U) |
| #define | DSI_FBSR_VCWFE_Msk (0x1UL << DSI_FBSR_VCWFE_Pos) |
| #define | DSI_FBSR_VCWFE DSI_FBSR_VCWFE_Msk |
| #define | DSI_FBSR_VCWFF_Pos (1U) |
| #define | DSI_FBSR_VCWFF_Msk (0x1UL << DSI_FBSR_VCWFF_Pos) |
| #define | DSI_FBSR_VCWFF DSI_FBSR_VCWFF_Msk |
| #define | DSI_FBSR_VPWFE_Pos (2U) |
| #define | DSI_FBSR_VPWFE_Msk (0x1UL << DSI_FBSR_VPWFE_Pos) |
| #define | DSI_FBSR_VPWFE DSI_FBSR_VPWFE_Msk |
| #define | DSI_FBSR_VPWFF_Pos (3U) |
| #define | DSI_FBSR_VPWFF_Msk (0x1UL << DSI_FBSR_VPWFF_Pos) |
| #define | DSI_FBSR_VPWFF DSI_FBSR_VPWFF_Msk |
| #define | DSI_FBSR_ACWFE_Pos (4U) |
| #define | DSI_FBSR_ACWFE_Msk (0x1UL << DSI_FBSR_ACWFE_Pos) |
| #define | DSI_FBSR_ACWFE DSI_FBSR_ACWFE_Msk |
| #define | DSI_FBSR_ACWFF_Pos (5U) |
| #define | DSI_FBSR_ACWFF_Msk (0x1UL << DSI_FBSR_ACWFF_Pos) |
| #define | DSI_FBSR_ACWFF DSI_FBSR_ACWFF_Msk |
| #define | DSI_FBSR_APWFE_Pos (6U) |
| #define | DSI_FBSR_APWFE_Msk (0x1UL << DSI_FBSR_APWFE_Pos) |
| #define | DSI_FBSR_APWFE DSI_FBSR_APWFE_Msk |
| #define | DSI_FBSR_APWFF_Pos (7U) |
| #define | DSI_FBSR_APWFF_Msk (0x1UL << DSI_FBSR_APWFF_Pos) |
| #define | DSI_FBSR_APWFF DSI_FBSR_APWFF_Msk |
| #define | DSI_FBSR_VPBE_Pos (16U) |
| #define | DSI_FBSR_VPBE_Msk (0x1UL << DSI_FBSR_VPBE_Pos) |
| #define | DSI_FBSR_VPBE DSI_FBSR_VPBE_Msk |
| #define | DSI_FBSR_VPBF_Pos (17U) |
| #define | DSI_FBSR_VPBF_Msk (0x1UL << DSI_FBSR_VPBF_Pos) |
| #define | DSI_FBSR_VPBF DSI_FBSR_VPBF_Msk |
| #define | DSI_FBSR_ACBE_Pos (20U) |
| #define | DSI_FBSR_ACBE_Msk (0x1UL << DSI_FBSR_ACBE_Pos) |
| #define | DSI_FBSR_ACBE DSI_FBSR_ACBE_Msk |
| #define | DSI_FBSR_ACBF_Pos (21U) |
| #define | DSI_FBSR_ACBF_Msk (0x1UL << DSI_FBSR_ACBF_Pos) |
| #define | DSI_FBSR_ACBF DSI_FBSR_ACBF_Msk |
| #define | DSI_FBSR_APBE_Pos (22U) |
| #define | DSI_FBSR_APBE_Msk (0x1UL << DSI_FBSR_APBE_Pos) |
| #define | DSI_FBSR_APBE DSI_FBSR_APBE_Msk |
| #define | DSI_FBSR_APBF_Pos (23U) |
| #define | DSI_FBSR_APBF_Msk (0x1UL << DSI_FBSR_APBF_Pos) |
| #define | DSI_FBSR_APBF DSI_FBSR_APBF_Msk |
| #define | DSI_WCFGR_DSIM_Pos (0U) |
| #define | DSI_WCFGR_DSIM_Msk (0x1UL << DSI_WCFGR_DSIM_Pos) |
| #define | DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk |
| #define | DSI_WCFGR_COLMUX_Pos (1U) |
| #define | DSI_WCFGR_COLMUX_Msk (0x7UL << DSI_WCFGR_COLMUX_Pos) |
| #define | DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk |
| #define | DSI_WCFGR_COLMUX0_Pos (1U) |
| #define | DSI_WCFGR_COLMUX0_Msk (0x1UL << DSI_WCFGR_COLMUX0_Pos) |
| #define | DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk |
| #define | DSI_WCFGR_COLMUX1_Pos (2U) |
| #define | DSI_WCFGR_COLMUX1_Msk (0x1UL << DSI_WCFGR_COLMUX1_Pos) |
| #define | DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk |
| #define | DSI_WCFGR_COLMUX2_Pos (3U) |
| #define | DSI_WCFGR_COLMUX2_Msk (0x1UL << DSI_WCFGR_COLMUX2_Pos) |
| #define | DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk |
| #define | DSI_WCFGR_TESRC_Pos (4U) |
| #define | DSI_WCFGR_TESRC_Msk (0x1UL << DSI_WCFGR_TESRC_Pos) |
| #define | DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk |
| #define | DSI_WCFGR_TEPOL_Pos (5U) |
| #define | DSI_WCFGR_TEPOL_Msk (0x1UL << DSI_WCFGR_TEPOL_Pos) |
| #define | DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk |
| #define | DSI_WCFGR_AR_Pos (6U) |
| #define | DSI_WCFGR_AR_Msk (0x1UL << DSI_WCFGR_AR_Pos) |
| #define | DSI_WCFGR_AR DSI_WCFGR_AR_Msk |
| #define | DSI_WCFGR_VSPOL_Pos (7U) |
| #define | DSI_WCFGR_VSPOL_Msk (0x1UL << DSI_WCFGR_VSPOL_Pos) |
| #define | DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk |
| #define | DSI_WCR_COLM_Pos (0U) |
| #define | DSI_WCR_COLM_Msk (0x1UL << DSI_WCR_COLM_Pos) |
| #define | DSI_WCR_COLM DSI_WCR_COLM_Msk |
| #define | DSI_WCR_SHTDN_Pos (1U) |
| #define | DSI_WCR_SHTDN_Msk (0x1UL << DSI_WCR_SHTDN_Pos) |
| #define | DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk |
| #define | DSI_WCR_LTDCEN_Pos (2U) |
| #define | DSI_WCR_LTDCEN_Msk (0x1UL << DSI_WCR_LTDCEN_Pos) |
| #define | DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk |
| #define | DSI_WCR_DSIEN_Pos (3U) |
| #define | DSI_WCR_DSIEN_Msk (0x1UL << DSI_WCR_DSIEN_Pos) |
| #define | DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk |
| #define | DSI_WIER_TEIE_Pos (0U) |
| #define | DSI_WIER_TEIE_Msk (0x1UL << DSI_WIER_TEIE_Pos) |
| #define | DSI_WIER_TEIE DSI_WIER_TEIE_Msk |
| #define | DSI_WIER_ERIE_Pos (1U) |
| #define | DSI_WIER_ERIE_Msk (0x1UL << DSI_WIER_ERIE_Pos) |
| #define | DSI_WIER_ERIE DSI_WIER_ERIE_Msk |
| #define | DSI_WIER_PLLLIE_Pos (9U) |
| #define | DSI_WIER_PLLLIE_Msk (0x1UL << DSI_WIER_PLLLIE_Pos) |
| #define | DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk |
| #define | DSI_WIER_PLLUIE_Pos (10U) |
| #define | DSI_WIER_PLLUIE_Msk (0x1UL << DSI_WIER_PLLUIE_Pos) |
| #define | DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk |
| #define | DSI_WISR_TEIF_Pos (0U) |
| #define | DSI_WISR_TEIF_Msk (0x1UL << DSI_WISR_TEIF_Pos) |
| #define | DSI_WISR_TEIF DSI_WISR_TEIF_Msk |
| #define | DSI_WISR_ERIF_Pos (1U) |
| #define | DSI_WISR_ERIF_Msk (0x1UL << DSI_WISR_ERIF_Pos) |
| #define | DSI_WISR_ERIF DSI_WISR_ERIF_Msk |
| #define | DSI_WISR_BUSY_Pos (2U) |
| #define | DSI_WISR_BUSY_Msk (0x1UL << DSI_WISR_BUSY_Pos) |
| #define | DSI_WISR_BUSY DSI_WISR_BUSY_Msk |
| #define | DSI_WISR_PLLLS_Pos (8U) |
| #define | DSI_WISR_PLLLS_Msk (0x1UL << DSI_WISR_PLLLS_Pos) |
| #define | DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk |
| #define | DSI_WISR_PLLLIF_Pos (9U) |
| #define | DSI_WISR_PLLLIF_Msk (0x1UL << DSI_WISR_PLLLIF_Pos) |
| #define | DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk |
| #define | DSI_WISR_PLLUIF_Pos (10U) |
| #define | DSI_WISR_PLLUIF_Msk (0x1UL << DSI_WISR_PLLUIF_Pos) |
| #define | DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk |
| #define | DSI_WIFCR_CTEIF_Pos (0U) |
| #define | DSI_WIFCR_CTEIF_Msk (0x1UL << DSI_WIFCR_CTEIF_Pos) |
| #define | DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk |
| #define | DSI_WIFCR_CERIF_Pos (1U) |
| #define | DSI_WIFCR_CERIF_Msk (0x1UL << DSI_WIFCR_CERIF_Pos) |
| #define | DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk |
| #define | DSI_WIFCR_CPLLLIF_Pos (9U) |
| #define | DSI_WIFCR_CPLLLIF_Msk (0x1UL << DSI_WIFCR_CPLLLIF_Pos) |
| #define | DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk |
| #define | DSI_WIFCR_CPLLUIF_Pos (10U) |
| #define | DSI_WIFCR_CPLLUIF_Msk (0x1UL << DSI_WIFCR_CPLLUIF_Pos) |
| #define | DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk |
| #define | DSI_WPCR0_SWCL_Pos (6U) |
| #define | DSI_WPCR0_SWCL_Msk (0x1UL << DSI_WPCR0_SWCL_Pos) |
| #define | DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk |
| #define | DSI_WPCR0_SWDL0_Pos (7U) |
| #define | DSI_WPCR0_SWDL0_Msk (0x1UL << DSI_WPCR0_SWDL0_Pos) |
| #define | DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk |
| #define | DSI_WPCR0_SWDL1_Pos (8U) |
| #define | DSI_WPCR0_SWDL1_Msk (0x1UL << DSI_WPCR0_SWDL1_Pos) |
| #define | DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk |
| #define | DSI_WPCR0_FTXSMCL_Pos (12U) |
| #define | DSI_WPCR0_FTXSMCL_Msk (0x1UL << DSI_WPCR0_FTXSMCL_Pos) |
| #define | DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk |
| #define | DSI_WPCR0_FTXSMDL_Pos (13U) |
| #define | DSI_WPCR0_FTXSMDL_Msk (0x1UL << DSI_WPCR0_FTXSMDL_Pos) |
| #define | DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk |
| #define | DSI_WRPCR_PLLEN_Pos (0U) |
| #define | DSI_WRPCR_PLLEN_Msk (0x1UL << DSI_WRPCR_PLLEN_Pos) |
| #define | DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk |
| #define | DSI_WRPCR_PLL_NDIV_Pos (2U) |
| #define | DSI_WRPCR_PLL_NDIV_Msk (0x1FFUL << DSI_WRPCR_PLL_NDIV_Pos) |
| #define | DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk |
| #define | DSI_WRPCR_PLL_NDIV0_Pos (2U) |
| #define | DSI_WRPCR_PLL_NDIV0_Msk (0x1UL << DSI_WRPCR_PLL_NDIV0_Pos) |
| #define | DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk |
| #define | DSI_WRPCR_PLL_NDIV1_Pos (3U) |
| #define | DSI_WRPCR_PLL_NDIV1_Msk (0x1UL << DSI_WRPCR_PLL_NDIV1_Pos) |
| #define | DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk |
| #define | DSI_WRPCR_PLL_NDIV2_Pos (4U) |
| #define | DSI_WRPCR_PLL_NDIV2_Msk (0x1UL << DSI_WRPCR_PLL_NDIV2_Pos) |
| #define | DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk |
| #define | DSI_WRPCR_PLL_NDIV3_Pos (5U) |
| #define | DSI_WRPCR_PLL_NDIV3_Msk (0x1UL << DSI_WRPCR_PLL_NDIV3_Pos) |
| #define | DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk |
| #define | DSI_WRPCR_PLL_NDIV4_Pos (6U) |
| #define | DSI_WRPCR_PLL_NDIV4_Msk (0x1UL << DSI_WRPCR_PLL_NDIV4_Pos) |
| #define | DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk |
| #define | DSI_WRPCR_PLL_NDIV5_Pos (7U) |
| #define | DSI_WRPCR_PLL_NDIV5_Msk (0x1UL << DSI_WRPCR_PLL_NDIV5_Pos) |
| #define | DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk |
| #define | DSI_WRPCR_PLL_NDIV6_Pos (8U) |
| #define | DSI_WRPCR_PLL_NDIV6_Msk (0x1UL << DSI_WRPCR_PLL_NDIV6_Pos) |
| #define | DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk |
| #define | DSI_WRPCR_PLL_NDIV7_Pos (9U) |
| #define | DSI_WRPCR_PLL_NDIV7_Msk (0x1UL << DSI_WRPCR_PLL_NDIV7_Pos) |
| #define | DSI_WRPCR_PLL_NDIV7 DSI_WRPCR_PLL_NDIV7_Msk |
| #define | DSI_WRPCR_PLL_NDIV8_Pos (10U) |
| #define | DSI_WRPCR_PLL_NDIV8_Msk (0x1UL << DSI_WRPCR_PLL_NDIV8_Pos) |
| #define | DSI_WRPCR_PLL_NDIV8 DSI_WRPCR_PLL_NDIV8_Msk |
| #define | DSI_WRPCR_PLL_IDF_Pos (11U) |
| #define | DSI_WRPCR_PLL_IDF_Msk (0x1FFUL << DSI_WRPCR_PLL_IDF_Pos) |
| #define | DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk |
| #define | DSI_WRPCR_PLL_IDF0_Pos (11U) |
| #define | DSI_WRPCR_PLL_IDF0_Msk (0x1UL << DSI_WRPCR_PLL_IDF0_Pos) |
| #define | DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk |
| #define | DSI_WRPCR_PLL_IDF1_Pos (12U) |
| #define | DSI_WRPCR_PLL_IDF1_Msk (0x1UL << DSI_WRPCR_PLL_IDF1_Pos) |
| #define | DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk |
| #define | DSI_WRPCR_PLL_IDF2_Pos (13U) |
| #define | DSI_WRPCR_PLL_IDF2_Msk (0x1UL << DSI_WRPCR_PLL_IDF2_Pos) |
| #define | DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk |
| #define | DSI_WRPCR_PLL_IDF3_Pos (14U) |
| #define | DSI_WRPCR_PLL_IDF3_Msk (0x1UL << DSI_WRPCR_PLL_IDF3_Pos) |
| #define | DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk |
| #define | DSI_WRPCR_PLL_IDF4_Pos (15U) |
| #define | DSI_WRPCR_PLL_IDF4_Msk (0x1UL << DSI_WRPCR_PLL_IDF4_Pos) |
| #define | DSI_WRPCR_PLL_IDF4 DSI_WRPCR_PLL_IDF4_Msk |
| #define | DSI_WRPCR_PLL_IDF5_Pos (16U) |
| #define | DSI_WRPCR_PLL_IDF5_Msk (0x1UL << DSI_WRPCR_PLL_IDF5_Pos) |
| #define | DSI_WRPCR_PLL_IDF5 DSI_WRPCR_PLL_IDF5_Msk |
| #define | DSI_WRPCR_PLL_IDF6_Pos (17U) |
| #define | DSI_WRPCR_PLL_IDF6_Msk (0x1UL << DSI_WRPCR_PLL_IDF6_Pos) |
| #define | DSI_WRPCR_PLL_IDF6 DSI_WRPCR_PLL_IDF6_Msk |
| #define | DSI_WRPCR_PLL_IDF7_Pos (18U) |
| #define | DSI_WRPCR_PLL_IDF7_Msk (0x1UL << DSI_WRPCR_PLL_IDF7_Pos) |
| #define | DSI_WRPCR_PLL_IDF7 DSI_WRPCR_PLL_IDF7_Msk |
| #define | DSI_WRPCR_PLL_IDF8_Pos (19U) |
| #define | DSI_WRPCR_PLL_IDF8_Msk (0x1UL << DSI_WRPCR_PLL_IDF8_Pos) |
| #define | DSI_WRPCR_PLL_IDF8 DSI_WRPCR_PLL_IDF8_Msk |
| #define | DSI_WRPCR_PLL_ODF_Pos (20U) |
| #define | DSI_WRPCR_PLL_ODF_Msk (0x1FFUL << DSI_WRPCR_PLL_ODF_Pos) |
| #define | DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk |
| #define | DSI_WRPCR_PLL_ODF0_Pos (20U) |
| #define | DSI_WRPCR_PLL_ODF0_Msk (0x1UL << DSI_WRPCR_PLL_ODF0_Pos) |
| #define | DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk |
| #define | DSI_WRPCR_PLL_ODF1_Pos (21U) |
| #define | DSI_WRPCR_PLL_ODF1_Msk (0x1UL << DSI_WRPCR_PLL_ODF1_Pos) |
| #define | DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk |
| #define | DSI_WRPCR_PLL_ODF2_Pos (22U) |
| #define | DSI_WRPCR_PLL_ODF2_Msk (0x1UL << DSI_WRPCR_PLL_ODF2_Pos) |
| #define | DSI_WRPCR_PLL_ODF2 DSI_WRPCR_PLL_ODF2_Msk |
| #define | DSI_WRPCR_PLL_ODF3_Pos (23U) |
| #define | DSI_WRPCR_PLL_ODF3_Msk (0x1UL << DSI_WRPCR_PLL_ODF3_Pos) |
| #define | DSI_WRPCR_PLL_ODF3 DSI_WRPCR_PLL_ODF3_Msk |
| #define | DSI_WRPCR_PLL_ODF4_Pos (24U) |
| #define | DSI_WRPCR_PLL_ODF4_Msk (0x1UL << DSI_WRPCR_PLL_ODF4_Pos) |
| #define | DSI_WRPCR_PLL_ODF4 DSI_WRPCR_PLL_ODF4_Msk |
| #define | DSI_WRPCR_PLL_ODF5_Pos (25U) |
| #define | DSI_WRPCR_PLL_ODF5_Msk (0x1UL << DSI_WRPCR_PLL_ODF5_Pos) |
| #define | DSI_WRPCR_PLL_ODF5 DSI_WRPCR_PLL_ODF5_Msk |
| #define | DSI_WRPCR_PLL_ODF6_Pos (26U) |
| #define | DSI_WRPCR_PLL_ODF6_Msk (0x1UL << DSI_WRPCR_PLL_ODF6_Pos) |
| #define | DSI_WRPCR_PLL_ODF6 DSI_WRPCR_PLL_ODF6_Msk |
| #define | DSI_WRPCR_PLL_ODF7_Pos (27U) |
| #define | DSI_WRPCR_PLL_ODF7_Msk (0x1UL << DSI_WRPCR_PLL_ODF7_Pos) |
| #define | DSI_WRPCR_PLL_ODF7 DSI_WRPCR_PLL_ODF7_Msk |
| #define | DSI_WRPCR_PLL_ODF8_Pos (28U) |
| #define | DSI_WRPCR_PLL_ODF8_Msk (0x1UL << DSI_WRPCR_PLL_ODF8_Pos) |
| #define | DSI_WRPCR_PLL_ODF8 DSI_WRPCR_PLL_ODF8_Msk |
| #define | DSI_WRPCR_BC_Pos (29U) |
| #define | DSI_WRPCR_BC_Msk (0x1UL << DSI_WRPCR_BC_Pos) |
| #define | DSI_WRPCR_BC DSI_WRPCR_BC_Msk |
| #define | DSI_WPTR_CP_Pos (8U) |
| #define | DSI_WPTR_CP_Msk (0xFUL << DSI_WPTR_CP_Pos) |
| #define | DSI_WPTR_CP DSI_WPTR_CP_Msk |
| #define | DSI_WPTR_CP0_Pos (8U) |
| #define | DSI_WPTR_CP0_Msk (0x1UL << DSI_WPTR_CP0_Pos) |
| #define | DSI_WPTR_CP0 DSI_WPTR_CP0_Msk |
| #define | DSI_WPTR_CP1_Pos (9U) |
| #define | DSI_WPTR_CP1_Msk (0x1UL << DSI_WPTR_CP1_Pos) |
| #define | DSI_WPTR_CP1 DSI_WPTR_CP1_Msk |
| #define | DSI_WPTR_CP2_Pos (10U) |
| #define | DSI_WPTR_CP2_Msk (0x1UL << DSI_WPTR_CP2_Pos) |
| #define | DSI_WPTR_CP2 DSI_WPTR_CP2_Msk |
| #define | DSI_WPTR_CP3_Pos (11U) |
| #define | DSI_WPTR_CP3_Msk (0x1UL << DSI_WPTR_CP3_Pos) |
| #define | DSI_WPTR_CP3 DSI_WPTR_CP3_Msk |
| #define | DSI_WPTR_LPF_Pos (12U) |
| #define | DSI_WPTR_LPF_Msk (0xFUL << DSI_WPTR_LPF_Pos) |
| #define | DSI_WPTR_LPF DSI_WPTR_LPF_Msk |
| #define | DSI_WPTR_LPF0_Pos (12U) |
| #define | DSI_WPTR_LPF0_Msk (0x1UL << DSI_WPTR_LPF0_Pos) |
| #define | DSI_WPTR_LPF0 DSI_WPTR_LPF0_Msk |
| #define | DSI_WPTR_LPF1_Pos (13U) |
| #define | DSI_WPTR_LPF1_Msk (0x1UL << DSI_WPTR_LPF1_Pos) |
| #define | DSI_WPTR_LPF1 DSI_WPTR_LPF1_Msk |
| #define | DSI_WPTR_LPF2_Pos (14U) |
| #define | DSI_WPTR_LPF2_Msk (0x1UL << DSI_WPTR_LPF2_Pos) |
| #define | DSI_WPTR_LPF2 DSI_WPTR_LPF2_Msk |
| #define | DSI_WPTR_LPF3_Pos (15U) |
| #define | DSI_WPTR_LPF3_Msk (0x1UL << DSI_WPTR_LPF3_Pos) |
| #define | DSI_WPTR_LPF3 DSI_WPTR_LPF3_Msk |
| #define | DSI_BCFGR_PWRUP_Pos (6U) |
| #define | DSI_BCFGR_PWRUP_Msk (0x1UL << DSI_BCFGR_PWRUP_Pos) |
| #define | DSI_BCFGR_PWRUP DSI_BCFGR_PWRUP_Msk |
| #define | DSI_DPCBCR_Pos (3U) |
| #define | DSI_DPCBCR_Msk (0x1FUL << DSI_DPCBCR_Pos) |
| #define | DSI_DPCBCR DSI_DPCBCR_Msk |
| #define | DSI_DPCBCR0_Pos (3U) |
| #define | DSI_DPCBCR0_Msk (0x1UL << DSI_DPCBCR0_Pos) |
| #define | DSI_DPCBCR0 DSI_DPCBCR0_Msk |
| #define | DSI_DPCBCR1_Pos (4U) |
| #define | DSI_DPCBCR1_Msk (0x1UL << DSI_DPCBCR1_Pos) |
| #define | DSI_DPCBCR1 DSI_DPCBCR1_Msk |
| #define | DSI_DPCBCR2_Pos (5U) |
| #define | DSI_DPCBCR2_Msk (0x1UL << DSI_DPCBCR2_Pos) |
| #define | DSI_DPCBCR2 DSI_DPCBCR2_Msk |
| #define | DSI_DPCBCR3_Pos (6U) |
| #define | DSI_DPCBCR3_Msk (0x1UL << DSI_DPCBCR3_Pos) |
| #define | DSI_DPCBCR3 DSI_DPCBCR3_Msk |
| #define | DSI_DPCBCR4_Pos (7U) |
| #define | DSI_DPCBCR4_Msk (0x1UL << DSI_DPCBCR4_Pos) |
| #define | DSI_DPCBCR4 DSI_DPCBCR4_Msk |
| #define | DSI_DPCSRCR_Pos (0U) |
| #define | DSI_DPCSRCR_Msk (0xFFUL << DSI_DPCSRCR_Pos) |
| #define | DSI_DPCSRCR DSI_DPCSRCR_Msk |
| #define | DSI_DPCSRCR0_Pos (0U) |
| #define | DSI_DPCSRCR0_Msk (0x1UL << DSI_DPCSRCR0_Pos) |
| #define | DSI_DPCSRCR0 DSI_DPCSRCR0_Msk |
| #define | DSI_DPCSRCR1_Pos (1U) |
| #define | DSI_DPCSRCR1_Msk (0x1UL << DSI_DPCSRCR1_Pos) |
| #define | DSI_DPCSRCR1 DSI_DPCSRCR1_Msk |
| #define | DSI_DPCSRCR2_Pos (2U) |
| #define | DSI_DPCSRCR2_Msk (0x1UL << DSI_DPCSRCR2_Pos) |
| #define | DSI_DPCSRCR2 DSI_DPCSRCR2_Msk |
| #define | DSI_DPCSRCR3_Pos (3U) |
| #define | DSI_DPCSRCR3_Msk (0x1UL << DSI_DPCSRCR3_Pos) |
| #define | DSI_DPCSRCR3 DSI_DPCSRCR3_Msk |
| #define | DSI_DPCSRCR4_Pos (4U) |
| #define | DSI_DPCSRCR4_Msk (0x1UL << DSI_DPCSRCR4_Pos) |
| #define | DSI_DPCSRCR4 DSI_DPCSRCR4_Msk |
| #define | DSI_DPCSRCR5_Pos (5U) |
| #define | DSI_DPCSRCR5_Msk (0x1UL << DSI_DPCSRCR5_Pos) |
| #define | DSI_DPCSRCR5 DSI_DPCSRCR5_Msk |
| #define | DSI_DPCSRCR6_Pos (6U) |
| #define | DSI_DPCSRCR6_Msk (0x1UL << DSI_DPCSRCR6_Pos) |
| #define | DSI_DPCSRCR6 DSI_DPCSRCR6_Msk |
| #define | DSI_DPCSRCR7_Pos (7U) |
| #define | DSI_DPCSRCR7_Msk (0x1UL << DSI_DPCSRCR7_Pos) |
| #define | DSI_DPCSRCR7 DSI_DPCSRCR7_Msk |
| #define | DSI_DPDL0HSOCR_Pos (4U) |
| #define | DSI_DPDL0HSOCR_Msk (0xFUL << DSI_DPDL0HSOCR_Pos) |
| #define | DSI_DPDL0HSOCR DSI_DPDL0HSOCR_Msk |
| #define | DSI_DPDL0HSOCR_HSPRPO0_Pos (4U) |
| #define | DSI_DPDL0HSOCR_HSPRPO0_Msk (0x1UL << DSI_DPDL0HSOCR_HSPRPO0_Pos) |
| #define | DSI_DPDL0HSOCR_HSPRPO0 DSI_DPDL0HSOCR_HSPRPO0_Msk |
| #define | DSI_DPDL0HSOCR_HSPRPO1_Pos (5U) |
| #define | DSI_DPDL0HSOCR_HSPRPO1_Msk (0x1UL << DSI_DPDL0HSOCR_HSPRPO1_Pos) |
| #define | DSI_DPDL0HSOCR_HSPRPO1 DSI_DPDL0HSOCR_HSPRPO1_Msk |
| #define | DSI_DPDL0HSOCR_HSPRPO2_Pos (6U) |
| #define | DSI_DPDL0HSOCR_HSPRPO2_Msk (0x1UL << DSI_DPDL0HSOCR_HSPRPO2_Pos) |
| #define | DSI_DPDL0HSOCR_HSPRPO2 DSI_DPDL0HSOCR_HSPRPO2_Msk |
| #define | DSI_DPDL0HSOCR_HSPRPO3_Pos (7U) |
| #define | DSI_DPDL0HSOCR_HSPRPO3_Msk (0x1UL << DSI_DPDL0HSOCR_HSPRPO3_Pos) |
| #define | DSI_DPDL0HSOCR_HSPRPO3 DSI_DPDL0HSOCR_HSPRPO3_Msk |
| #define | DSI_DPDL0LPXOCR_Pos (0U) |
| #define | DSI_DPDL0LPXOCR_Msk (0xFUL << DSI_DPDL0LPXOCR_Pos) |
| #define | DSI_DPDL0LPXOCR DSI_DPDL0LPXOCR_Msk |
| #define | DSI_DPDL0LPXOCR_LPXO0_Pos (0U) |
| #define | DSI_DPDL0LPXOCR_LPXO0_Msk (0x1UL << DSI_DPDL0LPXOCR_LPXO0_Pos) |
| #define | DSI_DPDL0LPXOCR_LPXO0 DSI_DPDL0LPXOCR_LPXO0_Msk |
| #define | DSI_DPDL0LPXOCR_LPXO1_Pos (1U) |
| #define | DSI_DPDL0LPXOCR_LPXO1_Msk (0x1UL << DSI_DPDL0LPXOCR_LPXO1_Pos) |
| #define | DSI_DPDL0LPXOCR_LPXO1 DSI_DPDL0LPXOCR_LPXO1_Msk |
| #define | DSI_DPDL0LPXOCR_LPXO2_Pos (2U) |
| #define | DSI_DPDL0LPXOCR_LPXO2_Msk (0x1UL << DSI_DPDL0LPXOCR_LPXO2_Pos) |
| #define | DSI_DPDL0LPXOCR_LPXO2 DSI_DPDL0LPXOCR_LPXO2_Msk |
| #define | DSI_DPDL0LPXOCR_LPXO3_Pos (3U) |
| #define | DSI_DPDL0LPXOCR_LPXO3_Msk (0x1UL << DSI_DPDL0LPXOCR_LPXO3_Pos) |
| #define | DSI_DPDL0LPXOCR_LPXO3 DSI_DPDL0LPXOCR_LPXO3_Msk |
| #define | DSI_DPDL0BCR_Pos (0U) |
| #define | DSI_DPDL0BCR_Msk (0x1FUL << DSI_DPDL0BCR_Pos) |
| #define | DSI_DPDL0BCR DSI_DPDL0BCR_Msk |
| #define | DSI_DPDL0BCR0_Pos (0U) |
| #define | DSI_DPDL0BCR0_Msk (0x1UL << DSI_DPDL0BCR0_Pos) |
| #define | DSI_DPDL0BCR0 DSI_DPDL0BCR0_Msk |
| #define | DSI_DPDL0BCR1_Pos (1U) |
| #define | DSI_DPDL0BCR1_Msk (0x1UL << DSI_DPDL0BCR1_Pos) |
| #define | DSI_DPDL0BCR1 DSI_DPDL0BCR1_Msk |
| #define | DSI_DPDL0BCR2_Pos (2U) |
| #define | DSI_DPDL0BCR2_Msk (0x1UL << DSI_DPDL0BCR2_Pos) |
| #define | DSI_DPDL0BCR2 DSI_DPDL0BCR2_Msk |
| #define | DSI_DPDL0BCR3_Pos (3U) |
| #define | DSI_DPDL0BCR3_Msk (0x1UL << DSI_DPDL0BCR3_Pos) |
| #define | DSI_DPDL0BCR3 DSI_DPDL0BCR3_Msk |
| #define | DSI_DPDL0BCR4_Pos (4U) |
| #define | DSI_DPDL0BCR4_Msk (0x1UL << DSI_DPDL0BCR4_Pos) |
| #define | DSI_DPDL0BCR4 DSI_DPDL0BCR4_Msk |
| #define | DSI_DPDL0SRCR_Pos (0U) |
| #define | DSI_DPDL0SRCR_Msk (0xFFUL << DSI_DPDL0SRCR_Pos) |
| #define | DSI_DPDL0SRCR DSI_DPDL0SRCR_Msk |
| #define | DSI_DPDL0SRCR0_Pos (0U) |
| #define | DSI_DPDL0SRCR0_Msk (0x1UL << DSI_DPDL0SRCR0_Pos) |
| #define | DSI_DPDL0SRCR0 DSI_DPDL0SRCR0_Msk |
| #define | DSI_DPDL0SRCR1_Pos (1U) |
| #define | DSI_DPDL0SRCR1_Msk (0x1UL << DSI_DPDL0SRCR1_Pos) |
| #define | DSI_DPDL0SRCR1 DSI_DPDL0SRCR1_Msk |
| #define | DSI_DPDL0SRCR2_Pos (2U) |
| #define | DSI_DPDL0SRCR2_Msk (0x1UL << DSI_DPDL0SRCR2_Pos) |
| #define | DSI_DPDL0SRCR2 DSI_DPDL0SRCR2_Msk |
| #define | DSI_DPDL0SRCR3_Pos (3U) |
| #define | DSI_DPDL0SRCR3_Msk (0x1UL << DSI_DPDL0SRCR3_Pos) |
| #define | DSI_DPDL0SRCR3 DSI_DPDL0SRCR3_Msk |
| #define | DSI_DPDL0SRCR4_Pos (4U) |
| #define | DSI_DPDL0SRCR4_Msk (0x1UL << DSI_DPDL0SRCR4_Pos) |
| #define | DSI_DPDL0SRCR4 DSI_DPDL0SRCR4_Msk |
| #define | DSI_DPDL0SRCR5_Pos (5U) |
| #define | DSI_DPDL0SRCR5_Msk (0x1UL << DSI_DPDL0SRCR5_Pos) |
| #define | DSI_DPDL0SRCR5 DSI_DPDL0SRCR5_Msk |
| #define | DSI_DPDL0SRCR6_Pos (6U) |
| #define | DSI_DPDL0SRCR6_Msk (0x1UL << DSI_DPDL0SRCR6_Pos) |
| #define | DSI_DPDL0SRCR6 DSI_DPDL0SRCR6_Msk |
| #define | DSI_DPDL0SRCR7_Pos (7U) |
| #define | DSI_DPDL0SRCR7_Msk (0x1UL << DSI_DPDL0SRCR7_Pos) |
| #define | DSI_DPDL0SRCR7 DSI_DPDL0SRCR7_Msk |
| #define | DSI_DPDL1HSOCR_Pos (4U) |
| #define | DSI_DPDL1HSOCR_Msk (0xFUL << DSI_DPDL1HSOCR_Pos) |
| #define | DSI_DPDL1HSOCR DSI_DPDL1HSOCR_Msk |
| #define | DSI_DPDL1HSOCR_HSPRPO00_Pos (4U) |
| #define | DSI_DPDL1HSOCR_HSPRPO00_Msk (0x1UL << DSI_DPDL1HSOCR_HSPRPO00_Pos) |
| #define | DSI_DPDL1HSOCR_HSPRPO00 DSI_DPDL1HSOCR_HSPRPO00_Msk |
| #define | DSI_DPDL1HSOCR_HSPRPO01_Pos (5U) |
| #define | DSI_DPDL1HSOCR_HSPRPO01_Msk (0x1UL << DSI_DPDL1HSOCR_HSPRPO01_Pos) |
| #define | DSI_DPDL1HSOCR_HSPRPO01 DSI_DPDL1HSOCR_HSPRPO01_Msk |
| #define | DSI_DPDL1HSOCR_HSPRPO02_Pos (6U) |
| #define | DSI_DPDL1HSOCR_HSPRPO02_Msk (0x1UL << DSI_DPDL1HSOCR_HSPRPO02_Pos) |
| #define | DSI_DPDL1HSOCR_HSPRPO02 DSI_DPDL1HSOCR_HSPRPO02_Msk |
| #define | DSI_DPDL1HSOCR_HSPRPO03_Pos (7U) |
| #define | DSI_DPDL1HSOCR_HSPRPO03_Msk (0x1UL << DSI_DPDL1HSOCR_HSPRPO03_Pos) |
| #define | DSI_DPDL1HSOCR_HSPRPO03 DSI_DPDL1HSOCR_HSPRPO03_Msk |
| #define | DSI_DPDL1LPXOCR_Pos (0U) |
| #define | DSI_DPDL1LPXOCR_Msk (0xFUL << DSI_DPDL1LPXOCR_Pos) |
| #define | DSI_DPDL1LPXOCR DSI_DPDL1LPXOCR_Msk |
| #define | DSI_DPDL1LPXOCR_LPXO0_Pos (0U) |
| #define | DSI_DPDL1LPXOCR_LPXO0_Msk (0x1UL << DSI_DPDL1LPXOCR_LPXO0_Pos) |
| #define | DSI_DPDL1LPXOCR_LPXO0 DSI_DPDL1LPXOCR_LPXO0_Msk |
| #define | DSI_DPDL1LPXOCR_LPXO1_Pos (1U) |
| #define | DSI_DPDL1LPXOCR_LPXO1_Msk (0x1UL << DSI_DPDL1LPXOCR_LPXO1_Pos) |
| #define | DSI_DPDL1LPXOCR_LPXO1 DSI_DPDL1LPXOCR_LPXO1_Msk |
| #define | DSI_DPDL1LPXOCR_LPXO2_Pos (2U) |
| #define | DSI_DPDL1LPXOCR_LPXO2_Msk (0x1UL << DSI_DPDL1LPXOCR_LPXO2_Pos) |
| #define | DSI_DPDL1LPXOCR_LPXO2 DSI_DPDL1LPXOCR_LPXO2_Msk |
| #define | DSI_DPDL1LPXOCR_LPXO3_Pos (3U) |
| #define | DSI_DPDL1LPXOCR_LPXO3_Msk (0x1UL << DSI_DPDL1LPXOCR_LPXO3_Pos) |
| #define | DSI_DPDL1LPXOCR_LPXO3 DSI_DPDL1LPXOCR_LPXO3_Msk |
| #define | DSI_DPDL1BCR_Pos (0U) |
| #define | DSI_DPDL1BCR_Msk (0x1FUL << DSI_DPDL1BCR_Pos) |
| #define | DSI_DPDL1BCR DSI_DPDL1BCR_Msk |
| #define | DSI_DPDL1BCR0_Pos (0U) |
| #define | DSI_DPDL1BCR0_Msk (0x1UL << DSI_DPDL1BCR0_Pos) |
| #define | DSI_DPDL1BCR0 DSI_DPDL1BCR0_Msk |
| #define | DSI_DPDL1BCR1_Pos (1U) |
| #define | DSI_DPDL1BCR1_Msk (0x1UL << DSI_DPDL1BCR1_Pos) |
| #define | DSI_DPDL1BCR1 DSI_DPDL1BCR1_Msk |
| #define | DSI_DPDL1BCR2_Pos (2U) |
| #define | DSI_DPDL1BCR2_Msk (0x1UL << DSI_DPDL1BCR2_Pos) |
| #define | DSI_DPDL1BCR2 DSI_DPDL1BCR2_Msk |
| #define | DSI_DPDL1BCR3_Pos (3U) |
| #define | DSI_DPDL1BCR3_Msk (0x1UL << DSI_DPDL1BCR3_Pos) |
| #define | DSI_DPDL1BCR3 DSI_DPDL1BCR3_Msk |
| #define | DSI_DPDL1BCR4_Pos (4U) |
| #define | DSI_DPDL1BCR4_Msk (0x1UL << DSI_DPDL1BCR4_Pos) |
| #define | DSI_DPDL1BCR4 DSI_DPDL1BCR4_Msk |
| #define | DSI_DPDL1SRCR_Pos (0U) |
| #define | DSI_DPDL1SRCR_Msk (0xFFUL << DSI_DPDL1SRCR_Pos) |
| #define | DSI_DPDL1SRCR DSI_DPDL1SRCR_Msk |
| #define | DSI_DPDL1SRCR0_Pos (0U) |
| #define | DSI_DPDL1SRCR0_Msk (0x1UL << DSI_DPDL1SRCR0_Pos) |
| #define | DSI_DPDL1SRCR0 DSI_DPDL1SRCR0_Msk |
| #define | DSI_DPDL1SRCR1_Pos (1U) |
| #define | DSI_DPDL1SRCR1_Msk (0x1UL << DSI_DPDL1SRCR1_Pos) |
| #define | DSI_DPDL1SRCR1 DSI_DPDL1SRCR1_Msk |
| #define | DSI_DPDL1SRCR2_Pos (2U) |
| #define | DSI_DPDL1SRCR2_Msk (0x1UL << DSI_DPDL1SRCR2_Pos) |
| #define | DSI_DPDL1SRCR2 DSI_DPDL1SRCR2_Msk |
| #define | DSI_DPDL1SRCR3_Pos (3U) |
| #define | DSI_DPDL1SRCR3_Msk (0x1UL << DSI_DPDL1SRCR3_Pos) |
| #define | DSI_DPDL1SRCR3 DSI_DPDL1SRCR3_Msk |
| #define | DSI_DPDL1SRCR4_Pos (4U) |
| #define | DSI_DPDL1SRCR4_Msk (0x1UL << DSI_DPDL1SRCR4_Pos) |
| #define | DSI_DPDL1SRCR4 DSI_DPDL1SRCR4_Msk |
| #define | DSI_DPDL1SRCR5_Pos (5U) |
| #define | DSI_DPDL1SRCR5_Msk (0x1UL << DSI_DPDL1SRCR5_Pos) |
| #define | DSI_DPDL1SRCR5 DSI_DPDL1SRCR5_Msk |
| #define | DSI_DPDL1SRCR6_Pos (6U) |
| #define | DSI_DPDL1SRCR6_Msk (0x1UL << DSI_DPDL1SRCR6_Pos) |
| #define | DSI_DPDL1SRCR6 DSI_DPDL1SRCR6_Msk |
| #define | DSI_DPDL1SRCR7_Pos (7U) |
| #define | DSI_DPDL1SRCR7_Msk (0x1UL << DSI_DPDL1SRCR7_Pos) |
| #define | DSI_DPDL1SRCR7 DSI_DPDL1SRCR7_Msk |
| #define | EXTI_RTSR1_RT0_Pos (0U) |
| #define | EXTI_RTSR1_RT0_Msk (0x1UL << EXTI_RTSR1_RT0_Pos) |
| #define | EXTI_RTSR1_RT0 EXTI_RTSR1_RT0_Msk |
| #define | EXTI_RTSR1_RT1_Pos (1U) |
| #define | EXTI_RTSR1_RT1_Msk (0x1UL << EXTI_RTSR1_RT1_Pos) |
| #define | EXTI_RTSR1_RT1 EXTI_RTSR1_RT1_Msk |
| #define | EXTI_RTSR1_RT2_Pos (2U) |
| #define | EXTI_RTSR1_RT2_Msk (0x1UL << EXTI_RTSR1_RT2_Pos) |
| #define | EXTI_RTSR1_RT2 EXTI_RTSR1_RT2_Msk |
| #define | EXTI_RTSR1_RT3_Pos (3U) |
| #define | EXTI_RTSR1_RT3_Msk (0x1UL << EXTI_RTSR1_RT3_Pos) |
| #define | EXTI_RTSR1_RT3 EXTI_RTSR1_RT3_Msk |
| #define | EXTI_RTSR1_RT4_Pos (4U) |
| #define | EXTI_RTSR1_RT4_Msk (0x1UL << EXTI_RTSR1_RT4_Pos) |
| #define | EXTI_RTSR1_RT4 EXTI_RTSR1_RT4_Msk |
| #define | EXTI_RTSR1_RT5_Pos (5U) |
| #define | EXTI_RTSR1_RT5_Msk (0x1UL << EXTI_RTSR1_RT5_Pos) |
| #define | EXTI_RTSR1_RT5 EXTI_RTSR1_RT5_Msk |
| #define | EXTI_RTSR1_RT6_Pos (6U) |
| #define | EXTI_RTSR1_RT6_Msk (0x1UL << EXTI_RTSR1_RT6_Pos) |
| #define | EXTI_RTSR1_RT6 EXTI_RTSR1_RT6_Msk |
| #define | EXTI_RTSR1_RT7_Pos (7U) |
| #define | EXTI_RTSR1_RT7_Msk (0x1UL << EXTI_RTSR1_RT7_Pos) |
| #define | EXTI_RTSR1_RT7 EXTI_RTSR1_RT7_Msk |
| #define | EXTI_RTSR1_RT8_Pos (8U) |
| #define | EXTI_RTSR1_RT8_Msk (0x1UL << EXTI_RTSR1_RT8_Pos) |
| #define | EXTI_RTSR1_RT8 EXTI_RTSR1_RT8_Msk |
| #define | EXTI_RTSR1_RT9_Pos (9U) |
| #define | EXTI_RTSR1_RT9_Msk (0x1UL << EXTI_RTSR1_RT9_Pos) |
| #define | EXTI_RTSR1_RT9 EXTI_RTSR1_RT9_Msk |
| #define | EXTI_RTSR1_RT10_Pos (10U) |
| #define | EXTI_RTSR1_RT10_Msk (0x1UL << EXTI_RTSR1_RT10_Pos) |
| #define | EXTI_RTSR1_RT10 EXTI_RTSR1_RT10_Msk |
| #define | EXTI_RTSR1_RT11_Pos (11U) |
| #define | EXTI_RTSR1_RT11_Msk (0x1UL << EXTI_RTSR1_RT11_Pos) |
| #define | EXTI_RTSR1_RT11 EXTI_RTSR1_RT11_Msk |
| #define | EXTI_RTSR1_RT12_Pos (12U) |
| #define | EXTI_RTSR1_RT12_Msk (0x1UL << EXTI_RTSR1_RT12_Pos) |
| #define | EXTI_RTSR1_RT12 EXTI_RTSR1_RT12_Msk |
| #define | EXTI_RTSR1_RT13_Pos (13U) |
| #define | EXTI_RTSR1_RT13_Msk (0x1UL << EXTI_RTSR1_RT13_Pos) |
| #define | EXTI_RTSR1_RT13 EXTI_RTSR1_RT13_Msk |
| #define | EXTI_RTSR1_RT14_Pos (14U) |
| #define | EXTI_RTSR1_RT14_Msk (0x1UL << EXTI_RTSR1_RT14_Pos) |
| #define | EXTI_RTSR1_RT14 EXTI_RTSR1_RT14_Msk |
| #define | EXTI_RTSR1_RT15_Pos (15U) |
| #define | EXTI_RTSR1_RT15_Msk (0x1UL << EXTI_RTSR1_RT15_Pos) |
| #define | EXTI_RTSR1_RT15 EXTI_RTSR1_RT15_Msk |
| #define | EXTI_RTSR1_RT16_Pos (16U) |
| #define | EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) |
| #define | EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk |
| #define | EXTI_RTSR1_RT17_Pos (17U) |
| #define | EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) |
| #define | EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk |
| #define | EXTI_RTSR1_RT18_Pos (18U) |
| #define | EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) |
| #define | EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk |
| #define | EXTI_RTSR1_RT19_Pos (19U) |
| #define | EXTI_RTSR1_RT19_Msk (0x1UL << EXTI_RTSR1_RT19_Pos) |
| #define | EXTI_RTSR1_RT19 EXTI_RTSR1_RT19_Msk |
| #define | EXTI_RTSR1_RT20_Pos (20U) |
| #define | EXTI_RTSR1_RT20_Msk (0x1UL << EXTI_RTSR1_RT20_Pos) |
| #define | EXTI_RTSR1_RT20 EXTI_RTSR1_RT20_Msk |
| #define | EXTI_RTSR1_RT21_Pos (21U) |
| #define | EXTI_RTSR1_RT21_Msk (0x1UL << EXTI_RTSR1_RT21_Pos) |
| #define | EXTI_RTSR1_RT21 EXTI_RTSR1_RT21_Msk |
| #define | EXTI_RTSR1_RT22_Pos (22U) |
| #define | EXTI_RTSR1_RT22_Msk (0x1UL << EXTI_RTSR1_RT22_Pos) |
| #define | EXTI_RTSR1_RT22 EXTI_RTSR1_RT22_Msk |
| #define | EXTI_RTSR1_RT23_Pos (23U) |
| #define | EXTI_RTSR1_RT23_Msk (0x1UL << EXTI_RTSR1_RT23_Pos) |
| #define | EXTI_RTSR1_RT23 EXTI_RTSR1_RT23_Msk |
| #define | EXTI_RTSR1_RT24_Pos (24U) |
| #define | EXTI_RTSR1_RT24_Msk (0x1UL << EXTI_RTSR1_RT24_Pos) |
| #define | EXTI_RTSR1_RT24 EXTI_RTSR1_RT24_Msk |
| #define | EXTI_RTSR1_RT25_Pos (25U) |
| #define | EXTI_RTSR1_RT25_Msk (0x1UL << EXTI_RTSR1_RT25_Pos) |
| #define | EXTI_RTSR1_RT25 EXTI_RTSR1_RT25_Msk |
| #define | EXTI_FTSR1_FT0_Pos (0U) |
| #define | EXTI_FTSR1_FT0_Msk (0x1UL << EXTI_FTSR1_FT0_Pos) |
| #define | EXTI_FTSR1_FT0 EXTI_FTSR1_FT0_Msk |
| #define | EXTI_FTSR1_FT1_Pos (1U) |
| #define | EXTI_FTSR1_FT1_Msk (0x1UL << EXTI_FTSR1_FT1_Pos) |
| #define | EXTI_FTSR1_FT1 EXTI_FTSR1_FT1_Msk |
| #define | EXTI_FTSR1_FT2_Pos (2U) |
| #define | EXTI_FTSR1_FT2_Msk (0x1UL << EXTI_FTSR1_FT2_Pos) |
| #define | EXTI_FTSR1_FT2 EXTI_FTSR1_FT2_Msk |
| #define | EXTI_FTSR1_FT3_Pos (3U) |
| #define | EXTI_FTSR1_FT3_Msk (0x1UL << EXTI_FTSR1_FT3_Pos) |
| #define | EXTI_FTSR1_FT3 EXTI_FTSR1_FT3_Msk |
| #define | EXTI_FTSR1_FT4_Pos (4U) |
| #define | EXTI_FTSR1_FT4_Msk (0x1UL << EXTI_FTSR1_FT4_Pos) |
| #define | EXTI_FTSR1_FT4 EXTI_FTSR1_FT4_Msk |
| #define | EXTI_FTSR1_FT5_Pos (5U) |
| #define | EXTI_FTSR1_FT5_Msk (0x1UL << EXTI_FTSR1_FT5_Pos) |
| #define | EXTI_FTSR1_FT5 EXTI_FTSR1_FT5_Msk |
| #define | EXTI_FTSR1_FT6_Pos (6U) |
| #define | EXTI_FTSR1_FT6_Msk (0x1UL << EXTI_FTSR1_FT6_Pos) |
| #define | EXTI_FTSR1_FT6 EXTI_FTSR1_FT6_Msk |
| #define | EXTI_FTSR1_FT7_Pos (7U) |
| #define | EXTI_FTSR1_FT7_Msk (0x1UL << EXTI_FTSR1_FT7_Pos) |
| #define | EXTI_FTSR1_FT7 EXTI_FTSR1_FT7_Msk |
| #define | EXTI_FTSR1_FT8_Pos (8U) |
| #define | EXTI_FTSR1_FT8_Msk (0x1UL << EXTI_FTSR1_FT8_Pos) |
| #define | EXTI_FTSR1_FT8 EXTI_FTSR1_FT8_Msk |
| #define | EXTI_FTSR1_FT9_Pos (9U) |
| #define | EXTI_FTSR1_FT9_Msk (0x1UL << EXTI_FTSR1_FT9_Pos) |
| #define | EXTI_FTSR1_FT9 EXTI_FTSR1_FT9_Msk |
| #define | EXTI_FTSR1_FT10_Pos (10U) |
| #define | EXTI_FTSR1_FT10_Msk (0x1UL << EXTI_FTSR1_FT10_Pos) |
| #define | EXTI_FTSR1_FT10 EXTI_FTSR1_FT10_Msk |
| #define | EXTI_FTSR1_FT11_Pos (11U) |
| #define | EXTI_FTSR1_FT11_Msk (0x1UL << EXTI_FTSR1_FT11_Pos) |
| #define | EXTI_FTSR1_FT11 EXTI_FTSR1_FT11_Msk |
| #define | EXTI_FTSR1_FT12_Pos (12U) |
| #define | EXTI_FTSR1_FT12_Msk (0x1UL << EXTI_FTSR1_FT12_Pos) |
| #define | EXTI_FTSR1_FT12 EXTI_FTSR1_FT12_Msk |
| #define | EXTI_FTSR1_FT13_Pos (13U) |
| #define | EXTI_FTSR1_FT13_Msk (0x1UL << EXTI_FTSR1_FT13_Pos) |
| #define | EXTI_FTSR1_FT13 EXTI_FTSR1_FT13_Msk |
| #define | EXTI_FTSR1_FT14_Pos (14U) |
| #define | EXTI_FTSR1_FT14_Msk (0x1UL << EXTI_FTSR1_FT14_Pos) |
| #define | EXTI_FTSR1_FT14 EXTI_FTSR1_FT14_Msk |
| #define | EXTI_FTSR1_FT15_Pos (15U) |
| #define | EXTI_FTSR1_FT15_Msk (0x1UL << EXTI_FTSR1_FT15_Pos) |
| #define | EXTI_FTSR1_FT15 EXTI_FTSR1_FT15_Msk |
| #define | EXTI_FTSR1_FT16_Pos (16U) |
| #define | EXTI_FTSR1_FT16_Msk (0x1UL << EXTI_FTSR1_FT16_Pos) |
| #define | EXTI_FTSR1_FT16 EXTI_FTSR1_FT16_Msk |
| #define | EXTI_FTSR1_FT17_Pos (17U) |
| #define | EXTI_FTSR1_FT17_Msk (0x1UL << EXTI_FTSR1_FT17_Pos) |
| #define | EXTI_FTSR1_FT17 EXTI_FTSR1_FT17_Msk |
| #define | EXTI_FTSR1_FT18_Pos (18U) |
| #define | EXTI_FTSR1_FT18_Msk (0x1UL << EXTI_FTSR1_FT18_Pos) |
| #define | EXTI_FTSR1_FT18 EXTI_FTSR1_FT18_Msk |
| #define | EXTI_FTSR1_FT19_Pos (19U) |
| #define | EXTI_FTSR1_FT19_Msk (0x1UL << EXTI_FTSR1_FT19_Pos) |
| #define | EXTI_FTSR1_FT19 EXTI_FTSR1_FT19_Msk |
| #define | EXTI_FTSR1_FT20_Pos (20U) |
| #define | EXTI_FTSR1_FT20_Msk (0x1UL << EXTI_FTSR1_FT20_Pos) |
| #define | EXTI_FTSR1_FT20 EXTI_FTSR1_FT20_Msk |
| #define | EXTI_FTSR1_FT21_Pos (21U) |
| #define | EXTI_FTSR1_FT21_Msk (0x1UL << EXTI_FTSR1_FT21_Pos) |
| #define | EXTI_FTSR1_FT21 EXTI_FTSR1_FT21_Msk |
| #define | EXTI_FTSR1_FT22_Pos (22U) |
| #define | EXTI_FTSR1_FT22_Msk (0x1UL << EXTI_FTSR1_FT22_Pos) |
| #define | EXTI_FTSR1_FT22 EXTI_FTSR1_FT22_Msk |
| #define | EXTI_FTSR1_FT23_Pos (23U) |
| #define | EXTI_FTSR1_FT23_Msk (0x1UL << EXTI_FTSR1_FT23_Pos) |
| #define | EXTI_FTSR1_FT23 EXTI_FTSR1_FT23_Msk |
| #define | EXTI_FTSR1_FT24_Pos (24U) |
| #define | EXTI_FTSR1_FT24_Msk (0x1UL << EXTI_FTSR1_FT24_Pos) |
| #define | EXTI_FTSR1_FT24 EXTI_FTSR1_FT24_Msk |
| #define | EXTI_FTSR1_FT25_Pos (25U) |
| #define | EXTI_FTSR1_FT25_Msk (0x1UL << EXTI_FTSR1_FT25_Pos) |
| #define | EXTI_FTSR1_FT25 EXTI_FTSR1_FT25_Msk |
| #define | EXTI_SWIER1_SWI0_Pos (0U) |
| #define | EXTI_SWIER1_SWI0_Msk (0x1UL << EXTI_SWIER1_SWI0_Pos) |
| #define | EXTI_SWIER1_SWI0 EXTI_SWIER1_SWI0_Msk |
| #define | EXTI_SWIER1_SWI1_Pos (1U) |
| #define | EXTI_SWIER1_SWI1_Msk (0x1UL << EXTI_SWIER1_SWI1_Pos) |
| #define | EXTI_SWIER1_SWI1 EXTI_SWIER1_SWI1_Msk |
| #define | EXTI_SWIER1_SWI2_Pos (2U) |
| #define | EXTI_SWIER1_SWI2_Msk (0x1UL << EXTI_SWIER1_SWI2_Pos) |
| #define | EXTI_SWIER1_SWI2 EXTI_SWIER1_SWI2_Msk |
| #define | EXTI_SWIER1_SWI3_Pos (3U) |
| #define | EXTI_SWIER1_SWI3_Msk (0x1UL << EXTI_SWIER1_SWI3_Pos) |
| #define | EXTI_SWIER1_SWI3 EXTI_SWIER1_SWI3_Msk |
| #define | EXTI_SWIER1_SWI4_Pos (4U) |
| #define | EXTI_SWIER1_SWI4_Msk (0x1UL << EXTI_SWIER1_SWI4_Pos) |
| #define | EXTI_SWIER1_SWI4 EXTI_SWIER1_SWI4_Msk |
| #define | EXTI_SWIER1_SWI5_Pos (5U) |
| #define | EXTI_SWIER1_SWI5_Msk (0x1UL << EXTI_SWIER1_SWI5_Pos) |
| #define | EXTI_SWIER1_SWI5 EXTI_SWIER1_SWI5_Msk |
| #define | EXTI_SWIER1_SWI6_Pos (6U) |
| #define | EXTI_SWIER1_SWI6_Msk (0x1UL << EXTI_SWIER1_SWI6_Pos) |
| #define | EXTI_SWIER1_SWI6 EXTI_SWIER1_SWI6_Msk |
| #define | EXTI_SWIER1_SWI7_Pos (7U) |
| #define | EXTI_SWIER1_SWI7_Msk (0x1UL << EXTI_SWIER1_SWI7_Pos) |
| #define | EXTI_SWIER1_SWI7 EXTI_SWIER1_SWI7_Msk |
| #define | EXTI_SWIER1_SWI8_Pos (8U) |
| #define | EXTI_SWIER1_SWI8_Msk (0x1UL << EXTI_SWIER1_SWI8_Pos) |
| #define | EXTI_SWIER1_SWI8 EXTI_SWIER1_SWI8_Msk |
| #define | EXTI_SWIER1_SWI9_Pos (9U) |
| #define | EXTI_SWIER1_SWI9_Msk (0x1UL << EXTI_SWIER1_SWI9_Pos) |
| #define | EXTI_SWIER1_SWI9 EXTI_SWIER1_SWI9_Msk |
| #define | EXTI_SWIER1_SWI10_Pos (10U) |
| #define | EXTI_SWIER1_SWI10_Msk (0x1UL << EXTI_SWIER1_SWI10_Pos) |
| #define | EXTI_SWIER1_SWI10 EXTI_SWIER1_SWI10_Msk |
| #define | EXTI_SWIER1_SWI11_Pos (11U) |
| #define | EXTI_SWIER1_SWI11_Msk (0x1UL << EXTI_SWIER1_SWI11_Pos) |
| #define | EXTI_SWIER1_SWI11 EXTI_SWIER1_SWI11_Msk |
| #define | EXTI_SWIER1_SWI12_Pos (12U) |
| #define | EXTI_SWIER1_SWI12_Msk (0x1UL << EXTI_SWIER1_SWI12_Pos) |
| #define | EXTI_SWIER1_SWI12 EXTI_SWIER1_SWI12_Msk |
| #define | EXTI_SWIER1_SWI13_Pos (13U) |
| #define | EXTI_SWIER1_SWI13_Msk (0x1UL << EXTI_SWIER1_SWI13_Pos) |
| #define | EXTI_SWIER1_SWI13 EXTI_SWIER1_SWI13_Msk |
| #define | EXTI_SWIER1_SWI14_Pos (14U) |
| #define | EXTI_SWIER1_SWI14_Msk (0x1UL << EXTI_SWIER1_SWI14_Pos) |
| #define | EXTI_SWIER1_SWI14 EXTI_SWIER1_SWI14_Msk |
| #define | EXTI_SWIER1_SWI15_Pos (15U) |
| #define | EXTI_SWIER1_SWI15_Msk (0x1UL << EXTI_SWIER1_SWI15_Pos) |
| #define | EXTI_SWIER1_SWI15 EXTI_SWIER1_SWI15_Msk |
| #define | EXTI_SWIER1_SWI16_Pos (16U) |
| #define | EXTI_SWIER1_SWI16_Msk (0x1UL << EXTI_SWIER1_SWI16_Pos) |
| #define | EXTI_SWIER1_SWI16 EXTI_SWIER1_SWI16_Msk |
| #define | EXTI_SWIER1_SWI17_Pos (17U) |
| #define | EXTI_SWIER1_SWI17_Msk (0x1UL << EXTI_SWIER1_SWI17_Pos) |
| #define | EXTI_SWIER1_SWI17 EXTI_SWIER1_SWI17_Msk |
| #define | EXTI_SWIER1_SWI18_Pos (18U) |
| #define | EXTI_SWIER1_SWI18_Msk (0x1UL << EXTI_SWIER1_SWI18_Pos) |
| #define | EXTI_SWIER1_SWI18 EXTI_SWIER1_SWI18_Msk |
| #define | EXTI_SWIER1_SWI19_Pos (19U) |
| #define | EXTI_SWIER1_SWI19_Msk (0x1UL << EXTI_SWIER1_SWI19_Pos) |
| #define | EXTI_SWIER1_SWI19 EXTI_SWIER1_SWI19_Msk |
| #define | EXTI_SWIER1_SWI20_Pos (20U) |
| #define | EXTI_SWIER1_SWI20_Msk (0x1UL << EXTI_SWIER1_SWI20_Pos) |
| #define | EXTI_SWIER1_SWI20 EXTI_SWIER1_SWI20_Msk |
| #define | EXTI_SWIER1_SWI21_Pos (21U) |
| #define | EXTI_SWIER1_SWI21_Msk (0x1UL << EXTI_SWIER1_SWI21_Pos) |
| #define | EXTI_SWIER1_SWI21 EXTI_SWIER1_SWI21_Msk |
| #define | EXTI_SWIER1_SWI22_Pos (22U) |
| #define | EXTI_SWIER1_SWI22_Msk (0x1UL << EXTI_SWIER1_SWI22_Pos) |
| #define | EXTI_SWIER1_SWI22 EXTI_SWIER1_SWI22_Msk |
| #define | EXTI_SWIER1_SWI23_Pos (23U) |
| #define | EXTI_SWIER1_SWI23_Msk (0x1UL << EXTI_SWIER1_SWI23_Pos) |
| #define | EXTI_SWIER1_SWI23 EXTI_SWIER1_SWI23_Msk |
| #define | EXTI_SWIER1_SWI24_Pos (24U) |
| #define | EXTI_SWIER1_SWI24_Msk (0x1UL << EXTI_SWIER1_SWI24_Pos) |
| #define | EXTI_SWIER1_SWI24 EXTI_SWIER1_SWI24_Msk |
| #define | EXTI_SWIER1_SWI25_Pos (25U) |
| #define | EXTI_SWIER1_SWI25_Msk (0x1UL << EXTI_SWIER1_SWI25_Pos) |
| #define | EXTI_SWIER1_SWI25 EXTI_SWIER1_SWI25_Msk |
| #define | EXTI_RPR1_RPIF0_Pos (0U) |
| #define | EXTI_RPR1_RPIF0_Msk (0x1UL << EXTI_RPR1_RPIF0_Pos) |
| #define | EXTI_RPR1_RPIF0 EXTI_RPR1_RPIF0_Msk |
| #define | EXTI_RPR1_RPIF1_Pos (1U) |
| #define | EXTI_RPR1_RPIF1_Msk (0x1UL << EXTI_RPR1_RPIF1_Pos) |
| #define | EXTI_RPR1_RPIF1 EXTI_RPR1_RPIF1_Msk |
| #define | EXTI_RPR1_RPIF2_Pos (2U) |
| #define | EXTI_RPR1_RPIF2_Msk (0x1UL << EXTI_RPR1_RPIF2_Pos) |
| #define | EXTI_RPR1_RPIF2 EXTI_RPR1_RPIF2_Msk |
| #define | EXTI_RPR1_RPIF3_Pos (3U) |
| #define | EXTI_RPR1_RPIF3_Msk (0x1UL << EXTI_RPR1_RPIF3_Pos) |
| #define | EXTI_RPR1_RPIF3 EXTI_RPR1_RPIF3_Msk |
| #define | EXTI_RPR1_RPIF4_Pos (4U) |
| #define | EXTI_RPR1_RPIF4_Msk (0x1UL << EXTI_RPR1_RPIF4_Pos) |
| #define | EXTI_RPR1_RPIF4 EXTI_RPR1_RPIF4_Msk |
| #define | EXTI_RPR1_RPIF5_Pos (5U) |
| #define | EXTI_RPR1_RPIF5_Msk (0x1UL << EXTI_RPR1_RPIF5_Pos) |
| #define | EXTI_RPR1_RPIF5 EXTI_RPR1_RPIF5_Msk |
| #define | EXTI_RPR1_RPIF6_Pos (6U) |
| #define | EXTI_RPR1_RPIF6_Msk (0x1UL << EXTI_RPR1_RPIF6_Pos) |
| #define | EXTI_RPR1_RPIF6 EXTI_RPR1_RPIF6_Msk |
| #define | EXTI_RPR1_RPIF7_Pos (7U) |
| #define | EXTI_RPR1_RPIF7_Msk (0x1UL << EXTI_RPR1_RPIF7_Pos) |
| #define | EXTI_RPR1_RPIF7 EXTI_RPR1_RPIF7_Msk |
| #define | EXTI_RPR1_RPIF8_Pos (8U) |
| #define | EXTI_RPR1_RPIF8_Msk (0x1UL << EXTI_RPR1_RPIF8_Pos) |
| #define | EXTI_RPR1_RPIF8 EXTI_RPR1_RPIF8_Msk |
| #define | EXTI_RPR1_RPIF9_Pos (9U) |
| #define | EXTI_RPR1_RPIF9_Msk (0x1UL << EXTI_RPR1_RPIF9_Pos) |
| #define | EXTI_RPR1_RPIF9 EXTI_RPR1_RPIF9_Msk |
| #define | EXTI_RPR1_RPIF10_Pos (10U) |
| #define | EXTI_RPR1_RPIF10_Msk (0x1UL << EXTI_RPR1_RPIF10_Pos) |
| #define | EXTI_RPR1_RPIF10 EXTI_RPR1_RPIF10_Msk |
| #define | EXTI_RPR1_RPIF11_Pos (11U) |
| #define | EXTI_RPR1_RPIF11_Msk (0x1UL << EXTI_RPR1_RPIF11_Pos) |
| #define | EXTI_RPR1_RPIF11 EXTI_RPR1_RPIF11_Msk |
| #define | EXTI_RPR1_RPIF12_Pos (12U) |
| #define | EXTI_RPR1_RPIF12_Msk (0x1UL << EXTI_RPR1_RPIF12_Pos) |
| #define | EXTI_RPR1_RPIF12 EXTI_RPR1_RPIF12_Msk |
| #define | EXTI_RPR1_RPIF13_Pos (13U) |
| #define | EXTI_RPR1_RPIF13_Msk (0x1UL << EXTI_RPR1_RPIF13_Pos) |
| #define | EXTI_RPR1_RPIF13 EXTI_RPR1_RPIF13_Msk |
| #define | EXTI_RPR1_RPIF14_Pos (14U) |
| #define | EXTI_RPR1_RPIF14_Msk (0x1UL << EXTI_RPR1_RPIF14_Pos) |
| #define | EXTI_RPR1_RPIF14 EXTI_RPR1_RPIF14_Msk |
| #define | EXTI_RPR1_RPIF15_Pos (15U) |
| #define | EXTI_RPR1_RPIF15_Msk (0x1UL << EXTI_RPR1_RPIF15_Pos) |
| #define | EXTI_RPR1_RPIF15 EXTI_RPR1_RPIF15_Msk |
| #define | EXTI_RPR1_RPIF16_Pos (16U) |
| #define | EXTI_RPR1_RPIF16_Msk (0x1UL << EXTI_RPR1_RPIF16_Pos) |
| #define | EXTI_RPR1_RPIF16 EXTI_RPR1_RPIF16_Msk |
| #define | EXTI_RPR1_RPIF17_Pos (17U) |
| #define | EXTI_RPR1_RPIF17_Msk (0x1UL << EXTI_RPR1_RPIF17_Pos) |
| #define | EXTI_RPR1_RPIF17 EXTI_RPR1_RPIF17_Msk |
| #define | EXTI_RPR1_RPIF18_Pos (18U) |
| #define | EXTI_RPR1_RPIF18_Msk (0x1UL << EXTI_RPR1_RPIF18_Pos) |
| #define | EXTI_RPR1_RPIF18 EXTI_RPR1_RPIF18_Msk |
| #define | EXTI_RPR1_RPIF19_Pos (19U) |
| #define | EXTI_RPR1_RPIF19_Msk (0x1UL << EXTI_RPR1_RPIF19_Pos) |
| #define | EXTI_RPR1_RPIF19 EXTI_RPR1_RPIF19_Msk |
| #define | EXTI_RPR1_RPIF20_Pos (20U) |
| #define | EXTI_RPR1_RPIF20_Msk (0x1UL << EXTI_RPR1_RPIF20_Pos) |
| #define | EXTI_RPR1_RPIF20 EXTI_RPR1_RPIF20_Msk |
| #define | EXTI_RPR1_RPIF21_Pos (21U) |
| #define | EXTI_RPR1_RPIF21_Msk (0x1UL << EXTI_RPR1_RPIF21_Pos) |
| #define | EXTI_RPR1_RPIF21 EXTI_RPR1_RPIF21_Msk |
| #define | EXTI_RPR1_RPIF22_Pos (22U) |
| #define | EXTI_RPR1_RPIF22_Msk (0x1UL << EXTI_RPR1_RPIF22_Pos) |
| #define | EXTI_RPR1_RPIF22 EXTI_RPR1_RPIF22_Msk |
| #define | EXTI_RPR1_RPIF23_Pos (23U) |
| #define | EXTI_RPR1_RPIF23_Msk (0x1UL << EXTI_RPR1_RPIF23_Pos) |
| #define | EXTI_RPR1_RPIF23 EXTI_RPR1_RPIF23_Msk |
| #define | EXTI_RPR1_RPIF24_Pos (24U) |
| #define | EXTI_RPR1_RPIF24_Msk (0x1UL << EXTI_RPR1_RPIF24_Pos) |
| #define | EXTI_RPR1_RPIF24 EXTI_RPR1_RPIF24_Msk |
| #define | EXTI_RPR1_RPIF25_Pos (25U) |
| #define | EXTI_RPR1_RPIF25_Msk (0x1UL << EXTI_RPR1_RPIF25_Pos) |
| #define | EXTI_RPR1_RPIF25 EXTI_RPR1_RPIF25_Msk |
| #define | EXTI_FPR1_FPIF0_Pos (0U) |
| #define | EXTI_FPR1_FPIF0_Msk (0x1UL << EXTI_FPR1_FPIF0_Pos) |
| #define | EXTI_FPR1_FPIF0 EXTI_FPR1_FPIF0_Msk |
| #define | EXTI_FPR1_FPIF1_Pos (1U) |
| #define | EXTI_FPR1_FPIF1_Msk (0x1UL << EXTI_FPR1_FPIF1_Pos) |
| #define | EXTI_FPR1_FPIF1 EXTI_FPR1_FPIF1_Msk |
| #define | EXTI_FPR1_FPIF2_Pos (2U) |
| #define | EXTI_FPR1_FPIF2_Msk (0x1UL << EXTI_FPR1_FPIF2_Pos) |
| #define | EXTI_FPR1_FPIF2 EXTI_FPR1_FPIF2_Msk |
| #define | EXTI_FPR1_FPIF3_Pos (3U) |
| #define | EXTI_FPR1_FPIF3_Msk (0x1UL << EXTI_FPR1_FPIF3_Pos) |
| #define | EXTI_FPR1_FPIF3 EXTI_FPR1_FPIF3_Msk |
| #define | EXTI_FPR1_FPIF4_Pos (4U) |
| #define | EXTI_FPR1_FPIF4_Msk (0x1UL << EXTI_FPR1_FPIF4_Pos) |
| #define | EXTI_FPR1_FPIF4 EXTI_FPR1_FPIF4_Msk |
| #define | EXTI_FPR1_FPIF5_Pos (5U) |
| #define | EXTI_FPR1_FPIF5_Msk (0x1UL << EXTI_FPR1_FPIF5_Pos) |
| #define | EXTI_FPR1_FPIF5 EXTI_FPR1_FPIF5_Msk |
| #define | EXTI_FPR1_FPIF6_Pos (6U) |
| #define | EXTI_FPR1_FPIF6_Msk (0x1UL << EXTI_FPR1_FPIF6_Pos) |
| #define | EXTI_FPR1_FPIF6 EXTI_FPR1_FPIF6_Msk |
| #define | EXTI_FPR1_FPIF7_Pos (7U) |
| #define | EXTI_FPR1_FPIF7_Msk (0x1UL << EXTI_FPR1_FPIF7_Pos) |
| #define | EXTI_FPR1_FPIF7 EXTI_FPR1_FPIF7_Msk |
| #define | EXTI_FPR1_FPIF8_Pos (8U) |
| #define | EXTI_FPR1_FPIF8_Msk (0x1UL << EXTI_FPR1_FPIF8_Pos) |
| #define | EXTI_FPR1_FPIF8 EXTI_FPR1_FPIF8_Msk |
| #define | EXTI_FPR1_FPIF9_Pos (9U) |
| #define | EXTI_FPR1_FPIF9_Msk (0x1UL << EXTI_FPR1_FPIF9_Pos) |
| #define | EXTI_FPR1_FPIF9 EXTI_FPR1_FPIF9_Msk |
| #define | EXTI_FPR1_FPIF10_Pos (10U) |
| #define | EXTI_FPR1_FPIF10_Msk (0x1UL << EXTI_FPR1_FPIF10_Pos) |
| #define | EXTI_FPR1_FPIF10 EXTI_FPR1_FPIF10_Msk |
| #define | EXTI_FPR1_FPIF11_Pos (11U) |
| #define | EXTI_FPR1_FPIF11_Msk (0x1UL << EXTI_FPR1_FPIF11_Pos) |
| #define | EXTI_FPR1_FPIF11 EXTI_FPR1_FPIF11_Msk |
| #define | EXTI_FPR1_FPIF12_Pos (12U) |
| #define | EXTI_FPR1_FPIF12_Msk (0x1UL << EXTI_FPR1_FPIF12_Pos) |
| #define | EXTI_FPR1_FPIF12 EXTI_FPR1_FPIF12_Msk |
| #define | EXTI_FPR1_FPIF13_Pos (13U) |
| #define | EXTI_FPR1_FPIF13_Msk (0x1UL << EXTI_FPR1_FPIF13_Pos) |
| #define | EXTI_FPR1_FPIF13 EXTI_FPR1_FPIF13_Msk |
| #define | EXTI_FPR1_FPIF14_Pos (14U) |
| #define | EXTI_FPR1_FPIF14_Msk (0x1UL << EXTI_FPR1_FPIF14_Pos) |
| #define | EXTI_FPR1_FPIF14 EXTI_FPR1_FPIF14_Msk |
| #define | EXTI_FPR1_FPIF15_Pos (15U) |
| #define | EXTI_FPR1_FPIF15_Msk (0x1UL << EXTI_FPR1_FPIF15_Pos) |
| #define | EXTI_FPR1_FPIF15 EXTI_FPR1_FPIF15_Msk |
| #define | EXTI_FPR1_FPIF16_Pos (16U) |
| #define | EXTI_FPR1_FPIF16_Msk (0x1UL << EXTI_FPR1_FPIF16_Pos) |
| #define | EXTI_FPR1_FPIF16 EXTI_FPR1_FPIF16_Msk |
| #define | EXTI_FPR1_FPIF17_Pos (17U) |
| #define | EXTI_FPR1_FPIF17_Msk (0x1UL << EXTI_FPR1_FPIF17_Pos) |
| #define | EXTI_FPR1_FPIF17 EXTI_FPR1_FPIF17_Msk |
| #define | EXTI_FPR1_FPIF18_Pos (18U) |
| #define | EXTI_FPR1_FPIF18_Msk (0x1UL << EXTI_FPR1_FPIF18_Pos) |
| #define | EXTI_FPR1_FPIF18 EXTI_FPR1_FPIF18_Msk |
| #define | EXTI_FPR1_FPIF19_Pos (19U) |
| #define | EXTI_FPR1_FPIF19_Msk (0x1UL << EXTI_FPR1_FPIF19_Pos) |
| #define | EXTI_FPR1_FPIF19 EXTI_FPR1_FPIF19_Msk |
| #define | EXTI_FPR1_FPIF20_Pos (20U) |
| #define | EXTI_FPR1_FPIF20_Msk (0x1UL << EXTI_FPR1_FPIF20_Pos) |
| #define | EXTI_FPR1_FPIF20 EXTI_FPR1_FPIF20_Msk |
| #define | EXTI_FPR1_FPIF21_Pos (21U) |
| #define | EXTI_FPR1_FPIF21_Msk (0x1UL << EXTI_FPR1_FPIF21_Pos) |
| #define | EXTI_FPR1_FPIF21 EXTI_FPR1_FPIF21_Msk |
| #define | EXTI_FPR1_FPIF22_Pos (22U) |
| #define | EXTI_FPR1_FPIF22_Msk (0x1UL << EXTI_FPR1_FPIF22_Pos) |
| #define | EXTI_FPR1_FPIF22 EXTI_FPR1_FPIF22_Msk |
| #define | EXTI_FPR1_FPIF23_Pos (23U) |
| #define | EXTI_FPR1_FPIF23_Msk (0x1UL << EXTI_FPR1_FPIF23_Pos) |
| #define | EXTI_FPR1_FPIF23 EXTI_FPR1_FPIF23_Msk |
| #define | EXTI_FPR1_FPIF24_Pos (24U) |
| #define | EXTI_FPR1_FPIF24_Msk (0x1UL << EXTI_FPR1_FPIF24_Pos) |
| #define | EXTI_FPR1_FPIF24 EXTI_FPR1_FPIF24_Msk |
| #define | EXTI_FPR1_FPIF25_Pos (25U) |
| #define | EXTI_FPR1_FPIF25_Msk (0x1UL << EXTI_FPR1_FPIF25_Pos) |
| #define | EXTI_FPR1_FPIF25 EXTI_FPR1_FPIF25_Msk |
| #define | EXTI_SECCFGR1_SEC0_Pos (0U) |
| #define | EXTI_SECCFGR1_SEC0_Msk (0x1UL << EXTI_SECCFGR1_SEC0_Pos) |
| #define | EXTI_SECCFGR1_SEC0 EXTI_SECCFGR1_SEC0_Msk |
| #define | EXTI_SECCFGR1_SEC1_Pos (1U) |
| #define | EXTI_SECCFGR1_SEC1_Msk (0x1UL << EXTI_SECCFGR1_SEC1_Pos) |
| #define | EXTI_SECCFGR1_SEC1 EXTI_SECCFGR1_SEC1_Msk |
| #define | EXTI_SECCFGR1_SEC2_Pos (2U) |
| #define | EXTI_SECCFGR1_SEC2_Msk (0x1UL << EXTI_SECCFGR1_SEC2_Pos) |
| #define | EXTI_SECCFGR1_SEC2 EXTI_SECCFGR1_SEC2_Msk |
| #define | EXTI_SECCFGR1_SEC3_Pos (3U) |
| #define | EXTI_SECCFGR1_SEC3_Msk (0x1UL << EXTI_SECCFGR1_SEC3_Pos) |
| #define | EXTI_SECCFGR1_SEC3 EXTI_SECCFGR1_SEC3_Msk |
| #define | EXTI_SECCFGR1_SEC4_Pos (4U) |
| #define | EXTI_SECCFGR1_SEC4_Msk (0x1UL << EXTI_SECCFGR1_SEC4_Pos) |
| #define | EXTI_SECCFGR1_SEC4 EXTI_SECCFGR1_SEC4_Msk |
| #define | EXTI_SECCFGR1_SEC5_Pos (5U) |
| #define | EXTI_SECCFGR1_SEC5_Msk (0x1UL << EXTI_SECCFGR1_SEC5_Pos) |
| #define | EXTI_SECCFGR1_SEC5 EXTI_SECCFGR1_SEC5_Msk |
| #define | EXTI_SECCFGR1_SEC6_Pos (6U) |
| #define | EXTI_SECCFGR1_SEC6_Msk (0x1UL << EXTI_SECCFGR1_SEC6_Pos) |
| #define | EXTI_SECCFGR1_SEC6 EXTI_SECCFGR1_SEC6_Msk |
| #define | EXTI_SECCFGR1_SEC7_Pos (7U) |
| #define | EXTI_SECCFGR1_SEC7_Msk (0x1UL << EXTI_SECCFGR1_SEC7_Pos) |
| #define | EXTI_SECCFGR1_SEC7 EXTI_SECCFGR1_SEC7_Msk |
| #define | EXTI_SECCFGR1_SEC8_Pos (8U) |
| #define | EXTI_SECCFGR1_SEC8_Msk (0x1UL << EXTI_SECCFGR1_SEC8_Pos) |
| #define | EXTI_SECCFGR1_SEC8 EXTI_SECCFGR1_SEC8_Msk |
| #define | EXTI_SECCFGR1_SEC9_Pos (9U) |
| #define | EXTI_SECCFGR1_SEC9_Msk (0x1UL << EXTI_SECCFGR1_SEC9_Pos) |
| #define | EXTI_SECCFGR1_SEC9 EXTI_SECCFGR1_SEC9_Msk |
| #define | EXTI_SECCFGR1_SEC10_Pos (10U) |
| #define | EXTI_SECCFGR1_SEC10_Msk (0x1UL << EXTI_SECCFGR1_SEC10_Pos) |
| #define | EXTI_SECCFGR1_SEC10 EXTI_SECCFGR1_SEC10_Msk |
| #define | EXTI_SECCFGR1_SEC11_Pos (11U) |
| #define | EXTI_SECCFGR1_SEC11_Msk (0x1UL << EXTI_SECCFGR1_SEC11_Pos) |
| #define | EXTI_SECCFGR1_SEC11 EXTI_SECCFGR1_SEC11_Msk |
| #define | EXTI_SECCFGR1_SEC12_Pos (12U) |
| #define | EXTI_SECCFGR1_SEC12_Msk (0x1UL << EXTI_SECCFGR1_SEC12_Pos) |
| #define | EXTI_SECCFGR1_SEC12 EXTI_SECCFGR1_SEC12_Msk |
| #define | EXTI_SECCFGR1_SEC13_Pos (13U) |
| #define | EXTI_SECCFGR1_SEC13_Msk (0x1UL << EXTI_SECCFGR1_SEC13_Pos) |
| #define | EXTI_SECCFGR1_SEC13 EXTI_SECCFGR1_SEC13_Msk |
| #define | EXTI_SECCFGR1_SEC14_Pos (14U) |
| #define | EXTI_SECCFGR1_SEC14_Msk (0x1UL << EXTI_SECCFGR1_SEC14_Pos) |
| #define | EXTI_SECCFGR1_SEC14 EXTI_SECCFGR1_SEC14_Msk |
| #define | EXTI_SECCFGR1_SEC15_Pos (15U) |
| #define | EXTI_SECCFGR1_SEC15_Msk (0x1UL << EXTI_SECCFGR1_SEC15_Pos) |
| #define | EXTI_SECCFGR1_SEC15 EXTI_SECCFGR1_SEC15_Msk |
| #define | EXTI_SECCFGR1_SEC16_Pos (16U) |
| #define | EXTI_SECCFGR1_SEC16_Msk (0x1UL << EXTI_SECCFGR1_SEC16_Pos) |
| #define | EXTI_SECCFGR1_SEC16 EXTI_SECCFGR1_SEC16_Msk |
| #define | EXTI_SECCFGR1_SEC17_Pos (17U) |
| #define | EXTI_SECCFGR1_SEC17_Msk (0x1UL << EXTI_SECCFGR1_SEC17_Pos) |
| #define | EXTI_SECCFGR1_SEC17 EXTI_SECCFGR1_SEC17_Msk |
| #define | EXTI_SECCFGR1_SEC18_Pos (18U) |
| #define | EXTI_SECCFGR1_SEC18_Msk (0x1UL << EXTI_SECCFGR1_SEC18_Pos) |
| #define | EXTI_SECCFGR1_SEC18 EXTI_SECCFGR1_SEC18_Msk |
| #define | EXTI_SECCFGR1_SEC19_Pos (19U) |
| #define | EXTI_SECCFGR1_SEC19_Msk (0x1UL << EXTI_SECCFGR1_SEC19_Pos) |
| #define | EXTI_SECCFGR1_SEC19 EXTI_SECCFGR1_SEC19_Msk |
| #define | EXTI_SECCFGR1_SEC20_Pos (20U) |
| #define | EXTI_SECCFGR1_SEC20_Msk (0x1UL << EXTI_SECCFGR1_SEC20_Pos) |
| #define | EXTI_SECCFGR1_SEC20 EXTI_SECCFGR1_SEC20_Msk |
| #define | EXTI_SECCFGR1_SEC21_Pos (21U) |
| #define | EXTI_SECCFGR1_SEC21_Msk (0x1UL << EXTI_SECCFGR1_SEC21_Pos) |
| #define | EXTI_SECCFGR1_SEC21 EXTI_SECCFGR1_SEC21_Msk |
| #define | EXTI_SECCFGR1_SEC22_Pos (22U) |
| #define | EXTI_SECCFGR1_SEC22_Msk (0x1UL << EXTI_SECCFGR1_SEC22_Pos) |
| #define | EXTI_SECCFGR1_SEC22 EXTI_SECCFGR1_SEC22_Msk |
| #define | EXTI_SECCFGR1_SEC23_Pos (23U) |
| #define | EXTI_SECCFGR1_SEC23_Msk (0x1UL << EXTI_SECCFGR1_SEC23_Pos) |
| #define | EXTI_SECCFGR1_SEC23 EXTI_SECCFGR1_SEC23_Msk |
| #define | EXTI_SECCFGR1_SEC24_Pos (24U) |
| #define | EXTI_SECCFGR1_SEC24_Msk (0x1UL << EXTI_SECCFGR1_SEC24_Pos) |
| #define | EXTI_SECCFGR1_SEC24 EXTI_SECCFGR1_SEC24_Msk |
| #define | EXTI_SECCFGR1_SEC25_Pos (25U) |
| #define | EXTI_SECCFGR1_SEC25_Msk (0x1UL << EXTI_SECCFGR1_SEC25_Pos) |
| #define | EXTI_SECCFGR1_SEC25 EXTI_SECCFGR1_SEC25_Msk |
| #define | EXTI_PRIVCFGR1_PRIV0_Pos (0U) |
| #define | EXTI_PRIVCFGR1_PRIV0_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV0_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV0 EXTI_PRIVCFGR1_PRIV0_Msk |
| #define | EXTI_PRIVCFGR1_PRIV1_Pos (1U) |
| #define | EXTI_PRIVCFGR1_PRIV1_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV1_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV1 EXTI_PRIVCFGR1_PRIV1_Msk |
| #define | EXTI_PRIVCFGR1_PRIV2_Pos (2U) |
| #define | EXTI_PRIVCFGR1_PRIV2_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV2_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV2 EXTI_PRIVCFGR1_PRIV2_Msk |
| #define | EXTI_PRIVCFGR1_PRIV3_Pos (3U) |
| #define | EXTI_PRIVCFGR1_PRIV3_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV3_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV3 EXTI_PRIVCFGR1_PRIV3_Msk |
| #define | EXTI_PRIVCFGR1_PRIV4_Pos (4U) |
| #define | EXTI_PRIVCFGR1_PRIV4_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV4_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV4 EXTI_PRIVCFGR1_PRIV4_Msk |
| #define | EXTI_PRIVCFGR1_PRIV5_Pos (5U) |
| #define | EXTI_PRIVCFGR1_PRIV5_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV5_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV5 EXTI_PRIVCFGR1_PRIV5_Msk |
| #define | EXTI_PRIVCFGR1_PRIV6_Pos (6U) |
| #define | EXTI_PRIVCFGR1_PRIV6_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV6_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV6 EXTI_PRIVCFGR1_PRIV6_Msk |
| #define | EXTI_PRIVCFGR1_PRIV7_Pos (7U) |
| #define | EXTI_PRIVCFGR1_PRIV7_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV7_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV7 EXTI_PRIVCFGR1_PRIV7_Msk |
| #define | EXTI_PRIVCFGR1_PRIV8_Pos (8U) |
| #define | EXTI_PRIVCFGR1_PRIV8_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV8_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV8 EXTI_PRIVCFGR1_PRIV8_Msk |
| #define | EXTI_PRIVCFGR1_PRIV9_Pos (9U) |
| #define | EXTI_PRIVCFGR1_PRIV9_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV9_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV9 EXTI_PRIVCFGR1_PRIV9_Msk |
| #define | EXTI_PRIVCFGR1_PRIV10_Pos (10U) |
| #define | EXTI_PRIVCFGR1_PRIV10_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV10_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV10 EXTI_PRIVCFGR1_PRIV10_Msk |
| #define | EXTI_PRIVCFGR1_PRIV11_Pos (11U) |
| #define | EXTI_PRIVCFGR1_PRIV11_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV11_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV11 EXTI_PRIVCFGR1_PRIV11_Msk |
| #define | EXTI_PRIVCFGR1_PRIV12_Pos (12U) |
| #define | EXTI_PRIVCFGR1_PRIV12_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV12_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV12 EXTI_PRIVCFGR1_PRIV12_Msk |
| #define | EXTI_PRIVCFGR1_PRIV13_Pos (13U) |
| #define | EXTI_PRIVCFGR1_PRIV13_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV13_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV13 EXTI_PRIVCFGR1_PRIV13_Msk |
| #define | EXTI_PRIVCFGR1_PRIV14_Pos (14U) |
| #define | EXTI_PRIVCFGR1_PRIV14_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV14_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV14 EXTI_PRIVCFGR1_PRIV14_Msk |
| #define | EXTI_PRIVCFGR1_PRIV15_Pos (15U) |
| #define | EXTI_PRIVCFGR1_PRIV15_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV15_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV15 EXTI_PRIVCFGR1_PRIV15_Msk |
| #define | EXTI_PRIVCFGR1_PRIV16_Pos (16U) |
| #define | EXTI_PRIVCFGR1_PRIV16_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV16_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV16 EXTI_PRIVCFGR1_PRIV16_Msk |
| #define | EXTI_PRIVCFGR1_PRIV17_Pos (17U) |
| #define | EXTI_PRIVCFGR1_PRIV17_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV17_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV17 EXTI_PRIVCFGR1_PRIV17_Msk |
| #define | EXTI_PRIVCFGR1_PRIV18_Pos (18U) |
| #define | EXTI_PRIVCFGR1_PRIV18_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV18_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV18 EXTI_PRIVCFGR1_PRIV18_Msk |
| #define | EXTI_PRIVCFGR1_PRIV19_Pos (19U) |
| #define | EXTI_PRIVCFGR1_PRIV19_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV19_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV19 EXTI_PRIVCFGR1_PRIV19_Msk |
| #define | EXTI_PRIVCFGR1_PRIV20_Pos (20U) |
| #define | EXTI_PRIVCFGR1_PRIV20_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV20_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV20 EXTI_PRIVCFGR1_PRIV20_Msk |
| #define | EXTI_PRIVCFGR1_PRIV21_Pos (21U) |
| #define | EXTI_PRIVCFGR1_PRIV21_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV21_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV21 EXTI_PRIVCFGR1_PRIV21_Msk |
| #define | EXTI_PRIVCFGR1_PRIV22_Pos (22U) |
| #define | EXTI_PRIVCFGR1_PRIV22_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV22_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV22 EXTI_PRIVCFGR1_PRIV22_Msk |
| #define | EXTI_PRIVCFGR1_PRIV23_Pos (23U) |
| #define | EXTI_PRIVCFGR1_PRIV23_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV23_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV23 EXTI_PRIVCFGR1_PRIV23_Msk |
| #define | EXTI_PRIVCFGR1_PRIV24_Pos (24U) |
| #define | EXTI_PRIVCFGR1_PRIV24_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV24_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV24 EXTI_PRIVCFGR1_PRIV24_Msk |
| #define | EXTI_PRIVCFGR1_PRIV25_Pos (25U) |
| #define | EXTI_PRIVCFGR1_PRIV25_Msk (0x1UL << EXTI_PRIVCFGR1_PRIV25_Pos) |
| #define | EXTI_PRIVCFGR1_PRIV25 EXTI_PRIVCFGR1_PRIV25_Msk |
| #define | EXTI_EXTICR1_EXTI0_Pos (0U) |
| #define | EXTI_EXTICR1_EXTI0_Msk (0xFUL << EXTI_EXTICR1_EXTI0_Pos) |
| #define | EXTI_EXTICR1_EXTI0 EXTI_EXTICR1_EXTI0_Msk |
| #define | EXTI_EXTICR1_EXTI0_0 (0x1UL << EXTI_EXTICR1_EXTI0_Pos) |
| #define | EXTI_EXTICR1_EXTI0_1 (0x2UL << EXTI_EXTICR1_EXTI0_Pos) |
| #define | EXTI_EXTICR1_EXTI0_2 (0x4UL << EXTI_EXTICR1_EXTI0_Pos) |
| #define | EXTI_EXTICR1_EXTI0_3 (0x8UL << EXTI_EXTICR1_EXTI0_Pos) |
| #define | EXTI_EXTICR1_EXTI1_Pos (8U) |
| #define | EXTI_EXTICR1_EXTI1_Msk (0xFUL << EXTI_EXTICR1_EXTI1_Pos) |
| #define | EXTI_EXTICR1_EXTI1 EXTI_EXTICR1_EXTI1_Msk |
| #define | EXTI_EXTICR1_EXTI1_0 (0x1UL << EXTI_EXTICR1_EXTI1_Pos) |
| #define | EXTI_EXTICR1_EXTI1_1 (0x2UL << EXTI_EXTICR1_EXTI1_Pos) |
| #define | EXTI_EXTICR1_EXTI1_2 (0x4UL << EXTI_EXTICR1_EXTI1_Pos) |
| #define | EXTI_EXTICR1_EXTI1_3 (0x8UL << EXTI_EXTICR1_EXTI1_Pos) |
| #define | EXTI_EXTICR1_EXTI2_Pos (16U) |
| #define | EXTI_EXTICR1_EXTI2_Msk (0xFUL << EXTI_EXTICR1_EXTI2_Pos) |
| #define | EXTI_EXTICR1_EXTI2 EXTI_EXTICR1_EXTI2_Msk |
| #define | EXTI_EXTICR1_EXTI2_0 (0x1UL << EXTI_EXTICR1_EXTI2_Pos) |
| #define | EXTI_EXTICR1_EXTI2_1 (0x2UL << EXTI_EXTICR1_EXTI2_Pos) |
| #define | EXTI_EXTICR1_EXTI2_2 (0x4UL << EXTI_EXTICR1_EXTI2_Pos) |
| #define | EXTI_EXTICR1_EXTI2_3 (0x8UL << EXTI_EXTICR1_EXTI2_Pos) |
| #define | EXTI_EXTICR1_EXTI3_Pos (24U) |
| #define | EXTI_EXTICR1_EXTI3_Msk (0xFUL << EXTI_EXTICR1_EXTI3_Pos) |
| #define | EXTI_EXTICR1_EXTI3 EXTI_EXTICR1_EXTI3_Msk |
| #define | EXTI_EXTICR1_EXTI3_0 (0x1UL << EXTI_EXTICR1_EXTI3_Pos) |
| #define | EXTI_EXTICR1_EXTI3_1 (0x2UL << EXTI_EXTICR1_EXTI3_Pos) |
| #define | EXTI_EXTICR1_EXTI3_2 (0x4UL << EXTI_EXTICR1_EXTI3_Pos) |
| #define | EXTI_EXTICR1_EXTI3_3 (0x8UL << EXTI_EXTICR1_EXTI3_Pos) |
| #define | EXTI_EXTICR2_EXTI4_Pos (0U) |
| #define | EXTI_EXTICR2_EXTI4_Msk (0xFUL << EXTI_EXTICR2_EXTI4_Pos) |
| #define | EXTI_EXTICR2_EXTI4 EXTI_EXTICR2_EXTI4_Msk |
| #define | EXTI_EXTICR2_EXTI4_0 (0x1UL << EXTI_EXTICR2_EXTI4_Pos) |
| #define | EXTI_EXTICR2_EXTI4_1 (0x2UL << EXTI_EXTICR2_EXTI4_Pos) |
| #define | EXTI_EXTICR2_EXTI4_2 (0x4UL << EXTI_EXTICR2_EXTI4_Pos) |
| #define | EXTI_EXTICR2_EXTI4_3 (0x8UL << EXTI_EXTICR2_EXTI4_Pos) |
| #define | EXTI_EXTICR2_EXTI5_Pos (8U) |
| #define | EXTI_EXTICR2_EXTI5_Msk (0xFUL << EXTI_EXTICR2_EXTI5_Pos) |
| #define | EXTI_EXTICR2_EXTI5 EXTI_EXTICR2_EXTI5_Msk |
| #define | EXTI_EXTICR2_EXTI5_0 (0x1UL << EXTI_EXTICR2_EXTI5_Pos) |
| #define | EXTI_EXTICR2_EXTI5_1 (0x2UL << EXTI_EXTICR2_EXTI5_Pos) |
| #define | EXTI_EXTICR2_EXTI5_2 (0x4UL << EXTI_EXTICR2_EXTI5_Pos) |
| #define | EXTI_EXTICR2_EXTI5_3 (0x8UL << EXTI_EXTICR2_EXTI5_Pos) |
| #define | EXTI_EXTICR2_EXTI6_Pos (16U) |
| #define | EXTI_EXTICR2_EXTI6_Msk (0xFUL << EXTI_EXTICR2_EXTI6_Pos) |
| #define | EXTI_EXTICR2_EXTI6 EXTI_EXTICR2_EXTI6_Msk |
| #define | EXTI_EXTICR2_EXTI6_0 (0x1UL << EXTI_EXTICR2_EXTI6_Pos) |
| #define | EXTI_EXTICR2_EXTI6_1 (0x2UL << EXTI_EXTICR2_EXTI6_Pos) |
| #define | EXTI_EXTICR2_EXTI6_2 (0x4UL << EXTI_EXTICR2_EXTI6_Pos) |
| #define | EXTI_EXTICR2_EXTI6_3 (0x8UL << EXTI_EXTICR2_EXTI6_Pos) |
| #define | EXTI_EXTICR2_EXTI7_Pos (24U) |
| #define | EXTI_EXTICR2_EXTI7_Msk (0xFUL << EXTI_EXTICR2_EXTI7_Pos) |
| #define | EXTI_EXTICR2_EXTI7 EXTI_EXTICR2_EXTI7_Msk |
| #define | EXTI_EXTICR2_EXTI7_0 (0x1UL << EXTI_EXTICR2_EXTI7_Pos) |
| #define | EXTI_EXTICR2_EXTI7_1 (0x2UL << EXTI_EXTICR2_EXTI7_Pos) |
| #define | EXTI_EXTICR2_EXTI7_2 (0x4UL << EXTI_EXTICR2_EXTI7_Pos) |
| #define | EXTI_EXTICR2_EXTI7_3 (0x8UL << EXTI_EXTICR2_EXTI7_Pos) |
| #define | EXTI_EXTICR3_EXTI8_Pos (0U) |
| #define | EXTI_EXTICR3_EXTI8_Msk (0xFUL << EXTI_EXTICR3_EXTI8_Pos) |
| #define | EXTI_EXTICR3_EXTI8 EXTI_EXTICR3_EXTI8_Msk |
| #define | EXTI_EXTICR3_EXTI8_0 (0x1UL << EXTI_EXTICR3_EXTI8_Pos) |
| #define | EXTI_EXTICR3_EXTI8_1 (0x2UL << EXTI_EXTICR3_EXTI8_Pos) |
| #define | EXTI_EXTICR3_EXTI8_2 (0x4UL << EXTI_EXTICR3_EXTI8_Pos) |
| #define | EXTI_EXTICR3_EXTI8_3 (0x8UL << EXTI_EXTICR3_EXTI8_Pos) |
| #define | EXTI_EXTICR3_EXTI9_Pos (8U) |
| #define | EXTI_EXTICR3_EXTI9_Msk (0xFUL << EXTI_EXTICR3_EXTI9_Pos) |
| #define | EXTI_EXTICR3_EXTI9 EXTI_EXTICR3_EXTI9_Msk |
| #define | EXTI_EXTICR3_EXTI9_0 (0x1UL << EXTI_EXTICR3_EXTI9_Pos) |
| #define | EXTI_EXTICR3_EXTI9_1 (0x2UL << EXTI_EXTICR3_EXTI9_Pos) |
| #define | EXTI_EXTICR3_EXTI9_2 (0x4UL << EXTI_EXTICR3_EXTI9_Pos) |
| #define | EXTI_EXTICR3_EXTI9_3 (0x8UL << EXTI_EXTICR3_EXTI9_Pos) |
| #define | EXTI_EXTICR3_EXTI10_Pos (16U) |
| #define | EXTI_EXTICR3_EXTI10_Msk (0xFUL << EXTI_EXTICR3_EXTI10_Pos) |
| #define | EXTI_EXTICR3_EXTI10 EXTI_EXTICR3_EXTI10_Msk |
| #define | EXTI_EXTICR3_EXTI10_0 (0x1UL << EXTI_EXTICR3_EXTI10_Pos) |
| #define | EXTI_EXTICR3_EXTI10_1 (0x2UL << EXTI_EXTICR3_EXTI10_Pos) |
| #define | EXTI_EXTICR3_EXTI10_2 (0x4UL << EXTI_EXTICR3_EXTI10_Pos) |
| #define | EXTI_EXTICR3_EXTI10_3 (0x8UL << EXTI_EXTICR3_EXTI10_Pos) |
| #define | EXTI_EXTICR3_EXTI11_Pos (24U) |
| #define | EXTI_EXTICR3_EXTI11_Msk (0xFUL << EXTI_EXTICR3_EXTI11_Pos) |
| #define | EXTI_EXTICR3_EXTI11 EXTI_EXTICR3_EXTI11_Msk |
| #define | EXTI_EXTICR3_EXTI11_0 (0x1UL << EXTI_EXTICR3_EXTI11_Pos) |
| #define | EXTI_EXTICR3_EXTI11_1 (0x2UL << EXTI_EXTICR3_EXTI11_Pos) |
| #define | EXTI_EXTICR3_EXTI11_2 (0x4UL << EXTI_EXTICR3_EXTI11_Pos) |
| #define | EXTI_EXTICR3_EXTI11_3 (0x8UL << EXTI_EXTICR3_EXTI11_Pos) |
| #define | EXTI_EXTICR4_EXTI12_Pos (0U) |
| #define | EXTI_EXTICR4_EXTI12_Msk (0xFUL << EXTI_EXTICR4_EXTI12_Pos) |
| #define | EXTI_EXTICR4_EXTI12 EXTI_EXTICR4_EXTI12_Msk |
| #define | EXTI_EXTICR4_EXTI12_0 (0x1UL << EXTI_EXTICR4_EXTI12_Pos) |
| #define | EXTI_EXTICR4_EXTI12_1 (0x2UL << EXTI_EXTICR4_EXTI12_Pos) |
| #define | EXTI_EXTICR4_EXTI12_2 (0x4UL << EXTI_EXTICR4_EXTI12_Pos) |
| #define | EXTI_EXTICR4_EXTI12_3 (0x8UL << EXTI_EXTICR4_EXTI12_Pos) |
| #define | EXTI_EXTICR4_EXTI13_Pos (8U) |
| #define | EXTI_EXTICR4_EXTI13_Msk (0xFUL << EXTI_EXTICR4_EXTI13_Pos) |
| #define | EXTI_EXTICR4_EXTI13 EXTI_EXTICR4_EXTI13_Msk |
| #define | EXTI_EXTICR4_EXTI13_0 (0x1UL << EXTI_EXTICR4_EXTI13_Pos) |
| #define | EXTI_EXTICR4_EXTI13_1 (0x2UL << EXTI_EXTICR4_EXTI13_Pos) |
| #define | EXTI_EXTICR4_EXTI13_2 (0x4UL << EXTI_EXTICR4_EXTI13_Pos) |
| #define | EXTI_EXTICR4_EXTI13_3 (0x8UL << EXTI_EXTICR4_EXTI13_Pos) |
| #define | EXTI_EXTICR4_EXTI14_Pos (16U) |
| #define | EXTI_EXTICR4_EXTI14_Msk (0xFUL << EXTI_EXTICR4_EXTI14_Pos) |
| #define | EXTI_EXTICR4_EXTI14 EXTI_EXTICR4_EXTI14_Msk |
| #define | EXTI_EXTICR4_EXTI14_0 (0x1UL << EXTI_EXTICR4_EXTI14_Pos) |
| #define | EXTI_EXTICR4_EXTI14_1 (0x2UL << EXTI_EXTICR4_EXTI14_Pos) |
| #define | EXTI_EXTICR4_EXTI14_2 (0x4UL << EXTI_EXTICR4_EXTI14_Pos) |
| #define | EXTI_EXTICR4_EXTI14_3 (0x8UL << EXTI_EXTICR4_EXTI14_Pos) |
| #define | EXTI_EXTICR4_EXTI15_Pos (24U) |
| #define | EXTI_EXTICR4_EXTI15_Msk (0xFUL << EXTI_EXTICR4_EXTI15_Pos) |
| #define | EXTI_EXTICR4_EXTI15 EXTI_EXTICR4_EXTI15_Msk |
| #define | EXTI_EXTICR4_EXTI15_0 (0x1UL << EXTI_EXTICR4_EXTI15_Pos) |
| #define | EXTI_EXTICR4_EXTI15_1 (0x2UL << EXTI_EXTICR4_EXTI15_Pos) |
| #define | EXTI_EXTICR4_EXTI15_2 (0x4UL << EXTI_EXTICR4_EXTI15_Pos) |
| #define | EXTI_EXTICR4_EXTI15_3 (0x8UL << EXTI_EXTICR4_EXTI15_Pos) |
| #define | EXTI_LOCKR_LOCK_Pos (0U) |
| #define | EXTI_LOCKR_LOCK_Msk (0x1UL << EXTI_LOCKR_LOCK_Pos) |
| #define | EXTI_LOCKR_LOCK EXTI_LOCKR_LOCK_Msk |
| #define | EXTI_IMR1_IM0_Pos (0U) |
| #define | EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) |
| #define | EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk |
| #define | EXTI_IMR1_IM1_Pos (1U) |
| #define | EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) |
| #define | EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk |
| #define | EXTI_IMR1_IM2_Pos (2U) |
| #define | EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) |
| #define | EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk |
| #define | EXTI_IMR1_IM3_Pos (3U) |
| #define | EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) |
| #define | EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk |
| #define | EXTI_IMR1_IM4_Pos (4U) |
| #define | EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) |
| #define | EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk |
| #define | EXTI_IMR1_IM5_Pos (5U) |
| #define | EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) |
| #define | EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk |
| #define | EXTI_IMR1_IM6_Pos (6U) |
| #define | EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) |
| #define | EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk |
| #define | EXTI_IMR1_IM7_Pos (7U) |
| #define | EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) |
| #define | EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk |
| #define | EXTI_IMR1_IM8_Pos (8U) |
| #define | EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) |
| #define | EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk |
| #define | EXTI_IMR1_IM9_Pos (9U) |
| #define | EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) |
| #define | EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk |
| #define | EXTI_IMR1_IM10_Pos (10U) |
| #define | EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) |
| #define | EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk |
| #define | EXTI_IMR1_IM11_Pos (11U) |
| #define | EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) |
| #define | EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk |
| #define | EXTI_IMR1_IM12_Pos (12U) |
| #define | EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) |
| #define | EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk |
| #define | EXTI_IMR1_IM13_Pos (13U) |
| #define | EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) |
| #define | EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk |
| #define | EXTI_IMR1_IM14_Pos (14U) |
| #define | EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) |
| #define | EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk |
| #define | EXTI_IMR1_IM15_Pos (15U) |
| #define | EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) |
| #define | EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk |
| #define | EXTI_IMR1_IM16_Pos (16U) |
| #define | EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) |
| #define | EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk |
| #define | EXTI_IMR1_IM17_Pos (17U) |
| #define | EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) |
| #define | EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk |
| #define | EXTI_IMR1_IM18_Pos (18U) |
| #define | EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) |
| #define | EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk |
| #define | EXTI_IMR1_IM19_Pos (19U) |
| #define | EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) |
| #define | EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk |
| #define | EXTI_IMR1_IM20_Pos (20U) |
| #define | EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) |
| #define | EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk |
| #define | EXTI_IMR1_IM21_Pos (21U) |
| #define | EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) |
| #define | EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk |
| #define | EXTI_IMR1_IM22_Pos (22U) |
| #define | EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) |
| #define | EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk |
| #define | EXTI_IMR1_IM23_Pos (23U) |
| #define | EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) |
| #define | EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk |
| #define | EXTI_IMR1_IM24_Pos (24U) |
| #define | EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) |
| #define | EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk |
| #define | EXTI_IMR1_IM25_Pos (25U) |
| #define | EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) |
| #define | EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk |
| #define | EXTI_EMR1_EM0_Pos (0U) |
| #define | EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) |
| #define | EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk |
| #define | EXTI_EMR1_EM1_Pos (1U) |
| #define | EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) |
| #define | EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk |
| #define | EXTI_EMR1_EM2_Pos (2U) |
| #define | EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) |
| #define | EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk |
| #define | EXTI_EMR1_EM3_Pos (3U) |
| #define | EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) |
| #define | EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk |
| #define | EXTI_EMR1_EM4_Pos (4U) |
| #define | EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) |
| #define | EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk |
| #define | EXTI_EMR1_EM5_Pos (5U) |
| #define | EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) |
| #define | EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk |
| #define | EXTI_EMR1_EM6_Pos (6U) |
| #define | EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) |
| #define | EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk |
| #define | EXTI_EMR1_EM7_Pos (7U) |
| #define | EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) |
| #define | EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk |
| #define | EXTI_EMR1_EM8_Pos (8U) |
| #define | EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) |
| #define | EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk |
| #define | EXTI_EMR1_EM9_Pos (9U) |
| #define | EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) |
| #define | EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk |
| #define | EXTI_EMR1_EM10_Pos (10U) |
| #define | EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) |
| #define | EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk |
| #define | EXTI_EMR1_EM11_Pos (11U) |
| #define | EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) |
| #define | EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk |
| #define | EXTI_EMR1_EM12_Pos (12U) |
| #define | EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) |
| #define | EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk |
| #define | EXTI_EMR1_EM13_Pos (13U) |
| #define | EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) |
| #define | EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk |
| #define | EXTI_EMR1_EM14_Pos (14U) |
| #define | EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) |
| #define | EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk |
| #define | EXTI_EMR1_EM15_Pos (15U) |
| #define | EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) |
| #define | EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk |
| #define | EXTI_EMR1_EM16_Pos (16U) |
| #define | EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) |
| #define | EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk |
| #define | EXTI_EMR1_EM17_Pos (17U) |
| #define | EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) |
| #define | EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk |
| #define | EXTI_EMR1_EM18_Pos (18U) |
| #define | EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) |
| #define | EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk |
| #define | EXTI_EMR1_EM19_Pos (19U) |
| #define | EXTI_EMR1_EM19_Msk (0x1UL << EXTI_EMR1_EM19_Pos) |
| #define | EXTI_EMR1_EM19 EXTI_EMR1_EM19_Msk |
| #define | EXTI_EMR1_EM20_Pos (20U) |
| #define | EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) |
| #define | EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk |
| #define | EXTI_EMR1_EM21_Pos (21U) |
| #define | EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) |
| #define | EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk |
| #define | EXTI_EMR1_EM22_Pos (22U) |
| #define | EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) |
| #define | EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk |
| #define | EXTI_EMR1_EM23_Pos (23U) |
| #define | EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) |
| #define | EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk |
| #define | EXTI_EMR1_EM24_Pos (24U) |
| #define | EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) |
| #define | EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk |
| #define | EXTI_EMR1_EM25_Pos (25U) |
| #define | EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) |
| #define | EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk |
| #define | FDCAN_CREL_DAY_Pos (0U) |
| #define | FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) |
| #define | FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk |
| #define | FDCAN_CREL_MON_Pos (8U) |
| #define | FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) |
| #define | FDCAN_CREL_MON FDCAN_CREL_MON_Msk |
| #define | FDCAN_CREL_YEAR_Pos (16U) |
| #define | FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) |
| #define | FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk |
| #define | FDCAN_CREL_SUBSTEP_Pos (20U) |
| #define | FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) |
| #define | FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk |
| #define | FDCAN_CREL_STEP_Pos (24U) |
| #define | FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) |
| #define | FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk |
| #define | FDCAN_CREL_REL_Pos (28U) |
| #define | FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) |
| #define | FDCAN_CREL_REL FDCAN_CREL_REL_Msk |
| #define | FDCAN_ENDN_ETV_Pos (0U) |
| #define | FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) |
| #define | FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk |
| #define | FDCAN_DBTP_DSJW_Pos (0U) |
| #define | FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) |
| #define | FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk |
| #define | FDCAN_DBTP_DTSEG2_Pos (4U) |
| #define | FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) |
| #define | FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk |
| #define | FDCAN_DBTP_DTSEG1_Pos (8U) |
| #define | FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) |
| #define | FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk |
| #define | FDCAN_DBTP_DBRP_Pos (16U) |
| #define | FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) |
| #define | FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk |
| #define | FDCAN_DBTP_TDC_Pos (23U) |
| #define | FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) |
| #define | FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk |
| #define | FDCAN_TEST_LBCK_Pos (4U) |
| #define | FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) |
| #define | FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk |
| #define | FDCAN_TEST_TX_Pos (5U) |
| #define | FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) |
| #define | FDCAN_TEST_TX FDCAN_TEST_TX_Msk |
| #define | FDCAN_TEST_RX_Pos (7U) |
| #define | FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) |
| #define | FDCAN_TEST_RX FDCAN_TEST_RX_Msk |
| #define | FDCAN_RWD_WDC_Pos (0U) |
| #define | FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) |
| #define | FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk |
| #define | FDCAN_RWD_WDV_Pos (8U) |
| #define | FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) |
| #define | FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk |
| #define | FDCAN_CCCR_INIT_Pos (0U) |
| #define | FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) |
| #define | FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk |
| #define | FDCAN_CCCR_CCE_Pos (1U) |
| #define | FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) |
| #define | FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk |
| #define | FDCAN_CCCR_ASM_Pos (2U) |
| #define | FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) |
| #define | FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk |
| #define | FDCAN_CCCR_CSA_Pos (3U) |
| #define | FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) |
| #define | FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk |
| #define | FDCAN_CCCR_CSR_Pos (4U) |
| #define | FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) |
| #define | FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk |
| #define | FDCAN_CCCR_MON_Pos (5U) |
| #define | FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) |
| #define | FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk |
| #define | FDCAN_CCCR_DAR_Pos (6U) |
| #define | FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) |
| #define | FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk |
| #define | FDCAN_CCCR_TEST_Pos (7U) |
| #define | FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) |
| #define | FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk |
| #define | FDCAN_CCCR_FDOE_Pos (8U) |
| #define | FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) |
| #define | FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk |
| #define | FDCAN_CCCR_BRSE_Pos (9U) |
| #define | FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) |
| #define | FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk |
| #define | FDCAN_CCCR_PXHD_Pos (12U) |
| #define | FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) |
| #define | FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk |
| #define | FDCAN_CCCR_EFBI_Pos (13U) |
| #define | FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) |
| #define | FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk |
| #define | FDCAN_CCCR_TXP_Pos (14U) |
| #define | FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) |
| #define | FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk |
| #define | FDCAN_CCCR_NISO_Pos (15U) |
| #define | FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) |
| #define | FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk |
| #define | FDCAN_NBTP_NTSEG2_Pos (0U) |
| #define | FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) |
| #define | FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk |
| #define | FDCAN_NBTP_NTSEG1_Pos (8U) |
| #define | FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) |
| #define | FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk |
| #define | FDCAN_NBTP_NBRP_Pos (16U) |
| #define | FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) |
| #define | FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk |
| #define | FDCAN_NBTP_NSJW_Pos (25U) |
| #define | FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) |
| #define | FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk |
| #define | FDCAN_TSCC_TSS_Pos (0U) |
| #define | FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) |
| #define | FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk |
| #define | FDCAN_TSCC_TCP_Pos (16U) |
| #define | FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) |
| #define | FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk |
| #define | FDCAN_TSCV_TSC_Pos (0U) |
| #define | FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) |
| #define | FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk |
| #define | FDCAN_TOCC_ETOC_Pos (0U) |
| #define | FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) |
| #define | FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk |
| #define | FDCAN_TOCC_TOS_Pos (1U) |
| #define | FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) |
| #define | FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk |
| #define | FDCAN_TOCC_TOP_Pos (16U) |
| #define | FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) |
| #define | FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk |
| #define | FDCAN_TOCV_TOC_Pos (0U) |
| #define | FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) |
| #define | FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk |
| #define | FDCAN_ECR_TEC_Pos (0U) |
| #define | FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) |
| #define | FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk |
| #define | FDCAN_ECR_REC_Pos (8U) |
| #define | FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) |
| #define | FDCAN_ECR_REC FDCAN_ECR_REC_Msk |
| #define | FDCAN_ECR_RP_Pos (15U) |
| #define | FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) |
| #define | FDCAN_ECR_RP FDCAN_ECR_RP_Msk |
| #define | FDCAN_ECR_CEL_Pos (16U) |
| #define | FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) |
| #define | FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk |
| #define | FDCAN_PSR_LEC_Pos (0U) |
| #define | FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) |
| #define | FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk |
| #define | FDCAN_PSR_ACT_Pos (3U) |
| #define | FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) |
| #define | FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk |
| #define | FDCAN_PSR_EP_Pos (5U) |
| #define | FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) |
| #define | FDCAN_PSR_EP FDCAN_PSR_EP_Msk |
| #define | FDCAN_PSR_EW_Pos (6U) |
| #define | FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) |
| #define | FDCAN_PSR_EW FDCAN_PSR_EW_Msk |
| #define | FDCAN_PSR_BO_Pos (7U) |
| #define | FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) |
| #define | FDCAN_PSR_BO FDCAN_PSR_BO_Msk |
| #define | FDCAN_PSR_DLEC_Pos (8U) |
| #define | FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) |
| #define | FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk |
| #define | FDCAN_PSR_RESI_Pos (11U) |
| #define | FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) |
| #define | FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk |
| #define | FDCAN_PSR_RBRS_Pos (12U) |
| #define | FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) |
| #define | FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk |
| #define | FDCAN_PSR_REDL_Pos (13U) |
| #define | FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) |
| #define | FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk |
| #define | FDCAN_PSR_PXE_Pos (14U) |
| #define | FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) |
| #define | FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk |
| #define | FDCAN_PSR_TDCV_Pos (16U) |
| #define | FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) |
| #define | FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk |
| #define | FDCAN_TDCR_TDCF_Pos (0U) |
| #define | FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) |
| #define | FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk |
| #define | FDCAN_TDCR_TDCO_Pos (8U) |
| #define | FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) |
| #define | FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk |
| #define | FDCAN_IR_RF0N_Pos (0U) |
| #define | FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) |
| #define | FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk |
| #define | FDCAN_IR_RF0F_Pos (1U) |
| #define | FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) |
| #define | FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk |
| #define | FDCAN_IR_RF0L_Pos (2U) |
| #define | FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) |
| #define | FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk |
| #define | FDCAN_IR_RF1N_Pos (3U) |
| #define | FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) |
| #define | FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk |
| #define | FDCAN_IR_RF1F_Pos (4U) |
| #define | FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) |
| #define | FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk |
| #define | FDCAN_IR_RF1L_Pos (5U) |
| #define | FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) |
| #define | FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk |
| #define | FDCAN_IR_HPM_Pos (6U) |
| #define | FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) |
| #define | FDCAN_IR_HPM FDCAN_IR_HPM_Msk |
| #define | FDCAN_IR_TC_Pos (7U) |
| #define | FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) |
| #define | FDCAN_IR_TC FDCAN_IR_TC_Msk |
| #define | FDCAN_IR_TCF_Pos (8U) |
| #define | FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) |
| #define | FDCAN_IR_TCF FDCAN_IR_TCF_Msk |
| #define | FDCAN_IR_TFE_Pos (9U) |
| #define | FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) |
| #define | FDCAN_IR_TFE FDCAN_IR_TFE_Msk |
| #define | FDCAN_IR_TEFN_Pos (10U) |
| #define | FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) |
| #define | FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk |
| #define | FDCAN_IR_TEFF_Pos (11U) |
| #define | FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) |
| #define | FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk |
| #define | FDCAN_IR_TEFL_Pos (12U) |
| #define | FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) |
| #define | FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk |
| #define | FDCAN_IR_TSW_Pos (13U) |
| #define | FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) |
| #define | FDCAN_IR_TSW FDCAN_IR_TSW_Msk |
| #define | FDCAN_IR_MRAF_Pos (14U) |
| #define | FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) |
| #define | FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk |
| #define | FDCAN_IR_TOO_Pos (15U) |
| #define | FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) |
| #define | FDCAN_IR_TOO FDCAN_IR_TOO_Msk |
| #define | FDCAN_IR_ELO_Pos (16U) |
| #define | FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) |
| #define | FDCAN_IR_ELO FDCAN_IR_ELO_Msk |
| #define | FDCAN_IR_EP_Pos (17U) |
| #define | FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) |
| #define | FDCAN_IR_EP FDCAN_IR_EP_Msk |
| #define | FDCAN_IR_EW_Pos (18U) |
| #define | FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) |
| #define | FDCAN_IR_EW FDCAN_IR_EW_Msk |
| #define | FDCAN_IR_BO_Pos (19U) |
| #define | FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) |
| #define | FDCAN_IR_BO FDCAN_IR_BO_Msk |
| #define | FDCAN_IR_WDI_Pos (20U) |
| #define | FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) |
| #define | FDCAN_IR_WDI FDCAN_IR_WDI_Msk |
| #define | FDCAN_IR_PEA_Pos (21U) |
| #define | FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) |
| #define | FDCAN_IR_PEA FDCAN_IR_PEA_Msk |
| #define | FDCAN_IR_PED_Pos (22U) |
| #define | FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) |
| #define | FDCAN_IR_PED FDCAN_IR_PED_Msk |
| #define | FDCAN_IR_ARA_Pos (23U) |
| #define | FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) |
| #define | FDCAN_IR_ARA FDCAN_IR_ARA_Msk |
| #define | FDCAN_IE_RF0NE_Pos (0U) |
| #define | FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) |
| #define | FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk |
| #define | FDCAN_IE_RF0FE_Pos (1U) |
| #define | FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) |
| #define | FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk |
| #define | FDCAN_IE_RF0LE_Pos (2U) |
| #define | FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) |
| #define | FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk |
| #define | FDCAN_IE_RF1NE_Pos (3U) |
| #define | FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) |
| #define | FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk |
| #define | FDCAN_IE_RF1FE_Pos (4U) |
| #define | FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) |
| #define | FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk |
| #define | FDCAN_IE_RF1LE_Pos (5U) |
| #define | FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) |
| #define | FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk |
| #define | FDCAN_IE_HPME_Pos (6U) |
| #define | FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) |
| #define | FDCAN_IE_HPME FDCAN_IE_HPME_Msk |
| #define | FDCAN_IE_TCE_Pos (7U) |
| #define | FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) |
| #define | FDCAN_IE_TCE FDCAN_IE_TCE_Msk |
| #define | FDCAN_IE_TCFE_Pos (8U) |
| #define | FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) |
| #define | FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk |
| #define | FDCAN_IE_TFEE_Pos (9U) |
| #define | FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) |
| #define | FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk |
| #define | FDCAN_IE_TEFNE_Pos (10U) |
| #define | FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) |
| #define | FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk |
| #define | FDCAN_IE_TEFFE_Pos (11U) |
| #define | FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) |
| #define | FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk |
| #define | FDCAN_IE_TEFLE_Pos (12U) |
| #define | FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) |
| #define | FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk |
| #define | FDCAN_IE_TSWE_Pos (13U) |
| #define | FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) |
| #define | FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk |
| #define | FDCAN_IE_MRAFE_Pos (14U) |
| #define | FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) |
| #define | FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk |
| #define | FDCAN_IE_TOOE_Pos (15U) |
| #define | FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) |
| #define | FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk |
| #define | FDCAN_IE_ELOE_Pos (16U) |
| #define | FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) |
| #define | FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk |
| #define | FDCAN_IE_EPE_Pos (17U) |
| #define | FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) |
| #define | FDCAN_IE_EPE FDCAN_IE_EPE_Msk |
| #define | FDCAN_IE_EWE_Pos (18U) |
| #define | FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) |
| #define | FDCAN_IE_EWE FDCAN_IE_EWE_Msk |
| #define | FDCAN_IE_BOE_Pos (19U) |
| #define | FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) |
| #define | FDCAN_IE_BOE FDCAN_IE_BOE_Msk |
| #define | FDCAN_IE_WDIE_Pos (20U) |
| #define | FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) |
| #define | FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk |
| #define | FDCAN_IE_PEAE_Pos (21U) |
| #define | FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) |
| #define | FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk |
| #define | FDCAN_IE_PEDE_Pos (22U) |
| #define | FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) |
| #define | FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk |
| #define | FDCAN_IE_ARAE_Pos (23U) |
| #define | FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) |
| #define | FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk |
| #define | FDCAN_ILS_RXFIFO0_Pos (0U) |
| #define | FDCAN_ILS_RXFIFO0_Msk (0x1UL << FDCAN_ILS_RXFIFO0_Pos) |
| #define | FDCAN_ILS_RXFIFO0 FDCAN_ILS_RXFIFO0_Msk |
| #define | FDCAN_ILS_RXFIFO1_Pos (1U) |
| #define | FDCAN_ILS_RXFIFO1_Msk (0x1UL << FDCAN_ILS_RXFIFO1_Pos) |
| #define | FDCAN_ILS_RXFIFO1 FDCAN_ILS_RXFIFO1_Msk |
| #define | FDCAN_ILS_SMSG_Pos (2U) |
| #define | FDCAN_ILS_SMSG_Msk (0x1UL << FDCAN_ILS_SMSG_Pos) |
| #define | FDCAN_ILS_SMSG FDCAN_ILS_SMSG_Msk |
| #define | FDCAN_ILS_TFERR_Pos (3U) |
| #define | FDCAN_ILS_TFERR_Msk (0x1UL << FDCAN_ILS_TFERR_Pos) |
| #define | FDCAN_ILS_TFERR FDCAN_ILS_TFERR_Msk |
| #define | FDCAN_ILS_MISC_Pos (4U) |
| #define | FDCAN_ILS_MISC_Msk (0x1UL << FDCAN_ILS_MISC_Pos) |
| #define | FDCAN_ILS_MISC FDCAN_ILS_MISC_Msk |
| #define | FDCAN_ILS_BERR_Pos (5U) |
| #define | FDCAN_ILS_BERR_Msk (0x1UL << FDCAN_ILS_BERR_Pos) |
| #define | FDCAN_ILS_BERR FDCAN_ILS_BERR_Msk |
| #define | FDCAN_ILS_PERR_Pos (6U) |
| #define | FDCAN_ILS_PERR_Msk (0x1UL << FDCAN_ILS_PERR_Pos) |
| #define | FDCAN_ILS_PERR FDCAN_ILS_PERR_Msk |
| #define | FDCAN_ILE_EINT0_Pos (0U) |
| #define | FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) |
| #define | FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk |
| #define | FDCAN_ILE_EINT1_Pos (1U) |
| #define | FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) |
| #define | FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk |
| #define | FDCAN_RXGFC_RRFE_Pos (0U) |
| #define | FDCAN_RXGFC_RRFE_Msk (0x1UL << FDCAN_RXGFC_RRFE_Pos) |
| #define | FDCAN_RXGFC_RRFE FDCAN_RXGFC_RRFE_Msk |
| #define | FDCAN_RXGFC_RRFS_Pos (1U) |
| #define | FDCAN_RXGFC_RRFS_Msk (0x1UL << FDCAN_RXGFC_RRFS_Pos) |
| #define | FDCAN_RXGFC_RRFS FDCAN_RXGFC_RRFS_Msk |
| #define | FDCAN_RXGFC_ANFE_Pos (2U) |
| #define | FDCAN_RXGFC_ANFE_Msk (0x3UL << FDCAN_RXGFC_ANFE_Pos) |
| #define | FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk |
| #define | FDCAN_RXGFC_ANFS_Pos (4U) |
| #define | FDCAN_RXGFC_ANFS_Msk (0x3UL << FDCAN_RXGFC_ANFS_Pos) |
| #define | FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk |
| #define | FDCAN_RXGFC_F1OM_Pos (8U) |
| #define | FDCAN_RXGFC_F1OM_Msk (0x1UL << FDCAN_RXGFC_F1OM_Pos) |
| #define | FDCAN_RXGFC_F1OM FDCAN_RXGFC_F1OM_Msk |
| #define | FDCAN_RXGFC_F0OM_Pos (9U) |
| #define | FDCAN_RXGFC_F0OM_Msk (0x1UL << FDCAN_RXGFC_F0OM_Pos) |
| #define | FDCAN_RXGFC_F0OM FDCAN_RXGFC_F0OM_Msk |
| #define | FDCAN_RXGFC_LSS_Pos (16U) |
| #define | FDCAN_RXGFC_LSS_Msk (0x1FUL << FDCAN_RXGFC_LSS_Pos) |
| #define | FDCAN_RXGFC_LSS FDCAN_RXGFC_LSS_Msk |
| #define | FDCAN_RXGFC_LSE_Pos (24U) |
| #define | FDCAN_RXGFC_LSE_Msk (0xFUL << FDCAN_RXGFC_LSE_Pos) |
| #define | FDCAN_RXGFC_LSE FDCAN_RXGFC_LSE_Msk |
| #define | FDCAN_XIDAM_EIDM_Pos (0U) |
| #define | FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) |
| #define | FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk |
| #define | FDCAN_HPMS_BIDX_Pos (0U) |
| #define | FDCAN_HPMS_BIDX_Msk (0x7UL << FDCAN_HPMS_BIDX_Pos) |
| #define | FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk |
| #define | FDCAN_HPMS_MSI_Pos (6U) |
| #define | FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) |
| #define | FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk |
| #define | FDCAN_HPMS_FIDX_Pos (8U) |
| #define | FDCAN_HPMS_FIDX_Msk (0x1FUL << FDCAN_HPMS_FIDX_Pos) |
| #define | FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk |
| #define | FDCAN_HPMS_FLST_Pos (15U) |
| #define | FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) |
| #define | FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk |
| #define | FDCAN_RXF0S_F0FL_Pos (0U) |
| #define | FDCAN_RXF0S_F0FL_Msk (0xFUL << FDCAN_RXF0S_F0FL_Pos) |
| #define | FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk |
| #define | FDCAN_RXF0S_F0GI_Pos (8U) |
| #define | FDCAN_RXF0S_F0GI_Msk (0x3UL << FDCAN_RXF0S_F0GI_Pos) |
| #define | FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk |
| #define | FDCAN_RXF0S_F0PI_Pos (16U) |
| #define | FDCAN_RXF0S_F0PI_Msk (0x3UL << FDCAN_RXF0S_F0PI_Pos) |
| #define | FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk |
| #define | FDCAN_RXF0S_F0F_Pos (24U) |
| #define | FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) |
| #define | FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk |
| #define | FDCAN_RXF0S_RF0L_Pos (25U) |
| #define | FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) |
| #define | FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk |
| #define | FDCAN_RXF0A_F0AI_Pos (0U) |
| #define | FDCAN_RXF0A_F0AI_Msk (0x7UL << FDCAN_RXF0A_F0AI_Pos) |
| #define | FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk |
| #define | FDCAN_RXF1S_F1FL_Pos (0U) |
| #define | FDCAN_RXF1S_F1FL_Msk (0xFUL << FDCAN_RXF1S_F1FL_Pos) |
| #define | FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk |
| #define | FDCAN_RXF1S_F1GI_Pos (8U) |
| #define | FDCAN_RXF1S_F1GI_Msk (0x3UL << FDCAN_RXF1S_F1GI_Pos) |
| #define | FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk |
| #define | FDCAN_RXF1S_F1PI_Pos (16U) |
| #define | FDCAN_RXF1S_F1PI_Msk (0x3UL << FDCAN_RXF1S_F1PI_Pos) |
| #define | FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk |
| #define | FDCAN_RXF1S_F1F_Pos (24U) |
| #define | FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) |
| #define | FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk |
| #define | FDCAN_RXF1S_RF1L_Pos (25U) |
| #define | FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) |
| #define | FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk |
| #define | FDCAN_RXF1A_F1AI_Pos (0U) |
| #define | FDCAN_RXF1A_F1AI_Msk (0x7UL << FDCAN_RXF1A_F1AI_Pos) |
| #define | FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk |
| #define | FDCAN_TXBC_TFQM_Pos (24U) |
| #define | FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) |
| #define | FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk |
| #define | FDCAN_TXFQS_TFFL_Pos (0U) |
| #define | FDCAN_TXFQS_TFFL_Msk (0x7UL << FDCAN_TXFQS_TFFL_Pos) |
| #define | FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk |
| #define | FDCAN_TXFQS_TFGI_Pos (8U) |
| #define | FDCAN_TXFQS_TFGI_Msk (0x3UL << FDCAN_TXFQS_TFGI_Pos) |
| #define | FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk |
| #define | FDCAN_TXFQS_TFQPI_Pos (16U) |
| #define | FDCAN_TXFQS_TFQPI_Msk (0x3UL << FDCAN_TXFQS_TFQPI_Pos) |
| #define | FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk |
| #define | FDCAN_TXFQS_TFQF_Pos (21U) |
| #define | FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) |
| #define | FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk |
| #define | FDCAN_TXBRP_TRP_Pos (0U) |
| #define | FDCAN_TXBRP_TRP_Msk (0x7UL << FDCAN_TXBRP_TRP_Pos) |
| #define | FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk |
| #define | FDCAN_TXBAR_AR_Pos (0U) |
| #define | FDCAN_TXBAR_AR_Msk (0x7UL << FDCAN_TXBAR_AR_Pos) |
| #define | FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk |
| #define | FDCAN_TXBCR_CR_Pos (0U) |
| #define | FDCAN_TXBCR_CR_Msk (0x7UL << FDCAN_TXBCR_CR_Pos) |
| #define | FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk |
| #define | FDCAN_TXBTO_TO_Pos (0U) |
| #define | FDCAN_TXBTO_TO_Msk (0x7UL << FDCAN_TXBTO_TO_Pos) |
| #define | FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk |
| #define | FDCAN_TXBCF_CF_Pos (0U) |
| #define | FDCAN_TXBCF_CF_Msk (0x7UL << FDCAN_TXBCF_CF_Pos) |
| #define | FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk |
| #define | FDCAN_TXBTIE_TIE_Pos (0U) |
| #define | FDCAN_TXBTIE_TIE_Msk (0x7UL << FDCAN_TXBTIE_TIE_Pos) |
| #define | FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk |
| #define | FDCAN_TXBCIE_CFIE_Pos (0U) |
| #define | FDCAN_TXBCIE_CFIE_Msk (0x7UL << FDCAN_TXBCIE_CFIE_Pos) |
| #define | FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk |
| #define | FDCAN_TXEFS_EFFL_Pos (0U) |
| #define | FDCAN_TXEFS_EFFL_Msk (0x7UL << FDCAN_TXEFS_EFFL_Pos) |
| #define | FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk |
| #define | FDCAN_TXEFS_EFGI_Pos (8U) |
| #define | FDCAN_TXEFS_EFGI_Msk (0x3UL << FDCAN_TXEFS_EFGI_Pos) |
| #define | FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk |
| #define | FDCAN_TXEFS_EFPI_Pos (16U) |
| #define | FDCAN_TXEFS_EFPI_Msk (0x3UL << FDCAN_TXEFS_EFPI_Pos) |
| #define | FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk |
| #define | FDCAN_TXEFS_EFF_Pos (24U) |
| #define | FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) |
| #define | FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk |
| #define | FDCAN_TXEFS_TEFL_Pos (25U) |
| #define | FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) |
| #define | FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk |
| #define | FDCAN_TXEFA_EFAI_Pos (0U) |
| #define | FDCAN_TXEFA_EFAI_Msk (0x3UL << FDCAN_TXEFA_EFAI_Pos) |
| #define | FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk |
| #define | FDCAN_CKDIV_PDIV_Pos (0U) |
| #define | FDCAN_CKDIV_PDIV_Msk (0xFUL << FDCAN_CKDIV_PDIV_Pos) |
| #define | FDCAN_CKDIV_PDIV FDCAN_CKDIV_PDIV_Msk |
| #define | FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_0WS |
| #define | FLASH_SIZE_DEFAULT 0x400000U |
| #define | FLASH_BLOCKBASED_NB_REG (8U) |
| #define | FLASH_SIZE |
| #define | FLASH_BANK_SIZE (FLASH_SIZE >> 1U) |
| #define | FLASH_PAGE_SIZE 0x2000U /* 8 KB */ |
| #define | FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) |
| #define | FLASH_ACR_LATENCY_Pos (0U) |
| #define | FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) |
| #define | FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk |
| #define | FLASH_ACR_LATENCY_0WS (0x00000000U) |
| #define | FLASH_ACR_LATENCY_1WS (0x00000001U) |
| #define | FLASH_ACR_LATENCY_2WS (0x00000002U) |
| #define | FLASH_ACR_LATENCY_3WS (0x00000003U) |
| #define | FLASH_ACR_LATENCY_4WS (0x00000004U) |
| #define | FLASH_ACR_LATENCY_5WS (0x00000005U) |
| #define | FLASH_ACR_LATENCY_6WS (0x00000006U) |
| #define | FLASH_ACR_LATENCY_7WS (0x00000007U) |
| #define | FLASH_ACR_LATENCY_8WS (0x00000008U) |
| #define | FLASH_ACR_LATENCY_9WS (0x00000009U) |
| #define | FLASH_ACR_LATENCY_10WS (0x0000000AU) |
| #define | FLASH_ACR_LATENCY_11WS (0x0000000BU) |
| #define | FLASH_ACR_LATENCY_12WS (0x0000000CU) |
| #define | FLASH_ACR_LATENCY_13WS (0x0000000DU) |
| #define | FLASH_ACR_LATENCY_14WS (0x0000000EU) |
| #define | FLASH_ACR_LATENCY_15WS (0x0000000FU) |
| #define | FLASH_ACR_PRFTEN_Pos (8U) |
| #define | FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) |
| #define | FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk |
| #define | FLASH_ACR_LPM_Pos (11U) |
| #define | FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) |
| #define | FLASH_ACR_LPM FLASH_ACR_LPM_Msk |
| #define | FLASH_ACR_PDREQ1_Pos (12U) |
| #define | FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) |
| #define | FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk |
| #define | FLASH_ACR_PDREQ2_Pos (13U) |
| #define | FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) |
| #define | FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk |
| #define | FLASH_ACR_SLEEP_PD_Pos (14U) |
| #define | FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) |
| #define | FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk |
| #define | FLASH_NSSR_EOP_Pos (0U) |
| #define | FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) |
| #define | FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk |
| #define | FLASH_NSSR_OPERR_Pos (1U) |
| #define | FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) |
| #define | FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk |
| #define | FLASH_NSSR_PROGERR_Pos (3U) |
| #define | FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) |
| #define | FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk |
| #define | FLASH_NSSR_WRPERR_Pos (4U) |
| #define | FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) |
| #define | FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk |
| #define | FLASH_NSSR_PGAERR_Pos (5U) |
| #define | FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) |
| #define | FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk |
| #define | FLASH_NSSR_SIZERR_Pos (6U) |
| #define | FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) |
| #define | FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk |
| #define | FLASH_NSSR_PGSERR_Pos (7U) |
| #define | FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) |
| #define | FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk |
| #define | FLASH_NSSR_OPTWERR_Pos (13U) |
| #define | FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) |
| #define | FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk |
| #define | FLASH_NSSR_BSY_Pos (16U) |
| #define | FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) |
| #define | FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk |
| #define | FLASH_NSSR_WDW_Pos (17U) |
| #define | FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) |
| #define | FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk |
| #define | FLASH_NSSR_OEM1LOCK_Pos (18U) |
| #define | FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) |
| #define | FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk |
| #define | FLASH_NSSR_OEM2LOCK_Pos (19U) |
| #define | FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) |
| #define | FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk |
| #define | FLASH_NSSR_PD1_Pos (20U) |
| #define | FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) |
| #define | FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk |
| #define | FLASH_NSSR_PD2_Pos (21U) |
| #define | FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) |
| #define | FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk |
| #define | FLASH_SECSR_EOP_Pos (0U) |
| #define | FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) |
| #define | FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk |
| #define | FLASH_SECSR_OPERR_Pos (1U) |
| #define | FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) |
| #define | FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk |
| #define | FLASH_SECSR_PROGERR_Pos (3U) |
| #define | FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) |
| #define | FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk |
| #define | FLASH_SECSR_WRPERR_Pos (4U) |
| #define | FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) |
| #define | FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk |
| #define | FLASH_SECSR_PGAERR_Pos (5U) |
| #define | FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) |
| #define | FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk |
| #define | FLASH_SECSR_SIZERR_Pos (6U) |
| #define | FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) |
| #define | FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk |
| #define | FLASH_SECSR_PGSERR_Pos (7U) |
| #define | FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) |
| #define | FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk |
| #define | FLASH_SECSR_BSY_Pos (16U) |
| #define | FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) |
| #define | FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk |
| #define | FLASH_SECSR_WDW_Pos (17U) |
| #define | FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) |
| #define | FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk |
| #define | FLASH_NSCR_PG_Pos (0U) |
| #define | FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) |
| #define | FLASH_NSCR_PG FLASH_NSCR_PG_Msk |
| #define | FLASH_NSCR_PER_Pos (1U) |
| #define | FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) |
| #define | FLASH_NSCR_PER FLASH_NSCR_PER_Msk |
| #define | FLASH_NSCR_MER1_Pos (2U) |
| #define | FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) |
| #define | FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk |
| #define | FLASH_NSCR_PNB_Pos (3U) |
| #define | FLASH_NSCR_PNB_Msk (0xFFUL << FLASH_NSCR_PNB_Pos) |
| #define | FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk |
| #define | FLASH_NSCR_BKER_Pos (11U) |
| #define | FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) |
| #define | FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk |
| #define | FLASH_NSCR_BWR_Pos (14U) |
| #define | FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) |
| #define | FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk |
| #define | FLASH_NSCR_MER2_Pos (15U) |
| #define | FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) |
| #define | FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk |
| #define | FLASH_NSCR_STRT_Pos (16U) |
| #define | FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) |
| #define | FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk |
| #define | FLASH_NSCR_OPTSTRT_Pos (17U) |
| #define | FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) |
| #define | FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk |
| #define | FLASH_NSCR_EOPIE_Pos (24U) |
| #define | FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) |
| #define | FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk |
| #define | FLASH_NSCR_ERRIE_Pos (25U) |
| #define | FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) |
| #define | FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk |
| #define | FLASH_NSCR_OBL_LAUNCH_Pos (27U) |
| #define | FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) |
| #define | FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk |
| #define | FLASH_NSCR_OPTLOCK_Pos (30U) |
| #define | FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) |
| #define | FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk |
| #define | FLASH_NSCR_LOCK_Pos (31U) |
| #define | FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) |
| #define | FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk |
| #define | FLASH_SECCR_PG_Pos (0U) |
| #define | FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) |
| #define | FLASH_SECCR_PG FLASH_SECCR_PG_Msk |
| #define | FLASH_SECCR_PER_Pos (1U) |
| #define | FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) |
| #define | FLASH_SECCR_PER FLASH_SECCR_PER_Msk |
| #define | FLASH_SECCR_MER1_Pos (2U) |
| #define | FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) |
| #define | FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk |
| #define | FLASH_SECCR_PNB_Pos (3U) |
| #define | FLASH_SECCR_PNB_Msk (0xFFUL << FLASH_SECCR_PNB_Pos) |
| #define | FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk |
| #define | FLASH_SECCR_BKER_Pos (11U) |
| #define | FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) |
| #define | FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk |
| #define | FLASH_SECCR_BWR_Pos (14U) |
| #define | FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) |
| #define | FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk |
| #define | FLASH_SECCR_MER2_Pos (15U) |
| #define | FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) |
| #define | FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk |
| #define | FLASH_SECCR_STRT_Pos (16U) |
| #define | FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) |
| #define | FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk |
| #define | FLASH_SECCR_EOPIE_Pos (24U) |
| #define | FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) |
| #define | FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk |
| #define | FLASH_SECCR_ERRIE_Pos (25U) |
| #define | FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) |
| #define | FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk |
| #define | FLASH_SECCR_INV_Pos (29U) |
| #define | FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) |
| #define | FLASH_SECCR_INV FLASH_SECCR_INV_Msk |
| #define | FLASH_SECCR_LOCK_Pos (31U) |
| #define | FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) |
| #define | FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk |
| #define | FLASH_ECCR_ADDR_ECC_Pos (0U) |
| #define | FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) |
| #define | FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk |
| #define | FLASH_ECCR_BK_ECC_Pos (21U) |
| #define | FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) |
| #define | FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk |
| #define | FLASH_ECCR_SYSF_ECC_Pos (22U) |
| #define | FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) |
| #define | FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk |
| #define | FLASH_ECCR_ECCIE_Pos (24U) |
| #define | FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) |
| #define | FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk |
| #define | FLASH_ECCR_ECCC_Pos (30U) |
| #define | FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) |
| #define | FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk |
| #define | FLASH_ECCR_ECCD_Pos (31U) |
| #define | FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) |
| #define | FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk |
| #define | FLASH_OPSR_ADDR_OP_Pos (0U) |
| #define | FLASH_OPSR_ADDR_OP_Msk (0x1FFFFFUL << FLASH_OPSR_ADDR_OP_Pos) |
| #define | FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk |
| #define | FLASH_OPSR_BK_OP_Pos (21U) |
| #define | FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) |
| #define | FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk |
| #define | FLASH_OPSR_SYSF_OP_Pos (22U) |
| #define | FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) |
| #define | FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk |
| #define | FLASH_OPSR_CODE_OP_Pos (29U) |
| #define | FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) |
| #define | FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk |
| #define | FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) |
| #define | FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) |
| #define | FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) |
| #define | FLASH_OPTR_RDP_Pos (0U) |
| #define | FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) |
| #define | FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk |
| #define | FLASH_OPTR_BOR_LEV_Pos (8U) |
| #define | FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) |
| #define | FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk |
| #define | FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) |
| #define | FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) |
| #define | FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) |
| #define | FLASH_OPTR_nRST_STOP_Pos (12U) |
| #define | FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) |
| #define | FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk |
| #define | FLASH_OPTR_nRST_STDBY_Pos (13U) |
| #define | FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) |
| #define | FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk |
| #define | FLASH_OPTR_nRST_SHDW_Pos (14U) |
| #define | FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) |
| #define | FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk |
| #define | FLASH_OPTR_SRAM_RST_Pos (15U) |
| #define | FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) |
| #define | FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk |
| #define | FLASH_OPTR_IWDG_SW_Pos (16U) |
| #define | FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) |
| #define | FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk |
| #define | FLASH_OPTR_IWDG_STOP_Pos (17U) |
| #define | FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) |
| #define | FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk |
| #define | FLASH_OPTR_IWDG_STDBY_Pos (18U) |
| #define | FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) |
| #define | FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk |
| #define | FLASH_OPTR_WWDG_SW_Pos (19U) |
| #define | FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) |
| #define | FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk |
| #define | FLASH_OPTR_SWAP_BANK_Pos (20U) |
| #define | FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) |
| #define | FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk |
| #define | FLASH_OPTR_DUALBANK_Pos (21U) |
| #define | FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) |
| #define | FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk |
| #define | FLASH_OPTR_BKPRAM_ECC_Pos (22U) |
| #define | FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) |
| #define | FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk |
| #define | FLASH_OPTR_SRAM3_ECC_Pos (23U) |
| #define | FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) |
| #define | FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk |
| #define | FLASH_OPTR_SRAM2_ECC_Pos (24U) |
| #define | FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) |
| #define | FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk |
| #define | FLASH_OPTR_SRAM2_RST_Pos (25U) |
| #define | FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) |
| #define | FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk |
| #define | FLASH_OPTR_nSWBOOT0_Pos (26U) |
| #define | FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) |
| #define | FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk |
| #define | FLASH_OPTR_nBOOT0_Pos (27U) |
| #define | FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) |
| #define | FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk |
| #define | FLASH_OPTR_PA15_PUPEN_Pos (28U) |
| #define | FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) |
| #define | FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk |
| #define | FLASH_OPTR_IO_VDD_HSLV_Pos (29U) |
| #define | FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) |
| #define | FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk |
| #define | FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30U) |
| #define | FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) |
| #define | FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk |
| #define | FLASH_OPTR_TZEN_Pos (31U) |
| #define | FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) |
| #define | FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk |
| #define | FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U) |
| #define | FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) |
| #define | FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk |
| #define | FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U) |
| #define | FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) |
| #define | FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk |
| #define | FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U) |
| #define | FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) |
| #define | FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk |
| #define | FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U) |
| #define | FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) |
| #define | FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk |
| #define | FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0U) |
| #define | FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) |
| #define | FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk |
| #define | FLASH_SECWM1R1_SECWM1_PEND_Pos (16U) |
| #define | FLASH_SECWM1R1_SECWM1_PEND_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) |
| #define | FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk |
| #define | FLASH_SECWM1R2_HDP1_PEND_Pos (16U) |
| #define | FLASH_SECWM1R2_HDP1_PEND_Msk (0xFFUL << FLASH_SECWM1R2_HDP1_PEND_Pos) |
| #define | FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk |
| #define | FLASH_SECWM1R2_HDP1EN_Pos (31U) |
| #define | FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) |
| #define | FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk |
| #define | FLASH_WRP1AR_WRP1A_PSTRT_Pos (0U) |
| #define | FLASH_WRP1AR_WRP1A_PSTRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) |
| #define | FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk |
| #define | FLASH_WRP1AR_WRP1A_PEND_Pos (16U) |
| #define | FLASH_WRP1AR_WRP1A_PEND_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PEND_Pos) |
| #define | FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk |
| #define | FLASH_WRP1AR_UNLOCK_Pos (31U) |
| #define | FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) |
| #define | FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk |
| #define | FLASH_WRP1BR_WRP1B_PSTRT_Pos (0U) |
| #define | FLASH_WRP1BR_WRP1B_PSTRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) |
| #define | FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk |
| #define | FLASH_WRP1BR_WRP1B_PEND_Pos (16U) |
| #define | FLASH_WRP1BR_WRP1B_PEND_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PEND_Pos) |
| #define | FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk |
| #define | FLASH_WRP1BR_UNLOCK_Pos (31U) |
| #define | FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) |
| #define | FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk |
| #define | FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0U) |
| #define | FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) |
| #define | FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk |
| #define | FLASH_SECWM2R1_SECWM2_PEND_Pos (16U) |
| #define | FLASH_SECWM2R1_SECWM2_PEND_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) |
| #define | FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk |
| #define | FLASH_SECWM2R2_HDP2_PEND_Pos (16U) |
| #define | FLASH_SECWM2R2_HDP2_PEND_Msk (0xFFUL << FLASH_SECWM2R2_HDP2_PEND_Pos) |
| #define | FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk |
| #define | FLASH_SECWM2R2_HDP2EN_Pos (31U) |
| #define | FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) |
| #define | FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk |
| #define | FLASH_WRP2AR_WRP2A_PSTRT_Pos (0U) |
| #define | FLASH_WRP2AR_WRP2A_PSTRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) |
| #define | FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk |
| #define | FLASH_WRP2AR_WRP2A_PEND_Pos (16U) |
| #define | FLASH_WRP2AR_WRP2A_PEND_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PEND_Pos) |
| #define | FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk |
| #define | FLASH_WRP2AR_UNLOCK_Pos (31U) |
| #define | FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) |
| #define | FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk |
| #define | FLASH_WRP2BR_WRP2B_PSTRT_Pos (0U) |
| #define | FLASH_WRP2BR_WRP2B_PSTRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) |
| #define | FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk |
| #define | FLASH_WRP2BR_WRP2B_PEND_Pos (16U) |
| #define | FLASH_WRP2BR_WRP2B_PEND_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PEND_Pos) |
| #define | FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk |
| #define | FLASH_WRP2BR_UNLOCK_Pos (31U) |
| #define | FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) |
| #define | FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk |
| #define | FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0U) |
| #define | FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) |
| #define | FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk |
| #define | FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1U) |
| #define | FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) |
| #define | FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk |
| #define | FLASH_PRIVCFGR_SPRIV_Pos (0U) |
| #define | FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) |
| #define | FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk |
| #define | FLASH_PRIVCFGR_NSPRIV_Pos (1U) |
| #define | FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) |
| #define | FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk |
| #define | FMAC_X1BUFCFG_X1_BASE_Pos (0U) |
| #define | FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) |
| #define | FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk |
| #define | FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U) |
| #define | FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) |
| #define | FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk |
| #define | FMAC_X1BUFCFG_FULL_WM_Pos (24U) |
| #define | FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) |
| #define | FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk |
| #define | FMAC_X2BUFCFG_X2_BASE_Pos (0U) |
| #define | FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) |
| #define | FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk |
| #define | FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U) |
| #define | FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) |
| #define | FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk |
| #define | FMAC_YBUFCFG_Y_BASE_Pos (0U) |
| #define | FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) |
| #define | FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk |
| #define | FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U) |
| #define | FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) |
| #define | FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk |
| #define | FMAC_YBUFCFG_EMPTY_WM_Pos (24U) |
| #define | FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) |
| #define | FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk |
| #define | FMAC_PARAM_P_Pos (0U) |
| #define | FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) |
| #define | FMAC_PARAM_P FMAC_PARAM_P_Msk |
| #define | FMAC_PARAM_Q_Pos (8U) |
| #define | FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) |
| #define | FMAC_PARAM_Q FMAC_PARAM_Q_Msk |
| #define | FMAC_PARAM_R_Pos (16U) |
| #define | FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) |
| #define | FMAC_PARAM_R FMAC_PARAM_R_Msk |
| #define | FMAC_PARAM_FUNC_Pos (24U) |
| #define | FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) |
| #define | FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk |
| #define | FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) |
| #define | FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) |
| #define | FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) |
| #define | FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) |
| #define | FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) |
| #define | FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) |
| #define | FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) |
| #define | FMAC_PARAM_START_Pos (31U) |
| #define | FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) |
| #define | FMAC_PARAM_START FMAC_PARAM_START_Msk |
| #define | FMAC_CR_RIEN_Pos (0U) |
| #define | FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) |
| #define | FMAC_CR_RIEN FMAC_CR_RIEN_Msk |
| #define | FMAC_CR_WIEN_Pos (1U) |
| #define | FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) |
| #define | FMAC_CR_WIEN FMAC_CR_WIEN_Msk |
| #define | FMAC_CR_OVFLIEN_Pos (2U) |
| #define | FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) |
| #define | FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk |
| #define | FMAC_CR_UNFLIEN_Pos (3U) |
| #define | FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) |
| #define | FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk |
| #define | FMAC_CR_SATIEN_Pos (4U) |
| #define | FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) |
| #define | FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk |
| #define | FMAC_CR_DMAREN_Pos (8U) |
| #define | FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) |
| #define | FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk |
| #define | FMAC_CR_DMAWEN_Pos (9U) |
| #define | FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) |
| #define | FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk |
| #define | FMAC_CR_CLIPEN_Pos (15U) |
| #define | FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) |
| #define | FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk |
| #define | FMAC_CR_RESET_Pos (16U) |
| #define | FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) |
| #define | FMAC_CR_RESET FMAC_CR_RESET_Msk |
| #define | FMAC_SR_YEMPTY_Pos (0U) |
| #define | FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) |
| #define | FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk |
| #define | FMAC_SR_X1FULL_Pos (1U) |
| #define | FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) |
| #define | FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk |
| #define | FMAC_SR_OVFL_Pos (8U) |
| #define | FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) |
| #define | FMAC_SR_OVFL FMAC_SR_OVFL_Msk |
| #define | FMAC_SR_UNFL_Pos (9U) |
| #define | FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) |
| #define | FMAC_SR_UNFL FMAC_SR_UNFL_Msk |
| #define | FMAC_SR_SAT_Pos (10U) |
| #define | FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) |
| #define | FMAC_SR_SAT FMAC_SR_SAT_Msk |
| #define | FMAC_WDATA_WDATA_Pos (0U) |
| #define | FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) |
| #define | FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk |
| #define | FMAC_RDATA_RDATA_Pos (0U) |
| #define | FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) |
| #define | FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk |
| #define | FMC_BCR1_CCLKEN_Pos (20U) |
| #define | FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) |
| #define | FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk |
| #define | FMC_BCR1_WFDIS_Pos (21U) |
| #define | FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) |
| #define | FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk |
| #define | FMC_BCR1_FMCEN_Pos (31U) |
| #define | FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos) |
| #define | FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk |
| #define | FMC_BCRx_MBKEN_Pos (0U) |
| #define | FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) |
| #define | FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk |
| #define | FMC_BCRx_MUXEN_Pos (1U) |
| #define | FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) |
| #define | FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk |
| #define | FMC_BCRx_MTYP_Pos (2U) |
| #define | FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) |
| #define | FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk |
| #define | FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) |
| #define | FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) |
| #define | FMC_BCRx_MWID_Pos (4U) |
| #define | FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) |
| #define | FMC_BCRx_MWID FMC_BCRx_MWID_Msk |
| #define | FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) |
| #define | FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) |
| #define | FMC_BCRx_FACCEN_Pos (6U) |
| #define | FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) |
| #define | FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk |
| #define | FMC_BCRx_BURSTEN_Pos (8U) |
| #define | FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) |
| #define | FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk |
| #define | FMC_BCRx_WAITPOL_Pos (9U) |
| #define | FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) |
| #define | FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk |
| #define | FMC_BCRx_WAITCFG_Pos (11U) |
| #define | FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) |
| #define | FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk |
| #define | FMC_BCRx_WREN_Pos (12U) |
| #define | FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) |
| #define | FMC_BCRx_WREN FMC_BCRx_WREN_Msk |
| #define | FMC_BCRx_WAITEN_Pos (13U) |
| #define | FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) |
| #define | FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk |
| #define | FMC_BCRx_EXTMOD_Pos (14U) |
| #define | FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) |
| #define | FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk |
| #define | FMC_BCRx_ASYNCWAIT_Pos (15U) |
| #define | FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) |
| #define | FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk |
| #define | FMC_BCRx_CPSIZE_Pos (16U) |
| #define | FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) |
| #define | FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk |
| #define | FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) |
| #define | FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) |
| #define | FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) |
| #define | FMC_BCRx_CBURSTRW_Pos (19U) |
| #define | FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) |
| #define | FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk |
| #define | FMC_BCRx_NBLSET_Pos (22U) |
| #define | FMC_BCRx_NBLSET_Msk (0x3UL << FMC_BCRx_NBLSET_Pos) |
| #define | FMC_BCRx_NBLSET FMC_BCRx_NBLSET_Msk |
| #define | FMC_BCRx_NBLSET_0 (0x1UL << FMC_BCRx_NBLSET_Pos) |
| #define | FMC_BCRx_NBLSET_1 (0x2UL << FMC_BCRx_NBLSET_Pos) |
| #define | FMC_BTRx_ADDSET_Pos (0U) |
| #define | FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) |
| #define | FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk |
| #define | FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) |
| #define | FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) |
| #define | FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) |
| #define | FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) |
| #define | FMC_BTRx_ADDHLD_Pos (4U) |
| #define | FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) |
| #define | FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk |
| #define | FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) |
| #define | FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) |
| #define | FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) |
| #define | FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) |
| #define | FMC_BTRx_DATAST_Pos (8U) |
| #define | FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) |
| #define | FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk |
| #define | FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) |
| #define | FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) |
| #define | FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) |
| #define | FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) |
| #define | FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) |
| #define | FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) |
| #define | FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) |
| #define | FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) |
| #define | FMC_BTRx_BUSTURN_Pos (16U) |
| #define | FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) |
| #define | FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk |
| #define | FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) |
| #define | FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) |
| #define | FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) |
| #define | FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) |
| #define | FMC_BTRx_CLKDIV_Pos (20U) |
| #define | FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) |
| #define | FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk |
| #define | FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) |
| #define | FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) |
| #define | FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) |
| #define | FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) |
| #define | FMC_BTRx_DATLAT_Pos (24U) |
| #define | FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) |
| #define | FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk |
| #define | FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) |
| #define | FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) |
| #define | FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) |
| #define | FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) |
| #define | FMC_BTRx_ACCMOD_Pos (28U) |
| #define | FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) |
| #define | FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk |
| #define | FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) |
| #define | FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) |
| #define | FMC_BTRx_DATAHLD_Pos (30U) |
| #define | FMC_BTRx_DATAHLD_Msk (0x3UL << FMC_BTRx_DATAHLD_Pos) |
| #define | FMC_BTRx_DATAHLD FMC_BTRx_DATAHLD_Msk |
| #define | FMC_BTRx_DATAHLD_0 (0x1UL << FMC_BTRx_DATAHLD_Pos) |
| #define | FMC_BTRx_DATAHLD_1 (0x2UL << FMC_BTRx_DATAHLD_Pos) |
| #define | FMC_BWTRx_ADDSET_Pos (0U) |
| #define | FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) |
| #define | FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk |
| #define | FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) |
| #define | FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) |
| #define | FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) |
| #define | FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) |
| #define | FMC_BWTRx_ADDHLD_Pos (4U) |
| #define | FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) |
| #define | FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk |
| #define | FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) |
| #define | FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) |
| #define | FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) |
| #define | FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) |
| #define | FMC_BWTRx_DATAST_Pos (8U) |
| #define | FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) |
| #define | FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk |
| #define | FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) |
| #define | FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) |
| #define | FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) |
| #define | FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) |
| #define | FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) |
| #define | FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) |
| #define | FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) |
| #define | FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) |
| #define | FMC_BWTRx_BUSTURN_Pos (16U) |
| #define | FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) |
| #define | FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk |
| #define | FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) |
| #define | FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) |
| #define | FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) |
| #define | FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) |
| #define | FMC_BWTRx_ACCMOD_Pos (28U) |
| #define | FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) |
| #define | FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk |
| #define | FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) |
| #define | FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) |
| #define | FMC_BWTRx_DATAHLD_Pos (30U) |
| #define | FMC_BWTRx_DATAHLD_Msk (0x3UL << FMC_BWTRx_DATAHLD_Pos) |
| #define | FMC_BWTRx_DATAHLD FMC_BWTRx_DATAHLD_Msk |
| #define | FMC_BWTRx_DATAHLD_0 (0x1UL << FMC_BWTRx_DATAHLD_Pos) |
| #define | FMC_BWTRx_DATAHLD_1 (0x2UL << FMC_BWTRx_DATAHLD_Pos) |
| #define | FMC_PCSCNTR_CSCOUNT_Pos (0U) |
| #define | FMC_PCSCNTR_CSCOUNT_Msk (0xFFFFUL << FMC_PCSCNTR_CSCOUNT_Pos) |
| #define | FMC_PCSCNTR_CSCOUNT FMC_PCSCNTR_CSCOUNT_Msk |
| #define | FMC_PCSCNTR_CNTB1EN_Pos (16U) |
| #define | FMC_PCSCNTR_CNTB1EN_Msk (0x1UL << FMC_PCSCNTR_CNTB1EN_Pos) |
| #define | FMC_PCSCNTR_CNTB1EN FMC_PCSCNTR_CNTB1EN_Msk |
| #define | FMC_PCSCNTR_CNTB2EN_Pos (17U) |
| #define | FMC_PCSCNTR_CNTB2EN_Msk (0x1UL << FMC_PCSCNTR_CNTB2EN_Pos) |
| #define | FMC_PCSCNTR_CNTB2EN FMC_PCSCNTR_CNTB2EN_Msk |
| #define | FMC_PCSCNTR_CNTB3EN_Pos (18U) |
| #define | FMC_PCSCNTR_CNTB3EN_Msk (0x1UL << FMC_PCSCNTR_CNTB3EN_Pos) |
| #define | FMC_PCSCNTR_CNTB3EN FMC_PCSCNTR_CNTB3EN_Msk |
| #define | FMC_PCSCNTR_CNTB4EN_Pos (19U) |
| #define | FMC_PCSCNTR_CNTB4EN_Msk (0x1UL << FMC_PCSCNTR_CNTB4EN_Pos) |
| #define | FMC_PCSCNTR_CNTB4EN FMC_PCSCNTR_CNTB4EN_Msk |
| #define | FMC_PCR_PWAITEN_Pos (1U) |
| #define | FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) |
| #define | FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk |
| #define | FMC_PCR_PBKEN_Pos (2U) |
| #define | FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) |
| #define | FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk |
| #define | FMC_PCR_PTYP_Pos (3U) |
| #define | FMC_PCR_PTYP_Msk (0x1UL << FMC_PCR_PTYP_Pos) |
| #define | FMC_PCR_PTYP FMC_PCR_PTYP_Msk |
| #define | FMC_PCR_PWID_Pos (4U) |
| #define | FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) |
| #define | FMC_PCR_PWID FMC_PCR_PWID_Msk |
| #define | FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) |
| #define | FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) |
| #define | FMC_PCR_ECCEN_Pos (6U) |
| #define | FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) |
| #define | FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk |
| #define | FMC_PCR_TCLR_Pos (9U) |
| #define | FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) |
| #define | FMC_PCR_TCLR FMC_PCR_TCLR_Msk |
| #define | FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) |
| #define | FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) |
| #define | FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) |
| #define | FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) |
| #define | FMC_PCR_TAR_Pos (13U) |
| #define | FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) |
| #define | FMC_PCR_TAR FMC_PCR_TAR_Msk |
| #define | FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) |
| #define | FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) |
| #define | FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) |
| #define | FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) |
| #define | FMC_PCR_ECCPS_Pos (17U) |
| #define | FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) |
| #define | FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk |
| #define | FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) |
| #define | FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) |
| #define | FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) |
| #define | FMC_SR_IRS_Pos (0U) |
| #define | FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) |
| #define | FMC_SR_IRS FMC_SR_IRS_Msk |
| #define | FMC_SR_ILS_Pos (1U) |
| #define | FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) |
| #define | FMC_SR_ILS FMC_SR_ILS_Msk |
| #define | FMC_SR_IFS_Pos (2U) |
| #define | FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) |
| #define | FMC_SR_IFS FMC_SR_IFS_Msk |
| #define | FMC_SR_IREN_Pos (3U) |
| #define | FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) |
| #define | FMC_SR_IREN FMC_SR_IREN_Msk |
| #define | FMC_SR_ILEN_Pos (4U) |
| #define | FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) |
| #define | FMC_SR_ILEN FMC_SR_ILEN_Msk |
| #define | FMC_SR_IFEN_Pos (5U) |
| #define | FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) |
| #define | FMC_SR_IFEN FMC_SR_IFEN_Msk |
| #define | FMC_SR_FEMPT_Pos (6U) |
| #define | FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) |
| #define | FMC_SR_FEMPT FMC_SR_FEMPT_Msk |
| #define | FMC_PMEM_MEMSET_Pos (0U) |
| #define | FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) |
| #define | FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk |
| #define | FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) |
| #define | FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) |
| #define | FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) |
| #define | FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) |
| #define | FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) |
| #define | FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) |
| #define | FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) |
| #define | FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) |
| #define | FMC_PMEM_MEMWAIT_Pos (8U) |
| #define | FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) |
| #define | FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk |
| #define | FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) |
| #define | FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) |
| #define | FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) |
| #define | FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) |
| #define | FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) |
| #define | FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) |
| #define | FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) |
| #define | FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) |
| #define | FMC_PMEM_MEMHOLD_Pos (16U) |
| #define | FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) |
| #define | FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk |
| #define | FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) |
| #define | FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) |
| #define | FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) |
| #define | FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) |
| #define | FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) |
| #define | FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) |
| #define | FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) |
| #define | FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) |
| #define | FMC_PMEM_MEMHIZ_Pos (24U) |
| #define | FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) |
| #define | FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk |
| #define | FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) |
| #define | FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) |
| #define | FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) |
| #define | FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) |
| #define | FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) |
| #define | FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) |
| #define | FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) |
| #define | FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) |
| #define | FMC_PATT_ATTSET_Pos (0U) |
| #define | FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) |
| #define | FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk |
| #define | FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) |
| #define | FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) |
| #define | FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) |
| #define | FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) |
| #define | FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) |
| #define | FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) |
| #define | FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) |
| #define | FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) |
| #define | FMC_PATT_ATTWAIT_Pos (8U) |
| #define | FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) |
| #define | FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk |
| #define | FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) |
| #define | FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) |
| #define | FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) |
| #define | FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) |
| #define | FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) |
| #define | FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) |
| #define | FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) |
| #define | FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) |
| #define | FMC_PATT_ATTHOLD_Pos (16U) |
| #define | FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) |
| #define | FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk |
| #define | FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) |
| #define | FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) |
| #define | FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) |
| #define | FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) |
| #define | FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) |
| #define | FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) |
| #define | FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) |
| #define | FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) |
| #define | FMC_PATT_ATTHIZ_Pos (24U) |
| #define | FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) |
| #define | FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk |
| #define | FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) |
| #define | FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) |
| #define | FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) |
| #define | FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) |
| #define | FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) |
| #define | FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) |
| #define | FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) |
| #define | FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) |
| #define | FMC_ECCR3_ECC3_Pos (0U) |
| #define | FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos) |
| #define | FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk |
| #define | GFXMMU_CR_B0OIE_Pos (0U) |
| #define | GFXMMU_CR_B0OIE_Msk (0x1UL << GFXMMU_CR_B0OIE_Pos) |
| #define | GFXMMU_CR_B0OIE GFXMMU_CR_B0OIE_Msk |
| #define | GFXMMU_CR_B1OIE_Pos (1U) |
| #define | GFXMMU_CR_B1OIE_Msk (0x1UL << GFXMMU_CR_B1OIE_Pos) |
| #define | GFXMMU_CR_B1OIE GFXMMU_CR_B1OIE_Msk |
| #define | GFXMMU_CR_B2OIE_Pos (2U) |
| #define | GFXMMU_CR_B2OIE_Msk (0x1UL << GFXMMU_CR_B2OIE_Pos) |
| #define | GFXMMU_CR_B2OIE GFXMMU_CR_B2OIE_Msk |
| #define | GFXMMU_CR_B3OIE_Pos (3U) |
| #define | GFXMMU_CR_B3OIE_Msk (0x1UL << GFXMMU_CR_B3OIE_Pos) |
| #define | GFXMMU_CR_B3OIE GFXMMU_CR_B3OIE_Msk |
| #define | GFXMMU_CR_AMEIE_Pos (4U) |
| #define | GFXMMU_CR_AMEIE_Msk (0x1UL << GFXMMU_CR_AMEIE_Pos) |
| #define | GFXMMU_CR_AMEIE GFXMMU_CR_AMEIE_Msk |
| #define | GFXMMU_CR_192BM_Pos (6U) |
| #define | GFXMMU_CR_192BM_Msk (0x1UL << GFXMMU_CR_192BM_Pos) |
| #define | GFXMMU_CR_192BM GFXMMU_CR_192BM_Msk |
| #define | GFXMMU_CR_ACE_Pos (20U) |
| #define | GFXMMU_CR_ACE_Msk (0x1UL << GFXMMU_CR_ACE_Pos) |
| #define | GFXMMU_CR_ACE GFXMMU_CR_ACE_Msk |
| #define | GFXMMU_CR_ACLB_Pos (21U) |
| #define | GFXMMU_CR_ACLB_Msk (0x3UL << GFXMMU_CR_ACLB_Pos) |
| #define | GFXMMU_CR_ACLB GFXMMU_CR_ACLB_Msk |
| #define | GFXMMU_CR_ACLB_0 (0x1UL << GFXMMU_CR_ACLB_Pos) |
| #define | GFXMMU_CR_ACLB_1 (0x2UL << GFXMMU_CR_ACLB_Pos) |
| #define | GFXMMU_SR_B0OF_Pos (0U) |
| #define | GFXMMU_SR_B0OF_Msk (0x1UL << GFXMMU_SR_B0OF_Pos) |
| #define | GFXMMU_SR_B0OF GFXMMU_SR_B0OF_Msk |
| #define | GFXMMU_SR_B1OF_Pos (1U) |
| #define | GFXMMU_SR_B1OF_Msk (0x1UL << GFXMMU_SR_B1OF_Pos) |
| #define | GFXMMU_SR_B1OF GFXMMU_SR_B1OF_Msk |
| #define | GFXMMU_SR_B2OF_Pos (2U) |
| #define | GFXMMU_SR_B2OF_Msk (0x1UL << GFXMMU_SR_B2OF_Pos) |
| #define | GFXMMU_SR_B2OF GFXMMU_SR_B2OF_Msk |
| #define | GFXMMU_SR_B3OF_Pos (3U) |
| #define | GFXMMU_SR_B3OF_Msk (0x1UL << GFXMMU_SR_B3OF_Pos) |
| #define | GFXMMU_SR_B3OF GFXMMU_SR_B3OF_Msk |
| #define | GFXMMU_SR_AMEF_Pos (4U) |
| #define | GFXMMU_SR_AMEF_Msk (0x1UL << GFXMMU_SR_AMEF_Pos) |
| #define | GFXMMU_SR_AMEF GFXMMU_SR_AMEF_Msk |
| #define | GFXMMU_FCR_CB0OF_Pos (0U) |
| #define | GFXMMU_FCR_CB0OF_Msk (0x1UL << GFXMMU_FCR_CB0OF_Pos) |
| #define | GFXMMU_FCR_CB0OF GFXMMU_FCR_CB0OF_Msk |
| #define | GFXMMU_FCR_CB1OF_Pos (1U) |
| #define | GFXMMU_FCR_CB1OF_Msk (0x1UL << GFXMMU_FCR_CB1OF_Pos) |
| #define | GFXMMU_FCR_CB1OF GFXMMU_FCR_CB1OF_Msk |
| #define | GFXMMU_FCR_CB2OF_Pos (2U) |
| #define | GFXMMU_FCR_CB2OF_Msk (0x1UL << GFXMMU_FCR_CB2OF_Pos) |
| #define | GFXMMU_FCR_CB2OF GFXMMU_FCR_CB2OF_Msk |
| #define | GFXMMU_FCR_CB3OF_Pos (3U) |
| #define | GFXMMU_FCR_CB3OF_Msk (0x1UL << GFXMMU_FCR_CB3OF_Pos) |
| #define | GFXMMU_FCR_CB3OF GFXMMU_FCR_CB3OF_Msk |
| #define | GFXMMU_FCR_CAMEF_Pos (4U) |
| #define | GFXMMU_FCR_CAMEF_Msk (0x1UL << GFXMMU_FCR_CAMEF_Pos) |
| #define | GFXMMU_FCR_CAMEF GFXMMU_FCR_CAMEF_Msk |
| #define | GFXMMU_CCR_FF_Pos (0U) |
| #define | GFXMMU_CCR_FF_Msk (0x1UL << GFXMMU_CCR_FF_Pos) |
| #define | GFXMMU_CCR_FF GFXMMU_CCR_FF_Msk |
| #define | GFXMMU_CCR_FI_Pos (1U) |
| #define | GFXMMU_CCR_FI_Msk (0x1UL << GFXMMU_CCR_FI_Pos) |
| #define | GFXMMU_CCR_FI GFXMMU_CCR_FI_Msk |
| #define | GFXMMU_DVR_DV_Pos (0U) |
| #define | GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) |
| #define | GFXMMU_DVR_DV GFXMMU_DVR_DV_Msk |
| #define | GFXMMU_B0CR_PBO_Pos (4U) |
| #define | GFXMMU_B0CR_PBO_Msk (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos) |
| #define | GFXMMU_B0CR_PBO GFXMMU_B0CR_PBO_Msk |
| #define | GFXMMU_B0CR_PBBA_Pos (23U) |
| #define | GFXMMU_B0CR_PBBA_Msk (0x1FFUL << GFXMMU_B0CR_PBBA_Pos) |
| #define | GFXMMU_B0CR_PBBA GFXMMU_B0CR_PBBA_Msk |
| #define | GFXMMU_B1CR_PBO_Pos (4U) |
| #define | GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) |
| #define | GFXMMU_B1CR_PBO GFXMMU_B1CR_PBO_Msk |
| #define | GFXMMU_B1CR_PBBA_Pos (23U) |
| #define | GFXMMU_B1CR_PBBA_Msk (0x1FFUL << GFXMMU_B1CR_PBBA_Pos) |
| #define | GFXMMU_B1CR_PBBA GFXMMU_B1CR_PBBA_Msk |
| #define | GFXMMU_B2CR_PBO_Pos (4U) |
| #define | GFXMMU_B2CR_PBO_Msk (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos) |
| #define | GFXMMU_B2CR_PBO GFXMMU_B2CR_PBO_Msk |
| #define | GFXMMU_B2CR_PBBA_Pos (23U) |
| #define | GFXMMU_B2CR_PBBA_Msk (0x1FFUL << GFXMMU_B2CR_PBBA_Pos) |
| #define | GFXMMU_B2CR_PBBA GFXMMU_B2CR_PBBA_Msk |
| #define | GFXMMU_B3CR_PBO_Pos (4U) |
| #define | GFXMMU_B3CR_PBO_Msk (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos) |
| #define | GFXMMU_B3CR_PBO GFXMMU_B3CR_PBO_Msk |
| #define | GFXMMU_B3CR_PBBA_Pos (23U) |
| #define | GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) |
| #define | GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk |
| #define | GFXMMU_LUTxL_EN_Pos (0U) |
| #define | GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) |
| #define | GFXMMU_LUTxL_EN GFXMMU_LUTxL_EN_Msk |
| #define | GFXMMU_LUTxL_FVB_Pos (8U) |
| #define | GFXMMU_LUTxL_FVB_Msk (0xFFUL << GFXMMU_LUTxL_FVB_Pos) |
| #define | GFXMMU_LUTxL_FVB GFXMMU_LUTxL_FVB_Msk |
| #define | GFXMMU_LUTxL_LVB_Pos (16U) |
| #define | GFXMMU_LUTxL_LVB_Msk (0xFFUL << GFXMMU_LUTxL_LVB_Pos) |
| #define | GFXMMU_LUTxL_LVB GFXMMU_LUTxL_LVB_Msk |
| #define | GFXMMU_LUTxH_LO_Pos (4U) |
| #define | GFXMMU_LUTxH_LO_Msk (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos) |
| #define | GFXMMU_LUTxH_LO GFXMMU_LUTxH_LO_Msk |
| #define | GFXTIM_CR_TES_Pos (0U) |
| #define | GFXTIM_CR_TES_Msk (0x3UL << GFXTIM_CR_TES_Pos) |
| #define | GFXTIM_CR_TES GFXTIM_CR_TES_Msk |
| #define | GFXTIM_CR_TES_0 (0x1UL << GFXTIM_CR_TES_Pos) |
| #define | GFXTIM_CR_TES_1 (0x2UL << GFXTIM_CR_TES_Pos) |
| #define | GFXTIM_CR_TEPOL_Pos (4U) |
| #define | GFXTIM_CR_TEPOL_Msk (0x1UL << GFXTIM_CR_TEPOL_Pos) |
| #define | GFXTIM_CR_TEPOL GFXTIM_CR_TEPOL_Msk |
| #define | GFXTIM_CR_SYNCS_Pos (8U) |
| #define | GFXTIM_CR_SYNCS_Msk (0x3UL << GFXTIM_CR_SYNCS_Pos) |
| #define | GFXTIM_CR_SYNCS GFXTIM_CR_SYNCS_Msk |
| #define | GFXTIM_CR_SYNCS_0 (0x1UL << GFXTIM_CR_SYNCS_Pos) |
| #define | GFXTIM_CR_SYNCS_1 (0x2UL << GFXTIM_CR_SYNCS_Pos) |
| #define | GFXTIM_CR_FCCOE_Pos (16U) |
| #define | GFXTIM_CR_FCCOE_Msk (0x1UL << GFXTIM_CR_FCCOE_Pos) |
| #define | GFXTIM_CR_FCCOE GFXTIM_CR_FCCOE_Msk |
| #define | GFXTIM_CR_LCCOE_Pos (17U) |
| #define | GFXTIM_CR_LCCOE_Msk (0x1UL << GFXTIM_CR_LCCOE_Pos) |
| #define | GFXTIM_CR_LCCOE GFXTIM_CR_LCCOE_Msk |
| #define | GFXTIM_CGCR_LCS_Pos (0U) |
| #define | GFXTIM_CGCR_LCS_Msk (0x7UL << GFXTIM_CGCR_LCS_Pos) |
| #define | GFXTIM_CGCR_LCS GFXTIM_CGCR_LCS_Msk |
| #define | GFXTIM_CGCR_LCS_0 (0x1UL << GFXTIM_CGCR_LCS_Pos) |
| #define | GFXTIM_CGCR_LCS_1 (0x2UL << GFXTIM_CGCR_LCS_Pos) |
| #define | GFXTIM_CGCR_LCS_2 (0x4UL << GFXTIM_CGCR_LCS_Pos) |
| #define | GFXTIM_CGCR_LCCCS_Pos (4U) |
| #define | GFXTIM_CGCR_LCCCS_Msk (0x1UL << GFXTIM_CGCR_LCCCS_Pos) |
| #define | GFXTIM_CGCR_LCCCS GFXTIM_CGCR_LCCCS_Msk |
| #define | GFXTIM_CGCR_LCCFR_Pos (8U) |
| #define | GFXTIM_CGCR_LCCFR_Msk (0x1UL << GFXTIM_CGCR_LCCFR_Pos) |
| #define | GFXTIM_CGCR_LCCFR GFXTIM_CGCR_LCCFR_Msk |
| #define | GFXTIM_CGCR_LCCHRS_Pos (12U) |
| #define | GFXTIM_CGCR_LCCHRS_Msk (0x7UL << GFXTIM_CGCR_LCCHRS_Pos) |
| #define | GFXTIM_CGCR_LCCHRS GFXTIM_CGCR_LCCHRS_Msk |
| #define | GFXTIM_CGCR_LCCHRS_0 (0x1UL << GFXTIM_CGCR_LCCHRS_Pos) |
| #define | GFXTIM_CGCR_LCCHRS_1 (0x2UL << GFXTIM_CGCR_LCCHRS_Pos) |
| #define | GFXTIM_CGCR_LCCHRS_2 (0x4UL << GFXTIM_CGCR_LCCHRS_Pos) |
| #define | GFXTIM_CGCR_FCS_Pos (16U) |
| #define | GFXTIM_CGCR_FCS_Msk (0x7UL << GFXTIM_CGCR_FCS_Pos) |
| #define | GFXTIM_CGCR_FCS GFXTIM_CGCR_FCS_Msk |
| #define | GFXTIM_CGCR_FCS_0 (0x1UL << GFXTIM_CGCR_FCS_Pos) |
| #define | GFXTIM_CGCR_FCS_1 (0x2UL << GFXTIM_CGCR_FCS_Pos) |
| #define | GFXTIM_CGCR_FCS_2 (0x4UL << GFXTIM_CGCR_FCS_Pos) |
| #define | GFXTIM_CGCR_FCCCS_Pos (20U) |
| #define | GFXTIM_CGCR_FCCCS_Msk (0x7UL << GFXTIM_CGCR_FCCCS_Pos) |
| #define | GFXTIM_CGCR_FCCCS GFXTIM_CGCR_FCCCS_Msk |
| #define | GFXTIM_CGCR_FCCCS_0 (0x1UL << GFXTIM_CGCR_FCCCS_Pos) |
| #define | GFXTIM_CGCR_FCCCS_1 (0x2UL << GFXTIM_CGCR_FCCCS_Pos) |
| #define | GFXTIM_CGCR_FCCCS_2 (0x4UL << GFXTIM_CGCR_FCCCS_Pos) |
| #define | GFXTIM_CGCR_FCCFR_Pos (24U) |
| #define | GFXTIM_CGCR_FCCFR_Msk (0x1UL << GFXTIM_CGCR_FCCFR_Pos) |
| #define | GFXTIM_CGCR_FCCFR GFXTIM_CGCR_FCCFR_Msk |
| #define | GFXTIM_CGCR_FCCHRS_Pos (28U) |
| #define | GFXTIM_CGCR_FCCHRS_Msk (0x7UL << GFXTIM_CGCR_FCCHRS_Pos) |
| #define | GFXTIM_CGCR_FCCHRS GFXTIM_CGCR_FCCHRS_Msk |
| #define | GFXTIM_CGCR_FCCHRS_0 (0x1UL << GFXTIM_CGCR_FCCHRS_Pos) |
| #define | GFXTIM_CGCR_FCCHRS_1 (0x2UL << GFXTIM_CGCR_FCCHRS_Pos) |
| #define | GFXTIM_CGCR_FCCHRS_2 (0x4UL << GFXTIM_CGCR_FCCHRS_Pos) |
| #define | GFXTIM_TCR_AFCEN_Pos (0U) |
| #define | GFXTIM_TCR_AFCEN_Msk (0x1UL << GFXTIM_TCR_AFCEN_Pos) |
| #define | GFXTIM_TCR_AFCEN GFXTIM_TCR_AFCEN_Msk |
| #define | GFXTIM_TCR_FAFCR_Pos (1U) |
| #define | GFXTIM_TCR_FAFCR_Msk (0x1UL << GFXTIM_TCR_FAFCR_Pos) |
| #define | GFXTIM_TCR_FAFCR GFXTIM_TCR_FAFCR_Msk |
| #define | GFXTIM_TCR_ALCEN_Pos (4U) |
| #define | GFXTIM_TCR_ALCEN_Msk (0x1UL << GFXTIM_TCR_ALCEN_Pos) |
| #define | GFXTIM_TCR_ALCEN GFXTIM_TCR_ALCEN_Msk |
| #define | GFXTIM_TCR_FALCR_Pos (5U) |
| #define | GFXTIM_TCR_FALCR_Msk (0x1UL << GFXTIM_TCR_FALCR_Pos) |
| #define | GFXTIM_TCR_FALCR GFXTIM_TCR_FALCR_Msk |
| #define | GFXTIM_TCR_RFC1EN_Pos (16U) |
| #define | GFXTIM_TCR_RFC1EN_Msk (0x1UL << GFXTIM_TCR_RFC1EN_Pos) |
| #define | GFXTIM_TCR_RFC1EN GFXTIM_TCR_RFC1EN_Msk |
| #define | GFXTIM_TCR_RFC1CM_Pos (17U) |
| #define | GFXTIM_TCR_RFC1CM_Msk (0x1UL << GFXTIM_TCR_RFC1CM_Pos) |
| #define | GFXTIM_TCR_RFC1CM GFXTIM_TCR_RFC1CM_Msk |
| #define | GFXTIM_TCR_FRFC1R_Pos (18U) |
| #define | GFXTIM_TCR_FRFC1R_Msk (0x1UL << GFXTIM_TCR_FRFC1R_Pos) |
| #define | GFXTIM_TCR_FRFC1R GFXTIM_TCR_FRFC1R_Msk |
| #define | GFXTIM_TCR_RFC2EN_Pos (20U) |
| #define | GFXTIM_TCR_RFC2EN_Msk (0x1UL << GFXTIM_TCR_RFC2EN_Pos) |
| #define | GFXTIM_TCR_RFC2EN GFXTIM_TCR_RFC2EN_Msk |
| #define | GFXTIM_TCR_RFC2CM_Pos (21U) |
| #define | GFXTIM_TCR_RFC2CM_Msk (0x1UL << GFXTIM_TCR_RFC2CM_Pos) |
| #define | GFXTIM_TCR_RFC2CM GFXTIM_TCR_RFC2CM_Msk |
| #define | GFXTIM_TCR_FRFC2R_Pos (22U) |
| #define | GFXTIM_TCR_FRFC2R_Msk (0x1UL << GFXTIM_TCR_FRFC2R_Pos) |
| #define | GFXTIM_TCR_FRFC2R GFXTIM_TCR_FRFC2R_Msk |
| #define | GFXTIM_TDR_AFCDIS_Pos (0U) |
| #define | GFXTIM_TDR_AFCDIS_Msk (0x1UL << GFXTIM_TDR_AFCDIS_Pos) |
| #define | GFXTIM_TDR_AFCDIS GFXTIM_TDR_AFCDIS_Msk |
| #define | GFXTIM_TDR_ALCDIS_Pos (4U) |
| #define | GFXTIM_TDR_ALCDIS_Msk (0x1UL << GFXTIM_TDR_ALCDIS_Pos) |
| #define | GFXTIM_TDR_ALCDIS GFXTIM_TDR_ALCDIS_Msk |
| #define | GFXTIM_TDR_RFC1DIS_Pos (16U) |
| #define | GFXTIM_TDR_RFC1DIS_Msk (0x1UL << GFXTIM_TDR_RFC1DIS_Pos) |
| #define | GFXTIM_TDR_RFC1DIS GFXTIM_TDR_RFC1DIS_Msk |
| #define | GFXTIM_TDR_RFC2DIS_Pos (20U) |
| #define | GFXTIM_TDR_RFC2DIS_Msk (0x1UL << GFXTIM_TDR_RFC2DIS_Pos) |
| #define | GFXTIM_TDR_RFC2DIS GFXTIM_TDR_RFC2DIS_Msk |
| #define | GFXTIM_EVCR_EV1EN_Pos (0U) |
| #define | GFXTIM_EVCR_EV1EN_Msk (0x1UL << GFXTIM_EVCR_EV1EN_Pos) |
| #define | GFXTIM_EVCR_EV1EN GFXTIM_EVCR_EV1EN_Msk |
| #define | GFXTIM_EVCR_EV2EN_Pos (1U) |
| #define | GFXTIM_EVCR_EV2EN_Msk (0x1UL << GFXTIM_EVCR_EV2EN_Pos) |
| #define | GFXTIM_EVCR_EV2EN GFXTIM_EVCR_EV2EN_Msk |
| #define | GFXTIM_EVCR_EV3EN_Pos (2U) |
| #define | GFXTIM_EVCR_EV3EN_Msk (0x1UL << GFXTIM_EVCR_EV3EN_Pos) |
| #define | GFXTIM_EVCR_EV3EN GFXTIM_EVCR_EV3EN_Msk |
| #define | GFXTIM_EVCR_EV4EN_Pos (3U) |
| #define | GFXTIM_EVCR_EV4EN_Msk (0x1UL << GFXTIM_EVCR_EV4EN_Pos) |
| #define | GFXTIM_EVCR_EV4EN GFXTIM_EVCR_EV4EN_Msk |
| #define | GFXTIM_EVSR_LES1_Pos (0U) |
| #define | GFXTIM_EVSR_LES1_Msk (0x7UL << GFXTIM_EVSR_LES1_Pos) |
| #define | GFXTIM_EVSR_LES1 GFXTIM_EVSR_LES1_Msk |
| #define | GFXTIM_EVSR_LES1_0 (0x1UL << GFXTIM_EVSR_LES1_Pos) |
| #define | GFXTIM_EVSR_LES1_1 (0x2UL << GFXTIM_EVSR_LES1_Pos) |
| #define | GFXTIM_EVSR_LES1_2 (0x4UL << GFXTIM_EVSR_LES1_Pos) |
| #define | GFXTIM_EVSR_FES1_Pos (4U) |
| #define | GFXTIM_EVSR_FES1_Msk (0x7UL << GFXTIM_EVSR_FES1_Pos) |
| #define | GFXTIM_EVSR_FES1 GFXTIM_EVSR_FES1_Msk |
| #define | GFXTIM_EVSR_FES1_0 (0x1UL << GFXTIM_EVSR_FES1_Pos) |
| #define | GFXTIM_EVSR_FES1_1 (0x2UL << GFXTIM_EVSR_FES1_Pos) |
| #define | GFXTIM_EVSR_FES1_2 (0x4UL << GFXTIM_EVSR_FES1_Pos) |
| #define | GFXTIM_EVSR_LES2_Pos (8U) |
| #define | GFXTIM_EVSR_LES2_Msk (0x7UL << GFXTIM_EVSR_LES2_Pos) |
| #define | GFXTIM_EVSR_LES2 GFXTIM_EVSR_LES2_Msk |
| #define | GFXTIM_EVSR_LES2_0 (0x1UL << GFXTIM_EVSR_LES2_Pos) |
| #define | GFXTIM_EVSR_LES2_1 (0x2UL << GFXTIM_EVSR_LES2_Pos) |
| #define | GFXTIM_EVSR_LES2_2 (0x4UL << GFXTIM_EVSR_LES2_Pos) |
| #define | GFXTIM_EVSR_FES2_Pos (12U) |
| #define | GFXTIM_EVSR_FES2_Msk (0x7UL << GFXTIM_EVSR_FES2_Pos) |
| #define | GFXTIM_EVSR_FES2 GFXTIM_EVSR_FES2_Msk |
| #define | GFXTIM_EVSR_FES2_0 (0x1UL << GFXTIM_EVSR_FES2_Pos) |
| #define | GFXTIM_EVSR_FES2_1 (0x2UL << GFXTIM_EVSR_FES2_Pos) |
| #define | GFXTIM_EVSR_FES2_2 (0x4UL << GFXTIM_EVSR_FES2_Pos) |
| #define | GFXTIM_EVSR_LES3_Pos (16U) |
| #define | GFXTIM_EVSR_LES3_Msk (0x7UL << GFXTIM_EVSR_LES3_Pos) |
| #define | GFXTIM_EVSR_LES3 GFXTIM_EVSR_LES3_Msk |
| #define | GFXTIM_EVSR_LES3_0 (0x1UL << GFXTIM_EVSR_LES3_Pos) |
| #define | GFXTIM_EVSR_LES3_1 (0x2UL << GFXTIM_EVSR_LES3_Pos) |
| #define | GFXTIM_EVSR_LES3_2 (0x4UL << GFXTIM_EVSR_LES3_Pos) |
| #define | GFXTIM_EVSR_FES3_Pos (20U) |
| #define | GFXTIM_EVSR_FES3_Msk (0x7UL << GFXTIM_EVSR_FES3_Pos) |
| #define | GFXTIM_EVSR_FES3 GFXTIM_EVSR_FES3_Msk |
| #define | GFXTIM_EVSR_FES3_0 (0x1UL << GFXTIM_EVSR_FES3_Pos) |
| #define | GFXTIM_EVSR_FES3_1 (0x2UL << GFXTIM_EVSR_FES3_Pos) |
| #define | GFXTIM_EVSR_FES3_2 (0x4UL << GFXTIM_EVSR_FES3_Pos) |
| #define | GFXTIM_EVSR_LES4_Pos (24U) |
| #define | GFXTIM_EVSR_LES4_Msk (0x7UL << GFXTIM_EVSR_LES4_Pos) |
| #define | GFXTIM_EVSR_LES4 GFXTIM_EVSR_LES4_Msk |
| #define | GFXTIM_EVSR_LES4_0 (0x1UL << GFXTIM_EVSR_LES4_Pos) |
| #define | GFXTIM_EVSR_LES4_1 (0x2UL << GFXTIM_EVSR_LES4_Pos) |
| #define | GFXTIM_EVSR_LES4_2 (0x4UL << GFXTIM_EVSR_LES4_Pos) |
| #define | GFXTIM_EVSR_FES4_Pos (28U) |
| #define | GFXTIM_EVSR_FES4_Msk (0x7UL << GFXTIM_EVSR_FES4_Pos) |
| #define | GFXTIM_EVSR_FES4 GFXTIM_EVSR_FES4_Msk |
| #define | GFXTIM_EVSR_FES4_0 (0x1UL << GFXTIM_EVSR_FES4_Pos) |
| #define | GFXTIM_EVSR_FES4_1 (0x2UL << GFXTIM_EVSR_FES4_Pos) |
| #define | GFXTIM_EVSR_FES4_2 (0x4UL << GFXTIM_EVSR_FES4_Pos) |
| #define | GFXTIM_WDGTCR_WDGEN_Pos (0U) |
| #define | GFXTIM_WDGTCR_WDGEN_Msk (0x1UL << GFXTIM_WDGTCR_WDGEN_Pos) |
| #define | GFXTIM_WDGTCR_WDGEN GFXTIM_WDGTCR_WDGEN_Msk |
| #define | GFXTIM_WDGTCR_WDGDIS_Pos (1U) |
| #define | GFXTIM_WDGTCR_WDGDIS_Msk (0x1UL << GFXTIM_WDGTCR_WDGDIS_Pos) |
| #define | GFXTIM_WDGTCR_WDGDIS GFXTIM_WDGTCR_WDGDIS_Msk |
| #define | GFXTIM_WDGTCR_WDGS_Pos (2U) |
| #define | GFXTIM_WDGTCR_WDGS_Msk (0x1UL << GFXTIM_WDGTCR_WDGS_Pos) |
| #define | GFXTIM_WDGTCR_WDGS GFXTIM_WDGTCR_WDGS_Msk |
| #define | GFXTIM_WDGTCR_WDGHRC_Pos (4U) |
| #define | GFXTIM_WDGTCR_WDGHRC_Msk (0x3UL << GFXTIM_WDGTCR_WDGHRC_Pos) |
| #define | GFXTIM_WDGTCR_WDGHRC GFXTIM_WDGTCR_WDGHRC_Msk |
| #define | GFXTIM_WDGTCR_WDGHRC_0 (0x1UL << GFXTIM_WDGTCR_WDGHRC_Pos) |
| #define | GFXTIM_WDGTCR_WDGHRC_1 (0x2UL << GFXTIM_WDGTCR_WDGHRC_Pos) |
| #define | GFXTIM_WDGTCR_WDGCS_Pos (8U) |
| #define | GFXTIM_WDGTCR_WDGCS_Msk (0xFUL << GFXTIM_WDGTCR_WDGCS_Pos) |
| #define | GFXTIM_WDGTCR_WDGCS GFXTIM_WDGTCR_WDGCS_Msk |
| #define | GFXTIM_WDGTCR_WDGCS_0 (0x1UL << GFXTIM_WDGTCR_WDGCS_Pos) |
| #define | GFXTIM_WDGTCR_WDGCS_1 (0x2UL << GFXTIM_WDGTCR_WDGCS_Pos) |
| #define | GFXTIM_WDGTCR_WDGCS_2 (0x4UL << GFXTIM_WDGTCR_WDGCS_Pos) |
| #define | GFXTIM_WDGTCR_WDGCS_3 (0x8UL << GFXTIM_WDGTCR_WDGCS_Pos) |
| #define | GFXTIM_WDGTCR_FWDGR_Pos (16U) |
| #define | GFXTIM_WDGTCR_FWDGR_Msk (0x1UL << GFXTIM_WDGTCR_FWDGR_Pos) |
| #define | GFXTIM_WDGTCR_FWDGR GFXTIM_WDGTCR_FWDGR_Msk |
| #define | GFXTIM_ISR_AFCOF_Pos (0U) |
| #define | GFXTIM_ISR_AFCOF_Msk (0x1UL << GFXTIM_ISR_AFCOF_Pos) |
| #define | GFXTIM_ISR_AFCOF GFXTIM_ISR_AFCOF_Msk |
| #define | GFXTIM_ISR_ALCOF_Pos (1U) |
| #define | GFXTIM_ISR_ALCOF_Msk (0x1UL << GFXTIM_ISR_ALCOF_Pos) |
| #define | GFXTIM_ISR_ALCOF GFXTIM_ISR_ALCOF_Msk |
| #define | GFXTIM_ISR_TEF_Pos (2U) |
| #define | GFXTIM_ISR_TEF_Msk (0x1UL << GFXTIM_ISR_TEF_Pos) |
| #define | GFXTIM_ISR_TEF GFXTIM_ISR_TEF_Msk |
| #define | GFXTIM_ISR_AFCC1F_Pos (4U) |
| #define | GFXTIM_ISR_AFCC1F_Msk (0x1UL << GFXTIM_ISR_AFCC1F_Pos) |
| #define | GFXTIM_ISR_AFCC1F GFXTIM_ISR_AFCC1F_Msk |
| #define | GFXTIM_ISR_ALCC1F_Pos (8U) |
| #define | GFXTIM_ISR_ALCC1F_Msk (0x1UL << GFXTIM_ISR_ALCC1F_Pos) |
| #define | GFXTIM_ISR_ALCC1F GFXTIM_ISR_ALCC1F_Msk |
| #define | GFXTIM_ISR_ALCC2F_Pos (9U) |
| #define | GFXTIM_ISR_ALCC2F_Msk (0x1UL << GFXTIM_ISR_ALCC2F_Pos) |
| #define | GFXTIM_ISR_ALCC2F GFXTIM_ISR_ALCC2F_Msk |
| #define | GFXTIM_ISR_RFC1RF_Pos (12U) |
| #define | GFXTIM_ISR_RFC1RF_Msk (0x1UL << GFXTIM_ISR_RFC1RF_Pos) |
| #define | GFXTIM_ISR_RFC1RF GFXTIM_ISR_RFC1RF_Msk |
| #define | GFXTIM_ISR_RFC2RF_Pos (13U) |
| #define | GFXTIM_ISR_RFC2RF_Msk (0x1UL << GFXTIM_ISR_RFC2RF_Pos) |
| #define | GFXTIM_ISR_RFC2RF GFXTIM_ISR_RFC2RF_Msk |
| #define | GFXTIM_ISR_EV1F_Pos (16U) |
| #define | GFXTIM_ISR_EV1F_Msk (0x1UL << GFXTIM_ISR_EV1F_Pos) |
| #define | GFXTIM_ISR_EV1F GFXTIM_ISR_EV1F_Msk |
| #define | GFXTIM_ISR_EV2F_Pos (17U) |
| #define | GFXTIM_ISR_EV2F_Msk (0x1UL << GFXTIM_ISR_EV2F_Pos) |
| #define | GFXTIM_ISR_EV2F GFXTIM_ISR_EV2F_Msk |
| #define | GFXTIM_ISR_EV3F_Pos (18U) |
| #define | GFXTIM_ISR_EV3F_Msk (0x1UL << GFXTIM_ISR_EV3F_Pos) |
| #define | GFXTIM_ISR_EV3F GFXTIM_ISR_EV3F_Msk |
| #define | GFXTIM_ISR_EV4F_Pos (19U) |
| #define | GFXTIM_ISR_EV4F_Msk (0x1UL << GFXTIM_ISR_EV4F_Pos) |
| #define | GFXTIM_ISR_EV4F GFXTIM_ISR_EV4F_Msk |
| #define | GFXTIM_ISR_WDGAF_Pos (24U) |
| #define | GFXTIM_ISR_WDGAF_Msk (0x1UL << GFXTIM_ISR_WDGAF_Pos) |
| #define | GFXTIM_ISR_WDGAF GFXTIM_ISR_WDGAF_Msk |
| #define | GFXTIM_ISR_WDGPF_Pos (25U) |
| #define | GFXTIM_ISR_WDGPF_Msk (0x1UL << GFXTIM_ISR_WDGPF_Pos) |
| #define | GFXTIM_ISR_WDGPF GFXTIM_ISR_WDGPF_Msk |
| #define | GFXTIM_ICR_CAFCOF_Pos (0U) |
| #define | GFXTIM_ICR_CAFCOF_Msk (0x1UL << GFXTIM_ICR_CAFCOF_Pos) |
| #define | GFXTIM_ICR_CAFCOF GFXTIM_ICR_CAFCOF_Msk |
| #define | GFXTIM_ICR_CALCOF_Pos (1U) |
| #define | GFXTIM_ICR_CALCOF_Msk (0x1UL << GFXTIM_ICR_CALCOF_Pos) |
| #define | GFXTIM_ICR_CALCOF GFXTIM_ICR_CALCOF_Msk |
| #define | GFXTIM_ICR_CTEF_Pos (2U) |
| #define | GFXTIM_ICR_CTEF_Msk (0x1UL << GFXTIM_ICR_CTEF_Pos) |
| #define | GFXTIM_ICR_CTEF GFXTIM_ICR_CTEF_Msk |
| #define | GFXTIM_ICR_CAFCC1F_Pos (4U) |
| #define | GFXTIM_ICR_CAFCC1F_Msk (0x1UL << GFXTIM_ICR_CAFCC1F_Pos) |
| #define | GFXTIM_ICR_CAFCC1F GFXTIM_ICR_CAFCC1F_Msk |
| #define | GFXTIM_ICR_CALCC1F_Pos (8U) |
| #define | GFXTIM_ICR_CALCC1F_Msk (0x1UL << GFXTIM_ICR_CALCC1F_Pos) |
| #define | GFXTIM_ICR_CALCC1F GFXTIM_ICR_CALCC1F_Msk |
| #define | GFXTIM_ICR_CALCC2F_Pos (9U) |
| #define | GFXTIM_ICR_CALCC2F_Msk (0x1UL << GFXTIM_ICR_CALCC2F_Pos) |
| #define | GFXTIM_ICR_CALCC2F GFXTIM_ICR_CALCC2F_Msk |
| #define | GFXTIM_ICR_CRFC1RF_Pos (12U) |
| #define | GFXTIM_ICR_CRFC1RF_Msk (0x1UL << GFXTIM_ICR_CRFC1RF_Pos) |
| #define | GFXTIM_ICR_CRFC1RF GFXTIM_ICR_CRFC1RF_Msk |
| #define | GFXTIM_ICR_CRFC2RF_Pos (13U) |
| #define | GFXTIM_ICR_CRFC2RF_Msk (0x1UL << GFXTIM_ICR_CRFC2RF_Pos) |
| #define | GFXTIM_ICR_CRFC2RF GFXTIM_ICR_CRFC2RF_Msk |
| #define | GFXTIM_ICR_CEV1F_Pos (16U) |
| #define | GFXTIM_ICR_CEV1F_Msk (0x1UL << GFXTIM_ICR_CEV1F_Pos) |
| #define | GFXTIM_ICR_CEV1F GFXTIM_ICR_CEV1F_Msk |
| #define | GFXTIM_ICR_CEV2F_Pos (17U) |
| #define | GFXTIM_ICR_CEV2F_Msk (0x1UL << GFXTIM_ICR_CEV2F_Pos) |
| #define | GFXTIM_ICR_CEV2F GFXTIM_ICR_CEV2F_Msk |
| #define | GFXTIM_ICR_CEV3F_Pos (18U) |
| #define | GFXTIM_ICR_CEV3F_Msk (0x1UL << GFXTIM_ICR_CEV3F_Pos) |
| #define | GFXTIM_ICR_CEV3F GFXTIM_ICR_CEV3F_Msk |
| #define | GFXTIM_ICR_CEV4F_Pos (19U) |
| #define | GFXTIM_ICR_CEV4F_Msk (0x1UL << GFXTIM_ICR_CEV4F_Pos) |
| #define | GFXTIM_ICR_CEV4F GFXTIM_ICR_CEV4F_Msk |
| #define | GFXTIM_ICR_CWDGAF_Pos (24U) |
| #define | GFXTIM_ICR_CWDGAF_Msk (0x1UL << GFXTIM_ICR_CWDGAF_Pos) |
| #define | GFXTIM_ICR_CWDGAF GFXTIM_ICR_CWDGAF_Msk |
| #define | GFXTIM_ICR_CWDGPF_Pos (25U) |
| #define | GFXTIM_ICR_CWDGPF_Msk (0x1UL << GFXTIM_ICR_CWDGPF_Pos) |
| #define | GFXTIM_ICR_CWDGPF GFXTIM_ICR_CWDGPF_Msk |
| #define | GFXTIM_IER_AFCOIE_Pos (0U) |
| #define | GFXTIM_IER_AFCOIE_Msk (0x1UL << GFXTIM_IER_AFCOIE_Pos) |
| #define | GFXTIM_IER_AFCOIE GFXTIM_IER_AFCOIE_Msk |
| #define | GFXTIM_IER_ALCOIE_Pos (1U) |
| #define | GFXTIM_IER_ALCOIE_Msk (0x1UL << GFXTIM_IER_ALCOIE_Pos) |
| #define | GFXTIM_IER_ALCOIE GFXTIM_IER_ALCOIE_Msk |
| #define | GFXTIM_IER_TEIE_Pos (2U) |
| #define | GFXTIM_IER_TEIE_Msk (0x1UL << GFXTIM_IER_TEIE_Pos) |
| #define | GFXTIM_IER_TEIE GFXTIM_IER_TEIE_Msk |
| #define | GFXTIM_IER_AFCC1IE_Pos (4U) |
| #define | GFXTIM_IER_AFCC1IE_Msk (0x1UL << GFXTIM_IER_AFCC1IE_Pos) |
| #define | GFXTIM_IER_AFCC1IE GFXTIM_IER_AFCC1IE_Msk |
| #define | GFXTIM_IER_ALCC1IE_Pos (8U) |
| #define | GFXTIM_IER_ALCC1IE_Msk (0x1UL << GFXTIM_IER_ALCC1IE_Pos) |
| #define | GFXTIM_IER_ALCC1IE GFXTIM_IER_ALCC1IE_Msk |
| #define | GFXTIM_IER_ALCC2IE_Pos (9U) |
| #define | GFXTIM_IER_ALCC2IE_Msk (0x1UL << GFXTIM_IER_ALCC2IE_Pos) |
| #define | GFXTIM_IER_ALCC2IE GFXTIM_IER_ALCC2IE_Msk |
| #define | GFXTIM_IER_RFC1RIE_Pos (12U) |
| #define | GFXTIM_IER_RFC1RIE_Msk (0x1UL << GFXTIM_IER_RFC1RIE_Pos) |
| #define | GFXTIM_IER_RFC1RIE GFXTIM_IER_RFC1RIE_Msk |
| #define | GFXTIM_IER_RFC2RIE_Pos (13U) |
| #define | GFXTIM_IER_RFC2RIE_Msk (0x1UL << GFXTIM_IER_RFC2RIE_Pos) |
| #define | GFXTIM_IER_RFC2RIE GFXTIM_IER_RFC2RIE_Msk |
| #define | GFXTIM_IER_EV1IE_Pos (16U) |
| #define | GFXTIM_IER_EV1IE_Msk (0x1UL << GFXTIM_IER_EV1IE_Pos) |
| #define | GFXTIM_IER_EV1IE GFXTIM_IER_EV1IE_Msk |
| #define | GFXTIM_IER_EV2IE_Pos (17U) |
| #define | GFXTIM_IER_EV2IE_Msk (0x1UL << GFXTIM_IER_EV2IE_Pos) |
| #define | GFXTIM_IER_EV2IE GFXTIM_IER_EV2IE_Msk |
| #define | GFXTIM_IER_EV3IE_Pos (18U) |
| #define | GFXTIM_IER_EV3IE_Msk (0x1UL << GFXTIM_IER_EV3IE_Pos) |
| #define | GFXTIM_IER_EV3IE GFXTIM_IER_EV3IE_Msk |
| #define | GFXTIM_IER_EV4IE_Pos (19U) |
| #define | GFXTIM_IER_EV4IE_Msk (0x1UL << GFXTIM_IER_EV4IE_Pos) |
| #define | GFXTIM_IER_EV4IE GFXTIM_IER_EV4IE_Msk |
| #define | GFXTIM_IER_WDGAIE_Pos (24U) |
| #define | GFXTIM_IER_WDGAIE_Msk (0x1UL << GFXTIM_IER_WDGAIE_Pos) |
| #define | GFXTIM_IER_WDGAIE GFXTIM_IER_WDGAIE_Msk |
| #define | GFXTIM_IER_WDGPIE_Pos (25U) |
| #define | GFXTIM_IER_WDGPIE_Msk (0x1UL << GFXTIM_IER_WDGPIE_Pos) |
| #define | GFXTIM_IER_WDGPIE GFXTIM_IER_WDGPIE_Msk |
| #define | GFXTIM_TSR_AFCS_Pos (0U) |
| #define | GFXTIM_TSR_AFCS_Msk (0x1UL << GFXTIM_TSR_AFCS_Pos) |
| #define | GFXTIM_TSR_AFCS GFXTIM_TSR_AFCS_Msk |
| #define | GFXTIM_TSR_ALCS_Pos (4U) |
| #define | GFXTIM_TSR_ALCS_Msk (0x1UL << GFXTIM_TSR_ALCS_Pos) |
| #define | GFXTIM_TSR_ALCS GFXTIM_TSR_ALCS_Msk |
| #define | GFXTIM_TSR_RFC1S_Pos (16U) |
| #define | GFXTIM_TSR_RFC1S_Msk (0x1UL << GFXTIM_TSR_RFC1S_Pos) |
| #define | GFXTIM_TSR_RFC1S GFXTIM_TSR_RFC1S_Msk |
| #define | GFXTIM_TSR_RFC2S_Pos (20U) |
| #define | GFXTIM_TSR_RFC2S_Msk (0x1UL << GFXTIM_TSR_RFC2S_Pos) |
| #define | GFXTIM_TSR_RFC2S GFXTIM_TSR_RFC2S_Msk |
| #define | GFXTIM_LCCRR_RELOAD_Pos (0U) |
| #define | GFXTIM_LCCRR_RELOAD_Msk (0x3FFFFFUL << GFXTIM_LCCRR_RELOAD_Pos) |
| #define | GFXTIM_LCCRR_RELOAD GFXTIM_LCCRR_RELOAD_Msk |
| #define | GFXTIM_FCCRR_RELOAD_Pos (0U) |
| #define | GFXTIM_FCCRR_RELOAD_Msk (0xFFFUL << GFXTIM_FCCRR_RELOAD_Pos) |
| #define | GFXTIM_FCCRR_RELOAD GFXTIM_FCCRR_RELOAD_Msk |
| #define | GFXTIM_ATR_LINE_Pos (0U) |
| #define | GFXTIM_ATR_LINE_Msk (0xFFFUL << GFXTIM_ATR_LINE_Pos) |
| #define | GFXTIM_ATR_LINE GFXTIM_ATR_LINE_Msk |
| #define | GFXTIM_ATR_FRAME_Pos (12U) |
| #define | GFXTIM_ATR_FRAME_Msk (0xFFFFFUL << GFXTIM_ATR_FRAME_Pos) |
| #define | GFXTIM_ATR_FRAME GFXTIM_ATR_FRAME_Msk |
| #define | GFXTIM_AFCR_FRAME_Pos (0U) |
| #define | GFXTIM_AFCR_FRAME_Msk (0xFFFFFUL << GFXTIM_AFCR_FRAME_Pos) |
| #define | GFXTIM_AFCR_FRAME GFXTIM_AFCR_FRAME_Msk |
| #define | GFXTIM_ALCR_LINE_Pos (0U) |
| #define | GFXTIM_ALCR_LINE_Msk (0xFFFUL << GFXTIM_ALCR_LINE_Pos) |
| #define | GFXTIM_ALCR_LINE GFXTIM_ALCR_LINE_Msk |
| #define | GFXTIM_AFCC1R_FRAME_Pos (0U) |
| #define | GFXTIM_AFCC1R_FRAME_Msk (0xFFFFFUL << GFXTIM_AFCC1R_FRAME_Pos) |
| #define | GFXTIM_AFCC1R_FRAME GFXTIM_AFCC1R_FRAME_Msk |
| #define | GFXTIM_ALCC1R_LINE_Pos (0U) |
| #define | GFXTIM_ALCC1R_LINE_Msk (0xFFFUL << GFXTIM_ALCC1R_LINE_Pos) |
| #define | GFXTIM_ALCC1R_LINE GFXTIM_ALCC1R_LINE_Msk |
| #define | GFXTIM_ALCC2R_LINE_Pos (0U) |
| #define | GFXTIM_ALCC2R_LINE_Msk (0xFFFUL << GFXTIM_ALCC2R_LINE_Pos) |
| #define | GFXTIM_ALCC2R_LINE GFXTIM_ALCC2R_LINE_Msk |
| #define | GFXTIM_RFC1R_FRAME_Pos (0U) |
| #define | GFXTIM_RFC1R_FRAME_Msk (0xFFFUL << GFXTIM_RFC1R_FRAME_Pos) |
| #define | GFXTIM_RFC1R_FRAME GFXTIM_RFC1R_FRAME_Msk |
| #define | GFXTIM_RFC1RR_FRAME_Pos (0U) |
| #define | GFXTIM_RFC1RR_FRAME_Msk (0xFFFUL << GFXTIM_RFC1RR_FRAME_Pos) |
| #define | GFXTIM_RFC1RR_FRAME GFXTIM_RFC1RR_FRAME_Msk |
| #define | GFXTIM_RFC2R_FRAME_Pos (0U) |
| #define | GFXTIM_RFC2R_FRAME_Msk (0xFFFUL << GFXTIM_RFC2R_FRAME_Pos) |
| #define | GFXTIM_RFC2R_FRAME GFXTIM_RFC2R_FRAME_Msk |
| #define | GFXTIM_RFC2RR_FRAME_Pos (0U) |
| #define | GFXTIM_RFC2RR_FRAME_Msk (0xFFFUL << GFXTIM_RFC2RR_FRAME_Pos) |
| #define | GFXTIM_RFC2RR_FRAME GFXTIM_RFC2RR_FRAME_Msk |
| #define | GFXTIM_WDGCR_VALUE_Pos (0U) |
| #define | GFXTIM_WDGCR_VALUE_Msk (0xFFFFUL << GFXTIM_WDGCR_VALUE_Pos) |
| #define | GFXTIM_WDGCR_VALUE GFXTIM_WDGCR_VALUE_Msk |
| #define | GFXTIM_WDGRR_RELOAD_Pos (0U) |
| #define | GFXTIM_WDGRR_RELOAD_Msk (0xFFFFUL << GFXTIM_WDGRR_RELOAD_Pos) |
| #define | GFXTIM_WDGRR_RELOAD GFXTIM_WDGRR_RELOAD_Msk |
| #define | GFXTIM_WDGPAR_PREALARM_Pos (0U) |
| #define | GFXTIM_WDGPAR_PREALARM_Msk (0xFFFFUL << GFXTIM_WDGPAR_PREALARM_Pos) |
| #define | GFXTIM_WDGPAR_PREALARM GFXTIM_WDGPAR_PREALARM_Msk |
| #define | GFXTIM_VERR_MINREV_Pos (0U) |
| #define | GFXTIM_VERR_MINREV_Msk (0xFUL << GFXTIM_VERR_MINREV_Pos) |
| #define | GFXTIM_VERR_MINREV GFXTIM_VERR_MINREV_Msk |
| #define | GFXTIM_VERR_MAJREV_Pos (4U) |
| #define | GFXTIM_VERR_MAJREV_Msk (0xFUL << GFXTIM_VERR_MAJREV_Pos) |
| #define | GFXTIM_VERR_MAJREV GFXTIM_VERR_MAJREV_Msk |
| #define | GFXTIM_IPIDR_ID_Pos (0U) |
| #define | GFXTIM_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXTIM_IPIDR_ID_Pos) |
| #define | GFXTIM_IPIDR_ID GFXTIM_IPIDR_ID_Msk |
| #define | GFXTIM_SIDR_SID_Pos (0U) |
| #define | GFXTIM_SIDR_SID_Msk (0xFFFFFFFFUL << GFXTIM_SIDR_SID_Pos) |
| #define | GFXTIM_SIDR_SID GFXTIM_SIDR_SID_Msk |
| #define | GPIO_MODER_MODE0_Pos (0U) |
| #define | GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) |
| #define | GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk |
| #define | GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) |
| #define | GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) |
| #define | GPIO_MODER_MODE1_Pos (2U) |
| #define | GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) |
| #define | GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk |
| #define | GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) |
| #define | GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) |
| #define | GPIO_MODER_MODE2_Pos (4U) |
| #define | GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) |
| #define | GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk |
| #define | GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) |
| #define | GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) |
| #define | GPIO_MODER_MODE3_Pos (6U) |
| #define | GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) |
| #define | GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk |
| #define | GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) |
| #define | GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) |
| #define | GPIO_MODER_MODE4_Pos (8U) |
| #define | GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) |
| #define | GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk |
| #define | GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) |
| #define | GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) |
| #define | GPIO_MODER_MODE5_Pos (10U) |
| #define | GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) |
| #define | GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk |
| #define | GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) |
| #define | GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) |
| #define | GPIO_MODER_MODE6_Pos (12U) |
| #define | GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) |
| #define | GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk |
| #define | GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) |
| #define | GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) |
| #define | GPIO_MODER_MODE7_Pos (14U) |
| #define | GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) |
| #define | GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk |
| #define | GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) |
| #define | GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) |
| #define | GPIO_MODER_MODE8_Pos (16U) |
| #define | GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) |
| #define | GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk |
| #define | GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) |
| #define | GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) |
| #define | GPIO_MODER_MODE9_Pos (18U) |
| #define | GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) |
| #define | GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk |
| #define | GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) |
| #define | GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) |
| #define | GPIO_MODER_MODE10_Pos (20U) |
| #define | GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) |
| #define | GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk |
| #define | GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) |
| #define | GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) |
| #define | GPIO_MODER_MODE11_Pos (22U) |
| #define | GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) |
| #define | GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk |
| #define | GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) |
| #define | GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) |
| #define | GPIO_MODER_MODE12_Pos (24U) |
| #define | GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) |
| #define | GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk |
| #define | GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) |
| #define | GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) |
| #define | GPIO_MODER_MODE13_Pos (26U) |
| #define | GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) |
| #define | GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk |
| #define | GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) |
| #define | GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) |
| #define | GPIO_MODER_MODE14_Pos (28U) |
| #define | GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) |
| #define | GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk |
| #define | GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) |
| #define | GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) |
| #define | GPIO_MODER_MODE15_Pos (30U) |
| #define | GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) |
| #define | GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk |
| #define | GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) |
| #define | GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) |
| #define | GPIO_OTYPER_OT0_Pos (0U) |
| #define | GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) |
| #define | GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk |
| #define | GPIO_OTYPER_OT1_Pos (1U) |
| #define | GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) |
| #define | GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk |
| #define | GPIO_OTYPER_OT2_Pos (2U) |
| #define | GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) |
| #define | GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk |
| #define | GPIO_OTYPER_OT3_Pos (3U) |
| #define | GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) |
| #define | GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk |
| #define | GPIO_OTYPER_OT4_Pos (4U) |
| #define | GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) |
| #define | GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk |
| #define | GPIO_OTYPER_OT5_Pos (5U) |
| #define | GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) |
| #define | GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk |
| #define | GPIO_OTYPER_OT6_Pos (6U) |
| #define | GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) |
| #define | GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk |
| #define | GPIO_OTYPER_OT7_Pos (7U) |
| #define | GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) |
| #define | GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk |
| #define | GPIO_OTYPER_OT8_Pos (8U) |
| #define | GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) |
| #define | GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk |
| #define | GPIO_OTYPER_OT9_Pos (9U) |
| #define | GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) |
| #define | GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk |
| #define | GPIO_OTYPER_OT10_Pos (10U) |
| #define | GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) |
| #define | GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk |
| #define | GPIO_OTYPER_OT11_Pos (11U) |
| #define | GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) |
| #define | GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk |
| #define | GPIO_OTYPER_OT12_Pos (12U) |
| #define | GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) |
| #define | GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk |
| #define | GPIO_OTYPER_OT13_Pos (13U) |
| #define | GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) |
| #define | GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk |
| #define | GPIO_OTYPER_OT14_Pos (14U) |
| #define | GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) |
| #define | GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk |
| #define | GPIO_OTYPER_OT15_Pos (15U) |
| #define | GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) |
| #define | GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk |
| #define | GPIO_OSPEEDR_OSPEED0_Pos (0U) |
| #define | GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) |
| #define | GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk |
| #define | GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) |
| #define | GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) |
| #define | GPIO_OSPEEDR_OSPEED1_Pos (2U) |
| #define | GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) |
| #define | GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk |
| #define | GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) |
| #define | GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) |
| #define | GPIO_OSPEEDR_OSPEED2_Pos (4U) |
| #define | GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) |
| #define | GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk |
| #define | GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) |
| #define | GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) |
| #define | GPIO_OSPEEDR_OSPEED3_Pos (6U) |
| #define | GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) |
| #define | GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk |
| #define | GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) |
| #define | GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) |
| #define | GPIO_OSPEEDR_OSPEED4_Pos (8U) |
| #define | GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) |
| #define | GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk |
| #define | GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) |
| #define | GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) |
| #define | GPIO_OSPEEDR_OSPEED5_Pos (10U) |
| #define | GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) |
| #define | GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk |
| #define | GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) |
| #define | GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) |
| #define | GPIO_OSPEEDR_OSPEED6_Pos (12U) |
| #define | GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) |
| #define | GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk |
| #define | GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) |
| #define | GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) |
| #define | GPIO_OSPEEDR_OSPEED7_Pos (14U) |
| #define | GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) |
| #define | GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk |
| #define | GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) |
| #define | GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) |
| #define | GPIO_OSPEEDR_OSPEED8_Pos (16U) |
| #define | GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) |
| #define | GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk |
| #define | GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) |
| #define | GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) |
| #define | GPIO_OSPEEDR_OSPEED9_Pos (18U) |
| #define | GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) |
| #define | GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk |
| #define | GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) |
| #define | GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) |
| #define | GPIO_OSPEEDR_OSPEED10_Pos (20U) |
| #define | GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) |
| #define | GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk |
| #define | GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) |
| #define | GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) |
| #define | GPIO_OSPEEDR_OSPEED11_Pos (22U) |
| #define | GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) |
| #define | GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk |
| #define | GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) |
| #define | GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) |
| #define | GPIO_OSPEEDR_OSPEED12_Pos (24U) |
| #define | GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) |
| #define | GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk |
| #define | GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) |
| #define | GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) |
| #define | GPIO_OSPEEDR_OSPEED13_Pos (26U) |
| #define | GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) |
| #define | GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk |
| #define | GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) |
| #define | GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) |
| #define | GPIO_OSPEEDR_OSPEED14_Pos (28U) |
| #define | GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) |
| #define | GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk |
| #define | GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) |
| #define | GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) |
| #define | GPIO_OSPEEDR_OSPEED15_Pos (30U) |
| #define | GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) |
| #define | GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk |
| #define | GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) |
| #define | GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) |
| #define | GPIO_PUPDR_PUPD0_Pos (0U) |
| #define | GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) |
| #define | GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk |
| #define | GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) |
| #define | GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) |
| #define | GPIO_PUPDR_PUPD1_Pos (2U) |
| #define | GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) |
| #define | GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk |
| #define | GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) |
| #define | GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) |
| #define | GPIO_PUPDR_PUPD2_Pos (4U) |
| #define | GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) |
| #define | GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk |
| #define | GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) |
| #define | GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) |
| #define | GPIO_PUPDR_PUPD3_Pos (6U) |
| #define | GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) |
| #define | GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk |
| #define | GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) |
| #define | GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) |
| #define | GPIO_PUPDR_PUPD4_Pos (8U) |
| #define | GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) |
| #define | GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk |
| #define | GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) |
| #define | GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) |
| #define | GPIO_PUPDR_PUPD5_Pos (10U) |
| #define | GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) |
| #define | GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk |
| #define | GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) |
| #define | GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) |
| #define | GPIO_PUPDR_PUPD6_Pos (12U) |
| #define | GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) |
| #define | GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk |
| #define | GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) |
| #define | GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) |
| #define | GPIO_PUPDR_PUPD7_Pos (14U) |
| #define | GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) |
| #define | GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk |
| #define | GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) |
| #define | GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) |
| #define | GPIO_PUPDR_PUPD8_Pos (16U) |
| #define | GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) |
| #define | GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk |
| #define | GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) |
| #define | GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) |
| #define | GPIO_PUPDR_PUPD9_Pos (18U) |
| #define | GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) |
| #define | GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk |
| #define | GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) |
| #define | GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) |
| #define | GPIO_PUPDR_PUPD10_Pos (20U) |
| #define | GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) |
| #define | GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk |
| #define | GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) |
| #define | GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) |
| #define | GPIO_PUPDR_PUPD11_Pos (22U) |
| #define | GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) |
| #define | GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk |
| #define | GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) |
| #define | GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) |
| #define | GPIO_PUPDR_PUPD12_Pos (24U) |
| #define | GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) |
| #define | GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk |
| #define | GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) |
| #define | GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) |
| #define | GPIO_PUPDR_PUPD13_Pos (26U) |
| #define | GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) |
| #define | GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk |
| #define | GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) |
| #define | GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) |
| #define | GPIO_PUPDR_PUPD14_Pos (28U) |
| #define | GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) |
| #define | GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk |
| #define | GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) |
| #define | GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) |
| #define | GPIO_PUPDR_PUPD15_Pos (30U) |
| #define | GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) |
| #define | GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk |
| #define | GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) |
| #define | GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) |
| #define | GPIO_IDR_ID0_Pos (0U) |
| #define | GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) |
| #define | GPIO_IDR_ID0 GPIO_IDR_ID0_Msk |
| #define | GPIO_IDR_ID1_Pos (1U) |
| #define | GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) |
| #define | GPIO_IDR_ID1 GPIO_IDR_ID1_Msk |
| #define | GPIO_IDR_ID2_Pos (2U) |
| #define | GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) |
| #define | GPIO_IDR_ID2 GPIO_IDR_ID2_Msk |
| #define | GPIO_IDR_ID3_Pos (3U) |
| #define | GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) |
| #define | GPIO_IDR_ID3 GPIO_IDR_ID3_Msk |
| #define | GPIO_IDR_ID4_Pos (4U) |
| #define | GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) |
| #define | GPIO_IDR_ID4 GPIO_IDR_ID4_Msk |
| #define | GPIO_IDR_ID5_Pos (5U) |
| #define | GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) |
| #define | GPIO_IDR_ID5 GPIO_IDR_ID5_Msk |
| #define | GPIO_IDR_ID6_Pos (6U) |
| #define | GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) |
| #define | GPIO_IDR_ID6 GPIO_IDR_ID6_Msk |
| #define | GPIO_IDR_ID7_Pos (7U) |
| #define | GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) |
| #define | GPIO_IDR_ID7 GPIO_IDR_ID7_Msk |
| #define | GPIO_IDR_ID8_Pos (8U) |
| #define | GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) |
| #define | GPIO_IDR_ID8 GPIO_IDR_ID8_Msk |
| #define | GPIO_IDR_ID9_Pos (9U) |
| #define | GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) |
| #define | GPIO_IDR_ID9 GPIO_IDR_ID9_Msk |
| #define | GPIO_IDR_ID10_Pos (10U) |
| #define | GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) |
| #define | GPIO_IDR_ID10 GPIO_IDR_ID10_Msk |
| #define | GPIO_IDR_ID11_Pos (11U) |
| #define | GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) |
| #define | GPIO_IDR_ID11 GPIO_IDR_ID11_Msk |
| #define | GPIO_IDR_ID12_Pos (12U) |
| #define | GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) |
| #define | GPIO_IDR_ID12 GPIO_IDR_ID12_Msk |
| #define | GPIO_IDR_ID13_Pos (13U) |
| #define | GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) |
| #define | GPIO_IDR_ID13 GPIO_IDR_ID13_Msk |
| #define | GPIO_IDR_ID14_Pos (14U) |
| #define | GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) |
| #define | GPIO_IDR_ID14 GPIO_IDR_ID14_Msk |
| #define | GPIO_IDR_ID15_Pos (15U) |
| #define | GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) |
| #define | GPIO_IDR_ID15 GPIO_IDR_ID15_Msk |
| #define | GPIO_ODR_OD0_Pos (0U) |
| #define | GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) |
| #define | GPIO_ODR_OD0 GPIO_ODR_OD0_Msk |
| #define | GPIO_ODR_OD1_Pos (1U) |
| #define | GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) |
| #define | GPIO_ODR_OD1 GPIO_ODR_OD1_Msk |
| #define | GPIO_ODR_OD2_Pos (2U) |
| #define | GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) |
| #define | GPIO_ODR_OD2 GPIO_ODR_OD2_Msk |
| #define | GPIO_ODR_OD3_Pos (3U) |
| #define | GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) |
| #define | GPIO_ODR_OD3 GPIO_ODR_OD3_Msk |
| #define | GPIO_ODR_OD4_Pos (4U) |
| #define | GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) |
| #define | GPIO_ODR_OD4 GPIO_ODR_OD4_Msk |
| #define | GPIO_ODR_OD5_Pos (5U) |
| #define | GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) |
| #define | GPIO_ODR_OD5 GPIO_ODR_OD5_Msk |
| #define | GPIO_ODR_OD6_Pos (6U) |
| #define | GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) |
| #define | GPIO_ODR_OD6 GPIO_ODR_OD6_Msk |
| #define | GPIO_ODR_OD7_Pos (7U) |
| #define | GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) |
| #define | GPIO_ODR_OD7 GPIO_ODR_OD7_Msk |
| #define | GPIO_ODR_OD8_Pos (8U) |
| #define | GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) |
| #define | GPIO_ODR_OD8 GPIO_ODR_OD8_Msk |
| #define | GPIO_ODR_OD9_Pos (9U) |
| #define | GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) |
| #define | GPIO_ODR_OD9 GPIO_ODR_OD9_Msk |
| #define | GPIO_ODR_OD10_Pos (10U) |
| #define | GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) |
| #define | GPIO_ODR_OD10 GPIO_ODR_OD10_Msk |
| #define | GPIO_ODR_OD11_Pos (11U) |
| #define | GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) |
| #define | GPIO_ODR_OD11 GPIO_ODR_OD11_Msk |
| #define | GPIO_ODR_OD12_Pos (12U) |
| #define | GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) |
| #define | GPIO_ODR_OD12 GPIO_ODR_OD12_Msk |
| #define | GPIO_ODR_OD13_Pos (13U) |
| #define | GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) |
| #define | GPIO_ODR_OD13 GPIO_ODR_OD13_Msk |
| #define | GPIO_ODR_OD14_Pos (14U) |
| #define | GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) |
| #define | GPIO_ODR_OD14 GPIO_ODR_OD14_Msk |
| #define | GPIO_ODR_OD15_Pos (15U) |
| #define | GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) |
| #define | GPIO_ODR_OD15 GPIO_ODR_OD15_Msk |
| #define | GPIO_BSRR_BS0_Pos (0U) |
| #define | GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) |
| #define | GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk |
| #define | GPIO_BSRR_BS1_Pos (1U) |
| #define | GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) |
| #define | GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk |
| #define | GPIO_BSRR_BS2_Pos (2U) |
| #define | GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) |
| #define | GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk |
| #define | GPIO_BSRR_BS3_Pos (3U) |
| #define | GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) |
| #define | GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk |
| #define | GPIO_BSRR_BS4_Pos (4U) |
| #define | GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) |
| #define | GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk |
| #define | GPIO_BSRR_BS5_Pos (5U) |
| #define | GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) |
| #define | GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk |
| #define | GPIO_BSRR_BS6_Pos (6U) |
| #define | GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) |
| #define | GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk |
| #define | GPIO_BSRR_BS7_Pos (7U) |
| #define | GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) |
| #define | GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk |
| #define | GPIO_BSRR_BS8_Pos (8U) |
| #define | GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) |
| #define | GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk |
| #define | GPIO_BSRR_BS9_Pos (9U) |
| #define | GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) |
| #define | GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk |
| #define | GPIO_BSRR_BS10_Pos (10U) |
| #define | GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) |
| #define | GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk |
| #define | GPIO_BSRR_BS11_Pos (11U) |
| #define | GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) |
| #define | GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk |
| #define | GPIO_BSRR_BS12_Pos (12U) |
| #define | GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) |
| #define | GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk |
| #define | GPIO_BSRR_BS13_Pos (13U) |
| #define | GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) |
| #define | GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk |
| #define | GPIO_BSRR_BS14_Pos (14U) |
| #define | GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) |
| #define | GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk |
| #define | GPIO_BSRR_BS15_Pos (15U) |
| #define | GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) |
| #define | GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk |
| #define | GPIO_BSRR_BR0_Pos (16U) |
| #define | GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) |
| #define | GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk |
| #define | GPIO_BSRR_BR1_Pos (17U) |
| #define | GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) |
| #define | GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk |
| #define | GPIO_BSRR_BR2_Pos (18U) |
| #define | GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) |
| #define | GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk |
| #define | GPIO_BSRR_BR3_Pos (19U) |
| #define | GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) |
| #define | GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk |
| #define | GPIO_BSRR_BR4_Pos (20U) |
| #define | GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) |
| #define | GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk |
| #define | GPIO_BSRR_BR5_Pos (21U) |
| #define | GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) |
| #define | GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk |
| #define | GPIO_BSRR_BR6_Pos (22U) |
| #define | GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) |
| #define | GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk |
| #define | GPIO_BSRR_BR7_Pos (23U) |
| #define | GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) |
| #define | GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk |
| #define | GPIO_BSRR_BR8_Pos (24U) |
| #define | GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) |
| #define | GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk |
| #define | GPIO_BSRR_BR9_Pos (25U) |
| #define | GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) |
| #define | GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk |
| #define | GPIO_BSRR_BR10_Pos (26U) |
| #define | GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) |
| #define | GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk |
| #define | GPIO_BSRR_BR11_Pos (27U) |
| #define | GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) |
| #define | GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk |
| #define | GPIO_BSRR_BR12_Pos (28U) |
| #define | GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) |
| #define | GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk |
| #define | GPIO_BSRR_BR13_Pos (29U) |
| #define | GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) |
| #define | GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk |
| #define | GPIO_BSRR_BR14_Pos (30U) |
| #define | GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) |
| #define | GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk |
| #define | GPIO_BSRR_BR15_Pos (31U) |
| #define | GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) |
| #define | GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk |
| #define | GPIO_LCKR_LCK0_Pos (0U) |
| #define | GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) |
| #define | GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk |
| #define | GPIO_LCKR_LCK1_Pos (1U) |
| #define | GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) |
| #define | GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk |
| #define | GPIO_LCKR_LCK2_Pos (2U) |
| #define | GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) |
| #define | GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk |
| #define | GPIO_LCKR_LCK3_Pos (3U) |
| #define | GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) |
| #define | GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk |
| #define | GPIO_LCKR_LCK4_Pos (4U) |
| #define | GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) |
| #define | GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk |
| #define | GPIO_LCKR_LCK5_Pos (5U) |
| #define | GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) |
| #define | GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk |
| #define | GPIO_LCKR_LCK6_Pos (6U) |
| #define | GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) |
| #define | GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk |
| #define | GPIO_LCKR_LCK7_Pos (7U) |
| #define | GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) |
| #define | GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk |
| #define | GPIO_LCKR_LCK8_Pos (8U) |
| #define | GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) |
| #define | GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk |
| #define | GPIO_LCKR_LCK9_Pos (9U) |
| #define | GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) |
| #define | GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk |
| #define | GPIO_LCKR_LCK10_Pos (10U) |
| #define | GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) |
| #define | GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk |
| #define | GPIO_LCKR_LCK11_Pos (11U) |
| #define | GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) |
| #define | GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk |
| #define | GPIO_LCKR_LCK12_Pos (12U) |
| #define | GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) |
| #define | GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk |
| #define | GPIO_LCKR_LCK13_Pos (13U) |
| #define | GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) |
| #define | GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk |
| #define | GPIO_LCKR_LCK14_Pos (14U) |
| #define | GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) |
| #define | GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk |
| #define | GPIO_LCKR_LCK15_Pos (15U) |
| #define | GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) |
| #define | GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk |
| #define | GPIO_LCKR_LCKK_Pos (16U) |
| #define | GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) |
| #define | GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk |
| #define | GPIO_AFRL_AFSEL0_Pos (0U) |
| #define | GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) |
| #define | GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk |
| #define | GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) |
| #define | GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) |
| #define | GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) |
| #define | GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) |
| #define | GPIO_AFRL_AFSEL1_Pos (4U) |
| #define | GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) |
| #define | GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk |
| #define | GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) |
| #define | GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) |
| #define | GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) |
| #define | GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) |
| #define | GPIO_AFRL_AFSEL2_Pos (8U) |
| #define | GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) |
| #define | GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk |
| #define | GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) |
| #define | GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) |
| #define | GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) |
| #define | GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) |
| #define | GPIO_AFRL_AFSEL3_Pos (12U) |
| #define | GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) |
| #define | GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk |
| #define | GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) |
| #define | GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) |
| #define | GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) |
| #define | GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) |
| #define | GPIO_AFRL_AFSEL4_Pos (16U) |
| #define | GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) |
| #define | GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk |
| #define | GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) |
| #define | GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) |
| #define | GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) |
| #define | GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) |
| #define | GPIO_AFRL_AFSEL5_Pos (20U) |
| #define | GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) |
| #define | GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk |
| #define | GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) |
| #define | GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) |
| #define | GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) |
| #define | GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) |
| #define | GPIO_AFRL_AFSEL6_Pos (24U) |
| #define | GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) |
| #define | GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
| #define | GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) |
| #define | GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) |
| #define | GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) |
| #define | GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) |
| #define | GPIO_AFRL_AFSEL7_Pos (28U) |
| #define | GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) |
| #define | GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
| #define | GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) |
| #define | GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) |
| #define | GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) |
| #define | GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) |
| #define | GPIO_AFRH_AFSEL8_Pos (0U) |
| #define | GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) |
| #define | GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk |
| #define | GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) |
| #define | GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) |
| #define | GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) |
| #define | GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) |
| #define | GPIO_AFRH_AFSEL9_Pos (4U) |
| #define | GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) |
| #define | GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk |
| #define | GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) |
| #define | GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) |
| #define | GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) |
| #define | GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) |
| #define | GPIO_AFRH_AFSEL10_Pos (8U) |
| #define | GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) |
| #define | GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk |
| #define | GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) |
| #define | GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) |
| #define | GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) |
| #define | GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) |
| #define | GPIO_AFRH_AFSEL11_Pos (12U) |
| #define | GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) |
| #define | GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk |
| #define | GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) |
| #define | GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) |
| #define | GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) |
| #define | GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) |
| #define | GPIO_AFRH_AFSEL12_Pos (16U) |
| #define | GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) |
| #define | GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk |
| #define | GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) |
| #define | GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) |
| #define | GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) |
| #define | GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) |
| #define | GPIO_AFRH_AFSEL13_Pos (20U) |
| #define | GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) |
| #define | GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk |
| #define | GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) |
| #define | GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) |
| #define | GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) |
| #define | GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) |
| #define | GPIO_AFRH_AFSEL14_Pos (24U) |
| #define | GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) |
| #define | GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk |
| #define | GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) |
| #define | GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) |
| #define | GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) |
| #define | GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) |
| #define | GPIO_AFRH_AFSEL15_Pos (28U) |
| #define | GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) |
| #define | GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk |
| #define | GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) |
| #define | GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) |
| #define | GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) |
| #define | GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) |
| #define | GPIO_BRR_BR0_Pos (0U) |
| #define | GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) |
| #define | GPIO_BRR_BR0 GPIO_BRR_BR0_Msk |
| #define | GPIO_BRR_BR1_Pos (1U) |
| #define | GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) |
| #define | GPIO_BRR_BR1 GPIO_BRR_BR1_Msk |
| #define | GPIO_BRR_BR2_Pos (2U) |
| #define | GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) |
| #define | GPIO_BRR_BR2 GPIO_BRR_BR2_Msk |
| #define | GPIO_BRR_BR3_Pos (3U) |
| #define | GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) |
| #define | GPIO_BRR_BR3 GPIO_BRR_BR3_Msk |
| #define | GPIO_BRR_BR4_Pos (4U) |
| #define | GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) |
| #define | GPIO_BRR_BR4 GPIO_BRR_BR4_Msk |
| #define | GPIO_BRR_BR5_Pos (5U) |
| #define | GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) |
| #define | GPIO_BRR_BR5 GPIO_BRR_BR5_Msk |
| #define | GPIO_BRR_BR6_Pos (6U) |
| #define | GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) |
| #define | GPIO_BRR_BR6 GPIO_BRR_BR6_Msk |
| #define | GPIO_BRR_BR7_Pos (7U) |
| #define | GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) |
| #define | GPIO_BRR_BR7 GPIO_BRR_BR7_Msk |
| #define | GPIO_BRR_BR8_Pos (8U) |
| #define | GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) |
| #define | GPIO_BRR_BR8 GPIO_BRR_BR8_Msk |
| #define | GPIO_BRR_BR9_Pos (9U) |
| #define | GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) |
| #define | GPIO_BRR_BR9 GPIO_BRR_BR9_Msk |
| #define | GPIO_BRR_BR10_Pos (10U) |
| #define | GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) |
| #define | GPIO_BRR_BR10 GPIO_BRR_BR10_Msk |
| #define | GPIO_BRR_BR11_Pos (11U) |
| #define | GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) |
| #define | GPIO_BRR_BR11 GPIO_BRR_BR11_Msk |
| #define | GPIO_BRR_BR12_Pos (12U) |
| #define | GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) |
| #define | GPIO_BRR_BR12 GPIO_BRR_BR12_Msk |
| #define | GPIO_BRR_BR13_Pos (13U) |
| #define | GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) |
| #define | GPIO_BRR_BR13 GPIO_BRR_BR13_Msk |
| #define | GPIO_BRR_BR14_Pos (14U) |
| #define | GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) |
| #define | GPIO_BRR_BR14 GPIO_BRR_BR14_Msk |
| #define | GPIO_BRR_BR15_Pos (15U) |
| #define | GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) |
| #define | GPIO_BRR_BR15 GPIO_BRR_BR15_Msk |
| #define | GPIO_HSLVR_HSLV0_Pos (0U) |
| #define | GPIO_HSLVR_HSLV0_Msk (0x1UL << GPIO_HSLVR_HSLV0_Pos) |
| #define | GPIO_HSLVR_HSLV0 GPIO_HSLVR_HSLV0_Msk |
| #define | GPIO_HSLVR_HSLV1_Pos (1U) |
| #define | GPIO_HSLVR_HSLV1_Msk (0x1UL << GPIO_HSLVR_HSLV1_Pos) |
| #define | GPIO_HSLVR_HSLV1 GPIO_HSLVR_HSLV1_Msk |
| #define | GPIO_HSLVR_HSLV2_Pos (2U) |
| #define | GPIO_HSLVR_HSLV2_Msk (0x1UL << GPIO_HSLVR_HSLV2_Pos) |
| #define | GPIO_HSLVR_HSLV2 GPIO_HSLVR_HSLV2_Msk |
| #define | GPIO_HSLVR_HSLV3_Pos (3U) |
| #define | GPIO_HSLVR_HSLV3_Msk (0x1UL << GPIO_HSLVR_HSLV3_Pos) |
| #define | GPIO_HSLVR_HSLV3 GPIO_HSLVR_HSLV3_Msk |
| #define | GPIO_HSLVR_HSLV4_Pos (4U) |
| #define | GPIO_HSLVR_HSLV4_Msk (0x1UL << GPIO_HSLVR_HSLV4_Pos) |
| #define | GPIO_HSLVR_HSLV4 GPIO_HSLVR_HSLV4_Msk |
| #define | GPIO_HSLVR_HSLV5_Pos (5U) |
| #define | GPIO_HSLVR_HSLV5_Msk (0x1UL << GPIO_HSLVR_HSLV5_Pos) |
| #define | GPIO_HSLVR_HSLV5 GPIO_HSLVR_HSLV5_Msk |
| #define | GPIO_HSLVR_HSLV6_Pos (6U) |
| #define | GPIO_HSLVR_HSLV6_Msk (0x1UL << GPIO_HSLVR_HSLV6_Pos) |
| #define | GPIO_HSLVR_HSLV6 GPIO_HSLVR_HSLV6_Msk |
| #define | GPIO_HSLVR_HSLV7_Pos (7U) |
| #define | GPIO_HSLVR_HSLV7_Msk (0x1UL << GPIO_HSLVR_HSLV7_Pos) |
| #define | GPIO_HSLVR_HSLV7 GPIO_HSLVR_HSLV7_Msk |
| #define | GPIO_HSLVR_HSLV8_Pos (8U) |
| #define | GPIO_HSLVR_HSLV8_Msk (0x1UL << GPIO_HSLVR_HSLV8_Pos) |
| #define | GPIO_HSLVR_HSLV8 GPIO_HSLVR_HSLV8_Msk |
| #define | GPIO_HSLVR_HSLV9_Pos (9U) |
| #define | GPIO_HSLVR_HSLV9_Msk (0x1UL << GPIO_HSLVR_HSLV9_Pos) |
| #define | GPIO_HSLVR_HSLV9 GPIO_HSLVR_HSLV9_Msk |
| #define | GPIO_HSLVR_HSLV10_Pos (10U) |
| #define | GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) |
| #define | GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk |
| #define | GPIO_HSLVR_HSLV11_Pos (11U) |
| #define | GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) |
| #define | GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk |
| #define | GPIO_HSLVR_HSLV12_Pos (12U) |
| #define | GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) |
| #define | GPIO_HSLVR_HSLV12 GPIO_HSLVR_HSLV12_Msk |
| #define | GPIO_HSLVR_HSLV13_Pos (13U) |
| #define | GPIO_HSLVR_HSLV13_Msk (0x1UL << GPIO_HSLVR_HSLV13_Pos) |
| #define | GPIO_HSLVR_HSLV13 GPIO_HSLVR_HSLV13_Msk |
| #define | GPIO_HSLVR_HSLV14_Pos (14U) |
| #define | GPIO_HSLVR_HSLV14_Msk (0x1UL << GPIO_HSLVR_HSLV14_Pos) |
| #define | GPIO_HSLVR_HSLV14 GPIO_HSLVR_HSLV14_Msk |
| #define | GPIO_HSLVR_HSLV15_Pos (15U) |
| #define | GPIO_HSLVR_HSLV15_Msk (0x1UL << GPIO_HSLVR_HSLV15_Pos) |
| #define | GPIO_HSLVR_HSLV15 GPIO_HSLVR_HSLV15_Msk |
| #define | GPIO_SECCFGR_SEC0_Pos (0U) |
| #define | GPIO_SECCFGR_SEC0_Msk (0x1UL << GPIO_SECCFGR_SEC0_Pos) |
| #define | GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk |
| #define | GPIO_SECCFGR_SEC1_Pos (1U) |
| #define | GPIO_SECCFGR_SEC1_Msk (0x1UL << GPIO_SECCFGR_SEC1_Pos) |
| #define | GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk |
| #define | GPIO_SECCFGR_SEC2_Pos (2U) |
| #define | GPIO_SECCFGR_SEC2_Msk (0x1UL << GPIO_SECCFGR_SEC2_Pos) |
| #define | GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk |
| #define | GPIO_SECCFGR_SEC3_Pos (3U) |
| #define | GPIO_SECCFGR_SEC3_Msk (0x1UL << GPIO_SECCFGR_SEC3_Pos) |
| #define | GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk |
| #define | GPIO_SECCFGR_SEC4_Pos (4U) |
| #define | GPIO_SECCFGR_SEC4_Msk (0x1UL << GPIO_SECCFGR_SEC4_Pos) |
| #define | GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk |
| #define | GPIO_SECCFGR_SEC5_Pos (5U) |
| #define | GPIO_SECCFGR_SEC5_Msk (0x1UL << GPIO_SECCFGR_SEC5_Pos) |
| #define | GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk |
| #define | GPIO_SECCFGR_SEC6_Pos (6U) |
| #define | GPIO_SECCFGR_SEC6_Msk (0x1UL << GPIO_SECCFGR_SEC6_Pos) |
| #define | GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk |
| #define | GPIO_SECCFGR_SEC7_Pos (7U) |
| #define | GPIO_SECCFGR_SEC7_Msk (0x1UL << GPIO_SECCFGR_SEC7_Pos) |
| #define | GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk |
| #define | GPIO_SECCFGR_SEC8_Pos (8U) |
| #define | GPIO_SECCFGR_SEC8_Msk (0x1UL << GPIO_SECCFGR_SEC8_Pos) |
| #define | GPIO_SECCFGR_SEC8 GPIO_SECCFGR_SEC8_Msk |
| #define | GPIO_SECCFGR_SEC9_Pos (9U) |
| #define | GPIO_SECCFGR_SEC9_Msk (0x1UL << GPIO_SECCFGR_SEC9_Pos) |
| #define | GPIO_SECCFGR_SEC9 GPIO_SECCFGR_SEC9_Msk |
| #define | GPIO_SECCFGR_SEC10_Pos (10U) |
| #define | GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) |
| #define | GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk |
| #define | GPIO_SECCFGR_SEC11_Pos (11U) |
| #define | GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) |
| #define | GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk |
| #define | GPIO_SECCFGR_SEC12_Pos (12U) |
| #define | GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) |
| #define | GPIO_SECCFGR_SEC12 GPIO_SECCFGR_SEC12_Msk |
| #define | GPIO_SECCFGR_SEC13_Pos (13U) |
| #define | GPIO_SECCFGR_SEC13_Msk (0x1UL << GPIO_SECCFGR_SEC13_Pos) |
| #define | GPIO_SECCFGR_SEC13 GPIO_SECCFGR_SEC13_Msk |
| #define | GPIO_SECCFGR_SEC14_Pos (14U) |
| #define | GPIO_SECCFGR_SEC14_Msk (0x1UL << GPIO_SECCFGR_SEC14_Pos) |
| #define | GPIO_SECCFGR_SEC14 GPIO_SECCFGR_SEC14_Msk |
| #define | GPIO_SECCFGR_SEC15_Pos (15U) |
| #define | GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) |
| #define | GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk |
| #define | JPEG_CONFR0_START_Pos (0U) |
| #define | JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos) |
| #define | JPEG_CONFR0_START JPEG_CONFR0_START_Msk |
| #define | JPEG_CONFR1_NF_Pos (0U) |
| #define | JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos) |
| #define | JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk |
| #define | JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos) |
| #define | JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos) |
| #define | JPEG_CONFR1_DE_Pos (3U) |
| #define | JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos) |
| #define | JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk |
| #define | JPEG_CONFR1_COLORSPACE_Pos (4U) |
| #define | JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos) |
| #define | JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk |
| #define | JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos) |
| #define | JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos) |
| #define | JPEG_CONFR1_NS_Pos (6U) |
| #define | JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos) |
| #define | JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk |
| #define | JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos) |
| #define | JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos) |
| #define | JPEG_CONFR1_HDR_Pos (8U) |
| #define | JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos) |
| #define | JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk |
| #define | JPEG_CONFR1_YSIZE_Pos (16U) |
| #define | JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos) |
| #define | JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk |
| #define | JPEG_CONFR2_NMCU_Pos (0U) |
| #define | JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos) |
| #define | JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk |
| #define | JPEG_CONFR3_XSIZE_Pos (16U) |
| #define | JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos) |
| #define | JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk |
| #define | JPEG_CONFR4_HD_Pos (0U) |
| #define | JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos) |
| #define | JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk |
| #define | JPEG_CONFR4_HA_Pos (1U) |
| #define | JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos) |
| #define | JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk |
| #define | JPEG_CONFR4_QT_Pos (2U) |
| #define | JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos) |
| #define | JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk |
| #define | JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos) |
| #define | JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos) |
| #define | JPEG_CONFR4_NB_Pos (4U) |
| #define | JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos) |
| #define | JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk |
| #define | JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos) |
| #define | JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos) |
| #define | JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos) |
| #define | JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos) |
| #define | JPEG_CONFR4_VSF_Pos (8U) |
| #define | JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos) |
| #define | JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk |
| #define | JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos) |
| #define | JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos) |
| #define | JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos) |
| #define | JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos) |
| #define | JPEG_CONFR4_HSF_Pos (12U) |
| #define | JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos) |
| #define | JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk |
| #define | JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos) |
| #define | JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos) |
| #define | JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos) |
| #define | JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos) |
| #define | JPEG_CONFR5_HD_Pos (0U) |
| #define | JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos) |
| #define | JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk |
| #define | JPEG_CONFR5_HA_Pos (1U) |
| #define | JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos) |
| #define | JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk |
| #define | JPEG_CONFR5_QT_Pos (2U) |
| #define | JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos) |
| #define | JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk |
| #define | JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos) |
| #define | JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos) |
| #define | JPEG_CONFR5_NB_Pos (4U) |
| #define | JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos) |
| #define | JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk |
| #define | JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos) |
| #define | JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos) |
| #define | JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos) |
| #define | JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos) |
| #define | JPEG_CONFR5_VSF_Pos (8U) |
| #define | JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos) |
| #define | JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk |
| #define | JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos) |
| #define | JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos) |
| #define | JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos) |
| #define | JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos) |
| #define | JPEG_CONFR5_HSF_Pos (12U) |
| #define | JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos) |
| #define | JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk |
| #define | JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos) |
| #define | JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos) |
| #define | JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos) |
| #define | JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos) |
| #define | JPEG_CONFR6_HD_Pos (0U) |
| #define | JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos) |
| #define | JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk |
| #define | JPEG_CONFR6_HA_Pos (1U) |
| #define | JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos) |
| #define | JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk |
| #define | JPEG_CONFR6_QT_Pos (2U) |
| #define | JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos) |
| #define | JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk |
| #define | JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos) |
| #define | JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos) |
| #define | JPEG_CONFR6_NB_Pos (4U) |
| #define | JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos) |
| #define | JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk |
| #define | JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos) |
| #define | JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos) |
| #define | JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos) |
| #define | JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos) |
| #define | JPEG_CONFR6_VSF_Pos (8U) |
| #define | JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos) |
| #define | JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk |
| #define | JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos) |
| #define | JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos) |
| #define | JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos) |
| #define | JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos) |
| #define | JPEG_CONFR6_HSF_Pos (12U) |
| #define | JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos) |
| #define | JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk |
| #define | JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos) |
| #define | JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos) |
| #define | JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos) |
| #define | JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos) |
| #define | JPEG_CONFR7_HD_Pos (0U) |
| #define | JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos) |
| #define | JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk |
| #define | JPEG_CONFR7_HA_Pos (1U) |
| #define | JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos) |
| #define | JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk |
| #define | JPEG_CONFR7_QT_Pos (2U) |
| #define | JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos) |
| #define | JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk |
| #define | JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos) |
| #define | JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos) |
| #define | JPEG_CONFR7_NB_Pos (4U) |
| #define | JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos) |
| #define | JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk |
| #define | JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos) |
| #define | JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos) |
| #define | JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos) |
| #define | JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos) |
| #define | JPEG_CONFR7_VSF_Pos (8U) |
| #define | JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos) |
| #define | JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk |
| #define | JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos) |
| #define | JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos) |
| #define | JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos) |
| #define | JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos) |
| #define | JPEG_CONFR7_HSF_Pos (12U) |
| #define | JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos) |
| #define | JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk |
| #define | JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos) |
| #define | JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos) |
| #define | JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos) |
| #define | JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos) |
| #define | JPEG_CR_JCEN_Pos (0U) |
| #define | JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos) |
| #define | JPEG_CR_JCEN JPEG_CR_JCEN_Msk |
| #define | JPEG_CR_IFTIE_Pos (1U) |
| #define | JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos) |
| #define | JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk |
| #define | JPEG_CR_IFNFIE_Pos (2U) |
| #define | JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos) |
| #define | JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk |
| #define | JPEG_CR_OFTIE_Pos (3U) |
| #define | JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos) |
| #define | JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk |
| #define | JPEG_CR_OFNEIE_Pos (4U) |
| #define | JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos) |
| #define | JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk |
| #define | JPEG_CR_EOCIE_Pos (5U) |
| #define | JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos) |
| #define | JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk |
| #define | JPEG_CR_HPDIE_Pos (6U) |
| #define | JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos) |
| #define | JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk |
| #define | JPEG_CR_IDMAEN_Pos (11U) |
| #define | JPEG_CR_IDMAEN_Msk (0x1UL << JPEG_CR_IDMAEN_Pos) |
| #define | JPEG_CR_IDMAEN JPEG_CR_IDMAEN_Msk |
| #define | JPEG_CR_ODMAEN_Pos (12U) |
| #define | JPEG_CR_ODMAEN_Msk (0x1UL << JPEG_CR_ODMAEN_Pos) |
| #define | JPEG_CR_ODMAEN JPEG_CR_ODMAEN_Msk |
| #define | JPEG_CR_IFF_Pos (13U) |
| #define | JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos) |
| #define | JPEG_CR_IFF JPEG_CR_IFF_Msk |
| #define | JPEG_CR_OFF_Pos (14U) |
| #define | JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos) |
| #define | JPEG_CR_OFF JPEG_CR_OFF_Msk |
| #define | JPEG_SR_IFTF_Pos (1U) |
| #define | JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) |
| #define | JPEG_SR_IFTF JPEG_SR_IFTF_Msk |
| #define | JPEG_SR_IFNFF_Pos (2U) |
| #define | JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) |
| #define | JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk |
| #define | JPEG_SR_OFTF_Pos (3U) |
| #define | JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos) |
| #define | JPEG_SR_OFTF JPEG_SR_OFTF_Msk |
| #define | JPEG_SR_OFNEF_Pos (4U) |
| #define | JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos) |
| #define | JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk |
| #define | JPEG_SR_EOCF_Pos (5U) |
| #define | JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos) |
| #define | JPEG_SR_EOCF JPEG_SR_EOCF_Msk |
| #define | JPEG_SR_HPDF_Pos (6U) |
| #define | JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos) |
| #define | JPEG_SR_HPDF JPEG_SR_HPDF_Msk |
| #define | JPEG_SR_COF_Pos (7U) |
| #define | JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos) |
| #define | JPEG_SR_COF JPEG_SR_COF_Msk |
| #define | JPEG_CFR_CEOCF_Pos (4U) |
| #define | JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos) |
| #define | JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk |
| #define | JPEG_CFR_CHPDF_Pos (5U) |
| #define | JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos) |
| #define | JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk |
| #define | JPEG_DIR_DATAIN_Pos (0U) |
| #define | JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos) |
| #define | JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk |
| #define | JPEG_DOR_DATAOUT_Pos (0U) |
| #define | JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) |
| #define | JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk |
| #define | LPGPIO_MODER_MOD0_Pos (0U) |
| #define | LPGPIO_MODER_MOD0_Msk (0x1UL << LPGPIO_MODER_MOD0_Pos) |
| #define | LPGPIO_MODER_MOD0 LPGPIO_MODER_MOD0_Msk |
| #define | LPGPIO_MODER_MOD1_Pos (1U) |
| #define | LPGPIO_MODER_MOD1_Msk (0x1UL << LPGPIO_MODER_MOD1_Pos) |
| #define | LPGPIO_MODER_MOD1 LPGPIO_MODER_MOD1_Msk |
| #define | LPGPIO_MODER_MOD2_Pos (2U) |
| #define | LPGPIO_MODER_MOD2_Msk (0x1UL << LPGPIO_MODER_MOD2_Pos) |
| #define | LPGPIO_MODER_MOD2 LPGPIO_MODER_MOD2_Msk |
| #define | LPGPIO_MODER_MOD3_Pos (3U) |
| #define | LPGPIO_MODER_MOD3_Msk (0x1UL << LPGPIO_MODER_MOD3_Pos) |
| #define | LPGPIO_MODER_MOD3 LPGPIO_MODER_MOD3_Msk |
| #define | LPGPIO_MODER_MOD4_Pos (4U) |
| #define | LPGPIO_MODER_MOD4_Msk (0x1UL << LPGPIO_MODER_MOD4_Pos) |
| #define | LPGPIO_MODER_MOD4 LPGPIO_MODER_MOD4_Msk |
| #define | LPGPIO_MODER_MOD5_Pos (5U) |
| #define | LPGPIO_MODER_MOD5_Msk (0x1UL << LPGPIO_MODER_MOD5_Pos) |
| #define | LPGPIO_MODER_MOD5 LPGPIO_MODER_MOD5_Msk |
| #define | LPGPIO_MODER_MOD6_Pos (6U) |
| #define | LPGPIO_MODER_MOD6_Msk (0x1UL << LPGPIO_MODER_MOD6_Pos) |
| #define | LPGPIO_MODER_MOD6 LPGPIO_MODER_MOD6_Msk |
| #define | LPGPIO_MODER_MOD7_Pos (7U) |
| #define | LPGPIO_MODER_MOD7_Msk (0x1UL << LPGPIO_MODER_MOD7_Pos) |
| #define | LPGPIO_MODER_MOD7 LPGPIO_MODER_MOD7_Msk |
| #define | LPGPIO_MODER_MOD8_Pos (8U) |
| #define | LPGPIO_MODER_MOD8_Msk (0x1UL << LPGPIO_MODER_MOD8_Pos) |
| #define | LPGPIO_MODER_MOD8 LPGPIO_MODER_MOD8_Msk |
| #define | LPGPIO_MODER_MOD9_Pos (9U) |
| #define | LPGPIO_MODER_MOD9_Msk (0x1UL << LPGPIO_MODER_MOD9_Pos) |
| #define | LPGPIO_MODER_MOD9 LPGPIO_MODER_MOD9_Msk |
| #define | LPGPIO_MODER_MOD10_Pos (10U) |
| #define | LPGPIO_MODER_MOD10_Msk (0x1UL << LPGPIO_MODER_MOD10_Pos) |
| #define | LPGPIO_MODER_MOD10 LPGPIO_MODER_MOD10_Msk |
| #define | LPGPIO_MODER_MOD11_Pos (11U) |
| #define | LPGPIO_MODER_MOD11_Msk (0x1UL << LPGPIO_MODER_MOD11_Pos) |
| #define | LPGPIO_MODER_MOD11 LPGPIO_MODER_MOD11_Msk |
| #define | LPGPIO_MODER_MOD12_Pos (12U) |
| #define | LPGPIO_MODER_MOD12_Msk (0x1UL << LPGPIO_MODER_MOD12_Pos) |
| #define | LPGPIO_MODER_MOD12 LPGPIO_MODER_MOD12_Msk |
| #define | LPGPIO_MODER_MOD13_Pos (13U) |
| #define | LPGPIO_MODER_MOD13_Msk (0x1UL << LPGPIO_MODER_MOD13_Pos) |
| #define | LPGPIO_MODER_MOD13 LPGPIO_MODER_MOD13_Msk |
| #define | LPGPIO_MODER_MOD14_Pos (14U) |
| #define | LPGPIO_MODER_MOD14_Msk (0x1UL << LPGPIO_MODER_MOD14_Pos) |
| #define | LPGPIO_MODER_MOD14 LPGPIO_MODER_MOD14_Msk |
| #define | LPGPIO_MODER_MOD15_Pos (15U) |
| #define | LPGPIO_MODER_MOD15_Msk (0x1UL << LPGPIO_MODER_MOD15_Pos) |
| #define | LPGPIO_MODER_MOD15 LPGPIO_MODER_MOD15_Msk |
| #define | LPGPIO_IDR_ID0_Pos (0U) |
| #define | LPGPIO_IDR_ID0_Msk (0x1UL << LPGPIO_IDR_ID0_Pos) |
| #define | LPGPIO_IDR_ID0 LPGPIO_IDR_ID0_Msk |
| #define | LPGPIO_IDR_ID1_Pos (1U) |
| #define | LPGPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) |
| #define | LPGPIO_IDR_ID1 LPGPIO_IDR_ID1_Msk |
| #define | LPGPIO_IDR_ID2_Pos (2U) |
| #define | LPGPIO_IDR_ID2_Msk (0x1UL << LPGPIO_IDR_ID2_Pos) |
| #define | LPGPIO_IDR_ID2 LPGPIO_IDR_ID2_Msk |
| #define | LPGPIO_IDR_ID3_Pos (3U) |
| #define | LPGPIO_IDR_ID3_Msk (0x1UL << LPGPIO_IDR_ID3_Pos) |
| #define | LPGPIO_IDR_ID3 LPGPIO_IDR_ID3_Msk |
| #define | LPGPIO_IDR_ID4_Pos (4U) |
| #define | LPGPIO_IDR_ID4_Msk (0x1UL << LPGPIO_IDR_ID4_Pos) |
| #define | LPGPIO_IDR_ID4 LPGPIO_IDR_ID4_Msk |
| #define | LPGPIO_IDR_ID5_Pos (5U) |
| #define | LPGPIO_IDR_ID5_Msk (0x1UL << LPGPIO_IDR_ID5_Pos) |
| #define | LPGPIO_IDR_ID5 LPGPIO_IDR_ID5_Msk |
| #define | LPGPIO_IDR_ID6_Pos (6U) |
| #define | LPGPIO_IDR_ID6_Msk (0x1UL << LPGPIO_IDR_ID6_Pos) |
| #define | LPGPIO_IDR_ID6 LPGPIO_IDR_ID6_Msk |
| #define | LPGPIO_IDR_ID7_Pos (7U) |
| #define | LPGPIO_IDR_ID7_Msk (0x1UL << LPGPIO_IDR_ID7_Pos) |
| #define | LPGPIO_IDR_ID7 LPGPIO_IDR_ID7_Msk |
| #define | LPGPIO_IDR_ID8_Pos (8U) |
| #define | LPGPIO_IDR_ID8_Msk (0x1UL << LPGPIO_IDR_ID8_Pos) |
| #define | LPGPIO_IDR_ID8 LPGPIO_IDR_ID8_Msk |
| #define | LPGPIO_IDR_ID9_Pos (9U) |
| #define | LPGPIO_IDR_ID9_Msk (0x1UL << LPGPIO_IDR_ID9_Pos) |
| #define | LPGPIO_IDR_ID9 LPGPIO_IDR_ID9_Msk |
| #define | LPGPIO_IDR_ID10_Pos (10U) |
| #define | LPGPIO_IDR_ID10_Msk (0x1UL << LPGPIO_IDR_ID10_Pos) |
| #define | LPGPIO_IDR_ID10 LPGPIO_IDR_ID10_Msk |
| #define | LPGPIO_IDR_ID11_Pos (11U) |
| #define | LPGPIO_IDR_ID11_Msk (0x1UL << LPGPIO_IDR_ID11_Pos) |
| #define | LPGPIO_IDR_ID11 LPGPIO_IDR_ID11_Msk |
| #define | LPGPIO_IDR_ID12_Pos (12U) |
| #define | LPGPIO_IDR_ID12_Msk (0x1UL << LPGPIO_IDR_ID12_Pos) |
| #define | LPGPIO_IDR_ID12 LPGPIO_IDR_ID12_Msk |
| #define | LPGPIO_IDR_ID13_Pos (13U) |
| #define | LPGPIO_IDR_ID13_Msk (0x1UL << LPGPIO_IDR_ID13_Pos) |
| #define | LPGPIO_IDR_ID13 LPGPIO_IDR_ID13_Msk |
| #define | LPGPIO_IDR_ID14_Pos (14U) |
| #define | LPGPIO_IDR_ID14_Msk (0x1UL << LPGPIO_IDR_ID14_Pos) |
| #define | LPGPIO_IDR_ID14 LPGPIO_IDR_ID14_Msk |
| #define | LPGPIO_IDR_ID15_Pos (15U) |
| #define | LPGPIO_IDR_ID15_Msk (0x1UL << LPGPIO_IDR_ID15_Pos) |
| #define | LPGPIO_IDR_ID15 LPGPIO_IDR_ID15_Msk |
| #define | LPGPIO_ODR_OD0_Pos (0U) |
| #define | LPGPIO_ODR_OD0_Msk (0x1UL << LPGPIO_ODR_OD0_Pos) |
| #define | LPGPIO_ODR_OD0 LPGPIO_ODR_OD0_Msk |
| #define | LPGPIO_ODR_OD1_Pos (1U) |
| #define | LPGPIO_ODR_OD1_Msk (0x1UL << LPGPIO_ODR_OD1_Pos) |
| #define | LPGPIO_ODR_OD1 LPGPIO_ODR_OD1_Msk |
| #define | LPGPIO_ODR_OD2_Pos (2U) |
| #define | LPGPIO_ODR_OD2_Msk (0x1UL << LPGPIO_ODR_OD2_Pos) |
| #define | LPGPIO_ODR_OD2 LPGPIO_ODR_OD2_Msk |
| #define | LPGPIO_ODR_OD3_Pos (3U) |
| #define | LPGPIO_ODR_OD3_Msk (0x1UL << LPGPIO_ODR_OD3_Pos) |
| #define | LPGPIO_ODR_OD3 LPGPIO_ODR_OD3_Msk |
| #define | LPGPIO_ODR_OD4_Pos (4U) |
| #define | LPGPIO_ODR_OD4_Msk (0x1UL << LPGPIO_ODR_OD4_Pos) |
| #define | LPGPIO_ODR_OD4 LPGPIO_ODR_OD4_Msk |
| #define | LPGPIO_ODR_OD5_Pos (5U) |
| #define | LPGPIO_ODR_OD5_Msk (0x1UL << LPGPIO_ODR_OD5_Pos) |
| #define | LPGPIO_ODR_OD5 LPGPIO_ODR_OD5_Msk |
| #define | LPGPIO_ODR_OD6_Pos (6U) |
| #define | LPGPIO_ODR_OD6_Msk (0x1UL << LPGPIO_ODR_OD6_Pos) |
| #define | LPGPIO_ODR_OD6 LPGPIO_ODR_OD6_Msk |
| #define | LPGPIO_ODR_OD7_Pos (7U) |
| #define | LPGPIO_ODR_OD7_Msk (0x1UL << LPGPIO_ODR_OD7_Pos) |
| #define | LPGPIO_ODR_OD7 LPGPIO_ODR_OD7_Msk |
| #define | LPGPIO_ODR_OD8_Pos (8U) |
| #define | LPGPIO_ODR_OD8_Msk (0x1UL << LPGPIO_ODR_OD8_Pos) |
| #define | LPGPIO_ODR_OD8 LPGPIO_ODR_OD8_Msk |
| #define | LPGPIO_ODR_OD9_Pos (9U) |
| #define | LPGPIO_ODR_OD9_Msk (0x1UL << LPGPIO_ODR_OD9_Pos) |
| #define | LPGPIO_ODR_OD9 LPGPIO_ODR_OD9_Msk |
| #define | LPGPIO_ODR_OD10_Pos (10U) |
| #define | LPGPIO_ODR_OD10_Msk (0x1UL << LPGPIO_ODR_OD10_Pos) |
| #define | LPGPIO_ODR_OD10 LPGPIO_ODR_OD10_Msk |
| #define | LPGPIO_ODR_OD11_Pos (11U) |
| #define | LPGPIO_ODR_OD11_Msk (0x1UL << LPGPIO_ODR_OD11_Pos) |
| #define | LPGPIO_ODR_OD11 LPGPIO_ODR_OD11_Msk |
| #define | LPGPIO_ODR_OD12_Pos (12U) |
| #define | LPGPIO_ODR_OD12_Msk (0x1UL << LPGPIO_ODR_OD12_Pos) |
| #define | LPGPIO_ODR_OD12 LPGPIO_ODR_OD12_Msk |
| #define | LPGPIO_ODR_OD13_Pos (13U) |
| #define | LPGPIO_ODR_OD13_Msk (0x1UL << LPGPIO_ODR_OD13_Pos) |
| #define | LPGPIO_ODR_OD13 LPGPIO_ODR_OD13_Msk |
| #define | LPGPIO_ODR_OD14_Pos (14U) |
| #define | LPGPIO_ODR_OD14_Msk (0x1UL << LPGPIO_ODR_OD14_Pos) |
| #define | LPGPIO_ODR_OD14 LPGPIO_ODR_OD14_Msk |
| #define | LPGPIO_ODR_OD15_Pos (15U) |
| #define | LPGPIO_ODR_OD15_Msk (0x1UL << LPGPIO_ODR_OD15_Pos) |
| #define | LPGPIO_ODR_OD15 LPGPIO_ODR_OD15_Msk |
| #define | LPGPIO_BSRR_BS0_Pos (0U) |
| #define | LPGPIO_BSRR_BS0_Msk (0x1UL << LPGPIO_BSRR_BS0_Pos) |
| #define | LPGPIO_BSRR_BS0 LPGPIO_BSRR_BS0_Msk |
| #define | LPGPIO_BSRR_BS1_Pos (1U) |
| #define | LPGPIO_BSRR_BS1_Msk (0x1UL << LPGPIO_BSRR_BS1_Pos) |
| #define | LPGPIO_BSRR_BS1 LPGPIO_BSRR_BS1_Msk |
| #define | LPGPIO_BSRR_BS2_Pos (2U) |
| #define | LPGPIO_BSRR_BS2_Msk (0x1UL << LPGPIO_BSRR_BS2_Pos) |
| #define | LPGPIO_BSRR_BS2 LPGPIO_BSRR_BS2_Msk |
| #define | LPGPIO_BSRR_BS3_Pos (3U) |
| #define | LPGPIO_BSRR_BS3_Msk (0x1UL << LPGPIO_BSRR_BS3_Pos) |
| #define | LPGPIO_BSRR_BS3 LPGPIO_BSRR_BS3_Msk |
| #define | LPGPIO_BSRR_BS4_Pos (4U) |
| #define | LPGPIO_BSRR_BS4_Msk (0x1UL << LPGPIO_BSRR_BS4_Pos) |
| #define | LPGPIO_BSRR_BS4 LPGPIO_BSRR_BS4_Msk |
| #define | LPGPIO_BSRR_BS5_Pos (5U) |
| #define | LPGPIO_BSRR_BS5_Msk (0x1UL << LPGPIO_BSRR_BS5_Pos) |
| #define | LPGPIO_BSRR_BS5 LPGPIO_BSRR_BS5_Msk |
| #define | LPGPIO_BSRR_BS6_Pos (6U) |
| #define | LPGPIO_BSRR_BS6_Msk (0x1UL << LPGPIO_BSRR_BS6_Pos) |
| #define | LPGPIO_BSRR_BS6 LPGPIO_BSRR_BS6_Msk |
| #define | LPGPIO_BSRR_BS7_Pos (7U) |
| #define | LPGPIO_BSRR_BS7_Msk (0x1UL << LPGPIO_BSRR_BS7_Pos) |
| #define | LPGPIO_BSRR_BS7 LPGPIO_BSRR_BS7_Msk |
| #define | LPGPIO_BSRR_BS8_Pos (8U) |
| #define | LPGPIO_BSRR_BS8_Msk (0x1UL << LPGPIO_BSRR_BS8_Pos) |
| #define | LPGPIO_BSRR_BS8 LPGPIO_BSRR_BS8_Msk |
| #define | LPGPIO_BSRR_BS9_Pos (9U) |
| #define | LPGPIO_BSRR_BS9_Msk (0x1UL << LPGPIO_BSRR_BS9_Pos) |
| #define | LPGPIO_BSRR_BS9 LPGPIO_BSRR_BS9_Msk |
| #define | LPGPIO_BSRR_BS10_Pos (10U) |
| #define | LPGPIO_BSRR_BS10_Msk (0x1UL << LPGPIO_BSRR_BS10_Pos) |
| #define | LPGPIO_BSRR_BS10 LPGPIO_BSRR_BS10_Msk |
| #define | LPGPIO_BSRR_BS11_Pos (11U) |
| #define | LPGPIO_BSRR_BS11_Msk (0x1UL << LPGPIO_BSRR_BS11_Pos) |
| #define | LPGPIO_BSRR_BS11 LPGPIO_BSRR_BS11_Msk |
| #define | LPGPIO_BSRR_BS12_Pos (12U) |
| #define | LPGPIO_BSRR_BS12_Msk (0x1UL << LPGPIO_BSRR_BS12_Pos) |
| #define | LPGPIO_BSRR_BS12 LPGPIO_BSRR_BS12_Msk |
| #define | LPGPIO_BSRR_BS13_Pos (13U) |
| #define | LPGPIO_BSRR_BS13_Msk (0x1UL << LPGPIO_BSRR_BS13_Pos) |
| #define | LPGPIO_BSRR_BS13 LPGPIO_BSRR_BS13_Msk |
| #define | LPGPIO_BSRR_BS14_Pos (14U) |
| #define | LPGPIO_BSRR_BS14_Msk (0x1UL << LPGPIO_BSRR_BS14_Pos) |
| #define | LPGPIO_BSRR_BS14 LPGPIO_BSRR_BS14_Msk |
| #define | LPGPIO_BSRR_BS15_Pos (15U) |
| #define | LPGPIO_BSRR_BS15_Msk (0x1UL << LPGPIO_BSRR_BS15_Pos) |
| #define | LPGPIO_BSRR_BS15 LPGPIO_BSRR_BS15_Msk |
| #define | LPGPIO_BSRR_BR0_Pos (16U) |
| #define | LPGPIO_BSRR_BR0_Msk (0x1UL << LPGPIO_BSRR_BR0_Pos) |
| #define | LPGPIO_BSRR_BR0 LPGPIO_BSRR_BR0_Msk |
| #define | LPGPIO_BSRR_BR1_Pos (17U) |
| #define | LPGPIO_BSRR_BR1_Msk (0x1UL << LPGPIO_BSRR_BR1_Pos) |
| #define | LPGPIO_BSRR_BR1 LPGPIO_BSRR_BR1_Msk |
| #define | LPGPIO_BSRR_BR2_Pos (18U) |
| #define | LPGPIO_BSRR_BR2_Msk (0x1UL << LPGPIO_BSRR_BR2_Pos) |
| #define | LPGPIO_BSRR_BR2 LPGPIO_BSRR_BR2_Msk |
| #define | LPGPIO_BSRR_BR3_Pos (19U) |
| #define | LPGPIO_BSRR_BR3_Msk (0x1UL << LPGPIO_BSRR_BR3_Pos) |
| #define | LPGPIO_BSRR_BR3 LPGPIO_BSRR_BR3_Msk |
| #define | LPGPIO_BSRR_BR4_Pos (20U) |
| #define | LPGPIO_BSRR_BR4_Msk (0x1UL << LPGPIO_BSRR_BR4_Pos) |
| #define | LPGPIO_BSRR_BR4 LPGPIO_BSRR_BR4_Msk |
| #define | LPGPIO_BSRR_BR5_Pos (21U) |
| #define | LPGPIO_BSRR_BR5_Msk (0x1UL << LPGPIO_BSRR_BR5_Pos) |
| #define | LPGPIO_BSRR_BR5 LPGPIO_BSRR_BR5_Msk |
| #define | LPGPIO_BSRR_BR6_Pos (22U) |
| #define | LPGPIO_BSRR_BR6_Msk (0x1UL << LPGPIO_BSRR_BR6_Pos) |
| #define | LPGPIO_BSRR_BR6 LPGPIO_BSRR_BR6_Msk |
| #define | LPGPIO_BSRR_BR7_Pos (23U) |
| #define | LPGPIO_BSRR_BR7_Msk (0x1UL << LPGPIO_BSRR_BR7_Pos) |
| #define | LPGPIO_BSRR_BR7 LPGPIO_BSRR_BR7_Msk |
| #define | LPGPIO_BSRR_BR8_Pos (24U) |
| #define | LPGPIO_BSRR_BR8_Msk (0x1UL << LPGPIO_BSRR_BR8_Pos) |
| #define | LPGPIO_BSRR_BR8 LPGPIO_BSRR_BR8_Msk |
| #define | LPGPIO_BSRR_BR9_Pos (25U) |
| #define | LPGPIO_BSRR_BR9_Msk (0x1UL << LPGPIO_BSRR_BR9_Pos) |
| #define | LPGPIO_BSRR_BR9 LPGPIO_BSRR_BR9_Msk |
| #define | LPGPIO_BSRR_BR10_Pos (26U) |
| #define | LPGPIO_BSRR_BR10_Msk (0x1UL << LPGPIO_BSRR_BR10_Pos) |
| #define | LPGPIO_BSRR_BR10 LPGPIO_BSRR_BR10_Msk |
| #define | LPGPIO_BSRR_BR11_Pos (27U) |
| #define | LPGPIO_BSRR_BR11_Msk (0x1UL << LPGPIO_BSRR_BR11_Pos) |
| #define | LPGPIO_BSRR_BR11 LPGPIO_BSRR_BR11_Msk |
| #define | LPGPIO_BSRR_BR12_Pos (28U) |
| #define | LPGPIO_BSRR_BR12_Msk (0x1UL << LPGPIO_BSRR_BR12_Pos) |
| #define | LPGPIO_BSRR_BR12 LPGPIO_BSRR_BR12_Msk |
| #define | LPGPIO_BSRR_BR13_Pos (29U) |
| #define | LPGPIO_BSRR_BR13_Msk (0x1UL << LPGPIO_BSRR_BR13_Pos) |
| #define | LPGPIO_BSRR_BR13 LPGPIO_BSRR_BR13_Msk |
| #define | LPGPIO_BSRR_BR14_Pos (30U) |
| #define | LPGPIO_BSRR_BR14_Msk (0x1UL << LPGPIO_BSRR_BR14_Pos) |
| #define | LPGPIO_BSRR_BR14 LPGPIO_BSRR_BR14_Msk |
| #define | LPGPIO_BSRR_BR15_Pos (31U) |
| #define | LPGPIO_BSRR_BR15_Msk (0x1UL << LPGPIO_BSRR_BR15_Pos) |
| #define | LPGPIO_BSRR_BR15 LPGPIO_BSRR_BR15_Msk |
| #define | LPGPIO_BRR_BR0_Pos (0U) |
| #define | LPGPIO_BRR_BR0_Msk (0x1UL << LPGPIO_BRR_BR0_Pos) |
| #define | LPGPIO_BRR_BR0 LPGPIO_BRR_BR0_Msk |
| #define | LPGPIO_BRR_BR1_Pos (1U) |
| #define | LPGPIO_BRR_BR1_Msk (0x1UL << LPGPIO_BRR_BR1_Pos) |
| #define | LPGPIO_BRR_BR1 LPGPIO_BRR_BR1_Msk |
| #define | LPGPIO_BRR_BR2_Pos (2U) |
| #define | LPGPIO_BRR_BR2_Msk (0x1UL << LPGPIO_BRR_BR2_Pos) |
| #define | LPGPIO_BRR_BR2 LPGPIO_BRR_BR2_Msk |
| #define | LPGPIO_BRR_BR3_Pos (3U) |
| #define | LPGPIO_BRR_BR3_Msk (0x1UL << LPGPIO_BRR_BR3_Pos) |
| #define | LPGPIO_BRR_BR3 LPGPIO_BRR_BR3_Msk |
| #define | LPGPIO_BRR_BR4_Pos (4U) |
| #define | LPGPIO_BRR_BR4_Msk (0x1UL << LPGPIO_BRR_BR4_Pos) |
| #define | LPGPIO_BRR_BR4 LPGPIO_BRR_BR4_Msk |
| #define | LPGPIO_BRR_BR5_Pos (5U) |
| #define | LPGPIO_BRR_BR5_Msk (0x1UL << LPGPIO_BRR_BR5_Pos) |
| #define | LPGPIO_BRR_BR5 LPGPIO_BRR_BR5_Msk |
| #define | LPGPIO_BRR_BR6_Pos (6U) |
| #define | LPGPIO_BRR_BR6_Msk (0x1UL << LPGPIO_BRR_BR6_Pos) |
| #define | LPGPIO_BRR_BR6 LPGPIO_BRR_BR6_Msk |
| #define | LPGPIO_BRR_BR7_Pos (7U) |
| #define | LPGPIO_BRR_BR7_Msk (0x1UL << LPGPIO_BRR_BR7_Pos) |
| #define | LPGPIO_BRR_BR7 LPGPIO_BRR_BR7_Msk |
| #define | LPGPIO_BRR_BR8_Pos (8U) |
| #define | LPGPIO_BRR_BR8_Msk (0x1UL << LPGPIO_BRR_BR8_Pos) |
| #define | LPGPIO_BRR_BR8 LPGPIO_BRR_BR8_Msk |
| #define | LPGPIO_BRR_BR9_Pos (9U) |
| #define | LPGPIO_BRR_BR9_Msk (0x1UL << LPGPIO_BRR_BR9_Pos) |
| #define | LPGPIO_BRR_BR9 LPGPIO_BRR_BR9_Msk |
| #define | LPGPIO_BRR_BR10_Pos (10U) |
| #define | LPGPIO_BRR_BR10_Msk (0x1UL << LPGPIO_BRR_BR10_Pos) |
| #define | LPGPIO_BRR_BR10 LPGPIO_BRR_BR10_Msk |
| #define | LPGPIO_BRR_BR11_Pos (11U) |
| #define | LPGPIO_BRR_BR11_Msk (0x1UL << LPGPIO_BRR_BR11_Pos) |
| #define | LPGPIO_BRR_BR11 LPGPIO_BRR_BR11_Msk |
| #define | LPGPIO_BRR_BR12_Pos (12U) |
| #define | LPGPIO_BRR_BR12_Msk (0x1UL << LPGPIO_BRR_BR12_Pos) |
| #define | LPGPIO_BRR_BR12 LPGPIO_BRR_BR12_Msk |
| #define | LPGPIO_BRR_BR13_Pos (13U) |
| #define | LPGPIO_BRR_BR13_Msk (0x1UL << LPGPIO_BRR_BR13_Pos) |
| #define | LPGPIO_BRR_BR13 LPGPIO_BRR_BR13_Msk |
| #define | LPGPIO_BRR_BR14_Pos (14U) |
| #define | LPGPIO_BRR_BR14_Msk (0x1UL << LPGPIO_BRR_BR14_Pos) |
| #define | LPGPIO_BRR_BR14 LPGPIO_BRR_BR14_Msk |
| #define | LPGPIO_BRR_BR15_Pos (15U) |
| #define | LPGPIO_BRR_BR15_Msk (0x1UL << LPGPIO_BRR_BR15_Pos) |
| #define | LPGPIO_BRR_BR15 LPGPIO_BRR_BR15_Msk |
| #define | LTDC_SSCR_VSH_Pos (0U) |
| #define | LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos) |
| #define | LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk |
| #define | LTDC_SSCR_HSW_Pos (16U) |
| #define | LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos) |
| #define | LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk |
| #define | LTDC_BPCR_AVBP_Pos (0U) |
| #define | LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos) |
| #define | LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk |
| #define | LTDC_BPCR_AHBP_Pos (16U) |
| #define | LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos) |
| #define | LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk |
| #define | LTDC_AWCR_AAH_Pos (0U) |
| #define | LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) |
| #define | LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk |
| #define | LTDC_AWCR_AAW_Pos (16U) |
| #define | LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) |
| #define | LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk |
| #define | LTDC_TWCR_TOTALH_Pos (0U) |
| #define | LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) |
| #define | LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk |
| #define | LTDC_TWCR_TOTALW_Pos (16U) |
| #define | LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) |
| #define | LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk |
| #define | LTDC_GCR_LTDCEN_Pos (0U) |
| #define | LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos) |
| #define | LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk |
| #define | LTDC_GCR_DBW_Pos (4U) |
| #define | LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos) |
| #define | LTDC_GCR_DBW LTDC_GCR_DBW_Msk |
| #define | LTDC_GCR_DGW_Pos (8U) |
| #define | LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos) |
| #define | LTDC_GCR_DGW LTDC_GCR_DGW_Msk |
| #define | LTDC_GCR_DRW_Pos (12U) |
| #define | LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos) |
| #define | LTDC_GCR_DRW LTDC_GCR_DRW_Msk |
| #define | LTDC_GCR_DEN_Pos (16U) |
| #define | LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos) |
| #define | LTDC_GCR_DEN LTDC_GCR_DEN_Msk |
| #define | LTDC_GCR_PCPOL_Pos (28U) |
| #define | LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos) |
| #define | LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk |
| #define | LTDC_GCR_DEPOL_Pos (29U) |
| #define | LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos) |
| #define | LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk |
| #define | LTDC_GCR_VSPOL_Pos (30U) |
| #define | LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos) |
| #define | LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk |
| #define | LTDC_GCR_HSPOL_Pos (31U) |
| #define | LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos) |
| #define | LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk |
| #define | LTDC_SRCR_IMR_Pos (0U) |
| #define | LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos) |
| #define | LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk |
| #define | LTDC_SRCR_VBR_Pos (1U) |
| #define | LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos) |
| #define | LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk |
| #define | LTDC_BCCR_BCBLUE_Pos (0U) |
| #define | LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos) |
| #define | LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk |
| #define | LTDC_BCCR_BCGREEN_Pos (8U) |
| #define | LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos) |
| #define | LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk |
| #define | LTDC_BCCR_BCRED_Pos (16U) |
| #define | LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos) |
| #define | LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk |
| #define | LTDC_IER_LIE_Pos (0U) |
| #define | LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos) |
| #define | LTDC_IER_LIE LTDC_IER_LIE_Msk |
| #define | LTDC_IER_FUIE_Pos (1U) |
| #define | LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos) |
| #define | LTDC_IER_FUIE LTDC_IER_FUIE_Msk |
| #define | LTDC_IER_TERRIE_Pos (2U) |
| #define | LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos) |
| #define | LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk |
| #define | LTDC_IER_RRIE_Pos (3U) |
| #define | LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos) |
| #define | LTDC_IER_RRIE LTDC_IER_RRIE_Msk |
| #define | LTDC_ISR_LIF_Pos (0U) |
| #define | LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos) |
| #define | LTDC_ISR_LIF LTDC_ISR_LIF_Msk |
| #define | LTDC_ISR_FUIF_Pos (1U) |
| #define | LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos) |
| #define | LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk |
| #define | LTDC_ISR_TERRIF_Pos (2U) |
| #define | LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos) |
| #define | LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk |
| #define | LTDC_ISR_RRIF_Pos (3U) |
| #define | LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos) |
| #define | LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk |
| #define | LTDC_ICR_CLIF_Pos (0U) |
| #define | LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos) |
| #define | LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk |
| #define | LTDC_ICR_CFUIF_Pos (1U) |
| #define | LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos) |
| #define | LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk |
| #define | LTDC_ICR_CTERRIF_Pos (2U) |
| #define | LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos) |
| #define | LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk |
| #define | LTDC_ICR_CRRIF_Pos (3U) |
| #define | LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos) |
| #define | LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk |
| #define | LTDC_LIPCR_LIPOS_Pos (0U) |
| #define | LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos) |
| #define | LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk |
| #define | LTDC_CPSR_CYPOS_Pos (0U) |
| #define | LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos) |
| #define | LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk |
| #define | LTDC_CPSR_CXPOS_Pos (16U) |
| #define | LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos) |
| #define | LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk |
| #define | LTDC_CDSR_VDES_Pos (0U) |
| #define | LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos) |
| #define | LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk |
| #define | LTDC_CDSR_HDES_Pos (1U) |
| #define | LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos) |
| #define | LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk |
| #define | LTDC_CDSR_VSYNCS_Pos (2U) |
| #define | LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos) |
| #define | LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk |
| #define | LTDC_CDSR_HSYNCS_Pos (3U) |
| #define | LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos) |
| #define | LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk |
| #define | LTDC_LxCR_LEN_Pos (0U) |
| #define | LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos) |
| #define | LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk |
| #define | LTDC_LxCR_COLKEN_Pos (1U) |
| #define | LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos) |
| #define | LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk |
| #define | LTDC_LxCR_CLUTEN_Pos (4U) |
| #define | LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos) |
| #define | LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk |
| #define | LTDC_LxWHPCR_WHSTPOS_Pos (0U) |
| #define | LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos) |
| #define | LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk |
| #define | LTDC_LxWHPCR_WHSPPOS_Pos (16U) |
| #define | LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos) |
| #define | LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk |
| #define | LTDC_LxWVPCR_WVSTPOS_Pos (0U) |
| #define | LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos) |
| #define | LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk |
| #define | LTDC_LxWVPCR_WVSPPOS_Pos (16U) |
| #define | LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos) |
| #define | LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk |
| #define | LTDC_LxCKCR_CKBLUE_Pos (0U) |
| #define | LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos) |
| #define | LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk |
| #define | LTDC_LxCKCR_CKGREEN_Pos (8U) |
| #define | LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos) |
| #define | LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk |
| #define | LTDC_LxCKCR_CKRED_Pos (16U) |
| #define | LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos) |
| #define | LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk |
| #define | LTDC_LxPFCR_PF_Pos (0U) |
| #define | LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) |
| #define | LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk |
| #define | LTDC_LxCACR_CONSTA_Pos (0U) |
| #define | LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos) |
| #define | LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk |
| #define | LTDC_LxDCCR_DCBLUE_Pos (0U) |
| #define | LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos) |
| #define | LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk |
| #define | LTDC_LxDCCR_DCGREEN_Pos (8U) |
| #define | LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos) |
| #define | LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk |
| #define | LTDC_LxDCCR_DCRED_Pos (16U) |
| #define | LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos) |
| #define | LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk |
| #define | LTDC_LxDCCR_DCALPHA_Pos (24U) |
| #define | LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos) |
| #define | LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk |
| #define | LTDC_LxBFCR_BF2_Pos (0U) |
| #define | LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) |
| #define | LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk |
| #define | LTDC_LxBFCR_BF1_Pos (8U) |
| #define | LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) |
| #define | LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk |
| #define | LTDC_LxCFBAR_CFBADD_Pos (0U) |
| #define | LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) |
| #define | LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk |
| #define | LTDC_LxCFBLR_CFBLL_Pos (0U) |
| #define | LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos) |
| #define | LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk |
| #define | LTDC_LxCFBLR_CFBP_Pos (16U) |
| #define | LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos) |
| #define | LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk |
| #define | LTDC_LxCFBLNR_CFBLNBR_Pos (0U) |
| #define | LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos) |
| #define | LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk |
| #define | LTDC_LxCLUTWR_BLUE_Pos (0U) |
| #define | LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos) |
| #define | LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk |
| #define | LTDC_LxCLUTWR_GREEN_Pos (8U) |
| #define | LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos) |
| #define | LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk |
| #define | LTDC_LxCLUTWR_RED_Pos (16U) |
| #define | LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos) |
| #define | LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk |
| #define | LTDC_LxCLUTWR_CLUTADD_Pos (24U) |
| #define | LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos) |
| #define | LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk |
| #define | ICACHE_CR_EN_Pos (0U) |
| #define | ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) |
| #define | ICACHE_CR_EN ICACHE_CR_EN_Msk |
| #define | ICACHE_CR_CACHEINV_Pos (1U) |
| #define | ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) |
| #define | ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk |
| #define | ICACHE_CR_WAYSEL_Pos (2U) |
| #define | ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) |
| #define | ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk |
| #define | ICACHE_CR_HITMEN_Pos (16U) |
| #define | ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) |
| #define | ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk |
| #define | ICACHE_CR_MISSMEN_Pos (17U) |
| #define | ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) |
| #define | ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk |
| #define | ICACHE_CR_HITMRST_Pos (18U) |
| #define | ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) |
| #define | ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk |
| #define | ICACHE_CR_MISSMRST_Pos (19U) |
| #define | ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) |
| #define | ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk |
| #define | ICACHE_SR_BUSYF_Pos (0U) |
| #define | ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) |
| #define | ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk |
| #define | ICACHE_SR_BSYENDF_Pos (1U) |
| #define | ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) |
| #define | ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk |
| #define | ICACHE_SR_ERRF_Pos (2U) |
| #define | ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) |
| #define | ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk |
| #define | ICACHE_IER_BSYENDIE_Pos (1U) |
| #define | ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) |
| #define | ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk |
| #define | ICACHE_IER_ERRIE_Pos (2U) |
| #define | ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) |
| #define | ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk |
| #define | ICACHE_FCR_CBSYENDF_Pos (1U) |
| #define | ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) |
| #define | ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk |
| #define | ICACHE_FCR_CERRF_Pos (2U) |
| #define | ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) |
| #define | ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk |
| #define | ICACHE_HMONR_HITMON_Pos (0U) |
| #define | ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) |
| #define | ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk |
| #define | ICACHE_MMONR_MISSMON_Pos (0U) |
| #define | ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) |
| #define | ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk |
| #define | ICACHE_CRRx_BASEADDR_Pos (0U) |
| #define | ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) |
| #define | ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk |
| #define | ICACHE_CRRx_RSIZE_Pos (9U) |
| #define | ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) |
| #define | ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk |
| #define | ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) |
| #define | ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) |
| #define | ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) |
| #define | ICACHE_CRRx_REN_Pos (15U) |
| #define | ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) |
| #define | ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk |
| #define | ICACHE_CRRx_REMAPADDR_Pos (16U) |
| #define | ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) |
| #define | ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk |
| #define | ICACHE_CRRx_MSTSEL_Pos (28U) |
| #define | ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) |
| #define | ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk |
| #define | ICACHE_CRRx_HBURST_Pos (31U) |
| #define | ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) |
| #define | ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk |
| #define | DCACHE_CR_EN_Pos (0U) |
| #define | DCACHE_CR_EN_Msk (0x1UL << DCACHE_CR_EN_Pos) |
| #define | DCACHE_CR_EN DCACHE_CR_EN_Msk |
| #define | DCACHE_CR_CACHEINV_Pos (1U) |
| #define | DCACHE_CR_CACHEINV_Msk (0x1UL << DCACHE_CR_CACHEINV_Pos) |
| #define | DCACHE_CR_CACHEINV DCACHE_CR_CACHEINV_Msk |
| #define | DCACHE_CR_CACHECMD_Pos (8U) |
| #define | DCACHE_CR_CACHECMD_Msk (0x7UL << DCACHE_CR_CACHECMD_Pos) |
| #define | DCACHE_CR_CACHECMD DCACHE_CR_CACHECMD_Msk |
| #define | DCACHE_CR_CACHECMD_0 (0x1UL << DCACHE_CR_CACHECMD_Pos) |
| #define | DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) |
| #define | DCACHE_CR_CACHECMD_2 (0x4UL << DCACHE_CR_CACHECMD_Pos) |
| #define | DCACHE_CR_STARTCMD_Pos (11U) |
| #define | DCACHE_CR_STARTCMD_Msk (0x1UL << DCACHE_CR_STARTCMD_Pos) |
| #define | DCACHE_CR_STARTCMD DCACHE_CR_STARTCMD_Msk |
| #define | DCACHE_CR_RHITMEN_Pos (16U) |
| #define | DCACHE_CR_RHITMEN_Msk (0x1UL << DCACHE_CR_RHITMEN_Pos) |
| #define | DCACHE_CR_RHITMEN DCACHE_CR_RHITMEN_Msk |
| #define | DCACHE_CR_RMISSMEN_Pos (17U) |
| #define | DCACHE_CR_RMISSMEN_Msk (0x1UL << DCACHE_CR_RMISSMEN_Pos) |
| #define | DCACHE_CR_RMISSMEN DCACHE_CR_RMISSMEN_Msk |
| #define | DCACHE_CR_RHITMRST_Pos (18U) |
| #define | DCACHE_CR_RHITMRST_Msk (0x1UL << DCACHE_CR_RHITMRST_Pos) |
| #define | DCACHE_CR_RHITMRST DCACHE_CR_RHITMRST_Msk |
| #define | DCACHE_CR_RMISSMRST_Pos (19U) |
| #define | DCACHE_CR_RMISSMRST_Msk (0x1UL << DCACHE_CR_RMISSMRST_Pos) |
| #define | DCACHE_CR_RMISSMRST DCACHE_CR_RMISSMRST_Msk |
| #define | DCACHE_CR_WHITMEN_Pos (20U) |
| #define | DCACHE_CR_WHITMEN_Msk (0x1UL << DCACHE_CR_WHITMEN_Pos) |
| #define | DCACHE_CR_WHITMEN DCACHE_CR_WHITMEN_Msk |
| #define | DCACHE_CR_WMISSMEN_Pos (21U) |
| #define | DCACHE_CR_WMISSMEN_Msk (0x1UL << DCACHE_CR_WMISSMEN_Pos) |
| #define | DCACHE_CR_WMISSMEN DCACHE_CR_WMISSMEN_Msk |
| #define | DCACHE_CR_WHITMRST_Pos (22U) |
| #define | DCACHE_CR_WHITMRST_Msk (0x1UL << DCACHE_CR_WHITMRST_Pos) |
| #define | DCACHE_CR_WHITMRST DCACHE_CR_WHITMRST_Msk |
| #define | DCACHE_CR_WMISSMRST_Pos (23U) |
| #define | DCACHE_CR_WMISSMRST_Msk (0x1UL << DCACHE_CR_WMISSMRST_Pos) |
| #define | DCACHE_CR_WMISSMRST DCACHE_CR_WMISSMRST_Msk |
| #define | DCACHE_CR_HBURST_Pos (31U) |
| #define | DCACHE_CR_HBURST_Msk (0x1UL << DCACHE_CR_HBURST_Pos) |
| #define | DCACHE_CR_HBURST DCACHE_CR_HBURST_Msk |
| #define | DCACHE_SR_BUSYF_Pos (0U) |
| #define | DCACHE_SR_BUSYF_Msk (0x1UL << DCACHE_SR_BUSYF_Pos) |
| #define | DCACHE_SR_BUSYF DCACHE_SR_BUSYF_Msk |
| #define | DCACHE_SR_BSYENDF_Pos (1U) |
| #define | DCACHE_SR_BSYENDF_Msk (0x1UL << DCACHE_SR_BSYENDF_Pos) |
| #define | DCACHE_SR_BSYENDF DCACHE_SR_BSYENDF_Msk |
| #define | DCACHE_SR_ERRF_Pos (2U) |
| #define | DCACHE_SR_ERRF_Msk (0x1UL << DCACHE_SR_ERRF_Pos) |
| #define | DCACHE_SR_ERRF DCACHE_SR_ERRF_Msk |
| #define | DCACHE_SR_BUSYCMDF_Pos (3U) |
| #define | DCACHE_SR_BUSYCMDF_Msk (0x1UL << DCACHE_SR_BUSYCMDF_Pos) |
| #define | DCACHE_SR_BUSYCMDF DCACHE_SR_BUSYCMDF_Msk |
| #define | DCACHE_SR_CMDENDF_Pos (4U) |
| #define | DCACHE_SR_CMDENDF_Msk (0x1UL << DCACHE_SR_CMDENDF_Pos) |
| #define | DCACHE_SR_CMDENDF DCACHE_SR_CMDENDF_Msk |
| #define | DCACHE_IER_BSYENDIE_Pos (1U) |
| #define | DCACHE_IER_BSYENDIE_Msk (0x1UL << DCACHE_IER_BSYENDIE_Pos) |
| #define | DCACHE_IER_BSYENDIE DCACHE_IER_BSYENDIE_Msk |
| #define | DCACHE_IER_ERRIE_Pos (2U) |
| #define | DCACHE_IER_ERRIE_Msk (0x1UL << DCACHE_IER_ERRIE_Pos) |
| #define | DCACHE_IER_ERRIE DCACHE_IER_ERRIE_Msk |
| #define | DCACHE_IER_CMDENDIE_Pos (4U) |
| #define | DCACHE_IER_CMDENDIE_Msk (0x1UL << DCACHE_IER_CMDENDIE_Pos) |
| #define | DCACHE_IER_CMDENDIE DCACHE_IER_CMDENDIE_Msk |
| #define | DCACHE_FCR_CBSYENDF_Pos (1U) |
| #define | DCACHE_FCR_CBSYENDF_Msk (0x1UL << DCACHE_FCR_CBSYENDF_Pos) |
| #define | DCACHE_FCR_CBSYENDF DCACHE_FCR_CBSYENDF_Msk |
| #define | DCACHE_FCR_CERRF_Pos (2U) |
| #define | DCACHE_FCR_CERRF_Msk (0x1UL << DCACHE_FCR_CERRF_Pos) |
| #define | DCACHE_FCR_CERRF DCACHE_FCR_CERRF_Msk |
| #define | DCACHE_FCR_CCMDENDF_Pos (4U) |
| #define | DCACHE_FCR_CCMDENDF_Msk (0x1UL << DCACHE_FCR_CCMDENDF_Pos) |
| #define | DCACHE_FCR_CCMDENDF DCACHE_FCR_CCMDENDF_Msk |
| #define | DCACHE_RHMONR_RHITMON_Pos (0U) |
| #define | DCACHE_RHMONR_RHITMON_Msk (0xFFFFFFFFUL << DCACHE_RHMONR_RHITMON_Pos) |
| #define | DCACHE_RHMONR_RHITMON DCACHE_RHMONR_RHITMON_Msk |
| #define | DCACHE_RMMONR_RMISSMON_Pos (0U) |
| #define | DCACHE_RMMONR_RMISSMON_Msk (0xFFFFUL << DCACHE_RMMONR_RMISSMON_Pos) |
| #define | DCACHE_RMMONR_RMISSMON DCACHE_RMMONR_RMISSMON_Msk |
| #define | DCACHE_WHMONR_WHITMON_Pos (0U) |
| #define | DCACHE_WHMONR_WHITMON_Msk (0xFFFFFFFFUL << DCACHE_WHMONR_WHITMON_Pos) |
| #define | DCACHE_WHMONR_WHITMON DCACHE_WHMONR_WHITMON_Msk |
| #define | DCACHE_WMMONR_WMISSMON_Pos (0U) |
| #define | DCACHE_WMMONR_WMISSMON_Msk (0xFFFFUL << DCACHE_WMMONR_WMISSMON_Pos) |
| #define | DCACHE_WMMONR_WMISSMON DCACHE_WMMONR_WMISSMON_Msk |
| #define | DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos (0U) |
| #define | DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk (0xFFFFFFE0UL << DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos) |
| #define | DCACHE_CMDRSADDRR_CMDSTARTADDR DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk |
| #define | DCACHE_CMDREADDRR_CMDENDADDR_Pos (0U) |
| #define | DCACHE_CMDREADDRR_CMDENDADDR_Msk (0xFFFFFFE0UL << DCACHE_CMDREADDRR_CMDENDADDR_Pos) |
| #define | DCACHE_CMDREADDRR_CMDENDADDR DCACHE_CMDREADDRR_CMDENDADDR_Msk |
| #define | COMP_WINDOW_MODE_SUPPORT |
| #define | COMP_CSR_EN_Pos (0U) |
| #define | COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) |
| #define | COMP_CSR_EN COMP_CSR_EN_Msk |
| #define | COMP_CSR_INMSEL_Pos (4U) |
| #define | COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) |
| #define | COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk |
| #define | COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) |
| #define | COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) |
| #define | COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) |
| #define | COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) |
| #define | COMP_CSR_INPSEL_Pos (8U) |
| #define | COMP_CSR_INPSEL_Msk (0x3UL << COMP_CSR_INPSEL_Pos) |
| #define | COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk |
| #define | COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) |
| #define | COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) |
| #define | COMP_CSR_WINMODE_Pos (11U) |
| #define | COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) |
| #define | COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk |
| #define | COMP_CSR_WINOUT_Pos (14U) |
| #define | COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) |
| #define | COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk |
| #define | COMP_CSR_POLARITY_Pos (15U) |
| #define | COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) |
| #define | COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk |
| #define | COMP_CSR_HYST_Pos (16U) |
| #define | COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) |
| #define | COMP_CSR_HYST COMP_CSR_HYST_Msk |
| #define | COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) |
| #define | COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) |
| #define | COMP_CSR_PWRMODE_Pos (18U) |
| #define | COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) |
| #define | COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk |
| #define | COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) |
| #define | COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) |
| #define | COMP_CSR_BLANKSEL_Pos (20U) |
| #define | COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) |
| #define | COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk |
| #define | COMP_CSR_BLANKSEL_0 (0x01UL << COMP_CSR_BLANKSEL_Pos) |
| #define | COMP_CSR_BLANKSEL_1 (0x02UL << COMP_CSR_BLANKSEL_Pos) |
| #define | COMP_CSR_BLANKSEL_2 (0x04UL << COMP_CSR_BLANKSEL_Pos) |
| #define | COMP_CSR_BLANKSEL_3 (0x08UL << COMP_CSR_BLANKSEL_Pos) |
| #define | COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) |
| #define | COMP_CSR_VALUE_Pos (30U) |
| #define | COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) |
| #define | COMP_CSR_VALUE COMP_CSR_VALUE_Msk |
| #define | COMP_CSR_LOCK_Pos (31U) |
| #define | COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) |
| #define | COMP_CSR_LOCK COMP_CSR_LOCK_Msk |
| #define | OPAMP_CSR_OPAEN_Pos (0U) |
| #define | OPAMP_CSR_OPAEN_Msk (0x1UL << OPAMP_CSR_OPAEN_Pos) |
| #define | OPAMP_CSR_OPAEN OPAMP_CSR_OPAEN_Msk |
| #define | OPAMP_CSR_OPALPM_Pos (1U) |
| #define | OPAMP_CSR_OPALPM_Msk (0x1UL << OPAMP_CSR_OPALPM_Pos) |
| #define | OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk |
| #define | OPAMP_CSR_OPAMODE_Pos (2U) |
| #define | OPAMP_CSR_OPAMODE_Msk (0x3UL << OPAMP_CSR_OPAMODE_Pos) |
| #define | OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk |
| #define | OPAMP_CSR_OPAMODE_0 (0x1UL << OPAMP_CSR_OPAMODE_Pos) |
| #define | OPAMP_CSR_OPAMODE_1 (0x2UL << OPAMP_CSR_OPAMODE_Pos) |
| #define | OPAMP_CSR_PGA_GAIN_Pos (4U) |
| #define | OPAMP_CSR_PGA_GAIN_Msk (0x3UL << OPAMP_CSR_PGA_GAIN_Pos) |
| #define | OPAMP_CSR_PGA_GAIN OPAMP_CSR_PGA_GAIN_Msk |
| #define | OPAMP_CSR_PGA_GAIN_0 (0x1UL << OPAMP_CSR_PGA_GAIN_Pos) |
| #define | OPAMP_CSR_PGA_GAIN_1 (0x2UL << OPAMP_CSR_PGA_GAIN_Pos) |
| #define | OPAMP_CSR_VM_SEL_Pos (8U) |
| #define | OPAMP_CSR_VM_SEL_Msk (0x3UL << OPAMP_CSR_VM_SEL_Pos) |
| #define | OPAMP_CSR_VM_SEL OPAMP_CSR_VM_SEL_Msk |
| #define | OPAMP_CSR_VM_SEL_0 (0x1UL << OPAMP_CSR_VM_SEL_Pos) |
| #define | OPAMP_CSR_VM_SEL_1 (0x2UL << OPAMP_CSR_VM_SEL_Pos) |
| #define | OPAMP_CSR_VP_SEL_Pos (10U) |
| #define | OPAMP_CSR_VP_SEL_Msk (0x1UL << OPAMP_CSR_VP_SEL_Pos) |
| #define | OPAMP_CSR_VP_SEL OPAMP_CSR_VP_SEL_Msk |
| #define | OPAMP_CSR_CALON_Pos (12U) |
| #define | OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) |
| #define | OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk |
| #define | OPAMP_CSR_CALSEL_Pos (13U) |
| #define | OPAMP_CSR_CALSEL_Msk (0x1UL << OPAMP_CSR_CALSEL_Pos) |
| #define | OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk |
| #define | OPAMP_CSR_USERTRIM_Pos (14U) |
| #define | OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) |
| #define | OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk |
| #define | OPAMP_CSR_CALOUT_Pos (15U) |
| #define | OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) |
| #define | OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk |
| #define | OPAMP_CSR_HSM_Pos (30U) |
| #define | OPAMP_CSR_HSM_Msk (0x1UL << OPAMP_CSR_HSM_Pos) |
| #define | OPAMP_CSR_HSM OPAMP_CSR_HSM_Msk |
| #define | OPAMP_CSR_OPARANGE_Pos (31U) |
| #define | OPAMP_CSR_OPARANGE_Msk (0x1UL << OPAMP_CSR_OPARANGE_Pos) |
| #define | OPAMP_CSR_OPARANGE OPAMP_CSR_OPARANGE_Msk |
| #define | OPAMP_OTR_TRIMOFFSETN_Pos (0U) |
| #define | OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) |
| #define | OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk |
| #define | OPAMP_OTR_TRIMOFFSETP_Pos (8U) |
| #define | OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) |
| #define | OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk |
| #define | OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0U) |
| #define | OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) |
| #define | OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk |
| #define | OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8U) |
| #define | OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) |
| #define | OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk |
| #define | MDF_GCR_TRGO_Pos (0U) |
| #define | MDF_GCR_TRGO_Msk (0x1UL << MDF_GCR_TRGO_Pos) |
| #define | MDF_GCR_TRGO MDF_GCR_TRGO_Msk |
| #define | MDF_GCR_ILVNB_Pos (4U) |
| #define | MDF_GCR_ILVNB_Msk (0xFUL << MDF_GCR_ILVNB_Pos) |
| #define | MDF_GCR_ILVNB MDF_GCR_ILVNB_Msk |
| #define | MDF_CKGCR_CKDEN_Pos (0U) |
| #define | MDF_CKGCR_CKDEN_Msk (0x1UL << MDF_CKGCR_CKDEN_Pos) |
| #define | MDF_CKGCR_CKDEN MDF_CKGCR_CKDEN_Msk |
| #define | MDF_CKGCR_CCK0EN_Pos (1U) |
| #define | MDF_CKGCR_CCK0EN_Msk (0x1UL << MDF_CKGCR_CCK0EN_Pos) |
| #define | MDF_CKGCR_CCK0EN MDF_CKGCR_CCK0EN_Msk |
| #define | MDF_CKGCR_CCK1EN_Pos (2U) |
| #define | MDF_CKGCR_CCK1EN_Msk (0x1UL << MDF_CKGCR_CCK1EN_Pos) |
| #define | MDF_CKGCR_CCK1EN MDF_CKGCR_CCK1EN_Msk |
| #define | MDF_CKGCR_CKGMOD_Pos (4U) |
| #define | MDF_CKGCR_CKGMOD_Msk (0x1UL << MDF_CKGCR_CKGMOD_Pos) |
| #define | MDF_CKGCR_CKGMOD MDF_CKGCR_CKGMOD_Msk |
| #define | MDF_CKGCR_CCK0DIR_Pos (5U) |
| #define | MDF_CKGCR_CCK0DIR_Msk (0x1UL << MDF_CKGCR_CCK0DIR_Pos) |
| #define | MDF_CKGCR_CCK0DIR MDF_CKGCR_CCK0DIR_Msk |
| #define | MDF_CKGCR_CCK1DIR_Pos (6U) |
| #define | MDF_CKGCR_CCK1DIR_Msk (0x1UL << MDF_CKGCR_CCK1DIR_Pos) |
| #define | MDF_CKGCR_CCK1DIR MDF_CKGCR_CCK1DIR_Msk |
| #define | MDF_CKGCR_TRGSENS_Pos (8U) |
| #define | MDF_CKGCR_TRGSENS_Msk (0x1UL << MDF_CKGCR_TRGSENS_Pos) |
| #define | MDF_CKGCR_TRGSENS MDF_CKGCR_TRGSENS_Msk |
| #define | MDF_CKGCR_TRGSRC_Pos (12U) |
| #define | MDF_CKGCR_TRGSRC_Msk (0xFUL << MDF_CKGCR_TRGSRC_Pos) |
| #define | MDF_CKGCR_TRGSRC MDF_CKGCR_TRGSRC_Msk |
| #define | MDF_CKGCR_TRGSRC_0 (0x1UL << MDF_CKGCR_TRGSRC_Pos) |
| #define | MDF_CKGCR_TRGSRC_1 (0x2UL << MDF_CKGCR_TRGSRC_Pos) |
| #define | MDF_CKGCR_TRGSRC_2 (0x4UL << MDF_CKGCR_TRGSRC_Pos) |
| #define | MDF_CKGCR_TRGSRC_3 (0x8UL << MDF_CKGCR_TRGSRC_Pos) |
| #define | MDF_CKGCR_CCKDIV_Pos (16U) |
| #define | MDF_CKGCR_CCKDIV_Msk (0xFUL << MDF_CKGCR_CCKDIV_Pos) |
| #define | MDF_CKGCR_CCKDIV MDF_CKGCR_CCKDIV_Msk |
| #define | MDF_CKGCR_PROCDIV_Pos (24U) |
| #define | MDF_CKGCR_PROCDIV_Msk (0x7FUL << MDF_CKGCR_PROCDIV_Pos) |
| #define | MDF_CKGCR_PROCDIV MDF_CKGCR_PROCDIV_Msk |
| #define | MDF_CKGCR_CCKACTIVE_Pos (31U) |
| #define | MDF_CKGCR_CCKACTIVE_Msk (0x1UL << MDF_CKGCR_CCKACTIVE_Pos) |
| #define | MDF_CKGCR_CCKACTIVE MDF_CKGCR_CCKACTIVE_Msk |
| #define | MDF_OR_OPTION_Pos (0U) |
| #define | MDF_OR_OPTION_Msk (0xFFFFFFFFUL << MDF_OR_OPTION_Pos) |
| #define | MDF_OR_OPTION MDF_OR_OPTION_Msk |
| #define | MDF_SITFCR_SITFEN_Pos (0U) |
| #define | MDF_SITFCR_SITFEN_Msk (0x1UL << MDF_SITFCR_SITFEN_Pos) |
| #define | MDF_SITFCR_SITFEN MDF_SITFCR_SITFEN_Msk |
| #define | MDF_SITFCR_SCKSRC_Pos (1U) |
| #define | MDF_SITFCR_SCKSRC_Msk (0x3UL << MDF_SITFCR_SCKSRC_Pos) |
| #define | MDF_SITFCR_SCKSRC MDF_SITFCR_SCKSRC_Msk |
| #define | MDF_SITFCR_SCKSRC_0 (0x1UL << MDF_SITFCR_SCKSRC_Pos) |
| #define | MDF_SITFCR_SCKSRC_1 (0x2UL << MDF_SITFCR_SCKSRC_Pos) |
| #define | MDF_SITFCR_SITFMOD_Pos (4U) |
| #define | MDF_SITFCR_SITFMOD_Msk (0x3UL << MDF_SITFCR_SITFMOD_Pos) |
| #define | MDF_SITFCR_SITFMOD MDF_SITFCR_SITFMOD_Msk |
| #define | MDF_SITFCR_SITFMOD_0 (0x1UL << MDF_SITFCR_SITFMOD_Pos) |
| #define | MDF_SITFCR_SITFMOD_1 (0x2UL << MDF_SITFCR_SITFMOD_Pos) |
| #define | MDF_SITFCR_STH_Pos (8U) |
| #define | MDF_SITFCR_STH_Msk (0x1FUL << MDF_SITFCR_STH_Pos) |
| #define | MDF_SITFCR_STH MDF_SITFCR_STH_Msk |
| #define | MDF_SITFCR_SITFACTIVE_Pos (31U) |
| #define | MDF_SITFCR_SITFACTIVE_Msk (0x1UL << MDF_SITFCR_SITFACTIVE_Pos) |
| #define | MDF_SITFCR_SITFACTIVE MDF_SITFCR_SITFACTIVE_Msk |
| #define | MDF_BSMXCR_BSSEL_Pos (0U) |
| #define | MDF_BSMXCR_BSSEL_Msk (0x1FUL << MDF_BSMXCR_BSSEL_Pos) |
| #define | MDF_BSMXCR_BSSEL MDF_BSMXCR_BSSEL_Msk |
| #define | MDF_BSMXCR_BSSEL_0 (0x1UL << MDF_BSMXCR_BSSEL_Pos) |
| #define | MDF_BSMXCR_BSSEL_1 (0x2UL << MDF_BSMXCR_BSSEL_Pos) |
| #define | MDF_BSMXCR_BSSEL_2 (0x4UL << MDF_BSMXCR_BSSEL_Pos) |
| #define | MDF_BSMXCR_BSSEL_3 (0x8UL << MDF_BSMXCR_BSSEL_Pos) |
| #define | MDF_BSMXCR_BSSEL_4 (0x10UL << MDF_BSMXCR_BSSEL_Pos) |
| #define | MDF_BSMXCR_BSMXACTIVATE_Pos (31U) |
| #define | MDF_BSMXCR_BSMXACTIVATE_Msk (0x1UL << MDF_BSMXCR_BSMXACTIVATE_Pos) |
| #define | MDF_BSMXCR_BSMXACTIVATE MDF_BSMXCR_BSMXACTIVATE_Msk |
| #define | MDF_DFLTCR_DFLTEN_Pos (0U) |
| #define | MDF_DFLTCR_DFLTEN_Msk (0x1UL << MDF_DFLTCR_DFLTEN_Pos) |
| #define | MDF_DFLTCR_DFLTEN MDF_DFLTCR_DFLTEN_Msk |
| #define | MDF_DFLTCR_DMAEN_Pos (1U) |
| #define | MDF_DFLTCR_DMAEN_Msk (0x1UL << MDF_DFLTCR_DMAEN_Pos) |
| #define | MDF_DFLTCR_DMAEN MDF_DFLTCR_DMAEN_Msk |
| #define | MDF_DFLTCR_FTH_Pos (2U) |
| #define | MDF_DFLTCR_FTH_Msk (0x1UL << MDF_DFLTCR_FTH_Pos) |
| #define | MDF_DFLTCR_FTH MDF_DFLTCR_FTH_Msk |
| #define | MDF_DFLTCR_ACQMOD_Pos (4U) |
| #define | MDF_DFLTCR_ACQMOD_Msk (0x7UL << MDF_DFLTCR_ACQMOD_Pos) |
| #define | MDF_DFLTCR_ACQMOD MDF_DFLTCR_ACQMOD_Msk |
| #define | MDF_DFLTCR_ACQMOD_0 (0x1UL << MDF_DFLTCR_ACQMOD_Pos) |
| #define | MDF_DFLTCR_ACQMOD_1 (0x2UL << MDF_DFLTCR_ACQMOD_Pos) |
| #define | MDF_DFLTCR_ACQMOD_2 (0x4UL << MDF_DFLTCR_ACQMOD_Pos) |
| #define | MDF_DFLTCR_TRGSENS_Pos (8U) |
| #define | MDF_DFLTCR_TRGSENS_Msk (0x1UL << MDF_DFLTCR_TRGSENS_Pos) |
| #define | MDF_DFLTCR_TRGSENS MDF_DFLTCR_TRGSENS_Msk |
| #define | MDF_DFLTCR_TRGSRC_Pos (12U) |
| #define | MDF_DFLTCR_TRGSRC_Msk (0xFUL << MDF_DFLTCR_TRGSRC_Pos) |
| #define | MDF_DFLTCR_TRGSRC MDF_DFLTCR_TRGSRC_Msk |
| #define | MDF_DFLTCR_TRGSRC_0 (0x1UL << MDF_DFLTCR_TRGSRC_Pos) |
| #define | MDF_DFLTCR_TRGSRC_1 (0x2UL << MDF_DFLTCR_TRGSRC_Pos) |
| #define | MDF_DFLTCR_TRGSRC_2 (0x4UL << MDF_DFLTCR_TRGSRC_Pos) |
| #define | MDF_DFLTCR_TRGSRC_3 (0x8UL << MDF_DFLTCR_TRGSRC_Pos) |
| #define | MDF_DFLTCR_SNPSFMT_Pos (16U) |
| #define | MDF_DFLTCR_SNPSFMT_Msk (0x1UL << MDF_DFLTCR_SNPSFMT_Pos) |
| #define | MDF_DFLTCR_SNPSFMT MDF_DFLTCR_SNPSFMT_Msk |
| #define | MDF_DFLTCR_NBDIS_Pos (20U) |
| #define | MDF_DFLTCR_NBDIS_Msk (0xFFUL << MDF_DFLTCR_NBDIS_Pos) |
| #define | MDF_DFLTCR_NBDIS MDF_DFLTCR_NBDIS_Msk |
| #define | MDF_DFLTCR_DFLTRUN_Pos (30U) |
| #define | MDF_DFLTCR_DFLTRUN_Msk (0x1UL << MDF_DFLTCR_DFLTRUN_Pos) |
| #define | MDF_DFLTCR_DFLTRUN MDF_DFLTCR_DFLTRUN_Msk |
| #define | MDF_DFLTCR_DFLTACTIVE_Pos (31U) |
| #define | MDF_DFLTCR_DFLTACTIVE_Msk (0x1UL << MDF_DFLTCR_DFLTACTIVE_Pos) |
| #define | MDF_DFLTCR_DFLTACTIVE MDF_DFLTCR_DFLTACTIVE_Msk |
| #define | MDF_DFLTCICR_DATSRC_Pos (0U) |
| #define | MDF_DFLTCICR_DATSRC_Msk (0x3UL << MDF_DFLTCICR_DATSRC_Pos) |
| #define | MDF_DFLTCICR_DATSRC MDF_DFLTCICR_DATSRC_Msk |
| #define | MDF_DFLTCICR_DATSRC_0 (0x1UL << MDF_DFLTCICR_DATSRC_Pos) |
| #define | MDF_DFLTCICR_DATSRC_1 (0x2UL << MDF_DFLTCICR_DATSRC_Pos) |
| #define | MDF_DFLTCICR_CICMOD_Pos (4U) |
| #define | MDF_DFLTCICR_CICMOD_Msk (0x7UL << MDF_DFLTCICR_CICMOD_Pos) |
| #define | MDF_DFLTCICR_CICMOD MDF_DFLTCICR_CICMOD_Msk |
| #define | MDF_DFLTCICR_CICMOD_0 (0x1UL << MDF_DFLTCICR_CICMOD_Pos) |
| #define | MDF_DFLTCICR_CICMOD_1 (0x2UL << MDF_DFLTCICR_CICMOD_Pos) |
| #define | MDF_DFLTCICR_CICMOD_2 (0x4UL << MDF_DFLTCICR_CICMOD_Pos) |
| #define | MDF_DFLTCICR_MCICD_Pos (8U) |
| #define | MDF_DFLTCICR_MCICD_Msk (0x1FFUL << MDF_DFLTCICR_MCICD_Pos) |
| #define | MDF_DFLTCICR_MCICD MDF_DFLTCICR_MCICD_Msk |
| #define | MDF_DFLTCICR_SCALE_Pos (20U) |
| #define | MDF_DFLTCICR_SCALE_Msk (0x3FUL << MDF_DFLTCICR_SCALE_Pos) |
| #define | MDF_DFLTCICR_SCALE MDF_DFLTCICR_SCALE_Msk |
| #define | MDF_DFLTRSFR_RSFLTBYP_Pos (0U) |
| #define | MDF_DFLTRSFR_RSFLTBYP_Msk (0x1UL << MDF_DFLTRSFR_RSFLTBYP_Pos) |
| #define | MDF_DFLTRSFR_RSFLTBYP MDF_DFLTRSFR_RSFLTBYP_Msk |
| #define | MDF_DFLTRSFR_RSFLTD_Pos (4U) |
| #define | MDF_DFLTRSFR_RSFLTD_Msk (0x1UL << MDF_DFLTRSFR_RSFLTD_Pos) |
| #define | MDF_DFLTRSFR_RSFLTD MDF_DFLTRSFR_RSFLTD_Msk |
| #define | MDF_DFLTRSFR_HPFBYP_Pos (7U) |
| #define | MDF_DFLTRSFR_HPFBYP_Msk (0x1UL << MDF_DFLTRSFR_HPFBYP_Pos) |
| #define | MDF_DFLTRSFR_HPFBYP MDF_DFLTRSFR_HPFBYP_Msk |
| #define | MDF_DFLTRSFR_HPFC_Pos (8U) |
| #define | MDF_DFLTRSFR_HPFC_Msk (0x3UL << MDF_DFLTRSFR_HPFC_Pos) |
| #define | MDF_DFLTRSFR_HPFC MDF_DFLTRSFR_HPFC_Msk |
| #define | MDF_DFLTRSFR_HPFC_0 (0x1UL << MDF_DFLTRSFR_HPFC_Pos) |
| #define | MDF_DFLTRSFR_HPFC_1 (0x2UL << MDF_DFLTRSFR_HPFC_Pos) |
| #define | MDF_DFLTINTR_INTDIV_Pos (0U) |
| #define | MDF_DFLTINTR_INTDIV_Msk (0x3UL << MDF_DFLTINTR_INTDIV_Pos) |
| #define | MDF_DFLTINTR_INTDIV MDF_DFLTINTR_INTDIV_Msk |
| #define | MDF_DFLTINTR_INTDIV_0 (0x1UL << MDF_DFLTINTR_INTDIV_Pos) |
| #define | MDF_DFLTINTR_INTDIV_1 (0x2UL << MDF_DFLTINTR_INTDIV_Pos) |
| #define | MDF_DFLTINTR_INTVAL_Pos (4U) |
| #define | MDF_DFLTINTR_INTVAL_Msk (0x7FUL << MDF_DFLTINTR_INTVAL_Pos) |
| #define | MDF_DFLTINTR_INTVAL MDF_DFLTINTR_INTVAL_Msk |
| #define | MDF_OLDCR_OLDEN_Pos (0U) |
| #define | MDF_OLDCR_OLDEN_Msk (0x1UL << MDF_OLDCR_OLDEN_Pos) |
| #define | MDF_OLDCR_OLDEN MDF_OLDCR_OLDEN_Msk |
| #define | MDF_OLDCR_THINB_Pos (1U) |
| #define | MDF_OLDCR_THINB_Msk (0x1UL << MDF_OLDCR_THINB_Pos) |
| #define | MDF_OLDCR_THINB MDF_OLDCR_THINB_Msk |
| #define | MDF_OLDCR_BKOLD_Pos (4U) |
| #define | MDF_OLDCR_BKOLD_Msk (0xFUL << MDF_OLDCR_BKOLD_Pos) |
| #define | MDF_OLDCR_BKOLD MDF_OLDCR_BKOLD_Msk |
| #define | MDF_OLDCR_BKOLD_0 (0x1UL << MDF_OLDCR_BKOLD_Pos) |
| #define | MDF_OLDCR_BKOLD_1 (0x2UL << MDF_OLDCR_BKOLD_Pos) |
| #define | MDF_OLDCR_BKOLD_2 (0x4UL << MDF_OLDCR_BKOLD_Pos) |
| #define | MDF_OLDCR_BKOLD_3 (0x8UL << MDF_OLDCR_BKOLD_Pos) |
| #define | MDF_OLDCR_ACICN_Pos (12U) |
| #define | MDF_OLDCR_ACICN_Msk (0x3UL << MDF_OLDCR_ACICN_Pos) |
| #define | MDF_OLDCR_ACICN MDF_OLDCR_ACICN_Msk |
| #define | MDF_OLDCR_ACICN_0 (0x1UL << MDF_OLDCR_ACICN_Pos) |
| #define | MDF_OLDCR_ACICN_1 (0x2UL << MDF_OLDCR_ACICN_Pos) |
| #define | MDF_OLDCR_ACICD_Pos (17U) |
| #define | MDF_OLDCR_ACICD_Msk (0x1FUL << MDF_OLDCR_ACICD_Pos) |
| #define | MDF_OLDCR_ACICD MDF_OLDCR_ACICD_Msk |
| #define | MDF_OLDCR_OLDACTIVE_Pos (31U) |
| #define | MDF_OLDCR_OLDACTIVE_Msk (0x1UL << MDF_OLDCR_OLDACTIVE_Pos) |
| #define | MDF_OLDCR_OLDACTIVE MDF_OLDCR_OLDACTIVE_Msk |
| #define | MDF_OLDTHLR_OLDTHL_Pos (0U) |
| #define | MDF_OLDTHLR_OLDTHL_Msk (0x3FFFFFFUL << MDF_OLDTHLR_OLDTHL_Pos) |
| #define | MDF_OLDTHLR_OLDTHL MDF_OLDTHLR_OLDTHL_Msk |
| #define | MDF_OLDTHHR_OLDTHH_Pos (0U) |
| #define | MDF_OLDTHHR_OLDTHH_Msk (0x3FFFFFFUL << MDF_OLDTHHR_OLDTHH_Pos) |
| #define | MDF_OLDTHHR_OLDTHH MDF_OLDTHHR_OLDTHH_Msk |
| #define | MDF_DLYCR_SKPDLY_Pos (0U) |
| #define | MDF_DLYCR_SKPDLY_Msk (0x7FUL << MDF_DLYCR_SKPDLY_Pos) |
| #define | MDF_DLYCR_SKPDLY MDF_DLYCR_SKPDLY_Msk |
| #define | MDF_DLYCR_SKPBF_Pos (31U) |
| #define | MDF_DLYCR_SKPBF_Msk (0x1UL << MDF_DLYCR_SKPBF_Pos) |
| #define | MDF_DLYCR_SKPBF MDF_DLYCR_SKPBF_Msk |
| #define | MDF_SCDCR_SCDEN_Pos (0U) |
| #define | MDF_SCDCR_SCDEN_Msk (0x1UL << MDF_SCDCR_SCDEN_Pos) |
| #define | MDF_SCDCR_SCDEN MDF_SCDCR_SCDEN_Msk |
| #define | MDF_SCDCR_BKSCD_Pos (4U) |
| #define | MDF_SCDCR_BKSCD_Msk (0xFUL << MDF_SCDCR_BKSCD_Pos) |
| #define | MDF_SCDCR_BKSCD MDF_SCDCR_BKSCD_Msk |
| #define | MDF_SCDCR_BKSCD_0 (0x1UL << MDF_SCDCR_BKSCD_Pos) |
| #define | MDF_SCDCR_BKSCD_1 (0x2UL << MDF_SCDCR_BKSCD_Pos) |
| #define | MDF_SCDCR_BKSCD_2 (0x4UL << MDF_SCDCR_BKSCD_Pos) |
| #define | MDF_SCDCR_BKSCD_3 (0x8UL << MDF_SCDCR_BKSCD_Pos) |
| #define | MDF_SCDCR_SCDT_Pos (12U) |
| #define | MDF_SCDCR_SCDT_Msk (0xFFUL << MDF_SCDCR_SCDT_Pos) |
| #define | MDF_SCDCR_SCDT MDF_SCDCR_SCDT_Msk |
| #define | MDF_SCDCR_SCDACTIVE_Pos (31U) |
| #define | MDF_SCDCR_SCDACTIVE_Msk (0x1UL << MDF_SCDCR_SCDACTIVE_Pos) |
| #define | MDF_SCDCR_SCDACTIVE MDF_SCDCR_SCDACTIVE_Msk |
| #define | MDF_DFLTIER_FTHIE_Pos (0U) |
| #define | MDF_DFLTIER_FTHIE_Msk (0x1UL << MDF_DFLTIER_FTHIE_Pos) |
| #define | MDF_DFLTIER_FTHIE MDF_DFLTIER_FTHIE_Msk |
| #define | MDF_DFLTIER_DOVRIE_Pos (1U) |
| #define | MDF_DFLTIER_DOVRIE_Msk (0x1UL << MDF_DFLTIER_DOVRIE_Pos) |
| #define | MDF_DFLTIER_DOVRIE MDF_DFLTIER_DOVRIE_Msk |
| #define | MDF_DFLTIER_SSDRIE_Pos (2U) |
| #define | MDF_DFLTIER_SSDRIE_Msk (0x1UL << MDF_DFLTIER_SSDRIE_Pos) |
| #define | MDF_DFLTIER_SSDRIE MDF_DFLTIER_SSDRIE_Msk |
| #define | MDF_DFLTIER_OLDIE_Pos (4U) |
| #define | MDF_DFLTIER_OLDIE_Msk (0x1UL << MDF_DFLTIER_OLDIE_Pos) |
| #define | MDF_DFLTIER_OLDIE MDF_DFLTIER_OLDIE_Msk |
| #define | MDF_DFLTIER_SSOVRIE_Pos (7U) |
| #define | MDF_DFLTIER_SSOVRIE_Msk (0x1UL << MDF_DFLTIER_SSOVRIE_Pos) |
| #define | MDF_DFLTIER_SSOVRIE MDF_DFLTIER_SSOVRIE_Msk |
| #define | MDF_DFLTIER_SCDIE_Pos (8U) |
| #define | MDF_DFLTIER_SCDIE_Msk (0x1UL << MDF_DFLTIER_SCDIE_Pos) |
| #define | MDF_DFLTIER_SCDIE MDF_DFLTIER_SCDIE_Msk |
| #define | MDF_DFLTIER_SATIE_Pos (9U) |
| #define | MDF_DFLTIER_SATIE_Msk (0x1UL << MDF_DFLTIER_SATIE_Pos) |
| #define | MDF_DFLTIER_SATIE MDF_DFLTIER_SATIE_Msk |
| #define | MDF_DFLTIER_CKABIE_Pos (10U) |
| #define | MDF_DFLTIER_CKABIE_Msk (0x1UL << MDF_DFLTIER_CKABIE_Pos) |
| #define | MDF_DFLTIER_CKABIE MDF_DFLTIER_CKABIE_Msk |
| #define | MDF_DFLTIER_RFOVRIE_Pos (11U) |
| #define | MDF_DFLTIER_RFOVRIE_Msk (0x1UL << MDF_DFLTIER_RFOVRIE_Pos) |
| #define | MDF_DFLTIER_RFOVRIE MDF_DFLTIER_RFOVRIE_Msk |
| #define | MDF_DFLTIER_SDDETIE_Pos (12U) |
| #define | MDF_DFLTIER_SDDETIE_Msk (0x1UL << MDF_DFLTIER_SDDETIE_Pos) |
| #define | MDF_DFLTIER_SDDETIE MDF_DFLTIER_SDDETIE_Msk |
| #define | MDF_DFLTIER_SDLVLIE_Pos (13U) |
| #define | MDF_DFLTIER_SDLVLIE_Msk (0x1UL << MDF_DFLTIER_SDLVLIE_Pos) |
| #define | MDF_DFLTIER_SDLVLIE MDF_DFLTIER_SDLVLIE_Msk |
| #define | MDF_DFLTISR_FTHF_Pos (0U) |
| #define | MDF_DFLTISR_FTHF_Msk (0x1UL << MDF_DFLTISR_FTHF_Pos) |
| #define | MDF_DFLTISR_FTHF MDF_DFLTISR_FTHF_Msk |
| #define | MDF_DFLTISR_DOVRF_Pos (1U) |
| #define | MDF_DFLTISR_DOVRF_Msk (0x1UL << MDF_DFLTISR_DOVRF_Pos) |
| #define | MDF_DFLTISR_DOVRF MDF_DFLTISR_DOVRF_Msk |
| #define | MDF_DFLTISR_SSDRF_Pos (2U) |
| #define | MDF_DFLTISR_SSDRF_Msk (0x1UL << MDF_DFLTISR_SSDRF_Pos) |
| #define | MDF_DFLTISR_SSDRF MDF_DFLTISR_SSDRF_Msk |
| #define | MDF_DFLTISR_RXNEF_Pos (3U) |
| #define | MDF_DFLTISR_RXNEF_Msk (0x1UL << MDF_DFLTISR_RXNEF_Pos) |
| #define | MDF_DFLTISR_RXNEF MDF_DFLTISR_RXNEF_Msk |
| #define | MDF_DFLTISR_OLDF_Pos (4U) |
| #define | MDF_DFLTISR_OLDF_Msk (0x1UL << MDF_DFLTISR_OLDF_Pos) |
| #define | MDF_DFLTISR_OLDF MDF_DFLTISR_OLDF_Msk |
| #define | MDF_DFLTISR_THLF_Pos (5U) |
| #define | MDF_DFLTISR_THLF_Msk (0x1UL << MDF_DFLTISR_THLF_Pos) |
| #define | MDF_DFLTISR_THLF MDF_DFLTISR_THLF_Msk |
| #define | MDF_DFLTISR_THHF_Pos (6U) |
| #define | MDF_DFLTISR_THHF_Msk (0x1UL << MDF_DFLTISR_THHF_Pos) |
| #define | MDF_DFLTISR_THHF MDF_DFLTISR_THHF_Msk |
| #define | MDF_DFLTISR_SSOVRF_Pos (7U) |
| #define | MDF_DFLTISR_SSOVRF_Msk (0x1UL << MDF_DFLTISR_SSOVRF_Pos) |
| #define | MDF_DFLTISR_SSOVRF MDF_DFLTISR_SSOVRF_Msk |
| #define | MDF_DFLTISR_SCDF_Pos (8U) |
| #define | MDF_DFLTISR_SCDF_Msk (0x1UL << MDF_DFLTISR_SCDF_Pos) |
| #define | MDF_DFLTISR_SCDF MDF_DFLTISR_SCDF_Msk |
| #define | MDF_DFLTISR_SATF_Pos (9U) |
| #define | MDF_DFLTISR_SATF_Msk (0x1UL << MDF_DFLTISR_SATF_Pos) |
| #define | MDF_DFLTISR_SATF MDF_DFLTISR_SATF_Msk |
| #define | MDF_DFLTISR_CKABF_Pos (10U) |
| #define | MDF_DFLTISR_CKABF_Msk (0x1UL << MDF_DFLTISR_CKABF_Pos) |
| #define | MDF_DFLTISR_CKABF MDF_DFLTISR_CKABF_Msk |
| #define | MDF_DFLTISR_RFOVRF_Pos (11U) |
| #define | MDF_DFLTISR_RFOVRF_Msk (0x1UL << MDF_DFLTISR_RFOVRF_Pos) |
| #define | MDF_DFLTISR_RFOVRF MDF_DFLTISR_RFOVRF_Msk |
| #define | MDF_DFLTISR_SDDETF_Pos (12U) |
| #define | MDF_DFLTISR_SDDETF_Msk (0x1UL << MDF_DFLTISR_SDDETF_Pos) |
| #define | MDF_DFLTISR_SDDETF MDF_DFLTISR_SDDETF_Msk |
| #define | MDF_DFLTISR_SDLVLF_Pos (13U) |
| #define | MDF_DFLTISR_SDLVLF_Msk (0x1UL << MDF_DFLTISR_SDLVLF_Pos) |
| #define | MDF_DFLTISR_SDLVLF MDF_DFLTISR_SDLVLF_Msk |
| #define | MDF_OECCR_OFFSET_Pos (0U) |
| #define | MDF_OECCR_OFFSET_Msk (0x3FFFFFFUL << MDF_OECCR_OFFSET_Pos) |
| #define | MDF_OECCR_OFFSET MDF_OECCR_OFFSET_Msk |
| #define | MDF_SADCR_SADEN_Pos (0U) |
| #define | MDF_SADCR_SADEN_Msk (0x1UL << MDF_SADCR_SADEN_Pos) |
| #define | MDF_SADCR_SADEN MDF_SADCR_SADEN_Msk |
| #define | MDF_SADCR_DATCAP_Pos (1U) |
| #define | MDF_SADCR_DATCAP_Msk (0x3UL << MDF_SADCR_DATCAP_Pos) |
| #define | MDF_SADCR_DATCAP MDF_SADCR_DATCAP_Msk |
| #define | MDF_SADCR_DATCAP_0 (0x1UL << MDF_SADCR_DATCAP_Pos) |
| #define | MDF_SADCR_DATCAP_1 (0x2UL << MDF_SADCR_DATCAP_Pos) |
| #define | MDF_SADCR_DETCFG_Pos (3U) |
| #define | MDF_SADCR_DETCFG_Msk (0x1UL << MDF_SADCR_DETCFG_Pos) |
| #define | MDF_SADCR_DETCFG MDF_SADCR_DETCFG_Msk |
| #define | MDF_SADCR_SADST_Pos (4U) |
| #define | MDF_SADCR_SADST_Msk (0x3UL << MDF_SADCR_SADST_Pos) |
| #define | MDF_SADCR_SADST MDF_SADCR_SADST_Msk |
| #define | MDF_SADCR_HYSTEN_Pos (7U) |
| #define | MDF_SADCR_HYSTEN_Msk (0x1UL << MDF_SADCR_HYSTEN_Pos) |
| #define | MDF_SADCR_HYSTEN MDF_SADCR_HYSTEN_Msk |
| #define | MDF_SADCR_FRSIZE_Pos (8U) |
| #define | MDF_SADCR_FRSIZE_Msk (0x7UL << MDF_SADCR_FRSIZE_Pos) |
| #define | MDF_SADCR_FRSIZE MDF_SADCR_FRSIZE_Msk |
| #define | MDF_SADCR_FRSIZE_0 (0x1UL << MDF_SADCR_FRSIZE_Pos) |
| #define | MDF_SADCR_FRSIZE_1 (0x2UL << MDF_SADCR_FRSIZE_Pos) |
| #define | MDF_SADCR_FRSIZE_2 (0x4UL << MDF_SADCR_FRSIZE_Pos) |
| #define | MDF_SADCR_SADMOD_Pos (12U) |
| #define | MDF_SADCR_SADMOD_Msk (0x3UL << MDF_SADCR_SADMOD_Pos) |
| #define | MDF_SADCR_SADMOD MDF_SADCR_SADMOD_Msk |
| #define | MDF_SADCR_SADMOD_0 (0x1UL << MDF_SADCR_SADMOD_Pos) |
| #define | MDF_SADCR_SADMOD_1 (0x2UL << MDF_SADCR_SADMOD_Pos) |
| #define | MDF_SADCR_SADACTIVE_Pos (31U) |
| #define | MDF_SADCR_SADACTIVE_Msk (0x1UL << MDF_SADCR_SADACTIVE_Pos) |
| #define | MDF_SADCR_SADACTIVE MDF_SADCR_SADACTIVE_Msk |
| #define | MDF_SADCFGR_SNTHR_Pos (0U) |
| #define | MDF_SADCFGR_SNTHR_Msk (0xFUL << MDF_SADCFGR_SNTHR_Pos) |
| #define | MDF_SADCFGR_SNTHR MDF_SADCFGR_SNTHR_Msk |
| #define | MDF_SADCFGR_SNTHR_0 (0x1UL << MDF_SADCFGR_SNTHR_Pos) |
| #define | MDF_SADCFGR_SNTHR_1 (0x2UL << MDF_SADCFGR_SNTHR_Pos) |
| #define | MDF_SADCFGR_SNTHR_2 (0x4UL << MDF_SADCFGR_SNTHR_Pos) |
| #define | MDF_SADCFGR_SNTHR_3 (0x8UL << MDF_SADCFGR_SNTHR_Pos) |
| #define | MDF_SADCFGR_ANSLP_Pos (4U) |
| #define | MDF_SADCFGR_ANSLP_Msk (0x7UL << MDF_SADCFGR_ANSLP_Pos) |
| #define | MDF_SADCFGR_ANSLP MDF_SADCFGR_ANSLP_Msk |
| #define | MDF_SADCFGR_LFRNB_Pos (8U) |
| #define | MDF_SADCFGR_LFRNB_Msk (0x7UL << MDF_SADCFGR_LFRNB_Pos) |
| #define | MDF_SADCFGR_LFRNB MDF_SADCFGR_LFRNB_Msk |
| #define | MDF_SADCFGR_LFRNB_0 (0x1UL << MDF_SADCFGR_LFRNB_Pos) |
| #define | MDF_SADCFGR_LFRNB_1 (0x2UL << MDF_SADCFGR_LFRNB_Pos) |
| #define | MDF_SADCFGR_LFRNB_2 (0x4UL << MDF_SADCFGR_LFRNB_Pos) |
| #define | MDF_SADCFGR_HGOVR_Pos (12U) |
| #define | MDF_SADCFGR_HGOVR_Msk (0x7UL << MDF_SADCFGR_HGOVR_Pos) |
| #define | MDF_SADCFGR_HGOVR MDF_SADCFGR_HGOVR_Msk |
| #define | MDF_SADCFGR_HGOVR_0 (0x1UL << MDF_SADCFGR_HGOVR_Pos) |
| #define | MDF_SADCFGR_HGOVR_1 (0x2UL << MDF_SADCFGR_HGOVR_Pos) |
| #define | MDF_SADCFGR_HGOVR_2 (0x4UL << MDF_SADCFGR_HGOVR_Pos) |
| #define | MDF_SADCFGR_ANMIN_Pos (16U) |
| #define | MDF_SADCFGR_ANMIN_Msk (0x1FFFUL << MDF_SADCFGR_ANMIN_Pos) |
| #define | MDF_SADCFGR_ANMIN MDF_SADCFGR_ANMIN_Msk |
| #define | MDF_SADSDLVR_SDLVL_Pos (0U) |
| #define | MDF_SADSDLVR_SDLVL_Msk (0x7FFFUL << MDF_SADSDLVR_SDLVL_Pos) |
| #define | MDF_SADSDLVR_SDLVL MDF_SADSDLVR_SDLVL_Msk |
| #define | MDF_SADANLVR_ANLVL_Pos (0U) |
| #define | MDF_SADANLVR_ANLVL_Msk (0x7FFFUL << MDF_SADANLVR_ANLVL_Pos) |
| #define | MDF_SADANLVR_ANLVL MDF_SADANLVR_ANLVL_Msk |
| #define | MDF_SNPSDR_MCICDC_Pos (0U) |
| #define | MDF_SNPSDR_MCICDC_Msk (0x1FFUL << MDF_SNPSDR_MCICDC_Pos) |
| #define | MDF_SNPSDR_MCICDC MDF_SNPSDR_MCICDC_Msk |
| #define | MDF_SNPSDR_EXTSDR_Pos (9U) |
| #define | MDF_SNPSDR_EXTSDR_Msk (0x7FUL << MDF_SNPSDR_EXTSDR_Pos) |
| #define | MDF_SNPSDR_EXTSDR MDF_SNPSDR_EXTSDR_Msk |
| #define | MDF_SNPSDR_SDR_Pos (16U) |
| #define | MDF_SNPSDR_SDR_Msk (0xFFFFUL << MDF_SNPSDR_SDR_Pos) |
| #define | MDF_SNPSDR_SDR MDF_SNPSDR_SDR_Msk |
| #define | MDF_DFLTDR_DR_Pos (8U) |
| #define | MDF_DFLTDR_DR_Msk (0xFFFFFFUL << MDF_DFLTDR_DR_Pos) |
| #define | MDF_DFLTDR_DR MDF_DFLTDR_DR_Msk |
| #define | TIM_CR1_CEN_Pos (0U) |
| #define | TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) |
| #define | TIM_CR1_CEN TIM_CR1_CEN_Msk |
| #define | TIM_CR1_UDIS_Pos (1U) |
| #define | TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) |
| #define | TIM_CR1_UDIS TIM_CR1_UDIS_Msk |
| #define | TIM_CR1_URS_Pos (2U) |
| #define | TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) |
| #define | TIM_CR1_URS TIM_CR1_URS_Msk |
| #define | TIM_CR1_OPM_Pos (3U) |
| #define | TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) |
| #define | TIM_CR1_OPM TIM_CR1_OPM_Msk |
| #define | TIM_CR1_DIR_Pos (4U) |
| #define | TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) |
| #define | TIM_CR1_DIR TIM_CR1_DIR_Msk |
| #define | TIM_CR1_CMS_Pos (5U) |
| #define | TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) |
| #define | TIM_CR1_CMS TIM_CR1_CMS_Msk |
| #define | TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) |
| #define | TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) |
| #define | TIM_CR1_ARPE_Pos (7U) |
| #define | TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) |
| #define | TIM_CR1_ARPE TIM_CR1_ARPE_Msk |
| #define | TIM_CR1_CKD_Pos (8U) |
| #define | TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) |
| #define | TIM_CR1_CKD TIM_CR1_CKD_Msk |
| #define | TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) |
| #define | TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) |
| #define | TIM_CR1_UIFREMAP_Pos (11U) |
| #define | TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) |
| #define | TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk |
| #define | TIM_CR1_DITHEN_Pos (12U) |
| #define | TIM_CR1_DITHEN_Msk (0x1UL << TIM_CR1_DITHEN_Pos) |
| #define | TIM_CR1_DITHEN TIM_CR1_DITHEN_Msk |
| #define | TIM_CR2_CCPC_Pos (0U) |
| #define | TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) |
| #define | TIM_CR2_CCPC TIM_CR2_CCPC_Msk |
| #define | TIM_CR2_CCUS_Pos (2U) |
| #define | TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) |
| #define | TIM_CR2_CCUS TIM_CR2_CCUS_Msk |
| #define | TIM_CR2_CCDS_Pos (3U) |
| #define | TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) |
| #define | TIM_CR2_CCDS TIM_CR2_CCDS_Msk |
| #define | TIM_CR2_MMS_Pos (4U) |
| #define | TIM_CR2_MMS_Msk (0x200007UL << TIM_CR2_MMS_Pos) |
| #define | TIM_CR2_MMS TIM_CR2_MMS_Msk |
| #define | TIM_CR2_MMS_0 (0x000001UL << TIM_CR2_MMS_Pos) |
| #define | TIM_CR2_MMS_1 (0x000002UL << TIM_CR2_MMS_Pos) |
| #define | TIM_CR2_MMS_2 (0x000004UL << TIM_CR2_MMS_Pos) |
| #define | TIM_CR2_MMS_3 (0x200000UL << TIM_CR2_MMS_Pos) |
| #define | TIM_CR2_TI1S_Pos (7U) |
| #define | TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) |
| #define | TIM_CR2_TI1S TIM_CR2_TI1S_Msk |
| #define | TIM_CR2_OIS1_Pos (8U) |
| #define | TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) |
| #define | TIM_CR2_OIS1 TIM_CR2_OIS1_Msk |
| #define | TIM_CR2_OIS1N_Pos (9U) |
| #define | TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) |
| #define | TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk |
| #define | TIM_CR2_OIS2_Pos (10U) |
| #define | TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) |
| #define | TIM_CR2_OIS2 TIM_CR2_OIS2_Msk |
| #define | TIM_CR2_OIS2N_Pos (11U) |
| #define | TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) |
| #define | TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk |
| #define | TIM_CR2_OIS3_Pos (12U) |
| #define | TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) |
| #define | TIM_CR2_OIS3 TIM_CR2_OIS3_Msk |
| #define | TIM_CR2_OIS3N_Pos (13U) |
| #define | TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) |
| #define | TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk |
| #define | TIM_CR2_OIS4_Pos (14U) |
| #define | TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) |
| #define | TIM_CR2_OIS4 TIM_CR2_OIS4_Msk |
| #define | TIM_CR2_OIS4N_Pos (15U) |
| #define | TIM_CR2_OIS4N_Msk (0x1UL << TIM_CR2_OIS4N_Pos) |
| #define | TIM_CR2_OIS4N TIM_CR2_OIS4N_Msk |
| #define | TIM_CR2_OIS5_Pos (16U) |
| #define | TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) |
| #define | TIM_CR2_OIS5 TIM_CR2_OIS5_Msk |
| #define | TIM_CR2_OIS6_Pos (18U) |
| #define | TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) |
| #define | TIM_CR2_OIS6 TIM_CR2_OIS6_Msk |
| #define | TIM_CR2_MMS2_Pos (20U) |
| #define | TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) |
| #define | TIM_CR2_MMS2 TIM_CR2_MMS2_Msk |
| #define | TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) |
| #define | TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) |
| #define | TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) |
| #define | TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) |
| #define | TIM_SMCR_SMS_Pos (0U) |
| #define | TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) |
| #define | TIM_SMCR_SMS TIM_SMCR_SMS_Msk |
| #define | TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) |
| #define | TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) |
| #define | TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) |
| #define | TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) |
| #define | TIM_SMCR_OCCS_Pos (3U) |
| #define | TIM_SMCR_OCCS_Msk (0x1UL << TIM_SMCR_OCCS_Pos) |
| #define | TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk |
| #define | TIM_SMCR_TS_Pos (4U) |
| #define | TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) |
| #define | TIM_SMCR_TS TIM_SMCR_TS_Msk |
| #define | TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) |
| #define | TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) |
| #define | TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) |
| #define | TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) |
| #define | TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) |
| #define | TIM_SMCR_MSM_Pos (7U) |
| #define | TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) |
| #define | TIM_SMCR_MSM TIM_SMCR_MSM_Msk |
| #define | TIM_SMCR_ETF_Pos (8U) |
| #define | TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) |
| #define | TIM_SMCR_ETF TIM_SMCR_ETF_Msk |
| #define | TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) |
| #define | TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) |
| #define | TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) |
| #define | TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) |
| #define | TIM_SMCR_ETPS_Pos (12U) |
| #define | TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) |
| #define | TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk |
| #define | TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) |
| #define | TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) |
| #define | TIM_SMCR_ECE_Pos (14U) |
| #define | TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) |
| #define | TIM_SMCR_ECE TIM_SMCR_ECE_Msk |
| #define | TIM_SMCR_ETP_Pos (15U) |
| #define | TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) |
| #define | TIM_SMCR_ETP TIM_SMCR_ETP_Msk |
| #define | TIM_SMCR_SMSPE_Pos (24U) |
| #define | TIM_SMCR_SMSPE_Msk (0x1UL << TIM_SMCR_SMSPE_Pos) |
| #define | TIM_SMCR_SMSPE TIM_SMCR_SMSPE_Msk |
| #define | TIM_SMCR_SMSPS_Pos (25U) |
| #define | TIM_SMCR_SMSPS_Msk (0x1UL << TIM_SMCR_SMSPS_Pos) |
| #define | TIM_SMCR_SMSPS TIM_SMCR_SMSPS_Msk |
| #define | TIM_DIER_UIE_Pos (0U) |
| #define | TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) |
| #define | TIM_DIER_UIE TIM_DIER_UIE_Msk |
| #define | TIM_DIER_CC1IE_Pos (1U) |
| #define | TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) |
| #define | TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk |
| #define | TIM_DIER_CC2IE_Pos (2U) |
| #define | TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) |
| #define | TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk |
| #define | TIM_DIER_CC3IE_Pos (3U) |
| #define | TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) |
| #define | TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk |
| #define | TIM_DIER_CC4IE_Pos (4U) |
| #define | TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) |
| #define | TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk |
| #define | TIM_DIER_COMIE_Pos (5U) |
| #define | TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) |
| #define | TIM_DIER_COMIE TIM_DIER_COMIE_Msk |
| #define | TIM_DIER_TIE_Pos (6U) |
| #define | TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) |
| #define | TIM_DIER_TIE TIM_DIER_TIE_Msk |
| #define | TIM_DIER_BIE_Pos (7U) |
| #define | TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) |
| #define | TIM_DIER_BIE TIM_DIER_BIE_Msk |
| #define | TIM_DIER_UDE_Pos (8U) |
| #define | TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) |
| #define | TIM_DIER_UDE TIM_DIER_UDE_Msk |
| #define | TIM_DIER_CC1DE_Pos (9U) |
| #define | TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) |
| #define | TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk |
| #define | TIM_DIER_CC2DE_Pos (10U) |
| #define | TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) |
| #define | TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk |
| #define | TIM_DIER_CC3DE_Pos (11U) |
| #define | TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) |
| #define | TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk |
| #define | TIM_DIER_CC4DE_Pos (12U) |
| #define | TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) |
| #define | TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk |
| #define | TIM_DIER_COMDE_Pos (13U) |
| #define | TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) |
| #define | TIM_DIER_COMDE TIM_DIER_COMDE_Msk |
| #define | TIM_DIER_TDE_Pos (14U) |
| #define | TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) |
| #define | TIM_DIER_TDE TIM_DIER_TDE_Msk |
| #define | TIM_DIER_IDXIE_Pos (20U) |
| #define | TIM_DIER_IDXIE_Msk (0x1UL << TIM_DIER_IDXIE_Pos) |
| #define | TIM_DIER_IDXIE TIM_DIER_IDXIE_Msk |
| #define | TIM_DIER_DIRIE_Pos (21U) |
| #define | TIM_DIER_DIRIE_Msk (0x1UL << TIM_DIER_DIRIE_Pos) |
| #define | TIM_DIER_DIRIE TIM_DIER_DIRIE_Msk |
| #define | TIM_DIER_IERRIE_Pos (22U) |
| #define | TIM_DIER_IERRIE_Msk (0x1UL << TIM_DIER_IERRIE_Pos) |
| #define | TIM_DIER_IERRIE TIM_DIER_IERRIE_Msk |
| #define | TIM_DIER_TERRIE_Pos (23U) |
| #define | TIM_DIER_TERRIE_Msk (0x1UL << TIM_DIER_TERRIE_Pos) |
| #define | TIM_DIER_TERRIE TIM_DIER_TERRIE_Msk |
| #define | TIM_SR_UIF_Pos (0U) |
| #define | TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) |
| #define | TIM_SR_UIF TIM_SR_UIF_Msk |
| #define | TIM_SR_CC1IF_Pos (1U) |
| #define | TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) |
| #define | TIM_SR_CC1IF TIM_SR_CC1IF_Msk |
| #define | TIM_SR_CC2IF_Pos (2U) |
| #define | TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) |
| #define | TIM_SR_CC2IF TIM_SR_CC2IF_Msk |
| #define | TIM_SR_CC3IF_Pos (3U) |
| #define | TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) |
| #define | TIM_SR_CC3IF TIM_SR_CC3IF_Msk |
| #define | TIM_SR_CC4IF_Pos (4U) |
| #define | TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) |
| #define | TIM_SR_CC4IF TIM_SR_CC4IF_Msk |
| #define | TIM_SR_COMIF_Pos (5U) |
| #define | TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) |
| #define | TIM_SR_COMIF TIM_SR_COMIF_Msk |
| #define | TIM_SR_TIF_Pos (6U) |
| #define | TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) |
| #define | TIM_SR_TIF TIM_SR_TIF_Msk |
| #define | TIM_SR_BIF_Pos (7U) |
| #define | TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) |
| #define | TIM_SR_BIF TIM_SR_BIF_Msk |
| #define | TIM_SR_B2IF_Pos (8U) |
| #define | TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) |
| #define | TIM_SR_B2IF TIM_SR_B2IF_Msk |
| #define | TIM_SR_CC1OF_Pos (9U) |
| #define | TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) |
| #define | TIM_SR_CC1OF TIM_SR_CC1OF_Msk |
| #define | TIM_SR_CC2OF_Pos (10U) |
| #define | TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) |
| #define | TIM_SR_CC2OF TIM_SR_CC2OF_Msk |
| #define | TIM_SR_CC3OF_Pos (11U) |
| #define | TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) |
| #define | TIM_SR_CC3OF TIM_SR_CC3OF_Msk |
| #define | TIM_SR_CC4OF_Pos (12U) |
| #define | TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) |
| #define | TIM_SR_CC4OF TIM_SR_CC4OF_Msk |
| #define | TIM_SR_SBIF_Pos (13U) |
| #define | TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) |
| #define | TIM_SR_SBIF TIM_SR_SBIF_Msk |
| #define | TIM_SR_CC5IF_Pos (16U) |
| #define | TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) |
| #define | TIM_SR_CC5IF TIM_SR_CC5IF_Msk |
| #define | TIM_SR_CC6IF_Pos (17U) |
| #define | TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) |
| #define | TIM_SR_CC6IF TIM_SR_CC6IF_Msk |
| #define | TIM_SR_IDXF_Pos (20U) |
| #define | TIM_SR_IDXF_Msk (0x1UL << TIM_SR_IDXF_Pos) |
| #define | TIM_SR_IDXF TIM_SR_IDXF_Msk |
| #define | TIM_SR_DIRF_Pos (21U) |
| #define | TIM_SR_DIRF_Msk (0x1UL << TIM_SR_DIRF_Pos) |
| #define | TIM_SR_DIRF TIM_SR_DIRF_Msk |
| #define | TIM_SR_IERRF_Pos (22U) |
| #define | TIM_SR_IERRF_Msk (0x1UL << TIM_SR_IERRF_Pos) |
| #define | TIM_SR_IERRF TIM_SR_IERRF_Msk |
| #define | TIM_SR_TERRF_Pos (23U) |
| #define | TIM_SR_TERRF_Msk (0x1UL << TIM_SR_TERRF_Pos) |
| #define | TIM_SR_TERRF TIM_SR_TERRF_Msk |
| #define | TIM_EGR_UG_Pos (0U) |
| #define | TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) |
| #define | TIM_EGR_UG TIM_EGR_UG_Msk |
| #define | TIM_EGR_CC1G_Pos (1U) |
| #define | TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) |
| #define | TIM_EGR_CC1G TIM_EGR_CC1G_Msk |
| #define | TIM_EGR_CC2G_Pos (2U) |
| #define | TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) |
| #define | TIM_EGR_CC2G TIM_EGR_CC2G_Msk |
| #define | TIM_EGR_CC3G_Pos (3U) |
| #define | TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) |
| #define | TIM_EGR_CC3G TIM_EGR_CC3G_Msk |
| #define | TIM_EGR_CC4G_Pos (4U) |
| #define | TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) |
| #define | TIM_EGR_CC4G TIM_EGR_CC4G_Msk |
| #define | TIM_EGR_COMG_Pos (5U) |
| #define | TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) |
| #define | TIM_EGR_COMG TIM_EGR_COMG_Msk |
| #define | TIM_EGR_TG_Pos (6U) |
| #define | TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) |
| #define | TIM_EGR_TG TIM_EGR_TG_Msk |
| #define | TIM_EGR_BG_Pos (7U) |
| #define | TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) |
| #define | TIM_EGR_BG TIM_EGR_BG_Msk |
| #define | TIM_EGR_B2G_Pos (8U) |
| #define | TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) |
| #define | TIM_EGR_B2G TIM_EGR_B2G_Msk |
| #define | TIM_CCMR1_CC1S_Pos (0U) |
| #define | TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) |
| #define | TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk |
| #define | TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) |
| #define | TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) |
| #define | TIM_CCMR1_OC1FE_Pos (2U) |
| #define | TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) |
| #define | TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk |
| #define | TIM_CCMR1_OC1PE_Pos (3U) |
| #define | TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) |
| #define | TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk |
| #define | TIM_CCMR1_OC1M_Pos (4U) |
| #define | TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) |
| #define | TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk |
| #define | TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) |
| #define | TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) |
| #define | TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) |
| #define | TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) |
| #define | TIM_CCMR1_OC1CE_Pos (7U) |
| #define | TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) |
| #define | TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk |
| #define | TIM_CCMR1_CC2S_Pos (8U) |
| #define | TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) |
| #define | TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk |
| #define | TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) |
| #define | TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) |
| #define | TIM_CCMR1_OC2FE_Pos (10U) |
| #define | TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) |
| #define | TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk |
| #define | TIM_CCMR1_OC2PE_Pos (11U) |
| #define | TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) |
| #define | TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk |
| #define | TIM_CCMR1_OC2M_Pos (12U) |
| #define | TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) |
| #define | TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk |
| #define | TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) |
| #define | TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) |
| #define | TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) |
| #define | TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) |
| #define | TIM_CCMR1_OC2CE_Pos (15U) |
| #define | TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) |
| #define | TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk |
| #define | TIM_CCMR1_IC1PSC_Pos (2U) |
| #define | TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) |
| #define | TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk |
| #define | TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) |
| #define | TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) |
| #define | TIM_CCMR1_IC1F_Pos (4U) |
| #define | TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) |
| #define | TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk |
| #define | TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) |
| #define | TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) |
| #define | TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) |
| #define | TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) |
| #define | TIM_CCMR1_IC2PSC_Pos (10U) |
| #define | TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) |
| #define | TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk |
| #define | TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) |
| #define | TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) |
| #define | TIM_CCMR1_IC2F_Pos (12U) |
| #define | TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) |
| #define | TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk |
| #define | TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) |
| #define | TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) |
| #define | TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) |
| #define | TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) |
| #define | TIM_CCMR2_CC3S_Pos (0U) |
| #define | TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) |
| #define | TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk |
| #define | TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) |
| #define | TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) |
| #define | TIM_CCMR2_OC3FE_Pos (2U) |
| #define | TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) |
| #define | TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk |
| #define | TIM_CCMR2_OC3PE_Pos (3U) |
| #define | TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) |
| #define | TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk |
| #define | TIM_CCMR2_OC3M_Pos (4U) |
| #define | TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos) |
| #define | TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk |
| #define | TIM_CCMR2_OC3M_0 (0x0001UL << TIM_CCMR2_OC3M_Pos) |
| #define | TIM_CCMR2_OC3M_1 (0x0002UL << TIM_CCMR2_OC3M_Pos) |
| #define | TIM_CCMR2_OC3M_2 (0x0004UL << TIM_CCMR2_OC3M_Pos) |
| #define | TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) |
| #define | TIM_CCMR2_OC3CE_Pos (7U) |
| #define | TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) |
| #define | TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk |
| #define | TIM_CCMR2_CC4S_Pos (8U) |
| #define | TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) |
| #define | TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk |
| #define | TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) |
| #define | TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) |
| #define | TIM_CCMR2_OC4FE_Pos (10U) |
| #define | TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) |
| #define | TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk |
| #define | TIM_CCMR2_OC4PE_Pos (11U) |
| #define | TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) |
| #define | TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk |
| #define | TIM_CCMR2_OC4M_Pos (12U) |
| #define | TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos) |
| #define | TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk |
| #define | TIM_CCMR2_OC4M_0 (0x0001UL << TIM_CCMR2_OC4M_Pos) |
| #define | TIM_CCMR2_OC4M_1 (0x0002UL << TIM_CCMR2_OC4M_Pos) |
| #define | TIM_CCMR2_OC4M_2 (0x0004UL << TIM_CCMR2_OC4M_Pos) |
| #define | TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos) |
| #define | TIM_CCMR2_OC4CE_Pos (15U) |
| #define | TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) |
| #define | TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk |
| #define | TIM_CCMR2_IC3PSC_Pos (2U) |
| #define | TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) |
| #define | TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk |
| #define | TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) |
| #define | TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) |
| #define | TIM_CCMR2_IC3F_Pos (4U) |
| #define | TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) |
| #define | TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk |
| #define | TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) |
| #define | TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) |
| #define | TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) |
| #define | TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) |
| #define | TIM_CCMR2_IC4PSC_Pos (10U) |
| #define | TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) |
| #define | TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk |
| #define | TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) |
| #define | TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) |
| #define | TIM_CCMR2_IC4F_Pos (12U) |
| #define | TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) |
| #define | TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk |
| #define | TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) |
| #define | TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) |
| #define | TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) |
| #define | TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) |
| #define | TIM_CCMR3_OC5FE_Pos (2U) |
| #define | TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) |
| #define | TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk |
| #define | TIM_CCMR3_OC5PE_Pos (3U) |
| #define | TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) |
| #define | TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk |
| #define | TIM_CCMR3_OC5M_Pos (4U) |
| #define | TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos) |
| #define | TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk |
| #define | TIM_CCMR3_OC5M_0 (0x0001UL << TIM_CCMR3_OC5M_Pos) |
| #define | TIM_CCMR3_OC5M_1 (0x0002UL << TIM_CCMR3_OC5M_Pos) |
| #define | TIM_CCMR3_OC5M_2 (0x0004UL << TIM_CCMR3_OC5M_Pos) |
| #define | TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) |
| #define | TIM_CCMR3_OC5CE_Pos (7U) |
| #define | TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) |
| #define | TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk |
| #define | TIM_CCMR3_OC6FE_Pos (10U) |
| #define | TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) |
| #define | TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk |
| #define | TIM_CCMR3_OC6PE_Pos (11U) |
| #define | TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) |
| #define | TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk |
| #define | TIM_CCMR3_OC6M_Pos (12U) |
| #define | TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos) |
| #define | TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk |
| #define | TIM_CCMR3_OC6M_0 (0x0001UL << TIM_CCMR3_OC6M_Pos) |
| #define | TIM_CCMR3_OC6M_1 (0x0002UL << TIM_CCMR3_OC6M_Pos) |
| #define | TIM_CCMR3_OC6M_2 (0x0004UL << TIM_CCMR3_OC6M_Pos) |
| #define | TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos) |
| #define | TIM_CCMR3_OC6CE_Pos (15U) |
| #define | TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) |
| #define | TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk |
| #define | TIM_CCER_CC1E_Pos (0U) |
| #define | TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) |
| #define | TIM_CCER_CC1E TIM_CCER_CC1E_Msk |
| #define | TIM_CCER_CC1P_Pos (1U) |
| #define | TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) |
| #define | TIM_CCER_CC1P TIM_CCER_CC1P_Msk |
| #define | TIM_CCER_CC1NE_Pos (2U) |
| #define | TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) |
| #define | TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk |
| #define | TIM_CCER_CC1NP_Pos (3U) |
| #define | TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) |
| #define | TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk |
| #define | TIM_CCER_CC2E_Pos (4U) |
| #define | TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) |
| #define | TIM_CCER_CC2E TIM_CCER_CC2E_Msk |
| #define | TIM_CCER_CC2P_Pos (5U) |
| #define | TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) |
| #define | TIM_CCER_CC2P TIM_CCER_CC2P_Msk |
| #define | TIM_CCER_CC2NE_Pos (6U) |
| #define | TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) |
| #define | TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk |
| #define | TIM_CCER_CC2NP_Pos (7U) |
| #define | TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) |
| #define | TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk |
| #define | TIM_CCER_CC3E_Pos (8U) |
| #define | TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) |
| #define | TIM_CCER_CC3E TIM_CCER_CC3E_Msk |
| #define | TIM_CCER_CC3P_Pos (9U) |
| #define | TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) |
| #define | TIM_CCER_CC3P TIM_CCER_CC3P_Msk |
| #define | TIM_CCER_CC3NE_Pos (10U) |
| #define | TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) |
| #define | TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk |
| #define | TIM_CCER_CC3NP_Pos (11U) |
| #define | TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) |
| #define | TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk |
| #define | TIM_CCER_CC4E_Pos (12U) |
| #define | TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) |
| #define | TIM_CCER_CC4E TIM_CCER_CC4E_Msk |
| #define | TIM_CCER_CC4P_Pos (13U) |
| #define | TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) |
| #define | TIM_CCER_CC4P TIM_CCER_CC4P_Msk |
| #define | TIM_CCER_CC4NE_Pos (14U) |
| #define | TIM_CCER_CC4NE_Msk (0x1UL << TIM_CCER_CC4NE_Pos) |
| #define | TIM_CCER_CC4NE TIM_CCER_CC4NE_Msk |
| #define | TIM_CCER_CC4NP_Pos (15U) |
| #define | TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) |
| #define | TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk |
| #define | TIM_CCER_CC5E_Pos (16U) |
| #define | TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) |
| #define | TIM_CCER_CC5E TIM_CCER_CC5E_Msk |
| #define | TIM_CCER_CC5P_Pos (17U) |
| #define | TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) |
| #define | TIM_CCER_CC5P TIM_CCER_CC5P_Msk |
| #define | TIM_CCER_CC6E_Pos (20U) |
| #define | TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) |
| #define | TIM_CCER_CC6E TIM_CCER_CC6E_Msk |
| #define | TIM_CCER_CC6P_Pos (21U) |
| #define | TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) |
| #define | TIM_CCER_CC6P TIM_CCER_CC6P_Msk |
| #define | TIM_CNT_CNT_Pos (0U) |
| #define | TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) |
| #define | TIM_CNT_CNT TIM_CNT_CNT_Msk |
| #define | TIM_CNT_UIFCPY_Pos (31U) |
| #define | TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) |
| #define | TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk |
| #define | TIM_PSC_PSC_Pos (0U) |
| #define | TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) |
| #define | TIM_PSC_PSC TIM_PSC_PSC_Msk |
| #define | TIM_ARR_ARR_Pos (0U) |
| #define | TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) |
| #define | TIM_ARR_ARR TIM_ARR_ARR_Msk |
| #define | TIM_RCR_REP_Pos (0U) |
| #define | TIM_RCR_REP_Msk (0xFFFFUL << TIM_RCR_REP_Pos) |
| #define | TIM_RCR_REP TIM_RCR_REP_Msk |
| #define | TIM_CCR1_CCR1_Pos (0U) |
| #define | TIM_CCR1_CCR1_Msk (0xFFFFFFFFUL << TIM_CCR1_CCR1_Pos) |
| #define | TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk |
| #define | TIM_CCR2_CCR2_Pos (0U) |
| #define | TIM_CCR2_CCR2_Msk (0xFFFFFFFFUL << TIM_CCR2_CCR2_Pos) |
| #define | TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk |
| #define | TIM_CCR3_CCR3_Pos (0U) |
| #define | TIM_CCR3_CCR3_Msk (0xFFFFFFFFUL << TIM_CCR3_CCR3_Pos) |
| #define | TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk |
| #define | TIM_CCR4_CCR4_Pos (0U) |
| #define | TIM_CCR4_CCR4_Msk (0xFFFFFFFFUL << TIM_CCR4_CCR4_Pos) |
| #define | TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk |
| #define | TIM_CCR5_CCR5_Pos (0U) |
| #define | TIM_CCR5_CCR5_Msk (0xFFFFFUL << TIM_CCR5_CCR5_Pos) |
| #define | TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk |
| #define | TIM_CCR5_GC5C1_Pos (29U) |
| #define | TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) |
| #define | TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk |
| #define | TIM_CCR5_GC5C2_Pos (30U) |
| #define | TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) |
| #define | TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk |
| #define | TIM_CCR5_GC5C3_Pos (31U) |
| #define | TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) |
| #define | TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk |
| #define | TIM_CCR6_CCR6_Pos (0U) |
| #define | TIM_CCR6_CCR6_Msk (0xFFFFFUL << TIM_CCR6_CCR6_Pos) |
| #define | TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk |
| #define | TIM_BDTR_DTG_Pos (0U) |
| #define | TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) |
| #define | TIM_BDTR_DTG TIM_BDTR_DTG_Msk |
| #define | TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) |
| #define | TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) |
| #define | TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) |
| #define | TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) |
| #define | TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) |
| #define | TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) |
| #define | TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) |
| #define | TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) |
| #define | TIM_BDTR_LOCK_Pos (8U) |
| #define | TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) |
| #define | TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk |
| #define | TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) |
| #define | TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) |
| #define | TIM_BDTR_OSSI_Pos (10U) |
| #define | TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) |
| #define | TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk |
| #define | TIM_BDTR_OSSR_Pos (11U) |
| #define | TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) |
| #define | TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk |
| #define | TIM_BDTR_BKE_Pos (12U) |
| #define | TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) |
| #define | TIM_BDTR_BKE TIM_BDTR_BKE_Msk |
| #define | TIM_BDTR_BKP_Pos (13U) |
| #define | TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) |
| #define | TIM_BDTR_BKP TIM_BDTR_BKP_Msk |
| #define | TIM_BDTR_AOE_Pos (14U) |
| #define | TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) |
| #define | TIM_BDTR_AOE TIM_BDTR_AOE_Msk |
| #define | TIM_BDTR_MOE_Pos (15U) |
| #define | TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) |
| #define | TIM_BDTR_MOE TIM_BDTR_MOE_Msk |
| #define | TIM_BDTR_BKF_Pos (16U) |
| #define | TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) |
| #define | TIM_BDTR_BKF TIM_BDTR_BKF_Msk |
| #define | TIM_BDTR_BK2F_Pos (20U) |
| #define | TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) |
| #define | TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk |
| #define | TIM_BDTR_BK2E_Pos (24U) |
| #define | TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) |
| #define | TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk |
| #define | TIM_BDTR_BK2P_Pos (25U) |
| #define | TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) |
| #define | TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk |
| #define | TIM_BDTR_BKDSRM_Pos (26U) |
| #define | TIM_BDTR_BKDSRM_Msk (0x1UL << TIM_BDTR_BKDSRM_Pos) |
| #define | TIM_BDTR_BKDSRM TIM_BDTR_BKDSRM_Msk |
| #define | TIM_BDTR_BK2DSRM_Pos (27U) |
| #define | TIM_BDTR_BK2DSRM_Msk (0x1UL << TIM_BDTR_BK2DSRM_Pos) |
| #define | TIM_BDTR_BK2DSRM TIM_BDTR_BK2DSRM_Msk |
| #define | TIM_BDTR_BKBID_Pos (28U) |
| #define | TIM_BDTR_BKBID_Msk (0x1UL << TIM_BDTR_BKBID_Pos) |
| #define | TIM_BDTR_BKBID TIM_BDTR_BKBID_Msk |
| #define | TIM_BDTR_BK2BID_Pos (29U) |
| #define | TIM_BDTR_BK2BID_Msk (0x1UL << TIM_BDTR_BK2BID_Pos) |
| #define | TIM_BDTR_BK2BID TIM_BDTR_BK2BID_Msk |
| #define | TIM_DCR_DBA_Pos (0U) |
| #define | TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) |
| #define | TIM_DCR_DBA TIM_DCR_DBA_Msk |
| #define | TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) |
| #define | TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) |
| #define | TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) |
| #define | TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) |
| #define | TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) |
| #define | TIM_DCR_DBL_Pos (8U) |
| #define | TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) |
| #define | TIM_DCR_DBL TIM_DCR_DBL_Msk |
| #define | TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) |
| #define | TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) |
| #define | TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) |
| #define | TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) |
| #define | TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) |
| #define | TIM_DCR_DBSS_Pos (16U) |
| #define | TIM_DCR_DBSS_Msk (0xFUL << TIM_DCR_DBSS_Pos) |
| #define | TIM_DCR_DBSS TIM_DCR_DBSS_Msk |
| #define | TIM_DCR_DBSS_0 (0x01UL << TIM_DCR_DBSS_Pos) |
| #define | TIM_DCR_DBSS_1 (0x02UL << TIM_DCR_DBSS_Pos) |
| #define | TIM_DCR_DBSS_2 (0x04UL << TIM_DCR_DBSS_Pos) |
| #define | TIM_DCR_DBSS_3 (0x08UL << TIM_DCR_DBSS_Pos) |
| #define | TIM1_AF1_BKINE_Pos (0U) |
| #define | TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) |
| #define | TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk |
| #define | TIM1_AF1_BKCMP1E_Pos (1U) |
| #define | TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) |
| #define | TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk |
| #define | TIM1_AF1_BKCMP2E_Pos (2U) |
| #define | TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) |
| #define | TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk |
| #define | TIM1_AF1_BKDF1BK0E_Pos (8U) |
| #define | TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos) |
| #define | TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk |
| #define | TIM1_AF1_BKINP_Pos (9U) |
| #define | TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) |
| #define | TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk |
| #define | TIM1_AF1_BKCMP1P_Pos (10U) |
| #define | TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) |
| #define | TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk |
| #define | TIM1_AF1_BKCMP2P_Pos (11U) |
| #define | TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) |
| #define | TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk |
| #define | TIM1_AF1_ETRSEL_Pos (14U) |
| #define | TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) |
| #define | TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk |
| #define | TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) |
| #define | TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) |
| #define | TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) |
| #define | TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) |
| #define | TIM1_AF2_BK2INE_Pos (0U) |
| #define | TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) |
| #define | TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk |
| #define | TIM1_AF2_BK2CMP1E_Pos (1U) |
| #define | TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) |
| #define | TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk |
| #define | TIM1_AF2_BK2CMP2E_Pos (2U) |
| #define | TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) |
| #define | TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk |
| #define | TIM1_AF2_BK2DF1BK1E_Pos (8U) |
| #define | TIM1_AF2_BK2DF1BK1E_Msk (0x1UL << TIM1_AF2_BK2DF1BK1E_Pos) |
| #define | TIM1_AF2_BK2DF1BK1E TIM1_AF2_BK2DF1BK1E_Msk |
| #define | TIM1_AF2_BK2INP_Pos (9U) |
| #define | TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) |
| #define | TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk |
| #define | TIM1_AF2_BK2CMP1P_Pos (10U) |
| #define | TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) |
| #define | TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk |
| #define | TIM1_AF2_BK2CMP2P_Pos (11U) |
| #define | TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) |
| #define | TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk |
| #define | TIM1_AF2_OCRSEL_Pos (16U) |
| #define | TIM1_AF2_OCRSEL_Msk (0x1UL << TIM1_AF2_OCRSEL_Pos) |
| #define | TIM1_AF2_OCRSEL TIM1_AF2_OCRSEL_Msk |
| #define | TIM1_AF2_OCRSEL_0 (0x1UL << TIM1_AF2_OCRSEL_Pos) |
| #define | TIM_OR1_HSE32EN_Pos (1U) |
| #define | TIM_OR1_HSE32EN_Msk (0x1UL << TIM_OR1_HSE32EN_Pos) |
| #define | TIM_OR1_HSE32EN TIM_OR1_HSE32EN_Msk |
| #define | TIM_TISEL_TI1SEL_Pos (0U) |
| #define | TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) |
| #define | TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk |
| #define | TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) |
| #define | TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) |
| #define | TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) |
| #define | TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) |
| #define | TIM_TISEL_TI2SEL_Pos (8U) |
| #define | TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) |
| #define | TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk |
| #define | TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) |
| #define | TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) |
| #define | TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) |
| #define | TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) |
| #define | TIM_TISEL_TI3SEL_Pos (16U) |
| #define | TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) |
| #define | TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk |
| #define | TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) |
| #define | TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) |
| #define | TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) |
| #define | TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) |
| #define | TIM_TISEL_TI4SEL_Pos (24U) |
| #define | TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) |
| #define | TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk |
| #define | TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) |
| #define | TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) |
| #define | TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) |
| #define | TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) |
| #define | TIM_DTR2_DTGF_Pos (0U) |
| #define | TIM_DTR2_DTGF_Msk (0xFFUL << TIM_DTR2_DTGF_Pos) |
| #define | TIM_DTR2_DTGF TIM_DTR2_DTGF_Msk |
| #define | TIM_DTR2_DTGF_0 (0x01UL << TIM_DTR2_DTGF_Pos) |
| #define | TIM_DTR2_DTGF_1 (0x02UL << TIM_DTR2_DTGF_Pos) |
| #define | TIM_DTR2_DTGF_2 (0x04UL << TIM_DTR2_DTGF_Pos) |
| #define | TIM_DTR2_DTGF_3 (0x08UL << TIM_DTR2_DTGF_Pos) |
| #define | TIM_DTR2_DTGF_4 (0x10UL << TIM_DTR2_DTGF_Pos) |
| #define | TIM_DTR2_DTGF_5 (0x20UL << TIM_DTR2_DTGF_Pos) |
| #define | TIM_DTR2_DTGF_6 (0x40UL << TIM_DTR2_DTGF_Pos) |
| #define | TIM_DTR2_DTGF_7 (0x80UL << TIM_DTR2_DTGF_Pos) |
| #define | TIM_DTR2_DTAE_Pos (16U) |
| #define | TIM_DTR2_DTAE_Msk (0x1UL << TIM_DTR2_DTAE_Pos) |
| #define | TIM_DTR2_DTAE TIM_DTR2_DTAE_Msk |
| #define | TIM_DTR2_DTPE_Pos (17U) |
| #define | TIM_DTR2_DTPE_Msk (0x1UL << TIM_DTR2_DTPE_Pos) |
| #define | TIM_DTR2_DTPE TIM_DTR2_DTPE_Msk |
| #define | TIM_ECR_IE_Pos (0U) |
| #define | TIM_ECR_IE_Msk (0x1UL << TIM_ECR_IE_Pos) |
| #define | TIM_ECR_IE TIM_ECR_IE_Msk |
| #define | TIM_ECR_IDIR_Pos (1U) |
| #define | TIM_ECR_IDIR_Msk (0x3UL << TIM_ECR_IDIR_Pos) |
| #define | TIM_ECR_IDIR TIM_ECR_IDIR_Msk |
| #define | TIM_ECR_IDIR_0 (0x01UL << TIM_ECR_IDIR_Pos) |
| #define | TIM_ECR_IDIR_1 (0x02UL << TIM_ECR_IDIR_Pos) |
| #define | TIM_ECR_IBLK_Pos (3U) |
| #define | TIM_ECR_IBLK_Msk (0x3UL << TIM_ECR_IBLK_Pos) |
| #define | TIM_ECR_IBLK TIM_ECR_IBLK_Msk |
| #define | TIM_ECR_IBLK_0 (0x01UL << TIM_ECR_IBLK_Pos) |
| #define | TIM_ECR_IBLK_1 (0x02UL << TIM_ECR_IBLK_Pos) |
| #define | TIM_ECR_FIDX_Pos (5U) |
| #define | TIM_ECR_FIDX_Msk (0x1UL << TIM_ECR_FIDX_Pos) |
| #define | TIM_ECR_FIDX TIM_ECR_FIDX_Msk |
| #define | TIM_ECR_IPOS_Pos (6U) |
| #define | TIM_ECR_IPOS_Msk (0x3UL << TIM_ECR_IPOS_Pos) |
| #define | TIM_ECR_IPOS TIM_ECR_IPOS_Msk |
| #define | TIM_ECR_IPOS_0 (0x01UL << TIM_ECR_IPOS_Pos) |
| #define | TIM_ECR_IPOS_1 (0x02UL << TIM_ECR_IPOS_Pos) |
| #define | TIM_ECR_PW_Pos (16U) |
| #define | TIM_ECR_PW_Msk (0xFFUL << TIM_ECR_PW_Pos) |
| #define | TIM_ECR_PW TIM_ECR_PW_Msk |
| #define | TIM_ECR_PW_0 (0x01UL << TIM_ECR_PW_Pos) |
| #define | TIM_ECR_PW_1 (0x02UL << TIM_ECR_PW_Pos) |
| #define | TIM_ECR_PW_2 (0x04UL << TIM_ECR_PW_Pos) |
| #define | TIM_ECR_PW_3 (0x08UL << TIM_ECR_PW_Pos) |
| #define | TIM_ECR_PW_4 (0x10UL << TIM_ECR_PW_Pos) |
| #define | TIM_ECR_PW_5 (0x20UL << TIM_ECR_PW_Pos) |
| #define | TIM_ECR_PW_6 (0x40UL << TIM_ECR_PW_Pos) |
| #define | TIM_ECR_PW_7 (0x80UL << TIM_ECR_PW_Pos) |
| #define | TIM_ECR_PWPRSC_Pos (24U) |
| #define | TIM_ECR_PWPRSC_Msk (0x7UL << TIM_ECR_PWPRSC_Pos) |
| #define | TIM_ECR_PWPRSC TIM_ECR_PWPRSC_Msk |
| #define | TIM_ECR_PWPRSC_0 (0x01UL << TIM_ECR_PWPRSC_Pos) |
| #define | TIM_ECR_PWPRSC_1 (0x02UL << TIM_ECR_PWPRSC_Pos) |
| #define | TIM_ECR_PWPRSC_2 (0x04UL << TIM_ECR_PWPRSC_Pos) |
| #define | TIM_DMAR_DMAB_Pos (0U) |
| #define | TIM_DMAR_DMAB_Msk (0xFFFFFFFFUL << TIM_DMAR_DMAB_Pos) |
| #define | TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk |
| #define | LPTIM_ISR_CC1IF_Pos (0U) |
| #define | LPTIM_ISR_CC1IF_Msk (0x1UL << LPTIM_ISR_CC1IF_Pos) |
| #define | LPTIM_ISR_CC1IF LPTIM_ISR_CC1IF_Msk |
| #define | LPTIM_ISR_ARRM_Pos (1U) |
| #define | LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) |
| #define | LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk |
| #define | LPTIM_ISR_EXTTRIG_Pos (2U) |
| #define | LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) |
| #define | LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk |
| #define | LPTIM_ISR_CMP1OK_Pos (3U) |
| #define | LPTIM_ISR_CMP1OK_Msk (0x1UL << LPTIM_ISR_CMP1OK_Pos) |
| #define | LPTIM_ISR_CMP1OK LPTIM_ISR_CMP1OK_Msk |
| #define | LPTIM_ISR_ARROK_Pos (4U) |
| #define | LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) |
| #define | LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk |
| #define | LPTIM_ISR_UP_Pos (5U) |
| #define | LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) |
| #define | LPTIM_ISR_UP LPTIM_ISR_UP_Msk |
| #define | LPTIM_ISR_DOWN_Pos (6U) |
| #define | LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) |
| #define | LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk |
| #define | LPTIM_ISR_UE_Pos (7U) |
| #define | LPTIM_ISR_UE_Msk (0x1UL << LPTIM_ISR_UE_Pos) |
| #define | LPTIM_ISR_UE LPTIM_ISR_UE_Msk |
| #define | LPTIM_ISR_REPOK_Pos (8U) |
| #define | LPTIM_ISR_REPOK_Msk (0x1UL << LPTIM_ISR_REPOK_Pos) |
| #define | LPTIM_ISR_REPOK LPTIM_ISR_REPOK_Msk |
| #define | LPTIM_ISR_CC2IF_Pos (9U) |
| #define | LPTIM_ISR_CC2IF_Msk (0x1UL << LPTIM_ISR_CC2IF_Pos) |
| #define | LPTIM_ISR_CC2IF LPTIM_ISR_CC2IF_Msk |
| #define | LPTIM_ISR_CC1OF_Pos (12U) |
| #define | LPTIM_ISR_CC1OF_Msk (0x1UL << LPTIM_ISR_CC1OF_Pos) |
| #define | LPTIM_ISR_CC1OF LPTIM_ISR_CC1OF_Msk |
| #define | LPTIM_ISR_CC2OF_Pos (13U) |
| #define | LPTIM_ISR_CC2OF_Msk (0x1UL << LPTIM_ISR_CC2OF_Pos) |
| #define | LPTIM_ISR_CC2OF LPTIM_ISR_CC2OF_Msk |
| #define | LPTIM_ISR_CMP2OK_Pos (19U) |
| #define | LPTIM_ISR_CMP2OK_Msk (0x1UL << LPTIM_ISR_CMP2OK_Pos) |
| #define | LPTIM_ISR_CMP2OK LPTIM_ISR_CMP2OK_Msk |
| #define | LPTIM_ISR_DIEROK_Pos (24U) |
| #define | LPTIM_ISR_DIEROK_Msk (0x1UL << LPTIM_ISR_DIEROK_Pos) |
| #define | LPTIM_ISR_DIEROK LPTIM_ISR_DIEROK_Msk |
| #define | LPTIM_ICR_CC1CF_Pos (0U) |
| #define | LPTIM_ICR_CC1CF_Msk (0x1UL << LPTIM_ICR_CC1CF_Pos) |
| #define | LPTIM_ICR_CC1CF LPTIM_ICR_CC1CF_Msk |
| #define | LPTIM_ICR_ARRMCF_Pos (1U) |
| #define | LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) |
| #define | LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk |
| #define | LPTIM_ICR_EXTTRIGCF_Pos (2U) |
| #define | LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) |
| #define | LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk |
| #define | LPTIM_ICR_CMP1OKCF_Pos (3U) |
| #define | LPTIM_ICR_CMP1OKCF_Msk (0x1UL << LPTIM_ICR_CMP1OKCF_Pos) |
| #define | LPTIM_ICR_CMP1OKCF LPTIM_ICR_CMP1OKCF_Msk |
| #define | LPTIM_ICR_ARROKCF_Pos (4U) |
| #define | LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) |
| #define | LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk |
| #define | LPTIM_ICR_UPCF_Pos (5U) |
| #define | LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) |
| #define | LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk |
| #define | LPTIM_ICR_DOWNCF_Pos (6U) |
| #define | LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) |
| #define | LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk |
| #define | LPTIM_ICR_UECF_Pos (7U) |
| #define | LPTIM_ICR_UECF_Msk (0x1UL << LPTIM_ICR_UECF_Pos) |
| #define | LPTIM_ICR_UECF LPTIM_ICR_UECF_Msk |
| #define | LPTIM_ICR_REPOKCF_Pos (8U) |
| #define | LPTIM_ICR_REPOKCF_Msk (0x1UL << LPTIM_ICR_REPOKCF_Pos) |
| #define | LPTIM_ICR_REPOKCF LPTIM_ICR_REPOKCF_Msk |
| #define | LPTIM_ICR_CC2CF_Pos (9U) |
| #define | LPTIM_ICR_CC2CF_Msk (0x1UL << LPTIM_ICR_CC2CF_Pos) |
| #define | LPTIM_ICR_CC2CF LPTIM_ICR_CC2CF_Msk |
| #define | LPTIM_ICR_CC1OCF_Pos (12U) |
| #define | LPTIM_ICR_CC1OCF_Msk (0x1UL << LPTIM_ICR_CC1OCF_Pos) |
| #define | LPTIM_ICR_CC1OCF LPTIM_ICR_CC1OCF_Msk |
| #define | LPTIM_ICR_CC2OCF_Pos (13U) |
| #define | LPTIM_ICR_CC2OCF_Msk (0x1UL << LPTIM_ICR_CC2OCF_Pos) |
| #define | LPTIM_ICR_CC2OCF LPTIM_ICR_CC2OCF_Msk |
| #define | LPTIM_ICR_CMP2OKCF_Pos (19U) |
| #define | LPTIM_ICR_CMP2OKCF_Msk (0x1UL << LPTIM_ICR_CMP2OKCF_Pos) |
| #define | LPTIM_ICR_CMP2OKCF LPTIM_ICR_CMP2OKCF_Msk |
| #define | LPTIM_ICR_DIEROKCF_Pos (24U) |
| #define | LPTIM_ICR_DIEROKCF_Msk (0x1UL << LPTIM_ICR_DIEROKCF_Pos) |
| #define | LPTIM_ICR_DIEROKCF LPTIM_ICR_DIEROKCF_Msk |
| #define | LPTIM_DIER_CC1IE_Pos (0U) |
| #define | LPTIM_DIER_CC1IE_Msk (0x1UL << LPTIM_DIER_CC1IE_Pos) |
| #define | LPTIM_DIER_CC1IE LPTIM_DIER_CC1IE_Msk |
| #define | LPTIM_DIER_ARRMIE_Pos (1U) |
| #define | LPTIM_DIER_ARRMIE_Msk (0x1UL << LPTIM_DIER_ARRMIE_Pos) |
| #define | LPTIM_DIER_ARRMIE LPTIM_DIER_ARRMIE_Msk |
| #define | LPTIM_DIER_EXTTRIGIE_Pos (2U) |
| #define | LPTIM_DIER_EXTTRIGIE_Msk (0x1UL << LPTIM_DIER_EXTTRIGIE_Pos) |
| #define | LPTIM_DIER_EXTTRIGIE LPTIM_DIER_EXTTRIGIE_Msk |
| #define | LPTIM_DIER_CMP1OKIE_Pos (3U) |
| #define | LPTIM_DIER_CMP1OKIE_Msk (0x1UL << LPTIM_DIER_CMP1OKIE_Pos) |
| #define | LPTIM_DIER_CMP1OKIE LPTIM_DIER_CMP1OKIE_Msk |
| #define | LPTIM_DIER_ARROKIE_Pos (4U) |
| #define | LPTIM_DIER_ARROKIE_Msk (0x1UL << LPTIM_DIER_ARROKIE_Pos) |
| #define | LPTIM_DIER_ARROKIE LPTIM_DIER_ARROKIE_Msk |
| #define | LPTIM_DIER_UPIE_Pos (5U) |
| #define | LPTIM_DIER_UPIE_Msk (0x1UL << LPTIM_DIER_UPIE_Pos) |
| #define | LPTIM_DIER_UPIE LPTIM_DIER_UPIE_Msk |
| #define | LPTIM_DIER_DOWNIE_Pos (6U) |
| #define | LPTIM_DIER_DOWNIE_Msk (0x1UL << LPTIM_DIER_DOWNIE_Pos) |
| #define | LPTIM_DIER_DOWNIE LPTIM_DIER_DOWNIE_Msk |
| #define | LPTIM_DIER_UEIE_Pos (7U) |
| #define | LPTIM_DIER_UEIE_Msk (0x1UL << LPTIM_DIER_UEIE_Pos) |
| #define | LPTIM_DIER_UEIE LPTIM_DIER_UEIE_Msk |
| #define | LPTIM_DIER_REPOKIE_Pos (8U) |
| #define | LPTIM_DIER_REPOKIE_Msk (0x1UL << LPTIM_DIER_REPOKIE_Pos) |
| #define | LPTIM_DIER_REPOKIE LPTIM_DIER_REPOKIE_Msk |
| #define | LPTIM_DIER_CC2IE_Pos (9U) |
| #define | LPTIM_DIER_CC2IE_Msk (0x1UL << LPTIM_DIER_CC2IE_Pos) |
| #define | LPTIM_DIER_CC2IE LPTIM_DIER_CC2IE_Msk |
| #define | LPTIM_DIER_CC1OIE_Pos (12U) |
| #define | LPTIM_DIER_CC1OIE_Msk (0x1UL << LPTIM_DIER_CC1OIE_Pos) |
| #define | LPTIM_DIER_CC1OIE LPTIM_DIER_CC1OIE_Msk |
| #define | LPTIM_DIER_CC2OIE_Pos (13U) |
| #define | LPTIM_DIER_CC2OIE_Msk (0x1UL << LPTIM_DIER_CC2OIE_Pos) |
| #define | LPTIM_DIER_CC2OIE LPTIM_DIER_CC2OIE_Msk |
| #define | LPTIM_DIER_CC1DE_Pos (16U) |
| #define | LPTIM_DIER_CC1DE_Msk (0x1UL << LPTIM_DIER_CC1DE_Pos) |
| #define | LPTIM_DIER_CC1DE LPTIM_DIER_CC1DE_Msk |
| #define | LPTIM_DIER_CMP2OKIE_Pos (19U) |
| #define | LPTIM_DIER_CMP2OKIE_Msk (0x1UL << LPTIM_DIER_CMP2OKIE_Pos) |
| #define | LPTIM_DIER_CMP2OKIE LPTIM_DIER_CMP2OKIE_Msk |
| #define | LPTIM_DIER_UEDE_Pos (23U) |
| #define | LPTIM_DIER_UEDE_Msk (0x1UL << LPTIM_DIER_UEDE_Pos) |
| #define | LPTIM_DIER_UEDE LPTIM_DIER_UEDE_Msk |
| #define | LPTIM_DIER_CC2DE_Pos (25U) |
| #define | LPTIM_DIER_CC2DE_Msk (0x1UL << LPTIM_DIER_CC2DE_Pos) |
| #define | LPTIM_DIER_CC2DE LPTIM_DIER_CC2DE_Msk |
| #define | LPTIM_CFGR_CKSEL_Pos (0U) |
| #define | LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) |
| #define | LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk |
| #define | LPTIM_CFGR_CKPOL_Pos (1U) |
| #define | LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) |
| #define | LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk |
| #define | LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) |
| #define | LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) |
| #define | LPTIM_CFGR_CKFLT_Pos (3U) |
| #define | LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) |
| #define | LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk |
| #define | LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) |
| #define | LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) |
| #define | LPTIM_CFGR_TRGFLT_Pos (6U) |
| #define | LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) |
| #define | LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk |
| #define | LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) |
| #define | LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) |
| #define | LPTIM_CFGR_PRESC_Pos (9U) |
| #define | LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) |
| #define | LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk |
| #define | LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) |
| #define | LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) |
| #define | LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) |
| #define | LPTIM_CFGR_TRIGSEL_Pos (13U) |
| #define | LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) |
| #define | LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk |
| #define | LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) |
| #define | LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) |
| #define | LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) |
| #define | LPTIM_CFGR_TRIGEN_Pos (17U) |
| #define | LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) |
| #define | LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk |
| #define | LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) |
| #define | LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) |
| #define | LPTIM_CFGR_TIMOUT_Pos (19U) |
| #define | LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) |
| #define | LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk |
| #define | LPTIM_CFGR_WAVE_Pos (20U) |
| #define | LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) |
| #define | LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk |
| #define | LPTIM_CFGR_WAVPOL_Pos (21U) |
| #define | LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) |
| #define | LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk |
| #define | LPTIM_CFGR_PRELOAD_Pos (22U) |
| #define | LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) |
| #define | LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk |
| #define | LPTIM_CFGR_COUNTMODE_Pos (23U) |
| #define | LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) |
| #define | LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk |
| #define | LPTIM_CFGR_ENC_Pos (24U) |
| #define | LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) |
| #define | LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk |
| #define | LPTIM_CR_ENABLE_Pos (0U) |
| #define | LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) |
| #define | LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk |
| #define | LPTIM_CR_SNGSTRT_Pos (1U) |
| #define | LPTIM_CR_SNGSTRT_Msk (0x1UL << LPTIM_CR_SNGSTRT_Pos) |
| #define | LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk |
| #define | LPTIM_CR_CNTSTRT_Pos (2U) |
| #define | LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) |
| #define | LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk |
| #define | LPTIM_CR_COUNTRST_Pos (3U) |
| #define | LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) |
| #define | LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk |
| #define | LPTIM_CR_RSTARE_Pos (4U) |
| #define | LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) |
| #define | LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk |
| #define | LPTIM_CCR1_CCR1_Pos (0U) |
| #define | LPTIM_CCR1_CCR1_Msk (0xFFFFUL << LPTIM_CCR1_CCR1_Pos) |
| #define | LPTIM_CCR1_CCR1 LPTIM_CCR1_CCR1_Msk |
| #define | LPTIM_ARR_ARR_Pos (0U) |
| #define | LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) |
| #define | LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk |
| #define | LPTIM_CNT_CNT_Pos (0U) |
| #define | LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) |
| #define | LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk |
| #define | LPTIM_CFGR2_IN1SEL_Pos (0U) |
| #define | LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) |
| #define | LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk |
| #define | LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos) |
| #define | LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos) |
| #define | LPTIM_CFGR2_IN2SEL_Pos (4U) |
| #define | LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) |
| #define | LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk |
| #define | LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) |
| #define | LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) |
| #define | LPTIM_CFGR2_IC1SEL_Pos (16U) |
| #define | LPTIM_CFGR2_IC1SEL_Msk (0x3UL << LPTIM_CFGR2_IC1SEL_Pos) |
| #define | LPTIM_CFGR2_IC1SEL LPTIM_CFGR2_IC1SEL_Msk |
| #define | LPTIM_CFGR2_IC1SEL_0 (0x1UL << LPTIM_CFGR2_IC1SEL_Pos) |
| #define | LPTIM_CFGR2_IC1SEL_1 (0x2UL << LPTIM_CFGR2_IC1SEL_Pos) |
| #define | LPTIM_CFGR2_IC2SEL_Pos (20U) |
| #define | LPTIM_CFGR2_IC2SEL_Msk (0x3UL << LPTIM_CFGR2_IC2SEL_Pos) |
| #define | LPTIM_CFGR2_IC2SEL LPTIM_CFGR2_IC2SEL_Msk |
| #define | LPTIM_CFGR2_IC2SEL_0 (0x1UL << LPTIM_CFGR2_IC2SEL_Pos) |
| #define | LPTIM_CFGR2_IC2SEL_1 (0x2UL << LPTIM_CFGR2_IC2SEL_Pos) |
| #define | LPTIM_RCR_REP_Pos (0U) |
| #define | LPTIM_RCR_REP_Msk (0xFFUL << LPTIM_RCR_REP_Pos) |
| #define | LPTIM_RCR_REP LPTIM_RCR_REP_Msk |
| #define | LPTIM_CCMR1_CC1SEL_Pos (0U) |
| #define | LPTIM_CCMR1_CC1SEL_Msk (0x1UL << LPTIM_CCMR1_CC1SEL_Pos) |
| #define | LPTIM_CCMR1_CC1SEL LPTIM_CCMR1_CC1SEL_Msk |
| #define | LPTIM_CCMR1_CC1E_Pos (1U) |
| #define | LPTIM_CCMR1_CC1E_Msk (0x1UL << LPTIM_CCMR1_CC1E_Pos) |
| #define | LPTIM_CCMR1_CC1E LPTIM_CCMR1_CC1E_Msk |
| #define | LPTIM_CCMR1_CC1P_Pos (2U) |
| #define | LPTIM_CCMR1_CC1P_Msk (0x3UL << LPTIM_CCMR1_CC1P_Pos) |
| #define | LPTIM_CCMR1_CC1P LPTIM_CCMR1_CC1P_Msk |
| #define | LPTIM_CCMR1_CC1P_0 (0x1UL << LPTIM_CCMR1_CC1P_Pos) |
| #define | LPTIM_CCMR1_CC1P_1 (0x2UL << LPTIM_CCMR1_CC1P_Pos) |
| #define | LPTIM_CCMR1_IC1PSC_Pos (8U) |
| #define | LPTIM_CCMR1_IC1PSC_Msk (0x3UL << LPTIM_CCMR1_IC1PSC_Pos) |
| #define | LPTIM_CCMR1_IC1PSC LPTIM_CCMR1_IC1PSC_Msk |
| #define | LPTIM_CCMR1_IC1PSC_0 (0x1UL << LPTIM_CCMR1_IC1PSC_Pos) |
| #define | LPTIM_CCMR1_IC1PSC_1 (0x2UL << LPTIM_CCMR1_IC1PSC_Pos) |
| #define | LPTIM_CCMR1_IC1F_Pos (12U) |
| #define | LPTIM_CCMR1_IC1F_Msk (0x3UL << LPTIM_CCMR1_IC1F_Pos) |
| #define | LPTIM_CCMR1_IC1F LPTIM_CCMR1_IC1F_Msk |
| #define | LPTIM_CCMR1_IC1F_0 (0x1UL << LPTIM_CCMR1_IC1F_Pos) |
| #define | LPTIM_CCMR1_IC1F_1 (0x2UL << LPTIM_CCMR1_IC1F_Pos) |
| #define | LPTIM_CCMR1_CC2SEL_Pos (16U) |
| #define | LPTIM_CCMR1_CC2SEL_Msk (0x1UL << LPTIM_CCMR1_CC2SEL_Pos) |
| #define | LPTIM_CCMR1_CC2SEL LPTIM_CCMR1_CC2SEL_Msk |
| #define | LPTIM_CCMR1_CC2E_Pos (17U) |
| #define | LPTIM_CCMR1_CC2E_Msk (0x1UL << LPTIM_CCMR1_CC2E_Pos) |
| #define | LPTIM_CCMR1_CC2E LPTIM_CCMR1_CC2E_Msk |
| #define | LPTIM_CCMR1_CC2P_Pos (18U) |
| #define | LPTIM_CCMR1_CC2P_Msk (0x3UL << LPTIM_CCMR1_CC2P_Pos) |
| #define | LPTIM_CCMR1_CC2P LPTIM_CCMR1_CC2P_Msk |
| #define | LPTIM_CCMR1_CC2P_0 (0x1UL << LPTIM_CCMR1_CC2P_Pos) |
| #define | LPTIM_CCMR1_CC2P_1 (0x2UL << LPTIM_CCMR1_CC2P_Pos) |
| #define | LPTIM_CCMR1_IC2PSC_Pos (24U) |
| #define | LPTIM_CCMR1_IC2PSC_Msk (0x3UL << LPTIM_CCMR1_IC2PSC_Pos) |
| #define | LPTIM_CCMR1_IC2PSC LPTIM_CCMR1_IC2PSC_Msk |
| #define | LPTIM_CCMR1_IC2PSC_0 (0x1UL << LPTIM_CCMR1_IC2PSC_Pos) |
| #define | LPTIM_CCMR1_IC2PSC_1 (0x2UL << LPTIM_CCMR1_IC2PSC_Pos) |
| #define | LPTIM_CCMR1_IC2F_Pos (28U) |
| #define | LPTIM_CCMR1_IC2F_Msk (0x3UL << LPTIM_CCMR1_IC2F_Pos) |
| #define | LPTIM_CCMR1_IC2F LPTIM_CCMR1_IC2F_Msk |
| #define | LPTIM_CCMR1_IC2F_0 (0x1UL << LPTIM_CCMR1_IC2F_Pos) |
| #define | LPTIM_CCMR1_IC2F_1 (0x2UL << LPTIM_CCMR1_IC2F_Pos) |
| #define | LPTIM_CCR2_CCR2_Pos (0U) |
| #define | LPTIM_CCR2_CCR2_Msk (0xFFFFUL << LPTIM_CCR2_CCR2_Pos) |
| #define | LPTIM_CCR2_CCR2 LPTIM_CCR2_CCR2_Msk |
| #define | PSSI_CR_CKPOL_Pos (5U) |
| #define | PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) |
| #define | PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk |
| #define | PSSI_CR_DEPOL_Pos (6U) |
| #define | PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) |
| #define | PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk |
| #define | PSSI_CR_RDYPOL_Pos (8U) |
| #define | PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) |
| #define | PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk |
| #define | PSSI_CR_EDM_Pos (10U) |
| #define | PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) |
| #define | PSSI_CR_EDM PSSI_CR_EDM_Msk |
| #define | PSSI_CR_ENABLE_Pos (14U) |
| #define | PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) |
| #define | PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk |
| #define | PSSI_CR_DERDYCFG_Pos (18U) |
| #define | PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) |
| #define | PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk |
| #define | PSSI_CR_DMAEN_Pos (30U) |
| #define | PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) |
| #define | PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk |
| #define | PSSI_CR_OUTEN_Pos (31U) |
| #define | PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) |
| #define | PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk |
| #define | PSSI_SR_RTT4B_Pos (2U) |
| #define | PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) |
| #define | PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk |
| #define | PSSI_SR_RTT1B_Pos (3U) |
| #define | PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) |
| #define | PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk |
| #define | PSSI_RIS_OVR_RIS_Pos (1U) |
| #define | PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) |
| #define | PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk |
| #define | PSSI_IER_OVR_IE_Pos (1U) |
| #define | PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) |
| #define | PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk |
| #define | PSSI_MIS_OVR_MIS_Pos (1U) |
| #define | PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) |
| #define | PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk |
| #define | PSSI_ICR_OVR_ISC_Pos (1U) |
| #define | PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) |
| #define | PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk |
| #define | PSSI_DR_DR_Pos (0U) |
| #define | PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) |
| #define | PSSI_DR_DR PSSI_DR_DR_Msk |
| #define | SDMMC_POWER_PWRCTRL_Pos (0U) |
| #define | SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) |
| #define | SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk |
| #define | SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) |
| #define | SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) |
| #define | SDMMC_POWER_VSWITCH_Pos (2U) |
| #define | SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos) |
| #define | SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk |
| #define | SDMMC_POWER_VSWITCHEN_Pos (3U) |
| #define | SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos) |
| #define | SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk |
| #define | SDMMC_POWER_DIRPOL_Pos (4U) |
| #define | SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos) |
| #define | SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk |
| #define | SDMMC_CLKCR_CLKDIV_Pos (0U) |
| #define | SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos) |
| #define | SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk |
| #define | SDMMC_CLKCR_PWRSAV_Pos (12U) |
| #define | SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) |
| #define | SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk |
| #define | SDMMC_CLKCR_WIDBUS_Pos (14U) |
| #define | SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) |
| #define | SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk |
| #define | SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) |
| #define | SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) |
| #define | SDMMC_CLKCR_NEGEDGE_Pos (16U) |
| #define | SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) |
| #define | SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk |
| #define | SDMMC_CLKCR_HWFC_EN_Pos (17U) |
| #define | SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) |
| #define | SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk |
| #define | SDMMC_CLKCR_DDR_Pos (18U) |
| #define | SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) |
| #define | SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk |
| #define | SDMMC_CLKCR_BUSSPEED_Pos (19U) |
| #define | SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos) |
| #define | SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk |
| #define | SDMMC_CLKCR_SELCLKRX_Pos (20U) |
| #define | SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos) |
| #define | SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk |
| #define | SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos) |
| #define | SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos) |
| #define | SDMMC_ARG_CMDARG_Pos (0U) |
| #define | SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) |
| #define | SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk |
| #define | SDMMC_CMD_CMDINDEX_Pos (0U) |
| #define | SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) |
| #define | SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk |
| #define | SDMMC_CMD_CMDTRANS_Pos (6U) |
| #define | SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos) |
| #define | SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk |
| #define | SDMMC_CMD_CMDSTOP_Pos (7U) |
| #define | SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos) |
| #define | SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk |
| #define | SDMMC_CMD_WAITRESP_Pos (8U) |
| #define | SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) |
| #define | SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk |
| #define | SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) |
| #define | SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) |
| #define | SDMMC_CMD_WAITINT_Pos (10U) |
| #define | SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) |
| #define | SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk |
| #define | SDMMC_CMD_WAITPEND_Pos (11U) |
| #define | SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) |
| #define | SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk |
| #define | SDMMC_CMD_CPSMEN_Pos (12U) |
| #define | SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) |
| #define | SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk |
| #define | SDMMC_CMD_DTHOLD_Pos (13U) |
| #define | SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos) |
| #define | SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk |
| #define | SDMMC_CMD_BOOTMODE_Pos (14U) |
| #define | SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos) |
| #define | SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk |
| #define | SDMMC_CMD_BOOTEN_Pos (15U) |
| #define | SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos) |
| #define | SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk |
| #define | SDMMC_CMD_CMDSUSPEND_Pos (16U) |
| #define | SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos) |
| #define | SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk |
| #define | SDMMC_RESPCMD_RESPCMD_Pos (0U) |
| #define | SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) |
| #define | SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk |
| #define | SDMMC_RESP1_CARDSTATUS1_Pos (0U) |
| #define | SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) |
| #define | SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk |
| #define | SDMMC_RESP2_CARDSTATUS2_Pos (0U) |
| #define | SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) |
| #define | SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk |
| #define | SDMMC_RESP3_CARDSTATUS3_Pos (0U) |
| #define | SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) |
| #define | SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk |
| #define | SDMMC_RESP4_CARDSTATUS4_Pos (0U) |
| #define | SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) |
| #define | SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk |
| #define | SDMMC_DTIMER_DATATIME_Pos (0U) |
| #define | SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) |
| #define | SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk |
| #define | SDMMC_DLEN_DATALENGTH_Pos (0U) |
| #define | SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) |
| #define | SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk |
| #define | SDMMC_DCTRL_DTEN_Pos (0U) |
| #define | SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) |
| #define | SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk |
| #define | SDMMC_DCTRL_DTDIR_Pos (1U) |
| #define | SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) |
| #define | SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk |
| #define | SDMMC_DCTRL_DTMODE_Pos (2U) |
| #define | SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos) |
| #define | SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk |
| #define | SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos) |
| #define | SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos) |
| #define | SDMMC_DCTRL_DBLOCKSIZE_Pos (4U) |
| #define | SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) |
| #define | SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk |
| #define | SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) |
| #define | SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) |
| #define | SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) |
| #define | SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) |
| #define | SDMMC_DCTRL_RWSTART_Pos (8U) |
| #define | SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) |
| #define | SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk |
| #define | SDMMC_DCTRL_RWSTOP_Pos (9U) |
| #define | SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) |
| #define | SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk |
| #define | SDMMC_DCTRL_RWMOD_Pos (10U) |
| #define | SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) |
| #define | SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk |
| #define | SDMMC_DCTRL_SDIOEN_Pos (11U) |
| #define | SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) |
| #define | SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk |
| #define | SDMMC_DCTRL_BOOTACKEN_Pos (12U) |
| #define | SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos) |
| #define | SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk |
| #define | SDMMC_DCTRL_FIFORST_Pos (13U) |
| #define | SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos) |
| #define | SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk |
| #define | SDMMC_DCOUNT_DATACOUNT_Pos (0U) |
| #define | SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) |
| #define | SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk |
| #define | SDMMC_STA_CCRCFAIL_Pos (0U) |
| #define | SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) |
| #define | SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk |
| #define | SDMMC_STA_DCRCFAIL_Pos (1U) |
| #define | SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) |
| #define | SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk |
| #define | SDMMC_STA_CTIMEOUT_Pos (2U) |
| #define | SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) |
| #define | SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk |
| #define | SDMMC_STA_DTIMEOUT_Pos (3U) |
| #define | SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) |
| #define | SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk |
| #define | SDMMC_STA_TXUNDERR_Pos (4U) |
| #define | SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) |
| #define | SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk |
| #define | SDMMC_STA_RXOVERR_Pos (5U) |
| #define | SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) |
| #define | SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk |
| #define | SDMMC_STA_CMDREND_Pos (6U) |
| #define | SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) |
| #define | SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk |
| #define | SDMMC_STA_CMDSENT_Pos (7U) |
| #define | SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) |
| #define | SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk |
| #define | SDMMC_STA_DATAEND_Pos (8U) |
| #define | SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) |
| #define | SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk |
| #define | SDMMC_STA_DHOLD_Pos (9U) |
| #define | SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos) |
| #define | SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk |
| #define | SDMMC_STA_DBCKEND_Pos (10U) |
| #define | SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) |
| #define | SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk |
| #define | SDMMC_STA_DABORT_Pos (11U) |
| #define | SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos) |
| #define | SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk |
| #define | SDMMC_STA_DPSMACT_Pos (12U) |
| #define | SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos) |
| #define | SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk |
| #define | SDMMC_STA_CPSMACT_Pos (13U) |
| #define | SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos) |
| #define | SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk |
| #define | SDMMC_STA_TXFIFOHE_Pos (14U) |
| #define | SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) |
| #define | SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk |
| #define | SDMMC_STA_RXFIFOHF_Pos (15U) |
| #define | SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) |
| #define | SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk |
| #define | SDMMC_STA_TXFIFOF_Pos (16U) |
| #define | SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) |
| #define | SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk |
| #define | SDMMC_STA_RXFIFOF_Pos (17U) |
| #define | SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) |
| #define | SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk |
| #define | SDMMC_STA_TXFIFOE_Pos (18U) |
| #define | SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) |
| #define | SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk |
| #define | SDMMC_STA_RXFIFOE_Pos (19U) |
| #define | SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) |
| #define | SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk |
| #define | SDMMC_STA_BUSYD0_Pos (20U) |
| #define | SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos) |
| #define | SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk |
| #define | SDMMC_STA_BUSYD0END_Pos (21U) |
| #define | SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos) |
| #define | SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk |
| #define | SDMMC_STA_SDIOIT_Pos (22U) |
| #define | SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) |
| #define | SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk |
| #define | SDMMC_STA_ACKFAIL_Pos (23U) |
| #define | SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos) |
| #define | SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk |
| #define | SDMMC_STA_ACKTIMEOUT_Pos (24U) |
| #define | SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos) |
| #define | SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk |
| #define | SDMMC_STA_VSWEND_Pos (25U) |
| #define | SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos) |
| #define | SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk |
| #define | SDMMC_STA_CKSTOP_Pos (26U) |
| #define | SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos) |
| #define | SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk |
| #define | SDMMC_STA_IDMATE_Pos (27U) |
| #define | SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos) |
| #define | SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk |
| #define | SDMMC_STA_IDMABTC_Pos (28U) |
| #define | SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos) |
| #define | SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk |
| #define | SDMMC_ICR_CCRCFAILC_Pos (0U) |
| #define | SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) |
| #define | SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk |
| #define | SDMMC_ICR_DCRCFAILC_Pos (1U) |
| #define | SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) |
| #define | SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk |
| #define | SDMMC_ICR_CTIMEOUTC_Pos (2U) |
| #define | SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) |
| #define | SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk |
| #define | SDMMC_ICR_DTIMEOUTC_Pos (3U) |
| #define | SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) |
| #define | SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk |
| #define | SDMMC_ICR_TXUNDERRC_Pos (4U) |
| #define | SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) |
| #define | SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk |
| #define | SDMMC_ICR_RXOVERRC_Pos (5U) |
| #define | SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) |
| #define | SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk |
| #define | SDMMC_ICR_CMDRENDC_Pos (6U) |
| #define | SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) |
| #define | SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk |
| #define | SDMMC_ICR_CMDSENTC_Pos (7U) |
| #define | SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) |
| #define | SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk |
| #define | SDMMC_ICR_DATAENDC_Pos (8U) |
| #define | SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) |
| #define | SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk |
| #define | SDMMC_ICR_DHOLDC_Pos (9U) |
| #define | SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos) |
| #define | SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk |
| #define | SDMMC_ICR_DBCKENDC_Pos (10U) |
| #define | SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) |
| #define | SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk |
| #define | SDMMC_ICR_DABORTC_Pos (11U) |
| #define | SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos) |
| #define | SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk |
| #define | SDMMC_ICR_BUSYD0ENDC_Pos (21U) |
| #define | SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos) |
| #define | SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk |
| #define | SDMMC_ICR_SDIOITC_Pos (22U) |
| #define | SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) |
| #define | SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk |
| #define | SDMMC_ICR_ACKFAILC_Pos (23U) |
| #define | SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos) |
| #define | SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk |
| #define | SDMMC_ICR_ACKTIMEOUTC_Pos (24U) |
| #define | SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos) |
| #define | SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk |
| #define | SDMMC_ICR_VSWENDC_Pos (25U) |
| #define | SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos) |
| #define | SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk |
| #define | SDMMC_ICR_CKSTOPC_Pos (26U) |
| #define | SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos) |
| #define | SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk |
| #define | SDMMC_ICR_IDMATEC_Pos (27U) |
| #define | SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos) |
| #define | SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk |
| #define | SDMMC_ICR_IDMABTCC_Pos (28U) |
| #define | SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos) |
| #define | SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk |
| #define | SDMMC_MASK_CCRCFAILIE_Pos (0U) |
| #define | SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) |
| #define | SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk |
| #define | SDMMC_MASK_DCRCFAILIE_Pos (1U) |
| #define | SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) |
| #define | SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk |
| #define | SDMMC_MASK_CTIMEOUTIE_Pos (2U) |
| #define | SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) |
| #define | SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk |
| #define | SDMMC_MASK_DTIMEOUTIE_Pos (3U) |
| #define | SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) |
| #define | SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk |
| #define | SDMMC_MASK_TXUNDERRIE_Pos (4U) |
| #define | SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) |
| #define | SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk |
| #define | SDMMC_MASK_RXOVERRIE_Pos (5U) |
| #define | SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) |
| #define | SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk |
| #define | SDMMC_MASK_CMDRENDIE_Pos (6U) |
| #define | SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) |
| #define | SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk |
| #define | SDMMC_MASK_CMDSENTIE_Pos (7U) |
| #define | SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) |
| #define | SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk |
| #define | SDMMC_MASK_DATAENDIE_Pos (8U) |
| #define | SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) |
| #define | SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk |
| #define | SDMMC_MASK_DHOLDIE_Pos (9U) |
| #define | SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos) |
| #define | SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk |
| #define | SDMMC_MASK_DBCKENDIE_Pos (10U) |
| #define | SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) |
| #define | SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk |
| #define | SDMMC_MASK_DABORTIE_Pos (11U) |
| #define | SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos) |
| #define | SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk |
| #define | SDMMC_MASK_TXFIFOHEIE_Pos (14U) |
| #define | SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) |
| #define | SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk |
| #define | SDMMC_MASK_RXFIFOHFIE_Pos (15U) |
| #define | SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) |
| #define | SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk |
| #define | SDMMC_MASK_RXFIFOFIE_Pos (17U) |
| #define | SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) |
| #define | SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk |
| #define | SDMMC_MASK_TXFIFOEIE_Pos (18U) |
| #define | SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) |
| #define | SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk |
| #define | SDMMC_MASK_BUSYD0ENDIE_Pos (21U) |
| #define | SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) |
| #define | SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk |
| #define | SDMMC_MASK_SDIOITIE_Pos (22U) |
| #define | SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) |
| #define | SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk |
| #define | SDMMC_MASK_ACKFAILIE_Pos (23U) |
| #define | SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos) |
| #define | SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk |
| #define | SDMMC_MASK_ACKTIMEOUTIE_Pos (24U) |
| #define | SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) |
| #define | SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk |
| #define | SDMMC_MASK_VSWENDIE_Pos (25U) |
| #define | SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos) |
| #define | SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk |
| #define | SDMMC_MASK_CKSTOPIE_Pos (26U) |
| #define | SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos) |
| #define | SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk |
| #define | SDMMC_MASK_IDMABTCIE_Pos (28U) |
| #define | SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos) |
| #define | SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk |
| #define | SDMMC_ACKTIME_ACKTIME_Pos (0U) |
| #define | SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) |
| #define | SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk |
| #define | SDMMC_FIFO_FIFODATA_Pos (0U) |
| #define | SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) |
| #define | SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk |
| #define | SDMMC_IDMA_IDMAEN_Pos (0U) |
| #define | SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos) |
| #define | SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk |
| #define | SDMMC_IDMA_IDMABMODE_Pos (1U) |
| #define | SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos) |
| #define | SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk |
| #define | SDMMC_IDMABSIZE_IDMABNDT_Pos (5U) |
| #define | SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) |
| #define | SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk |
| #define | SDMMC_IDMABASER_IDMABASER ((uint32_t)0xFFFFFFFF) |
| #define | SDMMC_IDMALAR_IDMALA_Pos (0U) |
| #define | SDMMC_IDMALAR_IDMALA_Msk (0x3FFFUL << SDMMC_IDMALAR_IDMALA_Pos) |
| #define | SDMMC_IDMALAR_IDMALA SDMMC_IDMALAR_IDMALA_Msk |
| #define | SDMMC_IDMALAR_ABR_Pos (29U) |
| #define | SDMMC_IDMALAR_ABR_Msk (0x1UL << SDMMC_IDMALAR_ABR_Pos) |
| #define | SDMMC_IDMALAR_ABR SDMMC_IDMALAR_ABR_Msk |
| #define | SDMMC_IDMALAR_ULS_Pos (30U) |
| #define | SDMMC_IDMALAR_ULS_Msk (0x1UL << SDMMC_IDMALAR_ULS_Pos) |
| #define | SDMMC_IDMALAR_ULS SDMMC_IDMALAR_ULS_Msk |
| #define | SDMMC_IDMALAR_ULA_Pos (31U) |
| #define | SDMMC_IDMALAR_ULA_Msk (0x1UL << SDMMC_IDMALAR_ULA_Pos) |
| #define | SDMMC_IDMALAR_ULA SDMMC_IDMALAR_ULA_Msk |
| #define | SDMMC_IDMABAR_IDMABAR ((uint32_t)0xFFFFFFFF) |
| #define | XSPI_CR_EN_Pos (0U) |
| #define | XSPI_CR_EN_Msk (0x1UL << XSPI_CR_EN_Pos) |
| #define | XSPI_CR_EN XSPI_CR_EN_Msk |
| #define | XSPI_CR_ABORT_Pos (1U) |
| #define | XSPI_CR_ABORT_Msk (0x1UL << XSPI_CR_ABORT_Pos) |
| #define | XSPI_CR_ABORT XSPI_CR_ABORT_Msk |
| #define | XSPI_CR_DMAEN_Pos (2U) |
| #define | XSPI_CR_DMAEN_Msk (0x1UL << XSPI_CR_DMAEN_Pos) |
| #define | XSPI_CR_DMAEN XSPI_CR_DMAEN_Msk |
| #define | XSPI_CR_TCEN_Pos (3U) |
| #define | XSPI_CR_TCEN_Msk (0x1UL << XSPI_CR_TCEN_Pos) |
| #define | XSPI_CR_TCEN XSPI_CR_TCEN_Msk |
| #define | XSPI_CR_DMM_Pos (6U) |
| #define | XSPI_CR_DMM_Msk (0x1UL << XSPI_CR_DMM_Pos) |
| #define | XSPI_CR_DMM XSPI_CR_DMM_Msk |
| #define | XSPI_OCTOSPI_CR_MSEL_Pos (7U) |
| #define | XSPI_OCTOSPI_CR_MSEL_Msk (0x1UL << XSPI_OCTOSPI_CR_MSEL_Pos) |
| #define | XSPI_OCTOSPI_CR_MSEL XSPI_OCTOSPI_CR_MSEL_Msk |
| #define | XSPI_CR_FTHRES_Pos (8U) |
| #define | XSPI_CR_FTHRES_Msk (0x3FUL << XSPI_CR_FTHRES_Pos) |
| #define | XSPI_CR_FTHRES XSPI_CR_FTHRES_Msk |
| #define | XSPI_CR_TEIE_Pos (16U) |
| #define | XSPI_CR_TEIE_Msk (0x1UL << XSPI_CR_TEIE_Pos) |
| #define | XSPI_CR_TEIE XSPI_CR_TEIE_Msk |
| #define | XSPI_CR_TCIE_Pos (17U) |
| #define | XSPI_CR_TCIE_Msk (0x1UL << XSPI_CR_TCIE_Pos) |
| #define | XSPI_CR_TCIE XSPI_CR_TCIE_Msk |
| #define | XSPI_CR_FTIE_Pos (18U) |
| #define | XSPI_CR_FTIE_Msk (0x1UL << XSPI_CR_FTIE_Pos) |
| #define | XSPI_CR_FTIE XSPI_CR_FTIE_Msk |
| #define | XSPI_CR_SMIE_Pos (19U) |
| #define | XSPI_CR_SMIE_Msk (0x1UL << XSPI_CR_SMIE_Pos) |
| #define | XSPI_CR_SMIE XSPI_CR_SMIE_Msk |
| #define | XSPI_CR_TOIE_Pos (20U) |
| #define | XSPI_CR_TOIE_Msk (0x1UL << XSPI_CR_TOIE_Pos) |
| #define | XSPI_CR_TOIE XSPI_CR_TOIE_Msk |
| #define | XSPI_CR_APMS_Pos (22U) |
| #define | XSPI_CR_APMS_Msk (0x1UL << XSPI_CR_APMS_Pos) |
| #define | XSPI_CR_APMS XSPI_CR_APMS_Msk |
| #define | XSPI_CR_PMM_Pos (23U) |
| #define | XSPI_CR_PMM_Msk (0x1UL << XSPI_CR_PMM_Pos) |
| #define | XSPI_CR_PMM XSPI_CR_PMM_Msk |
| #define | XSPI_CR_FMODE_Pos (28U) |
| #define | XSPI_CR_FMODE_Msk (0x3UL << XSPI_CR_FMODE_Pos) |
| #define | XSPI_CR_FMODE XSPI_CR_FMODE_Msk |
| #define | XSPI_CR_FMODE_0 (0x1UL << XSPI_CR_FMODE_Pos) |
| #define | XSPI_CR_FMODE_1 (0x2UL << XSPI_CR_FMODE_Pos) |
| #define | XSPI_HSPI_CR_MSEL_Pos (30U) |
| #define | XSPI_HSPI_CR_MSEL_Msk (0x3UL << XSPI_HSPI_CR_MSEL_Pos) |
| #define | XSPI_HSPI_CR_MSEL XSPI_HSPI_CR_MSEL_Msk |
| #define | XSPI_HSPI_CR_MSEL_0 (0x1UL << XSPI_HSPI_CR_MSEL_Pos) |
| #define | XSPI_HSPI_CR_MSEL_1 (0x2UL << XSPI_HSPI_CR_MSEL_Pos) |
| #define | XSPI_DCR1_CKMODE_Pos (0U) |
| #define | XSPI_DCR1_CKMODE_Msk (0x1UL << XSPI_DCR1_CKMODE_Pos) |
| #define | XSPI_DCR1_CKMODE XSPI_DCR1_CKMODE_Msk |
| #define | XSPI_DCR1_FRCK_Pos (1U) |
| #define | XSPI_DCR1_FRCK_Msk (0x1UL << XSPI_DCR1_FRCK_Pos) |
| #define | XSPI_DCR1_FRCK XSPI_DCR1_FRCK_Msk |
| #define | XSPI_OCTOSPI_DCR1_DLYBYP_Pos (3U) |
| #define | XSPI_OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << XSPI_OCTOSPI_DCR1_DLYBYP_Pos) |
| #define | XSPI_OCTOSPI_DCR1_DLYBYP XSPI_OCTOSPI_DCR1_DLYBYP_Msk |
| #define | XSPI_DCR1_CSHT_Pos (8U) |
| #define | XSPI_DCR1_CSHT_Msk (0x3FUL << XSPI_DCR1_CSHT_Pos) |
| #define | XSPI_DCR1_CSHT XSPI_DCR1_CSHT_Msk |
| #define | XSPI_DCR1_DEVSIZE_Pos (16U) |
| #define | XSPI_DCR1_DEVSIZE_Msk (0x1FUL << XSPI_DCR1_DEVSIZE_Pos) |
| #define | XSPI_DCR1_DEVSIZE XSPI_DCR1_DEVSIZE_Msk |
| #define | XSPI_DCR1_MTYP_Pos (24U) |
| #define | XSPI_DCR1_MTYP_Msk (0x7UL << XSPI_DCR1_MTYP_Pos) |
| #define | XSPI_DCR1_MTYP XSPI_DCR1_MTYP_Msk |
| #define | XSPI_DCR1_MTYP_0 (0x1UL << XSPI_DCR1_MTYP_Pos) |
| #define | XSPI_DCR1_MTYP_1 (0x2UL << XSPI_DCR1_MTYP_Pos) |
| #define | XSPI_DCR1_MTYP_2 (0x4UL << XSPI_DCR1_MTYP_Pos) |
| #define | XSPI_DCR2_PRESCALER_Pos (0U) |
| #define | XSPI_DCR2_PRESCALER_Msk (0xFFUL << XSPI_DCR2_PRESCALER_Pos) |
| #define | XSPI_DCR2_PRESCALER XSPI_DCR2_PRESCALER_Msk |
| #define | XSPI_DCR2_WRAPSIZE_Pos (16U) |
| #define | XSPI_DCR2_WRAPSIZE_Msk (0x7UL << XSPI_DCR2_WRAPSIZE_Pos) |
| #define | XSPI_DCR2_WRAPSIZE XSPI_DCR2_WRAPSIZE_Msk |
| #define | XSPI_DCR2_WRAPSIZE_0 (0x1UL << XSPI_DCR2_WRAPSIZE_Pos) |
| #define | XSPI_DCR2_WRAPSIZE_1 (0x2UL << XSPI_DCR2_WRAPSIZE_Pos) |
| #define | XSPI_DCR2_WRAPSIZE_2 (0x4UL << XSPI_DCR2_WRAPSIZE_Pos) |
| #define | XSPI_OCTOSPI_DCR3_MAXTRAN_Pos (0U) |
| #define | XSPI_OCTOSPI_DCR3_MAXTRAN_Msk (0xFFUL << XSPI_OCTOSPI_DCR3_MAXTRAN_Pos) |
| #define | XSPI_OCTOSPI_DCR3_MAXTRAN XSPI_OCTOSPI_DCR3_MAXTRAN_Msk |
| #define | XSPI_DCR3_CSBOUND_Pos (16U) |
| #define | XSPI_DCR3_CSBOUND_Msk (0x1FUL << XSPI_DCR3_CSBOUND_Pos) |
| #define | XSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND_Msk |
| #define | XSPI_DCR4_REFRESH_Pos (0U) |
| #define | XSPI_DCR4_REFRESH_Msk (0xFFFFFFFFUL << XSPI_DCR4_REFRESH_Pos) |
| #define | XSPI_DCR4_REFRESH XSPI_DCR4_REFRESH_Msk |
| #define | XSPI_SR_TEF_Pos (0U) |
| #define | XSPI_SR_TEF_Msk (0x1UL << XSPI_SR_TEF_Pos) |
| #define | XSPI_SR_TEF XSPI_SR_TEF_Msk |
| #define | XSPI_SR_TCF_Pos (1U) |
| #define | XSPI_SR_TCF_Msk (0x1UL << XSPI_SR_TCF_Pos) |
| #define | XSPI_SR_TCF XSPI_SR_TCF_Msk |
| #define | XSPI_SR_FTF_Pos (2U) |
| #define | XSPI_SR_FTF_Msk (0x1UL << XSPI_SR_FTF_Pos) |
| #define | XSPI_SR_FTF XSPI_SR_FTF_Msk |
| #define | XSPI_SR_SMF_Pos (3U) |
| #define | XSPI_SR_SMF_Msk (0x1UL << XSPI_SR_SMF_Pos) |
| #define | XSPI_SR_SMF XSPI_SR_SMF_Msk |
| #define | XSPI_SR_TOF_Pos (4U) |
| #define | XSPI_SR_TOF_Msk (0x1UL << XSPI_SR_TOF_Pos) |
| #define | XSPI_SR_TOF XSPI_SR_TOF_Msk |
| #define | XSPI_SR_BUSY_Pos (5U) |
| #define | XSPI_SR_BUSY_Msk (0x1UL << XSPI_SR_BUSY_Pos) |
| #define | XSPI_SR_BUSY XSPI_SR_BUSY_Msk |
| #define | XSPI_SR_FLEVEL_Pos (8U) |
| #define | XSPI_SR_FLEVEL_Msk (0x7FUL << XSPI_SR_FLEVEL_Pos) |
| #define | XSPI_SR_FLEVEL XSPI_SR_FLEVEL_Msk |
| #define | XSPI_FCR_CTEF_Pos (0U) |
| #define | XSPI_FCR_CTEF_Msk (0x1UL << XSPI_FCR_CTEF_Pos) |
| #define | XSPI_FCR_CTEF XSPI_FCR_CTEF_Msk |
| #define | XSPI_FCR_CTCF_Pos (1U) |
| #define | XSPI_FCR_CTCF_Msk (0x1UL << XSPI_FCR_CTCF_Pos) |
| #define | XSPI_FCR_CTCF XSPI_FCR_CTCF_Msk |
| #define | XSPI_FCR_CSMF_Pos (3U) |
| #define | XSPI_FCR_CSMF_Msk (0x1UL << XSPI_FCR_CSMF_Pos) |
| #define | XSPI_FCR_CSMF XSPI_FCR_CSMF_Msk |
| #define | XSPI_FCR_CTOF_Pos (4U) |
| #define | XSPI_FCR_CTOF_Msk (0x1UL << XSPI_FCR_CTOF_Pos) |
| #define | XSPI_FCR_CTOF XSPI_FCR_CTOF_Msk |
| #define | XSPI_DLR_DL_Pos (0U) |
| #define | XSPI_DLR_DL_Msk (0xFFFFFFFFUL << XSPI_DLR_DL_Pos) |
| #define | XSPI_DLR_DL XSPI_DLR_DL_Msk |
| #define | XSPI_AR_ADDRESS_Pos (0U) |
| #define | XSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << XSPI_AR_ADDRESS_Pos) |
| #define | XSPI_AR_ADDRESS XSPI_AR_ADDRESS_Msk |
| #define | XSPI_DR_DATA_Pos (0U) |
| #define | XSPI_DR_DATA_Msk (0xFFFFFFFFUL << XSPI_DR_DATA_Pos) |
| #define | XSPI_DR_DATA XSPI_DR_DATA_Msk |
| #define | XSPI_PSMKR_MASK_Pos (0U) |
| #define | XSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << XSPI_PSMKR_MASK_Pos) |
| #define | XSPI_PSMKR_MASK XSPI_PSMKR_MASK_Msk |
| #define | XSPI_PSMAR_MATCH_Pos (0U) |
| #define | XSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << XSPI_PSMAR_MATCH_Pos) |
| #define | XSPI_PSMAR_MATCH XSPI_PSMAR_MATCH_Msk |
| #define | XSPI_PIR_INTERVAL_Pos (0U) |
| #define | XSPI_PIR_INTERVAL_Msk (0xFFFFUL << XSPI_PIR_INTERVAL_Pos) |
| #define | XSPI_PIR_INTERVAL XSPI_PIR_INTERVAL_Msk |
| #define | XSPI_CCR_IMODE_Pos (0U) |
| #define | XSPI_CCR_IMODE_Msk (0x7UL << XSPI_CCR_IMODE_Pos) |
| #define | XSPI_CCR_IMODE XSPI_CCR_IMODE_Msk |
| #define | XSPI_CCR_IMODE_0 (0x1UL << XSPI_CCR_IMODE_Pos) |
| #define | XSPI_CCR_IMODE_1 (0x2UL << XSPI_CCR_IMODE_Pos) |
| #define | XSPI_CCR_IMODE_2 (0x4UL << XSPI_CCR_IMODE_Pos) |
| #define | XSPI_CCR_IDTR_Pos (3U) |
| #define | XSPI_CCR_IDTR_Msk (0x1UL << XSPI_CCR_IDTR_Pos) |
| #define | XSPI_CCR_IDTR XSPI_CCR_IDTR_Msk |
| #define | XSPI_CCR_ISIZE_Pos (4U) |
| #define | XSPI_CCR_ISIZE_Msk (0x3UL << XSPI_CCR_ISIZE_Pos) |
| #define | XSPI_CCR_ISIZE XSPI_CCR_ISIZE_Msk |
| #define | XSPI_CCR_ISIZE_0 (0x1UL << XSPI_CCR_ISIZE_Pos) |
| #define | XSPI_CCR_ISIZE_1 (0x2UL << XSPI_CCR_ISIZE_Pos) |
| #define | XSPI_CCR_ADMODE_Pos (8U) |
| #define | XSPI_CCR_ADMODE_Msk (0x7UL << XSPI_CCR_ADMODE_Pos) |
| #define | XSPI_CCR_ADMODE XSPI_CCR_ADMODE_Msk |
| #define | XSPI_CCR_ADMODE_0 (0x1UL << XSPI_CCR_ADMODE_Pos) |
| #define | XSPI_CCR_ADMODE_1 (0x2UL << XSPI_CCR_ADMODE_Pos) |
| #define | XSPI_CCR_ADMODE_2 (0x4UL << XSPI_CCR_ADMODE_Pos) |
| #define | XSPI_CCR_ADDTR_Pos (11U) |
| #define | XSPI_CCR_ADDTR_Msk (0x1UL << XSPI_CCR_ADDTR_Pos) |
| #define | XSPI_CCR_ADDTR XSPI_CCR_ADDTR_Msk |
| #define | XSPI_CCR_ADSIZE_Pos (12U) |
| #define | XSPI_CCR_ADSIZE_Msk (0x3UL << XSPI_CCR_ADSIZE_Pos) |
| #define | XSPI_CCR_ADSIZE XSPI_CCR_ADSIZE_Msk |
| #define | XSPI_CCR_ADSIZE_0 (0x1UL << XSPI_CCR_ADSIZE_Pos) |
| #define | XSPI_CCR_ADSIZE_1 (0x2UL << XSPI_CCR_ADSIZE_Pos) |
| #define | XSPI_CCR_ABMODE_Pos (16U) |
| #define | XSPI_CCR_ABMODE_Msk (0x7UL << XSPI_CCR_ABMODE_Pos) |
| #define | XSPI_CCR_ABMODE XSPI_CCR_ABMODE_Msk |
| #define | XSPI_CCR_ABMODE_0 (0x1UL << XSPI_CCR_ABMODE_Pos) |
| #define | XSPI_CCR_ABMODE_1 (0x2UL << XSPI_CCR_ABMODE_Pos) |
| #define | XSPI_CCR_ABMODE_2 (0x4UL << XSPI_CCR_ABMODE_Pos) |
| #define | XSPI_CCR_ABDTR_Pos (19U) |
| #define | XSPI_CCR_ABDTR_Msk (0x1UL << XSPI_CCR_ABDTR_Pos) |
| #define | XSPI_CCR_ABDTR XSPI_CCR_ABDTR_Msk |
| #define | XSPI_CCR_ABSIZE_Pos (20U) |
| #define | XSPI_CCR_ABSIZE_Msk (0x3UL << XSPI_CCR_ABSIZE_Pos) |
| #define | XSPI_CCR_ABSIZE XSPI_CCR_ABSIZE_Msk |
| #define | XSPI_CCR_ABSIZE_0 (0x1UL << XSPI_CCR_ABSIZE_Pos) |
| #define | XSPI_CCR_ABSIZE_1 (0x2UL << XSPI_CCR_ABSIZE_Pos) |
| #define | XSPI_CCR_DMODE_Pos (24U) |
| #define | XSPI_CCR_DMODE_Msk (0x7UL << XSPI_CCR_DMODE_Pos) |
| #define | XSPI_CCR_DMODE XSPI_CCR_DMODE_Msk |
| #define | XSPI_CCR_DMODE_0 (0x1UL << XSPI_CCR_DMODE_Pos) |
| #define | XSPI_CCR_DMODE_1 (0x2UL << XSPI_CCR_DMODE_Pos) |
| #define | XSPI_CCR_DMODE_2 (0x4UL << XSPI_CCR_DMODE_Pos) |
| #define | XSPI_CCR_DDTR_Pos (27U) |
| #define | XSPI_CCR_DDTR_Msk (0x1UL << XSPI_CCR_DDTR_Pos) |
| #define | XSPI_CCR_DDTR XSPI_CCR_DDTR_Msk |
| #define | XSPI_CCR_DQSE_Pos (29U) |
| #define | XSPI_CCR_DQSE_Msk (0x1UL << XSPI_CCR_DQSE_Pos) |
| #define | XSPI_CCR_DQSE XSPI_CCR_DQSE_Msk |
| #define | XSPI_CCR_SIOO_Pos (31U) |
| #define | XSPI_CCR_SIOO_Msk (0x1UL << XSPI_CCR_SIOO_Pos) |
| #define | XSPI_CCR_SIOO XSPI_CCR_SIOO_Msk |
| #define | XSPI_TCR_DCYC_Pos (0U) |
| #define | XSPI_TCR_DCYC_Msk (0x1FUL << XSPI_TCR_DCYC_Pos) |
| #define | XSPI_TCR_DCYC XSPI_TCR_DCYC_Msk |
| #define | XSPI_TCR_DHQC_Pos (28U) |
| #define | XSPI_TCR_DHQC_Msk (0x1UL << XSPI_TCR_DHQC_Pos) |
| #define | XSPI_TCR_DHQC XSPI_TCR_DHQC_Msk |
| #define | XSPI_TCR_SSHIFT_Pos (30U) |
| #define | XSPI_TCR_SSHIFT_Msk (0x1UL << XSPI_TCR_SSHIFT_Pos) |
| #define | XSPI_TCR_SSHIFT XSPI_TCR_SSHIFT_Msk |
| #define | XSPI_IR_INSTRUCTION_Pos (0U) |
| #define | XSPI_IR_INSTRUCTION_Msk (0xFFFFFFFFUL << XSPI_IR_INSTRUCTION_Pos) |
| #define | XSPI_IR_INSTRUCTION XSPI_IR_INSTRUCTION_Msk |
| #define | XSPI_ABR_ALTERNATE_Pos (0U) |
| #define | XSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << XSPI_ABR_ALTERNATE_Pos) |
| #define | XSPI_ABR_ALTERNATE XSPI_ABR_ALTERNATE_Msk |
| #define | XSPI_LPTR_TIMEOUT_Pos (0U) |
| #define | XSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << XSPI_LPTR_TIMEOUT_Pos) |
| #define | XSPI_LPTR_TIMEOUT XSPI_LPTR_TIMEOUT_Msk |
| #define | XSPI_WPCCR_IMODE_Pos (0U) |
| #define | XSPI_WPCCR_IMODE_Msk (0x7UL << XSPI_WPCCR_IMODE_Pos) |
| #define | XSPI_WPCCR_IMODE XSPI_WPCCR_IMODE_Msk |
| #define | XSPI_WPCCR_IMODE_0 (0x1UL << XSPI_WPCCR_IMODE_Pos) |
| #define | XSPI_WPCCR_IMODE_1 (0x2UL << XSPI_WPCCR_IMODE_Pos) |
| #define | XSPI_WPCCR_IMODE_2 (0x4UL << XSPI_WPCCR_IMODE_Pos) |
| #define | XSPI_WPCCR_IDTR_Pos (3U) |
| #define | XSPI_WPCCR_IDTR_Msk (0x1UL << XSPI_WPCCR_IDTR_Pos) |
| #define | XSPI_WPCCR_IDTR XSPI_WPCCR_IDTR_Msk |
| #define | XSPI_WPCCR_ISIZE_Pos (4U) |
| #define | XSPI_WPCCR_ISIZE_Msk (0x3UL << XSPI_WPCCR_ISIZE_Pos) |
| #define | XSPI_WPCCR_ISIZE XSPI_WPCCR_ISIZE_Msk |
| #define | XSPI_WPCCR_ISIZE_0 (0x1UL << XSPI_WPCCR_ISIZE_Pos) |
| #define | XSPI_WPCCR_ISIZE_1 (0x2UL << XSPI_WPCCR_ISIZE_Pos) |
| #define | XSPI_WPCCR_ADMODE_Pos (8U) |
| #define | XSPI_WPCCR_ADMODE_Msk (0x7UL << XSPI_WPCCR_ADMODE_Pos) |
| #define | XSPI_WPCCR_ADMODE XSPI_WPCCR_ADMODE_Msk |
| #define | XSPI_WPCCR_ADMODE_0 (0x1UL << XSPI_WPCCR_ADMODE_Pos) |
| #define | XSPI_WPCCR_ADMODE_1 (0x2UL << XSPI_WPCCR_ADMODE_Pos) |
| #define | XSPI_WPCCR_ADMODE_2 (0x4UL << XSPI_WPCCR_ADMODE_Pos) |
| #define | XSPI_WPCCR_ADDTR_Pos (11U) |
| #define | XSPI_WPCCR_ADDTR_Msk (0x1UL << XSPI_WPCCR_ADDTR_Pos) |
| #define | XSPI_WPCCR_ADDTR XSPI_WPCCR_ADDTR_Msk |
| #define | XSPI_WPCCR_ADSIZE_Pos (12U) |
| #define | XSPI_WPCCR_ADSIZE_Msk (0x3UL << XSPI_WPCCR_ADSIZE_Pos) |
| #define | XSPI_WPCCR_ADSIZE XSPI_WPCCR_ADSIZE_Msk |
| #define | XSPI_WPCCR_ADSIZE_0 (0x1UL << XSPI_WPCCR_ADSIZE_Pos) |
| #define | XSPI_WPCCR_ADSIZE_1 (0x2UL << XSPI_WPCCR_ADSIZE_Pos) |
| #define | XSPI_WPCCR_ABMODE_Pos (16U) |
| #define | XSPI_WPCCR_ABMODE_Msk (0x7UL << XSPI_WPCCR_ABMODE_Pos) |
| #define | XSPI_WPCCR_ABMODE XSPI_WPCCR_ABMODE_Msk |
| #define | XSPI_WPCCR_ABMODE_0 (0x1UL << XSPI_WPCCR_ABMODE_Pos) |
| #define | XSPI_WPCCR_ABMODE_1 (0x2UL << XSPI_WPCCR_ABMODE_Pos) |
| #define | XSPI_WPCCR_ABMODE_2 (0x4UL << XSPI_WPCCR_ABMODE_Pos) |
| #define | XSPI_WPCCR_ABDTR_Pos (19U) |
| #define | XSPI_WPCCR_ABDTR_Msk (0x1UL << XSPI_WPCCR_ABDTR_Pos) |
| #define | XSPI_WPCCR_ABDTR XSPI_WPCCR_ABDTR_Msk |
| #define | XSPI_WPCCR_ABSIZE_Pos (20U) |
| #define | XSPI_WPCCR_ABSIZE_Msk (0x3UL << XSPI_WPCCR_ABSIZE_Pos) |
| #define | XSPI_WPCCR_ABSIZE XSPI_WPCCR_ABSIZE_Msk |
| #define | XSPI_WPCCR_ABSIZE_0 (0x1UL << XSPI_WPCCR_ABSIZE_Pos) |
| #define | XSPI_WPCCR_ABSIZE_1 (0x2UL << XSPI_WPCCR_ABSIZE_Pos) |
| #define | XSPI_WPCCR_DMODE_Pos (24U) |
| #define | XSPI_WPCCR_DMODE_Msk (0x7UL << XSPI_WPCCR_DMODE_Pos) |
| #define | XSPI_WPCCR_DMODE XSPI_WPCCR_DMODE_Msk |
| #define | XSPI_WPCCR_DMODE_0 (0x1UL << XSPI_WPCCR_DMODE_Pos) |
| #define | XSPI_WPCCR_DMODE_1 (0x2UL << XSPI_WPCCR_DMODE_Pos) |
| #define | XSPI_WPCCR_DMODE_2 (0x4UL << XSPI_WPCCR_DMODE_Pos) |
| #define | XSPI_WPCCR_DDTR_Pos (27U) |
| #define | XSPI_WPCCR_DDTR_Msk (0x1UL << XSPI_WPCCR_DDTR_Pos) |
| #define | XSPI_WPCCR_DDTR XSPI_WPCCR_DDTR_Msk |
| #define | XSPI_WPCCR_DQSE_Pos (29U) |
| #define | XSPI_WPCCR_DQSE_Msk (0x1UL << XSPI_WPCCR_DQSE_Pos) |
| #define | XSPI_WPCCR_DQSE XSPI_WPCCR_DQSE_Msk |
| #define | XSPI_WPTCR_DCYC_Pos (0U) |
| #define | XSPI_WPTCR_DCYC_Msk (0x1FUL << XSPI_WPTCR_DCYC_Pos) |
| #define | XSPI_WPTCR_DCYC XSPI_WPTCR_DCYC_Msk |
| #define | XSPI_WPTCR_DHQC_Pos (28U) |
| #define | XSPI_WPTCR_DHQC_Msk (0x1UL << XSPI_WPTCR_DHQC_Pos) |
| #define | XSPI_WPTCR_DHQC XSPI_WPTCR_DHQC_Msk |
| #define | XSPI_WPTCR_SSHIFT_Pos (30U) |
| #define | XSPI_WPTCR_SSHIFT_Msk (0x1UL << XSPI_WPTCR_SSHIFT_Pos) |
| #define | XSPI_WPTCR_SSHIFT XSPI_WPTCR_SSHIFT_Msk |
| #define | XSPI_WPIR_INSTRUCTION_Pos (0U) |
| #define | XSPI_WPIR_INSTRUCTION_Msk (0xFFFFFFFFUL << XSPI_WPIR_INSTRUCTION_Pos) |
| #define | XSPI_WPIR_INSTRUCTION XSPI_WPIR_INSTRUCTION_Msk |
| #define | XSPI_WPABR_ALTERNATE_Pos (0U) |
| #define | XSPI_WPABR_ALTERNATE_Msk (0xFFFFFFFFUL << XSPI_WPABR_ALTERNATE_Pos) |
| #define | XSPI_WPABR_ALTERNATE XSPI_WPABR_ALTERNATE_Msk |
| #define | XSPI_WCCR_IMODE_Pos (0U) |
| #define | XSPI_WCCR_IMODE_Msk (0x7UL << XSPI_WCCR_IMODE_Pos) |
| #define | XSPI_WCCR_IMODE XSPI_WCCR_IMODE_Msk |
| #define | XSPI_WCCR_IMODE_0 (0x1UL << XSPI_WCCR_IMODE_Pos) |
| #define | XSPI_WCCR_IMODE_1 (0x2UL << XSPI_WCCR_IMODE_Pos) |
| #define | XSPI_WCCR_IMODE_2 (0x4UL << XSPI_WCCR_IMODE_Pos) |
| #define | XSPI_WCCR_IDTR_Pos (3U) |
| #define | XSPI_WCCR_IDTR_Msk (0x1UL << XSPI_WCCR_IDTR_Pos) |
| #define | XSPI_WCCR_IDTR XSPI_WCCR_IDTR_Msk |
| #define | XSPI_WCCR_ISIZE_Pos (4U) |
| #define | XSPI_WCCR_ISIZE_Msk (0x3UL << XSPI_WCCR_ISIZE_Pos) |
| #define | XSPI_WCCR_ISIZE XSPI_WCCR_ISIZE_Msk |
| #define | XSPI_WCCR_ISIZE_0 (0x1UL << XSPI_WCCR_ISIZE_Pos) |
| #define | XSPI_WCCR_ISIZE_1 (0x2UL << XSPI_WCCR_ISIZE_Pos) |
| #define | XSPI_WCCR_ADMODE_Pos (8U) |
| #define | XSPI_WCCR_ADMODE_Msk (0x7UL << XSPI_WCCR_ADMODE_Pos) |
| #define | XSPI_WCCR_ADMODE XSPI_WCCR_ADMODE_Msk |
| #define | XSPI_WCCR_ADMODE_0 (0x1UL << XSPI_WCCR_ADMODE_Pos) |
| #define | XSPI_WCCR_ADMODE_1 (0x2UL << XSPI_WCCR_ADMODE_Pos) |
| #define | XSPI_WCCR_ADMODE_2 (0x4UL << XSPI_WCCR_ADMODE_Pos) |
| #define | XSPI_WCCR_ADDTR_Pos (11U) |
| #define | XSPI_WCCR_ADDTR_Msk (0x1UL << XSPI_WCCR_ADDTR_Pos) |
| #define | XSPI_WCCR_ADDTR XSPI_WCCR_ADDTR_Msk |
| #define | XSPI_WCCR_ADSIZE_Pos (12U) |
| #define | XSPI_WCCR_ADSIZE_Msk (0x3UL << XSPI_WCCR_ADSIZE_Pos) |
| #define | XSPI_WCCR_ADSIZE XSPI_WCCR_ADSIZE_Msk |
| #define | XSPI_WCCR_ADSIZE_0 (0x1UL << XSPI_WCCR_ADSIZE_Pos) |
| #define | XSPI_WCCR_ADSIZE_1 (0x2UL << XSPI_WCCR_ADSIZE_Pos) |
| #define | XSPI_WCCR_ABMODE_Pos (16U) |
| #define | XSPI_WCCR_ABMODE_Msk (0x7UL << XSPI_WCCR_ABMODE_Pos) |
| #define | XSPI_WCCR_ABMODE XSPI_WCCR_ABMODE_Msk |
| #define | XSPI_WCCR_ABMODE_0 (0x1UL << XSPI_WCCR_ABMODE_Pos) |
| #define | XSPI_WCCR_ABMODE_1 (0x2UL << XSPI_WCCR_ABMODE_Pos) |
| #define | XSPI_WCCR_ABMODE_2 (0x4UL << XSPI_WCCR_ABMODE_Pos) |
| #define | XSPI_WCCR_ABDTR_Pos (19U) |
| #define | XSPI_WCCR_ABDTR_Msk (0x1UL << XSPI_WCCR_ABDTR_Pos) |
| #define | XSPI_WCCR_ABDTR XSPI_WCCR_ABDTR_Msk |
| #define | XSPI_WCCR_ABSIZE_Pos (20U) |
| #define | XSPI_WCCR_ABSIZE_Msk (0x3UL << XSPI_WCCR_ABSIZE_Pos) |
| #define | XSPI_WCCR_ABSIZE XSPI_WCCR_ABSIZE_Msk |
| #define | XSPI_WCCR_ABSIZE_0 (0x1UL << XSPI_WCCR_ABSIZE_Pos) |
| #define | XSPI_WCCR_ABSIZE_1 (0x2UL << XSPI_WCCR_ABSIZE_Pos) |
| #define | XSPI_WCCR_DMODE_Pos (24U) |
| #define | XSPI_WCCR_DMODE_Msk (0x7UL << XSPI_WCCR_DMODE_Pos) |
| #define | XSPI_WCCR_DMODE XSPI_WCCR_DMODE_Msk |
| #define | XSPI_WCCR_DMODE_0 (0x1UL << XSPI_WCCR_DMODE_Pos) |
| #define | XSPI_WCCR_DMODE_1 (0x2UL << XSPI_WCCR_DMODE_Pos) |
| #define | XSPI_WCCR_DMODE_2 (0x4UL << XSPI_WCCR_DMODE_Pos) |
| #define | XSPI_WCCR_DDTR_Pos (27U) |
| #define | XSPI_WCCR_DDTR_Msk (0x1UL << XSPI_WCCR_DDTR_Pos) |
| #define | XSPI_WCCR_DDTR XSPI_WCCR_DDTR_Msk |
| #define | XSPI_WCCR_DQSE_Pos (29U) |
| #define | XSPI_WCCR_DQSE_Msk (0x1UL << XSPI_WCCR_DQSE_Pos) |
| #define | XSPI_WCCR_DQSE XSPI_WCCR_DQSE_Msk |
| #define | XSPI_WTCR_DCYC_Pos (0U) |
| #define | XSPI_WTCR_DCYC_Msk (0x1FUL << XSPI_WTCR_DCYC_Pos) |
| #define | XSPI_WTCR_DCYC XSPI_WTCR_DCYC_Msk |
| #define | XSPI_WIR_INSTRUCTION_Pos (0U) |
| #define | XSPI_WIR_INSTRUCTION_Msk (0xFFFFFFFFUL << XSPI_WIR_INSTRUCTION_Pos) |
| #define | XSPI_WIR_INSTRUCTION XSPI_WIR_INSTRUCTION_Msk |
| #define | XSPI_WABR_ALTERNATE_Pos (0U) |
| #define | XSPI_WABR_ALTERNATE_Msk (0xFFFFFFFFUL << XSPI_WABR_ALTERNATE_Pos) |
| #define | XSPI_WABR_ALTERNATE XSPI_WABR_ALTERNATE_Msk |
| #define | XSPI_HLCR_LM_Pos (0U) |
| #define | XSPI_HLCR_LM_Msk (0x1UL << XSPI_HLCR_LM_Pos) |
| #define | XSPI_HLCR_LM XSPI_HLCR_LM_Msk |
| #define | XSPI_HLCR_WZL_Pos (1U) |
| #define | XSPI_HLCR_WZL_Msk (0x1UL << XSPI_HLCR_WZL_Pos) |
| #define | XSPI_HLCR_WZL XSPI_HLCR_WZL_Msk |
| #define | XSPI_HLCR_TACC_Pos (8U) |
| #define | XSPI_HLCR_TACC_Msk (0xFFUL << XSPI_HLCR_TACC_Pos) |
| #define | XSPI_HLCR_TACC XSPI_HLCR_TACC_Msk |
| #define | XSPI_HLCR_TRWR_Pos (16U) |
| #define | XSPI_HLCR_TRWR_Msk (0xFFUL << XSPI_HLCR_TRWR_Pos) |
| #define | XSPI_HLCR_TRWR XSPI_HLCR_TRWR_Msk |
| #define | XSPI_HSPI_CALFCR_FINE_Pos (0U) |
| #define | XSPI_HSPI_CALFCR_FINE_Msk (0x7FUL << XSPI_HSPI_CALFCR_FINE_Pos) |
| #define | XSPI_HSPI_CALFCR_FINE XSPI_HSPI_CALFCR_FINE_Msk |
| #define | XSPI_HSPI_CALFCR_COARSE_Pos (16U) |
| #define | XSPI_HSPI_CALFCR_COARSE_Msk (0x1FUL << XSPI_HSPI_CALFCR_COARSE_Pos) |
| #define | XSPI_HSPI_CALFCR_COARSE XSPI_HSPI_CALFCR_COARSE_Msk |
| #define | XSPI_HSPI_CALFCR_CALMAX_Pos (31U) |
| #define | XSPI_HSPI_CALFCR_CALMAX_Msk (0x1UL << XSPI_HSPI_CALFCR_CALMAX_Pos) |
| #define | XSPI_HSPI_CALFCR_CALMAX XSPI_HSPI_CALFCR_CALMAX_Msk |
| #define | XSPI_HSPI_CALMR_FINE_Pos (0U) |
| #define | XSPI_HSPI_CALMR_FINE_Msk (0x7FUL << XSPI_HSPI_CALMR_FINE_Pos) |
| #define | XSPI_HSPI_CALMR_FINE XSPI_HSPI_CALMR_FINE_Msk |
| #define | XSPI_HSPI_CALMR_COARSE_Pos (16U) |
| #define | XSPI_HSPI_CALMR_COARSE_Msk (0x1FUL << XSPI_HSPI_CALMR_COARSE_Pos) |
| #define | XSPI_HSPI_CALMR_COARSE XSPI_HSPI_CALMR_COARSE_Msk |
| #define | XSPI_HSPI_CALSOR_FINE_Pos (0U) |
| #define | XSPI_HSPI_CALSOR_FINE_Msk (0x7FUL << XSPI_HSPI_CALSOR_FINE_Pos) |
| #define | XSPI_HSPI_CALSOR_FINE XSPI_HSPI_CALSOR_FINE_Msk |
| #define | XSPI_HSPI_CALSOR_COARSE_Pos (16U) |
| #define | XSPI_HSPI_CALSOR_COARSE_Msk (0x1FUL << XSPI_HSPI_CALSOR_COARSE_Pos) |
| #define | XSPI_HSPI_CALSOR_COARSE XSPI_HSPI_CALSOR_COARSE_Msk |
| #define | XSPI_HSPI_CALSIR_FINE_Pos (0U) |
| #define | XSPI_HSPI_CALSIR_FINE_Msk (0x7FUL << XSPI_HSPI_CALSIR_FINE_Pos) |
| #define | XSPI_HSPI_CALSIR_FINE XSPI_HSPI_CALSIR_FINE_Msk |
| #define | XSPI_HSPI_CALSIR_COARSE_Pos (16U) |
| #define | XSPI_HSPI_CALSIR_COARSE_Msk (0x1FUL << XSPI_HSPI_CALSIR_COARSE_Pos) |
| #define | XSPI_HSPI_CALSIR_COARSE XSPI_HSPI_CALSIR_COARSE_Msk |
| #define | OCTOSPI_CR_EN_Pos XSPI_CR_EN_Pos |
| #define | OCTOSPI_CR_EN_Msk XSPI_CR_EN_Msk |
| #define | OCTOSPI_CR_EN XSPI_CR_EN |
| #define | OCTOSPI_CR_ABORT_Pos XSPI_CR_ABORT_Pos |
| #define | OCTOSPI_CR_ABORT_Msk XSPI_CR_ABORT_Msk |
| #define | OCTOSPI_CR_ABORT XSPI_CR_ABORT |
| #define | OCTOSPI_CR_DMAEN_Pos XSPI_CR_DMAEN_Pos |
| #define | OCTOSPI_CR_DMAEN_Msk XSPI_CR_DMAEN_Msk |
| #define | OCTOSPI_CR_DMAEN XSPI_CR_DMAEN |
| #define | OCTOSPI_CR_TCEN_Pos XSPI_CR_TCEN_Pos |
| #define | OCTOSPI_CR_TCEN_Msk XSPI_CR_TCEN_Msk |
| #define | OCTOSPI_CR_TCEN XSPI_CR_TCEN |
| #define | OCTOSPI_CR_DMM_Pos XSPI_CR_DMM_Pos |
| #define | OCTOSPI_CR_DMM_Msk XSPI_CR_DMM_Msk |
| #define | OCTOSPI_CR_DMM XSPI_CR_DMM |
| #define | OCTOSPI_CR_MSEL_Pos XSPI_OCTOSPI_CR_MSEL_Pos |
| #define | OCTOSPI_CR_MSEL_Msk XSPI_OCTOSPI_CR_MSEL_Msk |
| #define | OCTOSPI_CR_MSEL XSPI_OCTOSPI_CR_MSEL |
| #define | OCTOSPI_CR_FTHRES_Pos XSPI_CR_FTHRES_Pos |
| #define | OCTOSPI_CR_FTHRES_Msk (0x1FUL << OCTOSPI_CR_FTHRES_Pos) |
| #define | OCTOSPI_CR_FTHRES XSPI_CR_FTHRES |
| #define | OCTOSPI_CR_TEIE_Pos XSPI_CR_TEIE_Pos |
| #define | OCTOSPI_CR_TEIE_Msk XSPI_CR_TEIE_Msk |
| #define | OCTOSPI_CR_TEIE XSPI_CR_TEIE |
| #define | OCTOSPI_CR_TCIE_Pos XSPI_CR_TCIE_Pos |
| #define | OCTOSPI_CR_TCIE_Msk XSPI_CR_TCIE_Msk |
| #define | OCTOSPI_CR_TCIE XSPI_CR_TCIE |
| #define | OCTOSPI_CR_FTIE_Pos XSPI_CR_FTIE_Pos |
| #define | OCTOSPI_CR_FTIE_Msk XSPI_CR_FTIE_Msk) |
| #define | OCTOSPI_CR_FTIE XSPI_CR_FTIE |
| #define | OCTOSPI_CR_SMIE_Pos XSPI_CR_SMIE_Pos |
| #define | OCTOSPI_CR_SMIE_Msk XSPI_CR_SMIE_Msk |
| #define | OCTOSPI_CR_SMIE XSPI_CR_SMIE |
| #define | OCTOSPI_CR_TOIE_Pos XSPI_CR_TOIE_Pos |
| #define | OCTOSPI_CR_TOIE_Msk XSPI_CR_TOIE_Msk |
| #define | OCTOSPI_CR_TOIE XSPI_CR_TOIE |
| #define | OCTOSPI_CR_APMS_Pos XSPI_CR_APMS_Pos |
| #define | OCTOSPI_CR_APMS_Msk XSPI_CR_APMS_Msk |
| #define | OCTOSPI_CR_APMS XSPI_CR_APMS |
| #define | OCTOSPI_CR_PMM_Pos XSPI_CR_PMM_Pos |
| #define | OCTOSPI_CR_PMM_Msk XSPI_CR_PMM_Msk |
| #define | OCTOSPI_CR_PMM XSPI_CR_PMM |
| #define | OCTOSPI_CR_FMODE_Pos XSPI_CR_FMODE_Pos |
| #define | OCTOSPI_CR_FMODE_Msk XSPI_CR_FMODE_Msk |
| #define | OCTOSPI_CR_FMODE XSPI_CR_FMODE |
| #define | OCTOSPI_CR_FMODE_0 XSPI_CR_FMODE_0 |
| #define | OCTOSPI_CR_FMODE_1 XSPI_CR_FMODE_1 |
| #define | OCTOSPI_CR_DQM XSPI_CR_DMM |
| #define | OCTOSPI_CR_FSEL XSPI_OCTOSPI_CR_MSEL |
| #define | OCTOSPI_DCR1_CKMODE_Pos XSPI_DCR1_CKMODE_Pos |
| #define | OCTOSPI_DCR1_CKMODE_Msk XSPI_DCR1_CKMODE_Msk |
| #define | OCTOSPI_DCR1_CKMODE XSPI_DCR1_CKMODE |
| #define | OCTOSPI_DCR1_FRCK_Pos XSPI_DCR1_FRCK_Pos |
| #define | OCTOSPI_DCR1_FRCK_Msk XSPI_DCR1_FRCK_Msk |
| #define | OCTOSPI_DCR1_FRCK XSPI_DCR1_FRCK |
| #define | OCTOSPI_DCR1_DLYBYP_Pos XSPI_OCTOSPI_DCR1_DLYBYP_Pos |
| #define | OCTOSPI_DCR1_DLYBYP_Msk XSPI_OCTOSPI_DCR1_DLYBYP_Msk |
| #define | OCTOSPI_DCR1_DLYBYP XSPI_OCTOSPI_DCR1_DLYBYP |
| #define | OCTOSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos |
| #define | OCTOSPI_DCR1_CSHT_Msk XSPI_DCR1_CSHT_Msk |
| #define | OCTOSPI_DCR1_CSHT XSPI_DCR1_CSHT |
| #define | OCTOSPI_DCR1_DEVSIZE_Pos XSPI_DCR1_DEVSIZE_Pos |
| #define | OCTOSPI_DCR1_DEVSIZE_Msk XSPI_DCR1_DEVSIZE_Msk |
| #define | OCTOSPI_DCR1_DEVSIZE XSPI_DCR1_DEVSIZE |
| #define | OCTOSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos |
| #define | OCTOSPI_DCR1_MTYP_Msk XSPI_DCR1_MTYP_Msk |
| #define | OCTOSPI_DCR1_MTYP XSPI_DCR1_MTYP |
| #define | OCTOSPI_DCR1_MTYP_0 XSPI_DCR1_MTYP_0 |
| #define | OCTOSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 |
| #define | OCTOSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 |
| #define | OCTOSPI_DCR2_PRESCALER_Pos XSPI_DCR2_PRESCALER_Pos |
| #define | OCTOSPI_DCR2_PRESCALER_Msk XSPI_DCR2_PRESCALER_Msk |
| #define | OCTOSPI_DCR2_PRESCALER XSPI_DCR2_PRESCALER |
| #define | OCTOSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos |
| #define | OCTOSPI_DCR2_WRAPSIZE_Msk XSPI_DCR2_WRAPSIZE_Msk |
| #define | OCTOSPI_DCR2_WRAPSIZE XSPI_DCR2_WRAPSIZE |
| #define | OCTOSPI_DCR2_WRAPSIZE_0 XSPI_DCR2_WRAPSIZE_0 |
| #define | OCTOSPI_DCR2_WRAPSIZE_1 XSPI_DCR2_WRAPSIZE_1 |
| #define | OCTOSPI_DCR2_WRAPSIZE_2 XSPI_DCR2_WRAPSIZE_2 |
| #define | OCTOSPI_DCR3_MAXTRAN_Pos XSPI_OCTOSPI_DCR3_MAXTRAN_Pos |
| #define | OCTOSPI_DCR3_MAXTRAN_Msk XSPI_OCTOSPI_DCR3_MAXTRAN_Msk |
| #define | OCTOSPI_DCR3_MAXTRAN XSPI_OCTOSPI_DCR3_MAXTRAN |
| #define | OCTOSPI_DCR3_CSBOUND_Pos XSPI_DCR3_CSBOUND_Pos |
| #define | OCTOSPI_DCR3_CSBOUND_Msk XSPI_DCR3_CSBOUND_Msk |
| #define | OCTOSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND |
| #define | OCTOSPI_DCR4_REFRESH_Pos XSPI_DCR4_REFRESH_Pos |
| #define | OCTOSPI_DCR4_REFRESH_Msk XSPI_DCR4_REFRESH_Msk |
| #define | OCTOSPI_DCR4_REFRESH XSPI_DCR4_REFRESH |
| #define | OCTOSPI_SR_TEF_Pos XSPI_SR_TEF_Pos |
| #define | OCTOSPI_SR_TEF_Msk XSPI_SR_TEF_Msk |
| #define | OCTOSPI_SR_TEF XSPI_SR_TEF |
| #define | OCTOSPI_SR_TCF_Pos XSPI_SR_TCF_Pos |
| #define | OCTOSPI_SR_TCF_Msk XSPI_SR_TCF_Msk |
| #define | OCTOSPI_SR_TCF XSPI_SR_TCF |
| #define | OCTOSPI_SR_FTF_Pos XSPI_SR_FTF_Pos |
| #define | OCTOSPI_SR_FTF_Msk XSPI_SR_FTF_Msk |
| #define | OCTOSPI_SR_FTF XSPI_SR_FTF |
| #define | OCTOSPI_SR_SMF_Pos XSPI_SR_SMF_Pos |
| #define | OCTOSPI_SR_SMF_Msk XSPI_SR_SMF_Msk |
| #define | OCTOSPI_SR_SMF XSPI_SR_SMF |
| #define | OCTOSPI_SR_TOF_Pos XSPI_SR_TOF_Pos |
| #define | OCTOSPI_SR_TOF_Msk XSPI_SR_TOF_Msk |
| #define | OCTOSPI_SR_TOF XSPI_SR_TOF |
| #define | OCTOSPI_SR_BUSY_Pos XSPI_SR_BUSY_Pos |
| #define | OCTOSPI_SR_BUSY_Msk XSPI_SR_BUSY_Msk |
| #define | OCTOSPI_SR_BUSY XSPI_SR_BUSY |
| #define | OCTOSPI_SR_FLEVEL_Pos XSPI_SR_FLEVEL_Pos |
| #define | OCTOSPI_SR_FLEVEL_Msk (0x3FUL << OCTOSPI_SR_FLEVEL_Pos) |
| #define | OCTOSPI_SR_FLEVEL XSPI_SR_FLEVEL |
| #define | OCTOSPI_FCR_CTEF_Pos XSPI_FCR_CTEF_Pos |
| #define | OCTOSPI_FCR_CTEF_Msk XSPI_FCR_CTEF_Msk |
| #define | OCTOSPI_FCR_CTEF XSPI_FCR_CTEF |
| #define | OCTOSPI_FCR_CTCF_Pos XSPI_FCR_CTCF_Pos |
| #define | OCTOSPI_FCR_CTCF_Msk XSPI_FCR_CTCF_Msk |
| #define | OCTOSPI_FCR_CTCF XSPI_FCR_CTCF |
| #define | OCTOSPI_FCR_CSMF_Pos XSPI_FCR_CSMF_Pos |
| #define | OCTOSPI_FCR_CSMF_Msk XSPI_FCR_CSMF_Msk |
| #define | OCTOSPI_FCR_CSMF XSPI_FCR_CSMF |
| #define | OCTOSPI_FCR_CTOF_Pos XSPI_FCR_CTOF_Pos |
| #define | OCTOSPI_FCR_CTOF_Msk XSPI_FCR_CTOF_Msk |
| #define | OCTOSPI_FCR_CTOF XSPI_FCR_CTOF |
| #define | OCTOSPI_DLR_DL_Pos XSPI_DLR_DL_Pos |
| #define | OCTOSPI_DLR_DL_Msk XSPI_DLR_DL_Msk |
| #define | OCTOSPI_DLR_DL XSPI_DLR_DL |
| #define | OCTOSPI_AR_ADDRESS_Pos XSPI_AR_ADDRESS_Pos |
| #define | OCTOSPI_AR_ADDRESS_Msk XSPI_AR_ADDRESS_Msk |
| #define | OCTOSPI_AR_ADDRESS XSPI_AR_ADDRESS |
| #define | OCTOSPI_DR_DATA_Pos XSPI_DR_DATA_Pos |
| #define | OCTOSPI_DR_DATA_Msk XSPI_DR_DATA_Msk |
| #define | OCTOSPI_DR_DATA XSPI_DR_DATA |
| #define | OCTOSPI_PSMKR_MASK_Pos XSPI_PSMKR_MASK_Pos |
| #define | OCTOSPI_PSMKR_MASK_Msk XSPI_PSMKR_MASK_Msk |
| #define | OCTOSPI_PSMKR_MASK XSPI_PSMKR_MASK |
| #define | OCTOSPI_PSMAR_MATCH_Pos XSPI_PSMAR_MATCH_Pos |
| #define | OCTOSPI_PSMAR_MATCH_Msk XSPI_PSMAR_MATCH_Msk |
| #define | OCTOSPI_PSMAR_MATCH XSPI_PSMAR_MATCH |
| #define | OCTOSPI_PIR_INTERVAL_Pos XSPI_PIR_INTERVAL_Pos |
| #define | OCTOSPI_PIR_INTERVAL_Msk XSPI_PIR_INTERVAL_Msk |
| #define | OCTOSPI_PIR_INTERVAL XSPI_PIR_INTERVAL |
| #define | OCTOSPI_CCR_IMODE_Pos XSPI_CCR_IMODE_Pos |
| #define | OCTOSPI_CCR_IMODE_Msk XSPI_CCR_IMODE_Msk |
| #define | OCTOSPI_CCR_IMODE XSPI_CCR_IMODE |
| #define | OCTOSPI_CCR_IMODE_0 XSPI_CCR_IMODE_0 |
| #define | OCTOSPI_CCR_IMODE_1 XSPI_CCR_IMODE_1 |
| #define | OCTOSPI_CCR_IMODE_2 XSPI_CCR_IMODE_2 |
| #define | OCTOSPI_CCR_IDTR_Pos XSPI_CCR_IDTR_Pos |
| #define | OCTOSPI_CCR_IDTR_Msk XSPI_CCR_IDTR_Msk |
| #define | OCTOSPI_CCR_IDTR XSPI_CCR_IDTR |
| #define | OCTOSPI_CCR_ISIZE_Pos XSPI_CCR_ISIZE_Pos |
| #define | OCTOSPI_CCR_ISIZE_Msk XSPI_CCR_ISIZE_Msk |
| #define | OCTOSPI_CCR_ISIZE XSPI_CCR_ISIZE |
| #define | OCTOSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 |
| #define | OCTOSPI_CCR_ISIZE_1 XSPI_CCR_ISIZE_1 |
| #define | OCTOSPI_CCR_ADMODE_Pos XSPI_CCR_ADMODE_Pos |
| #define | OCTOSPI_CCR_ADMODE_Msk XSPI_CCR_ADMODE_Msk |
| #define | OCTOSPI_CCR_ADMODE XSPI_CCR_ADMODE |
| #define | OCTOSPI_CCR_ADMODE_0 XSPI_CCR_ADMODE_0 |
| #define | OCTOSPI_CCR_ADMODE_1 XSPI_CCR_ADMODE_1 |
| #define | OCTOSPI_CCR_ADMODE_2 XSPI_CCR_ADMODE_2 |
| #define | OCTOSPI_CCR_ADDTR_Pos XSPI_CCR_ADDTR_Pos |
| #define | OCTOSPI_CCR_ADDTR_Msk XSPI_CCR_ADDTR_Msk |
| #define | OCTOSPI_CCR_ADDTR XSPI_CCR_ADDTR |
| #define | OCTOSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos |
| #define | OCTOSPI_CCR_ADSIZE_Msk XSPI_CCR_ADSIZE_Msk |
| #define | OCTOSPI_CCR_ADSIZE XSPI_CCR_ADSIZE |
| #define | OCTOSPI_CCR_ADSIZE_0 XSPI_CCR_ADSIZE_0 |
| #define | OCTOSPI_CCR_ADSIZE_1 XSPI_CCR_ADSIZE_1 |
| #define | OCTOSPI_CCR_ABMODE_Pos XSPI_CCR_ABMODE_Pos |
| #define | OCTOSPI_CCR_ABMODE_Msk XSPI_CCR_ABMODE_Msk |
| #define | OCTOSPI_CCR_ABMODE XSPI_CCR_ABMODE |
| #define | OCTOSPI_CCR_ABMODE_0 XSPI_CCR_ABMODE_0 |
| #define | OCTOSPI_CCR_ABMODE_1 XSPI_CCR_ABMODE_1 |
| #define | OCTOSPI_CCR_ABMODE_2 XSPI_CCR_ABMODE_2 |
| #define | OCTOSPI_CCR_ABDTR_Pos XSPI_CCR_ABDTR_Pos |
| #define | OCTOSPI_CCR_ABDTR_Msk XSPI_CCR_ABDTR_Msk |
| #define | OCTOSPI_CCR_ABDTR XSPI_CCR_ABDTR |
| #define | OCTOSPI_CCR_ABSIZE_Pos XSPI_CCR_ABSIZE_Pos |
| #define | OCTOSPI_CCR_ABSIZE_Msk XSPI_CCR_ABSIZE_Msk |
| #define | OCTOSPI_CCR_ABSIZE XSPI_CCR_ABSIZE |
| #define | OCTOSPI_CCR_ABSIZE_0 XSPI_CCR_ABSIZE_0 |
| #define | OCTOSPI_CCR_ABSIZE_1 XSPI_CCR_ABSIZE_1 |
| #define | OCTOSPI_CCR_DMODE_Pos XSPI_CCR_DMODE_Pos |
| #define | OCTOSPI_CCR_DMODE_Msk XSPI_CCR_DMODE_Msk |
| #define | OCTOSPI_CCR_DMODE XSPI_CCR_DMODE |
| #define | OCTOSPI_CCR_DMODE_0 XSPI_CCR_DMODE_0 |
| #define | OCTOSPI_CCR_DMODE_1 XSPI_CCR_DMODE_1 |
| #define | OCTOSPI_CCR_DMODE_2 XSPI_CCR_DMODE_2 |
| #define | OCTOSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos |
| #define | OCTOSPI_CCR_DDTR_Msk XSPI_CCR_DDTR_Msk |
| #define | OCTOSPI_CCR_DDTR XSPI_CCR_DDTR |
| #define | OCTOSPI_CCR_DQSE_Pos XSPI_CCR_DQSE_Pos |
| #define | OCTOSPI_CCR_DQSE_Msk XSPI_CCR_DQSE_Msk |
| #define | OCTOSPI_CCR_DQSE XSPI_CCR_DQSE |
| #define | OCTOSPI_CCR_SIOO_Pos XSPI_CCR_SIOO_Pos |
| #define | OCTOSPI_CCR_SIOO_Msk XSPI_CCR_SIOO_Msk |
| #define | OCTOSPI_CCR_SIOO XSPI_CCR_SIOO |
| #define | OCTOSPI_TCR_DCYC_Pos XSPI_TCR_DCYC_Pos |
| #define | OCTOSPI_TCR_DCYC_Msk XSPI_TCR_DCYC_Msk |
| #define | OCTOSPI_TCR_DCYC XSPI_TCR_DCYC |
| #define | OCTOSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos |
| #define | OCTOSPI_TCR_DHQC_Msk XSPI_TCR_DHQC_Msk |
| #define | OCTOSPI_TCR_DHQC XSPI_TCR_DHQC |
| #define | OCTOSPI_TCR_SSHIFT_Pos XSPI_TCR_SSHIFT_Pos |
| #define | OCTOSPI_TCR_SSHIFT_Msk XSPI_TCR_SSHIFT_Msk |
| #define | OCTOSPI_TCR_SSHIFT XSPI_TCR_SSHIFT |
| #define | OCTOSPI_IR_INSTRUCTION_Pos XSPI_IR_INSTRUCTION_Pos |
| #define | OCTOSPI_IR_INSTRUCTION_Msk XSPI_IR_INSTRUCTION_Msk |
| #define | OCTOSPI_IR_INSTRUCTION XSPI_IR_INSTRUCTION |
| #define | OCTOSPI_ABR_ALTERNATE_Pos XSPI_ABR_ALTERNATE_Pos |
| #define | OCTOSPI_ABR_ALTERNATE_Msk XSPI_ABR_ALTERNATE_Msk |
| #define | OCTOSPI_ABR_ALTERNATE XSPI_ABR_ALTERNATE |
| #define | OCTOSPI_LPTR_TIMEOUT_Pos XSPI_LPTR_TIMEOUT_Pos |
| #define | OCTOSPI_LPTR_TIMEOUT_Msk XSPI_LPTR_TIMEOUT_Msk |
| #define | OCTOSPI_LPTR_TIMEOUT XSPI_LPTR_TIMEOUT |
| #define | OCTOSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos |
| #define | OCTOSPI_WPCCR_IMODE_Msk XSPI_WPCCR_IMODE_Msk |
| #define | OCTOSPI_WPCCR_IMODE XSPI_WPCCR_IMODE |
| #define | OCTOSPI_WPCCR_IMODE_0 XSPI_WPCCR_IMODE_0 |
| #define | OCTOSPI_WPCCR_IMODE_1 XSPI_WPCCR_IMODE_1 |
| #define | OCTOSPI_WPCCR_IMODE_2 XSPI_WPCCR_IMODE_2 |
| #define | OCTOSPI_WPCCR_IDTR_Pos XSPI_WPCCR_IDTR_Pos |
| #define | OCTOSPI_WPCCR_IDTR_Msk XSPI_WPCCR_IDTR_Msk |
| #define | OCTOSPI_WPCCR_IDTR XSPI_WPCCR_IDTR |
| #define | OCTOSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos |
| #define | OCTOSPI_WPCCR_ISIZE_Msk XSPI_WPCCR_ISIZE_Msk |
| #define | OCTOSPI_WPCCR_ISIZE XSPI_WPCCR_ISIZE |
| #define | OCTOSPI_WPCCR_ISIZE_0 XSPI_WPCCR_ISIZE_0 |
| #define | OCTOSPI_WPCCR_ISIZE_1 XSPI_WPCCR_ISIZE_1 |
| #define | OCTOSPI_WPCCR_ADMODE_Pos XSPI_WPCCR_ADMODE_Pos |
| #define | OCTOSPI_WPCCR_ADMODE_Msk XSPI_WPCCR_ADMODE_Msk |
| #define | OCTOSPI_WPCCR_ADMODE XSPI_WPCCR_ADMODE |
| #define | OCTOSPI_WPCCR_ADMODE_0 XSPI_WPCCR_ADMODE_0 |
| #define | OCTOSPI_WPCCR_ADMODE_1 XSPI_WPCCR_ADMODE_1 |
| #define | OCTOSPI_WPCCR_ADMODE_2 XSPI_WPCCR_ADMODE_2 |
| #define | OCTOSPI_WPCCR_ADDTR_Pos XSPI_WPCCR_ADDTR_Pos |
| #define | OCTOSPI_WPCCR_ADDTR_Msk XSPI_WPCCR_ADDTR_Msk |
| #define | OCTOSPI_WPCCR_ADDTR XSPI_WPCCR_ADDTR |
| #define | OCTOSPI_WPCCR_ADSIZE_Pos XSPI_WPCCR_ADSIZE_Pos |
| #define | OCTOSPI_WPCCR_ADSIZE_Msk XSPI_WPCCR_ADSIZE_Msk |
| #define | OCTOSPI_WPCCR_ADSIZE XSPI_WPCCR_ADSIZE |
| #define | OCTOSPI_WPCCR_ADSIZE_0 XSPI_WPCCR_ADSIZE_0 |
| #define | OCTOSPI_WPCCR_ADSIZE_1 XSPI_WPCCR_ADSIZE_1 |
| #define | OCTOSPI_WPCCR_ABMODE_Pos XSPI_WPCCR_ABMODE_Pos |
| #define | OCTOSPI_WPCCR_ABMODE_Msk XSPI_WPCCR_ABMODE_Msk |
| #define | OCTOSPI_WPCCR_ABMODE XSPI_WPCCR_ABMODE |
| #define | OCTOSPI_WPCCR_ABMODE_0 XSPI_WPCCR_ABMODE_0 |
| #define | OCTOSPI_WPCCR_ABMODE_1 XSPI_WPCCR_ABMODE_1 |
| #define | OCTOSPI_WPCCR_ABMODE_2 XSPI_WPCCR_ABMODE_2 |
| #define | OCTOSPI_WPCCR_ABDTR_Pos XSPI_WPCCR_ABDTR_Pos |
| #define | OCTOSPI_WPCCR_ABDTR_Msk XSPI_WPCCR_ABDTR_Msk |
| #define | OCTOSPI_WPCCR_ABDTR XSPI_WPCCR_ABDTR |
| #define | OCTOSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos |
| #define | OCTOSPI_WPCCR_ABSIZE_Msk XSPI_WPCCR_ABSIZE_Msk |
| #define | OCTOSPI_WPCCR_ABSIZE XSPI_WPCCR_ABSIZE |
| #define | OCTOSPI_WPCCR_ABSIZE_0 XSPI_WPCCR_ABSIZE_0 |
| #define | OCTOSPI_WPCCR_ABSIZE_1 XSPI_WPCCR_ABSIZE_1 |
| #define | OCTOSPI_WPCCR_DMODE_Pos XSPI_WPCCR_DMODE_Pos |
| #define | OCTOSPI_WPCCR_DMODE_Msk XSPI_WPCCR_DMODE_Msk |
| #define | OCTOSPI_WPCCR_DMODE XSPI_WPCCR_DMODE |
| #define | OCTOSPI_WPCCR_DMODE_0 XSPI_WPCCR_DMODE_0 |
| #define | OCTOSPI_WPCCR_DMODE_1 XSPI_WPCCR_DMODE_1 |
| #define | OCTOSPI_WPCCR_DMODE_2 XSPI_WPCCR_DMODE_2 |
| #define | OCTOSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos |
| #define | OCTOSPI_WPCCR_DDTR_Msk XSPI_WPCCR_DDTR_Msk |
| #define | OCTOSPI_WPCCR_DDTR XSPI_WPCCR_DDTR |
| #define | OCTOSPI_WPCCR_DQSE_Pos XSPI_WPCCR_DQSE_Pos |
| #define | OCTOSPI_WPCCR_DQSE_Msk XSPI_WPCCR_DQSE_Msk |
| #define | OCTOSPI_WPCCR_DQSE XSPI_WPCCR_DQSE |
| #define | OCTOSPI_WPTCR_DCYC_Pos XSPI_WPTCR_DCYC_Pos |
| #define | OCTOSPI_WPTCR_DCYC_Msk XSPI_WPTCR_DCYC_Msk |
| #define | OCTOSPI_WPTCR_DCYC XSPI_WPTCR_DCYC |
| #define | OCTOSPI_WPTCR_DHQC_Pos XSPI_WPTCR_DHQC_Pos |
| #define | OCTOSPI_WPTCR_DHQC_Msk XSPI_WPTCR_DHQC_Msk |
| #define | OCTOSPI_WPTCR_DHQC XSPI_WPTCR_DHQC |
| #define | OCTOSPI_WPTCR_SSHIFT_Pos XSPI_WPTCR_SSHIFT_Pos |
| #define | OCTOSPI_WPTCR_SSHIFT_Msk XSPI_WPTCR_SSHIFT_Msk |
| #define | OCTOSPI_WPTCR_SSHIFT XSPI_WPTCR_SSHIFT |
| #define | OCTOSPI_WPIR_INSTRUCTION_Pos XSPI_WPIR_INSTRUCTION_Pos |
| #define | OCTOSPI_WPIR_INSTRUCTION_Msk XSPI_WPIR_INSTRUCTION_Msk |
| #define | OCTOSPI_WPIR_INSTRUCTION XSPI_WPIR_INSTRUCTION |
| #define | OCTOSPI_WPABR_ALTERNATE_Pos XSPI_WPABR_ALTERNATE_Pos |
| #define | OCTOSPI_WPABR_ALTERNATE_Msk XSPI_WPABR_ALTERNATE_Msk |
| #define | OCTOSPI_WPABR_ALTERNATE XSPI_WPABR_ALTERNATE |
| #define | OCTOSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos |
| #define | OCTOSPI_WCCR_IMODE_Msk XSPI_WCCR_IMODE_Msk |
| #define | OCTOSPI_WCCR_IMODE XSPI_WCCR_IMODE |
| #define | OCTOSPI_WCCR_IMODE_0 XSPI_WCCR_IMODE_0 |
| #define | OCTOSPI_WCCR_IMODE_1 XSPI_WCCR_IMODE_1 |
| #define | OCTOSPI_WCCR_IMODE_2 XSPI_WCCR_IMODE_2 |
| #define | OCTOSPI_WCCR_IDTR_Pos XSPI_WCCR_IDTR_Pos |
| #define | OCTOSPI_WCCR_IDTR_Msk XSPI_WCCR_IDTR_Msk |
| #define | OCTOSPI_WCCR_IDTR XSPI_WCCR_IDTR |
| #define | OCTOSPI_WCCR_ISIZE_Pos XSPI_WCCR_ISIZE_Pos |
| #define | OCTOSPI_WCCR_ISIZE_Msk XSPI_WCCR_ISIZE_Msk |
| #define | OCTOSPI_WCCR_ISIZE XSPI_WCCR_ISIZE |
| #define | OCTOSPI_WCCR_ISIZE_0 XSPI_WCCR_ISIZE_0 |
| #define | OCTOSPI_WCCR_ISIZE_1 XSPI_WCCR_ISIZE_1 |
| #define | OCTOSPI_WCCR_ADMODE_Pos XSPI_WCCR_ADMODE_Pos |
| #define | OCTOSPI_WCCR_ADMODE_Msk XSPI_WCCR_ADMODE_Msk |
| #define | OCTOSPI_WCCR_ADMODE XSPI_WCCR_ADMODE |
| #define | OCTOSPI_WCCR_ADMODE_0 XSPI_WCCR_ADMODE_0 |
| #define | OCTOSPI_WCCR_ADMODE_1 XSPI_WCCR_ADMODE_1 |
| #define | OCTOSPI_WCCR_ADMODE_2 XSPI_WCCR_ADMODE_2 |
| #define | OCTOSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos |
| #define | OCTOSPI_WCCR_ADDTR_Msk XSPI_WCCR_ADDTR_Msk |
| #define | OCTOSPI_WCCR_ADDTR XSPI_WCCR_ADDTR |
| #define | OCTOSPI_WCCR_ADSIZE_Pos XSPI_WCCR_ADSIZE_Pos |
| #define | OCTOSPI_WCCR_ADSIZE_Msk XSPI_WCCR_ADSIZE_Msk |
| #define | OCTOSPI_WCCR_ADSIZE XSPI_WCCR_ADSIZE |
| #define | OCTOSPI_WCCR_ADSIZE_0 XSPI_WCCR_ADSIZE_0 |
| #define | OCTOSPI_WCCR_ADSIZE_1 XSPI_WCCR_ADSIZE_1 |
| #define | OCTOSPI_WCCR_ABMODE_Pos XSPI_WCCR_ABMODE_Pos |
| #define | OCTOSPI_WCCR_ABMODE_Msk XSPI_WCCR_ABMODE_Msk |
| #define | OCTOSPI_WCCR_ABMODE XSPI_WCCR_ABMODE |
| #define | OCTOSPI_WCCR_ABMODE_0 XSPI_WCCR_ABMODE_0 |
| #define | OCTOSPI_WCCR_ABMODE_1 XSPI_WCCR_ABMODE_1 |
| #define | OCTOSPI_WCCR_ABMODE_2 XSPI_WCCR_ABMODE_2 |
| #define | OCTOSPI_WCCR_ABDTR_Pos XSPI_WCCR_ABDTR_Pos |
| #define | OCTOSPI_WCCR_ABDTR_Msk XSPI_WCCR_ABDTR_Msk |
| #define | OCTOSPI_WCCR_ABDTR XSPI_WCCR_ABDTR |
| #define | OCTOSPI_WCCR_ABSIZE_Pos XSPI_WCCR_ABSIZE_Pos |
| #define | OCTOSPI_WCCR_ABSIZE_Msk XSPI_WCCR_ABSIZE_Msk |
| #define | OCTOSPI_WCCR_ABSIZE XSPI_WCCR_ABSIZE |
| #define | OCTOSPI_WCCR_ABSIZE_0 XSPI_WCCR_ABSIZE_0 |
| #define | OCTOSPI_WCCR_ABSIZE_1 XSPI_WCCR_ABSIZE_1 |
| #define | OCTOSPI_WCCR_DMODE_Pos XSPI_WCCR_DMODE_Pos |
| #define | OCTOSPI_WCCR_DMODE_Msk XSPI_WCCR_DMODE_Msk |
| #define | OCTOSPI_WCCR_DMODE XSPI_WCCR_DMODE |
| #define | OCTOSPI_WCCR_DMODE_0 XSPI_WCCR_DMODE_0 |
| #define | OCTOSPI_WCCR_DMODE_1 XSPI_WCCR_DMODE_1 |
| #define | OCTOSPI_WCCR_DMODE_2 XSPI_WCCR_DMODE_2 |
| #define | OCTOSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos |
| #define | OCTOSPI_WCCR_DDTR_Msk XSPI_WCCR_DDTR_Msk |
| #define | OCTOSPI_WCCR_DDTR XSPI_WCCR_DDTR |
| #define | OCTOSPI_WCCR_DQSE_Pos XSPI_WCCR_DQSE_Pos |
| #define | OCTOSPI_WCCR_DQSE_Msk XSPI_WCCR_DQSE_Msk |
| #define | OCTOSPI_WCCR_DQSE XSPI_WCCR_DQSE |
| #define | OCTOSPI_WTCR_DCYC_Pos XSPI_WTCR_DCYC_Pos |
| #define | OCTOSPI_WTCR_DCYC_Msk XSPI_WTCR_DCYC_Msk |
| #define | OCTOSPI_WTCR_DCYC XSPI_WTCR_DCYC |
| #define | OCTOSPI_WIR_INSTRUCTION_Pos XSPI_WIR_INSTRUCTION_Pos |
| #define | OCTOSPI_WIR_INSTRUCTION_Msk XSPI_WIR_INSTRUCTION_Msk |
| #define | OCTOSPI_WIR_INSTRUCTION XSPI_WIR_INSTRUCTION |
| #define | OCTOSPI_WABR_ALTERNATE_Pos XSPI_WABR_ALTERNATE_Pos |
| #define | OCTOSPI_WABR_ALTERNATE_Msk XSPI_WABR_ALTERNATE_Msk |
| #define | OCTOSPI_WABR_ALTERNATE XSPI_WABR_ALTERNATE |
| #define | OCTOSPI_HLCR_LM_Pos XSPI_HLCR_LM_Pos |
| #define | OCTOSPI_HLCR_LM_Msk XSPI_HLCR_LM_Msk |
| #define | OCTOSPI_HLCR_LM XSPI_HLCR_LM |
| #define | OCTOSPI_HLCR_WZL_Pos XSPI_HLCR_WZL_Pos |
| #define | OCTOSPI_HLCR_WZL_Msk XSPI_HLCR_WZL_Msk |
| #define | OCTOSPI_HLCR_WZL XSPI_HLCR_WZL |
| #define | OCTOSPI_HLCR_TACC_Pos XSPI_HLCR_TACC_Pos |
| #define | OCTOSPI_HLCR_TACC_Msk XSPI_HLCR_TACC_Msk |
| #define | OCTOSPI_HLCR_TACC XSPI_HLCR_TACC |
| #define | OCTOSPI_HLCR_TRWR_Pos XSPI_HLCR_TRWR_Pos |
| #define | OCTOSPI_HLCR_TRWR_Msk XSPI_HLCR_TRWR_Msk |
| #define | OCTOSPI_HLCR_TRWR XSPI_HLCR_TRWR |
| #define | HSPI_CR_EN_Pos XSPI_CR_EN_Pos |
| #define | HSPI_CR_EN_Msk XSPI_CR_EN_Msk |
| #define | HSPI_CR_EN XSPI_CR_EN |
| #define | HSPI_CR_ABORT_Pos XSPI_CR_ABORT_Pos |
| #define | HSPI_CR_ABORT_Msk XSPI_CR_ABORT_Msk |
| #define | HSPI_CR_ABORT XSPI_CR_ABORT |
| #define | HSPI_CR_DMAEN_Pos XSPI_CR_DMAEN_Pos |
| #define | HSPI_CR_DMAEN_Msk XSPI_CR_DMAEN_Msk |
| #define | HSPI_CR_DMAEN XSPI_CR_DMAEN |
| #define | HSPI_CR_TCEN_Pos XSPI_CR_TCEN_Pos |
| #define | HSPI_CR_TCEN_Msk XSPI_CR_TCEN_Msk |
| #define | HSPI_CR_TCEN XSPI_CR_TCEN |
| #define | HSPI_CR_DMM_Pos XSPI_CR_DMM_Pos |
| #define | HSPI_CR_DMM_Msk XSPI_CR_DMM_Msk |
| #define | HSPI_CR_DMM XSPI_CR_DMM |
| #define | HSPI_CR_FTHRES_Pos XSPI_CR_FTHRES_Pos |
| #define | HSPI_CR_FTHRES_Msk XSPI_CR_FTHRES_Msk |
| #define | HSPI_CR_FTHRES XSPI_CR_FTHRES |
| #define | HSPI_CR_TEIE_Pos XSPI_CR_TEIE_Pos |
| #define | HSPI_CR_TEIE_Msk XSPI_CR_TEIE_Msk |
| #define | HSPI_CR_TEIE XSPI_CR_TEIE |
| #define | HSPI_CR_TCIE_Pos XSPI_CR_TCIE_Pos |
| #define | HSPI_CR_TCIE_Msk XSPI_CR_TCIE_Msk |
| #define | HSPI_CR_TCIE XSPI_CR_TCIE |
| #define | HSPI_CR_FTIE_Pos XSPI_CR_FTIE_Pos |
| #define | HSPI_CR_FTIE_Msk XSPI_CR_FTIE_Msk |
| #define | HSPI_CR_FTIE XSPI_CR_FTIE |
| #define | HSPI_CR_SMIE_Pos XSPI_CR_SMIE_Pos |
| #define | HSPI_CR_SMIE_Msk XSPI_CR_SMIE_Msk |
| #define | HSPI_CR_SMIE XSPI_CR_SMIE |
| #define | HSPI_CR_TOIE_Pos XSPI_CR_TOIE_Pos |
| #define | HSPI_CR_TOIE_Msk XSPI_CR_TOIE_Msk |
| #define | HSPI_CR_TOIE XSPI_CR_TOIE |
| #define | HSPI_CR_APMS_Pos XSPI_CR_APMS_Pos |
| #define | HSPI_CR_APMS_Msk XSPI_CR_APMS_Msk |
| #define | HSPI_CR_APMS XSPI_CR_APMS |
| #define | HSPI_CR_PMM_Pos XSPI_CR_PMM_Pos |
| #define | HSPI_CR_PMM_Msk XSPI_CR_PMM_Msk |
| #define | HSPI_CR_PMM XSPI_CR_PMM |
| #define | HSPI_CR_FMODE_Pos XSPI_CR_FMODE_Pos |
| #define | HSPI_CR_FMODE_Msk XSPI_CR_FMODE_Msk |
| #define | HSPI_CR_FMODE XSPI_CR_FMODE |
| #define | HSPI_CR_FMODE_0 XSPI_CR_FMODE_0 |
| #define | HSPI_CR_FMODE_1 XSPI_CR_FMODE_1 |
| #define | HSPI_CR_MSEL_Pos XSPI_HSPI_CR_MSEL_Pos |
| #define | HSPI_CR_MSEL_Msk XSPI_HSPI_CR_MSEL_Msk |
| #define | HSPI_CR_MSEL XSPI_HSPI_CR_MSEL |
| #define | HSPI_CR_MSEL_0 XSPI_HSPI_CR_MSEL_0 |
| #define | HSPI_CR_MSEL_1 XSPI_HSPI_CR_MSEL_1 |
| #define | HSPI_DCR1_CKMODE_Pos XSPI_DCR1_CKMODE_Pos |
| #define | HSPI_DCR1_CKMODE_Msk XSPI_DCR1_CKMODE_Msk |
| #define | HSPI_DCR1_CKMODE XSPI_DCR1_CKMODE |
| #define | HSPI_DCR1_FRCK_Pos XSPI_DCR1_FRCK_Pos |
| #define | HSPI_DCR1_FRCK_Msk XSPI_DCR1_FRCK_Msk |
| #define | HSPI_DCR1_FRCK XSPI_DCR1_FRCK |
| #define | HSPI_DCR1_CSHT_Pos XSPI_DCR1_CSHT_Pos |
| #define | HSPI_DCR1_CSHT_Msk XSPI_DCR1_CSHT_Msk |
| #define | HSPI_DCR1_CSHT XSPI_DCR1_CSHT |
| #define | HSPI_DCR1_DEVSIZE_Pos XSPI_DCR1_DEVSIZE_Pos |
| #define | HSPI_DCR1_DEVSIZE_Msk XSPI_DCR1_DEVSIZE_Msk |
| #define | HSPI_DCR1_DEVSIZE XSPI_DCR1_DEVSIZE |
| #define | HSPI_DCR1_MTYP_Pos XSPI_DCR1_MTYP_Pos |
| #define | HSPI_DCR1_MTYP_Msk XSPI_DCR1_MTYP_Msk |
| #define | HSPI_DCR1_MTYP XSPI_DCR1_MTYP |
| #define | HSPI_DCR1_MTYP_0 XSPI_DCR1_MTYP_0 |
| #define | HSPI_DCR1_MTYP_1 XSPI_DCR1_MTYP_1 |
| #define | HSPI_DCR1_MTYP_2 XSPI_DCR1_MTYP_2 |
| #define | HSPI_DCR2_PRESCALER_Pos XSPI_DCR2_PRESCALER_Pos |
| #define | HSPI_DCR2_PRESCALER_Msk XSPI_DCR2_PRESCALER_Msk |
| #define | HSPI_DCR2_PRESCALER XSPI_DCR2_PRESCALER |
| #define | HSPI_DCR2_WRAPSIZE_Pos XSPI_DCR2_WRAPSIZE_Pos |
| #define | HSPI_DCR2_WRAPSIZE_Msk XSPI_DCR2_WRAPSIZE_Msk |
| #define | HSPI_DCR2_WRAPSIZE XSPI_DCR2_WRAPSIZE |
| #define | HSPI_DCR2_WRAPSIZE_0 XSPI_DCR2_WRAPSIZE_0 |
| #define | HSPI_DCR2_WRAPSIZE_1 XSPI_DCR2_WRAPSIZE_1 |
| #define | HSPI_DCR2_WRAPSIZE_2 XSPI_DCR2_WRAPSIZE_2 |
| #define | HSPI_DCR3_CSBOUND_Pos XSPI_DCR3_CSBOUND_Pos |
| #define | HSPI_DCR3_CSBOUND_Msk XSPI_DCR3_CSBOUND_Msk |
| #define | HSPI_DCR3_CSBOUND XSPI_DCR3_CSBOUND |
| #define | HSPI_DCR4_REFRESH_Pos XSPI_DCR4_REFRESH_Pos |
| #define | HSPI_DCR4_REFRESH_Msk XSPI_DCR4_REFRESH_Msk |
| #define | HSPI_DCR4_REFRESH XSPI_DCR4_REFRESH |
| #define | HSPI_SR_TEF_Pos XSPI_SR_TEF_Pos |
| #define | HSPI_SR_TEF_Msk XSPI_SR_TEF_Msk |
| #define | HSPI_SR_TEF XSPI_SR_TEF |
| #define | HSPI_SR_TCF_Pos XSPI_SR_TCF_Pos |
| #define | HSPI_SR_TCF_Msk XSPI_SR_TCF_Msk |
| #define | HSPI_SR_TCF XSPI_SR_TCF |
| #define | HSPI_SR_FTF_Pos XSPI_SR_FTF_Pos |
| #define | HSPI_SR_FTF_Msk XSPI_SR_FTF_Msk |
| #define | HSPI_SR_FTF XSPI_SR_FTF |
| #define | HSPI_SR_SMF_Pos XSPI_SR_SMF_Pos |
| #define | HSPI_SR_SMF_Msk XSPI_SR_SMF_Msk |
| #define | HSPI_SR_SMF XSPI_SR_SMF |
| #define | HSPI_SR_TOF_Pos XSPI_SR_TOF_Pos |
| #define | HSPI_SR_TOF_Msk XSPI_SR_TOF_Msk |
| #define | HSPI_SR_TOF XSPI_SR_TOF |
| #define | HSPI_SR_BUSY_Pos XSPI_SR_BUSY_Pos |
| #define | HSPI_SR_BUSY_Msk XSPI_SR_BUSY_Msk |
| #define | HSPI_SR_BUSY XSPI_SR_BUSY |
| #define | HSPI_SR_FLEVEL_Pos XSPI_SR_FLEVEL_Pos |
| #define | HSPI_SR_FLEVEL_Msk XSPI_SR_FLEVEL_Msk |
| #define | HSPI_SR_FLEVEL XSPI_SR_FLEVEL |
| #define | HSPI_FCR_CTEF_Pos XSPI_FCR_CTEF_Pos |
| #define | HSPI_FCR_CTEF_Msk XSPI_FCR_CTEF_Msk |
| #define | HSPI_FCR_CTEF XSPI_FCR_CTEF |
| #define | HSPI_FCR_CTCF_Pos XSPI_FCR_CTCF_Pos |
| #define | HSPI_FCR_CTCF_Msk XSPI_FCR_CTCF_Msk |
| #define | HSPI_FCR_CTCF XSPI_FCR_CTCF |
| #define | HSPI_FCR_CSMF_Pos XSPI_FCR_CSMF_Pos |
| #define | HSPI_FCR_CSMF_Msk XSPI_FCR_CSMF_Msk |
| #define | HSPI_FCR_CSMF XSPI_FCR_CSMF |
| #define | HSPI_FCR_CTOF_Pos XSPI_FCR_CTOF_Pos |
| #define | HSPI_FCR_CTOF_Msk XSPI_FCR_CTOF_Msk |
| #define | HSPI_FCR_CTOF XSPI_FCR_CTOF |
| #define | HSPI_DLR_DL_Pos XSPI_DLR_DL_Pos |
| #define | HSPI_DLR_DL_Msk XSPI_DLR_DL_Msk |
| #define | HSPI_DLR_DL XSPI_DLR_DL |
| #define | HSPI_AR_ADDRESS_Pos XSPI_AR_ADDRESS_Pos |
| #define | HSPI_AR_ADDRESS_Msk XSPI_AR_ADDRESS_Msk |
| #define | HSPI_AR_ADDRESS XSPI_AR_ADDRESS |
| #define | HSPI_DR_DATA_Pos XSPI_DR_DATA_Pos |
| #define | HSPI_DR_DATA_Msk XSPI_DR_DATA_Msk |
| #define | HSPI_DR_DATA XSPI_DR_DATA |
| #define | HSPI_PSMKR_MASK_Pos XSPI_PSMKR_MASK_Pos |
| #define | HSPI_PSMKR_MASK_Msk XSPI_PSMKR_MASK_Msk |
| #define | HSPI_PSMKR_MASK XSPI_PSMKR_MASK |
| #define | HSPI_PSMAR_MATCH_Pos XSPI_PSMAR_MATCH_Pos |
| #define | HSPI_PSMAR_MATCH_Msk XSPI_PSMAR_MATCH_Msk |
| #define | HSPI_PSMAR_MATCH XSPI_PSMAR_MATCH |
| #define | HSPI_PIR_INTERVAL_Pos XSPI_PIR_INTERVAL_Pos |
| #define | HSPI_PIR_INTERVAL_Msk XSPI_PIR_INTERVAL_Msk |
| #define | HSPI_PIR_INTERVAL XSPI_PIR_INTERVAL |
| #define | HSPI_CCR_IMODE_Pos XSPI_CCR_IMODE_Pos |
| #define | HSPI_CCR_IMODE_Msk XSPI_CCR_IMODE_Msk |
| #define | HSPI_CCR_IMODE XSPI_CCR_IMODE |
| #define | HSPI_CCR_IMODE_0 XSPI_CCR_IMODE_0 |
| #define | HSPI_CCR_IMODE_1 XSPI_CCR_IMODE_1 |
| #define | HSPI_CCR_IMODE_2 XSPI_CCR_IMODE_2 |
| #define | HSPI_CCR_IDTR_Pos XSPI_CCR_IDTR_Pos |
| #define | HSPI_CCR_IDTR_Msk XSPI_CCR_IDTR_Msk |
| #define | HSPI_CCR_IDTR XSPI_CCR_IDTR |
| #define | HSPI_CCR_ISIZE_Pos XSPI_CCR_ISIZE_Pos |
| #define | HSPI_CCR_ISIZE_Msk XSPI_CCR_ISIZE_Msk |
| #define | HSPI_CCR_ISIZE XSPI_CCR_ISIZE |
| #define | HSPI_CCR_ISIZE_0 XSPI_CCR_ISIZE_0 |
| #define | HSPI_CCR_ISIZE_1 XSPI_CCR_ISIZE_1 |
| #define | HSPI_CCR_ADMODE_Pos XSPI_CCR_ADMODE_Pos |
| #define | HSPI_CCR_ADMODE_Msk XSPI_CCR_ADMODE_Msk |
| #define | HSPI_CCR_ADMODE XSPI_CCR_ADMODE |
| #define | HSPI_CCR_ADMODE_0 XSPI_CCR_ADMODE_0 |
| #define | HSPI_CCR_ADMODE_1 XSPI_CCR_ADMODE_1 |
| #define | HSPI_CCR_ADMODE_2 XSPI_CCR_ADMODE_2 |
| #define | HSPI_CCR_ADDTR_Pos XSPI_CCR_ADDTR_Pos |
| #define | HSPI_CCR_ADDTR_Msk XSPI_CCR_ADDTR_Msk |
| #define | HSPI_CCR_ADDTR XSPI_CCR_ADDTR |
| #define | HSPI_CCR_ADSIZE_Pos XSPI_CCR_ADSIZE_Pos |
| #define | HSPI_CCR_ADSIZE_Msk XSPI_CCR_ADSIZE_Msk |
| #define | HSPI_CCR_ADSIZE XSPI_CCR_ADSIZE |
| #define | HSPI_CCR_ADSIZE_0 XSPI_CCR_ADSIZE_0 |
| #define | HSPI_CCR_ADSIZE_1 XSPI_CCR_ADSIZE_1 |
| #define | HSPI_CCR_ABMODE_Pos XSPI_CCR_ABMODE_Pos |
| #define | HSPI_CCR_ABMODE_Msk XSPI_CCR_ABMODE_Msk |
| #define | HSPI_CCR_ABMODE XSPI_CCR_ABMODE |
| #define | HSPI_CCR_ABMODE_0 XSPI_CCR_ABMODE_0 |
| #define | HSPI_CCR_ABMODE_1 XSPI_CCR_ABMODE_1 |
| #define | HSPI_CCR_ABMODE_2 XSPI_CCR_ABMODE_2 |
| #define | HSPI_CCR_ABDTR_Pos XSPI_CCR_ABDTR_Pos |
| #define | HSPI_CCR_ABDTR_Msk XSPI_CCR_ABDTR_Msk |
| #define | HSPI_CCR_ABDTR XSPI_CCR_ABDTR |
| #define | HSPI_CCR_ABSIZE_Pos XSPI_CCR_ABSIZE_Pos |
| #define | HSPI_CCR_ABSIZE_Msk XSPI_CCR_ABSIZE_Msk |
| #define | HSPI_CCR_ABSIZE XSPI_CCR_ABSIZE |
| #define | HSPI_CCR_ABSIZE_0 XSPI_CCR_ABSIZE_0 |
| #define | HSPI_CCR_ABSIZE_1 XSPI_CCR_ABSIZE_1 |
| #define | HSPI_CCR_DMODE_Pos XSPI_CCR_DMODE_Pos |
| #define | HSPI_CCR_DMODE_Msk XSPI_CCR_DMODE_Msk |
| #define | HSPI_CCR_DMODE XSPI_CCR_DMODE |
| #define | HSPI_CCR_DMODE_0 XSPI_CCR_DMODE_0 |
| #define | HSPI_CCR_DMODE_1 XSPI_CCR_DMODE_1 |
| #define | HSPI_CCR_DMODE_2 XSPI_CCR_DMODE_2 |
| #define | HSPI_CCR_DDTR_Pos XSPI_CCR_DDTR_Pos |
| #define | HSPI_CCR_DDTR_Msk XSPI_CCR_DDTR_Msk |
| #define | HSPI_CCR_DDTR XSPI_CCR_DDTR |
| #define | HSPI_CCR_DQSE_Pos XSPI_CCR_DQSE_Pos |
| #define | HSPI_CCR_DQSE_Msk XSPI_CCR_DQSE_Msk |
| #define | HSPI_CCR_DQSE XSPI_CCR_DQSE |
| #define | HSPI_CCR_SIOO_Pos XSPI_CCR_SIOO_Pos |
| #define | HSPI_CCR_SIOO_Msk XSPI_CCR_SIOO_Msk |
| #define | HSPI_CCR_SIOO XSPI_CCR_SIOO |
| #define | HSPI_TCR_DCYC_Pos XSPI_TCR_DCYC_Pos |
| #define | HSPI_TCR_DCYC_Msk XSPI_TCR_DCYC_Msk |
| #define | HSPI_TCR_DCYC XSPI_TCR_DCYC |
| #define | HSPI_TCR_DHQC_Pos XSPI_TCR_DHQC_Pos |
| #define | HSPI_TCR_DHQC_Msk XSPI_TCR_DHQC_Msk |
| #define | HSPI_TCR_DHQC XSPI_TCR_DHQC |
| #define | HSPI_TCR_SSHIFT_Pos XSPI_TCR_SSHIFT_Pos |
| #define | HSPI_TCR_SSHIFT_Msk XSPI_TCR_SSHIFT_Msk |
| #define | HSPI_TCR_SSHIFT XSPI_TCR_SSHIFT |
| #define | HSPI_IR_INSTRUCTION_Pos XSPI_IR_INSTRUCTION_Pos |
| #define | HSPI_IR_INSTRUCTION_Msk XSPI_IR_INSTRUCTION_Msk |
| #define | HSPI_IR_INSTRUCTION XSPI_IR_INSTRUCTION |
| #define | HSPI_ABR_ALTERNATE_Pos XSPI_ABR_ALTERNATE_Pos |
| #define | HSPI_ABR_ALTERNATE_Msk XSPI_ABR_ALTERNATE_Msk |
| #define | HSPI_ABR_ALTERNATE XSPI_ABR_ALTERNATE |
| #define | HSPI_LPTR_TIMEOUT_Pos XSPI_LPTR_TIMEOUT_Pos |
| #define | HSPI_LPTR_TIMEOUT_Msk XSPI_LPTR_TIMEOUT_Msk |
| #define | HSPI_LPTR_TIMEOUT XSPI_LPTR_TIMEOUT |
| #define | HSPI_WPCCR_IMODE_Pos XSPI_WPCCR_IMODE_Pos |
| #define | HSPI_WPCCR_IMODE_Msk XSPI_WPCCR_IMODE_Msk |
| #define | HSPI_WPCCR_IMODE XSPI_WPCCR_IMODE |
| #define | HSPI_WPCCR_IMODE_0 XSPI_WPCCR_IMODE_0 |
| #define | HSPI_WPCCR_IMODE_1 XSPI_WPCCR_IMODE_1 |
| #define | HSPI_WPCCR_IMODE_2 XSPI_WPCCR_IMODE_2 |
| #define | HSPI_WPCCR_IDTR_Pos XSPI_WPCCR_IDTR_Pos |
| #define | HSPI_WPCCR_IDTR_Msk XSPI_WPCCR_IDTR_Msk |
| #define | HSPI_WPCCR_IDTR XSPI_WPCCR_IDTR |
| #define | HSPI_WPCCR_ISIZE_Pos XSPI_WPCCR_ISIZE_Pos |
| #define | HSPI_WPCCR_ISIZE_Msk XSPI_WPCCR_ISIZE_Msk |
| #define | HSPI_WPCCR_ISIZE XSPI_WPCCR_ISIZE |
| #define | HSPI_WPCCR_ISIZE_0 XSPI_WPCCR_ISIZE_0 |
| #define | HSPI_WPCCR_ISIZE_1 XSPI_WPCCR_ISIZE_1 |
| #define | HSPI_WPCCR_ADMODE_Pos XSPI_WPCCR_ADMODE_Pos |
| #define | HSPI_WPCCR_ADMODE_Msk XSPI_WPCCR_ADMODE_Msk |
| #define | HSPI_WPCCR_ADMODE XSPI_WPCCR_ADMODE |
| #define | HSPI_WPCCR_ADMODE_0 XSPI_WPCCR_ADMODE_0 |
| #define | HSPI_WPCCR_ADMODE_1 XSPI_WPCCR_ADMODE_1 |
| #define | HSPI_WPCCR_ADMODE_2 XSPI_WPCCR_ADMODE_2 |
| #define | HSPI_WPCCR_ADDTR_Pos XSPI_WPCCR_ADDTR_Pos |
| #define | HSPI_WPCCR_ADDTR_Msk XSPI_WPCCR_ADDTR_Msk |
| #define | HSPI_WPCCR_ADDTR XSPI_WPCCR_ADDTR |
| #define | HSPI_WPCCR_ADSIZE_Pos XSPI_WPCCR_ADSIZE_Pos |
| #define | HSPI_WPCCR_ADSIZE_Msk XSPI_WPCCR_ADSIZE_Msk |
| #define | HSPI_WPCCR_ADSIZE XSPI_WPCCR_ADSIZE |
| #define | HSPI_WPCCR_ADSIZE_0 XSPI_WPCCR_ADSIZE_0 |
| #define | HSPI_WPCCR_ADSIZE_1 XSPI_WPCCR_ADSIZE_1 |
| #define | HSPI_WPCCR_ABMODE_Pos XSPI_WPCCR_ABMODE_Pos |
| #define | HSPI_WPCCR_ABMODE_Msk XSPI_WPCCR_ABMODE_Msk |
| #define | HSPI_WPCCR_ABMODE XSPI_WPCCR_ABMODE |
| #define | HSPI_WPCCR_ABMODE_0 XSPI_WPCCR_ABMODE_0 |
| #define | HSPI_WPCCR_ABMODE_1 XSPI_WPCCR_ABMODE_1 |
| #define | HSPI_WPCCR_ABMODE_2 XSPI_WPCCR_ABMODE_2 |
| #define | HSPI_WPCCR_ABDTR_Pos XSPI_WPCCR_ABDTR_Pos |
| #define | HSPI_WPCCR_ABDTR_Msk XSPI_WPCCR_ABDTR_Msk |
| #define | HSPI_WPCCR_ABDTR XSPI_WPCCR_ABDTR |
| #define | HSPI_WPCCR_ABSIZE_Pos XSPI_WPCCR_ABSIZE_Pos |
| #define | HSPI_WPCCR_ABSIZE_Msk XSPI_WPCCR_ABSIZE_Msk |
| #define | HSPI_WPCCR_ABSIZE XSPI_WPCCR_ABSIZE |
| #define | HSPI_WPCCR_ABSIZE_0 XSPI_WPCCR_ABSIZE_0 |
| #define | HSPI_WPCCR_ABSIZE_1 XSPI_WPCCR_ABSIZE_1 |
| #define | HSPI_WPCCR_DMODE_Pos XSPI_WPCCR_DMODE_Pos |
| #define | HSPI_WPCCR_DMODE_Msk XSPI_WPCCR_DMODE_Msk |
| #define | HSPI_WPCCR_DMODE XSPI_WPCCR_DMODE |
| #define | HSPI_WPCCR_DMODE_0 XSPI_WPCCR_DMODE_0 |
| #define | HSPI_WPCCR_DMODE_1 XSPI_WPCCR_DMODE_1 |
| #define | HSPI_WPCCR_DMODE_2 XSPI_WPCCR_DMODE_2 |
| #define | HSPI_WPCCR_DDTR_Pos XSPI_WPCCR_DDTR_Pos |
| #define | HSPI_WPCCR_DDTR_Msk XSPI_WPCCR_DDTR_Msk |
| #define | HSPI_WPCCR_DDTR XSPI_WPCCR_DDTR |
| #define | HSPI_WPCCR_DQSE_Pos XSPI_WPCCR_DQSE_Pos |
| #define | HSPI_WPCCR_DQSE_Msk XSPI_WPCCR_DQSE_Msk |
| #define | HSPI_WPCCR_DQSE XSPI_WPCCR_DQSE |
| #define | HSPI_WPTCR_DCYC_Pos XSPI_WPTCR_DCYC_Pos |
| #define | HSPI_WPTCR_DCYC_Msk XSPI_WPTCR_DCYC_Msk |
| #define | HSPI_WPTCR_DCYC XSPI_WPTCR_DCYC |
| #define | HSPI_WPTCR_DHQC_Pos XSPI_WPTCR_DHQC_Pos |
| #define | HSPI_WPTCR_DHQC_Msk XSPI_WPTCR_DHQC_Msk |
| #define | HSPI_WPTCR_DHQC XSPI_WPTCR_DHQC |
| #define | HSPI_WPTCR_SSHIFT_Pos XSPI_WPTCR_SSHIFT_Pos |
| #define | HSPI_WPTCR_SSHIFT_Msk XSPI_WPTCR_SSHIFT_Msk |
| #define | HSPI_WPTCR_SSHIFT XSPI_WPTCR_SSHIFT |
| #define | HSPI_WPIR_INSTRUCTION_Pos XSPI_WPIR_INSTRUCTION_Pos |
| #define | HSPI_WPIR_INSTRUCTION_Msk XSPI_WPIR_INSTRUCTION_Msk |
| #define | HSPI_WPIR_INSTRUCTION XSPI_WPIR_INSTRUCTION |
| #define | HSPI_WPABR_ALTERNATE_Pos XSPI_WPABR_ALTERNATE_Pos |
| #define | HSPI_WPABR_ALTERNATE_Msk XSPI_WPABR_ALTERNATE_Msk |
| #define | HSPI_WPABR_ALTERNATE XSPI_WPABR_ALTERNATE |
| #define | HSPI_WCCR_IMODE_Pos XSPI_WCCR_IMODE_Pos |
| #define | HSPI_WCCR_IMODE_Msk XSPI_WCCR_IMODE_Msk |
| #define | HSPI_WCCR_IMODE XSPI_WCCR_IMODE |
| #define | HSPI_WCCR_IMODE_0 XSPI_WCCR_IMODE_0 |
| #define | HSPI_WCCR_IMODE_1 XSPI_WCCR_IMODE_1 |
| #define | HSPI_WCCR_IMODE_2 XSPI_WCCR_IMODE_2 |
| #define | HSPI_WCCR_IDTR_Pos XSPI_WCCR_IDTR_Pos |
| #define | HSPI_WCCR_IDTR_Msk XSPI_WCCR_IDTR_Msk |
| #define | HSPI_WCCR_IDTR XSPI_WCCR_IDTR |
| #define | HSPI_WCCR_ISIZE_Pos XSPI_WCCR_ISIZE_Pos |
| #define | HSPI_WCCR_ISIZE_Msk XSPI_WCCR_ISIZE_Msk |
| #define | HSPI_WCCR_ISIZE XSPI_WCCR_ISIZE |
| #define | HSPI_WCCR_ISIZE_0 XSPI_WCCR_ISIZE_0 |
| #define | HSPI_WCCR_ISIZE_1 XSPI_WCCR_ISIZE_1 |
| #define | HSPI_WCCR_ADMODE_Pos XSPI_WCCR_ADMODE_Pos |
| #define | HSPI_WCCR_ADMODE_Msk XSPI_WCCR_ADMODE_Msk |
| #define | HSPI_WCCR_ADMODE XSPI_WCCR_ADMODE |
| #define | HSPI_WCCR_ADMODE_0 XSPI_WCCR_ADMODE_0 |
| #define | HSPI_WCCR_ADMODE_1 XSPI_WCCR_ADMODE_1 |
| #define | HSPI_WCCR_ADMODE_2 XSPI_WCCR_ADMODE_2 |
| #define | HSPI_WCCR_ADDTR_Pos XSPI_WCCR_ADDTR_Pos |
| #define | HSPI_WCCR_ADDTR_Msk XSPI_WCCR_ADDTR_Msk |
| #define | HSPI_WCCR_ADDTR XSPI_WCCR_ADDTR |
| #define | HSPI_WCCR_ADSIZE_Pos XSPI_WCCR_ADSIZE_Pos |
| #define | HSPI_WCCR_ADSIZE_Msk XSPI_WCCR_ADSIZE_Msk |
| #define | HSPI_WCCR_ADSIZE XSPI_WCCR_ADSIZE |
| #define | HSPI_WCCR_ADSIZE_0 XSPI_WCCR_ADSIZE_0 |
| #define | HSPI_WCCR_ADSIZE_1 XSPI_WCCR_ADSIZE_1 |
| #define | HSPI_WCCR_ABMODE_Pos XSPI_WCCR_ABMODE_Pos |
| #define | HSPI_WCCR_ABMODE_Msk XSPI_WCCR_ABMODE_Msk |
| #define | HSPI_WCCR_ABMODE XSPI_WCCR_ABMODE |
| #define | HSPI_WCCR_ABMODE_0 XSPI_WCCR_ABMODE_0 |
| #define | HSPI_WCCR_ABMODE_1 XSPI_WCCR_ABMODE_1 |
| #define | HSPI_WCCR_ABMODE_2 XSPI_WCCR_ABMODE_2 |
| #define | HSPI_WCCR_ABDTR_Pos XSPI_WCCR_ABDTR_Pos |
| #define | HSPI_WCCR_ABDTR_Msk XSPI_WCCR_ABDTR_Msk |
| #define | HSPI_WCCR_ABDTR XSPI_WCCR_ABDTR |
| #define | HSPI_WCCR_ABSIZE_Pos XSPI_WCCR_ABSIZE_Pos |
| #define | HSPI_WCCR_ABSIZE_Msk XSPI_WCCR_ABSIZE_Msk |
| #define | HSPI_WCCR_ABSIZE XSPI_WCCR_ABSIZE |
| #define | HSPI_WCCR_ABSIZE_0 XSPI_WCCR_ABSIZE_0 |
| #define | HSPI_WCCR_ABSIZE_1 XSPI_WCCR_ABSIZE_1 |
| #define | HSPI_WCCR_DMODE_Pos XSPI_WCCR_DMODE_Pos |
| #define | HSPI_WCCR_DMODE_Msk XSPI_WCCR_DMODE_Msk |
| #define | HSPI_WCCR_DMODE XSPI_WCCR_DMODE |
| #define | HSPI_WCCR_DMODE_0 XSPI_WCCR_DMODE_0 |
| #define | HSPI_WCCR_DMODE_1 XSPI_WCCR_DMODE_1 |
| #define | HSPI_WCCR_DMODE_2 XSPI_WCCR_DMODE_2 |
| #define | HSPI_WCCR_DDTR_Pos XSPI_WCCR_DDTR_Pos |
| #define | HSPI_WCCR_DDTR_Msk XSPI_WCCR_DDTR_Msk |
| #define | HSPI_WCCR_DDTR XSPI_WCCR_DDTR |
| #define | HSPI_WCCR_DQSE_Pos XSPI_WCCR_DQSE_Pos |
| #define | HSPI_WCCR_DQSE_Msk XSPI_WCCR_DQSE_Msk |
| #define | HSPI_WCCR_DQSE XSPI_WCCR_DQSE |
| #define | HSPI_WTCR_DCYC_Pos XSPI_WTCR_DCYC_Pos |
| #define | HSPI_WTCR_DCYC_Msk XSPI_WTCR_DCYC_Msk |
| #define | HSPI_WTCR_DCYC XSPI_WTCR_DCYC |
| #define | HSPI_WIR_INSTRUCTION_Pos XSPI_WIR_INSTRUCTION_Pos |
| #define | HSPI_WIR_INSTRUCTION_Msk XSPI_WIR_INSTRUCTION_Msk |
| #define | HSPI_WIR_INSTRUCTION XSPI_WIR_INSTRUCTION |
| #define | HSPI_WABR_ALTERNATE_Pos XSPI_WABR_ALTERNATE_Pos |
| #define | HSPI_WABR_ALTERNATE_Msk XSPI_WABR_ALTERNATE_Msk |
| #define | HSPI_WABR_ALTERNATE XSPI_WABR_ALTERNATE |
| #define | HSPI_HLCR_LM_Pos XSPI_HLCR_LM_Pos |
| #define | HSPI_HLCR_LM_Msk XSPI_HLCR_LM_Msk |
| #define | HSPI_HLCR_LM XSPI_HLCR_LM |
| #define | HSPI_HLCR_WZL_Pos XSPI_HLCR_WZL_Pos |
| #define | HSPI_HLCR_WZL_Msk XSPI_HLCR_WZL_Msk |
| #define | HSPI_HLCR_WZL XSPI_HLCR_WZL |
| #define | HSPI_HLCR_TACC_Pos XSPI_HLCR_TACC_Pos |
| #define | HSPI_HLCR_TACC_Msk XSPI_HLCR_TACC_Msk |
| #define | HSPI_HLCR_TACC XSPI_HLCR_TACC |
| #define | HSPI_HLCR_TRWR_Pos XSPI_HLCR_TRWR_Pos |
| #define | HSPI_HLCR_TRWR_Msk XSPI_HLCR_TRWR_Msk |
| #define | HSPI_HLCR_TRWR XSPI_HLCR_TRWR |
| #define | HSPI_CALFCR_FINE_Pos XSPI_HSPI_CALFCR_FINE_Pos |
| #define | HSPI_CALFCR_FINE_Msk XSPI_HSPI_CALFCR_FINE_Msk |
| #define | HSPI_CALFCR_FINE XSPI_HSPI_CALFCR_FINE |
| #define | HSPI_CALFCR_COARSE_Pos XSPI_HSPI_CALFCR_COARSE_Pos |
| #define | HSPI_CALFCR_COARSE_Msk XSPI_HSPI_CALFCR_COARSE_Msk |
| #define | HSPI_CALFCR_COARSE XSPI_HSPI_CALFCR_COARSE |
| #define | HSPI_CALFCR_CALMAX_Pos XSPI_HSPI_CALFCR_CALMAX_Pos |
| #define | HSPI_CALFCR_CALMAX_Msk XSPI_HSPI_CALFCR_CALMAX_Msk |
| #define | HSPI_CALFCR_CALMAX XSPI_HSPI_CALFCR_CALMAX |
| #define | HSPI_CALMR_FINE_Pos XSPI_HSPI_CALMR_FINE_Pos |
| #define | HSPI_CALMR_FINE_Msk XSPI_HSPI_CALMR_FINE_Msk |
| #define | HSPI_CALMR_FINE XSPI_HSPI_CALMR_FINE |
| #define | HSPI_CALMR_COARSE_Pos XSPI_HSPI_CALMR_COARSE_Pos |
| #define | HSPI_CALMR_COARSE_Msk XSPI_HSPI_CALMR_COARSE_Msk |
| #define | HSPI_CALMR_COARSE XSPI_HSPI_CALMR_COARSE |
| #define | HSPI_CALSOR_FINE_Pos XSPI_HSPI_CALSOR_FINE_Pos |
| #define | HSPI_CALSOR_FINE_Msk XSPI_HSPI_CALSOR_FINE_Msk |
| #define | HSPI_CALSOR_FINE XSPI_HSPI_CALSOR_FINE |
| #define | HSPI_CALSOR_COARSE_Pos XSPI_HSPI_CALSOR_COARSE_Pos |
| #define | HSPI_CALSOR_COARSE_Msk XSPI_HSPI_CALSOR_COARSE_Msk |
| #define | HSPI_CALSOR_COARSE XSPI_HSPI_CALSOR_COARSE |
| #define | HSPI_CALSIR_FINE_Pos XSPI_HSPI_CALSIR_FINE_Pos |
| #define | HSPI_CALSIR_FINE_Msk XSPI_HSPI_CALSIR_FINE_Msk |
| #define | HSPI_CALSIR_FINE XSPI_HSPI_CALSIR_FINE |
| #define | HSPI_CALSIR_COARSE_Pos XSPI_HSPI_CALSIR_COARSE_Pos |
| #define | HSPI_CALSIR_COARSE_Msk XSPI_HSPI_CALSIR_COARSE_Msk |
| #define | HSPI_CALSIR_COARSE XSPI_HSPI_CALSIR_COARSE |
| #define | XSPIM_CR_MUXEN_Pos (0U) |
| #define | XSPIM_CR_MUXEN_Msk (0x1UL << XSPIM_CR_MUXEN_Pos) |
| #define | XSPIM_CR_MUXEN XSPIM_CR_MUXEN_Msk |
| #define | XSPIM_CR_REQ2ACK_TIME_Pos (16U) |
| #define | XSPIM_CR_REQ2ACK_TIME_Msk (0xFFUL << XSPIM_CR_REQ2ACK_TIME_Pos) |
| #define | XSPIM_CR_REQ2ACK_TIME XSPIM_CR_REQ2ACK_TIME_Msk |
| #define | XSPIM_PCR_CLKEN_Pos (0U) |
| #define | XSPIM_PCR_CLKEN_Msk (0x1UL << XSPIM_PCR_CLKEN_Pos) |
| #define | XSPIM_PCR_CLKEN XSPIM_PCR_CLKEN_Msk |
| #define | XSPIM_PCR_CLKSRC_Pos (1U) |
| #define | XSPIM_PCR_CLKSRC_Msk (0x1UL << XSPIM_PCR_CLKSRC_Pos) |
| #define | XSPIM_PCR_CLKSRC XSPIM_PCR_CLKSRC_Msk |
| #define | XSPIM_PCR_DQSEN_Pos (4U) |
| #define | XSPIM_PCR_DQSEN_Msk (0x1UL << XSPIM_PCR_DQSEN_Pos) |
| #define | XSPIM_PCR_DQSEN XSPIM_PCR_DQSEN_Msk |
| #define | XSPIM_PCR_DQSSRC_Pos (5U) |
| #define | XSPIM_PCR_DQSSRC_Msk (0x1UL << XSPIM_PCR_DQSSRC_Pos) |
| #define | XSPIM_PCR_DQSSRC XSPIM_PCR_DQSSRC_Msk |
| #define | XSPIM_PCR_NCSEN_Pos (8U) |
| #define | XSPIM_PCR_NCSEN_Msk (0x1UL << XSPIM_PCR_NCSEN_Pos) |
| #define | XSPIM_PCR_NCSEN XSPIM_PCR_NCSEN_Msk |
| #define | XSPIM_PCR_NCSSRC_Pos (9U) |
| #define | XSPIM_PCR_NCSSRC_Msk (0x1UL << XSPIM_PCR_NCSSRC_Pos) |
| #define | XSPIM_PCR_NCSSRC XSPIM_PCR_NCSSRC_Msk |
| #define | XSPIM_PCR_IOLEN_Pos (16U) |
| #define | XSPIM_PCR_IOLEN_Msk (0x1UL << XSPIM_PCR_IOLEN_Pos) |
| #define | XSPIM_PCR_IOLEN XSPIM_PCR_IOLEN_Msk |
| #define | XSPIM_PCR_IOLSRC_Pos (17U) |
| #define | XSPIM_PCR_IOLSRC_Msk (0x3UL << XSPIM_PCR_IOLSRC_Pos) |
| #define | XSPIM_PCR_IOLSRC XSPIM_PCR_IOLSRC_Msk |
| #define | XSPIM_PCR_IOLSRC_0 (0x1UL << XSPIM_PCR_IOLSRC_Pos) |
| #define | XSPIM_PCR_IOLSRC_1 (0x2UL << XSPIM_PCR_IOLSRC_Pos) |
| #define | XSPIM_PCR_IOHEN_Pos (24U) |
| #define | XSPIM_PCR_IOHEN_Msk (0x1UL << XSPIM_PCR_IOHEN_Pos) |
| #define | XSPIM_PCR_IOHEN XSPIM_PCR_IOHEN_Msk |
| #define | XSPIM_PCR_IOHSRC_Pos (25U) |
| #define | XSPIM_PCR_IOHSRC_Msk (0x3UL << XSPIM_PCR_IOHSRC_Pos) |
| #define | XSPIM_PCR_IOHSRC XSPIM_PCR_IOHSRC_Msk |
| #define | XSPIM_PCR_IOHSRC_0 (0x1UL << XSPIM_PCR_IOHSRC_Pos) |
| #define | XSPIM_PCR_IOHSRC_1 (0x2UL << XSPIM_PCR_IOHSRC_Pos) |
| #define | OCTOSPIM_CR_MUXEN_Pos XSPIM_CR_MUXEN_Pos |
| #define | OCTOSPIM_CR_MUXEN_Msk XSPIM_CR_MUXEN_Msk |
| #define | OCTOSPIM_CR_MUXEN XSPIM_CR_MUXEN |
| #define | OCTOSPIM_CR_REQ2ACK_TIME_Pos XSPIM_CR_REQ2ACK_TIME_Pos |
| #define | OCTOSPIM_CR_REQ2ACK_TIME_Msk XSPIM_CR_REQ2ACK_TIME_Msk |
| #define | OCTOSPIM_CR_REQ2ACK_TIME XSPIM_CR_REQ2ACK_TIME |
| #define | OCTOSPIM_PCR_CLKEN_Pos XSPIM_PCR_CLKEN_Pos |
| #define | OCTOSPIM_PCR_CLKEN_Msk XSPIM_PCR_CLKEN_Msk |
| #define | OCTOSPIM_PCR_CLKEN XSPIM_PCR_CLKEN |
| #define | OCTOSPIM_PCR_CLKSRC_Pos XSPIM_PCR_CLKSRC_Pos |
| #define | OCTOSPIM_PCR_CLKSRC_Msk XSPIM_PCR_CLKSRC_Msk |
| #define | OCTOSPIM_PCR_CLKSRC XSPIM_PCR_CLKSRC |
| #define | OCTOSPIM_PCR_DQSEN_Pos XSPIM_PCR_DQSEN_Pos |
| #define | OCTOSPIM_PCR_DQSEN_Msk XSPIM_PCR_DQSEN_Msk |
| #define | OCTOSPIM_PCR_DQSEN XSPIM_PCR_DQSEN |
| #define | OCTOSPIM_PCR_DQSSRC_Pos XSPIM_PCR_DQSSRC_Pos |
| #define | OCTOSPIM_PCR_DQSSRC_Msk XSPIM_PCR_DQSSRC_Msk |
| #define | OCTOSPIM_PCR_DQSSRC XSPIM_PCR_DQSSRC |
| #define | OCTOSPIM_PCR_NCSEN_Pos XSPIM_PCR_NCSEN_Pos |
| #define | OCTOSPIM_PCR_NCSEN_Msk XSPIM_PCR_NCSEN_Msk |
| #define | OCTOSPIM_PCR_NCSEN XSPIM_PCR_NCSEN |
| #define | OCTOSPIM_PCR_NCSSRC_Pos XSPIM_PCR_NCSSRC_Pos |
| #define | OCTOSPIM_PCR_NCSSRC_Msk XSPIM_PCR_NCSSRC_Msk |
| #define | OCTOSPIM_PCR_NCSSRC XSPIM_PCR_NCSSRC |
| #define | OCTOSPIM_PCR_IOLEN_Pos XSPIM_PCR_IOLEN_Pos |
| #define | OCTOSPIM_PCR_IOLEN_Msk XSPIM_PCR_IOLEN_Msk |
| #define | OCTOSPIM_PCR_IOLEN XSPIM_PCR_IOLEN |
| #define | OCTOSPIM_PCR_IOLSRC_Pos XSPIM_PCR_IOLSRC_Pos |
| #define | OCTOSPIM_PCR_IOLSRC_Msk XSPIM_PCR_IOLSRC_Msk |
| #define | OCTOSPIM_PCR_IOLSRC XSPIM_PCR_IOLSRC |
| #define | OCTOSPIM_PCR_IOLSRC_0 XSPIM_PCR_IOLSRC_0 |
| #define | OCTOSPIM_PCR_IOLSRC_1 XSPIM_PCR_IOLSRC_1 |
| #define | OCTOSPIM_PCR_IOHEN_Pos XSPIM_PCR_IOHEN_Pos |
| #define | OCTOSPIM_PCR_IOHEN_Msk XSPIM_PCR_IOHEN_Msk |
| #define | OCTOSPIM_PCR_IOHEN XSPIM_PCR_IOHEN |
| #define | OCTOSPIM_PCR_IOHSRC_Pos XSPIM_PCR_IOHSRC_Pos |
| #define | OCTOSPIM_PCR_IOHSRC_Msk XSPIM_PCR_IOHSRC_Msk |
| #define | OCTOSPIM_PCR_IOHSRC XSPIM_PCR_IOHSRC |
| #define | OCTOSPIM_PCR_IOHSRC_0 XSPIM_PCR_IOHSRC_0 |
| #define | OCTOSPIM_PCR_IOHSRC_1 XSPIM_PCR_IOHSRC_1 |
| #define | DLYB_CR_DEN_Pos (0U) |
| #define | DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) |
| #define | DLYB_CR_DEN DLYB_CR_DEN_Msk |
| #define | DLYB_CR_SEN_Pos (1U) |
| #define | DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos) |
| #define | DLYB_CR_SEN DLYB_CR_SEN_Msk |
| #define | DLYB_CFGR_SEL_Pos (0U) |
| #define | DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos) |
| #define | DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk |
| #define | DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos) |
| #define | DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos) |
| #define | DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos) |
| #define | DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos) |
| #define | DLYB_CFGR_UNIT_Pos (8U) |
| #define | DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos) |
| #define | DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk |
| #define | DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos) |
| #define | DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos) |
| #define | DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos) |
| #define | DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos) |
| #define | DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos) |
| #define | DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos) |
| #define | DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos) |
| #define | DLYB_CFGR_LNG_Pos (16U) |
| #define | DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos) |
| #define | DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk |
| #define | DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos) |
| #define | DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos) |
| #define | DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos) |
| #define | DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos) |
| #define | DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos) |
| #define | DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos) |
| #define | DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos) |
| #define | DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos) |
| #define | DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos) |
| #define | DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos) |
| #define | DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos) |
| #define | DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos) |
| #define | DLYB_CFGR_LNGF_Pos (31U) |
| #define | DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos) |
| #define | DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk |
| #define | OTFDEC_CR_ENC_Pos (0U) |
| #define | OTFDEC_CR_ENC_Msk (0x1UL << OTFDEC_CR_ENC_Pos) |
| #define | OTFDEC_CR_ENC OTFDEC_CR_ENC_Msk |
| #define | OTFDEC_PRIVCFGR_PRIV_Pos (0U) |
| #define | OTFDEC_PRIVCFGR_PRIV_Msk (0x1UL << OTFDEC_PRIVCFGR_PRIV_Pos) |
| #define | OTFDEC_PRIVCFGR_PRIV OTFDEC_PRIVCFGR_PRIV_Msk |
| #define | OTFDEC_REG_CONFIGR_REG_EN_Pos (0U) |
| #define | OTFDEC_REG_CONFIGR_REG_EN_Msk (0x1UL << OTFDEC_REG_CONFIGR_REG_EN_Pos) |
| #define | OTFDEC_REG_CONFIGR_REG_EN OTFDEC_REG_CONFIGR_REG_EN_Msk |
| #define | OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos (1U) |
| #define | OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk (0x1UL << OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos) |
| #define | OTFDEC_REG_CONFIGR_CONFIGLOCK OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk |
| #define | OTFDEC_REG_CONFIGR_KEYLOCK_Pos (2U) |
| #define | OTFDEC_REG_CONFIGR_KEYLOCK_Msk (0x1UL << OTFDEC_REG_CONFIGR_KEYLOCK_Pos) |
| #define | OTFDEC_REG_CONFIGR_KEYLOCK OTFDEC_REG_CONFIGR_KEYLOCK_Msk |
| #define | OTFDEC_REG_CONFIGR_MODE_Pos (4U) |
| #define | OTFDEC_REG_CONFIGR_MODE_Msk (0x3UL << OTFDEC_REG_CONFIGR_MODE_Pos) |
| #define | OTFDEC_REG_CONFIGR_MODE OTFDEC_REG_CONFIGR_MODE_Msk |
| #define | OTFDEC_REG_CONFIGR_MODE_0 (0x1UL << OTFDEC_REG_CONFIGR_MODE_Pos) |
| #define | OTFDEC_REG_CONFIGR_MODE_1 (0x2UL << OTFDEC_REG_CONFIGR_MODE_Pos) |
| #define | OTFDEC_REG_CONFIGR_KEYCRC_Pos (8U) |
| #define | OTFDEC_REG_CONFIGR_KEYCRC_Msk (0xFFUL << OTFDEC_REG_CONFIGR_KEYCRC_Pos) |
| #define | OTFDEC_REG_CONFIGR_KEYCRC OTFDEC_REG_CONFIGR_KEYCRC_Msk |
| #define | OTFDEC_REG_CONFIGR_VERSION_Pos (16U) |
| #define | OTFDEC_REG_CONFIGR_VERSION_Msk (0xFFFFUL << OTFDEC_REG_CONFIGR_VERSION_Pos) |
| #define | OTFDEC_REG_CONFIGR_VERSION OTFDEC_REG_CONFIGR_VERSION_Msk |
| #define | OTFDEC_REG_START_ADDR_Pos (0U) |
| #define | OTFDEC_REG_START_ADDR_Msk (0xFFFFFFFFUL << OTFDEC_REG_START_ADDR_Pos) |
| #define | OTFDEC_REG_START_ADDR OTFDEC_REG_START_ADDR_Msk |
| #define | OTFDEC_REG_END_ADDR_Pos (0U) |
| #define | OTFDEC_REG_END_ADDR_Msk (0xFFFFFFFFUL << OTFDEC_REG_END_ADDR_Pos) |
| #define | OTFDEC_REG_END_ADDR OTFDEC_REG_END_ADDR_Msk |
| #define | OTFDEC_REG_NONCER0_Pos (0U) |
| #define | OTFDEC_REG_NONCER0_Msk (0xFFFFFFFFUL << OTFDEC_REG_NONCER0_Pos) |
| #define | OTFDEC_REG_NONCER0 OTFDEC_REG_NONCER0_Msk |
| #define | OTFDEC_REG_NONCER1_Pos (0U) |
| #define | OTFDEC_REG_NONCER1_Msk (0xFFFFFFFFUL << OTFDEC_REG_NONCER1_Pos) |
| #define | OTFDEC_REG_NONCER1 OTFDEC_REG_NONCER1_Msk |
| #define | OTFDEC_REG_KEYR0_Pos (0U) |
| #define | OTFDEC_REG_KEYR0_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR0_Pos) |
| #define | OTFDEC_REG_KEYR0 OTFDEC_REG_KEYR0_Msk |
| #define | OTFDEC_REG_KEYR1_Pos (0U) |
| #define | OTFDEC_REG_KEYR1_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR1_Pos) |
| #define | OTFDEC_REG_KEYR1 OTFDEC_REG_KEYR1_Msk |
| #define | OTFDEC_REG_KEYR2_Pos (0U) |
| #define | OTFDEC_REG_KEYR2_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR2_Pos) |
| #define | OTFDEC_REG_KEYR2 OTFDEC_REG_KEYR2_Msk |
| #define | OTFDEC_REG_KEYR3_Pos (0U) |
| #define | OTFDEC_REG_KEYR3_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR3_Pos) |
| #define | OTFDEC_REG_KEYR3 OTFDEC_REG_KEYR3_Msk |
| #define | OTFDEC_ISR_SEIF_Pos (0U) |
| #define | OTFDEC_ISR_SEIF_Msk (0x1UL << OTFDEC_ISR_SEIF_Pos) |
| #define | OTFDEC_ISR_SEIF OTFDEC_ISR_SEIF_Msk |
| #define | OTFDEC_ISR_XONEIF_Pos (1U) |
| #define | OTFDEC_ISR_XONEIF_Msk (0x1UL << OTFDEC_ISR_XONEIF_Pos) |
| #define | OTFDEC_ISR_XONEIF OTFDEC_ISR_XONEIF_Msk |
| #define | OTFDEC_ISR_KEIF_Pos (2U) |
| #define | OTFDEC_ISR_KEIF_Msk (0x1UL << OTFDEC_ISR_KEIF_Pos) |
| #define | OTFDEC_ISR_KEIF OTFDEC_ISR_KEIF_Msk |
| #define | OTFDEC_ICR_SEIF_Pos (0U) |
| #define | OTFDEC_ICR_SEIF_Msk (0x1UL << OTFDEC_ICR_SEIF_Pos) |
| #define | OTFDEC_ICR_SEIF OTFDEC_ICR_SEIF_Msk |
| #define | OTFDEC_ICR_XONEIF_Pos (1U) |
| #define | OTFDEC_ICR_XONEIF_Msk (0x1UL << OTFDEC_ICR_XONEIF_Pos) |
| #define | OTFDEC_ICR_XONEIF OTFDEC_ICR_XONEIF_Msk |
| #define | OTFDEC_ICR_KEIF_Pos (2U) |
| #define | OTFDEC_ICR_KEIF_Msk (0x1UL << OTFDEC_ICR_KEIF_Pos) |
| #define | OTFDEC_ICR_KEIF OTFDEC_ICR_KEIF_Msk |
| #define | OTFDEC_IER_SEIE_Pos (0U) |
| #define | OTFDEC_IER_SEIE_Msk (0x1UL << OTFDEC_IER_SEIE_Pos) |
| #define | OTFDEC_IER_SEIE OTFDEC_IER_SEIE_Msk |
| #define | OTFDEC_IER_XONEIE_Pos (1U) |
| #define | OTFDEC_IER_XONEIE_Msk (0x1UL << OTFDEC_IER_XONEIE_Pos) |
| #define | OTFDEC_IER_XONEIE OTFDEC_IER_XONEIE_Msk |
| #define | OTFDEC_IER_KEIE_Pos (2U) |
| #define | OTFDEC_IER_KEIE_Msk (0x1UL << OTFDEC_IER_KEIE_Pos) |
| #define | OTFDEC_IER_KEIE OTFDEC_IER_KEIE_Msk |
| #define | PWR_CR1_LPMS_Pos (0U) |
| #define | PWR_CR1_LPMS_Msk (0x7UL << PWR_CR1_LPMS_Pos) |
| #define | PWR_CR1_LPMS PWR_CR1_LPMS_Msk |
| #define | PWR_CR1_LPMS_0 (0x1UL << PWR_CR1_LPMS_Pos) |
| #define | PWR_CR1_LPMS_1 (0x2UL << PWR_CR1_LPMS_Pos) |
| #define | PWR_CR1_LPMS_2 (0x4UL << PWR_CR1_LPMS_Pos) |
| #define | PWR_CR1_RRSB1_Pos (5U) |
| #define | PWR_CR1_RRSB1_Msk (0x1UL << PWR_CR1_RRSB1_Pos) |
| #define | PWR_CR1_RRSB1 PWR_CR1_RRSB1_Msk |
| #define | PWR_CR1_RRSB2_Pos (6U) |
| #define | PWR_CR1_RRSB2_Msk (0x1UL << PWR_CR1_RRSB2_Pos) |
| #define | PWR_CR1_RRSB2 PWR_CR1_RRSB2_Msk |
| #define | PWR_CR1_ULPMEN_Pos (7U) |
| #define | PWR_CR1_ULPMEN_Msk (0x1UL << PWR_CR1_ULPMEN_Pos) |
| #define | PWR_CR1_ULPMEN PWR_CR1_ULPMEN_Msk |
| #define | PWR_CR1_SRAM1PD_Pos (8U) |
| #define | PWR_CR1_SRAM1PD_Msk (0x1UL << PWR_CR1_SRAM1PD_Pos) |
| #define | PWR_CR1_SRAM1PD PWR_CR1_SRAM1PD_Msk |
| #define | PWR_CR1_SRAM2PD_Pos (9U) |
| #define | PWR_CR1_SRAM2PD_Msk (0x1UL << PWR_CR1_SRAM2PD_Pos) |
| #define | PWR_CR1_SRAM2PD PWR_CR1_SRAM2PD_Msk |
| #define | PWR_CR1_SRAM3PD_Pos (10U) |
| #define | PWR_CR1_SRAM3PD_Msk (0x1UL << PWR_CR1_SRAM3PD_Pos) |
| #define | PWR_CR1_SRAM3PD PWR_CR1_SRAM3PD_Msk |
| #define | PWR_CR1_SRAM4PD_Pos (11U) |
| #define | PWR_CR1_SRAM4PD_Msk (0x1UL << PWR_CR1_SRAM4PD_Pos) |
| #define | PWR_CR1_SRAM4PD PWR_CR1_SRAM4PD_Msk |
| #define | PWR_CR1_SRAM5PD_Pos (12U) |
| #define | PWR_CR1_SRAM5PD_Msk (0x1UL << PWR_CR1_SRAM5PD_Pos) |
| #define | PWR_CR1_SRAM5PD PWR_CR1_SRAM5PD_Msk |
| #define | PWR_CR1_SRAM6PD_Pos (13U) |
| #define | PWR_CR1_SRAM6PD_Msk (0x1UL << PWR_CR1_SRAM6PD_Pos) |
| #define | PWR_CR1_SRAM6PD PWR_CR1_SRAM6PD_Msk |
| #define | PWR_CR1_FORCE_USBPWR_Pos (15U) |
| #define | PWR_CR1_FORCE_USBPWR_Msk (0x1UL << PWR_CR1_FORCE_USBPWR_Pos) |
| #define | PWR_CR1_FORCE_USBPWR PWR_CR1_FORCE_USBPWR_Msk |
| #define | PWR_CR2_SRAM1PDS1_Pos (0U) |
| #define | PWR_CR2_SRAM1PDS1_Msk (0x1UL << PWR_CR2_SRAM1PDS1_Pos) |
| #define | PWR_CR2_SRAM1PDS1 PWR_CR2_SRAM1PDS1_Msk |
| #define | PWR_CR2_SRAM1PDS2_Pos (1U) |
| #define | PWR_CR2_SRAM1PDS2_Msk (0x1UL << PWR_CR2_SRAM1PDS2_Pos) |
| #define | PWR_CR2_SRAM1PDS2 PWR_CR2_SRAM1PDS2_Msk |
| #define | PWR_CR2_SRAM1PDS3_Pos (2U) |
| #define | PWR_CR2_SRAM1PDS3_Msk (0x1UL << PWR_CR2_SRAM1PDS3_Pos) |
| #define | PWR_CR2_SRAM1PDS3 PWR_CR2_SRAM1PDS3_Msk |
| #define | PWR_CR2_SRAM2PDS1_Pos (4U) |
| #define | PWR_CR2_SRAM2PDS1_Msk (0x1UL << PWR_CR2_SRAM2PDS1_Pos) |
| #define | PWR_CR2_SRAM2PDS1 PWR_CR2_SRAM2PDS1_Msk |
| #define | PWR_CR2_SRAM2PDS2_Pos (5U) |
| #define | PWR_CR2_SRAM2PDS2_Msk (0x1UL << PWR_CR2_SRAM2PDS2_Pos) |
| #define | PWR_CR2_SRAM2PDS2 PWR_CR2_SRAM2PDS2_Msk |
| #define | PWR_CR2_SRAM4PDS_Pos (6U) |
| #define | PWR_CR2_SRAM4PDS_Msk (0x1UL << PWR_CR2_SRAM4PDS_Pos) |
| #define | PWR_CR2_SRAM4PDS PWR_CR2_SRAM4PDS_Msk |
| #define | PWR_CR2_DC2RAMPDS_Pos (7U) |
| #define | PWR_CR2_DC2RAMPDS_Msk (0x1UL << PWR_CR2_DC2RAMPDS_Pos) |
| #define | PWR_CR2_DC2RAMPDS PWR_CR2_DC2RAMPDS_Msk |
| #define | PWR_CR2_ICRAMPDS_Pos (8U) |
| #define | PWR_CR2_ICRAMPDS_Msk (0x1UL << PWR_CR2_ICRAMPDS_Pos) |
| #define | PWR_CR2_ICRAMPDS PWR_CR2_ICRAMPDS_Msk |
| #define | PWR_CR2_DC1RAMPDS_Pos (9U) |
| #define | PWR_CR2_DC1RAMPDS_Msk (0x1UL << PWR_CR2_DC1RAMPDS_Pos) |
| #define | PWR_CR2_DC1RAMPDS PWR_CR2_DC1RAMPDS_Msk |
| #define | PWR_CR2_DMA2DRAMPDS_Pos (10U) |
| #define | PWR_CR2_DMA2DRAMPDS_Msk (0x1UL << PWR_CR2_DMA2DRAMPDS_Pos) |
| #define | PWR_CR2_DMA2DRAMPDS PWR_CR2_DMA2DRAMPDS_Msk |
| #define | PWR_CR2_PRAMPDS_Pos (11U) |
| #define | PWR_CR2_PRAMPDS_Msk (0x1UL << PWR_CR2_PRAMPDS_Pos) |
| #define | PWR_CR2_PRAMPDS PWR_CR2_PRAMPDS_Msk |
| #define | PWR_CR2_PKARAMPDS_Pos (12U) |
| #define | PWR_CR2_PKARAMPDS_Msk (0x1UL << PWR_CR2_PKARAMPDS_Pos) |
| #define | PWR_CR2_PKARAMPDS PWR_CR2_PKARAMPDS_Msk |
| #define | PWR_CR2_SRAM4FWU_Pos (13U) |
| #define | PWR_CR2_SRAM4FWU_Msk (0x1UL << PWR_CR2_SRAM4FWU_Pos) |
| #define | PWR_CR2_SRAM4FWU PWR_CR2_SRAM4FWU_Msk |
| #define | PWR_CR2_FLASHFWU_Pos (14U) |
| #define | PWR_CR2_FLASHFWU_Msk (0x1UL << PWR_CR2_FLASHFWU_Pos) |
| #define | PWR_CR2_FLASHFWU PWR_CR2_FLASHFWU_Msk |
| #define | PWR_CR2_SRAM3PDS1_Pos (16U) |
| #define | PWR_CR2_SRAM3PDS1_Msk (0x1UL << PWR_CR2_SRAM3PDS1_Pos) |
| #define | PWR_CR2_SRAM3PDS1 PWR_CR2_SRAM3PDS1_Msk |
| #define | PWR_CR2_SRAM3PDS2_Pos (17U) |
| #define | PWR_CR2_SRAM3PDS2_Msk (0x1UL << PWR_CR2_SRAM3PDS2_Pos) |
| #define | PWR_CR2_SRAM3PDS2 PWR_CR2_SRAM3PDS2_Msk |
| #define | PWR_CR2_SRAM3PDS3_Pos (18U) |
| #define | PWR_CR2_SRAM3PDS3_Msk (0x1UL << PWR_CR2_SRAM3PDS3_Pos) |
| #define | PWR_CR2_SRAM3PDS3 PWR_CR2_SRAM3PDS3_Msk |
| #define | PWR_CR2_SRAM3PDS4_Pos (19U) |
| #define | PWR_CR2_SRAM3PDS4_Msk (0x1UL << PWR_CR2_SRAM3PDS4_Pos) |
| #define | PWR_CR2_SRAM3PDS4 PWR_CR2_SRAM3PDS4_Msk |
| #define | PWR_CR2_SRAM3PDS5_Pos (20U) |
| #define | PWR_CR2_SRAM3PDS5_Msk (0x1UL << PWR_CR2_SRAM3PDS5_Pos) |
| #define | PWR_CR2_SRAM3PDS5 PWR_CR2_SRAM3PDS5_Msk |
| #define | PWR_CR2_SRAM3PDS6_Pos (21U) |
| #define | PWR_CR2_SRAM3PDS6_Msk (0x1UL << PWR_CR2_SRAM3PDS6_Pos) |
| #define | PWR_CR2_SRAM3PDS6 PWR_CR2_SRAM3PDS6_Msk |
| #define | PWR_CR2_SRAM3PDS7_Pos (22U) |
| #define | PWR_CR2_SRAM3PDS7_Msk (0x1UL << PWR_CR2_SRAM3PDS7_Pos) |
| #define | PWR_CR2_SRAM3PDS7 PWR_CR2_SRAM3PDS7_Msk |
| #define | PWR_CR2_SRAM3PDS8_Pos (23U) |
| #define | PWR_CR2_SRAM3PDS8_Msk (0x1UL << PWR_CR2_SRAM3PDS8_Pos) |
| #define | PWR_CR2_SRAM3PDS8 PWR_CR2_SRAM3PDS8_Msk |
| #define | PWR_CR2_GPRAMPDS_Pos (24U) |
| #define | PWR_CR2_GPRAMPDS_Msk (0x1UL << PWR_CR2_GPRAMPDS_Pos) |
| #define | PWR_CR2_GPRAMPDS PWR_CR2_GPRAMPDS_Msk |
| #define | PWR_CR2_DSIRAMPDS_Pos (25U) |
| #define | PWR_CR2_DSIRAMPDS_Msk (0x1UL << PWR_CR2_DSIRAMPDS_Pos) |
| #define | PWR_CR2_DSIRAMPDS PWR_CR2_DSIRAMPDS_Msk |
| #define | PWR_CR2_JPEGRAMPDS_Pos (26U) |
| #define | PWR_CR2_JPEGRAMPDS_Msk (0x1UL << PWR_CR2_JPEGRAMPDS_Pos) |
| #define | PWR_CR2_JPEGRAMPDS PWR_CR2_JPEGRAMPDS_Msk |
| #define | PWR_CR2_SRDRUN_Pos (31U) |
| #define | PWR_CR2_SRDRUN_Msk (0x1UL << PWR_CR2_SRDRUN_Pos) |
| #define | PWR_CR2_SRDRUN PWR_CR2_SRDRUN_Msk |
| #define | PWR_CR3_REGSEL_Pos (1U) |
| #define | PWR_CR3_REGSEL_Msk (0x1UL << PWR_CR3_REGSEL_Pos) |
| #define | PWR_CR3_REGSEL PWR_CR3_REGSEL_Msk |
| #define | PWR_CR3_FSTEN_Pos (2U) |
| #define | PWR_CR3_FSTEN_Msk (0x1UL << PWR_CR3_FSTEN_Pos) |
| #define | PWR_CR3_FSTEN PWR_CR3_FSTEN_Msk |
| #define | PWR_VOSR_USBBOOSTRDY_Pos (13U) |
| #define | PWR_VOSR_USBBOOSTRDY_Msk (0x1UL << PWR_VOSR_USBBOOSTRDY_Pos) |
| #define | PWR_VOSR_USBBOOSTRDY PWR_VOSR_USBBOOSTRDY_Msk |
| #define | PWR_VOSR_BOOSTRDY_Pos (14U) |
| #define | PWR_VOSR_BOOSTRDY_Msk (0x1UL << PWR_VOSR_BOOSTRDY_Pos) |
| #define | PWR_VOSR_BOOSTRDY PWR_VOSR_BOOSTRDY_Msk |
| #define | PWR_VOSR_VOSRDY_Pos (15U) |
| #define | PWR_VOSR_VOSRDY_Msk (0x1UL << PWR_VOSR_VOSRDY_Pos) |
| #define | PWR_VOSR_VOSRDY PWR_VOSR_VOSRDY_Msk |
| #define | PWR_VOSR_VOS_Pos (16U) |
| #define | PWR_VOSR_VOS_Msk (0x3UL << PWR_VOSR_VOS_Pos) |
| #define | PWR_VOSR_VOS PWR_VOSR_VOS_Msk |
| #define | PWR_VOSR_VOS_0 (0x1UL << PWR_VOSR_VOS_Pos) |
| #define | PWR_VOSR_VOS_1 (0x2UL << PWR_VOSR_VOS_Pos) |
| #define | PWR_VOSR_BOOSTEN_Pos (18U) |
| #define | PWR_VOSR_BOOSTEN_Msk (0x1UL << PWR_VOSR_BOOSTEN_Pos) |
| #define | PWR_VOSR_BOOSTEN PWR_VOSR_BOOSTEN_Msk |
| #define | PWR_VOSR_USBPWREN_Pos (19U) |
| #define | PWR_VOSR_USBPWREN_Msk (0x1UL << PWR_VOSR_USBPWREN_Pos) |
| #define | PWR_VOSR_USBPWREN PWR_VOSR_USBPWREN_Msk |
| #define | PWR_VOSR_USBBOOSTEN_Pos (20U) |
| #define | PWR_VOSR_USBBOOSTEN_Msk (0x1UL << PWR_VOSR_USBBOOSTEN_Pos) |
| #define | PWR_VOSR_USBBOOSTEN PWR_VOSR_USBBOOSTEN_Msk |
| #define | PWR_VOSR_VDD11USBDIS_Pos (21U) |
| #define | PWR_VOSR_VDD11USBDIS_Msk (0x1UL << PWR_VOSR_VDD11USBDIS_Pos) |
| #define | PWR_VOSR_VDD11USBDIS PWR_VOSR_VDD11USBDIS_Msk |
| #define | PWR_SVMCR_PVDE_Pos (4U) |
| #define | PWR_SVMCR_PVDE_Msk (0x1UL << PWR_SVMCR_PVDE_Pos) |
| #define | PWR_SVMCR_PVDE PWR_SVMCR_PVDE_Msk |
| #define | PWR_SVMCR_PVDLS_Pos (5U) |
| #define | PWR_SVMCR_PVDLS_Msk (0x7UL << PWR_SVMCR_PVDLS_Pos) |
| #define | PWR_SVMCR_PVDLS PWR_SVMCR_PVDLS_Msk |
| #define | PWR_SVMCR_PVDLS_0 (0x1UL << PWR_SVMCR_PVDLS_Pos) |
| #define | PWR_SVMCR_PVDLS_1 (0x2UL << PWR_SVMCR_PVDLS_Pos) |
| #define | PWR_SVMCR_PVDLS_2 (0x4UL << PWR_SVMCR_PVDLS_Pos) |
| #define | PWR_SVMCR_UVMEN_Pos (24U) |
| #define | PWR_SVMCR_UVMEN_Msk (0x1UL << PWR_SVMCR_UVMEN_Pos) |
| #define | PWR_SVMCR_UVMEN PWR_SVMCR_UVMEN_Msk |
| #define | PWR_SVMCR_IO2VMEN_Pos (25U) |
| #define | PWR_SVMCR_IO2VMEN_Msk (0x1UL << PWR_SVMCR_IO2VMEN_Pos) |
| #define | PWR_SVMCR_IO2VMEN PWR_SVMCR_IO2VMEN_Msk |
| #define | PWR_SVMCR_AVM1EN_Pos (26U) |
| #define | PWR_SVMCR_AVM1EN_Msk (0x1UL << PWR_SVMCR_AVM1EN_Pos) |
| #define | PWR_SVMCR_AVM1EN PWR_SVMCR_AVM1EN_Msk |
| #define | PWR_SVMCR_AVM2EN_Pos (27U) |
| #define | PWR_SVMCR_AVM2EN_Msk (0x1UL << PWR_SVMCR_AVM2EN_Pos) |
| #define | PWR_SVMCR_AVM2EN PWR_SVMCR_AVM2EN_Msk |
| #define | PWR_SVMCR_USV_Pos (28U) |
| #define | PWR_SVMCR_USV_Msk (0x1UL << PWR_SVMCR_USV_Pos) |
| #define | PWR_SVMCR_USV PWR_SVMCR_USV_Msk |
| #define | PWR_SVMCR_IO2SV_Pos (29U) |
| #define | PWR_SVMCR_IO2SV_Msk (0x1UL << PWR_SVMCR_IO2SV_Pos) |
| #define | PWR_SVMCR_IO2SV PWR_SVMCR_IO2SV_Msk |
| #define | PWR_SVMCR_ASV_Pos (30U) |
| #define | PWR_SVMCR_ASV_Msk (0x1UL << PWR_SVMCR_ASV_Pos) |
| #define | PWR_SVMCR_ASV PWR_SVMCR_ASV_Msk |
| #define | PWR_WUCR1_WUPEN1_Pos (0U) |
| #define | PWR_WUCR1_WUPEN1_Msk (0x1UL << PWR_WUCR1_WUPEN1_Pos) |
| #define | PWR_WUCR1_WUPEN1 PWR_WUCR1_WUPEN1_Msk |
| #define | PWR_WUCR1_WUPEN2_Pos (1U) |
| #define | PWR_WUCR1_WUPEN2_Msk (0x1UL << PWR_WUCR1_WUPEN2_Pos) |
| #define | PWR_WUCR1_WUPEN2 PWR_WUCR1_WUPEN2_Msk |
| #define | PWR_WUCR1_WUPEN3_Pos (2U) |
| #define | PWR_WUCR1_WUPEN3_Msk (0x1UL << PWR_WUCR1_WUPEN3_Pos) |
| #define | PWR_WUCR1_WUPEN3 PWR_WUCR1_WUPEN3_Msk |
| #define | PWR_WUCR1_WUPEN4_Pos (3U) |
| #define | PWR_WUCR1_WUPEN4_Msk (0x1UL << PWR_WUCR1_WUPEN4_Pos) |
| #define | PWR_WUCR1_WUPEN4 PWR_WUCR1_WUPEN4_Msk |
| #define | PWR_WUCR1_WUPEN5_Pos (4U) |
| #define | PWR_WUCR1_WUPEN5_Msk (0x1UL << PWR_WUCR1_WUPEN5_Pos) |
| #define | PWR_WUCR1_WUPEN5 PWR_WUCR1_WUPEN5_Msk |
| #define | PWR_WUCR1_WUPEN6_Pos (5U) |
| #define | PWR_WUCR1_WUPEN6_Msk (0x1UL << PWR_WUCR1_WUPEN6_Pos) |
| #define | PWR_WUCR1_WUPEN6 PWR_WUCR1_WUPEN6_Msk |
| #define | PWR_WUCR1_WUPEN7_Pos (6U) |
| #define | PWR_WUCR1_WUPEN7_Msk (0x1UL << PWR_WUCR1_WUPEN7_Pos) |
| #define | PWR_WUCR1_WUPEN7 PWR_WUCR1_WUPEN7_Msk |
| #define | PWR_WUCR1_WUPEN8_Pos (7U) |
| #define | PWR_WUCR1_WUPEN8_Msk (0x1UL << PWR_WUCR1_WUPEN8_Pos) |
| #define | PWR_WUCR1_WUPEN8 PWR_WUCR1_WUPEN8_Msk |
| #define | PWR_WUCR2_WUPP1_Pos (0U) |
| #define | PWR_WUCR2_WUPP1_Msk (0x1UL << PWR_WUCR2_WUPP1_Pos) |
| #define | PWR_WUCR2_WUPP1 PWR_WUCR2_WUPP1_Msk |
| #define | PWR_WUCR2_WUPP2_Pos (1U) |
| #define | PWR_WUCR2_WUPP2_Msk (0x1UL << PWR_WUCR2_WUPP2_Pos) |
| #define | PWR_WUCR2_WUPP2 PWR_WUCR2_WUPP2_Msk |
| #define | PWR_WUCR2_WUPP3_Pos (2U) |
| #define | PWR_WUCR2_WUPP3_Msk (0x1UL << PWR_WUCR2_WUPP3_Pos) |
| #define | PWR_WUCR2_WUPP3 PWR_WUCR2_WUPP3_Msk |
| #define | PWR_WUCR2_WUPP4_Pos (3U) |
| #define | PWR_WUCR2_WUPP4_Msk (0x1UL << PWR_WUCR2_WUPP4_Pos) |
| #define | PWR_WUCR2_WUPP4 PWR_WUCR2_WUPP4_Msk |
| #define | PWR_WUCR2_WUPP5_Pos (4U) |
| #define | PWR_WUCR2_WUPP5_Msk (0x1UL << PWR_WUCR2_WUPP5_Pos) |
| #define | PWR_WUCR2_WUPP5 PWR_WUCR2_WUPP5_Msk |
| #define | PWR_WUCR2_WUPP6_Pos (5U) |
| #define | PWR_WUCR2_WUPP6_Msk (0x1UL << PWR_WUCR2_WUPP6_Pos) |
| #define | PWR_WUCR2_WUPP6 PWR_WUCR2_WUPP6_Msk |
| #define | PWR_WUCR2_WUPP7_Pos (6U) |
| #define | PWR_WUCR2_WUPP7_Msk (0x1UL << PWR_WUCR2_WUPP7_Pos) |
| #define | PWR_WUCR2_WUPP7 PWR_WUCR2_WUPP7_Msk |
| #define | PWR_WUCR2_WUPP8_Pos (7U) |
| #define | PWR_WUCR2_WUPP8_Msk (0x1UL << PWR_WUCR2_WUPP8_Pos) |
| #define | PWR_WUCR2_WUPP8 PWR_WUCR2_WUPP8_Msk |
| #define | PWR_WUCR3_WUSEL1_Pos (0U) |
| #define | PWR_WUCR3_WUSEL1_Msk (0x3UL << PWR_WUCR3_WUSEL1_Pos) |
| #define | PWR_WUCR3_WUSEL1 PWR_WUCR3_WUSEL1_Msk |
| #define | PWR_WUCR3_WUSEL1_0 (0x1UL << PWR_WUCR3_WUSEL1_Pos) |
| #define | PWR_WUCR3_WUSEL1_1 (0x2UL << PWR_WUCR3_WUSEL1_Pos) |
| #define | PWR_WUCR3_WUSEL2_Pos (2U) |
| #define | PWR_WUCR3_WUSEL2_Msk (0x3UL << PWR_WUCR3_WUSEL2_Pos) |
| #define | PWR_WUCR3_WUSEL2 PWR_WUCR3_WUSEL2_Msk |
| #define | PWR_WUCR3_WUSEL2_0 (0x1UL << PWR_WUCR3_WUSEL2_Pos) |
| #define | PWR_WUCR3_WUSEL2_1 (0x2UL << PWR_WUCR3_WUSEL2_Pos) |
| #define | PWR_WUCR3_WUSEL3_Pos (4U) |
| #define | PWR_WUCR3_WUSEL3_Msk (0x3UL << PWR_WUCR3_WUSEL3_Pos) |
| #define | PWR_WUCR3_WUSEL3 PWR_WUCR3_WUSEL3_Msk |
| #define | PWR_WUCR3_WUSEL3_0 (0x1UL << PWR_WUCR3_WUSEL3_Pos) |
| #define | PWR_WUCR3_WUSEL3_1 (0x2UL << PWR_WUCR3_WUSEL3_Pos) |
| #define | PWR_WUCR3_WUSEL4_Pos (6U) |
| #define | PWR_WUCR3_WUSEL4_Msk (0x3UL << PWR_WUCR3_WUSEL4_Pos) |
| #define | PWR_WUCR3_WUSEL4 PWR_WUCR3_WUSEL4_Msk |
| #define | PWR_WUCR3_WUSEL4_0 (0x1UL << PWR_WUCR3_WUSEL4_Pos) |
| #define | PWR_WUCR3_WUSEL4_1 (0x2UL << PWR_WUCR3_WUSEL4_Pos) |
| #define | PWR_WUCR3_WUSEL5_Pos (8U) |
| #define | PWR_WUCR3_WUSEL5_Msk (0x3UL << PWR_WUCR3_WUSEL5_Pos) |
| #define | PWR_WUCR3_WUSEL5 PWR_WUCR3_WUSEL5_Msk |
| #define | PWR_WUCR3_WUSEL5_0 (0x1UL << PWR_WUCR3_WUSEL5_Pos) |
| #define | PWR_WUCR3_WUSEL5_1 (0x2UL << PWR_WUCR3_WUSEL5_Pos) |
| #define | PWR_WUCR3_WUSEL6_Pos (10U) |
| #define | PWR_WUCR3_WUSEL6_Msk (0x3UL << PWR_WUCR3_WUSEL6_Pos) |
| #define | PWR_WUCR3_WUSEL6 PWR_WUCR3_WUSEL6_Msk |
| #define | PWR_WUCR3_WUSEL6_0 (0x1UL << PWR_WUCR3_WUSEL6_Pos) |
| #define | PWR_WUCR3_WUSEL6_1 (0x2UL << PWR_WUCR3_WUSEL6_Pos) |
| #define | PWR_WUCR3_WUSEL7_Pos (12U) |
| #define | PWR_WUCR3_WUSEL7_Msk (0x3UL << PWR_WUCR3_WUSEL7_Pos) |
| #define | PWR_WUCR3_WUSEL7 PWR_WUCR3_WUSEL7_Msk |
| #define | PWR_WUCR3_WUSEL7_0 (0x1UL << PWR_WUCR3_WUSEL7_Pos) |
| #define | PWR_WUCR3_WUSEL7_1 (0x2UL << PWR_WUCR3_WUSEL7_Pos) |
| #define | PWR_WUCR3_WUSEL8_Pos (14U) |
| #define | PWR_WUCR3_WUSEL8_Msk (0x3UL << PWR_WUCR3_WUSEL8_Pos) |
| #define | PWR_WUCR3_WUSEL8 PWR_WUCR3_WUSEL8_Msk |
| #define | PWR_WUCR3_WUSEL8_0 (0x1UL << PWR_WUCR3_WUSEL8_Pos) |
| #define | PWR_WUCR3_WUSEL8_1 (0x2UL << PWR_WUCR3_WUSEL8_Pos) |
| #define | PWR_BDCR1_BREN_Pos (0U) |
| #define | PWR_BDCR1_BREN_Msk (0x1UL << PWR_BDCR1_BREN_Pos) |
| #define | PWR_BDCR1_BREN PWR_BDCR1_BREN_Msk |
| #define | PWR_BDCR1_MONEN_Pos (4U) |
| #define | PWR_BDCR1_MONEN_Msk (0x1UL << PWR_BDCR1_MONEN_Pos) |
| #define | PWR_BDCR1_MONEN PWR_BDCR1_MONEN_Msk |
| #define | PWR_BDCR2_VBE_Pos (0U) |
| #define | PWR_BDCR2_VBE_Msk (0x1UL << PWR_BDCR2_VBE_Pos) |
| #define | PWR_BDCR2_VBE PWR_BDCR2_VBE_Msk |
| #define | PWR_BDCR2_VBRS_Pos (1U) |
| #define | PWR_BDCR2_VBRS_Msk (0x1UL << PWR_BDCR2_VBRS_Pos) |
| #define | PWR_BDCR2_VBRS PWR_BDCR2_VBRS_Msk |
| #define | PWR_DBPR_DBP_Pos (0U) |
| #define | PWR_DBPR_DBP_Msk (0x1UL << PWR_DBPR_DBP_Pos) |
| #define | PWR_DBPR_DBP PWR_DBPR_DBP_Msk |
| #define | PWR_UCPDR_UCPD_DBDIS_Pos (0U) |
| #define | PWR_UCPDR_UCPD_DBDIS_Msk (0x1UL << PWR_UCPDR_UCPD_DBDIS_Pos) |
| #define | PWR_UCPDR_UCPD_DBDIS PWR_UCPDR_UCPD_DBDIS_Msk |
| #define | PWR_UCPDR_UCPD_STDBY_Pos (1U) |
| #define | PWR_UCPDR_UCPD_STDBY_Msk (0x1UL << PWR_UCPDR_UCPD_STDBY_Pos) |
| #define | PWR_UCPDR_UCPD_STDBY PWR_UCPDR_UCPD_STDBY_Msk |
| #define | PWR_SECCFGR_WUP1SEC_Pos (0U) |
| #define | PWR_SECCFGR_WUP1SEC_Msk (0x1UL << PWR_SECCFGR_WUP1SEC_Pos) |
| #define | PWR_SECCFGR_WUP1SEC PWR_SECCFGR_WUP1SEC_Msk |
| #define | PWR_SECCFGR_WUP2SEC_Pos (1U) |
| #define | PWR_SECCFGR_WUP2SEC_Msk (0x1UL << PWR_SECCFGR_WUP2SEC_Pos) |
| #define | PWR_SECCFGR_WUP2SEC PWR_SECCFGR_WUP2SEC_Msk |
| #define | PWR_SECCFGR_WUP3SEC_Pos (2U) |
| #define | PWR_SECCFGR_WUP3SEC_Msk (0x1UL << PWR_SECCFGR_WUP3SEC_Pos) |
| #define | PWR_SECCFGR_WUP3SEC PWR_SECCFGR_WUP3SEC_Msk |
| #define | PWR_SECCFGR_WUP4SEC_Pos (3U) |
| #define | PWR_SECCFGR_WUP4SEC_Msk (0x1UL << PWR_SECCFGR_WUP4SEC_Pos) |
| #define | PWR_SECCFGR_WUP4SEC PWR_SECCFGR_WUP4SEC_Msk |
| #define | PWR_SECCFGR_WUP5SEC_Pos (4U) |
| #define | PWR_SECCFGR_WUP5SEC_Msk (0x1UL << PWR_SECCFGR_WUP5SEC_Pos) |
| #define | PWR_SECCFGR_WUP5SEC PWR_SECCFGR_WUP5SEC_Msk |
| #define | PWR_SECCFGR_WUP6SEC_Pos (5U) |
| #define | PWR_SECCFGR_WUP6SEC_Msk (0x1UL << PWR_SECCFGR_WUP6SEC_Pos) |
| #define | PWR_SECCFGR_WUP6SEC PWR_SECCFGR_WUP6SEC_Msk |
| #define | PWR_SECCFGR_WUP7SEC_Pos (6U) |
| #define | PWR_SECCFGR_WUP7SEC_Msk (0x1UL << PWR_SECCFGR_WUP7SEC_Pos) |
| #define | PWR_SECCFGR_WUP7SEC PWR_SECCFGR_WUP7SEC_Msk |
| #define | PWR_SECCFGR_WUP8SEC_Pos (7U) |
| #define | PWR_SECCFGR_WUP8SEC_Msk (0x1UL << PWR_SECCFGR_WUP8SEC_Pos) |
| #define | PWR_SECCFGR_WUP8SEC PWR_SECCFGR_WUP8SEC_Msk |
| #define | PWR_SECCFGR_LPMSEC_Pos (12U) |
| #define | PWR_SECCFGR_LPMSEC_Msk (0x1UL << PWR_SECCFGR_LPMSEC_Pos) |
| #define | PWR_SECCFGR_LPMSEC PWR_SECCFGR_LPMSEC_Msk |
| #define | PWR_SECCFGR_VDMSEC_Pos (13U) |
| #define | PWR_SECCFGR_VDMSEC_Msk (0x1UL << PWR_SECCFGR_VDMSEC_Pos) |
| #define | PWR_SECCFGR_VDMSEC PWR_SECCFGR_VDMSEC_Msk |
| #define | PWR_SECCFGR_VBSEC_Pos (14U) |
| #define | PWR_SECCFGR_VBSEC_Msk (0x1UL << PWR_SECCFGR_VBSEC_Pos) |
| #define | PWR_SECCFGR_VBSEC PWR_SECCFGR_VBSEC_Msk |
| #define | PWR_SECCFGR_APCSEC_Pos (15U) |
| #define | PWR_SECCFGR_APCSEC_Msk (0x1UL << PWR_SECCFGR_APCSEC_Pos) |
| #define | PWR_SECCFGR_APCSEC PWR_SECCFGR_APCSEC_Msk |
| #define | PWR_PRIVCFGR_SPRIV_Pos (0U) |
| #define | PWR_PRIVCFGR_SPRIV_Msk (0x1UL << PWR_PRIVCFGR_SPRIV_Pos) |
| #define | PWR_PRIVCFGR_SPRIV PWR_PRIVCFGR_SPRIV_Msk |
| #define | PWR_PRIVCFGR_NSPRIV_Pos (1U) |
| #define | PWR_PRIVCFGR_NSPRIV_Msk (0x1UL << PWR_PRIVCFGR_NSPRIV_Pos) |
| #define | PWR_PRIVCFGR_NSPRIV PWR_PRIVCFGR_NSPRIV_Msk |
| #define | PWR_SR_CSSF_Pos (0U) |
| #define | PWR_SR_CSSF_Msk (0x1UL << PWR_SR_CSSF_Pos) |
| #define | PWR_SR_CSSF PWR_SR_CSSF_Msk |
| #define | PWR_SR_STOPF_Pos (1U) |
| #define | PWR_SR_STOPF_Msk (0x1UL << PWR_SR_STOPF_Pos) |
| #define | PWR_SR_STOPF PWR_SR_STOPF_Msk |
| #define | PWR_SR_SBF_Pos (2U) |
| #define | PWR_SR_SBF_Msk (0x1UL << PWR_SR_SBF_Pos) |
| #define | PWR_SR_SBF PWR_SR_SBF_Msk |
| #define | PWR_SVMSR_REGS_Pos (1U) |
| #define | PWR_SVMSR_REGS_Msk (0x1UL << PWR_SVMSR_REGS_Pos) |
| #define | PWR_SVMSR_REGS PWR_SVMSR_REGS_Msk |
| #define | PWR_SVMSR_PVDO_Pos (4U) |
| #define | PWR_SVMSR_PVDO_Msk (0x1UL << PWR_SVMSR_PVDO_Pos) |
| #define | PWR_SVMSR_PVDO PWR_SVMSR_PVDO_Msk |
| #define | PWR_SVMSR_ACTVOSRDY_Pos (15U) |
| #define | PWR_SVMSR_ACTVOSRDY_Msk (0x1UL << PWR_SVMSR_ACTVOSRDY_Pos) |
| #define | PWR_SVMSR_ACTVOSRDY PWR_SVMSR_ACTVOSRDY_Msk |
| #define | PWR_SVMSR_ACTVOS_Pos (16U) |
| #define | PWR_SVMSR_ACTVOS_Msk (0x3UL << PWR_SVMSR_ACTVOS_Pos) |
| #define | PWR_SVMSR_ACTVOS PWR_SVMSR_ACTVOS_Msk |
| #define | PWR_SVMSR_ACTVOS_0 (0x1UL << PWR_SVMSR_ACTVOS_Pos) |
| #define | PWR_SVMSR_ACTVOS_1 (0x2UL << PWR_SVMSR_ACTVOS_Pos) |
| #define | PWR_SVMSR_VDDUSBRDY_Pos (24U) |
| #define | PWR_SVMSR_VDDUSBRDY_Msk (0x1UL << PWR_SVMSR_VDDUSBRDY_Pos) |
| #define | PWR_SVMSR_VDDUSBRDY PWR_SVMSR_VDDUSBRDY_Msk |
| #define | PWR_SVMSR_VDDIO2RDY_Pos (25U) |
| #define | PWR_SVMSR_VDDIO2RDY_Msk (0x1UL << PWR_SVMSR_VDDIO2RDY_Pos) |
| #define | PWR_SVMSR_VDDIO2RDY PWR_SVMSR_VDDIO2RDY_Msk |
| #define | PWR_SVMSR_VDDA1RDY_Pos (26U) |
| #define | PWR_SVMSR_VDDA1RDY_Msk (0x1UL << PWR_SVMSR_VDDA1RDY_Pos) |
| #define | PWR_SVMSR_VDDA1RDY PWR_SVMSR_VDDA1RDY_Msk |
| #define | PWR_SVMSR_VDDA2RDY_Pos (27U) |
| #define | PWR_SVMSR_VDDA2RDY_Msk (0x1UL << PWR_SVMSR_VDDA2RDY_Pos) |
| #define | PWR_SVMSR_VDDA2RDY PWR_SVMSR_VDDA2RDY_Msk |
| #define | PWR_BDSR_VBATH_Pos (1U) |
| #define | PWR_BDSR_VBATH_Msk (0x1UL << PWR_BDSR_VBATH_Pos) |
| #define | PWR_BDSR_VBATH PWR_BDSR_VBATH_Msk |
| #define | PWR_BDSR_TEMPL_Pos (2U) |
| #define | PWR_BDSR_TEMPL_Msk (0x1UL << PWR_BDSR_TEMPL_Pos) |
| #define | PWR_BDSR_TEMPL PWR_BDSR_TEMPL_Msk |
| #define | PWR_BDSR_TEMPH_Pos (3U) |
| #define | PWR_BDSR_TEMPH_Msk (0x1UL << PWR_BDSR_TEMPH_Pos) |
| #define | PWR_BDSR_TEMPH PWR_BDSR_TEMPH_Msk |
| #define | PWR_WUSR_WUF1_Pos (0U) |
| #define | PWR_WUSR_WUF1_Msk (0x1UL << PWR_WUSR_WUF1_Pos) |
| #define | PWR_WUSR_WUF1 PWR_WUSR_WUF1_Msk |
| #define | PWR_WUSR_WUF2_Pos (1U) |
| #define | PWR_WUSR_WUF2_Msk (0x1UL << PWR_WUSR_WUF2_Pos) |
| #define | PWR_WUSR_WUF2 PWR_WUSR_WUF2_Msk |
| #define | PWR_WUSR_WUF3_Pos (2U) |
| #define | PWR_WUSR_WUF3_Msk (0x1UL << PWR_WUSR_WUF3_Pos) |
| #define | PWR_WUSR_WUF3 PWR_WUSR_WUF3_Msk |
| #define | PWR_WUSR_WUF4_Pos (3U) |
| #define | PWR_WUSR_WUF4_Msk (0x1UL << PWR_WUSR_WUF4_Pos) |
| #define | PWR_WUSR_WUF4 PWR_WUSR_WUF4_Msk |
| #define | PWR_WUSR_WUF5_Pos (4U) |
| #define | PWR_WUSR_WUF5_Msk (0x1UL << PWR_WUSR_WUF5_Pos) |
| #define | PWR_WUSR_WUF5 PWR_WUSR_WUF5_Msk |
| #define | PWR_WUSR_WUF6_Pos (5U) |
| #define | PWR_WUSR_WUF6_Msk (0x1UL << PWR_WUSR_WUF6_Pos) |
| #define | PWR_WUSR_WUF6 PWR_WUSR_WUF6_Msk |
| #define | PWR_WUSR_WUF7_Pos (6U) |
| #define | PWR_WUSR_WUF7_Msk (0x1UL << PWR_WUSR_WUF7_Pos) |
| #define | PWR_WUSR_WUF7 PWR_WUSR_WUF7_Msk |
| #define | PWR_WUSR_WUF8_Pos (7U) |
| #define | PWR_WUSR_WUF8_Msk (0x1UL << PWR_WUSR_WUF8_Pos) |
| #define | PWR_WUSR_WUF8 PWR_WUSR_WUF8_Msk |
| #define | PWR_WUSR_WUF_Pos (0U) |
| #define | PWR_WUSR_WUF_Msk (0xFFUL << PWR_WUSR_WUF_Pos) |
| #define | PWR_WUSR_WUF PWR_WUSR_WUF_Msk |
| #define | PWR_WUSCR_CWUF1_Pos (0U) |
| #define | PWR_WUSCR_CWUF1_Msk (0x1UL << PWR_WUSCR_CWUF1_Pos) |
| #define | PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1_Msk |
| #define | PWR_WUSCR_CWUF2_Pos (1U) |
| #define | PWR_WUSCR_CWUF2_Msk (0x1UL << PWR_WUSCR_CWUF2_Pos) |
| #define | PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2_Msk |
| #define | PWR_WUSCR_CWUF3_Pos (2U) |
| #define | PWR_WUSCR_CWUF3_Msk (0x1UL << PWR_WUSCR_CWUF3_Pos) |
| #define | PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3_Msk |
| #define | PWR_WUSCR_CWUF4_Pos (3U) |
| #define | PWR_WUSCR_CWUF4_Msk (0x1UL << PWR_WUSCR_CWUF4_Pos) |
| #define | PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4_Msk |
| #define | PWR_WUSCR_CWUF5_Pos (4U) |
| #define | PWR_WUSCR_CWUF5_Msk (0x1UL << PWR_WUSCR_CWUF5_Pos) |
| #define | PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5_Msk |
| #define | PWR_WUSCR_CWUF6_Pos (5U) |
| #define | PWR_WUSCR_CWUF6_Msk (0x1UL << PWR_WUSCR_CWUF6_Pos) |
| #define | PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6_Msk |
| #define | PWR_WUSCR_CWUF7_Pos (6U) |
| #define | PWR_WUSCR_CWUF7_Msk (0x1UL << PWR_WUSCR_CWUF7_Pos) |
| #define | PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7_Msk |
| #define | PWR_WUSCR_CWUF8_Pos (7U) |
| #define | PWR_WUSCR_CWUF8_Msk (0x1UL << PWR_WUSCR_CWUF8_Pos) |
| #define | PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8_Msk |
| #define | PWR_WUSCR_CWUF_Pos (0U) |
| #define | PWR_WUSCR_CWUF_Msk (0xFFUL << PWR_WUSCR_CWUF_Pos) |
| #define | PWR_WUSCR_CWUF PWR_WUSCR_CWUF_Msk |
| #define | PWR_APCR_APC_Pos (0U) |
| #define | PWR_APCR_APC_Msk (0x1UL << PWR_APCR_APC_Pos) |
| #define | PWR_APCR_APC PWR_APCR_APC_Msk |
| #define | PWR_PUCRA_PU0_Pos (0U) |
| #define | PWR_PUCRA_PU0_Msk (0x1UL << PWR_PUCRA_PU0_Pos) |
| #define | PWR_PUCRA_PU0 PWR_PUCRA_PU0_Msk |
| #define | PWR_PUCRA_PU1_Pos (1U) |
| #define | PWR_PUCRA_PU1_Msk (0x1UL << PWR_PUCRA_PU1_Pos) |
| #define | PWR_PUCRA_PU1 PWR_PUCRA_PU1_Msk |
| #define | PWR_PUCRA_PU2_Pos (2U) |
| #define | PWR_PUCRA_PU2_Msk (0x1UL << PWR_PUCRA_PU2_Pos) |
| #define | PWR_PUCRA_PU2 PWR_PUCRA_PU2_Msk |
| #define | PWR_PUCRA_PU3_Pos (3U) |
| #define | PWR_PUCRA_PU3_Msk (0x1UL << PWR_PUCRA_PU3_Pos) |
| #define | PWR_PUCRA_PU3 PWR_PUCRA_PU3_Msk |
| #define | PWR_PUCRA_PU4_Pos (4U) |
| #define | PWR_PUCRA_PU4_Msk (0x1UL << PWR_PUCRA_PU4_Pos) |
| #define | PWR_PUCRA_PU4 PWR_PUCRA_PU4_Msk |
| #define | PWR_PUCRA_PU5_Pos (5U) |
| #define | PWR_PUCRA_PU5_Msk (0x1UL << PWR_PUCRA_PU5_Pos) |
| #define | PWR_PUCRA_PU5 PWR_PUCRA_PU5_Msk |
| #define | PWR_PUCRA_PU6_Pos (6U) |
| #define | PWR_PUCRA_PU6_Msk (0x1UL << PWR_PUCRA_PU6_Pos) |
| #define | PWR_PUCRA_PU6 PWR_PUCRA_PU6_Msk |
| #define | PWR_PUCRA_PU7_Pos (7U) |
| #define | PWR_PUCRA_PU7_Msk (0x1UL << PWR_PUCRA_PU7_Pos) |
| #define | PWR_PUCRA_PU7 PWR_PUCRA_PU7_Msk |
| #define | PWR_PUCRA_PU8_Pos (8U) |
| #define | PWR_PUCRA_PU8_Msk (0x1UL << PWR_PUCRA_PU8_Pos) |
| #define | PWR_PUCRA_PU8 PWR_PUCRA_PU8_Msk |
| #define | PWR_PUCRA_PU9_Pos (9U) |
| #define | PWR_PUCRA_PU9_Msk (0x1UL << PWR_PUCRA_PU9_Pos) |
| #define | PWR_PUCRA_PU9 PWR_PUCRA_PU9_Msk |
| #define | PWR_PUCRA_PU10_Pos (10U) |
| #define | PWR_PUCRA_PU10_Msk (0x1UL << PWR_PUCRA_PU10_Pos) |
| #define | PWR_PUCRA_PU10 PWR_PUCRA_PU10_Msk |
| #define | PWR_PUCRA_PU11_Pos (11U) |
| #define | PWR_PUCRA_PU11_Msk (0x1UL << PWR_PUCRA_PU11_Pos) |
| #define | PWR_PUCRA_PU11 PWR_PUCRA_PU11_Msk |
| #define | PWR_PUCRA_PU12_Pos (12U) |
| #define | PWR_PUCRA_PU12_Msk (0x1UL << PWR_PUCRA_PU12_Pos) |
| #define | PWR_PUCRA_PU12 PWR_PUCRA_PU12_Msk |
| #define | PWR_PUCRA_PU13_Pos (13U) |
| #define | PWR_PUCRA_PU13_Msk (0x1UL << PWR_PUCRA_PU13_Pos) |
| #define | PWR_PUCRA_PU13 PWR_PUCRA_PU13_Msk |
| #define | PWR_PUCRA_PU15_Pos (15U) |
| #define | PWR_PUCRA_PU15_Msk (0x1UL << PWR_PUCRA_PU15_Pos) |
| #define | PWR_PUCRA_PU15 PWR_PUCRA_PU15_Msk |
| #define | PWR_PDCRA_PD0_Pos (0U) |
| #define | PWR_PDCRA_PD0_Msk (0x1UL << PWR_PDCRA_PD0_Pos) |
| #define | PWR_PDCRA_PD0 PWR_PDCRA_PD0_Msk |
| #define | PWR_PDCRA_PD1_Pos (1U) |
| #define | PWR_PDCRA_PD1_Msk (0x1UL << PWR_PDCRA_PD1_Pos) |
| #define | PWR_PDCRA_PD1 PWR_PDCRA_PD1_Msk |
| #define | PWR_PDCRA_PD2_Pos (2U) |
| #define | PWR_PDCRA_PD2_Msk (0x1UL << PWR_PDCRA_PD2_Pos) |
| #define | PWR_PDCRA_PD2 PWR_PDCRA_PD2_Msk |
| #define | PWR_PDCRA_PD3_Pos (3U) |
| #define | PWR_PDCRA_PD3_Msk (0x1UL << PWR_PDCRA_PD3_Pos) |
| #define | PWR_PDCRA_PD3 PWR_PDCRA_PD3_Msk |
| #define | PWR_PDCRA_PD4_Pos (4U) |
| #define | PWR_PDCRA_PD4_Msk (0x1UL << PWR_PDCRA_PD4_Pos) |
| #define | PWR_PDCRA_PD4 PWR_PDCRA_PD4_Msk |
| #define | PWR_PDCRA_PD5_Pos (5U) |
| #define | PWR_PDCRA_PD5_Msk (0x1UL << PWR_PDCRA_PD5_Pos) |
| #define | PWR_PDCRA_PD5 PWR_PDCRA_PD5_Msk |
| #define | PWR_PDCRA_PD6_Pos (6U) |
| #define | PWR_PDCRA_PD6_Msk (0x1UL << PWR_PDCRA_PD6_Pos) |
| #define | PWR_PDCRA_PD6 PWR_PDCRA_PD6_Msk |
| #define | PWR_PDCRA_PD7_Pos (7U) |
| #define | PWR_PDCRA_PD7_Msk (0x1UL << PWR_PDCRA_PD7_Pos) |
| #define | PWR_PDCRA_PD7 PWR_PDCRA_PD7_Msk |
| #define | PWR_PDCRA_PD8_Pos (8U) |
| #define | PWR_PDCRA_PD8_Msk (0x1UL << PWR_PDCRA_PD8_Pos) |
| #define | PWR_PDCRA_PD8 PWR_PDCRA_PD8_Msk |
| #define | PWR_PDCRA_PD9_Pos (9U) |
| #define | PWR_PDCRA_PD9_Msk (0x1UL << PWR_PDCRA_PD9_Pos) |
| #define | PWR_PDCRA_PD9 PWR_PDCRA_PD9_Msk |
| #define | PWR_PDCRA_PD10_Pos (10U) |
| #define | PWR_PDCRA_PD10_Msk (0x1UL << PWR_PDCRA_PD10_Pos) |
| #define | PWR_PDCRA_PD10 PWR_PDCRA_PD10_Msk |
| #define | PWR_PDCRA_PD11_Pos (11U) |
| #define | PWR_PDCRA_PD11_Msk (0x1UL << PWR_PDCRA_PD11_Pos) |
| #define | PWR_PDCRA_PD11 PWR_PDCRA_PD11_Msk |
| #define | PWR_PDCRA_PD12_Pos (12U) |
| #define | PWR_PDCRA_PD12_Msk (0x1UL << PWR_PDCRA_PD12_Pos) |
| #define | PWR_PDCRA_PD12 PWR_PDCRA_PD12_Msk |
| #define | PWR_PDCRA_PD14_Pos (14U) |
| #define | PWR_PDCRA_PD14_Msk (0x1UL << PWR_PDCRA_PD14_Pos) |
| #define | PWR_PDCRA_PD14 PWR_PDCRA_PD14_Msk |
| #define | PWR_PUCRB_PU0_Pos (0U) |
| #define | PWR_PUCRB_PU0_Msk (0x1UL << PWR_PUCRB_PU0_Pos) |
| #define | PWR_PUCRB_PU0 PWR_PUCRB_PU0_Msk |
| #define | PWR_PUCRB_PU1_Pos (1U) |
| #define | PWR_PUCRB_PU1_Msk (0x1UL << PWR_PUCRB_PU1_Pos) |
| #define | PWR_PUCRB_PU1 PWR_PUCRB_PU1_Msk |
| #define | PWR_PUCRB_PU2_Pos (2U) |
| #define | PWR_PUCRB_PU2_Msk (0x1UL << PWR_PUCRB_PU2_Pos) |
| #define | PWR_PUCRB_PU2 PWR_PUCRB_PU2_Msk |
| #define | PWR_PUCRB_PU3_Pos (3U) |
| #define | PWR_PUCRB_PU3_Msk (0x1UL << PWR_PUCRB_PU3_Pos) |
| #define | PWR_PUCRB_PU3 PWR_PUCRB_PU3_Msk |
| #define | PWR_PUCRB_PU4_Pos (4U) |
| #define | PWR_PUCRB_PU4_Msk (0x1UL << PWR_PUCRB_PU4_Pos) |
| #define | PWR_PUCRB_PU4 PWR_PUCRB_PU4_Msk |
| #define | PWR_PUCRB_PU5_Pos (5U) |
| #define | PWR_PUCRB_PU5_Msk (0x1UL << PWR_PUCRB_PU5_Pos) |
| #define | PWR_PUCRB_PU5 PWR_PUCRB_PU5_Msk |
| #define | PWR_PUCRB_PU6_Pos (6U) |
| #define | PWR_PUCRB_PU6_Msk (0x1UL << PWR_PUCRB_PU6_Pos) |
| #define | PWR_PUCRB_PU6 PWR_PUCRB_PU6_Msk |
| #define | PWR_PUCRB_PU7_Pos (7U) |
| #define | PWR_PUCRB_PU7_Msk (0x1UL << PWR_PUCRB_PU7_Pos) |
| #define | PWR_PUCRB_PU7 PWR_PUCRB_PU7_Msk |
| #define | PWR_PUCRB_PU8_Pos (8U) |
| #define | PWR_PUCRB_PU8_Msk (0x1UL << PWR_PUCRB_PU8_Pos) |
| #define | PWR_PUCRB_PU8 PWR_PUCRB_PU8_Msk |
| #define | PWR_PUCRB_PU9_Pos (9U) |
| #define | PWR_PUCRB_PU9_Msk (0x1UL << PWR_PUCRB_PU9_Pos) |
| #define | PWR_PUCRB_PU9 PWR_PUCRB_PU9_Msk |
| #define | PWR_PUCRB_PU10_Pos (10U) |
| #define | PWR_PUCRB_PU10_Msk (0x1UL << PWR_PUCRB_PU10_Pos) |
| #define | PWR_PUCRB_PU10 PWR_PUCRB_PU10_Msk |
| #define | PWR_PUCRB_PU11_Pos (11U) |
| #define | PWR_PUCRB_PU11_Msk (0x1UL << PWR_PUCRB_PU11_Pos) |
| #define | PWR_PUCRB_PU11 PWR_PUCRB_PU11_Msk |
| #define | PWR_PUCRB_PU12_Pos (12U) |
| #define | PWR_PUCRB_PU12_Msk (0x1UL << PWR_PUCRB_PU12_Pos) |
| #define | PWR_PUCRB_PU12 PWR_PUCRB_PU12_Msk |
| #define | PWR_PUCRB_PU13_Pos (13U) |
| #define | PWR_PUCRB_PU13_Msk (0x1UL << PWR_PUCRB_PU13_Pos) |
| #define | PWR_PUCRB_PU13 PWR_PUCRB_PU13_Msk |
| #define | PWR_PUCRB_PU14_Pos (14U) |
| #define | PWR_PUCRB_PU14_Msk (0x1UL << PWR_PUCRB_PU14_Pos) |
| #define | PWR_PUCRB_PU14 PWR_PUCRB_PU14_Msk |
| #define | PWR_PUCRB_PU15_Pos (15U) |
| #define | PWR_PUCRB_PU15_Msk (0x1UL << PWR_PUCRB_PU15_Pos) |
| #define | PWR_PUCRB_PU15 PWR_PUCRB_PU15_Msk |
| #define | PWR_PDCRB_PD0_Pos (0U) |
| #define | PWR_PDCRB_PD0_Msk (0x1UL << PWR_PDCRB_PD0_Pos) |
| #define | PWR_PDCRB_PD0 PWR_PDCRB_PD0_Msk |
| #define | PWR_PDCRB_PD1_Pos (1U) |
| #define | PWR_PDCRB_PD1_Msk (0x1UL << PWR_PDCRB_PD1_Pos) |
| #define | PWR_PDCRB_PD1 PWR_PDCRB_PD1_Msk |
| #define | PWR_PDCRB_PD2_Pos (2U) |
| #define | PWR_PDCRB_PD2_Msk (0x1UL << PWR_PDCRB_PD2_Pos) |
| #define | PWR_PDCRB_PD2 PWR_PDCRB_PD2_Msk |
| #define | PWR_PDCRB_PD3_Pos (3U) |
| #define | PWR_PDCRB_PD3_Msk (0x1UL << PWR_PDCRB_PD3_Pos) |
| #define | PWR_PDCRB_PD3 PWR_PDCRB_PD3_Msk |
| #define | PWR_PDCRB_PD5_Pos (5U) |
| #define | PWR_PDCRB_PD5_Msk (0x1UL << PWR_PDCRB_PD5_Pos) |
| #define | PWR_PDCRB_PD5 PWR_PDCRB_PD5_Msk |
| #define | PWR_PDCRB_PD6_Pos (6U) |
| #define | PWR_PDCRB_PD6_Msk (0x1UL << PWR_PDCRB_PD6_Pos) |
| #define | PWR_PDCRB_PD6 PWR_PDCRB_PD6_Msk |
| #define | PWR_PDCRB_PD7_Pos (7U) |
| #define | PWR_PDCRB_PD7_Msk (0x1UL << PWR_PDCRB_PD7_Pos) |
| #define | PWR_PDCRB_PD7 PWR_PDCRB_PD7_Msk |
| #define | PWR_PDCRB_PD8_Pos (8U) |
| #define | PWR_PDCRB_PD8_Msk (0x1UL << PWR_PDCRB_PD8_Pos) |
| #define | PWR_PDCRB_PD8 PWR_PDCRB_PD8_Msk |
| #define | PWR_PDCRB_PD9_Pos (9U) |
| #define | PWR_PDCRB_PD9_Msk (0x1UL << PWR_PDCRB_PD9_Pos) |
| #define | PWR_PDCRB_PD9 PWR_PDCRB_PD9_Msk |
| #define | PWR_PDCRB_PD10_Pos (10U) |
| #define | PWR_PDCRB_PD10_Msk (0x1UL << PWR_PDCRB_PD10_Pos) |
| #define | PWR_PDCRB_PD10 PWR_PDCRB_PD10_Msk |
| #define | PWR_PDCRB_PD11_Pos (11U) |
| #define | PWR_PDCRB_PD11_Msk (0x1UL << PWR_PDCRB_PD11_Pos) |
| #define | PWR_PDCRB_PD11 PWR_PDCRB_PD11_Msk |
| #define | PWR_PDCRB_PD12_Pos (12U) |
| #define | PWR_PDCRB_PD12_Msk (0x1UL << PWR_PDCRB_PD12_Pos) |
| #define | PWR_PDCRB_PD12 PWR_PDCRB_PD12_Msk |
| #define | PWR_PDCRB_PD13_Pos (13U) |
| #define | PWR_PDCRB_PD13_Msk (0x1UL << PWR_PDCRB_PD13_Pos) |
| #define | PWR_PDCRB_PD13 PWR_PDCRB_PD13_Msk |
| #define | PWR_PDCRB_PD14_Pos (14U) |
| #define | PWR_PDCRB_PD14_Msk (0x1UL << PWR_PDCRB_PD14_Pos) |
| #define | PWR_PDCRB_PD14 PWR_PDCRB_PD14_Msk |
| #define | PWR_PDCRB_PD15_Pos (15U) |
| #define | PWR_PDCRB_PD15_Msk (0x1UL << PWR_PDCRB_PD15_Pos) |
| #define | PWR_PDCRB_PD15 PWR_PDCRB_PD15_Msk |
| #define | PWR_PUCRC_PU0_Pos (0U) |
| #define | PWR_PUCRC_PU0_Msk (0x1UL << PWR_PUCRC_PU0_Pos) |
| #define | PWR_PUCRC_PU0 PWR_PUCRC_PU0_Msk |
| #define | PWR_PUCRC_PU1_Pos (1U) |
| #define | PWR_PUCRC_PU1_Msk (0x1UL << PWR_PUCRC_PU1_Pos) |
| #define | PWR_PUCRC_PU1 PWR_PUCRC_PU1_Msk |
| #define | PWR_PUCRC_PU2_Pos (2U) |
| #define | PWR_PUCRC_PU2_Msk (0x1UL << PWR_PUCRC_PU2_Pos) |
| #define | PWR_PUCRC_PU2 PWR_PUCRC_PU2_Msk |
| #define | PWR_PUCRC_PU3_Pos (3U) |
| #define | PWR_PUCRC_PU3_Msk (0x1UL << PWR_PUCRC_PU3_Pos) |
| #define | PWR_PUCRC_PU3 PWR_PUCRC_PU3_Msk |
| #define | PWR_PUCRC_PU4_Pos (4U) |
| #define | PWR_PUCRC_PU4_Msk (0x1UL << PWR_PUCRC_PU4_Pos) |
| #define | PWR_PUCRC_PU4 PWR_PUCRC_PU4_Msk |
| #define | PWR_PUCRC_PU5_Pos (5U) |
| #define | PWR_PUCRC_PU5_Msk (0x1UL << PWR_PUCRC_PU5_Pos) |
| #define | PWR_PUCRC_PU5 PWR_PUCRC_PU5_Msk |
| #define | PWR_PUCRC_PU6_Pos (6U) |
| #define | PWR_PUCRC_PU6_Msk (0x1UL << PWR_PUCRC_PU6_Pos) |
| #define | PWR_PUCRC_PU6 PWR_PUCRC_PU6_Msk |
| #define | PWR_PUCRC_PU7_Pos (7U) |
| #define | PWR_PUCRC_PU7_Msk (0x1UL << PWR_PUCRC_PU7_Pos) |
| #define | PWR_PUCRC_PU7 PWR_PUCRC_PU7_Msk |
| #define | PWR_PUCRC_PU8_Pos (8U) |
| #define | PWR_PUCRC_PU8_Msk (0x1UL << PWR_PUCRC_PU8_Pos) |
| #define | PWR_PUCRC_PU8 PWR_PUCRC_PU8_Msk |
| #define | PWR_PUCRC_PU9_Pos (9U) |
| #define | PWR_PUCRC_PU9_Msk (0x1UL << PWR_PUCRC_PU9_Pos) |
| #define | PWR_PUCRC_PU9 PWR_PUCRC_PU9_Msk |
| #define | PWR_PUCRC_PU10_Pos (10U) |
| #define | PWR_PUCRC_PU10_Msk (0x1UL << PWR_PUCRC_PU10_Pos) |
| #define | PWR_PUCRC_PU10 PWR_PUCRC_PU10_Msk |
| #define | PWR_PUCRC_PU11_Pos (11U) |
| #define | PWR_PUCRC_PU11_Msk (0x1UL << PWR_PUCRC_PU11_Pos) |
| #define | PWR_PUCRC_PU11 PWR_PUCRC_PU11_Msk |
| #define | PWR_PUCRC_PU12_Pos (12U) |
| #define | PWR_PUCRC_PU12_Msk (0x1UL << PWR_PUCRC_PU12_Pos) |
| #define | PWR_PUCRC_PU12 PWR_PUCRC_PU12_Msk |
| #define | PWR_PUCRC_PU13_Pos (13U) |
| #define | PWR_PUCRC_PU13_Msk (0x1UL << PWR_PUCRC_PU13_Pos) |
| #define | PWR_PUCRC_PU13 PWR_PUCRC_PU13_Msk |
| #define | PWR_PUCRC_PU14_Pos (14U) |
| #define | PWR_PUCRC_PU14_Msk (0x1UL << PWR_PUCRC_PU14_Pos) |
| #define | PWR_PUCRC_PU14 PWR_PUCRC_PU14_Msk |
| #define | PWR_PUCRC_PU15_Pos (15U) |
| #define | PWR_PUCRC_PU15_Msk (0x1UL << PWR_PUCRC_PU15_Pos) |
| #define | PWR_PUCRC_PU15 PWR_PUCRC_PU15_Msk |
| #define | PWR_PDCRC_PD0_Pos (0U) |
| #define | PWR_PDCRC_PD0_Msk (0x1UL << PWR_PDCRC_PD0_Pos) |
| #define | PWR_PDCRC_PD0 PWR_PDCRC_PD0_Msk |
| #define | PWR_PDCRC_PD1_Pos (1U) |
| #define | PWR_PDCRC_PD1_Msk (0x1UL << PWR_PDCRC_PD1_Pos) |
| #define | PWR_PDCRC_PD1 PWR_PDCRC_PD1_Msk |
| #define | PWR_PDCRC_PD2_Pos (2U) |
| #define | PWR_PDCRC_PD2_Msk (0x1UL << PWR_PDCRC_PD2_Pos) |
| #define | PWR_PDCRC_PD2 PWR_PDCRC_PD2_Msk |
| #define | PWR_PDCRC_PD3_Pos (3U) |
| #define | PWR_PDCRC_PD3_Msk (0x1UL << PWR_PDCRC_PD3_Pos) |
| #define | PWR_PDCRC_PD3 PWR_PDCRC_PD3_Msk |
| #define | PWR_PDCRC_PD4_Pos (4U) |
| #define | PWR_PDCRC_PD4_Msk (0x1UL << PWR_PDCRC_PD4_Pos) |
| #define | PWR_PDCRC_PD4 PWR_PDCRC_PD4_Msk |
| #define | PWR_PDCRC_PD5_Pos (5U) |
| #define | PWR_PDCRC_PD5_Msk (0x1UL << PWR_PDCRC_PD5_Pos) |
| #define | PWR_PDCRC_PD5 PWR_PDCRC_PD5_Msk |
| #define | PWR_PDCRC_PD6_Pos (6U) |
| #define | PWR_PDCRC_PD6_Msk (0x1UL << PWR_PDCRC_PD6_Pos) |
| #define | PWR_PDCRC_PD6 PWR_PDCRC_PD6_Msk |
| #define | PWR_PDCRC_PD7_Pos (7U) |
| #define | PWR_PDCRC_PD7_Msk (0x1UL << PWR_PDCRC_PD7_Pos) |
| #define | PWR_PDCRC_PD7 PWR_PDCRC_PD7_Msk |
| #define | PWR_PDCRC_PD8_Pos (8U) |
| #define | PWR_PDCRC_PD8_Msk (0x1UL << PWR_PDCRC_PD8_Pos) |
| #define | PWR_PDCRC_PD8 PWR_PDCRC_PD8_Msk |
| #define | PWR_PDCRC_PD9_Pos (9U) |
| #define | PWR_PDCRC_PD9_Msk (0x1UL << PWR_PDCRC_PD9_Pos) |
| #define | PWR_PDCRC_PD9 PWR_PDCRC_PD9_Msk |
| #define | PWR_PDCRC_PD10_Pos (10U) |
| #define | PWR_PDCRC_PD10_Msk (0x1UL << PWR_PDCRC_PD10_Pos) |
| #define | PWR_PDCRC_PD10 PWR_PDCRC_PD10_Msk |
| #define | PWR_PDCRC_PD11_Pos (11U) |
| #define | PWR_PDCRC_PD11_Msk (0x1UL << PWR_PDCRC_PD11_Pos) |
| #define | PWR_PDCRC_PD11 PWR_PDCRC_PD11_Msk |
| #define | PWR_PDCRC_PD12_Pos (12U) |
| #define | PWR_PDCRC_PD12_Msk (0x1UL << PWR_PDCRC_PD12_Pos) |
| #define | PWR_PDCRC_PD12 PWR_PDCRC_PD12_Msk |
| #define | PWR_PDCRC_PD13_Pos (13U) |
| #define | PWR_PDCRC_PD13_Msk (0x1UL << PWR_PDCRC_PD13_Pos) |
| #define | PWR_PDCRC_PD13 PWR_PDCRC_PD13_Msk |
| #define | PWR_PDCRC_PD14_Pos (14U) |
| #define | PWR_PDCRC_PD14_Msk (0x1UL << PWR_PDCRC_PD14_Pos) |
| #define | PWR_PDCRC_PD14 PWR_PDCRC_PD14_Msk |
| #define | PWR_PDCRC_PD15_Pos (15U) |
| #define | PWR_PDCRC_PD15_Msk (0x1UL << PWR_PDCRC_PD15_Pos) |
| #define | PWR_PDCRC_PD15 PWR_PDCRC_PD15_Msk |
| #define | PWR_PUCRD_PU0_Pos (0U) |
| #define | PWR_PUCRD_PU0_Msk (0x1UL << PWR_PUCRD_PU0_Pos) |
| #define | PWR_PUCRD_PU0 PWR_PUCRD_PU0_Msk |
| #define | PWR_PUCRD_PU1_Pos (1U) |
| #define | PWR_PUCRD_PU1_Msk (0x1UL << PWR_PUCRD_PU1_Pos) |
| #define | PWR_PUCRD_PU1 PWR_PUCRD_PU1_Msk |
| #define | PWR_PUCRD_PU2_Pos (2U) |
| #define | PWR_PUCRD_PU2_Msk (0x1UL << PWR_PUCRD_PU2_Pos) |
| #define | PWR_PUCRD_PU2 PWR_PUCRD_PU2_Msk |
| #define | PWR_PUCRD_PU3_Pos (3U) |
| #define | PWR_PUCRD_PU3_Msk (0x1UL << PWR_PUCRD_PU3_Pos) |
| #define | PWR_PUCRD_PU3 PWR_PUCRD_PU3_Msk |
| #define | PWR_PUCRD_PU4_Pos (4U) |
| #define | PWR_PUCRD_PU4_Msk (0x1UL << PWR_PUCRD_PU4_Pos) |
| #define | PWR_PUCRD_PU4 PWR_PUCRD_PU4_Msk |
| #define | PWR_PUCRD_PU5_Pos (5U) |
| #define | PWR_PUCRD_PU5_Msk (0x1UL << PWR_PUCRD_PU5_Pos) |
| #define | PWR_PUCRD_PU5 PWR_PUCRD_PU5_Msk |
| #define | PWR_PUCRD_PU6_Pos (6U) |
| #define | PWR_PUCRD_PU6_Msk (0x1UL << PWR_PUCRD_PU6_Pos) |
| #define | PWR_PUCRD_PU6 PWR_PUCRD_PU6_Msk |
| #define | PWR_PUCRD_PU7_Pos (7U) |
| #define | PWR_PUCRD_PU7_Msk (0x1UL << PWR_PUCRD_PU7_Pos) |
| #define | PWR_PUCRD_PU7 PWR_PUCRD_PU7_Msk |
| #define | PWR_PUCRD_PU8_Pos (8U) |
| #define | PWR_PUCRD_PU8_Msk (0x1UL << PWR_PUCRD_PU8_Pos) |
| #define | PWR_PUCRD_PU8 PWR_PUCRD_PU8_Msk |
| #define | PWR_PUCRD_PU9_Pos (9U) |
| #define | PWR_PUCRD_PU9_Msk (0x1UL << PWR_PUCRD_PU9_Pos) |
| #define | PWR_PUCRD_PU9 PWR_PUCRD_PU9_Msk |
| #define | PWR_PUCRD_PU10_Pos (10U) |
| #define | PWR_PUCRD_PU10_Msk (0x1UL << PWR_PUCRD_PU10_Pos) |
| #define | PWR_PUCRD_PU10 PWR_PUCRD_PU10_Msk |
| #define | PWR_PUCRD_PU11_Pos (11U) |
| #define | PWR_PUCRD_PU11_Msk (0x1UL << PWR_PUCRD_PU11_Pos) |
| #define | PWR_PUCRD_PU11 PWR_PUCRD_PU11_Msk |
| #define | PWR_PUCRD_PU12_Pos (12U) |
| #define | PWR_PUCRD_PU12_Msk (0x1UL << PWR_PUCRD_PU12_Pos) |
| #define | PWR_PUCRD_PU12 PWR_PUCRD_PU12_Msk |
| #define | PWR_PUCRD_PU13_Pos (13U) |
| #define | PWR_PUCRD_PU13_Msk (0x1UL << PWR_PUCRD_PU13_Pos) |
| #define | PWR_PUCRD_PU13 PWR_PUCRD_PU13_Msk |
| #define | PWR_PUCRD_PU14_Pos (14U) |
| #define | PWR_PUCRD_PU14_Msk (0x1UL << PWR_PUCRD_PU14_Pos) |
| #define | PWR_PUCRD_PU14 PWR_PUCRD_PU14_Msk |
| #define | PWR_PUCRD_PU15_Pos (15U) |
| #define | PWR_PUCRD_PU15_Msk (0x1UL << PWR_PUCRD_PU15_Pos) |
| #define | PWR_PUCRD_PU15 PWR_PUCRD_PU15_Msk |
| #define | PWR_PDCRD_PD0_Pos (0U) |
| #define | PWR_PDCRD_PD0_Msk (0x1UL << PWR_PDCRD_PD0_Pos) |
| #define | PWR_PDCRD_PD0 PWR_PDCRD_PD0_Msk |
| #define | PWR_PDCRD_PD1_Pos (1U) |
| #define | PWR_PDCRD_PD1_Msk (0x1UL << PWR_PDCRD_PD1_Pos) |
| #define | PWR_PDCRD_PD1 PWR_PDCRD_PD1_Msk |
| #define | PWR_PDCRD_PD2_Pos (2U) |
| #define | PWR_PDCRD_PD2_Msk (0x1UL << PWR_PDCRD_PD2_Pos) |
| #define | PWR_PDCRD_PD2 PWR_PDCRD_PD2_Msk |
| #define | PWR_PDCRD_PD3_Pos (3U) |
| #define | PWR_PDCRD_PD3_Msk (0x1UL << PWR_PDCRD_PD3_Pos) |
| #define | PWR_PDCRD_PD3 PWR_PDCRD_PD3_Msk |
| #define | PWR_PDCRD_PD4_Pos (4U) |
| #define | PWR_PDCRD_PD4_Msk (0x1UL << PWR_PDCRD_PD4_Pos) |
| #define | PWR_PDCRD_PD4 PWR_PDCRD_PD4_Msk |
| #define | PWR_PDCRD_PD5_Pos (5U) |
| #define | PWR_PDCRD_PD5_Msk (0x1UL << PWR_PDCRD_PD5_Pos) |
| #define | PWR_PDCRD_PD5 PWR_PDCRD_PD5_Msk |
| #define | PWR_PDCRD_PD6_Pos (6U) |
| #define | PWR_PDCRD_PD6_Msk (0x1UL << PWR_PDCRD_PD6_Pos) |
| #define | PWR_PDCRD_PD6 PWR_PDCRD_PD6_Msk |
| #define | PWR_PDCRD_PD7_Pos (7U) |
| #define | PWR_PDCRD_PD7_Msk (0x1UL << PWR_PDCRD_PD7_Pos) |
| #define | PWR_PDCRD_PD7 PWR_PDCRD_PD7_Msk |
| #define | PWR_PDCRD_PD8_Pos (8U) |
| #define | PWR_PDCRD_PD8_Msk (0x1UL << PWR_PDCRD_PD8_Pos) |
| #define | PWR_PDCRD_PD8 PWR_PDCRD_PD8_Msk |
| #define | PWR_PDCRD_PD9_Pos (9U) |
| #define | PWR_PDCRD_PD9_Msk (0x1UL << PWR_PDCRD_PD9_Pos) |
| #define | PWR_PDCRD_PD9 PWR_PDCRD_PD9_Msk |
| #define | PWR_PDCRD_PD10_Pos (10U) |
| #define | PWR_PDCRD_PD10_Msk (0x1UL << PWR_PDCRD_PD10_Pos) |
| #define | PWR_PDCRD_PD10 PWR_PDCRD_PD10_Msk |
| #define | PWR_PDCRD_PD11_Pos (11U) |
| #define | PWR_PDCRD_PD11_Msk (0x1UL << PWR_PDCRD_PD11_Pos) |
| #define | PWR_PDCRD_PD11 PWR_PDCRD_PD11_Msk |
| #define | PWR_PDCRD_PD12_Pos (12U) |
| #define | PWR_PDCRD_PD12_Msk (0x1UL << PWR_PDCRD_PD12_Pos) |
| #define | PWR_PDCRD_PD12 PWR_PDCRD_PD12_Msk |
| #define | PWR_PDCRD_PD13_Pos (13U) |
| #define | PWR_PDCRD_PD13_Msk (0x1UL << PWR_PDCRD_PD13_Pos) |
| #define | PWR_PDCRD_PD13 PWR_PDCRD_PD13_Msk |
| #define | PWR_PDCRD_PD14_Pos (14U) |
| #define | PWR_PDCRD_PD14_Msk (0x1UL << PWR_PDCRD_PD14_Pos) |
| #define | PWR_PDCRD_PD14 PWR_PDCRD_PD14_Msk |
| #define | PWR_PDCRD_PD15_Pos (15U) |
| #define | PWR_PDCRD_PD15_Msk (0x1UL << PWR_PDCRD_PD15_Pos) |
| #define | PWR_PDCRD_PD15 PWR_PDCRD_PD15_Msk |
| #define | PWR_PUCRE_PU0_Pos (0U) |
| #define | PWR_PUCRE_PU0_Msk (0x1UL << PWR_PUCRE_PU0_Pos) |
| #define | PWR_PUCRE_PU0 PWR_PUCRE_PU0_Msk |
| #define | PWR_PUCRE_PU1_Pos (1U) |
| #define | PWR_PUCRE_PU1_Msk (0x1UL << PWR_PUCRE_PU1_Pos) |
| #define | PWR_PUCRE_PU1 PWR_PUCRE_PU1_Msk |
| #define | PWR_PUCRE_PU2_Pos (2U) |
| #define | PWR_PUCRE_PU2_Msk (0x1UL << PWR_PUCRE_PU2_Pos) |
| #define | PWR_PUCRE_PU2 PWR_PUCRE_PU2_Msk |
| #define | PWR_PUCRE_PU3_Pos (3U) |
| #define | PWR_PUCRE_PU3_Msk (0x1UL << PWR_PUCRE_PU3_Pos) |
| #define | PWR_PUCRE_PU3 PWR_PUCRE_PU3_Msk |
| #define | PWR_PUCRE_PU4_Pos (4U) |
| #define | PWR_PUCRE_PU4_Msk (0x1UL << PWR_PUCRE_PU4_Pos) |
| #define | PWR_PUCRE_PU4 PWR_PUCRE_PU4_Msk |
| #define | PWR_PUCRE_PU5_Pos (5U) |
| #define | PWR_PUCRE_PU5_Msk (0x1UL << PWR_PUCRE_PU5_Pos) |
| #define | PWR_PUCRE_PU5 PWR_PUCRE_PU5_Msk |
| #define | PWR_PUCRE_PU6_Pos (6U) |
| #define | PWR_PUCRE_PU6_Msk (0x1UL << PWR_PUCRE_PU6_Pos) |
| #define | PWR_PUCRE_PU6 PWR_PUCRE_PU6_Msk |
| #define | PWR_PUCRE_PU7_Pos (7U) |
| #define | PWR_PUCRE_PU7_Msk (0x1UL << PWR_PUCRE_PU7_Pos) |
| #define | PWR_PUCRE_PU7 PWR_PUCRE_PU7_Msk |
| #define | PWR_PUCRE_PU8_Pos (8U) |
| #define | PWR_PUCRE_PU8_Msk (0x1UL << PWR_PUCRE_PU8_Pos) |
| #define | PWR_PUCRE_PU8 PWR_PUCRE_PU8_Msk |
| #define | PWR_PUCRE_PU9_Pos (9U) |
| #define | PWR_PUCRE_PU9_Msk (0x1UL << PWR_PUCRE_PU9_Pos) |
| #define | PWR_PUCRE_PU9 PWR_PUCRE_PU9_Msk |
| #define | PWR_PUCRE_PU10_Pos (10U) |
| #define | PWR_PUCRE_PU10_Msk (0x1UL << PWR_PUCRE_PU10_Pos) |
| #define | PWR_PUCRE_PU10 PWR_PUCRE_PU10_Msk |
| #define | PWR_PUCRE_PU11_Pos (11U) |
| #define | PWR_PUCRE_PU11_Msk (0x1UL << PWR_PUCRE_PU11_Pos) |
| #define | PWR_PUCRE_PU11 PWR_PUCRE_PU11_Msk |
| #define | PWR_PUCRE_PU12_Pos (12U) |
| #define | PWR_PUCRE_PU12_Msk (0x1UL << PWR_PUCRE_PU12_Pos) |
| #define | PWR_PUCRE_PU12 PWR_PUCRE_PU12_Msk |
| #define | PWR_PUCRE_PU13_Pos (13U) |
| #define | PWR_PUCRE_PU13_Msk (0x1UL << PWR_PUCRE_PU13_Pos) |
| #define | PWR_PUCRE_PU13 PWR_PUCRE_PU13_Msk |
| #define | PWR_PUCRE_PU14_Pos (14U) |
| #define | PWR_PUCRE_PU14_Msk (0x1UL << PWR_PUCRE_PU14_Pos) |
| #define | PWR_PUCRE_PU14 PWR_PUCRE_PU14_Msk |
| #define | PWR_PUCRE_PU15_Pos (15U) |
| #define | PWR_PUCRE_PU15_Msk (0x1UL << PWR_PUCRE_PU15_Pos) |
| #define | PWR_PUCRE_PU15 PWR_PUCRE_PU15_Msk |
| #define | PWR_PDCRE_PD0_Pos (0U) |
| #define | PWR_PDCRE_PD0_Msk (0x1UL << PWR_PDCRE_PD0_Pos) |
| #define | PWR_PDCRE_PD0 PWR_PDCRE_PD0_Msk |
| #define | PWR_PDCRE_PD1_Pos (1U) |
| #define | PWR_PDCRE_PD1_Msk (0x1UL << PWR_PDCRE_PD1_Pos) |
| #define | PWR_PDCRE_PD1 PWR_PDCRE_PD1_Msk |
| #define | PWR_PDCRE_PD2_Pos (2U) |
| #define | PWR_PDCRE_PD2_Msk (0x1UL << PWR_PDCRE_PD2_Pos) |
| #define | PWR_PDCRE_PD2 PWR_PDCRE_PD2_Msk |
| #define | PWR_PDCRE_PD3_Pos (3U) |
| #define | PWR_PDCRE_PD3_Msk (0x1UL << PWR_PDCRE_PD3_Pos) |
| #define | PWR_PDCRE_PD3 PWR_PDCRE_PD3_Msk |
| #define | PWR_PDCRE_PD4_Pos (4U) |
| #define | PWR_PDCRE_PD4_Msk (0x1UL << PWR_PDCRE_PD4_Pos) |
| #define | PWR_PDCRE_PD4 PWR_PDCRE_PD4_Msk |
| #define | PWR_PDCRE_PD5_Pos (5U) |
| #define | PWR_PDCRE_PD5_Msk (0x1UL << PWR_PDCRE_PD5_Pos) |
| #define | PWR_PDCRE_PD5 PWR_PDCRE_PD5_Msk |
| #define | PWR_PDCRE_PD6_Pos (6U) |
| #define | PWR_PDCRE_PD6_Msk (0x1UL << PWR_PDCRE_PD6_Pos) |
| #define | PWR_PDCRE_PD6 PWR_PDCRE_PD6_Msk |
| #define | PWR_PDCRE_PD7_Pos (7U) |
| #define | PWR_PDCRE_PD7_Msk (0x1UL << PWR_PDCRE_PD7_Pos) |
| #define | PWR_PDCRE_PD7 PWR_PDCRE_PD7_Msk |
| #define | PWR_PDCRE_PD8_Pos (8U) |
| #define | PWR_PDCRE_PD8_Msk (0x1UL << PWR_PDCRE_PD8_Pos) |
| #define | PWR_PDCRE_PD8 PWR_PDCRE_PD8_Msk |
| #define | PWR_PDCRE_PD9_Pos (9U) |
| #define | PWR_PDCRE_PD9_Msk (0x1UL << PWR_PDCRE_PD9_Pos) |
| #define | PWR_PDCRE_PD9 PWR_PDCRE_PD9_Msk |
| #define | PWR_PDCRE_PD10_Pos (10U) |
| #define | PWR_PDCRE_PD10_Msk (0x1UL << PWR_PDCRE_PD10_Pos) |
| #define | PWR_PDCRE_PD10 PWR_PDCRE_PD10_Msk |
| #define | PWR_PDCRE_PD11_Pos (11U) |
| #define | PWR_PDCRE_PD11_Msk (0x1UL << PWR_PDCRE_PD11_Pos) |
| #define | PWR_PDCRE_PD11 PWR_PDCRE_PD11_Msk |
| #define | PWR_PDCRE_PD12_Pos (12U) |
| #define | PWR_PDCRE_PD12_Msk (0x1UL << PWR_PDCRE_PD12_Pos) |
| #define | PWR_PDCRE_PD12 PWR_PDCRE_PD12_Msk |
| #define | PWR_PDCRE_PD13_Pos (13U) |
| #define | PWR_PDCRE_PD13_Msk (0x1UL << PWR_PDCRE_PD13_Pos) |
| #define | PWR_PDCRE_PD13 PWR_PDCRE_PD13_Msk |
| #define | PWR_PDCRE_PD14_Pos (14U) |
| #define | PWR_PDCRE_PD14_Msk (0x1UL << PWR_PDCRE_PD14_Pos) |
| #define | PWR_PDCRE_PD14 PWR_PDCRE_PD14_Msk |
| #define | PWR_PDCRE_PD15_Pos (15U) |
| #define | PWR_PDCRE_PD15_Msk (0x1UL << PWR_PDCRE_PD15_Pos) |
| #define | PWR_PDCRE_PD15 PWR_PDCRE_PD15_Msk |
| #define | PWR_PUCRF_PU0_Pos (0U) |
| #define | PWR_PUCRF_PU0_Msk (0x1UL << PWR_PUCRF_PU0_Pos) |
| #define | PWR_PUCRF_PU0 PWR_PUCRF_PU0_Msk |
| #define | PWR_PUCRF_PU1_Pos (1U) |
| #define | PWR_PUCRF_PU1_Msk (0x1UL << PWR_PUCRF_PU1_Pos) |
| #define | PWR_PUCRF_PU1 PWR_PUCRF_PU1_Msk |
| #define | PWR_PUCRF_PU2_Pos (2U) |
| #define | PWR_PUCRF_PU2_Msk (0x1UL << PWR_PUCRF_PU2_Pos) |
| #define | PWR_PUCRF_PU2 PWR_PUCRF_PU2_Msk |
| #define | PWR_PUCRF_PU3_Pos (3U) |
| #define | PWR_PUCRF_PU3_Msk (0x1UL << PWR_PUCRF_PU3_Pos) |
| #define | PWR_PUCRF_PU3 PWR_PUCRF_PU3_Msk |
| #define | PWR_PUCRF_PU4_Pos (4U) |
| #define | PWR_PUCRF_PU4_Msk (0x1UL << PWR_PUCRF_PU4_Pos) |
| #define | PWR_PUCRF_PU4 PWR_PUCRF_PU4_Msk |
| #define | PWR_PUCRF_PU5_Pos (5U) |
| #define | PWR_PUCRF_PU5_Msk (0x1UL << PWR_PUCRF_PU5_Pos) |
| #define | PWR_PUCRF_PU5 PWR_PUCRF_PU5_Msk |
| #define | PWR_PUCRF_PU6_Pos (6U) |
| #define | PWR_PUCRF_PU6_Msk (0x1UL << PWR_PUCRF_PU6_Pos) |
| #define | PWR_PUCRF_PU6 PWR_PUCRF_PU6_Msk |
| #define | PWR_PUCRF_PU7_Pos (7U) |
| #define | PWR_PUCRF_PU7_Msk (0x1UL << PWR_PUCRF_PU7_Pos) |
| #define | PWR_PUCRF_PU7 PWR_PUCRF_PU7_Msk |
| #define | PWR_PUCRF_PU8_Pos (8U) |
| #define | PWR_PUCRF_PU8_Msk (0x1UL << PWR_PUCRF_PU8_Pos) |
| #define | PWR_PUCRF_PU8 PWR_PUCRF_PU8_Msk |
| #define | PWR_PUCRF_PU9_Pos (9U) |
| #define | PWR_PUCRF_PU9_Msk (0x1UL << PWR_PUCRF_PU9_Pos) |
| #define | PWR_PUCRF_PU9 PWR_PUCRF_PU9_Msk |
| #define | PWR_PUCRF_PU10_Pos (10U) |
| #define | PWR_PUCRF_PU10_Msk (0x1UL << PWR_PUCRF_PU10_Pos) |
| #define | PWR_PUCRF_PU10 PWR_PUCRF_PU10_Msk |
| #define | PWR_PUCRF_PU11_Pos (11U) |
| #define | PWR_PUCRF_PU11_Msk (0x1UL << PWR_PUCRF_PU11_Pos) |
| #define | PWR_PUCRF_PU11 PWR_PUCRF_PU11_Msk |
| #define | PWR_PUCRF_PU12_Pos (12U) |
| #define | PWR_PUCRF_PU12_Msk (0x1UL << PWR_PUCRF_PU12_Pos) |
| #define | PWR_PUCRF_PU12 PWR_PUCRF_PU12_Msk |
| #define | PWR_PUCRF_PU13_Pos (13U) |
| #define | PWR_PUCRF_PU13_Msk (0x1UL << PWR_PUCRF_PU13_Pos) |
| #define | PWR_PUCRF_PU13 PWR_PUCRF_PU13_Msk |
| #define | PWR_PUCRF_PU14_Pos (14U) |
| #define | PWR_PUCRF_PU14_Msk (0x1UL << PWR_PUCRF_PU14_Pos) |
| #define | PWR_PUCRF_PU14 PWR_PUCRF_PU14_Msk |
| #define | PWR_PUCRF_PU15_Pos (15U) |
| #define | PWR_PUCRF_PU15_Msk (0x1UL << PWR_PUCRF_PU15_Pos) |
| #define | PWR_PUCRF_PU15 PWR_PUCRF_PU15_Msk |
| #define | PWR_PDCRF_PD0_Pos (0U) |
| #define | PWR_PDCRF_PD0_Msk (0x1UL << PWR_PDCRF_PD0_Pos) |
| #define | PWR_PDCRF_PD0 PWR_PDCRF_PD0_Msk |
| #define | PWR_PDCRF_PD1_Pos (1U) |
| #define | PWR_PDCRF_PD1_Msk (0x1UL << PWR_PDCRF_PD1_Pos) |
| #define | PWR_PDCRF_PD1 PWR_PDCRF_PD1_Msk |
| #define | PWR_PDCRF_PD2_Pos (2U) |
| #define | PWR_PDCRF_PD2_Msk (0x1UL << PWR_PDCRF_PD2_Pos) |
| #define | PWR_PDCRF_PD2 PWR_PDCRF_PD2_Msk |
| #define | PWR_PDCRF_PD3_Pos (3U) |
| #define | PWR_PDCRF_PD3_Msk (0x1UL << PWR_PDCRF_PD3_Pos) |
| #define | PWR_PDCRF_PD3 PWR_PDCRF_PD3_Msk |
| #define | PWR_PDCRF_PD4_Pos (4U) |
| #define | PWR_PDCRF_PD4_Msk (0x1UL << PWR_PDCRF_PD4_Pos) |
| #define | PWR_PDCRF_PD4 PWR_PDCRF_PD4_Msk |
| #define | PWR_PDCRF_PD5_Pos (5U) |
| #define | PWR_PDCRF_PD5_Msk (0x1UL << PWR_PDCRF_PD5_Pos) |
| #define | PWR_PDCRF_PD5 PWR_PDCRF_PD5_Msk |
| #define | PWR_PDCRF_PD6_Pos (6U) |
| #define | PWR_PDCRF_PD6_Msk (0x1UL << PWR_PDCRF_PD6_Pos) |
| #define | PWR_PDCRF_PD6 PWR_PDCRF_PD6_Msk |
| #define | PWR_PDCRF_PD7_Pos (7U) |
| #define | PWR_PDCRF_PD7_Msk (0x1UL << PWR_PDCRF_PD7_Pos) |
| #define | PWR_PDCRF_PD7 PWR_PDCRF_PD7_Msk |
| #define | PWR_PDCRF_PD8_Pos (8U) |
| #define | PWR_PDCRF_PD8_Msk (0x1UL << PWR_PDCRF_PD8_Pos) |
| #define | PWR_PDCRF_PD8 PWR_PDCRF_PD8_Msk |
| #define | PWR_PDCRF_PD9_Pos (9U) |
| #define | PWR_PDCRF_PD9_Msk (0x1UL << PWR_PDCRF_PD9_Pos) |
| #define | PWR_PDCRF_PD9 PWR_PDCRF_PD9_Msk |
| #define | PWR_PDCRF_PD10_Pos (10U) |
| #define | PWR_PDCRF_PD10_Msk (0x1UL << PWR_PDCRF_PD10_Pos) |
| #define | PWR_PDCRF_PD10 PWR_PDCRF_PD10_Msk |
| #define | PWR_PDCRF_PD11_Pos (11U) |
| #define | PWR_PDCRF_PD11_Msk (0x1UL << PWR_PDCRF_PD11_Pos) |
| #define | PWR_PDCRF_PD11 PWR_PDCRF_PD11_Msk |
| #define | PWR_PDCRF_PD12_Pos (12U) |
| #define | PWR_PDCRF_PD12_Msk (0x1UL << PWR_PDCRF_PD12_Pos) |
| #define | PWR_PDCRF_PD12 PWR_PDCRF_PD12_Msk |
| #define | PWR_PDCRF_PD13_Pos (13U) |
| #define | PWR_PDCRF_PD13_Msk (0x1UL << PWR_PDCRF_PD13_Pos) |
| #define | PWR_PDCRF_PD13 PWR_PDCRF_PD13_Msk |
| #define | PWR_PDCRF_PD14_Pos (14U) |
| #define | PWR_PDCRF_PD14_Msk (0x1UL << PWR_PDCRF_PD14_Pos) |
| #define | PWR_PDCRF_PD14 PWR_PDCRF_PD14_Msk |
| #define | PWR_PDCRF_PD15_Pos (15U) |
| #define | PWR_PDCRF_PD15_Msk (0x1UL << PWR_PDCRF_PD15_Pos) |
| #define | PWR_PDCRF_PD15 PWR_PDCRF_PD15_Msk |
| #define | PWR_PUCRG_PU0_Pos (0U) |
| #define | PWR_PUCRG_PU0_Msk (0x1UL << PWR_PUCRG_PU0_Pos) |
| #define | PWR_PUCRG_PU0 PWR_PUCRG_PU0_Msk |
| #define | PWR_PUCRG_PU1_Pos (1U) |
| #define | PWR_PUCRG_PU1_Msk (0x1UL << PWR_PUCRG_PU1_Pos) |
| #define | PWR_PUCRG_PU1 PWR_PUCRG_PU1_Msk |
| #define | PWR_PUCRG_PU2_Pos (2U) |
| #define | PWR_PUCRG_PU2_Msk (0x1UL << PWR_PUCRG_PU2_Pos) |
| #define | PWR_PUCRG_PU2 PWR_PUCRG_PU2_Msk |
| #define | PWR_PUCRG_PU3_Pos (3U) |
| #define | PWR_PUCRG_PU3_Msk (0x1UL << PWR_PUCRG_PU3_Pos) |
| #define | PWR_PUCRG_PU3 PWR_PUCRG_PU3_Msk |
| #define | PWR_PUCRG_PU4_Pos (4U) |
| #define | PWR_PUCRG_PU4_Msk (0x1UL << PWR_PUCRG_PU4_Pos) |
| #define | PWR_PUCRG_PU4 PWR_PUCRG_PU4_Msk |
| #define | PWR_PUCRG_PU5_Pos (5U) |
| #define | PWR_PUCRG_PU5_Msk (0x1UL << PWR_PUCRG_PU5_Pos) |
| #define | PWR_PUCRG_PU5 PWR_PUCRG_PU5_Msk |
| #define | PWR_PUCRG_PU6_Pos (6U) |
| #define | PWR_PUCRG_PU6_Msk (0x1UL << PWR_PUCRG_PU6_Pos) |
| #define | PWR_PUCRG_PU6 PWR_PUCRG_PU6_Msk |
| #define | PWR_PUCRG_PU7_Pos (7U) |
| #define | PWR_PUCRG_PU7_Msk (0x1UL << PWR_PUCRG_PU7_Pos) |
| #define | PWR_PUCRG_PU7 PWR_PUCRG_PU7_Msk |
| #define | PWR_PUCRG_PU8_Pos (8U) |
| #define | PWR_PUCRG_PU8_Msk (0x1UL << PWR_PUCRG_PU8_Pos) |
| #define | PWR_PUCRG_PU8 PWR_PUCRG_PU8_Msk |
| #define | PWR_PUCRG_PU9_Pos (9U) |
| #define | PWR_PUCRG_PU9_Msk (0x1UL << PWR_PUCRG_PU9_Pos) |
| #define | PWR_PUCRG_PU9 PWR_PUCRG_PU9_Msk |
| #define | PWR_PUCRG_PU10_Pos (10U) |
| #define | PWR_PUCRG_PU10_Msk (0x1UL << PWR_PUCRG_PU10_Pos) |
| #define | PWR_PUCRG_PU10 PWR_PUCRG_PU10_Msk |
| #define | PWR_PUCRG_PU11_Pos (11U) |
| #define | PWR_PUCRG_PU11_Msk (0x1UL << PWR_PUCRG_PU11_Pos) |
| #define | PWR_PUCRG_PU11 PWR_PUCRG_PU11_Msk |
| #define | PWR_PUCRG_PU12_Pos (12U) |
| #define | PWR_PUCRG_PU12_Msk (0x1UL << PWR_PUCRG_PU12_Pos) |
| #define | PWR_PUCRG_PU12 PWR_PUCRG_PU12_Msk |
| #define | PWR_PUCRG_PU13_Pos (13U) |
| #define | PWR_PUCRG_PU13_Msk (0x1UL << PWR_PUCRG_PU13_Pos) |
| #define | PWR_PUCRG_PU13 PWR_PUCRG_PU13_Msk |
| #define | PWR_PUCRG_PU14_Pos (14U) |
| #define | PWR_PUCRG_PU14_Msk (0x1UL << PWR_PUCRG_PU14_Pos) |
| #define | PWR_PUCRG_PU14 PWR_PUCRG_PU14_Msk |
| #define | PWR_PUCRG_PU15_Pos (15U) |
| #define | PWR_PUCRG_PU15_Msk (0x1UL << PWR_PUCRG_PU15_Pos) |
| #define | PWR_PUCRG_PU15 PWR_PUCRG_PU15_Msk |
| #define | PWR_PDCRG_PD0_Pos (0U) |
| #define | PWR_PDCRG_PD0_Msk (0x1UL << PWR_PDCRG_PD0_Pos) |
| #define | PWR_PDCRG_PD0 PWR_PDCRG_PD0_Msk |
| #define | PWR_PDCRG_PD1_Pos (1U) |
| #define | PWR_PDCRG_PD1_Msk (0x1UL << PWR_PDCRG_PD1_Pos) |
| #define | PWR_PDCRG_PD1 PWR_PDCRG_PD1_Msk |
| #define | PWR_PDCRG_PD2_Pos (2U) |
| #define | PWR_PDCRG_PD2_Msk (0x1UL << PWR_PDCRG_PD2_Pos) |
| #define | PWR_PDCRG_PD2 PWR_PDCRG_PD2_Msk |
| #define | PWR_PDCRG_PD3_Pos (3U) |
| #define | PWR_PDCRG_PD3_Msk (0x1UL << PWR_PDCRG_PD3_Pos) |
| #define | PWR_PDCRG_PD3 PWR_PDCRG_PD3_Msk |
| #define | PWR_PDCRG_PD4_Pos (4U) |
| #define | PWR_PDCRG_PD4_Msk (0x1UL << PWR_PDCRG_PD4_Pos) |
| #define | PWR_PDCRG_PD4 PWR_PDCRG_PD4_Msk |
| #define | PWR_PDCRG_PD5_Pos (5U) |
| #define | PWR_PDCRG_PD5_Msk (0x1UL << PWR_PDCRG_PD5_Pos) |
| #define | PWR_PDCRG_PD5 PWR_PDCRG_PD5_Msk |
| #define | PWR_PDCRG_PD6_Pos (6U) |
| #define | PWR_PDCRG_PD6_Msk (0x1UL << PWR_PDCRG_PD6_Pos) |
| #define | PWR_PDCRG_PD6 PWR_PDCRG_PD6_Msk |
| #define | PWR_PDCRG_PD7_Pos (7U) |
| #define | PWR_PDCRG_PD7_Msk (0x1UL << PWR_PDCRG_PD7_Pos) |
| #define | PWR_PDCRG_PD7 PWR_PDCRG_PD7_Msk |
| #define | PWR_PDCRG_PD8_Pos (8U) |
| #define | PWR_PDCRG_PD8_Msk (0x1UL << PWR_PDCRG_PD8_Pos) |
| #define | PWR_PDCRG_PD8 PWR_PDCRG_PD8_Msk |
| #define | PWR_PDCRG_PD9_Pos (9U) |
| #define | PWR_PDCRG_PD9_Msk (0x1UL << PWR_PDCRG_PD9_Pos) |
| #define | PWR_PDCRG_PD9 PWR_PDCRG_PD9_Msk |
| #define | PWR_PDCRG_PD10_Pos (10U) |
| #define | PWR_PDCRG_PD10_Msk (0x1UL << PWR_PDCRG_PD10_Pos) |
| #define | PWR_PDCRG_PD10 PWR_PDCRG_PD10_Msk |
| #define | PWR_PDCRG_PD11_Pos (11U) |
| #define | PWR_PDCRG_PD11_Msk (0x1UL << PWR_PDCRG_PD11_Pos) |
| #define | PWR_PDCRG_PD11 PWR_PDCRG_PD11_Msk |
| #define | PWR_PDCRG_PD12_Pos (12U) |
| #define | PWR_PDCRG_PD12_Msk (0x1UL << PWR_PDCRG_PD12_Pos) |
| #define | PWR_PDCRG_PD12 PWR_PDCRG_PD12_Msk |
| #define | PWR_PDCRG_PD13_Pos (13U) |
| #define | PWR_PDCRG_PD13_Msk (0x1UL << PWR_PDCRG_PD13_Pos) |
| #define | PWR_PDCRG_PD13 PWR_PDCRG_PD13_Msk |
| #define | PWR_PDCRG_PD14_Pos (14U) |
| #define | PWR_PDCRG_PD14_Msk (0x1UL << PWR_PDCRG_PD14_Pos) |
| #define | PWR_PDCRG_PD14 PWR_PDCRG_PD14_Msk |
| #define | PWR_PDCRG_PD15_Pos (15U) |
| #define | PWR_PDCRG_PD15_Msk (0x1UL << PWR_PDCRG_PD15_Pos) |
| #define | PWR_PDCRG_PD15 PWR_PDCRG_PD15_Msk |
| #define | PWR_PUCRH_PU0_Pos (0U) |
| #define | PWR_PUCRH_PU0_Msk (0x1UL << PWR_PUCRH_PU0_Pos) |
| #define | PWR_PUCRH_PU0 PWR_PUCRH_PU0_Msk |
| #define | PWR_PUCRH_PU1_Pos (1U) |
| #define | PWR_PUCRH_PU1_Msk (0x1UL << PWR_PUCRH_PU1_Pos) |
| #define | PWR_PUCRH_PU1 PWR_PUCRH_PU1_Msk |
| #define | PWR_PUCRH_PU2_Pos (2U) |
| #define | PWR_PUCRH_PU2_Msk (0x1UL << PWR_PUCRH_PU2_Pos) |
| #define | PWR_PUCRH_PU2 PWR_PUCRH_PU2_Msk |
| #define | PWR_PUCRH_PU3_Pos (3U) |
| #define | PWR_PUCRH_PU3_Msk (0x1UL << PWR_PUCRH_PU3_Pos) |
| #define | PWR_PUCRH_PU3 PWR_PUCRH_PU3_Msk |
| #define | PWR_PUCRH_PU4_Pos (4U) |
| #define | PWR_PUCRH_PU4_Msk (0x1UL << PWR_PUCRH_PU4_Pos) |
| #define | PWR_PUCRH_PU4 PWR_PUCRH_PU4_Msk |
| #define | PWR_PUCRH_PU5_Pos (5U) |
| #define | PWR_PUCRH_PU5_Msk (0x1UL << PWR_PUCRH_PU5_Pos) |
| #define | PWR_PUCRH_PU5 PWR_PUCRH_PU5_Msk |
| #define | PWR_PUCRH_PU6_Pos (6U) |
| #define | PWR_PUCRH_PU6_Msk (0x1UL << PWR_PUCRH_PU6_Pos) |
| #define | PWR_PUCRH_PU6 PWR_PUCRH_PU6_Msk |
| #define | PWR_PUCRH_PU7_Pos (7U) |
| #define | PWR_PUCRH_PU7_Msk (0x1UL << PWR_PUCRH_PU7_Pos) |
| #define | PWR_PUCRH_PU7 PWR_PUCRH_PU7_Msk |
| #define | PWR_PUCRH_PU8_Pos (8U) |
| #define | PWR_PUCRH_PU8_Msk (0x1UL << PWR_PUCRH_PU8_Pos) |
| #define | PWR_PUCRH_PU8 PWR_PUCRH_PU8_Msk |
| #define | PWR_PUCRH_PU9_Pos (9U) |
| #define | PWR_PUCRH_PU9_Msk (0x1UL << PWR_PUCRH_PU9_Pos) |
| #define | PWR_PUCRH_PU9 PWR_PUCRH_PU9_Msk |
| #define | PWR_PUCRH_PU10_Pos (10U) |
| #define | PWR_PUCRH_PU10_Msk (0x1UL << PWR_PUCRH_PU10_Pos) |
| #define | PWR_PUCRH_PU10 PWR_PUCRH_PU10_Msk |
| #define | PWR_PUCRH_PU11_Pos (11U) |
| #define | PWR_PUCRH_PU11_Msk (0x1UL << PWR_PUCRH_PU11_Pos) |
| #define | PWR_PUCRH_PU11 PWR_PUCRH_PU11_Msk |
| #define | PWR_PUCRH_PU12_Pos (12U) |
| #define | PWR_PUCRH_PU12_Msk (0x1UL << PWR_PUCRH_PU12_Pos) |
| #define | PWR_PUCRH_PU12 PWR_PUCRH_PU12_Msk |
| #define | PWR_PUCRH_PU13_Pos (13U) |
| #define | PWR_PUCRH_PU13_Msk (0x1UL << PWR_PUCRH_PU13_Pos) |
| #define | PWR_PUCRH_PU13 PWR_PUCRH_PU13_Msk |
| #define | PWR_PUCRH_PU14_Pos (14U) |
| #define | PWR_PUCRH_PU14_Msk (0x1UL << PWR_PUCRH_PU14_Pos) |
| #define | PWR_PUCRH_PU14 PWR_PUCRH_PU14_Msk |
| #define | PWR_PUCRH_PU15_Pos (15U) |
| #define | PWR_PUCRH_PU15_Msk (0x1UL << PWR_PUCRH_PU15_Pos) |
| #define | PWR_PUCRH_PU15 PWR_PUCRH_PU15_Msk |
| #define | PWR_PDCRH_PD0_Pos (0U) |
| #define | PWR_PDCRH_PD0_Msk (0x1UL << PWR_PDCRH_PD0_Pos) |
| #define | PWR_PDCRH_PD0 PWR_PDCRH_PD0_Msk |
| #define | PWR_PDCRH_PD1_Pos (1U) |
| #define | PWR_PDCRH_PD1_Msk (0x1UL << PWR_PDCRH_PD1_Pos) |
| #define | PWR_PDCRH_PD1 PWR_PDCRH_PD1_Msk |
| #define | PWR_PDCRH_PD2_Pos (2U) |
| #define | PWR_PDCRH_PD2_Msk (0x1UL << PWR_PDCRH_PD2_Pos) |
| #define | PWR_PDCRH_PD2 PWR_PDCRH_PD2_Msk |
| #define | PWR_PDCRH_PD3_Pos (3U) |
| #define | PWR_PDCRH_PD3_Msk (0x1UL << PWR_PDCRH_PD3_Pos) |
| #define | PWR_PDCRH_PD3 PWR_PDCRH_PD3_Msk |
| #define | PWR_PDCRH_PD4_Pos (4U) |
| #define | PWR_PDCRH_PD4_Msk (0x1UL << PWR_PDCRH_PD4_Pos) |
| #define | PWR_PDCRH_PD4 PWR_PDCRH_PD4_Msk |
| #define | PWR_PDCRH_PD5_Pos (5U) |
| #define | PWR_PDCRH_PD5_Msk (0x1UL << PWR_PDCRH_PD5_Pos) |
| #define | PWR_PDCRH_PD5 PWR_PDCRH_PD5_Msk |
| #define | PWR_PDCRH_PD6_Pos (6U) |
| #define | PWR_PDCRH_PD6_Msk (0x1UL << PWR_PDCRH_PD6_Pos) |
| #define | PWR_PDCRH_PD6 PWR_PDCRH_PD6_Msk |
| #define | PWR_PDCRH_PD7_Pos (7U) |
| #define | PWR_PDCRH_PD7_Msk (0x1UL << PWR_PDCRH_PD7_Pos) |
| #define | PWR_PDCRH_PD7 PWR_PDCRH_PD7_Msk |
| #define | PWR_PDCRH_PD8_Pos (8U) |
| #define | PWR_PDCRH_PD8_Msk (0x1UL << PWR_PDCRH_PD8_Pos) |
| #define | PWR_PDCRH_PD8 PWR_PDCRH_PD8_Msk |
| #define | PWR_PDCRH_PD9_Pos (9U) |
| #define | PWR_PDCRH_PD9_Msk (0x1UL << PWR_PDCRH_PD9_Pos) |
| #define | PWR_PDCRH_PD9 PWR_PDCRH_PD9_Msk |
| #define | PWR_PDCRH_PD10_Pos (10U) |
| #define | PWR_PDCRH_PD10_Msk (0x1UL << PWR_PDCRH_PD10_Pos) |
| #define | PWR_PDCRH_PD10 PWR_PDCRH_PD10_Msk |
| #define | PWR_PDCRH_PD11_Pos (11U) |
| #define | PWR_PDCRH_PD11_Msk (0x1UL << PWR_PDCRH_PD11_Pos) |
| #define | PWR_PDCRH_PD11 PWR_PDCRH_PD11_Msk |
| #define | PWR_PDCRH_PD12_Pos (12U) |
| #define | PWR_PDCRH_PD12_Msk (0x1UL << PWR_PDCRH_PD12_Pos) |
| #define | PWR_PDCRH_PD12 PWR_PDCRH_PD12_Msk |
| #define | PWR_PDCRH_PD13_Pos (13U) |
| #define | PWR_PDCRH_PD13_Msk (0x1UL << PWR_PDCRH_PD13_Pos) |
| #define | PWR_PDCRH_PD13 PWR_PDCRH_PD13_Msk |
| #define | PWR_PDCRH_PD14_Pos (14U) |
| #define | PWR_PDCRH_PD14_Msk (0x1UL << PWR_PDCRH_PD14_Pos) |
| #define | PWR_PDCRH_PD14 PWR_PDCRH_PD14_Msk |
| #define | PWR_PDCRH_PD15_Pos (15U) |
| #define | PWR_PDCRH_PD15_Msk (0x1UL << PWR_PDCRH_PD15_Pos) |
| #define | PWR_PDCRH_PD15 PWR_PDCRH_PD15_Msk |
| #define | PWR_PUCRI_PU0_Pos (0U) |
| #define | PWR_PUCRI_PU0_Msk (0x1UL << PWR_PUCRI_PU0_Pos) |
| #define | PWR_PUCRI_PU0 PWR_PUCRI_PU0_Msk |
| #define | PWR_PUCRI_PU1_Pos (1U) |
| #define | PWR_PUCRI_PU1_Msk (0x1UL << PWR_PUCRI_PU1_Pos) |
| #define | PWR_PUCRI_PU1 PWR_PUCRI_PU1_Msk |
| #define | PWR_PUCRI_PU2_Pos (2U) |
| #define | PWR_PUCRI_PU2_Msk (0x1UL << PWR_PUCRI_PU2_Pos) |
| #define | PWR_PUCRI_PU2 PWR_PUCRI_PU2_Msk |
| #define | PWR_PUCRI_PU3_Pos (3U) |
| #define | PWR_PUCRI_PU3_Msk (0x1UL << PWR_PUCRI_PU3_Pos) |
| #define | PWR_PUCRI_PU3 PWR_PUCRI_PU3_Msk |
| #define | PWR_PUCRI_PU4_Pos (4U) |
| #define | PWR_PUCRI_PU4_Msk (0x1UL << PWR_PUCRI_PU4_Pos) |
| #define | PWR_PUCRI_PU4 PWR_PUCRI_PU4_Msk |
| #define | PWR_PUCRI_PU5_Pos (5U) |
| #define | PWR_PUCRI_PU5_Msk (0x1UL << PWR_PUCRI_PU5_Pos) |
| #define | PWR_PUCRI_PU5 PWR_PUCRI_PU5_Msk |
| #define | PWR_PUCRI_PU6_Pos (6U) |
| #define | PWR_PUCRI_PU6_Msk (0x1UL << PWR_PUCRI_PU6_Pos) |
| #define | PWR_PUCRI_PU6 PWR_PUCRI_PU6_Msk |
| #define | PWR_PUCRI_PU7_Pos (7U) |
| #define | PWR_PUCRI_PU7_Msk (0x1UL << PWR_PUCRI_PU7_Pos) |
| #define | PWR_PUCRI_PU7 PWR_PUCRI_PU7_Msk |
| #define | PWR_PUCRI_PU8_Pos (8U) |
| #define | PWR_PUCRI_PU8_Msk (0x1UL << PWR_PUCRI_PU8_Pos) |
| #define | PWR_PUCRI_PU8 PWR_PUCRI_PU8_Msk |
| #define | PWR_PUCRI_PU9_Pos (9U) |
| #define | PWR_PUCRI_PU9_Msk (0x1UL << PWR_PUCRI_PU9_Pos) |
| #define | PWR_PUCRI_PU9 PWR_PUCRI_PU9_Msk |
| #define | PWR_PUCRI_PU10_Pos (10U) |
| #define | PWR_PUCRI_PU10_Msk (0x1UL << PWR_PUCRI_PU10_Pos) |
| #define | PWR_PUCRI_PU10 PWR_PUCRI_PU10_Msk |
| #define | PWR_PUCRI_PU11_Pos (11U) |
| #define | PWR_PUCRI_PU11_Msk (0x1UL << PWR_PUCRI_PU11_Pos) |
| #define | PWR_PUCRI_PU11 PWR_PUCRI_PU11_Msk |
| #define | PWR_PUCRI_PU12_Pos (12U) |
| #define | PWR_PUCRI_PU12_Msk (0x1UL << PWR_PUCRI_PU12_Pos) |
| #define | PWR_PUCRI_PU12 PWR_PUCRI_PU12_Msk |
| #define | PWR_PUCRI_PU13_Pos (13U) |
| #define | PWR_PUCRI_PU13_Msk (0x1UL << PWR_PUCRI_PU13_Pos) |
| #define | PWR_PUCRI_PU13 PWR_PUCRI_PU13_Msk |
| #define | PWR_PUCRI_PU14_Pos (14U) |
| #define | PWR_PUCRI_PU14_Msk (0x1UL << PWR_PUCRI_PU14_Pos) |
| #define | PWR_PUCRI_PU14 PWR_PUCRI_PU14_Msk |
| #define | PWR_PUCRI_PU15_Pos (15U) |
| #define | PWR_PUCRI_PU15_Msk (0x1UL << PWR_PUCRI_PU15_Pos) |
| #define | PWR_PUCRI_PU15 PWR_PUCRI_PU15_Msk |
| #define | PWR_PDCRI_PD0_Pos (0U) |
| #define | PWR_PDCRI_PD0_Msk (0x1UL << PWR_PDCRI_PD0_Pos) |
| #define | PWR_PDCRI_PD0 PWR_PDCRI_PD0_Msk |
| #define | PWR_PDCRI_PD1_Pos (1U) |
| #define | PWR_PDCRI_PD1_Msk (0x1UL << PWR_PDCRI_PD1_Pos) |
| #define | PWR_PDCRI_PD1 PWR_PDCRI_PD1_Msk |
| #define | PWR_PDCRI_PD2_Pos (2U) |
| #define | PWR_PDCRI_PD2_Msk (0x1UL << PWR_PDCRI_PD2_Pos) |
| #define | PWR_PDCRI_PD2 PWR_PDCRI_PD2_Msk |
| #define | PWR_PDCRI_PD3_Pos (3U) |
| #define | PWR_PDCRI_PD3_Msk (0x1UL << PWR_PDCRI_PD3_Pos) |
| #define | PWR_PDCRI_PD3 PWR_PDCRI_PD3_Msk |
| #define | PWR_PDCRI_PD4_Pos (4U) |
| #define | PWR_PDCRI_PD4_Msk (0x1UL << PWR_PDCRI_PD4_Pos) |
| #define | PWR_PDCRI_PD4 PWR_PDCRI_PD4_Msk |
| #define | PWR_PDCRI_PD5_Pos (5U) |
| #define | PWR_PDCRI_PD5_Msk (0x1UL << PWR_PDCRI_PD5_Pos) |
| #define | PWR_PDCRI_PD5 PWR_PDCRI_PD5_Msk |
| #define | PWR_PDCRI_PD6_Pos (6U) |
| #define | PWR_PDCRI_PD6_Msk (0x1UL << PWR_PDCRI_PD6_Pos) |
| #define | PWR_PDCRI_PD6 PWR_PDCRI_PD6_Msk |
| #define | PWR_PDCRI_PD7_Pos (7U) |
| #define | PWR_PDCRI_PD7_Msk (0x1UL << PWR_PDCRI_PD7_Pos) |
| #define | PWR_PDCRI_PD7 PWR_PDCRI_PD7_Msk |
| #define | PWR_PDCRI_PD8_Pos (8U) |
| #define | PWR_PDCRI_PD8_Msk (0x1UL << PWR_PDCRI_PD8_Pos) |
| #define | PWR_PDCRI_PD8 PWR_PDCRI_PD8_Msk |
| #define | PWR_PDCRI_PD9_Pos (9U) |
| #define | PWR_PDCRI_PD9_Msk (0x1UL << PWR_PDCRI_PD9_Pos) |
| #define | PWR_PDCRI_PD9 PWR_PDCRI_PD9_Msk |
| #define | PWR_PDCRI_PD10_Pos (10U) |
| #define | PWR_PDCRI_PD10_Msk (0x1UL << PWR_PDCRI_PD10_Pos) |
| #define | PWR_PDCRI_PD10 PWR_PDCRI_PD10_Msk |
| #define | PWR_PDCRI_PD11_Pos (11U) |
| #define | PWR_PDCRI_PD11_Msk (0x1UL << PWR_PDCRI_PD11_Pos) |
| #define | PWR_PDCRI_PD11 PWR_PDCRI_PD11_Msk |
| #define | PWR_PDCRI_PD12_Pos (12U) |
| #define | PWR_PDCRI_PD12_Msk (0x1UL << PWR_PDCRI_PD12_Pos) |
| #define | PWR_PDCRI_PD12 PWR_PDCRI_PD12_Msk |
| #define | PWR_PDCRI_PD13_Pos (13U) |
| #define | PWR_PDCRI_PD13_Msk (0x1UL << PWR_PDCRI_PD13_Pos) |
| #define | PWR_PDCRI_PD13 PWR_PDCRI_PD13_Msk |
| #define | PWR_PDCRI_PD14_Pos (14U) |
| #define | PWR_PDCRI_PD14_Msk (0x1UL << PWR_PDCRI_PD14_Pos) |
| #define | PWR_PDCRI_PD14 PWR_PDCRI_PD14_Msk |
| #define | PWR_PDCRI_PD15_Pos (15U) |
| #define | PWR_PDCRI_PD15_Msk (0x1UL << PWR_PDCRI_PD15_Pos) |
| #define | PWR_PDCRI_PD15 PWR_PDCRI_PD15_Msk |
| #define | PWR_PUCRJ_PU0_Pos (0U) |
| #define | PWR_PUCRJ_PU0_Msk (0x1UL << PWR_PUCRJ_PU0_Pos) |
| #define | PWR_PUCRJ_PU0 PWR_PUCRJ_PU0_Msk |
| #define | PWR_PUCRJ_PU1_Pos (1U) |
| #define | PWR_PUCRJ_PU1_Msk (0x1UL << PWR_PUCRJ_PU1_Pos) |
| #define | PWR_PUCRJ_PU1 PWR_PUCRJ_PU1_Msk |
| #define | PWR_PUCRJ_PU2_Pos (2U) |
| #define | PWR_PUCRJ_PU2_Msk (0x1UL << PWR_PUCRJ_PU2_Pos) |
| #define | PWR_PUCRJ_PU2 PWR_PUCRJ_PU2_Msk |
| #define | PWR_PUCRJ_PU3_Pos (3U) |
| #define | PWR_PUCRJ_PU3_Msk (0x1UL << PWR_PUCRJ_PU3_Pos) |
| #define | PWR_PUCRJ_PU3 PWR_PUCRJ_PU3_Msk |
| #define | PWR_PUCRJ_PU4_Pos (4U) |
| #define | PWR_PUCRJ_PU4_Msk (0x1UL << PWR_PUCRJ_PU4_Pos) |
| #define | PWR_PUCRJ_PU4 PWR_PUCRJ_PU4_Msk |
| #define | PWR_PUCRJ_PU5_Pos (5U) |
| #define | PWR_PUCRJ_PU5_Msk (0x1UL << PWR_PUCRJ_PU5_Pos) |
| #define | PWR_PUCRJ_PU5 PWR_PUCRJ_PU5_Msk |
| #define | PWR_PUCRJ_PU6_Pos (6U) |
| #define | PWR_PUCRJ_PU6_Msk (0x1UL << PWR_PUCRJ_PU6_Pos) |
| #define | PWR_PUCRJ_PU6 PWR_PUCRJ_PU6_Msk |
| #define | PWR_PUCRJ_PU7_Pos (7U) |
| #define | PWR_PUCRJ_PU7_Msk (0x1UL << PWR_PUCRJ_PU7_Pos) |
| #define | PWR_PUCRJ_PU7 PWR_PUCRJ_PU7_Msk |
| #define | PWR_PUCRJ_PU8_Pos (8U) |
| #define | PWR_PUCRJ_PU8_Msk (0x1UL << PWR_PUCRJ_PU8_Pos) |
| #define | PWR_PUCRJ_PU8 PWR_PUCRJ_PU8_Msk |
| #define | PWR_PUCRJ_PU9_Pos (9U) |
| #define | PWR_PUCRJ_PU9_Msk (0x1UL << PWR_PUCRJ_PU9_Pos) |
| #define | PWR_PUCRJ_PU9 PWR_PUCRJ_PU9_Msk |
| #define | PWR_PUCRJ_PU10_Pos (10U) |
| #define | PWR_PUCRJ_PU10_Msk (0x1UL << PWR_PUCRJ_PU10_Pos) |
| #define | PWR_PUCRJ_PU10 PWR_PUCRJ_PU10_Msk |
| #define | PWR_PUCRJ_PU11_Pos (11U) |
| #define | PWR_PUCRJ_PU11_Msk (0x1UL << PWR_PUCRJ_PU11_Pos) |
| #define | PWR_PUCRJ_PU11 PWR_PUCRJ_PU11_Msk |
| #define | PWR_PDCRJ_PD0_Pos (0U) |
| #define | PWR_PDCRJ_PD0_Msk (0x1UL << PWR_PDCRJ_PD0_Pos) |
| #define | PWR_PDCRJ_PD0 PWR_PDCRJ_PD0_Msk |
| #define | PWR_PDCRJ_PD1_Pos (1U) |
| #define | PWR_PDCRJ_PD1_Msk (0x1UL << PWR_PDCRJ_PD1_Pos) |
| #define | PWR_PDCRJ_PD1 PWR_PDCRJ_PD1_Msk |
| #define | PWR_PDCRJ_PD2_Pos (2U) |
| #define | PWR_PDCRJ_PD2_Msk (0x1UL << PWR_PDCRJ_PD2_Pos) |
| #define | PWR_PDCRJ_PD2 PWR_PDCRJ_PD2_Msk |
| #define | PWR_PDCRJ_PD3_Pos (3U) |
| #define | PWR_PDCRJ_PD3_Msk (0x1UL << PWR_PDCRJ_PD3_Pos) |
| #define | PWR_PDCRJ_PD3 PWR_PDCRJ_PD3_Msk |
| #define | PWR_PDCRJ_PD4_Pos (4U) |
| #define | PWR_PDCRJ_PD4_Msk (0x1UL << PWR_PDCRJ_PD4_Pos) |
| #define | PWR_PDCRJ_PD4 PWR_PDCRJ_PD4_Msk |
| #define | PWR_PDCRJ_PD5_Pos (5U) |
| #define | PWR_PDCRJ_PD5_Msk (0x1UL << PWR_PDCRJ_PD5_Pos) |
| #define | PWR_PDCRJ_PD5 PWR_PDCRJ_PD5_Msk |
| #define | PWR_PDCRJ_PD6_Pos (6U) |
| #define | PWR_PDCRJ_PD6_Msk (0x1UL << PWR_PDCRJ_PD6_Pos) |
| #define | PWR_PDCRJ_PD6 PWR_PDCRJ_PD6_Msk |
| #define | PWR_PDCRJ_PD7_Pos (7U) |
| #define | PWR_PDCRJ_PD7_Msk (0x1UL << PWR_PDCRJ_PD7_Pos) |
| #define | PWR_PDCRJ_PD7 PWR_PDCRJ_PD7_Msk |
| #define | PWR_PDCRJ_PD8_Pos (8U) |
| #define | PWR_PDCRJ_PD8_Msk (0x1UL << PWR_PDCRJ_PD8_Pos) |
| #define | PWR_PDCRJ_PD8 PWR_PDCRJ_PD8_Msk |
| #define | PWR_PDCRJ_PD9_Pos (9U) |
| #define | PWR_PDCRJ_PD9_Msk (0x1UL << PWR_PDCRJ_PD9_Pos) |
| #define | PWR_PDCRJ_PD9 PWR_PDCRJ_PD9_Msk |
| #define | PWR_PDCRJ_PD10_Pos (10U) |
| #define | PWR_PDCRJ_PD10_Msk (0x1UL << PWR_PDCRJ_PD10_Pos) |
| #define | PWR_PDCRJ_PD10 PWR_PDCRJ_PD10_Msk |
| #define | PWR_PDCRJ_PD11_Pos (11U) |
| #define | PWR_PDCRJ_PD11_Msk (0x1UL << PWR_PDCRJ_PD11_Pos) |
| #define | PWR_PDCRJ_PD11 PWR_PDCRJ_PD11_Msk |
| #define | PWR_CR4_SRAM1PDS4_Pos (0U) |
| #define | PWR_CR4_SRAM1PDS4_Msk (0x1UL << PWR_CR4_SRAM1PDS4_Pos) |
| #define | PWR_CR4_SRAM1PDS4 PWR_CR4_SRAM1PDS4_Msk |
| #define | PWR_CR4_SRAM1PDS5_Pos (1U) |
| #define | PWR_CR4_SRAM1PDS5_Msk (0x1UL << PWR_CR4_SRAM1PDS5_Pos) |
| #define | PWR_CR4_SRAM1PDS5 PWR_CR4_SRAM1PDS5_Msk |
| #define | PWR_CR4_SRAM1PDS6_Pos (2U) |
| #define | PWR_CR4_SRAM1PDS6_Msk (0x1UL << PWR_CR4_SRAM1PDS6_Pos) |
| #define | PWR_CR4_SRAM1PDS6 PWR_CR4_SRAM1PDS6_Msk |
| #define | PWR_CR4_SRAM1PDS7_Pos (3U) |
| #define | PWR_CR4_SRAM1PDS7_Msk (0x1UL << PWR_CR4_SRAM1PDS7_Pos) |
| #define | PWR_CR4_SRAM1PDS7 PWR_CR4_SRAM1PDS7_Msk |
| #define | PWR_CR4_SRAM1PDS8_Pos (4U) |
| #define | PWR_CR4_SRAM1PDS8_Msk (0x1UL << PWR_CR4_SRAM1PDS8_Pos) |
| #define | PWR_CR4_SRAM1PDS8 PWR_CR4_SRAM1PDS8_Msk |
| #define | PWR_CR4_SRAM1PDS9_Pos (5U) |
| #define | PWR_CR4_SRAM1PDS9_Msk (0x1UL << PWR_CR4_SRAM1PDS9_Pos) |
| #define | PWR_CR4_SRAM1PDS9 PWR_CR4_SRAM1PDS9_Msk |
| #define | PWR_CR4_SRAM1PDS10_Pos (6U) |
| #define | PWR_CR4_SRAM1PDS10_Msk (0x1UL << PWR_CR4_SRAM1PDS10_Pos) |
| #define | PWR_CR4_SRAM1PDS10 PWR_CR4_SRAM1PDS10_Msk |
| #define | PWR_CR4_SRAM1PDS11_Pos (7U) |
| #define | PWR_CR4_SRAM1PDS11_Msk (0x1UL << PWR_CR4_SRAM1PDS11_Pos) |
| #define | PWR_CR4_SRAM1PDS11 PWR_CR4_SRAM1PDS11_Msk |
| #define | PWR_CR4_SRAM1PDS12_Pos (8U) |
| #define | PWR_CR4_SRAM1PDS12_Msk (0x1UL << PWR_CR4_SRAM1PDS12_Pos) |
| #define | PWR_CR4_SRAM1PDS12 PWR_CR4_SRAM1PDS12_Msk |
| #define | PWR_CR4_SRAM3PDS9_Pos (10U) |
| #define | PWR_CR4_SRAM3PDS9_Msk (0x1UL << PWR_CR4_SRAM3PDS9_Pos) |
| #define | PWR_CR4_SRAM3PDS9 PWR_CR4_SRAM3PDS9_Msk |
| #define | PWR_CR4_SRAM3PDS10_Pos (11U) |
| #define | PWR_CR4_SRAM3PDS10_Msk (0x1UL << PWR_CR4_SRAM3PDS10_Pos) |
| #define | PWR_CR4_SRAM3PDS10 PWR_CR4_SRAM3PDS10_Msk |
| #define | PWR_CR4_SRAM3PDS11_Pos (12U) |
| #define | PWR_CR4_SRAM3PDS11_Msk (0x1UL << PWR_CR4_SRAM3PDS11_Pos) |
| #define | PWR_CR4_SRAM3PDS11 PWR_CR4_SRAM3PDS11_Msk |
| #define | PWR_CR4_SRAM3PDS12_Pos (13U) |
| #define | PWR_CR4_SRAM3PDS12_Msk (0x1UL << PWR_CR4_SRAM3PDS12_Pos) |
| #define | PWR_CR4_SRAM3PDS12 PWR_CR4_SRAM3PDS12_Msk |
| #define | PWR_CR4_SRAM3PDS13_Pos (14U) |
| #define | PWR_CR4_SRAM3PDS13_Msk (0x1UL << PWR_CR4_SRAM3PDS13_Pos) |
| #define | PWR_CR4_SRAM3PDS13 PWR_CR4_SRAM3PDS13_Msk |
| #define | PWR_CR4_SRAM5PDS1_Pos (16U) |
| #define | PWR_CR4_SRAM5PDS1_Msk (0x1UL << PWR_CR4_SRAM5PDS1_Pos) |
| #define | PWR_CR4_SRAM5PDS1 PWR_CR4_SRAM5PDS1_Msk |
| #define | PWR_CR4_SRAM5PDS2_Pos (17U) |
| #define | PWR_CR4_SRAM5PDS2_Msk (0x1UL << PWR_CR4_SRAM5PDS2_Pos) |
| #define | PWR_CR4_SRAM5PDS2 PWR_CR4_SRAM5PDS2_Msk |
| #define | PWR_CR4_SRAM5PDS3_Pos (18U) |
| #define | PWR_CR4_SRAM5PDS3_Msk (0x1UL << PWR_CR4_SRAM5PDS3_Pos) |
| #define | PWR_CR4_SRAM5PDS3 PWR_CR4_SRAM5PDS3_Msk |
| #define | PWR_CR4_SRAM5PDS4_Pos (19U) |
| #define | PWR_CR4_SRAM5PDS4_Msk (0x1UL << PWR_CR4_SRAM5PDS4_Pos) |
| #define | PWR_CR4_SRAM5PDS4 PWR_CR4_SRAM5PDS4_Msk |
| #define | PWR_CR4_SRAM5PDS5_Pos (20U) |
| #define | PWR_CR4_SRAM5PDS5_Msk (0x1UL << PWR_CR4_SRAM5PDS5_Pos) |
| #define | PWR_CR4_SRAM5PDS5 PWR_CR4_SRAM5PDS5_Msk |
| #define | PWR_CR4_SRAM5PDS6_Pos (21U) |
| #define | PWR_CR4_SRAM5PDS6_Msk (0x1UL << PWR_CR4_SRAM5PDS6_Pos) |
| #define | PWR_CR4_SRAM5PDS6 PWR_CR4_SRAM5PDS6_Msk |
| #define | PWR_CR4_SRAM5PDS7_Pos (22U) |
| #define | PWR_CR4_SRAM5PDS7_Msk (0x1UL << PWR_CR4_SRAM5PDS7_Pos) |
| #define | PWR_CR4_SRAM5PDS7 PWR_CR4_SRAM5PDS7_Msk |
| #define | PWR_CR4_SRAM5PDS8_Pos (23U) |
| #define | PWR_CR4_SRAM5PDS8_Msk (0x1UL << PWR_CR4_SRAM5PDS8_Pos) |
| #define | PWR_CR4_SRAM5PDS8 PWR_CR4_SRAM5PDS8_Msk |
| #define | PWR_CR4_SRAM5PDS9_Pos (24U) |
| #define | PWR_CR4_SRAM5PDS9_Msk (0x1UL << PWR_CR4_SRAM5PDS9_Pos) |
| #define | PWR_CR4_SRAM5PDS9 PWR_CR4_SRAM5PDS9_Msk |
| #define | PWR_CR4_SRAM5PDS10_Pos (25U) |
| #define | PWR_CR4_SRAM5PDS10_Msk (0x1UL << PWR_CR4_SRAM5PDS10_Pos) |
| #define | PWR_CR4_SRAM5PDS10 PWR_CR4_SRAM5PDS10_Msk |
| #define | PWR_CR4_SRAM5PDS11_Pos (26U) |
| #define | PWR_CR4_SRAM5PDS11_Msk (0x1UL << PWR_CR4_SRAM5PDS11_Pos) |
| #define | PWR_CR4_SRAM5PDS11 PWR_CR4_SRAM5PDS11_Msk |
| #define | PWR_CR4_SRAM5PDS12_Pos (27U) |
| #define | PWR_CR4_SRAM5PDS12_Msk (0x1UL << PWR_CR4_SRAM5PDS12_Pos) |
| #define | PWR_CR4_SRAM5PDS12 PWR_CR4_SRAM5PDS12_Msk |
| #define | PWR_CR4_SRAM5PDS13_Pos (28U) |
| #define | PWR_CR4_SRAM5PDS13_Msk (0x1UL << PWR_CR4_SRAM5PDS13_Pos) |
| #define | PWR_CR4_SRAM5PDS13 PWR_CR4_SRAM5PDS13_Msk |
| #define | PWR_CR5_SRAM6PDS1_Pos (0U) |
| #define | PWR_CR5_SRAM6PDS1_Msk (0x1UL << PWR_CR5_SRAM6PDS1_Pos) |
| #define | PWR_CR5_SRAM6PDS1 PWR_CR5_SRAM6PDS1_Msk |
| #define | PWR_CR5_SRAM6PDS2_Pos (1U) |
| #define | PWR_CR5_SRAM6PDS2_Msk (0x1UL << PWR_CR5_SRAM6PDS2_Pos) |
| #define | PWR_CR5_SRAM6PDS2 PWR_CR5_SRAM6PDS2_Msk |
| #define | PWR_CR5_SRAM6PDS3_Pos (2U) |
| #define | PWR_CR5_SRAM6PDS3_Msk (0x1UL << PWR_CR5_SRAM6PDS3_Pos) |
| #define | PWR_CR5_SRAM6PDS3 PWR_CR5_SRAM6PDS3_Msk |
| #define | PWR_CR5_SRAM6PDS4_Pos (3U) |
| #define | PWR_CR5_SRAM6PDS4_Msk (0x1UL << PWR_CR5_SRAM6PDS4_Pos) |
| #define | PWR_CR5_SRAM6PDS4 PWR_CR5_SRAM6PDS4_Msk |
| #define | PWR_CR5_SRAM6PDS5_Pos (4U) |
| #define | PWR_CR5_SRAM6PDS5_Msk (0x1UL << PWR_CR5_SRAM6PDS5_Pos) |
| #define | PWR_CR5_SRAM6PDS5 PWR_CR5_SRAM6PDS5_Msk |
| #define | PWR_CR5_SRAM6PDS6_Pos (5U) |
| #define | PWR_CR5_SRAM6PDS6_Msk (0x1UL << PWR_CR5_SRAM6PDS6_Pos) |
| #define | PWR_CR5_SRAM6PDS6 PWR_CR5_SRAM6PDS6_Msk |
| #define | PWR_CR5_SRAM6PDS7_Pos (6U) |
| #define | PWR_CR5_SRAM6PDS7_Msk (0x1UL << PWR_CR5_SRAM6PDS7_Pos) |
| #define | PWR_CR5_SRAM6PDS7 PWR_CR5_SRAM6PDS7_Msk |
| #define | PWR_CR5_SRAM6PDS8_Pos (7U) |
| #define | PWR_CR5_SRAM6PDS8_Msk (0x1UL << PWR_CR5_SRAM6PDS8_Pos) |
| #define | PWR_CR5_SRAM6PDS8 PWR_CR5_SRAM6PDS8_Msk |
| #define | RAMCFG_CR_ECCE_Pos (0U) |
| #define | RAMCFG_CR_ECCE_Msk (0x1UL << RAMCFG_CR_ECCE_Pos) |
| #define | RAMCFG_CR_ECCE RAMCFG_CR_ECCE_Msk |
| #define | RAMCFG_CR_ALE_Pos (4U) |
| #define | RAMCFG_CR_ALE_Msk (0x1UL << RAMCFG_CR_ALE_Pos) |
| #define | RAMCFG_CR_ALE RAMCFG_CR_ALE_Msk |
| #define | RAMCFG_CR_SRAMER_Pos (8U) |
| #define | RAMCFG_CR_SRAMER_Msk (0x1UL << RAMCFG_CR_SRAMER_Pos) |
| #define | RAMCFG_CR_SRAMER RAMCFG_CR_SRAMER_Msk |
| #define | RAMCFG_CR_WSC_Pos (16U) |
| #define | RAMCFG_CR_WSC_Msk (0x7UL << RAMCFG_CR_WSC_Pos) |
| #define | RAMCFG_CR_WSC RAMCFG_CR_WSC_Msk |
| #define | RAMCFG_CR_WSC_0 (0x1UL << RAMCFG_CR_WSC_Pos) |
| #define | RAMCFG_CR_WSC_1 (0x2UL << RAMCFG_CR_WSC_Pos) |
| #define | RAMCFG_CR_WSC_2 (0x4UL << RAMCFG_CR_WSC_Pos) |
| #define | RAMCFG_IER_SEIE_Pos (0U) |
| #define | RAMCFG_IER_SEIE_Msk (0x1UL << RAMCFG_IER_SEIE_Pos) |
| #define | RAMCFG_IER_SEIE RAMCFG_IER_SEIE_Msk |
| #define | RAMCFG_IER_DEIE_Pos (1U) |
| #define | RAMCFG_IER_DEIE_Msk (0x1UL << RAMCFG_IER_DEIE_Pos) |
| #define | RAMCFG_IER_DEIE RAMCFG_IER_DEIE_Msk |
| #define | RAMCFG_IER_ECCNMI_Pos (3U) |
| #define | RAMCFG_IER_ECCNMI_Msk (0x1UL << RAMCFG_IER_ECCNMI_Pos) |
| #define | RAMCFG_IER_ECCNMI RAMCFG_IER_ECCNMI_Msk |
| #define | RAMCFG_ISR_SEDC_Pos (0U) |
| #define | RAMCFG_ISR_SEDC_Msk (0x1UL << RAMCFG_ISR_SEDC_Pos) |
| #define | RAMCFG_ISR_SEDC RAMCFG_ISR_SEDC_Msk |
| #define | RAMCFG_ISR_DED_Pos (1U) |
| #define | RAMCFG_ISR_DED_Msk (0x1UL << RAMCFG_ISR_DED_Pos) |
| #define | RAMCFG_ISR_DED RAMCFG_ISR_DED_Msk |
| #define | RAMCFG_ISR_SRAMBUSY_Pos (8U) |
| #define | RAMCFG_ISR_SRAMBUSY_Msk (0x1UL << RAMCFG_ISR_SRAMBUSY_Pos) |
| #define | RAMCFG_ISR_SRAMBUSY RAMCFG_ISR_SRAMBUSY_Msk |
| #define | RAMCFG_SEAR_ESEA_Pos (0U) |
| #define | RAMCFG_SEAR_ESEA_Msk (0xFFFFFFFFUL << RAMCFG_SEAR_ESEA_Pos) |
| #define | RAMCFG_SEAR_ESEA RAMCFG_SEAR_ESEA_Msk |
| #define | RAMCFG_DEAR_EDEA_Pos (0U) |
| #define | RAMCFG_DEAR_EDEA_Msk (0xFFFFFFFFUL << RAMCFG_DEAR_EDEA_Pos) |
| #define | RAMCFG_DEAR_EDEA RAMCFG_DEAR_EDEA_Msk |
| #define | RAMCFG_ICR_CSEDC_Pos (0U) |
| #define | RAMCFG_ICR_CSEDC_Msk (0x1UL << RAMCFG_ICR_CSEDC_Pos) |
| #define | RAMCFG_ICR_CSEDC RAMCFG_ICR_CSEDC_Msk |
| #define | RAMCFG_ICR_CDED_Pos (1U) |
| #define | RAMCFG_ICR_CDED_Msk (0x1UL << RAMCFG_ICR_CDED_Pos) |
| #define | RAMCFG_ICR_CDED RAMCFG_ICR_CDED_Msk |
| #define | RAMCFG_WPR1_P0WP_Pos (0U) |
| #define | RAMCFG_WPR1_P0WP_Msk (0x1UL << RAMCFG_WPR1_P0WP_Pos) |
| #define | RAMCFG_WPR1_P0WP RAMCFG_WPR1_P0WP_Msk |
| #define | RAMCFG_WPR1_P1WP_Pos (1U) |
| #define | RAMCFG_WPR1_P1WP_Msk (0x1UL << RAMCFG_WPR1_P1WP_Pos) |
| #define | RAMCFG_WPR1_P1WP RAMCFG_WPR1_P1WP_Msk |
| #define | RAMCFG_WPR1_P2WP_Pos (2U) |
| #define | RAMCFG_WPR1_P2WP_Msk (0x1UL << RAMCFG_WPR1_P2WP_Pos) |
| #define | RAMCFG_WPR1_P2WP RAMCFG_WPR1_P2WP_Msk |
| #define | RAMCFG_WPR1_P3WP_Pos (3U) |
| #define | RAMCFG_WPR1_P3WP_Msk (0x1UL << RAMCFG_WPR1_P3WP_Pos) |
| #define | RAMCFG_WPR1_P3WP RAMCFG_WPR1_P3WP_Msk |
| #define | RAMCFG_WPR1_P4WP_Pos (4U) |
| #define | RAMCFG_WPR1_P4WP_Msk (0x1UL << RAMCFG_WPR1_P4WP_Pos) |
| #define | RAMCFG_WPR1_P4WP RAMCFG_WPR1_P4WP_Msk |
| #define | RAMCFG_WPR1_P5WP_Pos (5U) |
| #define | RAMCFG_WPR1_P5WP_Msk (0x1UL << RAMCFG_WPR1_P5WP_Pos) |
| #define | RAMCFG_WPR1_P5WP RAMCFG_WPR1_P5WP_Msk |
| #define | RAMCFG_WPR1_P6WP_Pos (6U) |
| #define | RAMCFG_WPR1_P6WP_Msk (0x1UL << RAMCFG_WPR1_P6WP_Pos) |
| #define | RAMCFG_WPR1_P6WP RAMCFG_WPR1_P6WP_Msk |
| #define | RAMCFG_WPR1_P7WP_Pos (7U) |
| #define | RAMCFG_WPR1_P7WP_Msk (0x1UL << RAMCFG_WPR1_P7WP_Pos) |
| #define | RAMCFG_WPR1_P7WP RAMCFG_WPR1_P7WP_Msk |
| #define | RAMCFG_WPR1_P8WP_Pos (8U) |
| #define | RAMCFG_WPR1_P8WP_Msk (0x1UL << RAMCFG_WPR1_P8WP_Pos) |
| #define | RAMCFG_WPR1_P8WP RAMCFG_WPR1_P8WP_Msk |
| #define | RAMCFG_WPR1_P9WP_Pos (9U) |
| #define | RAMCFG_WPR1_P9WP_Msk (0x1UL << RAMCFG_WPR1_P9WP_Pos) |
| #define | RAMCFG_WPR1_P9WP RAMCFG_WPR1_P9WP_Msk |
| #define | RAMCFG_WPR1_P10WP_Pos (10U) |
| #define | RAMCFG_WPR1_P10WP_Msk (0x1UL << RAMCFG_WPR1_P10WP_Pos) |
| #define | RAMCFG_WPR1_P10WP RAMCFG_WPR1_P10WP_Msk |
| #define | RAMCFG_WPR1_P11WP_Pos (11U) |
| #define | RAMCFG_WPR1_P11WP_Msk (0x1UL << RAMCFG_WPR1_P11WP_Pos) |
| #define | RAMCFG_WPR1_P11WP RAMCFG_WPR1_P11WP_Msk |
| #define | RAMCFG_WPR1_P12WP_Pos (12U) |
| #define | RAMCFG_WPR1_P12WP_Msk (0x1UL << RAMCFG_WPR1_P12WP_Pos) |
| #define | RAMCFG_WPR1_P12WP RAMCFG_WPR1_P12WP_Msk |
| #define | RAMCFG_WPR1_P13WP_Pos (13U) |
| #define | RAMCFG_WPR1_P13WP_Msk (0x1UL << RAMCFG_WPR1_P13WP_Pos) |
| #define | RAMCFG_WPR1_P13WP RAMCFG_WPR1_P13WP_Msk |
| #define | RAMCFG_WPR1_P14WP_Pos (14U) |
| #define | RAMCFG_WPR1_P14WP_Msk (0x1UL << RAMCFG_WPR1_P14WP_Pos) |
| #define | RAMCFG_WPR1_P14WP RAMCFG_WPR1_P14WP_Msk |
| #define | RAMCFG_WPR1_P15WP_Pos (15U) |
| #define | RAMCFG_WPR1_P15WP_Msk (0x1UL << RAMCFG_WPR1_P15WP_Pos) |
| #define | RAMCFG_WPR1_P15WP RAMCFG_WPR1_P15WP_Msk |
| #define | RAMCFG_WPR1_P16WP_Pos (16U) |
| #define | RAMCFG_WPR1_P16WP_Msk (0x1UL << RAMCFG_WPR1_P16WP_Pos) |
| #define | RAMCFG_WPR1_P16WP RAMCFG_WPR1_P16WP_Msk |
| #define | RAMCFG_WPR1_P17WP_Pos (17U) |
| #define | RAMCFG_WPR1_P17WP_Msk (0x1UL << RAMCFG_WPR1_P17WP_Pos) |
| #define | RAMCFG_WPR1_P17WP RAMCFG_WPR1_P17WP_Msk |
| #define | RAMCFG_WPR1_P18WP_Pos (18U) |
| #define | RAMCFG_WPR1_P18WP_Msk (0x1UL << RAMCFG_WPR1_P18WP_Pos) |
| #define | RAMCFG_WPR1_P18WP RAMCFG_WPR1_P18WP_Msk |
| #define | RAMCFG_WPR1_P19WP_Pos (19U) |
| #define | RAMCFG_WPR1_P19WP_Msk (0x1UL << RAMCFG_WPR1_P19WP_Pos) |
| #define | RAMCFG_WPR1_P19WP RAMCFG_WPR1_P19WP_Msk |
| #define | RAMCFG_WPR1_P20WP_Pos (20U) |
| #define | RAMCFG_WPR1_P20WP_Msk (0x1UL << RAMCFG_WPR1_P20WP_Pos) |
| #define | RAMCFG_WPR1_P20WP RAMCFG_WPR1_P20WP_Msk |
| #define | RAMCFG_WPR1_P21WP_Pos (21U) |
| #define | RAMCFG_WPR1_P21WP_Msk (0x1UL << RAMCFG_WPR1_P21WP_Pos) |
| #define | RAMCFG_WPR1_P21WP RAMCFG_WPR1_P21WP_Msk |
| #define | RAMCFG_WPR1_P22WP_Pos (22U) |
| #define | RAMCFG_WPR1_P22WP_Msk (0x1UL << RAMCFG_WPR1_P22WP_Pos) |
| #define | RAMCFG_WPR1_P22WP RAMCFG_WPR1_P22WP_Msk |
| #define | RAMCFG_WPR1_P23WP_Pos (23U) |
| #define | RAMCFG_WPR1_P23WP_Msk (0x1UL << RAMCFG_WPR1_P23WP_Pos) |
| #define | RAMCFG_WPR1_P23WP RAMCFG_WPR1_P23WP_Msk |
| #define | RAMCFG_WPR1_P24WP_Pos (24U) |
| #define | RAMCFG_WPR1_P24WP_Msk (0x1UL << RAMCFG_WPR1_P24WP_Pos) |
| #define | RAMCFG_WPR1_P24WP RAMCFG_WPR1_P24WP_Msk |
| #define | RAMCFG_WPR1_P25WP_Pos (25U) |
| #define | RAMCFG_WPR1_P25WP_Msk (0x1UL << RAMCFG_WPR1_P25WP_Pos) |
| #define | RAMCFG_WPR1_P25WP RAMCFG_WPR1_P25WP_Msk |
| #define | RAMCFG_WPR1_P26WP_Pos (26U) |
| #define | RAMCFG_WPR1_P26WP_Msk (0x1UL << RAMCFG_WPR1_P26WP_Pos) |
| #define | RAMCFG_WPR1_P26WP RAMCFG_WPR1_P26WP_Msk |
| #define | RAMCFG_WPR1_P27WP_Pos (27U) |
| #define | RAMCFG_WPR1_P27WP_Msk (0x1UL << RAMCFG_WPR1_P27WP_Pos) |
| #define | RAMCFG_WPR1_P27WP RAMCFG_WPR1_P27WP_Msk |
| #define | RAMCFG_WPR1_P28WP_Pos (28U) |
| #define | RAMCFG_WPR1_P28WP_Msk (0x1UL << RAMCFG_WPR1_P28WP_Pos) |
| #define | RAMCFG_WPR1_P28WP RAMCFG_WPR1_P28WP_Msk |
| #define | RAMCFG_WPR1_P29WP_Pos (29U) |
| #define | RAMCFG_WPR1_P29WP_Msk (0x1UL << RAMCFG_WPR1_P29WP_Pos) |
| #define | RAMCFG_WPR1_P29WP RAMCFG_WPR1_P29WP_Msk |
| #define | RAMCFG_WPR1_P30WP_Pos (30U) |
| #define | RAMCFG_WPR1_P30WP_Msk (0x1UL << RAMCFG_WPR1_P30WP_Pos) |
| #define | RAMCFG_WPR1_P30WP RAMCFG_WPR1_P30WP_Msk |
| #define | RAMCFG_WPR1_P31WP_Pos (31U) |
| #define | RAMCFG_WPR1_P31WP_Msk (0x1UL << RAMCFG_WPR1_P31WP_Pos) |
| #define | RAMCFG_WPR1_P31WP RAMCFG_WPR1_P31WP_Msk |
| #define | RAMCFG_WPR2_P32WP_Pos (0U) |
| #define | RAMCFG_WPR2_P32WP_Msk (0x1UL << RAMCFG_WPR2_P32WP_Pos) |
| #define | RAMCFG_WPR2_P32WP RAMCFG_WPR2_P32WP_Msk |
| #define | RAMCFG_WPR2_P33WP_Pos (1U) |
| #define | RAMCFG_WPR2_P33WP_Msk (0x1UL << RAMCFG_WPR2_P33WP_Pos) |
| #define | RAMCFG_WPR2_P33WP RAMCFG_WPR2_P33WP_Msk |
| #define | RAMCFG_WPR2_P34WP_Pos (2U) |
| #define | RAMCFG_WPR2_P34WP_Msk (0x1UL << RAMCFG_WPR2_P34WP_Pos) |
| #define | RAMCFG_WPR2_P34WP RAMCFG_WPR2_P34WP_Msk |
| #define | RAMCFG_WPR2_P35WP_Pos (3U) |
| #define | RAMCFG_WPR2_P35WP_Msk (0x1UL << RAMCFG_WPR2_P35WP_Pos) |
| #define | RAMCFG_WPR2_P35WP RAMCFG_WPR2_P35WP_Msk |
| #define | RAMCFG_WPR2_P36WP_Pos (4U) |
| #define | RAMCFG_WPR2_P36WP_Msk (0x1UL << RAMCFG_WPR2_P36WP_Pos) |
| #define | RAMCFG_WPR2_P36WP RAMCFG_WPR2_P36WP_Msk |
| #define | RAMCFG_WPR2_P37WP_Pos (5U) |
| #define | RAMCFG_WPR2_P37WP_Msk (0x1UL << RAMCFG_WPR2_P37WP_Pos) |
| #define | RAMCFG_WPR2_P37WP RAMCFG_WPR2_P37WP_Msk |
| #define | RAMCFG_WPR2_P38WP_Pos (6U) |
| #define | RAMCFG_WPR2_P38WP_Msk (0x1UL << RAMCFG_WPR2_P38WP_Pos) |
| #define | RAMCFG_WPR2_P38WP RAMCFG_WPR2_P38WP_Msk |
| #define | RAMCFG_WPR2_P39WP_Pos (7U) |
| #define | RAMCFG_WPR2_P39WP_Msk (0x1UL << RAMCFG_WPR2_P39WP_Pos) |
| #define | RAMCFG_WPR2_P39WP RAMCFG_WPR2_P39WP_Msk |
| #define | RAMCFG_WPR2_P40WP_Pos (8U) |
| #define | RAMCFG_WPR2_P40WP_Msk (0x1UL << RAMCFG_WPR2_P40WP_Pos) |
| #define | RAMCFG_WPR2_P40WP RAMCFG_WPR2_P40WP_Msk |
| #define | RAMCFG_WPR2_P41WP_Pos (9U) |
| #define | RAMCFG_WPR2_P41WP_Msk (0x1UL << RAMCFG_WPR2_P41WP_Pos) |
| #define | RAMCFG_WPR2_P41WP RAMCFG_WPR2_P41WP_Msk |
| #define | RAMCFG_WPR2_P42WP_Pos (10U) |
| #define | RAMCFG_WPR2_P42WP_Msk (0x1UL << RAMCFG_WPR2_P42WP_Pos) |
| #define | RAMCFG_WPR2_P42WP RAMCFG_WPR2_P42WP_Msk |
| #define | RAMCFG_WPR2_P43WP_Pos (11U) |
| #define | RAMCFG_WPR2_P43WP_Msk (0x1UL << RAMCFG_WPR2_P43WP_Pos) |
| #define | RAMCFG_WPR2_P43WP RAMCFG_WPR2_P43WP_Msk |
| #define | RAMCFG_WPR2_P44WP_Pos (12U) |
| #define | RAMCFG_WPR2_P44WP_Msk (0x1UL << RAMCFG_WPR2_P44WP_Pos) |
| #define | RAMCFG_WPR2_P44WP RAMCFG_WPR2_P44WP_Msk |
| #define | RAMCFG_WPR2_P45WP_Pos (13U) |
| #define | RAMCFG_WPR2_P45WP_Msk (0x1UL << RAMCFG_WPR2_P45WP_Pos) |
| #define | RAMCFG_WPR2_P45WP RAMCFG_WPR2_P45WP_Msk |
| #define | RAMCFG_WPR2_P46WP_Pos (14U) |
| #define | RAMCFG_WPR2_P46WP_Msk (0x1UL << RAMCFG_WPR2_P46WP_Pos) |
| #define | RAMCFG_WPR2_P46WP RAMCFG_WPR2_P46WP_Msk |
| #define | RAMCFG_WPR2_P47WP_Pos (15U) |
| #define | RAMCFG_WPR2_P47WP_Msk (0x1UL << RAMCFG_WPR2_P47WP_Pos) |
| #define | RAMCFG_WPR2_P47WP RAMCFG_WPR2_P47WP_Msk |
| #define | RAMCFG_WPR2_P48WP_Pos (16U) |
| #define | RAMCFG_WPR2_P48WP_Msk (0x1UL << RAMCFG_WPR2_P48WP_Pos) |
| #define | RAMCFG_WPR2_P48WP RAMCFG_WPR2_P48WP_Msk |
| #define | RAMCFG_WPR2_P49WP_Pos (17U) |
| #define | RAMCFG_WPR2_P49WP_Msk (0x1UL << RAMCFG_WPR2_P49WP_Pos) |
| #define | RAMCFG_WPR2_P49WP RAMCFG_WPR2_P49WP_Msk |
| #define | RAMCFG_WPR2_P50WP_Pos (18U) |
| #define | RAMCFG_WPR2_P50WP_Msk (0x1UL << RAMCFG_WPR2_P50WP_Pos) |
| #define | RAMCFG_WPR2_P50WP RAMCFG_WPR2_P50WP_Msk |
| #define | RAMCFG_WPR2_P51WP_Pos (19U) |
| #define | RAMCFG_WPR2_P51WP_Msk (0x1UL << RAMCFG_WPR2_P51WP_Pos) |
| #define | RAMCFG_WPR2_P51WP RAMCFG_WPR2_P51WP_Msk |
| #define | RAMCFG_WPR2_P52WP_Pos (20U) |
| #define | RAMCFG_WPR2_P52WP_Msk (0x1UL << RAMCFG_WPR2_P52WP_Pos) |
| #define | RAMCFG_WPR2_P52WP RAMCFG_WPR2_P52WP_Msk |
| #define | RAMCFG_WPR2_P53WP_Pos (21U) |
| #define | RAMCFG_WPR2_P53WP_Msk (0x1UL << RAMCFG_WPR2_P53WP_Pos) |
| #define | RAMCFG_WPR2_P53WP RAMCFG_WPR2_P53WP_Msk |
| #define | RAMCFG_WPR2_P54WP_Pos (22U) |
| #define | RAMCFG_WPR2_P54WP_Msk (0x1UL << RAMCFG_WPR2_P54WP_Pos) |
| #define | RAMCFG_WPR2_P54WP RAMCFG_WPR2_P54WP_Msk |
| #define | RAMCFG_WPR2_P55WP_Pos (23U) |
| #define | RAMCFG_WPR2_P55WP_Msk (0x1UL << RAMCFG_WPR2_P55WP_Pos) |
| #define | RAMCFG_WPR2_P55WP RAMCFG_WPR2_P55WP_Msk |
| #define | RAMCFG_WPR2_P56WP_Pos (24U) |
| #define | RAMCFG_WPR2_P56WP_Msk (0x1UL << RAMCFG_WPR2_P56WP_Pos) |
| #define | RAMCFG_WPR2_P56WP RAMCFG_WPR2_P56WP_Msk |
| #define | RAMCFG_WPR2_P57WP_Pos (25U) |
| #define | RAMCFG_WPR2_P57WP_Msk (0x1UL << RAMCFG_WPR2_P57WP_Pos) |
| #define | RAMCFG_WPR2_P57WP RAMCFG_WPR2_P57WP_Msk |
| #define | RAMCFG_WPR2_P58WP_Pos (26U) |
| #define | RAMCFG_WPR2_P58WP_Msk (0x1UL << RAMCFG_WPR2_P58WP_Pos) |
| #define | RAMCFG_WPR2_P58WP RAMCFG_WPR2_P58WP_Msk |
| #define | RAMCFG_WPR2_P59WP_Pos (27U) |
| #define | RAMCFG_WPR2_P59WP_Msk (0x1UL << RAMCFG_WPR2_P59WP_Pos) |
| #define | RAMCFG_WPR2_P59WP RAMCFG_WPR2_P59WP_Msk |
| #define | RAMCFG_WPR2_P60WP_Pos (28U) |
| #define | RAMCFG_WPR2_P60WP_Msk (0x1UL << RAMCFG_WPR2_P60WP_Pos) |
| #define | RAMCFG_WPR2_P60WP RAMCFG_WPR2_P60WP_Msk |
| #define | RAMCFG_WPR2_P61WP_Pos (29U) |
| #define | RAMCFG_WPR2_P61WP_Msk (0x1UL << RAMCFG_WPR2_P61WP_Pos) |
| #define | RAMCFG_WPR2_P61WP RAMCFG_WPR2_P61WP_Msk |
| #define | RAMCFG_WPR2_P62WP_Pos (30U) |
| #define | RAMCFG_WPR2_P62WP_Msk (0x1UL << RAMCFG_WPR2_P62WP_Pos) |
| #define | RAMCFG_WPR2_P62WP RAMCFG_WPR2_P62WP_Msk |
| #define | RAMCFG_WPR2_P63WP_Pos (31U) |
| #define | RAMCFG_WPR2_P63WP_Msk (0x1UL << RAMCFG_WPR2_P63WP_Pos) |
| #define | RAMCFG_WPR2_P63WP RAMCFG_WPR2_P63WP_Msk |
| #define | RAMCFG_ECCKEYR_ECCKEY_Pos (0U) |
| #define | RAMCFG_ECCKEYR_ECCKEY_Msk (0xFFUL << RAMCFG_ECCKEYR_ECCKEY_Pos) |
| #define | RAMCFG_ECCKEYR_ECCKEY RAMCFG_ECCKEYR_ECCKEY_Msk |
| #define | RAMCFG_ERKEYR_ERASEKEY_Pos (0U) |
| #define | RAMCFG_ERKEYR_ERASEKEY_Msk (0xFFUL << RAMCFG_ERKEYR_ERASEKEY_Pos) |
| #define | RAMCFG_ERKEYR_ERASEKEY RAMCFG_ERKEYR_ERASEKEY_Msk |
| #define | RCC_CR_MSISON_Pos (0U) |
| #define | RCC_CR_MSISON_Msk (0x1UL << RCC_CR_MSISON_Pos) |
| #define | RCC_CR_MSISON RCC_CR_MSISON_Msk |
| #define | RCC_CR_MSIKERON_Pos (1U) |
| #define | RCC_CR_MSIKERON_Msk (0x1UL << RCC_CR_MSIKERON_Pos) |
| #define | RCC_CR_MSIKERON RCC_CR_MSIKERON_Msk |
| #define | RCC_CR_MSISRDY_Pos (2U) |
| #define | RCC_CR_MSISRDY_Msk (0x1UL << RCC_CR_MSISRDY_Pos) |
| #define | RCC_CR_MSISRDY RCC_CR_MSISRDY_Msk |
| #define | RCC_CR_MSIPLLEN_Pos (3U) |
| #define | RCC_CR_MSIPLLEN_Msk (0x1UL << RCC_CR_MSIPLLEN_Pos) |
| #define | RCC_CR_MSIPLLEN RCC_CR_MSIPLLEN_Msk |
| #define | RCC_CR_MSIKON_Pos (4U) |
| #define | RCC_CR_MSIKON_Msk (0x1UL << RCC_CR_MSIKON_Pos) |
| #define | RCC_CR_MSIKON RCC_CR_MSIKON_Msk |
| #define | RCC_CR_MSIKRDY_Pos (5U) |
| #define | RCC_CR_MSIKRDY_Msk (0x1UL << RCC_CR_MSIKRDY_Pos) |
| #define | RCC_CR_MSIKRDY RCC_CR_MSIKRDY_Msk |
| #define | RCC_CR_MSIPLLSEL_Pos (6U) |
| #define | RCC_CR_MSIPLLSEL_Msk (0x1UL << RCC_CR_MSIPLLSEL_Pos) |
| #define | RCC_CR_MSIPLLSEL RCC_CR_MSIPLLSEL_Msk |
| #define | RCC_CR_MSIPLLFAST_Pos (7U) |
| #define | RCC_CR_MSIPLLFAST_Msk (0x1UL << RCC_CR_MSIPLLFAST_Pos) |
| #define | RCC_CR_MSIPLLFAST RCC_CR_MSIPLLFAST_Msk |
| #define | RCC_CR_HSION_Pos (8U) |
| #define | RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) |
| #define | RCC_CR_HSION RCC_CR_HSION_Msk |
| #define | RCC_CR_HSIKERON_Pos (9U) |
| #define | RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) |
| #define | RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk |
| #define | RCC_CR_HSIRDY_Pos (10U) |
| #define | RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) |
| #define | RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk |
| #define | RCC_CR_HSI48ON_Pos (12U) |
| #define | RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) |
| #define | RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk |
| #define | RCC_CR_HSI48RDY_Pos (13U) |
| #define | RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) |
| #define | RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk |
| #define | RCC_CR_SHSION_Pos (14U) |
| #define | RCC_CR_SHSION_Msk (0x1UL << RCC_CR_SHSION_Pos) |
| #define | RCC_CR_SHSION RCC_CR_SHSION_Msk |
| #define | RCC_CR_SHSIRDY_Pos (15U) |
| #define | RCC_CR_SHSIRDY_Msk (0x1UL << RCC_CR_SHSIRDY_Pos) |
| #define | RCC_CR_SHSIRDY RCC_CR_SHSIRDY_Msk |
| #define | RCC_CR_HSEON_Pos (16U) |
| #define | RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) |
| #define | RCC_CR_HSEON RCC_CR_HSEON_Msk |
| #define | RCC_CR_HSERDY_Pos (17U) |
| #define | RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) |
| #define | RCC_CR_HSERDY RCC_CR_HSERDY_Msk |
| #define | RCC_CR_HSEBYP_Pos (18U) |
| #define | RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) |
| #define | RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk |
| #define | RCC_CR_CSSON_Pos (19U) |
| #define | RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) |
| #define | RCC_CR_CSSON RCC_CR_CSSON_Msk |
| #define | RCC_CR_HSEEXT_Pos (20U) |
| #define | RCC_CR_HSEEXT_Msk (0x1UL << RCC_CR_HSEEXT_Pos) |
| #define | RCC_CR_HSEEXT RCC_CR_HSEEXT_Msk |
| #define | RCC_CR_PLL1ON_Pos (24U) |
| #define | RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) |
| #define | RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk |
| #define | RCC_CR_PLL1RDY_Pos (25U) |
| #define | RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) |
| #define | RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk |
| #define | RCC_CR_PLL2ON_Pos (26U) |
| #define | RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) |
| #define | RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk |
| #define | RCC_CR_PLL2RDY_Pos (27U) |
| #define | RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) |
| #define | RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk |
| #define | RCC_CR_PLL3ON_Pos (28U) |
| #define | RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) |
| #define | RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk |
| #define | RCC_CR_PLL3RDY_Pos (29U) |
| #define | RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) |
| #define | RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk |
| #define | RCC_ICSCR1_MSICAL3_Pos (0U) |
| #define | RCC_ICSCR1_MSICAL3_Msk (0x1FUL << RCC_ICSCR1_MSICAL3_Pos) |
| #define | RCC_ICSCR1_MSICAL3 RCC_ICSCR1_MSICAL3_Msk |
| #define | RCC_ICSCR1_MSICAL3_0 (0x01UL << RCC_ICSCR1_MSICAL3_Pos) |
| #define | RCC_ICSCR1_MSICAL3_1 (0x02UL << RCC_ICSCR1_MSICAL3_Pos) |
| #define | RCC_ICSCR1_MSICAL3_2 (0x04UL << RCC_ICSCR1_MSICAL3_Pos) |
| #define | RCC_ICSCR1_MSICAL3_3 (0x08UL << RCC_ICSCR1_MSICAL3_Pos) |
| #define | RCC_ICSCR1_MSICAL3_4 (0x10UL << RCC_ICSCR1_MSICAL3_Pos) |
| #define | RCC_ICSCR1_MSICAL2_Pos (5U) |
| #define | RCC_ICSCR1_MSICAL2_Msk (0x1FUL << RCC_ICSCR1_MSICAL2_Pos) |
| #define | RCC_ICSCR1_MSICAL2 RCC_ICSCR1_MSICAL2_Msk |
| #define | RCC_ICSCR1_MSICAL2_0 (0x01UL << RCC_ICSCR1_MSICAL2_Pos) |
| #define | RCC_ICSCR1_MSICAL2_1 (0x02UL << RCC_ICSCR1_MSICAL2_Pos) |
| #define | RCC_ICSCR1_MSICAL2_2 (0x04UL << RCC_ICSCR1_MSICAL2_Pos) |
| #define | RCC_ICSCR1_MSICAL2_3 (0x08UL << RCC_ICSCR1_MSICAL2_Pos) |
| #define | RCC_ICSCR1_MSICAL2_4 (0x10UL << RCC_ICSCR1_MSICAL2_Pos) |
| #define | RCC_ICSCR1_MSICAL1_Pos (10U) |
| #define | RCC_ICSCR1_MSICAL1_Msk (0x1FUL << RCC_ICSCR1_MSICAL1_Pos) |
| #define | RCC_ICSCR1_MSICAL1 RCC_ICSCR1_MSICAL1_Msk |
| #define | RCC_ICSCR1_MSICAL1_0 (0x01UL << RCC_ICSCR1_MSICAL1_Pos) |
| #define | RCC_ICSCR1_MSICAL1_1 (0x02UL << RCC_ICSCR1_MSICAL1_Pos) |
| #define | RCC_ICSCR1_MSICAL1_2 (0x04UL << RCC_ICSCR1_MSICAL1_Pos) |
| #define | RCC_ICSCR1_MSICAL1_3 (0x08UL << RCC_ICSCR1_MSICAL1_Pos) |
| #define | RCC_ICSCR1_MSICAL1_4 (0x10UL << RCC_ICSCR1_MSICAL1_Pos) |
| #define | RCC_ICSCR1_MSICAL0_Pos (15U) |
| #define | RCC_ICSCR1_MSICAL0_Msk (0x1FUL << RCC_ICSCR1_MSICAL0_Pos) |
| #define | RCC_ICSCR1_MSICAL0 RCC_ICSCR1_MSICAL0_Msk |
| #define | RCC_ICSCR1_MSICAL0_0 (0x01UL << RCC_ICSCR1_MSICAL0_Pos) |
| #define | RCC_ICSCR1_MSICAL0_1 (0x02UL << RCC_ICSCR1_MSICAL0_Pos) |
| #define | RCC_ICSCR1_MSICAL0_2 (0x04UL << RCC_ICSCR1_MSICAL0_Pos) |
| #define | RCC_ICSCR1_MSICAL0_3 (0x08UL << RCC_ICSCR1_MSICAL0_Pos) |
| #define | RCC_ICSCR1_MSICAL0_4 (0x10UL << RCC_ICSCR1_MSICAL0_Pos) |
| #define | RCC_ICSCR1_MSIBIAS_Pos (22U) |
| #define | RCC_ICSCR1_MSIBIAS_Msk (0x1UL << RCC_ICSCR1_MSIBIAS_Pos) |
| #define | RCC_ICSCR1_MSIBIAS RCC_ICSCR1_MSIBIAS_Msk |
| #define | RCC_ICSCR1_MSIRGSEL_Pos (23U) |
| #define | RCC_ICSCR1_MSIRGSEL_Msk (0x1UL << RCC_ICSCR1_MSIRGSEL_Pos) |
| #define | RCC_ICSCR1_MSIRGSEL RCC_ICSCR1_MSIRGSEL_Msk |
| #define | RCC_ICSCR1_MSIKRANGE_Pos (24U) |
| #define | RCC_ICSCR1_MSIKRANGE_Msk (0xFUL << RCC_ICSCR1_MSIKRANGE_Pos) |
| #define | RCC_ICSCR1_MSIKRANGE RCC_ICSCR1_MSIKRANGE_Msk |
| #define | RCC_ICSCR1_MSIKRANGE_0 (0x1UL << RCC_ICSCR1_MSIKRANGE_Pos) |
| #define | RCC_ICSCR1_MSIKRANGE_1 (0x2UL << RCC_ICSCR1_MSIKRANGE_Pos) |
| #define | RCC_ICSCR1_MSIKRANGE_2 (0x4UL << RCC_ICSCR1_MSIKRANGE_Pos) |
| #define | RCC_ICSCR1_MSIKRANGE_3 (0x8UL << RCC_ICSCR1_MSIKRANGE_Pos) |
| #define | RCC_ICSCR1_MSISRANGE_Pos (28U) |
| #define | RCC_ICSCR1_MSISRANGE_Msk (0xFUL << RCC_ICSCR1_MSISRANGE_Pos) |
| #define | RCC_ICSCR1_MSISRANGE RCC_ICSCR1_MSISRANGE_Msk |
| #define | RCC_ICSCR1_MSISRANGE_0 (0x1UL << RCC_ICSCR1_MSISRANGE_Pos) |
| #define | RCC_ICSCR1_MSISRANGE_1 (0x2UL << RCC_ICSCR1_MSISRANGE_Pos) |
| #define | RCC_ICSCR1_MSISRANGE_2 (0x4UL << RCC_ICSCR1_MSISRANGE_Pos) |
| #define | RCC_ICSCR1_MSISRANGE_3 (0x8UL << RCC_ICSCR1_MSISRANGE_Pos) |
| #define | RCC_ICSCR2_MSITRIM3_Pos (0U) |
| #define | RCC_ICSCR2_MSITRIM3_Msk (0x1FUL << RCC_ICSCR2_MSITRIM3_Pos) |
| #define | RCC_ICSCR2_MSITRIM3 RCC_ICSCR2_MSITRIM3_Msk |
| #define | RCC_ICSCR2_MSITRIM3_0 (0x01UL << RCC_ICSCR2_MSITRIM3_Pos) |
| #define | RCC_ICSCR2_MSITRIM3_1 (0x02UL << RCC_ICSCR2_MSITRIM3_Pos) |
| #define | RCC_ICSCR2_MSITRIM3_2 (0x04UL << RCC_ICSCR2_MSITRIM3_Pos) |
| #define | RCC_ICSCR2_MSITRIM3_3 (0x08UL << RCC_ICSCR2_MSITRIM3_Pos) |
| #define | RCC_ICSCR2_MSITRIM3_4 (0x10UL << RCC_ICSCR2_MSITRIM3_Pos) |
| #define | RCC_ICSCR2_MSITRIM2_Pos (5U) |
| #define | RCC_ICSCR2_MSITRIM2_Msk (0x1FUL << RCC_ICSCR2_MSITRIM2_Pos) |
| #define | RCC_ICSCR2_MSITRIM2 RCC_ICSCR2_MSITRIM2_Msk |
| #define | RCC_ICSCR2_MSITRIM2_0 (0x01UL << RCC_ICSCR2_MSITRIM2_Pos) |
| #define | RCC_ICSCR2_MSITRIM2_1 (0x02UL << RCC_ICSCR2_MSITRIM2_Pos) |
| #define | RCC_ICSCR2_MSITRIM2_2 (0x04UL << RCC_ICSCR2_MSITRIM2_Pos) |
| #define | RCC_ICSCR2_MSITRIM2_3 (0x08UL << RCC_ICSCR2_MSITRIM2_Pos) |
| #define | RCC_ICSCR2_MSITRIM2_4 (0x10UL << RCC_ICSCR2_MSITRIM2_Pos) |
| #define | RCC_ICSCR2_MSITRIM1_Pos (10U) |
| #define | RCC_ICSCR2_MSITRIM1_Msk (0x1FUL << RCC_ICSCR2_MSITRIM1_Pos) |
| #define | RCC_ICSCR2_MSITRIM1 RCC_ICSCR2_MSITRIM1_Msk |
| #define | RCC_ICSCR2_MSITRIM1_0 (0x01UL << RCC_ICSCR2_MSITRIM1_Pos) |
| #define | RCC_ICSCR2_MSITRIM1_1 (0x02UL << RCC_ICSCR2_MSITRIM1_Pos) |
| #define | RCC_ICSCR2_MSITRIM1_2 (0x04UL << RCC_ICSCR2_MSITRIM1_Pos) |
| #define | RCC_ICSCR2_MSITRIM1_3 (0x08UL << RCC_ICSCR2_MSITRIM1_Pos) |
| #define | RCC_ICSCR2_MSITRIM1_4 (0x10UL << RCC_ICSCR2_MSITRIM1_Pos) |
| #define | RCC_ICSCR2_MSITRIM0_Pos (15U) |
| #define | RCC_ICSCR2_MSITRIM0_Msk (0x1FUL << RCC_ICSCR2_MSITRIM0_Pos) |
| #define | RCC_ICSCR2_MSITRIM0 RCC_ICSCR2_MSITRIM0_Msk |
| #define | RCC_ICSCR2_MSITRIM0_0 (0x01UL << RCC_ICSCR2_MSITRIM0_Pos) |
| #define | RCC_ICSCR2_MSITRIM0_1 (0x02UL << RCC_ICSCR2_MSITRIM0_Pos) |
| #define | RCC_ICSCR2_MSITRIM0_2 (0x04UL << RCC_ICSCR2_MSITRIM0_Pos) |
| #define | RCC_ICSCR2_MSITRIM0_3 (0x08UL << RCC_ICSCR2_MSITRIM0_Pos) |
| #define | RCC_ICSCR2_MSITRIM0_4 (0x10UL << RCC_ICSCR2_MSITRIM0_Pos) |
| #define | RCC_ICSCR3_HSICAL_Pos (0U) |
| #define | RCC_ICSCR3_HSICAL_Msk (0xFFFUL << RCC_ICSCR3_HSICAL_Pos) |
| #define | RCC_ICSCR3_HSICAL RCC_ICSCR3_HSICAL_Msk |
| #define | RCC_ICSCR3_HSICAL_0 (0x001UL << RCC_ICSCR3_HSICAL_Pos) |
| #define | RCC_ICSCR3_HSICAL_1 (0x002UL << RCC_ICSCR3_HSICAL_Pos) |
| #define | RCC_ICSCR3_HSICAL_2 (0x004UL << RCC_ICSCR3_HSICAL_Pos) |
| #define | RCC_ICSCR3_HSICAL_3 (0x008UL << RCC_ICSCR3_HSICAL_Pos) |
| #define | RCC_ICSCR3_HSICAL_4 (0x010UL << RCC_ICSCR3_HSICAL_Pos) |
| #define | RCC_ICSCR3_HSICAL_5 (0x020UL << RCC_ICSCR3_HSICAL_Pos) |
| #define | RCC_ICSCR3_HSICAL_6 (0x040UL << RCC_ICSCR3_HSICAL_Pos) |
| #define | RCC_ICSCR3_HSICAL_7 (0x080UL << RCC_ICSCR3_HSICAL_Pos) |
| #define | RCC_ICSCR3_HSICAL_8 (0x100UL << RCC_ICSCR3_HSICAL_Pos) |
| #define | RCC_ICSCR3_HSICAL_9 (0x200UL << RCC_ICSCR3_HSICAL_Pos) |
| #define | RCC_ICSCR3_HSICAL_10 (0x400UL << RCC_ICSCR3_HSICAL_Pos) |
| #define | RCC_ICSCR3_HSICAL_11 (0x800UL << RCC_ICSCR3_HSICAL_Pos) |
| #define | RCC_ICSCR3_HSITRIM_Pos (16U) |
| #define | RCC_ICSCR3_HSITRIM_Msk (0x1FUL << RCC_ICSCR3_HSITRIM_Pos) |
| #define | RCC_ICSCR3_HSITRIM RCC_ICSCR3_HSITRIM_Msk |
| #define | RCC_ICSCR3_HSITRIM_0 (0x01UL << RCC_ICSCR3_HSITRIM_Pos) |
| #define | RCC_ICSCR3_HSITRIM_1 (0x02UL << RCC_ICSCR3_HSITRIM_Pos) |
| #define | RCC_ICSCR3_HSITRIM_2 (0x04UL << RCC_ICSCR3_HSITRIM_Pos) |
| #define | RCC_ICSCR3_HSITRIM_3 (0x08UL << RCC_ICSCR3_HSITRIM_Pos) |
| #define | RCC_ICSCR3_HSITRIM_4 (0x10UL << RCC_ICSCR3_HSITRIM_Pos) |
| #define | RCC_CRRCR_HSI48CAL_Pos (0U) |
| #define | RCC_CRRCR_HSI48CAL_Msk (0x1FFUL << RCC_CRRCR_HSI48CAL_Pos) |
| #define | RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk |
| #define | RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) |
| #define | RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) |
| #define | RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) |
| #define | RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) |
| #define | RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) |
| #define | RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) |
| #define | RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) |
| #define | RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) |
| #define | RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) |
| #define | RCC_CFGR1_SW_Pos (0U) |
| #define | RCC_CFGR1_SW_Msk (0x3UL << RCC_CFGR1_SW_Pos) |
| #define | RCC_CFGR1_SW RCC_CFGR1_SW_Msk |
| #define | RCC_CFGR1_SW_0 (0x1UL << RCC_CFGR1_SW_Pos) |
| #define | RCC_CFGR1_SW_1 (0x2UL << RCC_CFGR1_SW_Pos) |
| #define | RCC_CFGR1_SWS_Pos (2U) |
| #define | RCC_CFGR1_SWS_Msk (0x3UL << RCC_CFGR1_SWS_Pos) |
| #define | RCC_CFGR1_SWS RCC_CFGR1_SWS_Msk |
| #define | RCC_CFGR1_SWS_0 (0x1UL << RCC_CFGR1_SWS_Pos) |
| #define | RCC_CFGR1_SWS_1 (0x2UL << RCC_CFGR1_SWS_Pos) |
| #define | RCC_CFGR1_STOPWUCK_Pos (4U) |
| #define | RCC_CFGR1_STOPWUCK_Msk (0x1UL << RCC_CFGR1_STOPWUCK_Pos) |
| #define | RCC_CFGR1_STOPWUCK RCC_CFGR1_STOPWUCK_Msk |
| #define | RCC_CFGR1_STOPKERWUCK_Pos (5U) |
| #define | RCC_CFGR1_STOPKERWUCK_Msk (0x1UL << RCC_CFGR1_STOPKERWUCK_Pos) |
| #define | RCC_CFGR1_STOPKERWUCK RCC_CFGR1_STOPKERWUCK_Msk |
| #define | RCC_CFGR1_MCOSEL_Pos (24U) |
| #define | RCC_CFGR1_MCOSEL_Msk (0xFUL << RCC_CFGR1_MCOSEL_Pos) |
| #define | RCC_CFGR1_MCOSEL RCC_CFGR1_MCOSEL_Msk |
| #define | RCC_CFGR1_MCOSEL_0 (0x1UL << RCC_CFGR1_MCOSEL_Pos) |
| #define | RCC_CFGR1_MCOSEL_1 (0x2UL << RCC_CFGR1_MCOSEL_Pos) |
| #define | RCC_CFGR1_MCOSEL_2 (0x4UL << RCC_CFGR1_MCOSEL_Pos) |
| #define | RCC_CFGR1_MCOSEL_3 (0x8UL << RCC_CFGR1_MCOSEL_Pos) |
| #define | RCC_CFGR1_MCOPRE_Pos (28U) |
| #define | RCC_CFGR1_MCOPRE_Msk (0x7UL << RCC_CFGR1_MCOPRE_Pos) |
| #define | RCC_CFGR1_MCOPRE RCC_CFGR1_MCOPRE_Msk |
| #define | RCC_CFGR1_MCOPRE_0 (0x1UL << RCC_CFGR1_MCOPRE_Pos) |
| #define | RCC_CFGR1_MCOPRE_1 (0x2UL << RCC_CFGR1_MCOPRE_Pos) |
| #define | RCC_CFGR1_MCOPRE_2 (0x4UL << RCC_CFGR1_MCOPRE_Pos) |
| #define | RCC_CFGR2_HPRE_Pos (0U) |
| #define | RCC_CFGR2_HPRE_Msk (0xFUL << RCC_CFGR2_HPRE_Pos) |
| #define | RCC_CFGR2_HPRE RCC_CFGR2_HPRE_Msk |
| #define | RCC_CFGR2_HPRE_0 (0x1UL << RCC_CFGR2_HPRE_Pos) |
| #define | RCC_CFGR2_HPRE_1 (0x2UL << RCC_CFGR2_HPRE_Pos) |
| #define | RCC_CFGR2_HPRE_2 (0x4UL << RCC_CFGR2_HPRE_Pos) |
| #define | RCC_CFGR2_HPRE_3 (0x8UL << RCC_CFGR2_HPRE_Pos) |
| #define | RCC_CFGR2_PPRE1_Pos (4U) |
| #define | RCC_CFGR2_PPRE1_Msk (0x7UL << RCC_CFGR2_PPRE1_Pos) |
| #define | RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_Msk |
| #define | RCC_CFGR2_PPRE1_0 (0x1UL << RCC_CFGR2_PPRE1_Pos) |
| #define | RCC_CFGR2_PPRE1_1 (0x2UL << RCC_CFGR2_PPRE1_Pos) |
| #define | RCC_CFGR2_PPRE1_2 (0x4UL << RCC_CFGR2_PPRE1_Pos) |
| #define | RCC_CFGR2_PPRE2_Pos (8U) |
| #define | RCC_CFGR2_PPRE2_Msk (0x7UL << RCC_CFGR2_PPRE2_Pos) |
| #define | RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_Msk |
| #define | RCC_CFGR2_PPRE2_0 (0x1UL << RCC_CFGR2_PPRE2_Pos) |
| #define | RCC_CFGR2_PPRE2_1 (0x2UL << RCC_CFGR2_PPRE2_Pos) |
| #define | RCC_CFGR2_PPRE2_2 (0x4UL << RCC_CFGR2_PPRE2_Pos) |
| #define | RCC_CFGR2_PPRE_DPHY_Pos (12U) |
| #define | RCC_CFGR2_PPRE_DPHY_Msk (0x7UL << RCC_CFGR2_PPRE_DPHY_Pos) |
| #define | RCC_CFGR2_PPRE_DPHY RCC_CFGR2_PPRE_DPHY_Msk |
| #define | RCC_CFGR2_PPRE_DPHY_0 (0x1UL << RCC_CFGR2_PPRE_DPHY_Pos) |
| #define | RCC_CFGR2_PPRE_DPHY_1 (0x2UL << RCC_CFGR2_PPRE_DPHY_Pos) |
| #define | RCC_CFGR2_PPRE_DPHY_2 (0x4UL << RCC_CFGR2_PPRE_DPHY_Pos) |
| #define | RCC_CFGR2_AHB1DIS_Pos (16U) |
| #define | RCC_CFGR2_AHB1DIS_Msk (0x1UL << RCC_CFGR2_AHB1DIS_Pos) |
| #define | RCC_CFGR2_AHB1DIS RCC_CFGR2_AHB1DIS_Msk |
| #define | RCC_CFGR2_AHB2DIS1_Pos (17U) |
| #define | RCC_CFGR2_AHB2DIS1_Msk (0x1UL << RCC_CFGR2_AHB2DIS1_Pos) |
| #define | RCC_CFGR2_AHB2DIS1 RCC_CFGR2_AHB2DIS1_Msk |
| #define | RCC_CFGR2_AHB2DIS2_Pos (18U) |
| #define | RCC_CFGR2_AHB2DIS2_Msk (0x1UL << RCC_CFGR2_AHB2DIS2_Pos) |
| #define | RCC_CFGR2_AHB2DIS2 RCC_CFGR2_AHB2DIS2_Msk |
| #define | RCC_CFGR2_APB1DIS_Pos (19U) |
| #define | RCC_CFGR2_APB1DIS_Msk (0x1UL << RCC_CFGR2_APB1DIS_Pos) |
| #define | RCC_CFGR2_APB1DIS RCC_CFGR2_APB1DIS_Msk |
| #define | RCC_CFGR2_APB2DIS_Pos (20U) |
| #define | RCC_CFGR2_APB2DIS_Msk (0x1UL << RCC_CFGR2_APB2DIS_Pos) |
| #define | RCC_CFGR2_APB2DIS RCC_CFGR2_APB2DIS_Msk |
| #define | RCC_CFGR3_PPRE3_Pos (4U) |
| #define | RCC_CFGR3_PPRE3_Msk (0x7UL << RCC_CFGR3_PPRE3_Pos) |
| #define | RCC_CFGR3_PPRE3 RCC_CFGR3_PPRE3_Msk |
| #define | RCC_CFGR3_PPRE3_0 (0x1UL << RCC_CFGR3_PPRE3_Pos) |
| #define | RCC_CFGR3_PPRE3_1 (0x2UL << RCC_CFGR3_PPRE3_Pos) |
| #define | RCC_CFGR3_PPRE3_2 (0x4UL << RCC_CFGR3_PPRE3_Pos) |
| #define | RCC_CFGR3_AHB3DIS_Pos (16U) |
| #define | RCC_CFGR3_AHB3DIS_Msk (0x1UL << RCC_CFGR3_AHB3DIS_Pos) |
| #define | RCC_CFGR3_AHB3DIS RCC_CFGR3_AHB3DIS_Msk |
| #define | RCC_CFGR3_APB3DIS_Pos (17U) |
| #define | RCC_CFGR3_APB3DIS_Msk (0x1UL << RCC_CFGR3_APB3DIS_Pos) |
| #define | RCC_CFGR3_APB3DIS RCC_CFGR3_APB3DIS_Msk |
| #define | RCC_PLL1CFGR_PLL1SRC_Pos (0U) |
| #define | RCC_PLL1CFGR_PLL1SRC_Msk (0x3UL << RCC_PLL1CFGR_PLL1SRC_Pos) |
| #define | RCC_PLL1CFGR_PLL1SRC RCC_PLL1CFGR_PLL1SRC_Msk |
| #define | RCC_PLL1CFGR_PLL1SRC_0 (0x1UL << RCC_PLL1CFGR_PLL1SRC_Pos) |
| #define | RCC_PLL1CFGR_PLL1SRC_1 (0x2UL << RCC_PLL1CFGR_PLL1SRC_Pos) |
| #define | RCC_PLL1CFGR_PLL1RGE_Pos (2U) |
| #define | RCC_PLL1CFGR_PLL1RGE_Msk (0x3UL << RCC_PLL1CFGR_PLL1RGE_Pos) |
| #define | RCC_PLL1CFGR_PLL1RGE RCC_PLL1CFGR_PLL1RGE_Msk |
| #define | RCC_PLL1CFGR_PLL1RGE_0 (0x1UL << RCC_PLL1CFGR_PLL1RGE_Pos) |
| #define | RCC_PLL1CFGR_PLL1RGE_1 (0x2UL << RCC_PLL1CFGR_PLL1RGE_Pos) |
| #define | RCC_PLL1CFGR_PLL1FRACEN_Pos (4U) |
| #define | RCC_PLL1CFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1FRACEN_Pos) |
| #define | RCC_PLL1CFGR_PLL1FRACEN RCC_PLL1CFGR_PLL1FRACEN_Msk |
| #define | RCC_PLL1CFGR_PLL1M_Pos (8U) |
| #define | RCC_PLL1CFGR_PLL1M_Msk (0xFUL << RCC_PLL1CFGR_PLL1M_Pos) |
| #define | RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M_Msk |
| #define | RCC_PLL1CFGR_PLL1M_0 (0x01UL << RCC_PLL1CFGR_PLL1M_Pos) |
| #define | RCC_PLL1CFGR_PLL1M_1 (0x02UL << RCC_PLL1CFGR_PLL1M_Pos) |
| #define | RCC_PLL1CFGR_PLL1M_2 (0x04UL << RCC_PLL1CFGR_PLL1M_Pos) |
| #define | RCC_PLL1CFGR_PLL1M_3 (0x08UL << RCC_PLL1CFGR_PLL1M_Pos) |
| #define | RCC_PLL1CFGR_PLL1MBOOST_Pos (12U) |
| #define | RCC_PLL1CFGR_PLL1MBOOST_Msk (0xFUL << RCC_PLL1CFGR_PLL1MBOOST_Pos) |
| #define | RCC_PLL1CFGR_PLL1MBOOST RCC_PLL1CFGR_PLL1MBOOST_Msk |
| #define | RCC_PLL1CFGR_PLL1MBOOST_0 (0x01UL << RCC_PLL1CFGR_PLL1MBOOST_Pos) |
| #define | RCC_PLL1CFGR_PLL1MBOOST_1 (0x02UL << RCC_PLL1CFGR_PLL1MBOOST_Pos) |
| #define | RCC_PLL1CFGR_PLL1MBOOST_2 (0x04UL << RCC_PLL1CFGR_PLL1MBOOST_Pos) |
| #define | RCC_PLL1CFGR_PLL1MBOOST_3 (0x08UL << RCC_PLL1CFGR_PLL1MBOOST_Pos) |
| #define | RCC_PLL1CFGR_PLL1PEN_Pos (16U) |
| #define | RCC_PLL1CFGR_PLL1PEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1PEN_Pos) |
| #define | RCC_PLL1CFGR_PLL1PEN RCC_PLL1CFGR_PLL1PEN_Msk |
| #define | RCC_PLL1CFGR_PLL1QEN_Pos (17U) |
| #define | RCC_PLL1CFGR_PLL1QEN_Msk (0x1UL << RCC_PLL1CFGR_PLL1QEN_Pos) |
| #define | RCC_PLL1CFGR_PLL1QEN RCC_PLL1CFGR_PLL1QEN_Msk |
| #define | RCC_PLL1CFGR_PLL1REN_Pos (18U) |
| #define | RCC_PLL1CFGR_PLL1REN_Msk (0x1UL << RCC_PLL1CFGR_PLL1REN_Pos) |
| #define | RCC_PLL1CFGR_PLL1REN RCC_PLL1CFGR_PLL1REN_Msk |
| #define | RCC_PLL2CFGR_PLL2SRC_Pos (0U) |
| #define | RCC_PLL2CFGR_PLL2SRC_Msk (0x3UL << RCC_PLL2CFGR_PLL2SRC_Pos) |
| #define | RCC_PLL2CFGR_PLL2SRC RCC_PLL2CFGR_PLL2SRC_Msk |
| #define | RCC_PLL2CFGR_PLL2SRC_0 (0x1UL << RCC_PLL2CFGR_PLL2SRC_Pos) |
| #define | RCC_PLL2CFGR_PLL2SRC_1 (0x2UL << RCC_PLL2CFGR_PLL2SRC_Pos) |
| #define | RCC_PLL2CFGR_PLL2RGE_Pos (2U) |
| #define | RCC_PLL2CFGR_PLL2RGE_Msk (0x3UL << RCC_PLL2CFGR_PLL2RGE_Pos) |
| #define | RCC_PLL2CFGR_PLL2RGE RCC_PLL2CFGR_PLL2RGE_Msk |
| #define | RCC_PLL2CFGR_PLL2RGE_0 (0x1UL << RCC_PLL2CFGR_PLL2RGE_Pos) |
| #define | RCC_PLL2CFGR_PLL2RGE_1 (0x2UL << RCC_PLL2CFGR_PLL2RGE_Pos) |
| #define | RCC_PLL2CFGR_PLL2FRACEN_Pos (4U) |
| #define | RCC_PLL2CFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLL2CFGR_PLL2FRACEN_Pos) |
| #define | RCC_PLL2CFGR_PLL2FRACEN RCC_PLL2CFGR_PLL2FRACEN_Msk |
| #define | RCC_PLL2CFGR_PLL2M_Pos (8U) |
| #define | RCC_PLL2CFGR_PLL2M_Msk (0xFUL << RCC_PLL2CFGR_PLL2M_Pos) |
| #define | RCC_PLL2CFGR_PLL2M RCC_PLL2CFGR_PLL2M_Msk |
| #define | RCC_PLL2CFGR_PLL2M_0 (0x01UL << RCC_PLL2CFGR_PLL2M_Pos) |
| #define | RCC_PLL2CFGR_PLL2M_1 (0x02UL << RCC_PLL2CFGR_PLL2M_Pos) |
| #define | RCC_PLL2CFGR_PLL2M_2 (0x04UL << RCC_PLL2CFGR_PLL2M_Pos) |
| #define | RCC_PLL2CFGR_PLL2M_3 (0x08UL << RCC_PLL2CFGR_PLL2M_Pos) |
| #define | RCC_PLL2CFGR_PLL2PEN_Pos (16U) |
| #define | RCC_PLL2CFGR_PLL2PEN_Msk (0x1UL << RCC_PLL2CFGR_PLL2PEN_Pos) |
| #define | RCC_PLL2CFGR_PLL2PEN RCC_PLL2CFGR_PLL2PEN_Msk |
| #define | RCC_PLL2CFGR_PLL2QEN_Pos (17U) |
| #define | RCC_PLL2CFGR_PLL2QEN_Msk (0x1UL << RCC_PLL2CFGR_PLL2QEN_Pos) |
| #define | RCC_PLL2CFGR_PLL2QEN RCC_PLL2CFGR_PLL2QEN_Msk |
| #define | RCC_PLL2CFGR_PLL2REN_Pos (18U) |
| #define | RCC_PLL2CFGR_PLL2REN_Msk (0x1UL << RCC_PLL2CFGR_PLL2REN_Pos) |
| #define | RCC_PLL2CFGR_PLL2REN RCC_PLL2CFGR_PLL2REN_Msk |
| #define | RCC_PLL3CFGR_PLL3SRC_Pos (0U) |
| #define | RCC_PLL3CFGR_PLL3SRC_Msk (0x3UL << RCC_PLL3CFGR_PLL3SRC_Pos) |
| #define | RCC_PLL3CFGR_PLL3SRC RCC_PLL3CFGR_PLL3SRC_Msk |
| #define | RCC_PLL3CFGR_PLL3SRC_0 (0x1UL << RCC_PLL3CFGR_PLL3SRC_Pos) |
| #define | RCC_PLL3CFGR_PLL3SRC_1 (0x2UL << RCC_PLL3CFGR_PLL3SRC_Pos) |
| #define | RCC_PLL3CFGR_PLL3RGE_Pos (2U) |
| #define | RCC_PLL3CFGR_PLL3RGE_Msk (0x3UL << RCC_PLL3CFGR_PLL3RGE_Pos) |
| #define | RCC_PLL3CFGR_PLL3RGE RCC_PLL3CFGR_PLL3RGE_Msk |
| #define | RCC_PLL3CFGR_PLL3RGE_0 (0x1UL << RCC_PLL3CFGR_PLL3RGE_Pos) |
| #define | RCC_PLL3CFGR_PLL3RGE_1 (0x2UL << RCC_PLL3CFGR_PLL3RGE_Pos) |
| #define | RCC_PLL3CFGR_PLL3FRACEN_Pos (4U) |
| #define | RCC_PLL3CFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLL3CFGR_PLL3FRACEN_Pos) |
| #define | RCC_PLL3CFGR_PLL3FRACEN RCC_PLL3CFGR_PLL3FRACEN_Msk |
| #define | RCC_PLL3CFGR_PLL3M_Pos (8U) |
| #define | RCC_PLL3CFGR_PLL3M_Msk (0xFUL << RCC_PLL3CFGR_PLL3M_Pos) |
| #define | RCC_PLL3CFGR_PLL3M RCC_PLL3CFGR_PLL3M_Msk |
| #define | RCC_PLL3CFGR_PLL3M_0 (0x01UL << RCC_PLL3CFGR_PLL3M_Pos) |
| #define | RCC_PLL3CFGR_PLL3M_1 (0x02UL << RCC_PLL3CFGR_PLL3M_Pos) |
| #define | RCC_PLL3CFGR_PLL3M_2 (0x04UL << RCC_PLL3CFGR_PLL3M_Pos) |
| #define | RCC_PLL3CFGR_PLL3M_3 (0x08UL << RCC_PLL3CFGR_PLL3M_Pos) |
| #define | RCC_PLL3CFGR_PLL3PEN_Pos (16U) |
| #define | RCC_PLL3CFGR_PLL3PEN_Msk (0x1UL << RCC_PLL3CFGR_PLL3PEN_Pos) |
| #define | RCC_PLL3CFGR_PLL3PEN RCC_PLL3CFGR_PLL3PEN_Msk |
| #define | RCC_PLL3CFGR_PLL3QEN_Pos (17U) |
| #define | RCC_PLL3CFGR_PLL3QEN_Msk (0x1UL << RCC_PLL3CFGR_PLL3QEN_Pos) |
| #define | RCC_PLL3CFGR_PLL3QEN RCC_PLL3CFGR_PLL3QEN_Msk |
| #define | RCC_PLL3CFGR_PLL3REN_Pos (18U) |
| #define | RCC_PLL3CFGR_PLL3REN_Msk (0x1UL << RCC_PLL3CFGR_PLL3REN_Pos) |
| #define | RCC_PLL3CFGR_PLL3REN RCC_PLL3CFGR_PLL3REN_Msk |
| #define | RCC_PLL1DIVR_PLL1N_Pos (0U) |
| #define | RCC_PLL1DIVR_PLL1N_Msk (0x1FFUL << RCC_PLL1DIVR_PLL1N_Pos) |
| #define | RCC_PLL1DIVR_PLL1N RCC_PLL1DIVR_PLL1N_Msk |
| #define | RCC_PLL1DIVR_PLL1N_0 (0x001UL << RCC_PLL1DIVR_PLL1N_Pos) |
| #define | RCC_PLL1DIVR_PLL1N_1 (0x002UL << RCC_PLL1DIVR_PLL1N_Pos) |
| #define | RCC_PLL1DIVR_PLL1N_2 (0x004UL << RCC_PLL1DIVR_PLL1N_Pos) |
| #define | RCC_PLL1DIVR_PLL1N_3 (0x008UL << RCC_PLL1DIVR_PLL1N_Pos) |
| #define | RCC_PLL1DIVR_PLL1N_4 (0x010UL << RCC_PLL1DIVR_PLL1N_Pos) |
| #define | RCC_PLL1DIVR_PLL1N_5 (0x020UL << RCC_PLL1DIVR_PLL1N_Pos) |
| #define | RCC_PLL1DIVR_PLL1N_6 (0x040UL << RCC_PLL1DIVR_PLL1N_Pos) |
| #define | RCC_PLL1DIVR_PLL1N_7 (0x080UL << RCC_PLL1DIVR_PLL1N_Pos) |
| #define | RCC_PLL1DIVR_PLL1N_8 (0x100UL << RCC_PLL1DIVR_PLL1N_Pos) |
| #define | RCC_PLL1DIVR_PLL1P_Pos (9U) |
| #define | RCC_PLL1DIVR_PLL1P_Msk (0x7FUL << RCC_PLL1DIVR_PLL1P_Pos) |
| #define | RCC_PLL1DIVR_PLL1P RCC_PLL1DIVR_PLL1P_Msk |
| #define | RCC_PLL1DIVR_PLL1P_0 (0x001UL << RCC_PLL1DIVR_PLL1P_Pos) |
| #define | RCC_PLL1DIVR_PLL1P_1 (0x002UL << RCC_PLL1DIVR_PLL1P_Pos) |
| #define | RCC_PLL1DIVR_PLL1P_2 (0x004UL << RCC_PLL1DIVR_PLL1P_Pos) |
| #define | RCC_PLL1DIVR_PLL1P_3 (0x008UL << RCC_PLL1DIVR_PLL1P_Pos) |
| #define | RCC_PLL1DIVR_PLL1P_4 (0x010UL << RCC_PLL1DIVR_PLL1P_Pos) |
| #define | RCC_PLL1DIVR_PLL1P_5 (0x020UL << RCC_PLL1DIVR_PLL1P_Pos) |
| #define | RCC_PLL1DIVR_PLL1P_6 (0x040UL << RCC_PLL1DIVR_PLL1P_Pos) |
| #define | RCC_PLL1DIVR_PLL1Q_Pos (16U) |
| #define | RCC_PLL1DIVR_PLL1Q_Msk (0x7FUL << RCC_PLL1DIVR_PLL1Q_Pos) |
| #define | RCC_PLL1DIVR_PLL1Q RCC_PLL1DIVR_PLL1Q_Msk |
| #define | RCC_PLL1DIVR_PLL1Q_0 (0x001UL << RCC_PLL1DIVR_PLL1Q_Pos) |
| #define | RCC_PLL1DIVR_PLL1Q_1 (0x002UL << RCC_PLL1DIVR_PLL1Q_Pos) |
| #define | RCC_PLL1DIVR_PLL1Q_2 (0x004UL << RCC_PLL1DIVR_PLL1Q_Pos) |
| #define | RCC_PLL1DIVR_PLL1Q_3 (0x008UL << RCC_PLL1DIVR_PLL1Q_Pos) |
| #define | RCC_PLL1DIVR_PLL1Q_4 (0x010UL << RCC_PLL1DIVR_PLL1Q_Pos) |
| #define | RCC_PLL1DIVR_PLL1Q_5 (0x020UL << RCC_PLL1DIVR_PLL1Q_Pos) |
| #define | RCC_PLL1DIVR_PLL1Q_6 (0x040UL << RCC_PLL1DIVR_PLL1Q_Pos) |
| #define | RCC_PLL1DIVR_PLL1R_Pos (24U) |
| #define | RCC_PLL1DIVR_PLL1R_Msk (0x7FUL << RCC_PLL1DIVR_PLL1R_Pos) |
| #define | RCC_PLL1DIVR_PLL1R RCC_PLL1DIVR_PLL1R_Msk |
| #define | RCC_PLL1DIVR_PLL1R_0 (0x001UL << RCC_PLL1DIVR_PLL1R_Pos) |
| #define | RCC_PLL1DIVR_PLL1R_1 (0x002UL << RCC_PLL1DIVR_PLL1R_Pos) |
| #define | RCC_PLL1DIVR_PLL1R_2 (0x004UL << RCC_PLL1DIVR_PLL1R_Pos) |
| #define | RCC_PLL1DIVR_PLL1R_3 (0x008UL << RCC_PLL1DIVR_PLL1R_Pos) |
| #define | RCC_PLL1DIVR_PLL1R_4 (0x010UL << RCC_PLL1DIVR_PLL1R_Pos) |
| #define | RCC_PLL1DIVR_PLL1R_5 (0x020UL << RCC_PLL1DIVR_PLL1R_Pos) |
| #define | RCC_PLL1DIVR_PLL1R_6 (0x040UL << RCC_PLL1DIVR_PLL1R_Pos) |
| #define | RCC_PLL1FRACR_PLL1FRACN_Pos (3U) |
| #define | RCC_PLL1FRACR_PLL1FRACN_Msk (0x1FFFUL << RCC_PLL1FRACR_PLL1FRACN_Pos) |
| #define | RCC_PLL1FRACR_PLL1FRACN RCC_PLL1FRACR_PLL1FRACN_Msk |
| #define | RCC_PLL1FRACR_PLL1FRACN_0 (0x0001UL << RCC_PLL1FRACR_PLL1FRACN_Pos) |
| #define | RCC_PLL1FRACR_PLL1FRACN_1 (0x0002UL << RCC_PLL1FRACR_PLL1FRACN_Pos) |
| #define | RCC_PLL1FRACR_PLL1FRACN_2 (0x0004UL << RCC_PLL1FRACR_PLL1FRACN_Pos) |
| #define | RCC_PLL1FRACR_PLL1FRACN_3 (0x0008UL << RCC_PLL1FRACR_PLL1FRACN_Pos) |
| #define | RCC_PLL1FRACR_PLL1FRACN_4 (0x0010UL << RCC_PLL1FRACR_PLL1FRACN_Pos) |
| #define | RCC_PLL1FRACR_PLL1FRACN_5 (0x0020UL << RCC_PLL1FRACR_PLL1FRACN_Pos) |
| #define | RCC_PLL1FRACR_PLL1FRACN_6 (0x0040UL << RCC_PLL1FRACR_PLL1FRACN_Pos) |
| #define | RCC_PLL1FRACR_PLL1FRACN_7 (0x0080UL << RCC_PLL1FRACR_PLL1FRACN_Pos) |
| #define | RCC_PLL1FRACR_PLL1FRACN_8 (0x0100UL << RCC_PLL1FRACR_PLL1FRACN_Pos) |
| #define | RCC_PLL1FRACR_PLL1FRACN_9 (0x0200UL << RCC_PLL1FRACR_PLL1FRACN_Pos) |
| #define | RCC_PLL1FRACR_PLL1FRACN_10 (0x0400UL << RCC_PLL1FRACR_PLL1FRACN_Pos) |
| #define | RCC_PLL1FRACR_PLL1FRACN_11 (0x0800UL << RCC_PLL1FRACR_PLL1FRACN_Pos) |
| #define | RCC_PLL1FRACR_PLL1FRACN_12 (0x1000UL << RCC_PLL1FRACR_PLL1FRACN_Pos) |
| #define | RCC_PLL2DIVR_PLL2N_Pos (0U) |
| #define | RCC_PLL2DIVR_PLL2N_Msk (0x1FFUL << RCC_PLL2DIVR_PLL2N_Pos) |
| #define | RCC_PLL2DIVR_PLL2N RCC_PLL2DIVR_PLL2N_Msk |
| #define | RCC_PLL2DIVR_PLL2N_0 (0x001UL << RCC_PLL2DIVR_PLL2N_Pos) |
| #define | RCC_PLL2DIVR_PLL2N_1 (0x002UL << RCC_PLL2DIVR_PLL2N_Pos) |
| #define | RCC_PLL2DIVR_PLL2N_2 (0x004UL << RCC_PLL2DIVR_PLL2N_Pos) |
| #define | RCC_PLL2DIVR_PLL2N_3 (0x008UL << RCC_PLL2DIVR_PLL2N_Pos) |
| #define | RCC_PLL2DIVR_PLL2N_4 (0x010UL << RCC_PLL2DIVR_PLL2N_Pos) |
| #define | RCC_PLL2DIVR_PLL2N_5 (0x020UL << RCC_PLL2DIVR_PLL2N_Pos) |
| #define | RCC_PLL2DIVR_PLL2N_6 (0x040UL << RCC_PLL2DIVR_PLL2N_Pos) |
| #define | RCC_PLL2DIVR_PLL2N_7 (0x080UL << RCC_PLL2DIVR_PLL2N_Pos) |
| #define | RCC_PLL2DIVR_PLL2N_8 (0x100UL << RCC_PLL2DIVR_PLL2N_Pos) |
| #define | RCC_PLL2DIVR_PLL2P_Pos (9U) |
| #define | RCC_PLL2DIVR_PLL2P_Msk (0x7FUL << RCC_PLL2DIVR_PLL2P_Pos) |
| #define | RCC_PLL2DIVR_PLL2P RCC_PLL2DIVR_PLL2P_Msk |
| #define | RCC_PLL2DIVR_PLL2P_0 (0x001UL << RCC_PLL2DIVR_PLL2P_Pos) |
| #define | RCC_PLL2DIVR_PLL2P_1 (0x002UL << RCC_PLL2DIVR_PLL2P_Pos) |
| #define | RCC_PLL2DIVR_PLL2P_2 (0x004UL << RCC_PLL2DIVR_PLL2P_Pos) |
| #define | RCC_PLL2DIVR_PLL2P_3 (0x008UL << RCC_PLL2DIVR_PLL2P_Pos) |
| #define | RCC_PLL2DIVR_PLL2P_4 (0x010UL << RCC_PLL2DIVR_PLL2P_Pos) |
| #define | RCC_PLL2DIVR_PLL2P_5 (0x020UL << RCC_PLL2DIVR_PLL2P_Pos) |
| #define | RCC_PLL2DIVR_PLL2P_6 (0x040UL << RCC_PLL2DIVR_PLL2P_Pos) |
| #define | RCC_PLL2DIVR_PLL2Q_Pos (16U) |
| #define | RCC_PLL2DIVR_PLL2Q_Msk (0x7FUL << RCC_PLL2DIVR_PLL2Q_Pos) |
| #define | RCC_PLL2DIVR_PLL2Q RCC_PLL2DIVR_PLL2Q_Msk |
| #define | RCC_PLL2DIVR_PLL2Q_0 (0x001UL << RCC_PLL2DIVR_PLL2Q_Pos) |
| #define | RCC_PLL2DIVR_PLL2Q_1 (0x002UL << RCC_PLL2DIVR_PLL2Q_Pos) |
| #define | RCC_PLL2DIVR_PLL2Q_2 (0x004UL << RCC_PLL2DIVR_PLL2Q_Pos) |
| #define | RCC_PLL2DIVR_PLL2Q_3 (0x008UL << RCC_PLL2DIVR_PLL2Q_Pos) |
| #define | RCC_PLL2DIVR_PLL2Q_4 (0x010UL << RCC_PLL2DIVR_PLL2Q_Pos) |
| #define | RCC_PLL2DIVR_PLL2Q_5 (0x020UL << RCC_PLL2DIVR_PLL2Q_Pos) |
| #define | RCC_PLL2DIVR_PLL2Q_6 (0x040UL << RCC_PLL2DIVR_PLL2Q_Pos) |
| #define | RCC_PLL2DIVR_PLL2R_Pos (24U) |
| #define | RCC_PLL2DIVR_PLL2R_Msk (0x7FUL << RCC_PLL2DIVR_PLL2R_Pos) |
| #define | RCC_PLL2DIVR_PLL2R RCC_PLL2DIVR_PLL2R_Msk |
| #define | RCC_PLL2DIVR_PLL2R_0 (0x001UL << RCC_PLL2DIVR_PLL2R_Pos) |
| #define | RCC_PLL2DIVR_PLL2R_1 (0x002UL << RCC_PLL2DIVR_PLL2R_Pos) |
| #define | RCC_PLL2DIVR_PLL2R_2 (0x004UL << RCC_PLL2DIVR_PLL2R_Pos) |
| #define | RCC_PLL2DIVR_PLL2R_3 (0x008UL << RCC_PLL2DIVR_PLL2R_Pos) |
| #define | RCC_PLL2DIVR_PLL2R_4 (0x010UL << RCC_PLL2DIVR_PLL2R_Pos) |
| #define | RCC_PLL2DIVR_PLL2R_5 (0x020UL << RCC_PLL2DIVR_PLL2R_Pos) |
| #define | RCC_PLL2DIVR_PLL2R_6 (0x040UL << RCC_PLL2DIVR_PLL2R_Pos) |
| #define | RCC_PLL2FRACR_PLL2FRACN_Pos (3U) |
| #define | RCC_PLL2FRACR_PLL2FRACN_Msk (0x1FFFUL << RCC_PLL2FRACR_PLL2FRACN_Pos) |
| #define | RCC_PLL2FRACR_PLL2FRACN RCC_PLL2FRACR_PLL2FRACN_Msk |
| #define | RCC_PLL2FRACR_PLL2FRACN_0 (0x0001UL << RCC_PLL2FRACR_PLL2FRACN_Pos) |
| #define | RCC_PLL2FRACR_PLL2FRACN_1 (0x0002UL << RCC_PLL2FRACR_PLL2FRACN_Pos) |
| #define | RCC_PLL2FRACR_PLL2FRACN_2 (0x0004UL << RCC_PLL2FRACR_PLL2FRACN_Pos) |
| #define | RCC_PLL2FRACR_PLL2FRACN_3 (0x0008UL << RCC_PLL2FRACR_PLL2FRACN_Pos) |
| #define | RCC_PLL2FRACR_PLL2FRACN_4 (0x0010UL << RCC_PLL2FRACR_PLL2FRACN_Pos) |
| #define | RCC_PLL2FRACR_PLL2FRACN_5 (0x0020UL << RCC_PLL2FRACR_PLL2FRACN_Pos) |
| #define | RCC_PLL2FRACR_PLL2FRACN_6 (0x0040UL << RCC_PLL2FRACR_PLL2FRACN_Pos) |
| #define | RCC_PLL2FRACR_PLL2FRACN_7 (0x0080UL << RCC_PLL2FRACR_PLL2FRACN_Pos) |
| #define | RCC_PLL2FRACR_PLL2FRACN_8 (0x0100UL << RCC_PLL2FRACR_PLL2FRACN_Pos) |
| #define | RCC_PLL2FRACR_PLL2FRACN_9 (0x0200UL << RCC_PLL2FRACR_PLL2FRACN_Pos) |
| #define | RCC_PLL2FRACR_PLL2FRACN_10 (0x0400UL << RCC_PLL2FRACR_PLL2FRACN_Pos) |
| #define | RCC_PLL2FRACR_PLL2FRACN_11 (0x0800UL << RCC_PLL2FRACR_PLL2FRACN_Pos) |
| #define | RCC_PLL2FRACR_PLL2FRACN_12 (0x1000UL << RCC_PLL2FRACR_PLL2FRACN_Pos) |
| #define | RCC_PLL3DIVR_PLL3N_Pos (0U) |
| #define | RCC_PLL3DIVR_PLL3N_Msk (0x1FFUL << RCC_PLL3DIVR_PLL3N_Pos) |
| #define | RCC_PLL3DIVR_PLL3N RCC_PLL3DIVR_PLL3N_Msk |
| #define | RCC_PLL3DIVR_PLL3N_0 (0x001UL << RCC_PLL3DIVR_PLL3N_Pos) |
| #define | RCC_PLL3DIVR_PLL3N_1 (0x002UL << RCC_PLL3DIVR_PLL3N_Pos) |
| #define | RCC_PLL3DIVR_PLL3N_2 (0x004UL << RCC_PLL3DIVR_PLL3N_Pos) |
| #define | RCC_PLL3DIVR_PLL3N_3 (0x008UL << RCC_PLL3DIVR_PLL3N_Pos) |
| #define | RCC_PLL3DIVR_PLL3N_4 (0x010UL << RCC_PLL3DIVR_PLL3N_Pos) |
| #define | RCC_PLL3DIVR_PLL3N_5 (0x020UL << RCC_PLL3DIVR_PLL3N_Pos) |
| #define | RCC_PLL3DIVR_PLL3N_6 (0x040UL << RCC_PLL3DIVR_PLL3N_Pos) |
| #define | RCC_PLL3DIVR_PLL3N_7 (0x080UL << RCC_PLL3DIVR_PLL3N_Pos) |
| #define | RCC_PLL3DIVR_PLL3N_8 (0x100UL << RCC_PLL3DIVR_PLL3N_Pos) |
| #define | RCC_PLL3DIVR_PLL3P_Pos (9U) |
| #define | RCC_PLL3DIVR_PLL3P_Msk (0x7FUL << RCC_PLL3DIVR_PLL3P_Pos) |
| #define | RCC_PLL3DIVR_PLL3P RCC_PLL3DIVR_PLL3P_Msk |
| #define | RCC_PLL3DIVR_PLL3P_0 (0x001UL << RCC_PLL3DIVR_PLL3P_Pos) |
| #define | RCC_PLL3DIVR_PLL3P_1 (0x002UL << RCC_PLL3DIVR_PLL3P_Pos) |
| #define | RCC_PLL3DIVR_PLL3P_2 (0x004UL << RCC_PLL3DIVR_PLL3P_Pos) |
| #define | RCC_PLL3DIVR_PLL3P_3 (0x008UL << RCC_PLL3DIVR_PLL3P_Pos) |
| #define | RCC_PLL3DIVR_PLL3P_4 (0x010UL << RCC_PLL3DIVR_PLL3P_Pos) |
| #define | RCC_PLL3DIVR_PLL3P_5 (0x020UL << RCC_PLL3DIVR_PLL3P_Pos) |
| #define | RCC_PLL3DIVR_PLL3P_6 (0x040UL << RCC_PLL3DIVR_PLL3P_Pos) |
| #define | RCC_PLL3DIVR_PLL3Q_Pos (16U) |
| #define | RCC_PLL3DIVR_PLL3Q_Msk (0x7FUL << RCC_PLL3DIVR_PLL3Q_Pos) |
| #define | RCC_PLL3DIVR_PLL3Q RCC_PLL3DIVR_PLL3Q_Msk |
| #define | RCC_PLL3DIVR_PLL3Q_0 (0x001UL << RCC_PLL3DIVR_PLL3Q_Pos) |
| #define | RCC_PLL3DIVR_PLL3Q_1 (0x002UL << RCC_PLL3DIVR_PLL3Q_Pos) |
| #define | RCC_PLL3DIVR_PLL3Q_2 (0x004UL << RCC_PLL3DIVR_PLL3Q_Pos) |
| #define | RCC_PLL3DIVR_PLL3Q_3 (0x008UL << RCC_PLL3DIVR_PLL3Q_Pos) |
| #define | RCC_PLL3DIVR_PLL3Q_4 (0x010UL << RCC_PLL3DIVR_PLL3Q_Pos) |
| #define | RCC_PLL3DIVR_PLL3Q_5 (0x020UL << RCC_PLL3DIVR_PLL3Q_Pos) |
| #define | RCC_PLL3DIVR_PLL3Q_6 (0x040UL << RCC_PLL3DIVR_PLL3Q_Pos) |
| #define | RCC_PLL3DIVR_PLL3R_Pos (24U) |
| #define | RCC_PLL3DIVR_PLL3R_Msk (0x7FUL << RCC_PLL3DIVR_PLL3R_Pos) |
| #define | RCC_PLL3DIVR_PLL3R RCC_PLL3DIVR_PLL3R_Msk |
| #define | RCC_PLL3DIVR_PLL3R_0 (0x001UL << RCC_PLL3DIVR_PLL3R_Pos) |
| #define | RCC_PLL3DIVR_PLL3R_1 (0x002UL << RCC_PLL3DIVR_PLL3R_Pos) |
| #define | RCC_PLL3DIVR_PLL3R_2 (0x004UL << RCC_PLL3DIVR_PLL3R_Pos) |
| #define | RCC_PLL3DIVR_PLL3R_3 (0x008UL << RCC_PLL3DIVR_PLL3R_Pos) |
| #define | RCC_PLL3DIVR_PLL3R_4 (0x010UL << RCC_PLL3DIVR_PLL3R_Pos) |
| #define | RCC_PLL3DIVR_PLL3R_5 (0x020UL << RCC_PLL3DIVR_PLL3R_Pos) |
| #define | RCC_PLL3DIVR_PLL3R_6 (0x040UL << RCC_PLL3DIVR_PLL3R_Pos) |
| #define | RCC_PLL3FRACR_PLL3FRACN_Pos (3U) |
| #define | RCC_PLL3FRACR_PLL3FRACN_Msk (0x1FFFUL << RCC_PLL3FRACR_PLL3FRACN_Pos) |
| #define | RCC_PLL3FRACR_PLL3FRACN RCC_PLL3FRACR_PLL3FRACN_Msk |
| #define | RCC_PLL3FRACR_PLL3FRACN_0 (0x0001UL << RCC_PLL3FRACR_PLL3FRACN_Pos) |
| #define | RCC_PLL3FRACR_PLL3FRACN_1 (0x0002UL << RCC_PLL3FRACR_PLL3FRACN_Pos) |
| #define | RCC_PLL3FRACR_PLL3FRACN_2 (0x0004UL << RCC_PLL3FRACR_PLL3FRACN_Pos) |
| #define | RCC_PLL3FRACR_PLL3FRACN_3 (0x0008UL << RCC_PLL3FRACR_PLL3FRACN_Pos) |
| #define | RCC_PLL3FRACR_PLL3FRACN_4 (0x0010UL << RCC_PLL3FRACR_PLL3FRACN_Pos) |
| #define | RCC_PLL3FRACR_PLL3FRACN_5 (0x0020UL << RCC_PLL3FRACR_PLL3FRACN_Pos) |
| #define | RCC_PLL3FRACR_PLL3FRACN_6 (0x0040UL << RCC_PLL3FRACR_PLL3FRACN_Pos) |
| #define | RCC_PLL3FRACR_PLL3FRACN_7 (0x0080UL << RCC_PLL3FRACR_PLL3FRACN_Pos) |
| #define | RCC_PLL3FRACR_PLL3FRACN_8 (0x0100UL << RCC_PLL3FRACR_PLL3FRACN_Pos) |
| #define | RCC_PLL3FRACR_PLL3FRACN_9 (0x0200UL << RCC_PLL3FRACR_PLL3FRACN_Pos) |
| #define | RCC_PLL3FRACR_PLL3FRACN_10 (0x0400UL << RCC_PLL3FRACR_PLL3FRACN_Pos) |
| #define | RCC_PLL3FRACR_PLL3FRACN_11 (0x0800UL << RCC_PLL3FRACR_PLL3FRACN_Pos) |
| #define | RCC_PLL3FRACR_PLL3FRACN_12 (0x1000UL << RCC_PLL3FRACR_PLL3FRACN_Pos) |
| #define | RCC_CIER_LSIRDYIE_Pos (0U) |
| #define | RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) |
| #define | RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk |
| #define | RCC_CIER_LSERDYIE_Pos (1U) |
| #define | RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) |
| #define | RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk |
| #define | RCC_CIER_MSISRDYIE_Pos (2U) |
| #define | RCC_CIER_MSISRDYIE_Msk (0x1UL << RCC_CIER_MSISRDYIE_Pos) |
| #define | RCC_CIER_MSISRDYIE RCC_CIER_MSISRDYIE_Msk |
| #define | RCC_CIER_HSIRDYIE_Pos (3U) |
| #define | RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) |
| #define | RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk |
| #define | RCC_CIER_HSERDYIE_Pos (4U) |
| #define | RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) |
| #define | RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk |
| #define | RCC_CIER_HSI48RDYIE_Pos (5U) |
| #define | RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) |
| #define | RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk |
| #define | RCC_CIER_PLL1RDYIE_Pos (6U) |
| #define | RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) |
| #define | RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk |
| #define | RCC_CIER_PLL2RDYIE_Pos (7U) |
| #define | RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) |
| #define | RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk |
| #define | RCC_CIER_PLL3RDYIE_Pos (8U) |
| #define | RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) |
| #define | RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk |
| #define | RCC_CIER_MSIKRDYIE_Pos (11U) |
| #define | RCC_CIER_MSIKRDYIE_Msk (0x1UL << RCC_CIER_MSIKRDYIE_Pos) |
| #define | RCC_CIER_MSIKRDYIE RCC_CIER_MSIKRDYIE_Msk |
| #define | RCC_CIER_SHSIRDYIE_Pos (12U) |
| #define | RCC_CIER_SHSIRDYIE_Msk (0x1UL << RCC_CIER_SHSIRDYIE_Pos) |
| #define | RCC_CIER_SHSIRDYIE RCC_CIER_SHSIRDYIE_Msk |
| #define | RCC_CIFR_LSIRDYF_Pos (0U) |
| #define | RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) |
| #define | RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk |
| #define | RCC_CIFR_LSERDYF_Pos (1U) |
| #define | RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) |
| #define | RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk |
| #define | RCC_CIFR_MSISRDYF_Pos (2U) |
| #define | RCC_CIFR_MSISRDYF_Msk (0x1UL << RCC_CIFR_MSISRDYF_Pos) |
| #define | RCC_CIFR_MSISRDYF RCC_CIFR_MSISRDYF_Msk |
| #define | RCC_CIFR_HSIRDYF_Pos (3U) |
| #define | RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) |
| #define | RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk |
| #define | RCC_CIFR_HSERDYF_Pos (4U) |
| #define | RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) |
| #define | RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk |
| #define | RCC_CIFR_HSI48RDYF_Pos (5U) |
| #define | RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) |
| #define | RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk |
| #define | RCC_CIFR_PLL1RDYF_Pos (6U) |
| #define | RCC_CIFR_PLL1RDYF_Msk (0x1UL << RCC_CIFR_PLL1RDYF_Pos) |
| #define | RCC_CIFR_PLL1RDYF RCC_CIFR_PLL1RDYF_Msk |
| #define | RCC_CIFR_PLL2RDYF_Pos (7U) |
| #define | RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) |
| #define | RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk |
| #define | RCC_CIFR_PLL3RDYF_Pos (8U) |
| #define | RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) |
| #define | RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk |
| #define | RCC_CIFR_CSSF_Pos (10U) |
| #define | RCC_CIFR_CSSF_Msk (0x1UL << RCC_CIFR_CSSF_Pos) |
| #define | RCC_CIFR_CSSF RCC_CIFR_CSSF_Msk |
| #define | RCC_CIFR_MSIKRDYF_Pos (11U) |
| #define | RCC_CIFR_MSIKRDYF_Msk (0x1UL << RCC_CIFR_MSIKRDYF_Pos) |
| #define | RCC_CIFR_MSIKRDYF RCC_CIFR_MSIKRDYF_Msk |
| #define | RCC_CIFR_SHSIRDYF_Pos (12U) |
| #define | RCC_CIFR_SHSIRDYF_Msk (0x1UL << RCC_CIFR_SHSIRDYF_Pos) |
| #define | RCC_CIFR_SHSIRDYF RCC_CIFR_SHSIRDYF_Msk |
| #define | RCC_CICR_LSIRDYC_Pos (0U) |
| #define | RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) |
| #define | RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk |
| #define | RCC_CICR_LSERDYC_Pos (1U) |
| #define | RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) |
| #define | RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk |
| #define | RCC_CICR_MSISRDYC_Pos (2U) |
| #define | RCC_CICR_MSISRDYC_Msk (0x1UL << RCC_CICR_MSISRDYC_Pos) |
| #define | RCC_CICR_MSISRDYC RCC_CICR_MSISRDYC_Msk |
| #define | RCC_CICR_HSIRDYC_Pos (3U) |
| #define | RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) |
| #define | RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk |
| #define | RCC_CICR_HSERDYC_Pos (4U) |
| #define | RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) |
| #define | RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk |
| #define | RCC_CICR_HSI48RDYC_Pos (5U) |
| #define | RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) |
| #define | RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk |
| #define | RCC_CICR_PLL1RDYC_Pos (6U) |
| #define | RCC_CICR_PLL1RDYC_Msk (0x1UL << RCC_CICR_PLL1RDYC_Pos) |
| #define | RCC_CICR_PLL1RDYC RCC_CICR_PLL1RDYC_Msk |
| #define | RCC_CICR_PLL2RDYC_Pos (7U) |
| #define | RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) |
| #define | RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk |
| #define | RCC_CICR_PLL3RDYC_Pos (8U) |
| #define | RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) |
| #define | RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk |
| #define | RCC_CICR_CSSC_Pos (10U) |
| #define | RCC_CICR_CSSC_Msk (0x1UL << RCC_CICR_CSSC_Pos) |
| #define | RCC_CICR_CSSC RCC_CICR_CSSC_Msk |
| #define | RCC_CICR_MSIKRDYC_Pos (11U) |
| #define | RCC_CICR_MSIKRDYC_Msk (0x1UL << RCC_CICR_MSIKRDYC_Pos) |
| #define | RCC_CICR_MSIKRDYC RCC_CICR_MSIKRDYC_Msk |
| #define | RCC_CICR_SHSIRDYC_Pos (12U) |
| #define | RCC_CICR_SHSIRDYC_Msk (0x1UL << RCC_CICR_SHSIRDYC_Pos) |
| #define | RCC_CICR_SHSIRDYC RCC_CICR_SHSIRDYC_Msk |
| #define | RCC_AHB1RSTR_GPDMA1RST_Pos (0U) |
| #define | RCC_AHB1RSTR_GPDMA1RST_Msk (0x1UL << RCC_AHB1RSTR_GPDMA1RST_Pos) |
| #define | RCC_AHB1RSTR_GPDMA1RST RCC_AHB1RSTR_GPDMA1RST_Msk |
| #define | RCC_AHB1RSTR_CORDICRST_Pos (1U) |
| #define | RCC_AHB1RSTR_CORDICRST_Msk (0x1UL << RCC_AHB1RSTR_CORDICRST_Pos) |
| #define | RCC_AHB1RSTR_CORDICRST RCC_AHB1RSTR_CORDICRST_Msk |
| #define | RCC_AHB1RSTR_FMACRST_Pos (2U) |
| #define | RCC_AHB1RSTR_FMACRST_Msk (0x1UL << RCC_AHB1RSTR_FMACRST_Pos) |
| #define | RCC_AHB1RSTR_FMACRST RCC_AHB1RSTR_FMACRST_Msk |
| #define | RCC_AHB1RSTR_MDF1RST_Pos (3U) |
| #define | RCC_AHB1RSTR_MDF1RST_Msk (0x1UL << RCC_AHB1RSTR_MDF1RST_Pos) |
| #define | RCC_AHB1RSTR_MDF1RST RCC_AHB1RSTR_MDF1RST_Msk |
| #define | RCC_AHB1RSTR_CRCRST_Pos (12U) |
| #define | RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) |
| #define | RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk |
| #define | RCC_AHB1RSTR_JPEGRST_Pos (15U) |
| #define | RCC_AHB1RSTR_JPEGRST_Msk (0x1UL << RCC_AHB1RSTR_JPEGRST_Pos) |
| #define | RCC_AHB1RSTR_JPEGRST RCC_AHB1RSTR_JPEGRST_Msk |
| #define | RCC_AHB1RSTR_TSCRST_Pos (16U) |
| #define | RCC_AHB1RSTR_TSCRST_Msk (0x1UL << RCC_AHB1RSTR_TSCRST_Pos) |
| #define | RCC_AHB1RSTR_TSCRST RCC_AHB1RSTR_TSCRST_Msk |
| #define | RCC_AHB1RSTR_RAMCFGRST_Pos (17U) |
| #define | RCC_AHB1RSTR_RAMCFGRST_Msk (0x1UL << RCC_AHB1RSTR_RAMCFGRST_Pos) |
| #define | RCC_AHB1RSTR_RAMCFGRST RCC_AHB1RSTR_RAMCFGRST_Msk |
| #define | RCC_AHB1RSTR_DMA2DRST_Pos (18U) |
| #define | RCC_AHB1RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB1RSTR_DMA2DRST_Pos) |
| #define | RCC_AHB1RSTR_DMA2DRST RCC_AHB1RSTR_DMA2DRST_Msk |
| #define | RCC_AHB1RSTR_GFXMMURST_Pos (19U) |
| #define | RCC_AHB1RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB1RSTR_GFXMMURST_Pos) |
| #define | RCC_AHB1RSTR_GFXMMURST RCC_AHB1RSTR_GFXMMURST_Msk |
| #define | RCC_AHB1RSTR_GPU2DRST_Pos (20U) |
| #define | RCC_AHB1RSTR_GPU2DRST_Msk (0x1UL << RCC_AHB1RSTR_GPU2DRST_Pos) |
| #define | RCC_AHB1RSTR_GPU2DRST RCC_AHB1RSTR_GPU2DRST_Msk |
| #define | RCC_AHB2RSTR1_GPIOARST_Pos (0U) |
| #define | RCC_AHB2RSTR1_GPIOARST_Msk (0x1UL << RCC_AHB2RSTR1_GPIOARST_Pos) |
| #define | RCC_AHB2RSTR1_GPIOARST RCC_AHB2RSTR1_GPIOARST_Msk |
| #define | RCC_AHB2RSTR1_GPIOBRST_Pos (1U) |
| #define | RCC_AHB2RSTR1_GPIOBRST_Msk (0x1UL << RCC_AHB2RSTR1_GPIOBRST_Pos) |
| #define | RCC_AHB2RSTR1_GPIOBRST RCC_AHB2RSTR1_GPIOBRST_Msk |
| #define | RCC_AHB2RSTR1_GPIOCRST_Pos (2U) |
| #define | RCC_AHB2RSTR1_GPIOCRST_Msk (0x1UL << RCC_AHB2RSTR1_GPIOCRST_Pos) |
| #define | RCC_AHB2RSTR1_GPIOCRST RCC_AHB2RSTR1_GPIOCRST_Msk |
| #define | RCC_AHB2RSTR1_GPIODRST_Pos (3U) |
| #define | RCC_AHB2RSTR1_GPIODRST_Msk (0x1UL << RCC_AHB2RSTR1_GPIODRST_Pos) |
| #define | RCC_AHB2RSTR1_GPIODRST RCC_AHB2RSTR1_GPIODRST_Msk |
| #define | RCC_AHB2RSTR1_GPIOERST_Pos (4U) |
| #define | RCC_AHB2RSTR1_GPIOERST_Msk (0x1UL << RCC_AHB2RSTR1_GPIOERST_Pos) |
| #define | RCC_AHB2RSTR1_GPIOERST RCC_AHB2RSTR1_GPIOERST_Msk |
| #define | RCC_AHB2RSTR1_GPIOFRST_Pos (5U) |
| #define | RCC_AHB2RSTR1_GPIOFRST_Msk (0x1UL << RCC_AHB2RSTR1_GPIOFRST_Pos) |
| #define | RCC_AHB2RSTR1_GPIOFRST RCC_AHB2RSTR1_GPIOFRST_Msk |
| #define | RCC_AHB2RSTR1_GPIOGRST_Pos (6U) |
| #define | RCC_AHB2RSTR1_GPIOGRST_Msk (0x1UL << RCC_AHB2RSTR1_GPIOGRST_Pos) |
| #define | RCC_AHB2RSTR1_GPIOGRST RCC_AHB2RSTR1_GPIOGRST_Msk |
| #define | RCC_AHB2RSTR1_GPIOHRST_Pos (7U) |
| #define | RCC_AHB2RSTR1_GPIOHRST_Msk (0x1UL << RCC_AHB2RSTR1_GPIOHRST_Pos) |
| #define | RCC_AHB2RSTR1_GPIOHRST RCC_AHB2RSTR1_GPIOHRST_Msk |
| #define | RCC_AHB2RSTR1_GPIOIRST_Pos (8U) |
| #define | RCC_AHB2RSTR1_GPIOIRST_Msk (0x1UL << RCC_AHB2RSTR1_GPIOIRST_Pos) |
| #define | RCC_AHB2RSTR1_GPIOIRST RCC_AHB2RSTR1_GPIOIRST_Msk |
| #define | RCC_AHB2RSTR1_GPIOJRST_Pos (9U) |
| #define | RCC_AHB2RSTR1_GPIOJRST_Msk (0x1UL << RCC_AHB2RSTR1_GPIOJRST_Pos) |
| #define | RCC_AHB2RSTR1_GPIOJRST RCC_AHB2RSTR1_GPIOJRST_Msk |
| #define | RCC_AHB2RSTR1_ADC12RST_Pos (10U) |
| #define | RCC_AHB2RSTR1_ADC12RST_Msk (0x1UL << RCC_AHB2RSTR1_ADC12RST_Pos) |
| #define | RCC_AHB2RSTR1_ADC12RST RCC_AHB2RSTR1_ADC12RST_Msk |
| #define | RCC_AHB2RSTR1_DCMI_PSSIRST_Pos (12U) |
| #define | RCC_AHB2RSTR1_DCMI_PSSIRST_Msk (0x1UL << RCC_AHB2RSTR1_DCMI_PSSIRST_Pos) |
| #define | RCC_AHB2RSTR1_DCMI_PSSIRST RCC_AHB2RSTR1_DCMI_PSSIRST_Msk |
| #define | RCC_AHB2RSTR1_OTGRST_Pos (14U) |
| #define | RCC_AHB2RSTR1_OTGRST_Msk (0x1UL << RCC_AHB2RSTR1_OTGRST_Pos) |
| #define | RCC_AHB2RSTR1_OTGRST RCC_AHB2RSTR1_OTGRST_Msk |
| #define | RCC_AHB2RSTR1_AESRST_Pos (16U) |
| #define | RCC_AHB2RSTR1_AESRST_Msk (0x1UL << RCC_AHB2RSTR1_AESRST_Pos) |
| #define | RCC_AHB2RSTR1_AESRST RCC_AHB2RSTR1_AESRST_Msk |
| #define | RCC_AHB2RSTR1_HASHRST_Pos (17U) |
| #define | RCC_AHB2RSTR1_HASHRST_Msk (0x1UL << RCC_AHB2RSTR1_HASHRST_Pos) |
| #define | RCC_AHB2RSTR1_HASHRST RCC_AHB2RSTR1_HASHRST_Msk |
| #define | RCC_AHB2RSTR1_RNGRST_Pos (18U) |
| #define | RCC_AHB2RSTR1_RNGRST_Msk (0x1UL << RCC_AHB2RSTR1_RNGRST_Pos) |
| #define | RCC_AHB2RSTR1_RNGRST RCC_AHB2RSTR1_RNGRST_Msk |
| #define | RCC_AHB2RSTR1_PKARST_Pos (19U) |
| #define | RCC_AHB2RSTR1_PKARST_Msk (0x1UL << RCC_AHB2RSTR1_PKARST_Pos) |
| #define | RCC_AHB2RSTR1_PKARST RCC_AHB2RSTR1_PKARST_Msk |
| #define | RCC_AHB2RSTR1_SAESRST_Pos (20U) |
| #define | RCC_AHB2RSTR1_SAESRST_Msk (0x1UL << RCC_AHB2RSTR1_SAESRST_Pos) |
| #define | RCC_AHB2RSTR1_SAESRST RCC_AHB2RSTR1_SAESRST_Msk |
| #define | RCC_AHB2RSTR1_OCTOSPIMRST_Pos (21U) |
| #define | RCC_AHB2RSTR1_OCTOSPIMRST_Msk (0x1UL << RCC_AHB2RSTR1_OCTOSPIMRST_Pos) |
| #define | RCC_AHB2RSTR1_OCTOSPIMRST RCC_AHB2RSTR1_OCTOSPIMRST_Msk |
| #define | RCC_AHB2RSTR1_OTFDEC1RST_Pos (23U) |
| #define | RCC_AHB2RSTR1_OTFDEC1RST_Msk (0x1UL << RCC_AHB2RSTR1_OTFDEC1RST_Pos) |
| #define | RCC_AHB2RSTR1_OTFDEC1RST RCC_AHB2RSTR1_OTFDEC1RST_Msk |
| #define | RCC_AHB2RSTR1_OTFDEC2RST_Pos (24U) |
| #define | RCC_AHB2RSTR1_OTFDEC2RST_Msk (0x1UL << RCC_AHB2RSTR1_OTFDEC2RST_Pos) |
| #define | RCC_AHB2RSTR1_OTFDEC2RST RCC_AHB2RSTR1_OTFDEC2RST_Msk |
| #define | RCC_AHB2RSTR1_SDMMC1RST_Pos (27U) |
| #define | RCC_AHB2RSTR1_SDMMC1RST_Msk (0x1UL << RCC_AHB2RSTR1_SDMMC1RST_Pos) |
| #define | RCC_AHB2RSTR1_SDMMC1RST RCC_AHB2RSTR1_SDMMC1RST_Msk |
| #define | RCC_AHB2RSTR1_SDMMC2RST_Pos (28U) |
| #define | RCC_AHB2RSTR1_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR1_SDMMC2RST_Pos) |
| #define | RCC_AHB2RSTR1_SDMMC2RST RCC_AHB2RSTR1_SDMMC2RST_Msk |
| #define | RCC_AHB2RSTR2_FSMCRST_Pos (0U) |
| #define | RCC_AHB2RSTR2_FSMCRST_Msk (0x1UL << RCC_AHB2RSTR2_FSMCRST_Pos) |
| #define | RCC_AHB2RSTR2_FSMCRST RCC_AHB2RSTR2_FSMCRST_Msk |
| #define | RCC_AHB2RSTR2_OCTOSPI1RST_Pos (4U) |
| #define | RCC_AHB2RSTR2_OCTOSPI1RST_Msk (0x1UL << RCC_AHB2RSTR2_OCTOSPI1RST_Pos) |
| #define | RCC_AHB2RSTR2_OCTOSPI1RST RCC_AHB2RSTR2_OCTOSPI1RST_Msk |
| #define | RCC_AHB2RSTR2_OCTOSPI2RST_Pos (8U) |
| #define | RCC_AHB2RSTR2_OCTOSPI2RST_Msk (0x1UL << RCC_AHB2RSTR2_OCTOSPI2RST_Pos) |
| #define | RCC_AHB2RSTR2_OCTOSPI2RST RCC_AHB2RSTR2_OCTOSPI2RST_Msk |
| #define | RCC_AHB2RSTR2_HSPI1RST_Pos (12U) |
| #define | RCC_AHB2RSTR2_HSPI1RST_Msk (0x1UL << RCC_AHB2RSTR2_HSPI1RST_Pos) |
| #define | RCC_AHB2RSTR2_HSPI1RST RCC_AHB2RSTR2_HSPI1RST_Msk |
| #define | RCC_AHB3RSTR_LPGPIO1RST_Pos (0U) |
| #define | RCC_AHB3RSTR_LPGPIO1RST_Msk (0x1UL << RCC_AHB3RSTR_LPGPIO1RST_Pos) |
| #define | RCC_AHB3RSTR_LPGPIO1RST RCC_AHB3RSTR_LPGPIO1RST_Msk |
| #define | RCC_AHB3RSTR_ADC4RST_Pos (5U) |
| #define | RCC_AHB3RSTR_ADC4RST_Msk (0x1UL << RCC_AHB3RSTR_ADC4RST_Pos) |
| #define | RCC_AHB3RSTR_ADC4RST RCC_AHB3RSTR_ADC4RST_Msk |
| #define | RCC_AHB3RSTR_DAC1RST_Pos (6U) |
| #define | RCC_AHB3RSTR_DAC1RST_Msk (0x1UL << RCC_AHB3RSTR_DAC1RST_Pos) |
| #define | RCC_AHB3RSTR_DAC1RST RCC_AHB3RSTR_DAC1RST_Msk |
| #define | RCC_AHB3RSTR_LPDMA1RST_Pos (9U) |
| #define | RCC_AHB3RSTR_LPDMA1RST_Msk (0x1UL << RCC_AHB3RSTR_LPDMA1RST_Pos) |
| #define | RCC_AHB3RSTR_LPDMA1RST RCC_AHB3RSTR_LPDMA1RST_Msk |
| #define | RCC_AHB3RSTR_ADF1RST_Pos (10U) |
| #define | RCC_AHB3RSTR_ADF1RST_Msk (0x1UL << RCC_AHB3RSTR_ADF1RST_Pos) |
| #define | RCC_AHB3RSTR_ADF1RST RCC_AHB3RSTR_ADF1RST_Msk |
| #define | RCC_APB1RSTR1_TIM2RST_Pos (0U) |
| #define | RCC_APB1RSTR1_TIM2RST_Msk (0x1UL << RCC_APB1RSTR1_TIM2RST_Pos) |
| #define | RCC_APB1RSTR1_TIM2RST RCC_APB1RSTR1_TIM2RST_Msk |
| #define | RCC_APB1RSTR1_TIM3RST_Pos (1U) |
| #define | RCC_APB1RSTR1_TIM3RST_Msk (0x1UL << RCC_APB1RSTR1_TIM3RST_Pos) |
| #define | RCC_APB1RSTR1_TIM3RST RCC_APB1RSTR1_TIM3RST_Msk |
| #define | RCC_APB1RSTR1_TIM4RST_Pos (2U) |
| #define | RCC_APB1RSTR1_TIM4RST_Msk (0x1UL << RCC_APB1RSTR1_TIM4RST_Pos) |
| #define | RCC_APB1RSTR1_TIM4RST RCC_APB1RSTR1_TIM4RST_Msk |
| #define | RCC_APB1RSTR1_TIM5RST_Pos (3U) |
| #define | RCC_APB1RSTR1_TIM5RST_Msk (0x1UL << RCC_APB1RSTR1_TIM5RST_Pos) |
| #define | RCC_APB1RSTR1_TIM5RST RCC_APB1RSTR1_TIM5RST_Msk |
| #define | RCC_APB1RSTR1_TIM6RST_Pos (4U) |
| #define | RCC_APB1RSTR1_TIM6RST_Msk (0x1UL << RCC_APB1RSTR1_TIM6RST_Pos) |
| #define | RCC_APB1RSTR1_TIM6RST RCC_APB1RSTR1_TIM6RST_Msk |
| #define | RCC_APB1RSTR1_TIM7RST_Pos (5U) |
| #define | RCC_APB1RSTR1_TIM7RST_Msk (0x1UL << RCC_APB1RSTR1_TIM7RST_Pos) |
| #define | RCC_APB1RSTR1_TIM7RST RCC_APB1RSTR1_TIM7RST_Msk |
| #define | RCC_APB1RSTR1_SPI2RST_Pos (14U) |
| #define | RCC_APB1RSTR1_SPI2RST_Msk (0x1UL << RCC_APB1RSTR1_SPI2RST_Pos) |
| #define | RCC_APB1RSTR1_SPI2RST RCC_APB1RSTR1_SPI2RST_Msk |
| #define | RCC_APB1RSTR1_USART2RST_Pos (17U) |
| #define | RCC_APB1RSTR1_USART2RST_Msk (0x1UL << RCC_APB1RSTR1_USART2RST_Pos) |
| #define | RCC_APB1RSTR1_USART2RST RCC_APB1RSTR1_USART2RST_Msk |
| #define | RCC_APB1RSTR1_USART3RST_Pos (18U) |
| #define | RCC_APB1RSTR1_USART3RST_Msk (0x1UL << RCC_APB1RSTR1_USART3RST_Pos) |
| #define | RCC_APB1RSTR1_USART3RST RCC_APB1RSTR1_USART3RST_Msk |
| #define | RCC_APB1RSTR1_UART4RST_Pos (19U) |
| #define | RCC_APB1RSTR1_UART4RST_Msk (0x1UL << RCC_APB1RSTR1_UART4RST_Pos) |
| #define | RCC_APB1RSTR1_UART4RST RCC_APB1RSTR1_UART4RST_Msk |
| #define | RCC_APB1RSTR1_UART5RST_Pos (20U) |
| #define | RCC_APB1RSTR1_UART5RST_Msk (0x1UL << RCC_APB1RSTR1_UART5RST_Pos) |
| #define | RCC_APB1RSTR1_UART5RST RCC_APB1RSTR1_UART5RST_Msk |
| #define | RCC_APB1RSTR1_I2C1RST_Pos (21U) |
| #define | RCC_APB1RSTR1_I2C1RST_Msk (0x1UL << RCC_APB1RSTR1_I2C1RST_Pos) |
| #define | RCC_APB1RSTR1_I2C1RST RCC_APB1RSTR1_I2C1RST_Msk |
| #define | RCC_APB1RSTR1_I2C2RST_Pos (22U) |
| #define | RCC_APB1RSTR1_I2C2RST_Msk (0x1UL << RCC_APB1RSTR1_I2C2RST_Pos) |
| #define | RCC_APB1RSTR1_I2C2RST RCC_APB1RSTR1_I2C2RST_Msk |
| #define | RCC_APB1RSTR1_CRSRST_Pos (24U) |
| #define | RCC_APB1RSTR1_CRSRST_Msk (0x1UL << RCC_APB1RSTR1_CRSRST_Pos) |
| #define | RCC_APB1RSTR1_CRSRST RCC_APB1RSTR1_CRSRST_Msk |
| #define | RCC_APB1RSTR1_USART6RST_Pos (25U) |
| #define | RCC_APB1RSTR1_USART6RST_Msk (0x1UL << RCC_APB1RSTR1_USART6RST_Pos) |
| #define | RCC_APB1RSTR1_USART6RST RCC_APB1RSTR1_USART6RST_Msk |
| #define | RCC_APB1RSTR2_I2C4RST_Pos (1U) |
| #define | RCC_APB1RSTR2_I2C4RST_Msk (0x1UL << RCC_APB1RSTR2_I2C4RST_Pos) |
| #define | RCC_APB1RSTR2_I2C4RST RCC_APB1RSTR2_I2C4RST_Msk |
| #define | RCC_APB1RSTR2_LPTIM2RST_Pos (5U) |
| #define | RCC_APB1RSTR2_LPTIM2RST_Msk (0x1UL << RCC_APB1RSTR2_LPTIM2RST_Pos) |
| #define | RCC_APB1RSTR2_LPTIM2RST RCC_APB1RSTR2_LPTIM2RST_Msk |
| #define | RCC_APB1RSTR2_I2C5RST_Pos (6U) |
| #define | RCC_APB1RSTR2_I2C5RST_Msk (0x1UL << RCC_APB1RSTR2_I2C5RST_Pos) |
| #define | RCC_APB1RSTR2_I2C5RST RCC_APB1RSTR2_I2C5RST_Msk |
| #define | RCC_APB1RSTR2_I2C6RST_Pos (7U) |
| #define | RCC_APB1RSTR2_I2C6RST_Msk (0x1UL << RCC_APB1RSTR2_I2C6RST_Pos) |
| #define | RCC_APB1RSTR2_I2C6RST RCC_APB1RSTR2_I2C6RST_Msk |
| #define | RCC_APB1RSTR2_FDCAN1RST_Pos (9U) |
| #define | RCC_APB1RSTR2_FDCAN1RST_Msk (0x1UL << RCC_APB1RSTR2_FDCAN1RST_Pos) |
| #define | RCC_APB1RSTR2_FDCAN1RST RCC_APB1RSTR2_FDCAN1RST_Msk |
| #define | RCC_APB1RSTR2_UCPD1RST_Pos (23U) |
| #define | RCC_APB1RSTR2_UCPD1RST_Msk (0x1UL << RCC_APB1RSTR2_UCPD1RST_Pos) |
| #define | RCC_APB1RSTR2_UCPD1RST RCC_APB1RSTR2_UCPD1RST_Msk |
| #define | RCC_APB2RSTR_TIM1RST_Pos (11U) |
| #define | RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) |
| #define | RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk |
| #define | RCC_APB2RSTR_SPI1RST_Pos (12U) |
| #define | RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) |
| #define | RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk |
| #define | RCC_APB2RSTR_TIM8RST_Pos (13U) |
| #define | RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) |
| #define | RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk |
| #define | RCC_APB2RSTR_USART1RST_Pos (14U) |
| #define | RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) |
| #define | RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk |
| #define | RCC_APB2RSTR_TIM15RST_Pos (16U) |
| #define | RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) |
| #define | RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk |
| #define | RCC_APB2RSTR_TIM16RST_Pos (17U) |
| #define | RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) |
| #define | RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk |
| #define | RCC_APB2RSTR_TIM17RST_Pos (18U) |
| #define | RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) |
| #define | RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk |
| #define | RCC_APB2RSTR_SAI1RST_Pos (21U) |
| #define | RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) |
| #define | RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk |
| #define | RCC_APB2RSTR_SAI2RST_Pos (22U) |
| #define | RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) |
| #define | RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk |
| #define | RCC_APB2RSTR_GFXTIMRST_Pos (25U) |
| #define | RCC_APB2RSTR_GFXTIMRST_Msk (0x1UL << RCC_APB2RSTR_GFXTIMRST_Pos) |
| #define | RCC_APB2RSTR_GFXTIMRST RCC_APB2RSTR_GFXTIMRST_Msk |
| #define | RCC_APB2RSTR_LTDCRST_Pos (26U) |
| #define | RCC_APB2RSTR_LTDCRST_Msk (0x1UL << RCC_APB2RSTR_LTDCRST_Pos) |
| #define | RCC_APB2RSTR_LTDCRST RCC_APB2RSTR_LTDCRST_Msk |
| #define | RCC_APB2RSTR_DSIHOSTRST_Pos (27U) |
| #define | RCC_APB2RSTR_DSIHOSTRST_Msk (0x1UL << RCC_APB2RSTR_DSIHOSTRST_Pos) |
| #define | RCC_APB2RSTR_DSIHOSTRST RCC_APB2RSTR_DSIHOSTRST_Msk |
| #define | RCC_APB3RSTR_SYSCFGRST_Pos (1U) |
| #define | RCC_APB3RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB3RSTR_SYSCFGRST_Pos) |
| #define | RCC_APB3RSTR_SYSCFGRST RCC_APB3RSTR_SYSCFGRST_Msk |
| #define | RCC_APB3RSTR_SPI3RST_Pos (5U) |
| #define | RCC_APB3RSTR_SPI3RST_Msk (0x1UL << RCC_APB3RSTR_SPI3RST_Pos) |
| #define | RCC_APB3RSTR_SPI3RST RCC_APB3RSTR_SPI3RST_Msk |
| #define | RCC_APB3RSTR_LPUART1RST_Pos (6U) |
| #define | RCC_APB3RSTR_LPUART1RST_Msk (0x1UL << RCC_APB3RSTR_LPUART1RST_Pos) |
| #define | RCC_APB3RSTR_LPUART1RST RCC_APB3RSTR_LPUART1RST_Msk |
| #define | RCC_APB3RSTR_I2C3RST_Pos (7U) |
| #define | RCC_APB3RSTR_I2C3RST_Msk (0x1UL << RCC_APB3RSTR_I2C3RST_Pos) |
| #define | RCC_APB3RSTR_I2C3RST RCC_APB3RSTR_I2C3RST_Msk |
| #define | RCC_APB3RSTR_LPTIM1RST_Pos (11U) |
| #define | RCC_APB3RSTR_LPTIM1RST_Msk (0x1UL << RCC_APB3RSTR_LPTIM1RST_Pos) |
| #define | RCC_APB3RSTR_LPTIM1RST RCC_APB3RSTR_LPTIM1RST_Msk |
| #define | RCC_APB3RSTR_LPTIM3RST_Pos (12U) |
| #define | RCC_APB3RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB3RSTR_LPTIM3RST_Pos) |
| #define | RCC_APB3RSTR_LPTIM3RST RCC_APB3RSTR_LPTIM3RST_Msk |
| #define | RCC_APB3RSTR_LPTIM4RST_Pos (13U) |
| #define | RCC_APB3RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB3RSTR_LPTIM4RST_Pos) |
| #define | RCC_APB3RSTR_LPTIM4RST RCC_APB3RSTR_LPTIM4RST_Msk |
| #define | RCC_APB3RSTR_OPAMPRST_Pos (14U) |
| #define | RCC_APB3RSTR_OPAMPRST_Msk (0x1UL << RCC_APB3RSTR_OPAMPRST_Pos) |
| #define | RCC_APB3RSTR_OPAMPRST RCC_APB3RSTR_OPAMPRST_Msk |
| #define | RCC_APB3RSTR_COMPRST_Pos (15U) |
| #define | RCC_APB3RSTR_COMPRST_Msk (0x1UL << RCC_APB3RSTR_COMPRST_Pos) |
| #define | RCC_APB3RSTR_COMPRST RCC_APB3RSTR_COMPRST_Msk |
| #define | RCC_APB3RSTR_VREFRST_Pos (20U) |
| #define | RCC_APB3RSTR_VREFRST_Msk (0x1UL << RCC_APB3RSTR_VREFRST_Pos) |
| #define | RCC_APB3RSTR_VREFRST RCC_APB3RSTR_VREFRST_Msk |
| #define | RCC_AHB1ENR_GPDMA1EN_Pos (0U) |
| #define | RCC_AHB1ENR_GPDMA1EN_Msk (0x1UL << RCC_AHB1ENR_GPDMA1EN_Pos) |
| #define | RCC_AHB1ENR_GPDMA1EN RCC_AHB1ENR_GPDMA1EN_Msk |
| #define | RCC_AHB1ENR_CORDICEN_Pos (1U) |
| #define | RCC_AHB1ENR_CORDICEN_Msk (0x1UL << RCC_AHB1ENR_CORDICEN_Pos) |
| #define | RCC_AHB1ENR_CORDICEN RCC_AHB1ENR_CORDICEN_Msk |
| #define | RCC_AHB1ENR_FMACEN_Pos (2U) |
| #define | RCC_AHB1ENR_FMACEN_Msk (0x1UL << RCC_AHB1ENR_FMACEN_Pos) |
| #define | RCC_AHB1ENR_FMACEN RCC_AHB1ENR_FMACEN_Msk |
| #define | RCC_AHB1ENR_MDF1EN_Pos (3U) |
| #define | RCC_AHB1ENR_MDF1EN_Msk (0x1UL << RCC_AHB1ENR_MDF1EN_Pos) |
| #define | RCC_AHB1ENR_MDF1EN RCC_AHB1ENR_MDF1EN_Msk |
| #define | RCC_AHB1ENR_FLASHEN_Pos (8U) |
| #define | RCC_AHB1ENR_FLASHEN_Msk (0x1UL << RCC_AHB1ENR_FLASHEN_Pos) |
| #define | RCC_AHB1ENR_FLASHEN RCC_AHB1ENR_FLASHEN_Msk |
| #define | RCC_AHB1ENR_CRCEN_Pos (12U) |
| #define | RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) |
| #define | RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk |
| #define | RCC_AHB1ENR_JPEGEN_Pos (15U) |
| #define | RCC_AHB1ENR_JPEGEN_Msk (0x1UL << RCC_AHB1ENR_JPEGEN_Pos) |
| #define | RCC_AHB1ENR_JPEGEN RCC_AHB1ENR_JPEGEN_Msk |
| #define | RCC_AHB1ENR_TSCEN_Pos (16U) |
| #define | RCC_AHB1ENR_TSCEN_Msk (0x1UL << RCC_AHB1ENR_TSCEN_Pos) |
| #define | RCC_AHB1ENR_TSCEN RCC_AHB1ENR_TSCEN_Msk |
| #define | RCC_AHB1ENR_RAMCFGEN_Pos (17U) |
| #define | RCC_AHB1ENR_RAMCFGEN_Msk (0x1UL << RCC_AHB1ENR_RAMCFGEN_Pos) |
| #define | RCC_AHB1ENR_RAMCFGEN RCC_AHB1ENR_RAMCFGEN_Msk |
| #define | RCC_AHB1ENR_DMA2DEN_Pos (18U) |
| #define | RCC_AHB1ENR_DMA2DEN_Msk (0x1UL << RCC_AHB1ENR_DMA2DEN_Pos) |
| #define | RCC_AHB1ENR_DMA2DEN RCC_AHB1ENR_DMA2DEN_Msk |
| #define | RCC_AHB1ENR_GFXMMUEN_Pos (19U) |
| #define | RCC_AHB1ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB1ENR_GFXMMUEN_Pos) |
| #define | RCC_AHB1ENR_GFXMMUEN RCC_AHB1ENR_GFXMMUEN_Msk |
| #define | RCC_AHB1ENR_GPU2DEN_Pos (20U) |
| #define | RCC_AHB1ENR_GPU2DEN_Msk (0x1UL << RCC_AHB1ENR_GPU2DEN_Pos) |
| #define | RCC_AHB1ENR_GPU2DEN RCC_AHB1ENR_GPU2DEN_Msk |
| #define | RCC_AHB1ENR_DCACHE2EN_Pos (21U) |
| #define | RCC_AHB1ENR_DCACHE2EN_Msk (0x1UL << RCC_AHB1ENR_DCACHE2EN_Pos) |
| #define | RCC_AHB1ENR_DCACHE2EN RCC_AHB1ENR_DCACHE2EN_Msk |
| #define | RCC_AHB1ENR_GTZC1EN_Pos (24U) |
| #define | RCC_AHB1ENR_GTZC1EN_Msk (0x1UL << RCC_AHB1ENR_GTZC1EN_Pos) |
| #define | RCC_AHB1ENR_GTZC1EN RCC_AHB1ENR_GTZC1EN_Msk |
| #define | RCC_AHB1ENR_BKPSRAMEN_Pos (28U) |
| #define | RCC_AHB1ENR_BKPSRAMEN_Msk (0x1UL << RCC_AHB1ENR_BKPSRAMEN_Pos) |
| #define | RCC_AHB1ENR_BKPSRAMEN RCC_AHB1ENR_BKPSRAMEN_Msk |
| #define | RCC_AHB1ENR_DCACHE1EN_Pos (30U) |
| #define | RCC_AHB1ENR_DCACHE1EN_Msk (0x1UL << RCC_AHB1ENR_DCACHE1EN_Pos) |
| #define | RCC_AHB1ENR_DCACHE1EN RCC_AHB1ENR_DCACHE1EN_Msk |
| #define | RCC_AHB1ENR_SRAM1EN_Pos (31U) |
| #define | RCC_AHB1ENR_SRAM1EN_Msk (0x1UL << RCC_AHB1ENR_SRAM1EN_Pos) |
| #define | RCC_AHB1ENR_SRAM1EN RCC_AHB1ENR_SRAM1EN_Msk |
| #define | RCC_AHB2ENR1_GPIOAEN_Pos (0U) |
| #define | RCC_AHB2ENR1_GPIOAEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOAEN_Pos) |
| #define | RCC_AHB2ENR1_GPIOAEN RCC_AHB2ENR1_GPIOAEN_Msk |
| #define | RCC_AHB2ENR1_GPIOBEN_Pos (1U) |
| #define | RCC_AHB2ENR1_GPIOBEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOBEN_Pos) |
| #define | RCC_AHB2ENR1_GPIOBEN RCC_AHB2ENR1_GPIOBEN_Msk |
| #define | RCC_AHB2ENR1_GPIOCEN_Pos (2U) |
| #define | RCC_AHB2ENR1_GPIOCEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOCEN_Pos) |
| #define | RCC_AHB2ENR1_GPIOCEN RCC_AHB2ENR1_GPIOCEN_Msk |
| #define | RCC_AHB2ENR1_GPIODEN_Pos (3U) |
| #define | RCC_AHB2ENR1_GPIODEN_Msk (0x1UL << RCC_AHB2ENR1_GPIODEN_Pos) |
| #define | RCC_AHB2ENR1_GPIODEN RCC_AHB2ENR1_GPIODEN_Msk |
| #define | RCC_AHB2ENR1_GPIOEEN_Pos (4U) |
| #define | RCC_AHB2ENR1_GPIOEEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOEEN_Pos) |
| #define | RCC_AHB2ENR1_GPIOEEN RCC_AHB2ENR1_GPIOEEN_Msk |
| #define | RCC_AHB2ENR1_GPIOFEN_Pos (5U) |
| #define | RCC_AHB2ENR1_GPIOFEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOFEN_Pos) |
| #define | RCC_AHB2ENR1_GPIOFEN RCC_AHB2ENR1_GPIOFEN_Msk |
| #define | RCC_AHB2ENR1_GPIOGEN_Pos (6U) |
| #define | RCC_AHB2ENR1_GPIOGEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOGEN_Pos) |
| #define | RCC_AHB2ENR1_GPIOGEN RCC_AHB2ENR1_GPIOGEN_Msk |
| #define | RCC_AHB2ENR1_GPIOHEN_Pos (7U) |
| #define | RCC_AHB2ENR1_GPIOHEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOHEN_Pos) |
| #define | RCC_AHB2ENR1_GPIOHEN RCC_AHB2ENR1_GPIOHEN_Msk |
| #define | RCC_AHB2ENR1_GPIOIEN_Pos (8U) |
| #define | RCC_AHB2ENR1_GPIOIEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOIEN_Pos) |
| #define | RCC_AHB2ENR1_GPIOIEN RCC_AHB2ENR1_GPIOIEN_Msk |
| #define | RCC_AHB2ENR1_GPIOJEN_Pos (9U) |
| #define | RCC_AHB2ENR1_GPIOJEN_Msk (0x1UL << RCC_AHB2ENR1_GPIOJEN_Pos) |
| #define | RCC_AHB2ENR1_GPIOJEN RCC_AHB2ENR1_GPIOJEN_Msk |
| #define | RCC_AHB2ENR1_ADC12EN_Pos (10U) |
| #define | RCC_AHB2ENR1_ADC12EN_Msk (0x1UL << RCC_AHB2ENR1_ADC12EN_Pos) |
| #define | RCC_AHB2ENR1_ADC12EN RCC_AHB2ENR1_ADC12EN_Msk |
| #define | RCC_AHB2ENR1_DCMI_PSSIEN_Pos (12U) |
| #define | RCC_AHB2ENR1_DCMI_PSSIEN_Msk (0x1UL << RCC_AHB2ENR1_DCMI_PSSIEN_Pos) |
| #define | RCC_AHB2ENR1_DCMI_PSSIEN RCC_AHB2ENR1_DCMI_PSSIEN_Msk |
| #define | RCC_AHB2ENR1_OTGEN_Pos (14U) |
| #define | RCC_AHB2ENR1_OTGEN_Msk (0x1UL << RCC_AHB2ENR1_OTGEN_Pos) |
| #define | RCC_AHB2ENR1_OTGEN RCC_AHB2ENR1_OTGEN_Msk |
| #define | RCC_AHB2ENR1_USBPHYCEN_Pos (15U) |
| #define | RCC_AHB2ENR1_USBPHYCEN_Msk (0x1UL << RCC_AHB2ENR1_USBPHYCEN_Pos) |
| #define | RCC_AHB2ENR1_USBPHYCEN RCC_AHB2ENR1_USBPHYCEN_Msk |
| #define | RCC_AHB2ENR1_AESEN_Pos (16U) |
| #define | RCC_AHB2ENR1_AESEN_Msk (0x1UL << RCC_AHB2ENR1_AESEN_Pos) |
| #define | RCC_AHB2ENR1_AESEN RCC_AHB2ENR1_AESEN_Msk |
| #define | RCC_AHB2ENR1_HASHEN_Pos (17U) |
| #define | RCC_AHB2ENR1_HASHEN_Msk (0x1UL << RCC_AHB2ENR1_HASHEN_Pos) |
| #define | RCC_AHB2ENR1_HASHEN RCC_AHB2ENR1_HASHEN_Msk |
| #define | RCC_AHB2ENR1_RNGEN_Pos (18U) |
| #define | RCC_AHB2ENR1_RNGEN_Msk (0x1UL << RCC_AHB2ENR1_RNGEN_Pos) |
| #define | RCC_AHB2ENR1_RNGEN RCC_AHB2ENR1_RNGEN_Msk |
| #define | RCC_AHB2ENR1_PKAEN_Pos (19U) |
| #define | RCC_AHB2ENR1_PKAEN_Msk (0x1UL << RCC_AHB2ENR1_PKAEN_Pos) |
| #define | RCC_AHB2ENR1_PKAEN RCC_AHB2ENR1_PKAEN_Msk |
| #define | RCC_AHB2ENR1_SAESEN_Pos (20U) |
| #define | RCC_AHB2ENR1_SAESEN_Msk (0x1UL << RCC_AHB2ENR1_SAESEN_Pos) |
| #define | RCC_AHB2ENR1_SAESEN RCC_AHB2ENR1_SAESEN_Msk |
| #define | RCC_AHB2ENR1_OCTOSPIMEN_Pos (21U) |
| #define | RCC_AHB2ENR1_OCTOSPIMEN_Msk (0x1UL << RCC_AHB2ENR1_OCTOSPIMEN_Pos) |
| #define | RCC_AHB2ENR1_OCTOSPIMEN RCC_AHB2ENR1_OCTOSPIMEN_Msk |
| #define | RCC_AHB2ENR1_OTFDEC1EN_Pos (23U) |
| #define | RCC_AHB2ENR1_OTFDEC1EN_Msk (0x1UL << RCC_AHB2ENR1_OTFDEC1EN_Pos) |
| #define | RCC_AHB2ENR1_OTFDEC1EN RCC_AHB2ENR1_OTFDEC1EN_Msk |
| #define | RCC_AHB2ENR1_OTFDEC2EN_Pos (24U) |
| #define | RCC_AHB2ENR1_OTFDEC2EN_Msk (0x1UL << RCC_AHB2ENR1_OTFDEC2EN_Pos) |
| #define | RCC_AHB2ENR1_OTFDEC2EN RCC_AHB2ENR1_OTFDEC2EN_Msk |
| #define | RCC_AHB2ENR1_SDMMC1EN_Pos (27U) |
| #define | RCC_AHB2ENR1_SDMMC1EN_Msk (0x1UL << RCC_AHB2ENR1_SDMMC1EN_Pos) |
| #define | RCC_AHB2ENR1_SDMMC1EN RCC_AHB2ENR1_SDMMC1EN_Msk |
| #define | RCC_AHB2ENR1_SDMMC2EN_Pos (28U) |
| #define | RCC_AHB2ENR1_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR1_SDMMC2EN_Pos) |
| #define | RCC_AHB2ENR1_SDMMC2EN RCC_AHB2ENR1_SDMMC2EN_Msk |
| #define | RCC_AHB2ENR1_SRAM2EN_Pos (30U) |
| #define | RCC_AHB2ENR1_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR1_SRAM2EN_Pos) |
| #define | RCC_AHB2ENR1_SRAM2EN RCC_AHB2ENR1_SRAM2EN_Msk |
| #define | RCC_AHB2ENR1_SRAM3EN_Pos (31U) |
| #define | RCC_AHB2ENR1_SRAM3EN_Msk (0x1UL << RCC_AHB2ENR1_SRAM3EN_Pos) |
| #define | RCC_AHB2ENR1_SRAM3EN RCC_AHB2ENR1_SRAM3EN_Msk |
| #define | RCC_AHB2ENR2_FSMCEN_Pos (0U) |
| #define | RCC_AHB2ENR2_FSMCEN_Msk (0x1UL << RCC_AHB2ENR2_FSMCEN_Pos) |
| #define | RCC_AHB2ENR2_FSMCEN RCC_AHB2ENR2_FSMCEN_Msk |
| #define | RCC_AHB2ENR2_OCTOSPI1EN_Pos (4U) |
| #define | RCC_AHB2ENR2_OCTOSPI1EN_Msk (0x1UL << RCC_AHB2ENR2_OCTOSPI1EN_Pos) |
| #define | RCC_AHB2ENR2_OCTOSPI1EN RCC_AHB2ENR2_OCTOSPI1EN_Msk |
| #define | RCC_AHB2ENR2_OCTOSPI2EN_Pos (8U) |
| #define | RCC_AHB2ENR2_OCTOSPI2EN_Msk (0x1UL << RCC_AHB2ENR2_OCTOSPI2EN_Pos) |
| #define | RCC_AHB2ENR2_OCTOSPI2EN RCC_AHB2ENR2_OCTOSPI2EN_Msk |
| #define | RCC_AHB2ENR2_HSPI1EN_Pos (12U) |
| #define | RCC_AHB2ENR2_HSPI1EN_Msk (0x1UL << RCC_AHB2ENR2_HSPI1EN_Pos) |
| #define | RCC_AHB2ENR2_HSPI1EN RCC_AHB2ENR2_HSPI1EN_Msk |
| #define | RCC_AHB2ENR2_SRAM6EN_Pos (30U) |
| #define | RCC_AHB2ENR2_SRAM6EN_Msk (0x1UL << RCC_AHB2ENR2_SRAM6EN_Pos) |
| #define | RCC_AHB2ENR2_SRAM6EN RCC_AHB2ENR2_SRAM6EN_Msk |
| #define | RCC_AHB2ENR2_SRAM5EN_Pos (31U) |
| #define | RCC_AHB2ENR2_SRAM5EN_Msk (0x1UL << RCC_AHB2ENR2_SRAM5EN_Pos) |
| #define | RCC_AHB2ENR2_SRAM5EN RCC_AHB2ENR2_SRAM5EN_Msk |
| #define | RCC_AHB3ENR_LPGPIO1EN_Pos (0U) |
| #define | RCC_AHB3ENR_LPGPIO1EN_Msk (0x1UL << RCC_AHB3ENR_LPGPIO1EN_Pos) |
| #define | RCC_AHB3ENR_LPGPIO1EN RCC_AHB3ENR_LPGPIO1EN_Msk |
| #define | RCC_AHB3ENR_PWREN_Pos (2U) |
| #define | RCC_AHB3ENR_PWREN_Msk (0x1UL << RCC_AHB3ENR_PWREN_Pos) |
| #define | RCC_AHB3ENR_PWREN RCC_AHB3ENR_PWREN_Msk |
| #define | RCC_AHB3ENR_ADC4EN_Pos (5U) |
| #define | RCC_AHB3ENR_ADC4EN_Msk (0x1UL << RCC_AHB3ENR_ADC4EN_Pos) |
| #define | RCC_AHB3ENR_ADC4EN RCC_AHB3ENR_ADC4EN_Msk |
| #define | RCC_AHB3ENR_DAC1EN_Pos (6U) |
| #define | RCC_AHB3ENR_DAC1EN_Msk (0x1UL << RCC_AHB3ENR_DAC1EN_Pos) |
| #define | RCC_AHB3ENR_DAC1EN RCC_AHB3ENR_DAC1EN_Msk |
| #define | RCC_AHB3ENR_LPDMA1EN_Pos (9U) |
| #define | RCC_AHB3ENR_LPDMA1EN_Msk (0x1UL << RCC_AHB3ENR_LPDMA1EN_Pos) |
| #define | RCC_AHB3ENR_LPDMA1EN RCC_AHB3ENR_LPDMA1EN_Msk |
| #define | RCC_AHB3ENR_ADF1EN_Pos (10U) |
| #define | RCC_AHB3ENR_ADF1EN_Msk (0x1UL << RCC_AHB3ENR_ADF1EN_Pos) |
| #define | RCC_AHB3ENR_ADF1EN RCC_AHB3ENR_ADF1EN_Msk |
| #define | RCC_AHB3ENR_GTZC2EN_Pos (12U) |
| #define | RCC_AHB3ENR_GTZC2EN_Msk (0x1UL << RCC_AHB3ENR_GTZC2EN_Pos) |
| #define | RCC_AHB3ENR_GTZC2EN RCC_AHB3ENR_GTZC2EN_Msk |
| #define | RCC_AHB3ENR_SRAM4EN_Pos (31U) |
| #define | RCC_AHB3ENR_SRAM4EN_Msk (0x1UL << RCC_AHB3ENR_SRAM4EN_Pos) |
| #define | RCC_AHB3ENR_SRAM4EN RCC_AHB3ENR_SRAM4EN_Msk |
| #define | RCC_APB1ENR1_TIM2EN_Pos (0U) |
| #define | RCC_APB1ENR1_TIM2EN_Msk (0x1UL << RCC_APB1ENR1_TIM2EN_Pos) |
| #define | RCC_APB1ENR1_TIM2EN RCC_APB1ENR1_TIM2EN_Msk |
| #define | RCC_APB1ENR1_TIM3EN_Pos (1U) |
| #define | RCC_APB1ENR1_TIM3EN_Msk (0x1UL << RCC_APB1ENR1_TIM3EN_Pos) |
| #define | RCC_APB1ENR1_TIM3EN RCC_APB1ENR1_TIM3EN_Msk |
| #define | RCC_APB1ENR1_TIM4EN_Pos (2U) |
| #define | RCC_APB1ENR1_TIM4EN_Msk (0x1UL << RCC_APB1ENR1_TIM4EN_Pos) |
| #define | RCC_APB1ENR1_TIM4EN RCC_APB1ENR1_TIM4EN_Msk |
| #define | RCC_APB1ENR1_TIM5EN_Pos (3U) |
| #define | RCC_APB1ENR1_TIM5EN_Msk (0x1UL << RCC_APB1ENR1_TIM5EN_Pos) |
| #define | RCC_APB1ENR1_TIM5EN RCC_APB1ENR1_TIM5EN_Msk |
| #define | RCC_APB1ENR1_TIM6EN_Pos (4U) |
| #define | RCC_APB1ENR1_TIM6EN_Msk (0x1UL << RCC_APB1ENR1_TIM6EN_Pos) |
| #define | RCC_APB1ENR1_TIM6EN RCC_APB1ENR1_TIM6EN_Msk |
| #define | RCC_APB1ENR1_TIM7EN_Pos (5U) |
| #define | RCC_APB1ENR1_TIM7EN_Msk (0x1UL << RCC_APB1ENR1_TIM7EN_Pos) |
| #define | RCC_APB1ENR1_TIM7EN RCC_APB1ENR1_TIM7EN_Msk |
| #define | RCC_APB1ENR1_WWDGEN_Pos (11U) |
| #define | RCC_APB1ENR1_WWDGEN_Msk (0x1UL << RCC_APB1ENR1_WWDGEN_Pos) |
| #define | RCC_APB1ENR1_WWDGEN RCC_APB1ENR1_WWDGEN_Msk |
| #define | RCC_APB1ENR1_SPI2EN_Pos (14U) |
| #define | RCC_APB1ENR1_SPI2EN_Msk (0x1UL << RCC_APB1ENR1_SPI2EN_Pos) |
| #define | RCC_APB1ENR1_SPI2EN RCC_APB1ENR1_SPI2EN_Msk |
| #define | RCC_APB1ENR1_USART2EN_Pos (17U) |
| #define | RCC_APB1ENR1_USART2EN_Msk (0x1UL << RCC_APB1ENR1_USART2EN_Pos) |
| #define | RCC_APB1ENR1_USART2EN RCC_APB1ENR1_USART2EN_Msk |
| #define | RCC_APB1ENR1_USART3EN_Pos (18U) |
| #define | RCC_APB1ENR1_USART3EN_Msk (0x1UL << RCC_APB1ENR1_USART3EN_Pos) |
| #define | RCC_APB1ENR1_USART3EN RCC_APB1ENR1_USART3EN_Msk |
| #define | RCC_APB1ENR1_UART4EN_Pos (19U) |
| #define | RCC_APB1ENR1_UART4EN_Msk (0x1UL << RCC_APB1ENR1_UART4EN_Pos) |
| #define | RCC_APB1ENR1_UART4EN RCC_APB1ENR1_UART4EN_Msk |
| #define | RCC_APB1ENR1_UART5EN_Pos (20U) |
| #define | RCC_APB1ENR1_UART5EN_Msk (0x1UL << RCC_APB1ENR1_UART5EN_Pos) |
| #define | RCC_APB1ENR1_UART5EN RCC_APB1ENR1_UART5EN_Msk |
| #define | RCC_APB1ENR1_I2C1EN_Pos (21U) |
| #define | RCC_APB1ENR1_I2C1EN_Msk (0x1UL << RCC_APB1ENR1_I2C1EN_Pos) |
| #define | RCC_APB1ENR1_I2C1EN RCC_APB1ENR1_I2C1EN_Msk |
| #define | RCC_APB1ENR1_I2C2EN_Pos (22U) |
| #define | RCC_APB1ENR1_I2C2EN_Msk (0x1UL << RCC_APB1ENR1_I2C2EN_Pos) |
| #define | RCC_APB1ENR1_I2C2EN RCC_APB1ENR1_I2C2EN_Msk |
| #define | RCC_APB1ENR1_CRSEN_Pos (24U) |
| #define | RCC_APB1ENR1_CRSEN_Msk (0x1UL << RCC_APB1ENR1_CRSEN_Pos) |
| #define | RCC_APB1ENR1_CRSEN RCC_APB1ENR1_CRSEN_Msk |
| #define | RCC_APB1ENR1_USART6EN_Pos (25U) |
| #define | RCC_APB1ENR1_USART6EN_Msk (0x1UL << RCC_APB1ENR1_USART6EN_Pos) |
| #define | RCC_APB1ENR1_USART6EN RCC_APB1ENR1_USART6EN_Msk |
| #define | RCC_APB1ENR2_I2C4EN_Pos (1U) |
| #define | RCC_APB1ENR2_I2C4EN_Msk (0x1UL << RCC_APB1ENR2_I2C4EN_Pos) |
| #define | RCC_APB1ENR2_I2C4EN RCC_APB1ENR2_I2C4EN_Msk |
| #define | RCC_APB1ENR2_LPTIM2EN_Pos (5U) |
| #define | RCC_APB1ENR2_LPTIM2EN_Msk (0x1UL << RCC_APB1ENR2_LPTIM2EN_Pos) |
| #define | RCC_APB1ENR2_LPTIM2EN RCC_APB1ENR2_LPTIM2EN_Msk |
| #define | RCC_APB1ENR2_I2C5EN_Pos (6U) |
| #define | RCC_APB1ENR2_I2C5EN_Msk (0x1UL << RCC_APB1ENR2_I2C5EN_Pos) |
| #define | RCC_APB1ENR2_I2C5EN RCC_APB1ENR2_I2C5EN_Msk |
| #define | RCC_APB1ENR2_I2C6EN_Pos (7U) |
| #define | RCC_APB1ENR2_I2C6EN_Msk (0x1UL << RCC_APB1ENR2_I2C6EN_Pos) |
| #define | RCC_APB1ENR2_I2C6EN RCC_APB1ENR2_I2C6EN_Msk |
| #define | RCC_APB1ENR2_FDCAN1EN_Pos (9U) |
| #define | RCC_APB1ENR2_FDCAN1EN_Msk (0x1UL << RCC_APB1ENR2_FDCAN1EN_Pos) |
| #define | RCC_APB1ENR2_FDCAN1EN RCC_APB1ENR2_FDCAN1EN_Msk |
| #define | RCC_APB1ENR2_UCPD1EN_Pos (23U) |
| #define | RCC_APB1ENR2_UCPD1EN_Msk (0x1UL << RCC_APB1ENR2_UCPD1EN_Pos) |
| #define | RCC_APB1ENR2_UCPD1EN RCC_APB1ENR2_UCPD1EN_Msk |
| #define | RCC_APB2ENR_TIM1EN_Pos (11U) |
| #define | RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) |
| #define | RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk |
| #define | RCC_APB2ENR_SPI1EN_Pos (12U) |
| #define | RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) |
| #define | RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk |
| #define | RCC_APB2ENR_TIM8EN_Pos (13U) |
| #define | RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) |
| #define | RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk |
| #define | RCC_APB2ENR_USART1EN_Pos (14U) |
| #define | RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) |
| #define | RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk |
| #define | RCC_APB2ENR_TIM15EN_Pos (16U) |
| #define | RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) |
| #define | RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk |
| #define | RCC_APB2ENR_TIM16EN_Pos (17U) |
| #define | RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) |
| #define | RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk |
| #define | RCC_APB2ENR_TIM17EN_Pos (18U) |
| #define | RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) |
| #define | RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk |
| #define | RCC_APB2ENR_SAI1EN_Pos (21U) |
| #define | RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) |
| #define | RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk |
| #define | RCC_APB2ENR_SAI2EN_Pos (22U) |
| #define | RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) |
| #define | RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk |
| #define | RCC_APB2ENR_GFXTIMEN_Pos (25U) |
| #define | RCC_APB2ENR_GFXTIMEN_Msk (0x1UL << RCC_APB2ENR_GFXTIMEN_Pos) |
| #define | RCC_APB2ENR_GFXTIMEN RCC_APB2ENR_GFXTIMEN_Msk |
| #define | RCC_APB2ENR_LTDCEN_Pos (26U) |
| #define | RCC_APB2ENR_LTDCEN_Msk (0x1UL << RCC_APB2ENR_LTDCEN_Pos) |
| #define | RCC_APB2ENR_LTDCEN RCC_APB2ENR_LTDCEN_Msk |
| #define | RCC_APB2ENR_DSIHOSTEN_Pos (27U) |
| #define | RCC_APB2ENR_DSIHOSTEN_Msk (0x1UL << RCC_APB2ENR_DSIHOSTEN_Pos) |
| #define | RCC_APB2ENR_DSIHOSTEN RCC_APB2ENR_DSIHOSTEN_Msk |
| #define | RCC_APB3ENR_SYSCFGEN_Pos (1U) |
| #define | RCC_APB3ENR_SYSCFGEN_Msk (0x1UL << RCC_APB3ENR_SYSCFGEN_Pos) |
| #define | RCC_APB3ENR_SYSCFGEN RCC_APB3ENR_SYSCFGEN_Msk |
| #define | RCC_APB3ENR_SPI3EN_Pos (5U) |
| #define | RCC_APB3ENR_SPI3EN_Msk (0x1UL << RCC_APB3ENR_SPI3EN_Pos) |
| #define | RCC_APB3ENR_SPI3EN RCC_APB3ENR_SPI3EN_Msk |
| #define | RCC_APB3ENR_LPUART1EN_Pos (6U) |
| #define | RCC_APB3ENR_LPUART1EN_Msk (0x1UL << RCC_APB3ENR_LPUART1EN_Pos) |
| #define | RCC_APB3ENR_LPUART1EN RCC_APB3ENR_LPUART1EN_Msk |
| #define | RCC_APB3ENR_I2C3EN_Pos (7U) |
| #define | RCC_APB3ENR_I2C3EN_Msk (0x1UL << RCC_APB3ENR_I2C3EN_Pos) |
| #define | RCC_APB3ENR_I2C3EN RCC_APB3ENR_I2C3EN_Msk |
| #define | RCC_APB3ENR_LPTIM1EN_Pos (11U) |
| #define | RCC_APB3ENR_LPTIM1EN_Msk (0x1UL << RCC_APB3ENR_LPTIM1EN_Pos) |
| #define | RCC_APB3ENR_LPTIM1EN RCC_APB3ENR_LPTIM1EN_Msk |
| #define | RCC_APB3ENR_LPTIM3EN_Pos (12U) |
| #define | RCC_APB3ENR_LPTIM3EN_Msk (0x1UL << RCC_APB3ENR_LPTIM3EN_Pos) |
| #define | RCC_APB3ENR_LPTIM3EN RCC_APB3ENR_LPTIM3EN_Msk |
| #define | RCC_APB3ENR_LPTIM4EN_Pos (13U) |
| #define | RCC_APB3ENR_LPTIM4EN_Msk (0x1UL << RCC_APB3ENR_LPTIM4EN_Pos) |
| #define | RCC_APB3ENR_LPTIM4EN RCC_APB3ENR_LPTIM4EN_Msk |
| #define | RCC_APB3ENR_OPAMPEN_Pos (14U) |
| #define | RCC_APB3ENR_OPAMPEN_Msk (0x1UL << RCC_APB3ENR_OPAMPEN_Pos) |
| #define | RCC_APB3ENR_OPAMPEN RCC_APB3ENR_OPAMPEN_Msk |
| #define | RCC_APB3ENR_COMPEN_Pos (15U) |
| #define | RCC_APB3ENR_COMPEN_Msk (0x1UL << RCC_APB3ENR_COMPEN_Pos) |
| #define | RCC_APB3ENR_COMPEN RCC_APB3ENR_COMPEN_Msk |
| #define | RCC_APB3ENR_VREFEN_Pos (20U) |
| #define | RCC_APB3ENR_VREFEN_Msk (0x1UL << RCC_APB3ENR_VREFEN_Pos) |
| #define | RCC_APB3ENR_VREFEN RCC_APB3ENR_VREFEN_Msk |
| #define | RCC_APB3ENR_RTCAPBEN_Pos (21U) |
| #define | RCC_APB3ENR_RTCAPBEN_Msk (0x1UL << RCC_APB3ENR_RTCAPBEN_Pos) |
| #define | RCC_APB3ENR_RTCAPBEN RCC_APB3ENR_RTCAPBEN_Msk |
| #define | RCC_AHB1SMENR_GPDMA1SMEN_Pos (0U) |
| #define | RCC_AHB1SMENR_GPDMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GPDMA1SMEN_Pos) |
| #define | RCC_AHB1SMENR_GPDMA1SMEN RCC_AHB1SMENR_GPDMA1SMEN_Msk |
| #define | RCC_AHB1SMENR_CORDICSMEN_Pos (1U) |
| #define | RCC_AHB1SMENR_CORDICSMEN_Msk (0x1UL << RCC_AHB1SMENR_CORDICSMEN_Pos) |
| #define | RCC_AHB1SMENR_CORDICSMEN RCC_AHB1SMENR_CORDICSMEN_Msk |
| #define | RCC_AHB1SMENR_FMACSMEN_Pos (2U) |
| #define | RCC_AHB1SMENR_FMACSMEN_Msk (0x1UL << RCC_AHB1SMENR_FMACSMEN_Pos) |
| #define | RCC_AHB1SMENR_FMACSMEN RCC_AHB1SMENR_FMACSMEN_Msk |
| #define | RCC_AHB1SMENR_MDF1SMEN_Pos (3U) |
| #define | RCC_AHB1SMENR_MDF1SMEN_Msk (0x1UL << RCC_AHB1SMENR_MDF1SMEN_Pos) |
| #define | RCC_AHB1SMENR_MDF1SMEN RCC_AHB1SMENR_MDF1SMEN_Msk |
| #define | RCC_AHB1SMENR_FLASHSMEN_Pos (8U) |
| #define | RCC_AHB1SMENR_FLASHSMEN_Msk (0x1UL << RCC_AHB1SMENR_FLASHSMEN_Pos) |
| #define | RCC_AHB1SMENR_FLASHSMEN RCC_AHB1SMENR_FLASHSMEN_Msk |
| #define | RCC_AHB1SMENR_CRCSMEN_Pos (12U) |
| #define | RCC_AHB1SMENR_CRCSMEN_Msk (0x1UL << RCC_AHB1SMENR_CRCSMEN_Pos) |
| #define | RCC_AHB1SMENR_CRCSMEN RCC_AHB1SMENR_CRCSMEN_Msk |
| #define | RCC_AHB1SMENR_JPEGSMEN_Pos (15U) |
| #define | RCC_AHB1SMENR_JPEGSMEN_Msk (0x1UL << RCC_AHB1SMENR_JPEGSMEN_Pos) |
| #define | RCC_AHB1SMENR_JPEGSMEN RCC_AHB1SMENR_JPEGSMEN_Msk |
| #define | RCC_AHB1SMENR_TSCSMEN_Pos (16U) |
| #define | RCC_AHB1SMENR_TSCSMEN_Msk (0x1UL << RCC_AHB1SMENR_TSCSMEN_Pos) |
| #define | RCC_AHB1SMENR_TSCSMEN RCC_AHB1SMENR_TSCSMEN_Msk |
| #define | RCC_AHB1SMENR_RAMCFGSMEN_Pos (17U) |
| #define | RCC_AHB1SMENR_RAMCFGSMEN_Msk (0x1UL << RCC_AHB1SMENR_RAMCFGSMEN_Pos) |
| #define | RCC_AHB1SMENR_RAMCFGSMEN RCC_AHB1SMENR_RAMCFGSMEN_Msk |
| #define | RCC_AHB1SMENR_DMA2DSMEN_Pos (18U) |
| #define | RCC_AHB1SMENR_DMA2DSMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA2DSMEN_Pos) |
| #define | RCC_AHB1SMENR_DMA2DSMEN RCC_AHB1SMENR_DMA2DSMEN_Msk |
| #define | RCC_AHB1SMENR_GFXMMUSMEN_Pos (19U) |
| #define | RCC_AHB1SMENR_GFXMMUSMEN_Msk (0x1UL << RCC_AHB1SMENR_GFXMMUSMEN_Pos) |
| #define | RCC_AHB1SMENR_GFXMMUSMEN RCC_AHB1SMENR_GFXMMUSMEN_Msk |
| #define | RCC_AHB1SMENR_GPU2DSMEN_Pos (20U) |
| #define | RCC_AHB1SMENR_GPU2DSMEN_Msk (0x1UL << RCC_AHB1SMENR_GPU2DSMEN_Pos) |
| #define | RCC_AHB1SMENR_GPU2DSMEN RCC_AHB1SMENR_GPU2DSMEN_Msk |
| #define | RCC_AHB1SMENR_DCACHE2SMEN_Pos (21U) |
| #define | RCC_AHB1SMENR_DCACHE2SMEN_Msk (0x1UL << RCC_AHB1SMENR_DCACHE2SMEN_Pos) |
| #define | RCC_AHB1SMENR_DCACHE2SMEN RCC_AHB1SMENR_DCACHE2SMEN_Msk |
| #define | RCC_AHB1SMENR_GTZC1SMEN_Pos (24U) |
| #define | RCC_AHB1SMENR_GTZC1SMEN_Msk (0x1UL << RCC_AHB1SMENR_GTZC1SMEN_Pos) |
| #define | RCC_AHB1SMENR_GTZC1SMEN RCC_AHB1SMENR_GTZC1SMEN_Msk |
| #define | RCC_AHB1SMENR_BKPSRAMSMEN_Pos (28U) |
| #define | RCC_AHB1SMENR_BKPSRAMSMEN_Msk (0x1UL << RCC_AHB1SMENR_BKPSRAMSMEN_Pos) |
| #define | RCC_AHB1SMENR_BKPSRAMSMEN RCC_AHB1SMENR_BKPSRAMSMEN_Msk |
| #define | RCC_AHB1SMENR_ICACHESMEN_Pos (29U) |
| #define | RCC_AHB1SMENR_ICACHESMEN_Msk (0x1UL << RCC_AHB1SMENR_ICACHESMEN_Pos) |
| #define | RCC_AHB1SMENR_ICACHESMEN RCC_AHB1SMENR_ICACHESMEN_Msk |
| #define | RCC_AHB1SMENR_DCACHE1SMEN_Pos (30U) |
| #define | RCC_AHB1SMENR_DCACHE1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DCACHE1SMEN_Pos) |
| #define | RCC_AHB1SMENR_DCACHE1SMEN RCC_AHB1SMENR_DCACHE1SMEN_Msk |
| #define | RCC_AHB1SMENR_SRAM1SMEN_Pos (31U) |
| #define | RCC_AHB1SMENR_SRAM1SMEN_Msk (0x1UL << RCC_AHB1SMENR_SRAM1SMEN_Pos) |
| #define | RCC_AHB1SMENR_SRAM1SMEN RCC_AHB1SMENR_SRAM1SMEN_Msk |
| #define | RCC_AHB2SMENR1_GPIOASMEN_Pos (0U) |
| #define | RCC_AHB2SMENR1_GPIOASMEN_Msk (0x1UL << RCC_AHB2SMENR1_GPIOASMEN_Pos) |
| #define | RCC_AHB2SMENR1_GPIOASMEN RCC_AHB2SMENR1_GPIOASMEN_Msk |
| #define | RCC_AHB2SMENR1_GPIOBSMEN_Pos (1U) |
| #define | RCC_AHB2SMENR1_GPIOBSMEN_Msk (0x1UL << RCC_AHB2SMENR1_GPIOBSMEN_Pos) |
| #define | RCC_AHB2SMENR1_GPIOBSMEN RCC_AHB2SMENR1_GPIOBSMEN_Msk |
| #define | RCC_AHB2SMENR1_GPIOCSMEN_Pos (2U) |
| #define | RCC_AHB2SMENR1_GPIOCSMEN_Msk (0x1UL << RCC_AHB2SMENR1_GPIOCSMEN_Pos) |
| #define | RCC_AHB2SMENR1_GPIOCSMEN RCC_AHB2SMENR1_GPIOCSMEN_Msk |
| #define | RCC_AHB2SMENR1_GPIODSMEN_Pos (3U) |
| #define | RCC_AHB2SMENR1_GPIODSMEN_Msk (0x1UL << RCC_AHB2SMENR1_GPIODSMEN_Pos) |
| #define | RCC_AHB2SMENR1_GPIODSMEN RCC_AHB2SMENR1_GPIODSMEN_Msk |
| #define | RCC_AHB2SMENR1_GPIOESMEN_Pos (4U) |
| #define | RCC_AHB2SMENR1_GPIOESMEN_Msk (0x1UL << RCC_AHB2SMENR1_GPIOESMEN_Pos) |
| #define | RCC_AHB2SMENR1_GPIOESMEN RCC_AHB2SMENR1_GPIOESMEN_Msk |
| #define | RCC_AHB2SMENR1_GPIOFSMEN_Pos (5U) |
| #define | RCC_AHB2SMENR1_GPIOFSMEN_Msk (0x1UL << RCC_AHB2SMENR1_GPIOFSMEN_Pos) |
| #define | RCC_AHB2SMENR1_GPIOFSMEN RCC_AHB2SMENR1_GPIOFSMEN_Msk |
| #define | RCC_AHB2SMENR1_GPIOGSMEN_Pos (6U) |
| #define | RCC_AHB2SMENR1_GPIOGSMEN_Msk (0x1UL << RCC_AHB2SMENR1_GPIOGSMEN_Pos) |
| #define | RCC_AHB2SMENR1_GPIOGSMEN RCC_AHB2SMENR1_GPIOGSMEN_Msk |
| #define | RCC_AHB2SMENR1_GPIOHSMEN_Pos (7U) |
| #define | RCC_AHB2SMENR1_GPIOHSMEN_Msk (0x1UL << RCC_AHB2SMENR1_GPIOHSMEN_Pos) |
| #define | RCC_AHB2SMENR1_GPIOHSMEN RCC_AHB2SMENR1_GPIOHSMEN_Msk |
| #define | RCC_AHB2SMENR1_GPIOISMEN_Pos (8U) |
| #define | RCC_AHB2SMENR1_GPIOISMEN_Msk (0x1UL << RCC_AHB2SMENR1_GPIOISMEN_Pos) |
| #define | RCC_AHB2SMENR1_GPIOISMEN RCC_AHB2SMENR1_GPIOISMEN_Msk |
| #define | RCC_AHB2SMENR1_GPIOJSMEN_Pos (9U) |
| #define | RCC_AHB2SMENR1_GPIOJSMEN_Msk (0x1UL << RCC_AHB2SMENR1_GPIOJSMEN_Pos) |
| #define | RCC_AHB2SMENR1_GPIOJSMEN RCC_AHB2SMENR1_GPIOJSMEN_Msk |
| #define | RCC_AHB2SMENR1_ADC12SMEN_Pos (10U) |
| #define | RCC_AHB2SMENR1_ADC12SMEN_Msk (0x1UL << RCC_AHB2SMENR1_ADC12SMEN_Pos) |
| #define | RCC_AHB2SMENR1_ADC12SMEN RCC_AHB2SMENR1_ADC12SMEN_Msk |
| #define | RCC_AHB2SMENR1_DCMI_PSSISMEN_Pos (12U) |
| #define | RCC_AHB2SMENR1_DCMI_PSSISMEN_Msk (0x1UL << RCC_AHB2SMENR1_DCMI_PSSISMEN_Pos) |
| #define | RCC_AHB2SMENR1_DCMI_PSSISMEN RCC_AHB2SMENR1_DCMI_PSSISMEN_Msk |
| #define | RCC_AHB2SMENR1_OTGSMEN_Pos (14U) |
| #define | RCC_AHB2SMENR1_OTGSMEN_Msk (0x1UL << RCC_AHB2SMENR1_OTGSMEN_Pos) |
| #define | RCC_AHB2SMENR1_OTGSMEN RCC_AHB2SMENR1_OTGSMEN_Msk |
| #define | RCC_AHB2SMENR1_USBPHYCSMEN_Pos (15U) |
| #define | RCC_AHB2SMENR1_USBPHYCSMEN_Msk (0x1UL << RCC_AHB2SMENR1_USBPHYCSMEN_Pos) |
| #define | RCC_AHB2SMENR1_USBPHYCSMEN RCC_AHB2SMENR1_USBPHYCSMEN_Msk |
| #define | RCC_AHB2SMENR1_AESSMEN_Pos (16U) |
| #define | RCC_AHB2SMENR1_AESSMEN_Msk (0x1UL << RCC_AHB2SMENR1_AESSMEN_Pos) |
| #define | RCC_AHB2SMENR1_AESSMEN RCC_AHB2SMENR1_AESSMEN_Msk |
| #define | RCC_AHB2SMENR1_HASHSMEN_Pos (17U) |
| #define | RCC_AHB2SMENR1_HASHSMEN_Msk (0x1UL << RCC_AHB2SMENR1_HASHSMEN_Pos) |
| #define | RCC_AHB2SMENR1_HASHSMEN RCC_AHB2SMENR1_HASHSMEN_Msk |
| #define | RCC_AHB2SMENR1_RNGSMEN_Pos (18U) |
| #define | RCC_AHB2SMENR1_RNGSMEN_Msk (0x1UL << RCC_AHB2SMENR1_RNGSMEN_Pos) |
| #define | RCC_AHB2SMENR1_RNGSMEN RCC_AHB2SMENR1_RNGSMEN_Msk |
| #define | RCC_AHB2SMENR1_PKASMEN_Pos (19U) |
| #define | RCC_AHB2SMENR1_PKASMEN_Msk (0x1UL << RCC_AHB2SMENR1_PKASMEN_Pos) |
| #define | RCC_AHB2SMENR1_PKASMEN RCC_AHB2SMENR1_PKASMEN_Msk |
| #define | RCC_AHB2SMENR1_SAESSMEN_Pos (20U) |
| #define | RCC_AHB2SMENR1_SAESSMEN_Msk (0x1UL << RCC_AHB2SMENR1_SAESSMEN_Pos) |
| #define | RCC_AHB2SMENR1_SAESSMEN RCC_AHB2SMENR1_SAESSMEN_Msk |
| #define | RCC_AHB2SMENR1_OCTOSPIMSMEN_Pos (21U) |
| #define | RCC_AHB2SMENR1_OCTOSPIMSMEN_Msk (0x1UL << RCC_AHB2SMENR1_OCTOSPIMSMEN_Pos) |
| #define | RCC_AHB2SMENR1_OCTOSPIMSMEN RCC_AHB2SMENR1_OCTOSPIMSMEN_Msk |
| #define | RCC_AHB2SMENR1_OTFDEC1SMEN_Pos (23U) |
| #define | RCC_AHB2SMENR1_OTFDEC1SMEN_Msk (0x1UL << RCC_AHB2SMENR1_OTFDEC1SMEN_Pos) |
| #define | RCC_AHB2SMENR1_OTFDEC1SMEN RCC_AHB2SMENR1_OTFDEC1SMEN_Msk |
| #define | RCC_AHB2SMENR1_OTFDEC2SMEN_Pos (24U) |
| #define | RCC_AHB2SMENR1_OTFDEC2SMEN_Msk (0x1UL << RCC_AHB2SMENR1_OTFDEC2SMEN_Pos) |
| #define | RCC_AHB2SMENR1_OTFDEC2SMEN RCC_AHB2SMENR1_OTFDEC2SMEN_Msk |
| #define | RCC_AHB2SMENR1_SDMMC1SMEN_Pos (27U) |
| #define | RCC_AHB2SMENR1_SDMMC1SMEN_Msk (0x1UL << RCC_AHB2SMENR1_SDMMC1SMEN_Pos) |
| #define | RCC_AHB2SMENR1_SDMMC1SMEN RCC_AHB2SMENR1_SDMMC1SMEN_Msk |
| #define | RCC_AHB2SMENR1_SDMMC2SMEN_Pos (28U) |
| #define | RCC_AHB2SMENR1_SDMMC2SMEN_Msk (0x1UL << RCC_AHB2SMENR1_SDMMC2SMEN_Pos) |
| #define | RCC_AHB2SMENR1_SDMMC2SMEN RCC_AHB2SMENR1_SDMMC2SMEN_Msk |
| #define | RCC_AHB2SMENR1_SRAM2SMEN_Pos (30U) |
| #define | RCC_AHB2SMENR1_SRAM2SMEN_Msk (0x1UL << RCC_AHB2SMENR1_SRAM2SMEN_Pos) |
| #define | RCC_AHB2SMENR1_SRAM2SMEN RCC_AHB2SMENR1_SRAM2SMEN_Msk |
| #define | RCC_AHB2SMENR1_SRAM3SMEN_Pos (31U) |
| #define | RCC_AHB2SMENR1_SRAM3SMEN_Msk (0x1UL << RCC_AHB2SMENR1_SRAM3SMEN_Pos) |
| #define | RCC_AHB2SMENR1_SRAM3SMEN RCC_AHB2SMENR1_SRAM3SMEN_Msk |
| #define | RCC_AHB2SMENR2_FSMCSMEN_Pos (0U) |
| #define | RCC_AHB2SMENR2_FSMCSMEN_Msk (0x1UL << RCC_AHB2SMENR2_FSMCSMEN_Pos) |
| #define | RCC_AHB2SMENR2_FSMCSMEN RCC_AHB2SMENR2_FSMCSMEN_Msk |
| #define | RCC_AHB2SMENR2_OCTOSPI1SMEN_Pos (4U) |
| #define | RCC_AHB2SMENR2_OCTOSPI1SMEN_Msk (0x1UL << RCC_AHB2SMENR2_OCTOSPI1SMEN_Pos) |
| #define | RCC_AHB2SMENR2_OCTOSPI1SMEN RCC_AHB2SMENR2_OCTOSPI1SMEN_Msk |
| #define | RCC_AHB2SMENR2_OCTOSPI2SMEN_Pos (8U) |
| #define | RCC_AHB2SMENR2_OCTOSPI2SMEN_Msk (0x1UL << RCC_AHB2SMENR2_OCTOSPI2SMEN_Pos) |
| #define | RCC_AHB2SMENR2_OCTOSPI2SMEN RCC_AHB2SMENR2_OCTOSPI2SMEN_Msk |
| #define | RCC_AHB2SMENR2_HSPI1SMEN_Pos (12U) |
| #define | RCC_AHB2SMENR2_HSPI1SMEN_Msk (0x1UL << RCC_AHB2SMENR2_HSPI1SMEN_Pos) |
| #define | RCC_AHB2SMENR2_HSPI1SMEN RCC_AHB2SMENR2_HSPI1SMEN_Msk |
| #define | RCC_AHB2SMENR2_SRAM6SMEN_Pos (30U) |
| #define | RCC_AHB2SMENR2_SRAM6SMEN_Msk (0x1UL << RCC_AHB2SMENR2_SRAM6SMEN_Pos) |
| #define | RCC_AHB2SMENR2_SRAM6SMEN RCC_AHB2SMENR2_SRAM6SMEN_Msk |
| #define | RCC_AHB2SMENR2_SRAM5SMEN_Pos (31U) |
| #define | RCC_AHB2SMENR2_SRAM5SMEN_Msk (0x1UL << RCC_AHB2SMENR2_SRAM5SMEN_Pos) |
| #define | RCC_AHB2SMENR2_SRAM5SMEN RCC_AHB2SMENR2_SRAM5SMEN_Msk |
| #define | RCC_AHB3SMENR_LPGPIO1SMEN_Pos (0U) |
| #define | RCC_AHB3SMENR_LPGPIO1SMEN_Msk (0x1UL << RCC_AHB3SMENR_LPGPIO1SMEN_Pos) |
| #define | RCC_AHB3SMENR_LPGPIO1SMEN RCC_AHB3SMENR_LPGPIO1SMEN_Msk |
| #define | RCC_AHB3SMENR_PWRSMEN_Pos (2U) |
| #define | RCC_AHB3SMENR_PWRSMEN_Msk (0x1UL << RCC_AHB3SMENR_PWRSMEN_Pos) |
| #define | RCC_AHB3SMENR_PWRSMEN RCC_AHB3SMENR_PWRSMEN_Msk |
| #define | RCC_AHB3SMENR_ADC4SMEN_Pos (5U) |
| #define | RCC_AHB3SMENR_ADC4SMEN_Msk (0x1UL << RCC_AHB3SMENR_ADC4SMEN_Pos) |
| #define | RCC_AHB3SMENR_ADC4SMEN RCC_AHB3SMENR_ADC4SMEN_Msk |
| #define | RCC_AHB3SMENR_DAC1SMEN_Pos (6U) |
| #define | RCC_AHB3SMENR_DAC1SMEN_Msk (0x1UL << RCC_AHB3SMENR_DAC1SMEN_Pos) |
| #define | RCC_AHB3SMENR_DAC1SMEN RCC_AHB3SMENR_DAC1SMEN_Msk |
| #define | RCC_AHB3SMENR_LPDMA1SMEN_Pos (9U) |
| #define | RCC_AHB3SMENR_LPDMA1SMEN_Msk (0x1UL << RCC_AHB3SMENR_LPDMA1SMEN_Pos) |
| #define | RCC_AHB3SMENR_LPDMA1SMEN RCC_AHB3SMENR_LPDMA1SMEN_Msk |
| #define | RCC_AHB3SMENR_ADF1SMEN_Pos (10U) |
| #define | RCC_AHB3SMENR_ADF1SMEN_Msk (0x1UL << RCC_AHB3SMENR_ADF1SMEN_Pos) |
| #define | RCC_AHB3SMENR_ADF1SMEN RCC_AHB3SMENR_ADF1SMEN_Msk |
| #define | RCC_AHB3SMENR_GTZC2SMEN_Pos (12U) |
| #define | RCC_AHB3SMENR_GTZC2SMEN_Msk (0x1UL << RCC_AHB3SMENR_GTZC2SMEN_Pos) |
| #define | RCC_AHB3SMENR_GTZC2SMEN RCC_AHB3SMENR_GTZC2SMEN_Msk |
| #define | RCC_AHB3SMENR_SRAM4SMEN_Pos (31U) |
| #define | RCC_AHB3SMENR_SRAM4SMEN_Msk (0x1UL << RCC_AHB3SMENR_SRAM4SMEN_Pos) |
| #define | RCC_AHB3SMENR_SRAM4SMEN RCC_AHB3SMENR_SRAM4SMEN_Msk |
| #define | RCC_APB1SMENR1_TIM2SMEN_Pos (0U) |
| #define | RCC_APB1SMENR1_TIM2SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM2SMEN_Pos) |
| #define | RCC_APB1SMENR1_TIM2SMEN RCC_APB1SMENR1_TIM2SMEN_Msk |
| #define | RCC_APB1SMENR1_TIM3SMEN_Pos (1U) |
| #define | RCC_APB1SMENR1_TIM3SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM3SMEN_Pos) |
| #define | RCC_APB1SMENR1_TIM3SMEN RCC_APB1SMENR1_TIM3SMEN_Msk |
| #define | RCC_APB1SMENR1_TIM4SMEN_Pos (2U) |
| #define | RCC_APB1SMENR1_TIM4SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM4SMEN_Pos) |
| #define | RCC_APB1SMENR1_TIM4SMEN RCC_APB1SMENR1_TIM4SMEN_Msk |
| #define | RCC_APB1SMENR1_TIM5SMEN_Pos (3U) |
| #define | RCC_APB1SMENR1_TIM5SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM5SMEN_Pos) |
| #define | RCC_APB1SMENR1_TIM5SMEN RCC_APB1SMENR1_TIM5SMEN_Msk |
| #define | RCC_APB1SMENR1_TIM6SMEN_Pos (4U) |
| #define | RCC_APB1SMENR1_TIM6SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM6SMEN_Pos) |
| #define | RCC_APB1SMENR1_TIM6SMEN RCC_APB1SMENR1_TIM6SMEN_Msk |
| #define | RCC_APB1SMENR1_TIM7SMEN_Pos (5U) |
| #define | RCC_APB1SMENR1_TIM7SMEN_Msk (0x1UL << RCC_APB1SMENR1_TIM7SMEN_Pos) |
| #define | RCC_APB1SMENR1_TIM7SMEN RCC_APB1SMENR1_TIM7SMEN_Msk |
| #define | RCC_APB1SMENR1_WWDGSMEN_Pos (11U) |
| #define | RCC_APB1SMENR1_WWDGSMEN_Msk (0x1UL << RCC_APB1SMENR1_WWDGSMEN_Pos) |
| #define | RCC_APB1SMENR1_WWDGSMEN RCC_APB1SMENR1_WWDGSMEN_Msk |
| #define | RCC_APB1SMENR1_SPI2SMEN_Pos (14U) |
| #define | RCC_APB1SMENR1_SPI2SMEN_Msk (0x1UL << RCC_APB1SMENR1_SPI2SMEN_Pos) |
| #define | RCC_APB1SMENR1_SPI2SMEN RCC_APB1SMENR1_SPI2SMEN_Msk |
| #define | RCC_APB1SMENR1_USART2SMEN_Pos (17U) |
| #define | RCC_APB1SMENR1_USART2SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART2SMEN_Pos) |
| #define | RCC_APB1SMENR1_USART2SMEN RCC_APB1SMENR1_USART2SMEN_Msk |
| #define | RCC_APB1SMENR1_USART3SMEN_Pos (18U) |
| #define | RCC_APB1SMENR1_USART3SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART3SMEN_Pos) |
| #define | RCC_APB1SMENR1_USART3SMEN RCC_APB1SMENR1_USART3SMEN_Msk |
| #define | RCC_APB1SMENR1_UART4SMEN_Pos (19U) |
| #define | RCC_APB1SMENR1_UART4SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART4SMEN_Pos) |
| #define | RCC_APB1SMENR1_UART4SMEN RCC_APB1SMENR1_UART4SMEN_Msk |
| #define | RCC_APB1SMENR1_UART5SMEN_Pos (20U) |
| #define | RCC_APB1SMENR1_UART5SMEN_Msk (0x1UL << RCC_APB1SMENR1_UART5SMEN_Pos) |
| #define | RCC_APB1SMENR1_UART5SMEN RCC_APB1SMENR1_UART5SMEN_Msk |
| #define | RCC_APB1SMENR1_I2C1SMEN_Pos (21U) |
| #define | RCC_APB1SMENR1_I2C1SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C1SMEN_Pos) |
| #define | RCC_APB1SMENR1_I2C1SMEN RCC_APB1SMENR1_I2C1SMEN_Msk |
| #define | RCC_APB1SMENR1_I2C2SMEN_Pos (22U) |
| #define | RCC_APB1SMENR1_I2C2SMEN_Msk (0x1UL << RCC_APB1SMENR1_I2C2SMEN_Pos) |
| #define | RCC_APB1SMENR1_I2C2SMEN RCC_APB1SMENR1_I2C2SMEN_Msk |
| #define | RCC_APB1SMENR1_CRSSMEN_Pos (24U) |
| #define | RCC_APB1SMENR1_CRSSMEN_Msk (0x1UL << RCC_APB1SMENR1_CRSSMEN_Pos) |
| #define | RCC_APB1SMENR1_CRSSMEN RCC_APB1SMENR1_CRSSMEN_Msk |
| #define | RCC_APB1SMENR1_USART6SMEN_Pos (25U) |
| #define | RCC_APB1SMENR1_USART6SMEN_Msk (0x1UL << RCC_APB1SMENR1_USART6SMEN_Pos) |
| #define | RCC_APB1SMENR1_USART6SMEN RCC_APB1SMENR1_USART6SMEN_Msk |
| #define | RCC_APB1SMENR2_I2C4SMEN_Pos (1U) |
| #define | RCC_APB1SMENR2_I2C4SMEN_Msk (0x1UL << RCC_APB1SMENR2_I2C4SMEN_Pos) |
| #define | RCC_APB1SMENR2_I2C4SMEN RCC_APB1SMENR2_I2C4SMEN_Msk |
| #define | RCC_APB1SMENR2_LPTIM2SMEN_Pos (5U) |
| #define | RCC_APB1SMENR2_LPTIM2SMEN_Msk (0x1UL << RCC_APB1SMENR2_LPTIM2SMEN_Pos) |
| #define | RCC_APB1SMENR2_LPTIM2SMEN RCC_APB1SMENR2_LPTIM2SMEN_Msk |
| #define | RCC_APB1SMENR2_I2C5SMEN_Pos (6U) |
| #define | RCC_APB1SMENR2_I2C5SMEN_Msk (0x1UL << RCC_APB1SMENR2_I2C5SMEN_Pos) |
| #define | RCC_APB1SMENR2_I2C5SMEN RCC_APB1SMENR2_I2C5SMEN_Msk |
| #define | RCC_APB1SMENR2_I2C6SMEN_Pos (7U) |
| #define | RCC_APB1SMENR2_I2C6SMEN_Msk (0x1UL << RCC_APB1SMENR2_I2C6SMEN_Pos) |
| #define | RCC_APB1SMENR2_I2C6SMEN RCC_APB1SMENR2_I2C6SMEN_Msk |
| #define | RCC_APB1SMENR2_FDCAN1SMEN_Pos (9U) |
| #define | RCC_APB1SMENR2_FDCAN1SMEN_Msk (0x1UL << RCC_APB1SMENR2_FDCAN1SMEN_Pos) |
| #define | RCC_APB1SMENR2_FDCAN1SMEN RCC_APB1SMENR2_FDCAN1SMEN_Msk |
| #define | RCC_APB1SMENR2_UCPD1SMEN_Pos (23U) |
| #define | RCC_APB1SMENR2_UCPD1SMEN_Msk (0x1UL << RCC_APB1SMENR2_UCPD1SMEN_Pos) |
| #define | RCC_APB1SMENR2_UCPD1SMEN RCC_APB1SMENR2_UCPD1SMEN_Msk |
| #define | RCC_APB2SMENR_TIM1SMEN_Pos (11U) |
| #define | RCC_APB2SMENR_TIM1SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM1SMEN_Pos) |
| #define | RCC_APB2SMENR_TIM1SMEN RCC_APB2SMENR_TIM1SMEN_Msk |
| #define | RCC_APB2SMENR_SPI1SMEN_Pos (12U) |
| #define | RCC_APB2SMENR_SPI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SPI1SMEN_Pos) |
| #define | RCC_APB2SMENR_SPI1SMEN RCC_APB2SMENR_SPI1SMEN_Msk |
| #define | RCC_APB2SMENR_TIM8SMEN_Pos (13U) |
| #define | RCC_APB2SMENR_TIM8SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM8SMEN_Pos) |
| #define | RCC_APB2SMENR_TIM8SMEN RCC_APB2SMENR_TIM8SMEN_Msk |
| #define | RCC_APB2SMENR_USART1SMEN_Pos (14U) |
| #define | RCC_APB2SMENR_USART1SMEN_Msk (0x1UL << RCC_APB2SMENR_USART1SMEN_Pos) |
| #define | RCC_APB2SMENR_USART1SMEN RCC_APB2SMENR_USART1SMEN_Msk |
| #define | RCC_APB2SMENR_TIM15SMEN_Pos (16U) |
| #define | RCC_APB2SMENR_TIM15SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM15SMEN_Pos) |
| #define | RCC_APB2SMENR_TIM15SMEN RCC_APB2SMENR_TIM15SMEN_Msk |
| #define | RCC_APB2SMENR_TIM16SMEN_Pos (17U) |
| #define | RCC_APB2SMENR_TIM16SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM16SMEN_Pos) |
| #define | RCC_APB2SMENR_TIM16SMEN RCC_APB2SMENR_TIM16SMEN_Msk |
| #define | RCC_APB2SMENR_TIM17SMEN_Pos (18U) |
| #define | RCC_APB2SMENR_TIM17SMEN_Msk (0x1UL << RCC_APB2SMENR_TIM17SMEN_Pos) |
| #define | RCC_APB2SMENR_TIM17SMEN RCC_APB2SMENR_TIM17SMEN_Msk |
| #define | RCC_APB2SMENR_SAI1SMEN_Pos (21U) |
| #define | RCC_APB2SMENR_SAI1SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI1SMEN_Pos) |
| #define | RCC_APB2SMENR_SAI1SMEN RCC_APB2SMENR_SAI1SMEN_Msk |
| #define | RCC_APB2SMENR_SAI2SMEN_Pos (22U) |
| #define | RCC_APB2SMENR_SAI2SMEN_Msk (0x1UL << RCC_APB2SMENR_SAI2SMEN_Pos) |
| #define | RCC_APB2SMENR_SAI2SMEN RCC_APB2SMENR_SAI2SMEN_Msk |
| #define | RCC_APB2SMENR_GFXTIMSMEN_Pos (25U) |
| #define | RCC_APB2SMENR_GFXTIMSMEN_Msk (0x1UL << RCC_APB2SMENR_GFXTIMSMEN_Pos) |
| #define | RCC_APB2SMENR_GFXTIMSMEN RCC_APB2SMENR_GFXTIMSMEN_Msk |
| #define | RCC_APB2SMENR_LTDCSMEN_Pos (26U) |
| #define | RCC_APB2SMENR_LTDCSMEN_Msk (0x1UL << RCC_APB2SMENR_LTDCSMEN_Pos) |
| #define | RCC_APB2SMENR_LTDCSMEN RCC_APB2SMENR_LTDCSMEN_Msk |
| #define | RCC_APB2SMENR_DSIHOSTSMEN_Pos (27U) |
| #define | RCC_APB2SMENR_DSIHOSTSMEN_Msk (0x1UL << RCC_APB2SMENR_DSIHOSTSMEN_Pos) |
| #define | RCC_APB2SMENR_DSIHOSTSMEN RCC_APB2SMENR_DSIHOSTSMEN_Msk |
| #define | RCC_APB3SMENR_SYSCFGSMEN_Pos (1U) |
| #define | RCC_APB3SMENR_SYSCFGSMEN_Msk (0x1UL << RCC_APB3SMENR_SYSCFGSMEN_Pos) |
| #define | RCC_APB3SMENR_SYSCFGSMEN RCC_APB3SMENR_SYSCFGSMEN_Msk |
| #define | RCC_APB3SMENR_SPI3SMEN_Pos (5U) |
| #define | RCC_APB3SMENR_SPI3SMEN_Msk (0x1UL << RCC_APB3SMENR_SPI3SMEN_Pos) |
| #define | RCC_APB3SMENR_SPI3SMEN RCC_APB3SMENR_SPI3SMEN_Msk |
| #define | RCC_APB3SMENR_LPUART1SMEN_Pos (6U) |
| #define | RCC_APB3SMENR_LPUART1SMEN_Msk (0x1UL << RCC_APB3SMENR_LPUART1SMEN_Pos) |
| #define | RCC_APB3SMENR_LPUART1SMEN RCC_APB3SMENR_LPUART1SMEN_Msk |
| #define | RCC_APB3SMENR_I2C3SMEN_Pos (7U) |
| #define | RCC_APB3SMENR_I2C3SMEN_Msk (0x1UL << RCC_APB3SMENR_I2C3SMEN_Pos) |
| #define | RCC_APB3SMENR_I2C3SMEN RCC_APB3SMENR_I2C3SMEN_Msk |
| #define | RCC_APB3SMENR_LPTIM1SMEN_Pos (11U) |
| #define | RCC_APB3SMENR_LPTIM1SMEN_Msk (0x1UL << RCC_APB3SMENR_LPTIM1SMEN_Pos) |
| #define | RCC_APB3SMENR_LPTIM1SMEN RCC_APB3SMENR_LPTIM1SMEN_Msk |
| #define | RCC_APB3SMENR_LPTIM3SMEN_Pos (12U) |
| #define | RCC_APB3SMENR_LPTIM3SMEN_Msk (0x1UL << RCC_APB3SMENR_LPTIM3SMEN_Pos) |
| #define | RCC_APB3SMENR_LPTIM3SMEN RCC_APB3SMENR_LPTIM3SMEN_Msk |
| #define | RCC_APB3SMENR_LPTIM4SMEN_Pos (13U) |
| #define | RCC_APB3SMENR_LPTIM4SMEN_Msk (0x1UL << RCC_APB3SMENR_LPTIM4SMEN_Pos) |
| #define | RCC_APB3SMENR_LPTIM4SMEN RCC_APB3SMENR_LPTIM4SMEN_Msk |
| #define | RCC_APB3SMENR_OPAMPSMEN_Pos (14U) |
| #define | RCC_APB3SMENR_OPAMPSMEN_Msk (0x1UL << RCC_APB3SMENR_OPAMPSMEN_Pos) |
| #define | RCC_APB3SMENR_OPAMPSMEN RCC_APB3SMENR_OPAMPSMEN_Msk |
| #define | RCC_APB3SMENR_COMPSMEN_Pos (15U) |
| #define | RCC_APB3SMENR_COMPSMEN_Msk (0x1UL << RCC_APB3SMENR_COMPSMEN_Pos) |
| #define | RCC_APB3SMENR_COMPSMEN RCC_APB3SMENR_COMPSMEN_Msk |
| #define | RCC_APB3SMENR_VREFSMEN_Pos (20U) |
| #define | RCC_APB3SMENR_VREFSMEN_Msk (0x1UL << RCC_APB3SMENR_VREFSMEN_Pos) |
| #define | RCC_APB3SMENR_VREFSMEN RCC_APB3SMENR_VREFSMEN_Msk |
| #define | RCC_APB3SMENR_RTCAPBSMEN_Pos (21U) |
| #define | RCC_APB3SMENR_RTCAPBSMEN_Msk (0x1UL << RCC_APB3SMENR_RTCAPBSMEN_Pos) |
| #define | RCC_APB3SMENR_RTCAPBSMEN RCC_APB3SMENR_RTCAPBSMEN_Msk |
| #define | RCC_SRDAMR_SPI3AMEN_Pos (5U) |
| #define | RCC_SRDAMR_SPI3AMEN_Msk (0x1UL << RCC_SRDAMR_SPI3AMEN_Pos) |
| #define | RCC_SRDAMR_SPI3AMEN RCC_SRDAMR_SPI3AMEN_Msk |
| #define | RCC_SRDAMR_LPUART1AMEN_Pos (6U) |
| #define | RCC_SRDAMR_LPUART1AMEN_Msk (0x1UL << RCC_SRDAMR_LPUART1AMEN_Pos) |
| #define | RCC_SRDAMR_LPUART1AMEN RCC_SRDAMR_LPUART1AMEN_Msk |
| #define | RCC_SRDAMR_I2C3AMEN_Pos (7U) |
| #define | RCC_SRDAMR_I2C3AMEN_Msk (0x1UL << RCC_SRDAMR_I2C3AMEN_Pos) |
| #define | RCC_SRDAMR_I2C3AMEN RCC_SRDAMR_I2C3AMEN_Msk |
| #define | RCC_SRDAMR_LPTIM1AMEN_Pos (11U) |
| #define | RCC_SRDAMR_LPTIM1AMEN_Msk (0x1UL << RCC_SRDAMR_LPTIM1AMEN_Pos) |
| #define | RCC_SRDAMR_LPTIM1AMEN RCC_SRDAMR_LPTIM1AMEN_Msk |
| #define | RCC_SRDAMR_LPTIM3AMEN_Pos (12U) |
| #define | RCC_SRDAMR_LPTIM3AMEN_Msk (0x1UL << RCC_SRDAMR_LPTIM3AMEN_Pos) |
| #define | RCC_SRDAMR_LPTIM3AMEN RCC_SRDAMR_LPTIM3AMEN_Msk |
| #define | RCC_SRDAMR_LPTIM4AMEN_Pos (13U) |
| #define | RCC_SRDAMR_LPTIM4AMEN_Msk (0x1UL << RCC_SRDAMR_LPTIM4AMEN_Pos) |
| #define | RCC_SRDAMR_LPTIM4AMEN RCC_SRDAMR_LPTIM4AMEN_Msk |
| #define | RCC_SRDAMR_OPAMPAMEN_Pos (14U) |
| #define | RCC_SRDAMR_OPAMPAMEN_Msk (0x1UL << RCC_SRDAMR_OPAMPAMEN_Pos) |
| #define | RCC_SRDAMR_OPAMPAMEN RCC_SRDAMR_OPAMPAMEN_Msk |
| #define | RCC_SRDAMR_COMPAMEN_Pos (15U) |
| #define | RCC_SRDAMR_COMPAMEN_Msk (0x1UL << RCC_SRDAMR_COMPAMEN_Pos) |
| #define | RCC_SRDAMR_COMPAMEN RCC_SRDAMR_COMPAMEN_Msk |
| #define | RCC_SRDAMR_VREFAMEN_Pos (20U) |
| #define | RCC_SRDAMR_VREFAMEN_Msk (0x1UL << RCC_SRDAMR_VREFAMEN_Pos) |
| #define | RCC_SRDAMR_VREFAMEN RCC_SRDAMR_VREFAMEN_Msk |
| #define | RCC_SRDAMR_RTCAPBAMEN_Pos (21U) |
| #define | RCC_SRDAMR_RTCAPBAMEN_Msk (0x1UL << RCC_SRDAMR_RTCAPBAMEN_Pos) |
| #define | RCC_SRDAMR_RTCAPBAMEN RCC_SRDAMR_RTCAPBAMEN_Msk |
| #define | RCC_SRDAMR_ADC4AMEN_Pos (25U) |
| #define | RCC_SRDAMR_ADC4AMEN_Msk (0x1UL << RCC_SRDAMR_ADC4AMEN_Pos) |
| #define | RCC_SRDAMR_ADC4AMEN RCC_SRDAMR_ADC4AMEN_Msk |
| #define | RCC_SRDAMR_LPGPIO1AMEN_Pos (26U) |
| #define | RCC_SRDAMR_LPGPIO1AMEN_Msk (0x1UL << RCC_SRDAMR_LPGPIO1AMEN_Pos) |
| #define | RCC_SRDAMR_LPGPIO1AMEN RCC_SRDAMR_LPGPIO1AMEN_Msk |
| #define | RCC_SRDAMR_DAC1AMEN_Pos (27U) |
| #define | RCC_SRDAMR_DAC1AMEN_Msk (0x1UL << RCC_SRDAMR_DAC1AMEN_Pos) |
| #define | RCC_SRDAMR_DAC1AMEN RCC_SRDAMR_DAC1AMEN_Msk |
| #define | RCC_SRDAMR_LPDMA1AMEN_Pos (28U) |
| #define | RCC_SRDAMR_LPDMA1AMEN_Msk (0x1UL << RCC_SRDAMR_LPDMA1AMEN_Pos) |
| #define | RCC_SRDAMR_LPDMA1AMEN RCC_SRDAMR_LPDMA1AMEN_Msk |
| #define | RCC_SRDAMR_ADF1AMEN_Pos (29U) |
| #define | RCC_SRDAMR_ADF1AMEN_Msk (0x1UL << RCC_SRDAMR_ADF1AMEN_Pos) |
| #define | RCC_SRDAMR_ADF1AMEN RCC_SRDAMR_ADF1AMEN_Msk |
| #define | RCC_SRDAMR_SRAM4AMEN_Pos (31U) |
| #define | RCC_SRDAMR_SRAM4AMEN_Msk (0x1UL << RCC_SRDAMR_SRAM4AMEN_Pos) |
| #define | RCC_SRDAMR_SRAM4AMEN RCC_SRDAMR_SRAM4AMEN_Msk |
| #define | RCC_CCIPR1_USART1SEL_Pos (0U) |
| #define | RCC_CCIPR1_USART1SEL_Msk (0x3UL << RCC_CCIPR1_USART1SEL_Pos) |
| #define | RCC_CCIPR1_USART1SEL RCC_CCIPR1_USART1SEL_Msk |
| #define | RCC_CCIPR1_USART1SEL_0 (0x1UL << RCC_CCIPR1_USART1SEL_Pos) |
| #define | RCC_CCIPR1_USART1SEL_1 (0x2UL << RCC_CCIPR1_USART1SEL_Pos) |
| #define | RCC_CCIPR1_USART2SEL_Pos (2U) |
| #define | RCC_CCIPR1_USART2SEL_Msk (0x3UL << RCC_CCIPR1_USART2SEL_Pos) |
| #define | RCC_CCIPR1_USART2SEL RCC_CCIPR1_USART2SEL_Msk |
| #define | RCC_CCIPR1_USART2SEL_0 (0x1UL << RCC_CCIPR1_USART2SEL_Pos) |
| #define | RCC_CCIPR1_USART2SEL_1 (0x2UL << RCC_CCIPR1_USART2SEL_Pos) |
| #define | RCC_CCIPR1_USART3SEL_Pos (4U) |
| #define | RCC_CCIPR1_USART3SEL_Msk (0x3UL << RCC_CCIPR1_USART3SEL_Pos) |
| #define | RCC_CCIPR1_USART3SEL RCC_CCIPR1_USART3SEL_Msk |
| #define | RCC_CCIPR1_USART3SEL_0 (0x1UL << RCC_CCIPR1_USART3SEL_Pos) |
| #define | RCC_CCIPR1_USART3SEL_1 (0x2UL << RCC_CCIPR1_USART3SEL_Pos) |
| #define | RCC_CCIPR1_UART4SEL_Pos (6U) |
| #define | RCC_CCIPR1_UART4SEL_Msk (0x3UL << RCC_CCIPR1_UART4SEL_Pos) |
| #define | RCC_CCIPR1_UART4SEL RCC_CCIPR1_UART4SEL_Msk |
| #define | RCC_CCIPR1_UART4SEL_0 (0x1UL << RCC_CCIPR1_UART4SEL_Pos) |
| #define | RCC_CCIPR1_UART4SEL_1 (0x2UL << RCC_CCIPR1_UART4SEL_Pos) |
| #define | RCC_CCIPR1_UART5SEL_Pos (8U) |
| #define | RCC_CCIPR1_UART5SEL_Msk (0x3UL << RCC_CCIPR1_UART5SEL_Pos) |
| #define | RCC_CCIPR1_UART5SEL RCC_CCIPR1_UART5SEL_Msk |
| #define | RCC_CCIPR1_UART5SEL_0 (0x1UL << RCC_CCIPR1_UART5SEL_Pos) |
| #define | RCC_CCIPR1_UART5SEL_1 (0x2UL << RCC_CCIPR1_UART5SEL_Pos) |
| #define | RCC_CCIPR1_I2C1SEL_Pos (10U) |
| #define | RCC_CCIPR1_I2C1SEL_Msk (0x3UL << RCC_CCIPR1_I2C1SEL_Pos) |
| #define | RCC_CCIPR1_I2C1SEL RCC_CCIPR1_I2C1SEL_Msk |
| #define | RCC_CCIPR1_I2C1SEL_0 (0x1UL << RCC_CCIPR1_I2C1SEL_Pos) |
| #define | RCC_CCIPR1_I2C1SEL_1 (0x2UL << RCC_CCIPR1_I2C1SEL_Pos) |
| #define | RCC_CCIPR1_I2C2SEL_Pos (12U) |
| #define | RCC_CCIPR1_I2C2SEL_Msk (0x3UL << RCC_CCIPR1_I2C2SEL_Pos) |
| #define | RCC_CCIPR1_I2C2SEL RCC_CCIPR1_I2C2SEL_Msk |
| #define | RCC_CCIPR1_I2C2SEL_0 (0x1UL << RCC_CCIPR1_I2C2SEL_Pos) |
| #define | RCC_CCIPR1_I2C2SEL_1 (0x2UL << RCC_CCIPR1_I2C2SEL_Pos) |
| #define | RCC_CCIPR1_I2C4SEL_Pos (14U) |
| #define | RCC_CCIPR1_I2C4SEL_Msk (0x3UL << RCC_CCIPR1_I2C4SEL_Pos) |
| #define | RCC_CCIPR1_I2C4SEL RCC_CCIPR1_I2C4SEL_Msk |
| #define | RCC_CCIPR1_I2C4SEL_0 (0x1UL << RCC_CCIPR1_I2C4SEL_Pos) |
| #define | RCC_CCIPR1_I2C4SEL_1 (0x2UL << RCC_CCIPR1_I2C4SEL_Pos) |
| #define | RCC_CCIPR1_SPI2SEL_Pos (16U) |
| #define | RCC_CCIPR1_SPI2SEL_Msk (0x3UL << RCC_CCIPR1_SPI2SEL_Pos) |
| #define | RCC_CCIPR1_SPI2SEL RCC_CCIPR1_SPI2SEL_Msk |
| #define | RCC_CCIPR1_SPI2SEL_0 (0x1UL << RCC_CCIPR1_SPI2SEL_Pos) |
| #define | RCC_CCIPR1_SPI2SEL_1 (0x2UL << RCC_CCIPR1_SPI2SEL_Pos) |
| #define | RCC_CCIPR1_LPTIM2SEL_Pos (18U) |
| #define | RCC_CCIPR1_LPTIM2SEL_Msk (0x3UL << RCC_CCIPR1_LPTIM2SEL_Pos) |
| #define | RCC_CCIPR1_LPTIM2SEL RCC_CCIPR1_LPTIM2SEL_Msk |
| #define | RCC_CCIPR1_LPTIM2SEL_0 (0x1UL << RCC_CCIPR1_LPTIM2SEL_Pos) |
| #define | RCC_CCIPR1_LPTIM2SEL_1 (0x2UL << RCC_CCIPR1_LPTIM2SEL_Pos) |
| #define | RCC_CCIPR1_SPI1SEL_Pos (20U) |
| #define | RCC_CCIPR1_SPI1SEL_Msk (0x3UL << RCC_CCIPR1_SPI1SEL_Pos) |
| #define | RCC_CCIPR1_SPI1SEL RCC_CCIPR1_SPI1SEL_Msk |
| #define | RCC_CCIPR1_SPI1SEL_0 (0x1UL << RCC_CCIPR1_SPI1SEL_Pos) |
| #define | RCC_CCIPR1_SPI1SEL_1 (0x2UL << RCC_CCIPR1_SPI1SEL_Pos) |
| #define | RCC_CCIPR1_SYSTICKSEL_Pos (22U) |
| #define | RCC_CCIPR1_SYSTICKSEL_Msk (0x3UL << RCC_CCIPR1_SYSTICKSEL_Pos) |
| #define | RCC_CCIPR1_SYSTICKSEL RCC_CCIPR1_SYSTICKSEL_Msk |
| #define | RCC_CCIPR1_SYSTICKSEL_0 (0x1UL << RCC_CCIPR1_SYSTICKSEL_Pos) |
| #define | RCC_CCIPR1_SYSTICKSEL_1 (0x2UL << RCC_CCIPR1_SYSTICKSEL_Pos) |
| #define | RCC_CCIPR1_FDCANSEL_Pos (24U) |
| #define | RCC_CCIPR1_FDCANSEL_Msk (0x3UL << RCC_CCIPR1_FDCANSEL_Pos) |
| #define | RCC_CCIPR1_FDCANSEL RCC_CCIPR1_FDCANSEL_Msk |
| #define | RCC_CCIPR1_FDCANSEL_0 (0x1UL << RCC_CCIPR1_FDCANSEL_Pos) |
| #define | RCC_CCIPR1_FDCANSEL_1 (0x2UL << RCC_CCIPR1_FDCANSEL_Pos) |
| #define | RCC_CCIPR1_ICLKSEL_Pos (26U) |
| #define | RCC_CCIPR1_ICLKSEL_Msk (0x3UL << RCC_CCIPR1_ICLKSEL_Pos) |
| #define | RCC_CCIPR1_ICLKSEL RCC_CCIPR1_ICLKSEL_Msk |
| #define | RCC_CCIPR1_ICLKSEL_0 (0x1UL << RCC_CCIPR1_ICLKSEL_Pos) |
| #define | RCC_CCIPR1_ICLKSEL_1 (0x2UL << RCC_CCIPR1_ICLKSEL_Pos) |
| #define | RCC_CCIPR1_TIMICSEL_Pos (29U) |
| #define | RCC_CCIPR1_TIMICSEL_Msk (0x7UL << RCC_CCIPR1_TIMICSEL_Pos) |
| #define | RCC_CCIPR1_TIMICSEL RCC_CCIPR1_TIMICSEL_Msk |
| #define | RCC_CCIPR1_TIMICSEL_0 (0x1UL << RCC_CCIPR1_TIMICSEL_Pos) |
| #define | RCC_CCIPR1_TIMICSEL_1 (0x2UL << RCC_CCIPR1_TIMICSEL_Pos) |
| #define | RCC_CCIPR1_TIMICSEL_2 (0x4UL << RCC_CCIPR1_TIMICSEL_Pos) |
| #define | RCC_CCIPR2_MDF1SEL_Pos (0U) |
| #define | RCC_CCIPR2_MDF1SEL_Msk (0x7UL << RCC_CCIPR2_MDF1SEL_Pos) |
| #define | RCC_CCIPR2_MDF1SEL RCC_CCIPR2_MDF1SEL_Msk |
| #define | RCC_CCIPR2_MDF1SEL_0 (0x1UL << RCC_CCIPR2_MDF1SEL_Pos) |
| #define | RCC_CCIPR2_MDF1SEL_1 (0x2UL << RCC_CCIPR2_MDF1SEL_Pos) |
| #define | RCC_CCIPR2_MDF1SEL_2 (0x4UL << RCC_CCIPR2_MDF1SEL_Pos) |
| #define | RCC_CCIPR2_SAI1SEL_Pos (5U) |
| #define | RCC_CCIPR2_SAI1SEL_Msk (0x7UL << RCC_CCIPR2_SAI1SEL_Pos) |
| #define | RCC_CCIPR2_SAI1SEL RCC_CCIPR2_SAI1SEL_Msk |
| #define | RCC_CCIPR2_SAI1SEL_0 (0x1UL << RCC_CCIPR2_SAI1SEL_Pos) |
| #define | RCC_CCIPR2_SAI1SEL_1 (0x2UL << RCC_CCIPR2_SAI1SEL_Pos) |
| #define | RCC_CCIPR2_SAI1SEL_2 (0x4UL << RCC_CCIPR2_SAI1SEL_Pos) |
| #define | RCC_CCIPR2_SAI2SEL_Pos (8U) |
| #define | RCC_CCIPR2_SAI2SEL_Msk (0x7UL << RCC_CCIPR2_SAI2SEL_Pos) |
| #define | RCC_CCIPR2_SAI2SEL RCC_CCIPR2_SAI2SEL_Msk |
| #define | RCC_CCIPR2_SAI2SEL_0 (0x1UL << RCC_CCIPR2_SAI2SEL_Pos) |
| #define | RCC_CCIPR2_SAI2SEL_1 (0x2UL << RCC_CCIPR2_SAI2SEL_Pos) |
| #define | RCC_CCIPR2_SAI2SEL_2 (0x4UL << RCC_CCIPR2_SAI2SEL_Pos) |
| #define | RCC_CCIPR2_SAESSEL_Pos (11U) |
| #define | RCC_CCIPR2_SAESSEL_Msk (0x1UL << RCC_CCIPR2_SAESSEL_Pos) |
| #define | RCC_CCIPR2_SAESSEL RCC_CCIPR2_SAESSEL_Msk |
| #define | RCC_CCIPR2_RNGSEL_Pos (12U) |
| #define | RCC_CCIPR2_RNGSEL_Msk (0x3UL << RCC_CCIPR2_RNGSEL_Pos) |
| #define | RCC_CCIPR2_RNGSEL RCC_CCIPR2_RNGSEL_Msk |
| #define | RCC_CCIPR2_RNGSEL_0 (0x1UL << RCC_CCIPR2_RNGSEL_Pos) |
| #define | RCC_CCIPR2_RNGSEL_1 (0x2UL << RCC_CCIPR2_RNGSEL_Pos) |
| #define | RCC_CCIPR2_SDMMCSEL_Pos (14U) |
| #define | RCC_CCIPR2_SDMMCSEL_Msk (0x1UL << RCC_CCIPR2_SDMMCSEL_Pos) |
| #define | RCC_CCIPR2_SDMMCSEL RCC_CCIPR2_SDMMCSEL_Msk |
| #define | RCC_CCIPR2_DSIHOSTSEL_Pos (15U) |
| #define | RCC_CCIPR2_DSIHOSTSEL_Msk (0x1UL << RCC_CCIPR2_DSIHOSTSEL_Pos) |
| #define | RCC_CCIPR2_DSIHOSTSEL RCC_CCIPR2_DSIHOSTSEL_Msk |
| #define | RCC_CCIPR2_USART6SEL_Pos (16U) |
| #define | RCC_CCIPR2_USART6SEL_Msk (0x3UL << RCC_CCIPR2_USART6SEL_Pos) |
| #define | RCC_CCIPR2_USART6SEL RCC_CCIPR2_USART6SEL_Msk |
| #define | RCC_CCIPR2_USART6SEL_0 (0x1UL << RCC_CCIPR2_USART6SEL_Pos) |
| #define | RCC_CCIPR2_USART6SEL_1 (0x2UL << RCC_CCIPR2_USART6SEL_Pos) |
| #define | RCC_CCIPR2_LTDCSEL_Pos (18U) |
| #define | RCC_CCIPR2_LTDCSEL_Msk (0x1UL << RCC_CCIPR2_LTDCSEL_Pos) |
| #define | RCC_CCIPR2_LTDCSEL RCC_CCIPR2_LTDCSEL_Msk |
| #define | RCC_CCIPR2_OCTOSPISEL_Pos (20U) |
| #define | RCC_CCIPR2_OCTOSPISEL_Msk (0x3UL << RCC_CCIPR2_OCTOSPISEL_Pos) |
| #define | RCC_CCIPR2_OCTOSPISEL RCC_CCIPR2_OCTOSPISEL_Msk |
| #define | RCC_CCIPR2_OCTOSPISEL_0 (0x1UL << RCC_CCIPR2_OCTOSPISEL_Pos) |
| #define | RCC_CCIPR2_OCTOSPISEL_1 (0x2UL << RCC_CCIPR2_OCTOSPISEL_Pos) |
| #define | RCC_CCIPR2_HSPISEL_Pos (22U) |
| #define | RCC_CCIPR2_HSPISEL_Msk (0x3UL << RCC_CCIPR2_HSPISEL_Pos) |
| #define | RCC_CCIPR2_HSPISEL RCC_CCIPR2_HSPISEL_Msk |
| #define | RCC_CCIPR2_HSPISEL_0 (0x1UL << RCC_CCIPR2_HSPISEL_Pos) |
| #define | RCC_CCIPR2_HSPISEL_1 (0x2UL << RCC_CCIPR2_HSPISEL_Pos) |
| #define | RCC_CCIPR2_I2C5SEL_Pos (24U) |
| #define | RCC_CCIPR2_I2C5SEL_Msk (0x3UL << RCC_CCIPR2_I2C5SEL_Pos) |
| #define | RCC_CCIPR2_I2C5SEL RCC_CCIPR2_I2C5SEL_Msk |
| #define | RCC_CCIPR2_I2C5SEL_0 (0x1UL << RCC_CCIPR2_I2C5SEL_Pos) |
| #define | RCC_CCIPR2_I2C5SEL_1 (0x2UL << RCC_CCIPR2_I2C5SEL_Pos) |
| #define | RCC_CCIPR2_I2C6SEL_Pos (26U) |
| #define | RCC_CCIPR2_I2C6SEL_Msk (0x3UL << RCC_CCIPR2_I2C6SEL_Pos) |
| #define | RCC_CCIPR2_I2C6SEL RCC_CCIPR2_I2C6SEL_Msk |
| #define | RCC_CCIPR2_I2C6SEL_0 (0x1UL << RCC_CCIPR2_I2C6SEL_Pos) |
| #define | RCC_CCIPR2_I2C6SEL_1 (0x2UL << RCC_CCIPR2_I2C6SEL_Pos) |
| #define | RCC_CCIPR2_USBPHYCSEL_Pos (30U) |
| #define | RCC_CCIPR2_USBPHYCSEL_Msk (0x3UL << RCC_CCIPR2_USBPHYCSEL_Pos) |
| #define | RCC_CCIPR2_USBPHYCSEL RCC_CCIPR2_USBPHYCSEL_Msk |
| #define | RCC_CCIPR2_USBPHYCSEL_0 (0x1UL << RCC_CCIPR2_USBPHYCSEL_Pos) |
| #define | RCC_CCIPR2_USBPHYCSEL_1 (0x2UL << RCC_CCIPR2_USBPHYCSEL_Pos) |
| #define | RCC_CCIPR3_LPUART1SEL_Pos (0U) |
| #define | RCC_CCIPR3_LPUART1SEL_Msk (0x7UL << RCC_CCIPR3_LPUART1SEL_Pos) |
| #define | RCC_CCIPR3_LPUART1SEL RCC_CCIPR3_LPUART1SEL_Msk |
| #define | RCC_CCIPR3_LPUART1SEL_0 (0x1UL << RCC_CCIPR3_LPUART1SEL_Pos) |
| #define | RCC_CCIPR3_LPUART1SEL_1 (0x2UL << RCC_CCIPR3_LPUART1SEL_Pos) |
| #define | RCC_CCIPR3_LPUART1SEL_2 (0x4UL << RCC_CCIPR3_LPUART1SEL_Pos) |
| #define | RCC_CCIPR3_SPI3SEL_Pos (3U) |
| #define | RCC_CCIPR3_SPI3SEL_Msk (0x3UL << RCC_CCIPR3_SPI3SEL_Pos) |
| #define | RCC_CCIPR3_SPI3SEL RCC_CCIPR3_SPI3SEL_Msk |
| #define | RCC_CCIPR3_SPI3SEL_0 (0x1UL << RCC_CCIPR3_SPI3SEL_Pos) |
| #define | RCC_CCIPR3_SPI3SEL_1 (0x2UL << RCC_CCIPR3_SPI3SEL_Pos) |
| #define | RCC_CCIPR3_I2C3SEL_Pos (6U) |
| #define | RCC_CCIPR3_I2C3SEL_Msk (0x3UL << RCC_CCIPR3_I2C3SEL_Pos) |
| #define | RCC_CCIPR3_I2C3SEL RCC_CCIPR3_I2C3SEL_Msk |
| #define | RCC_CCIPR3_I2C3SEL_0 (0x1UL << RCC_CCIPR3_I2C3SEL_Pos) |
| #define | RCC_CCIPR3_I2C3SEL_1 (0x2UL << RCC_CCIPR3_I2C3SEL_Pos) |
| #define | RCC_CCIPR3_LPTIM34SEL_Pos (8U) |
| #define | RCC_CCIPR3_LPTIM34SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM34SEL_Pos) |
| #define | RCC_CCIPR3_LPTIM34SEL RCC_CCIPR3_LPTIM34SEL_Msk |
| #define | RCC_CCIPR3_LPTIM34SEL_0 (0x1UL << RCC_CCIPR3_LPTIM34SEL_Pos) |
| #define | RCC_CCIPR3_LPTIM34SEL_1 (0x2UL << RCC_CCIPR3_LPTIM34SEL_Pos) |
| #define | RCC_CCIPR3_LPTIM1SEL_Pos (10U) |
| #define | RCC_CCIPR3_LPTIM1SEL_Msk (0x3UL << RCC_CCIPR3_LPTIM1SEL_Pos) |
| #define | RCC_CCIPR3_LPTIM1SEL RCC_CCIPR3_LPTIM1SEL_Msk |
| #define | RCC_CCIPR3_LPTIM1SEL_0 (0x1UL << RCC_CCIPR3_LPTIM1SEL_Pos) |
| #define | RCC_CCIPR3_LPTIM1SEL_1 (0x2UL << RCC_CCIPR3_LPTIM1SEL_Pos) |
| #define | RCC_CCIPR3_ADCDACSEL_Pos (12U) |
| #define | RCC_CCIPR3_ADCDACSEL_Msk (0x7UL << RCC_CCIPR3_ADCDACSEL_Pos) |
| #define | RCC_CCIPR3_ADCDACSEL RCC_CCIPR3_ADCDACSEL_Msk |
| #define | RCC_CCIPR3_ADCDACSEL_0 (0x1UL << RCC_CCIPR3_ADCDACSEL_Pos) |
| #define | RCC_CCIPR3_ADCDACSEL_1 (0x2UL << RCC_CCIPR3_ADCDACSEL_Pos) |
| #define | RCC_CCIPR3_ADCDACSEL_2 (0x4UL << RCC_CCIPR3_ADCDACSEL_Pos) |
| #define | RCC_CCIPR3_DAC1SEL_Pos (15U) |
| #define | RCC_CCIPR3_DAC1SEL_Msk (0x1UL << RCC_CCIPR3_DAC1SEL_Pos) |
| #define | RCC_CCIPR3_DAC1SEL RCC_CCIPR3_DAC1SEL_Msk |
| #define | RCC_CCIPR3_ADF1SEL_Pos (16U) |
| #define | RCC_CCIPR3_ADF1SEL_Msk (0x7UL << RCC_CCIPR3_ADF1SEL_Pos) |
| #define | RCC_CCIPR3_ADF1SEL RCC_CCIPR3_ADF1SEL_Msk |
| #define | RCC_CCIPR3_ADF1SEL_0 (0x1UL << RCC_CCIPR3_ADF1SEL_Pos) |
| #define | RCC_CCIPR3_ADF1SEL_1 (0x2UL << RCC_CCIPR3_ADF1SEL_Pos) |
| #define | RCC_CCIPR3_ADF1SEL_2 (0x4UL << RCC_CCIPR3_ADF1SEL_Pos) |
| #define | RCC_BDCR_LSEON_Pos (0U) |
| #define | RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) |
| #define | RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk |
| #define | RCC_BDCR_LSERDY_Pos (1U) |
| #define | RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) |
| #define | RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk |
| #define | RCC_BDCR_LSEBYP_Pos (2U) |
| #define | RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) |
| #define | RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk |
| #define | RCC_BDCR_LSEDRV_Pos (3U) |
| #define | RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) |
| #define | RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk |
| #define | RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) |
| #define | RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) |
| #define | RCC_BDCR_LSECSSON_Pos (5U) |
| #define | RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) |
| #define | RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk |
| #define | RCC_BDCR_LSECSSD_Pos (6U) |
| #define | RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) |
| #define | RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk |
| #define | RCC_BDCR_LSESYSEN_Pos (7U) |
| #define | RCC_BDCR_LSESYSEN_Msk (0x1UL << RCC_BDCR_LSESYSEN_Pos) |
| #define | RCC_BDCR_LSESYSEN RCC_BDCR_LSESYSEN_Msk |
| #define | RCC_BDCR_RTCSEL_Pos (8U) |
| #define | RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) |
| #define | RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk |
| #define | RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) |
| #define | RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) |
| #define | RCC_BDCR_LSESYSRDY_Pos (11U) |
| #define | RCC_BDCR_LSESYSRDY_Msk (0x1UL << RCC_BDCR_LSESYSRDY_Pos) |
| #define | RCC_BDCR_LSESYSRDY RCC_BDCR_LSESYSRDY_Msk |
| #define | RCC_BDCR_LSEGFON_Pos (12U) |
| #define | RCC_BDCR_LSEGFON_Msk (0x1UL << RCC_BDCR_LSEGFON_Pos) |
| #define | RCC_BDCR_LSEGFON RCC_BDCR_LSEGFON_Msk |
| #define | RCC_BDCR_RTCEN_Pos (15U) |
| #define | RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) |
| #define | RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk |
| #define | RCC_BDCR_BDRST_Pos (16U) |
| #define | RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) |
| #define | RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk |
| #define | RCC_BDCR_LSCOEN_Pos (24U) |
| #define | RCC_BDCR_LSCOEN_Msk (0x1UL << RCC_BDCR_LSCOEN_Pos) |
| #define | RCC_BDCR_LSCOEN RCC_BDCR_LSCOEN_Msk |
| #define | RCC_BDCR_LSCOSEL_Pos (25U) |
| #define | RCC_BDCR_LSCOSEL_Msk (0x1UL << RCC_BDCR_LSCOSEL_Pos) |
| #define | RCC_BDCR_LSCOSEL RCC_BDCR_LSCOSEL_Msk |
| #define | RCC_BDCR_LSION_Pos (26U) |
| #define | RCC_BDCR_LSION_Msk (0x1UL << RCC_BDCR_LSION_Pos) |
| #define | RCC_BDCR_LSION RCC_BDCR_LSION_Msk |
| #define | RCC_BDCR_LSIRDY_Pos (27U) |
| #define | RCC_BDCR_LSIRDY_Msk (0x1UL << RCC_BDCR_LSIRDY_Pos) |
| #define | RCC_BDCR_LSIRDY RCC_BDCR_LSIRDY_Msk |
| #define | RCC_BDCR_LSIPREDIV_Pos (28U) |
| #define | RCC_BDCR_LSIPREDIV_Msk (0x1UL << RCC_BDCR_LSIPREDIV_Pos) |
| #define | RCC_BDCR_LSIPREDIV RCC_BDCR_LSIPREDIV_Msk |
| #define | RCC_CSR_MSIKSRANGE_Pos (8U) |
| #define | RCC_CSR_MSIKSRANGE_Msk (0xFUL << RCC_CSR_MSIKSRANGE_Pos) |
| #define | RCC_CSR_MSIKSRANGE RCC_CSR_MSIKSRANGE_Msk |
| #define | RCC_CSR_MSIKSRANGE_0 (0x1UL << RCC_CSR_MSIKSRANGE_Pos) |
| #define | RCC_CSR_MSIKSRANGE_1 (0x2UL << RCC_CSR_MSIKSRANGE_Pos) |
| #define | RCC_CSR_MSIKSRANGE_2 (0x4UL << RCC_CSR_MSIKSRANGE_Pos) |
| #define | RCC_CSR_MSIKSRANGE_3 (0x8UL << RCC_CSR_MSIKSRANGE_Pos) |
| #define | RCC_CSR_MSISSRANGE_Pos (12U) |
| #define | RCC_CSR_MSISSRANGE_Msk (0xFUL << RCC_CSR_MSISSRANGE_Pos) |
| #define | RCC_CSR_MSISSRANGE RCC_CSR_MSISSRANGE_Msk |
| #define | RCC_CSR_MSISSRANGE_0 (0x1UL << RCC_CSR_MSISSRANGE_Pos) |
| #define | RCC_CSR_MSISSRANGE_1 (0x2UL << RCC_CSR_MSISSRANGE_Pos) |
| #define | RCC_CSR_MSISSRANGE_2 (0x4UL << RCC_CSR_MSISSRANGE_Pos) |
| #define | RCC_CSR_MSISSRANGE_3 (0x8UL << RCC_CSR_MSISSRANGE_Pos) |
| #define | RCC_CSR_RMVF_Pos (23U) |
| #define | RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) |
| #define | RCC_CSR_RMVF RCC_CSR_RMVF_Msk |
| #define | RCC_CSR_OBLRSTF_Pos (25U) |
| #define | RCC_CSR_OBLRSTF_Msk (0x1UL << RCC_CSR_OBLRSTF_Pos) |
| #define | RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk |
| #define | RCC_CSR_PINRSTF_Pos (26U) |
| #define | RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) |
| #define | RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk |
| #define | RCC_CSR_BORRSTF_Pos (27U) |
| #define | RCC_CSR_BORRSTF_Msk (0x1UL << RCC_CSR_BORRSTF_Pos) |
| #define | RCC_CSR_BORRSTF RCC_CSR_BORRSTF_Msk |
| #define | RCC_CSR_SFTRSTF_Pos (28U) |
| #define | RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) |
| #define | RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk |
| #define | RCC_CSR_IWDGRSTF_Pos (29U) |
| #define | RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) |
| #define | RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk |
| #define | RCC_CSR_WWDGRSTF_Pos (30U) |
| #define | RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) |
| #define | RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk |
| #define | RCC_CSR_LPWRRSTF_Pos (31U) |
| #define | RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) |
| #define | RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk |
| #define | RCC_SECCFGR_HSISEC_Pos (0U) |
| #define | RCC_SECCFGR_HSISEC_Msk (0x1UL << RCC_SECCFGR_HSISEC_Pos) |
| #define | RCC_SECCFGR_HSISEC RCC_SECCFGR_HSISEC_Msk |
| #define | RCC_SECCFGR_HSESEC_Pos (1U) |
| #define | RCC_SECCFGR_HSESEC_Msk (0x1UL << RCC_SECCFGR_HSESEC_Pos) |
| #define | RCC_SECCFGR_HSESEC RCC_SECCFGR_HSESEC_Msk |
| #define | RCC_SECCFGR_MSISEC_Pos (2U) |
| #define | RCC_SECCFGR_MSISEC_Msk (0x1UL << RCC_SECCFGR_MSISEC_Pos) |
| #define | RCC_SECCFGR_MSISEC RCC_SECCFGR_MSISEC_Msk |
| #define | RCC_SECCFGR_LSISEC_Pos (3U) |
| #define | RCC_SECCFGR_LSISEC_Msk (0x1UL << RCC_SECCFGR_LSISEC_Pos) |
| #define | RCC_SECCFGR_LSISEC RCC_SECCFGR_LSISEC_Msk |
| #define | RCC_SECCFGR_LSESEC_Pos (4U) |
| #define | RCC_SECCFGR_LSESEC_Msk (0x1UL << RCC_SECCFGR_LSESEC_Pos) |
| #define | RCC_SECCFGR_LSESEC RCC_SECCFGR_LSESEC_Msk |
| #define | RCC_SECCFGR_SYSCLKSEC_Pos (5U) |
| #define | RCC_SECCFGR_SYSCLKSEC_Msk (0x1UL << RCC_SECCFGR_SYSCLKSEC_Pos) |
| #define | RCC_SECCFGR_SYSCLKSEC RCC_SECCFGR_SYSCLKSEC_Msk |
| #define | RCC_SECCFGR_PRESCSEC_Pos (6U) |
| #define | RCC_SECCFGR_PRESCSEC_Msk (0x1UL << RCC_SECCFGR_PRESCSEC_Pos) |
| #define | RCC_SECCFGR_PRESCSEC RCC_SECCFGR_PRESCSEC_Msk |
| #define | RCC_SECCFGR_PLL1SEC_Pos (7U) |
| #define | RCC_SECCFGR_PLL1SEC_Msk (0x1UL << RCC_SECCFGR_PLL1SEC_Pos) |
| #define | RCC_SECCFGR_PLL1SEC RCC_SECCFGR_PLL1SEC_Msk |
| #define | RCC_SECCFGR_PLL2SEC_Pos (8U) |
| #define | RCC_SECCFGR_PLL2SEC_Msk (0x1UL << RCC_SECCFGR_PLL2SEC_Pos) |
| #define | RCC_SECCFGR_PLL2SEC RCC_SECCFGR_PLL2SEC_Msk |
| #define | RCC_SECCFGR_PLL3SEC_Pos (9U) |
| #define | RCC_SECCFGR_PLL3SEC_Msk (0x1UL << RCC_SECCFGR_PLL3SEC_Pos) |
| #define | RCC_SECCFGR_PLL3SEC RCC_SECCFGR_PLL3SEC_Msk |
| #define | RCC_SECCFGR_ICLKSEC_Pos (10U) |
| #define | RCC_SECCFGR_ICLKSEC_Msk (0x1UL << RCC_SECCFGR_ICLKSEC_Pos) |
| #define | RCC_SECCFGR_ICLKSEC RCC_SECCFGR_ICLKSEC_Msk |
| #define | RCC_SECCFGR_HSI48SEC_Pos (11U) |
| #define | RCC_SECCFGR_HSI48SEC_Msk (0x1UL << RCC_SECCFGR_HSI48SEC_Pos) |
| #define | RCC_SECCFGR_HSI48SEC RCC_SECCFGR_HSI48SEC_Msk |
| #define | RCC_SECCFGR_RMVFSEC_Pos (12U) |
| #define | RCC_SECCFGR_RMVFSEC_Msk (0x1UL << RCC_SECCFGR_RMVFSEC_Pos) |
| #define | RCC_SECCFGR_RMVFSEC RCC_SECCFGR_RMVFSEC_Msk |
| #define | RCC_PRIVCFGR_SPRIV_Pos (0U) |
| #define | RCC_PRIVCFGR_SPRIV_Msk (0x1UL << RCC_PRIVCFGR_SPRIV_Pos) |
| #define | RCC_PRIVCFGR_SPRIV RCC_PRIVCFGR_SPRIV_Msk |
| #define | RCC_PRIVCFGR_NSPRIV_Pos (1U) |
| #define | RCC_PRIVCFGR_NSPRIV_Msk (0x1UL << RCC_PRIVCFGR_NSPRIV_Pos) |
| #define | RCC_PRIVCFGR_NSPRIV RCC_PRIVCFGR_NSPRIV_Msk |
| #define | RTC_TR_SU_Pos (0U) |
| #define | RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) |
| #define | RTC_TR_SU RTC_TR_SU_Msk |
| #define | RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) |
| #define | RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) |
| #define | RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) |
| #define | RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) |
| #define | RTC_TR_ST_Pos (4U) |
| #define | RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) |
| #define | RTC_TR_ST RTC_TR_ST_Msk |
| #define | RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) |
| #define | RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) |
| #define | RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) |
| #define | RTC_TR_MNU_Pos (8U) |
| #define | RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) |
| #define | RTC_TR_MNU RTC_TR_MNU_Msk |
| #define | RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) |
| #define | RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) |
| #define | RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) |
| #define | RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) |
| #define | RTC_TR_MNT_Pos (12U) |
| #define | RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) |
| #define | RTC_TR_MNT RTC_TR_MNT_Msk |
| #define | RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) |
| #define | RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) |
| #define | RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) |
| #define | RTC_TR_HU_Pos (16U) |
| #define | RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) |
| #define | RTC_TR_HU RTC_TR_HU_Msk |
| #define | RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) |
| #define | RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) |
| #define | RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) |
| #define | RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) |
| #define | RTC_TR_HT_Pos (20U) |
| #define | RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) |
| #define | RTC_TR_HT RTC_TR_HT_Msk |
| #define | RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) |
| #define | RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) |
| #define | RTC_TR_PM_Pos (22U) |
| #define | RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) |
| #define | RTC_TR_PM RTC_TR_PM_Msk |
| #define | RTC_DR_DU_Pos (0U) |
| #define | RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) |
| #define | RTC_DR_DU RTC_DR_DU_Msk |
| #define | RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) |
| #define | RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) |
| #define | RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) |
| #define | RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) |
| #define | RTC_DR_DT_Pos (4U) |
| #define | RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) |
| #define | RTC_DR_DT RTC_DR_DT_Msk |
| #define | RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) |
| #define | RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) |
| #define | RTC_DR_MU_Pos (8U) |
| #define | RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) |
| #define | RTC_DR_MU RTC_DR_MU_Msk |
| #define | RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) |
| #define | RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) |
| #define | RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) |
| #define | RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) |
| #define | RTC_DR_MT_Pos (12U) |
| #define | RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) |
| #define | RTC_DR_MT RTC_DR_MT_Msk |
| #define | RTC_DR_WDU_Pos (13U) |
| #define | RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) |
| #define | RTC_DR_WDU RTC_DR_WDU_Msk |
| #define | RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) |
| #define | RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) |
| #define | RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) |
| #define | RTC_DR_YU_Pos (16U) |
| #define | RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) |
| #define | RTC_DR_YU RTC_DR_YU_Msk |
| #define | RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) |
| #define | RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) |
| #define | RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) |
| #define | RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) |
| #define | RTC_DR_YT_Pos (20U) |
| #define | RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) |
| #define | RTC_DR_YT RTC_DR_YT_Msk |
| #define | RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) |
| #define | RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) |
| #define | RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) |
| #define | RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) |
| #define | RTC_SSR_SS_Pos (0U) |
| #define | RTC_SSR_SS_Msk (0xFFFFFFFFUL << RTC_SSR_SS_Pos) |
| #define | RTC_SSR_SS RTC_SSR_SS_Msk |
| #define | RTC_ICSR_WUTWF_Pos (2U) |
| #define | RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) |
| #define | RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk |
| #define | RTC_ICSR_SHPF_Pos (3U) |
| #define | RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) |
| #define | RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk |
| #define | RTC_ICSR_INITS_Pos (4U) |
| #define | RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) |
| #define | RTC_ICSR_INITS RTC_ICSR_INITS_Msk |
| #define | RTC_ICSR_RSF_Pos (5U) |
| #define | RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) |
| #define | RTC_ICSR_RSF RTC_ICSR_RSF_Msk |
| #define | RTC_ICSR_INITF_Pos (6U) |
| #define | RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) |
| #define | RTC_ICSR_INITF RTC_ICSR_INITF_Msk |
| #define | RTC_ICSR_INIT_Pos (7U) |
| #define | RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) |
| #define | RTC_ICSR_INIT RTC_ICSR_INIT_Msk |
| #define | RTC_ICSR_BIN_Pos (8U) |
| #define | RTC_ICSR_BIN_Msk (0x3UL << RTC_ICSR_BIN_Pos) |
| #define | RTC_ICSR_BIN RTC_ICSR_BIN_Msk |
| #define | RTC_ICSR_BIN_0 (0x1UL << RTC_ICSR_BIN_Pos) |
| #define | RTC_ICSR_BIN_1 (0x2UL << RTC_ICSR_BIN_Pos) |
| #define | RTC_ICSR_BCDU_Pos (10U) |
| #define | RTC_ICSR_BCDU_Msk (0x7UL << RTC_ICSR_BCDU_Pos) |
| #define | RTC_ICSR_BCDU RTC_ICSR_BCDU_Msk |
| #define | RTC_ICSR_BCDU_0 (0x1UL << RTC_ICSR_BCDU_Pos) |
| #define | RTC_ICSR_BCDU_1 (0x2UL << RTC_ICSR_BCDU_Pos) |
| #define | RTC_ICSR_BCDU_2 (0x4UL << RTC_ICSR_BCDU_Pos) |
| #define | RTC_ICSR_RECALPF_Pos (16U) |
| #define | RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) |
| #define | RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk |
| #define | RTC_PRER_PREDIV_S_Pos (0U) |
| #define | RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) |
| #define | RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk |
| #define | RTC_PRER_PREDIV_A_Pos (16U) |
| #define | RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) |
| #define | RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk |
| #define | RTC_WUTR_WUT_Pos (0U) |
| #define | RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) |
| #define | RTC_WUTR_WUT RTC_WUTR_WUT_Msk |
| #define | RTC_WUTR_WUTOCLR_Pos (16U) |
| #define | RTC_WUTR_WUTOCLR_Msk (0xFFFFUL << RTC_WUTR_WUTOCLR_Pos) |
| #define | RTC_WUTR_WUTOCLR RTC_WUTR_WUTOCLR_Msk |
| #define | RTC_CR_WUCKSEL_Pos (0U) |
| #define | RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) |
| #define | RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk |
| #define | RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) |
| #define | RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) |
| #define | RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) |
| #define | RTC_CR_TSEDGE_Pos (3U) |
| #define | RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) |
| #define | RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk |
| #define | RTC_CR_REFCKON_Pos (4U) |
| #define | RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) |
| #define | RTC_CR_REFCKON RTC_CR_REFCKON_Msk |
| #define | RTC_CR_BYPSHAD_Pos (5U) |
| #define | RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) |
| #define | RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk |
| #define | RTC_CR_FMT_Pos (6U) |
| #define | RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) |
| #define | RTC_CR_FMT RTC_CR_FMT_Msk |
| #define | RTC_CR_SSRUIE_Pos (7U) |
| #define | RTC_CR_SSRUIE_Msk (0x1UL << RTC_CR_SSRUIE_Pos) |
| #define | RTC_CR_SSRUIE RTC_CR_SSRUIE_Msk |
| #define | RTC_CR_ALRAE_Pos (8U) |
| #define | RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) |
| #define | RTC_CR_ALRAE RTC_CR_ALRAE_Msk |
| #define | RTC_CR_ALRBE_Pos (9U) |
| #define | RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) |
| #define | RTC_CR_ALRBE RTC_CR_ALRBE_Msk |
| #define | RTC_CR_WUTE_Pos (10U) |
| #define | RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) |
| #define | RTC_CR_WUTE RTC_CR_WUTE_Msk |
| #define | RTC_CR_TSE_Pos (11U) |
| #define | RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) |
| #define | RTC_CR_TSE RTC_CR_TSE_Msk |
| #define | RTC_CR_ALRAIE_Pos (12U) |
| #define | RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) |
| #define | RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk |
| #define | RTC_CR_ALRBIE_Pos (13U) |
| #define | RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) |
| #define | RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk |
| #define | RTC_CR_WUTIE_Pos (14U) |
| #define | RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) |
| #define | RTC_CR_WUTIE RTC_CR_WUTIE_Msk |
| #define | RTC_CR_TSIE_Pos (15U) |
| #define | RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) |
| #define | RTC_CR_TSIE RTC_CR_TSIE_Msk |
| #define | RTC_CR_ADD1H_Pos (16U) |
| #define | RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) |
| #define | RTC_CR_ADD1H RTC_CR_ADD1H_Msk |
| #define | RTC_CR_SUB1H_Pos (17U) |
| #define | RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) |
| #define | RTC_CR_SUB1H RTC_CR_SUB1H_Msk |
| #define | RTC_CR_BKP_Pos (18U) |
| #define | RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) |
| #define | RTC_CR_BKP RTC_CR_BKP_Msk |
| #define | RTC_CR_COSEL_Pos (19U) |
| #define | RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) |
| #define | RTC_CR_COSEL RTC_CR_COSEL_Msk |
| #define | RTC_CR_POL_Pos (20U) |
| #define | RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) |
| #define | RTC_CR_POL RTC_CR_POL_Msk |
| #define | RTC_CR_OSEL_Pos (21U) |
| #define | RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) |
| #define | RTC_CR_OSEL RTC_CR_OSEL_Msk |
| #define | RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) |
| #define | RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) |
| #define | RTC_CR_COE_Pos (23U) |
| #define | RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) |
| #define | RTC_CR_COE RTC_CR_COE_Msk |
| #define | RTC_CR_ITSE_Pos (24U) |
| #define | RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) |
| #define | RTC_CR_ITSE RTC_CR_ITSE_Msk |
| #define | RTC_CR_TAMPTS_Pos (25U) |
| #define | RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) |
| #define | RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk |
| #define | RTC_CR_TAMPOE_Pos (26U) |
| #define | RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) |
| #define | RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk |
| #define | RTC_CR_ALRAFCLR_Pos (27U) |
| #define | RTC_CR_ALRAFCLR_Msk (0x1UL << RTC_CR_ALRAFCLR_Pos) |
| #define | RTC_CR_ALRAFCLR RTC_CR_ALRAFCLR_Msk |
| #define | RTC_CR_ALRBFCLR_Pos (28U) |
| #define | RTC_CR_ALRBFCLR_Msk (0x1UL << RTC_CR_ALRBFCLR_Pos) |
| #define | RTC_CR_ALRBFCLR RTC_CR_ALRBFCLR_Msk |
| #define | RTC_CR_TAMPALRM_PU_Pos (29U) |
| #define | RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) |
| #define | RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk |
| #define | RTC_CR_TAMPALRM_TYPE_Pos (30U) |
| #define | RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) |
| #define | RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk |
| #define | RTC_CR_OUT2EN_Pos (31U) |
| #define | RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) |
| #define | RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk |
| #define | RTC_PRIVCFGR_ALRAPRIV_Pos (0U) |
| #define | RTC_PRIVCFGR_ALRAPRIV_Msk (0x1UL << RTC_PRIVCFGR_ALRAPRIV_Pos) |
| #define | RTC_PRIVCFGR_ALRAPRIV RTC_PRIVCFGR_ALRAPRIV_Msk |
| #define | RTC_PRIVCFGR_ALRBPRIV_Pos (1U) |
| #define | RTC_PRIVCFGR_ALRBPRIV_Msk (0x1UL << RTC_PRIVCFGR_ALRBPRIV_Pos) |
| #define | RTC_PRIVCFGR_ALRBPRIV RTC_PRIVCFGR_ALRBPRIV_Msk |
| #define | RTC_PRIVCFGR_WUTPRIV_Pos (2U) |
| #define | RTC_PRIVCFGR_WUTPRIV_Msk (0x1UL << RTC_PRIVCFGR_WUTPRIV_Pos) |
| #define | RTC_PRIVCFGR_WUTPRIV RTC_PRIVCFGR_WUTPRIV_Msk |
| #define | RTC_PRIVCFGR_TSPRIV_Pos (3U) |
| #define | RTC_PRIVCFGR_TSPRIV_Msk (0x1UL << RTC_PRIVCFGR_TSPRIV_Pos) |
| #define | RTC_PRIVCFGR_TSPRIV RTC_PRIVCFGR_TSPRIV_Msk |
| #define | RTC_PRIVCFGR_CALPRIV_Pos (13U) |
| #define | RTC_PRIVCFGR_CALPRIV_Msk (0x1UL << RTC_PRIVCFGR_CALPRIV_Pos) |
| #define | RTC_PRIVCFGR_CALPRIV RTC_PRIVCFGR_CALPRIV_Msk |
| #define | RTC_PRIVCFGR_INITPRIV_Pos (14U) |
| #define | RTC_PRIVCFGR_INITPRIV_Msk (0x1UL << RTC_PRIVCFGR_INITPRIV_Pos) |
| #define | RTC_PRIVCFGR_INITPRIV RTC_PRIVCFGR_INITPRIV_Msk |
| #define | RTC_PRIVCFGR_PRIV_Pos (15U) |
| #define | RTC_PRIVCFGR_PRIV_Msk (0x1UL << RTC_PRIVCFGR_PRIV_Pos) |
| #define | RTC_PRIVCFGR_PRIV RTC_PRIVCFGR_PRIV_Msk |
| #define | RTC_SECCFGR_ALRASEC_Pos (0U) |
| #define | RTC_SECCFGR_ALRASEC_Msk (0x1UL << RTC_SECCFGR_ALRASEC_Pos) |
| #define | RTC_SECCFGR_ALRASEC RTC_SECCFGR_ALRASEC_Msk |
| #define | RTC_SECCFGR_ALRBSEC_Pos (1U) |
| #define | RTC_SECCFGR_ALRBSEC_Msk (0x1UL << RTC_SECCFGR_ALRBSEC_Pos) |
| #define | RTC_SECCFGR_ALRBSEC RTC_SECCFGR_ALRBSEC_Msk |
| #define | RTC_SECCFGR_WUTSEC_Pos (2U) |
| #define | RTC_SECCFGR_WUTSEC_Msk (0x1UL << RTC_SECCFGR_WUTSEC_Pos) |
| #define | RTC_SECCFGR_WUTSEC RTC_SECCFGR_WUTSEC_Msk |
| #define | RTC_SECCFGR_TSSEC_Pos (3U) |
| #define | RTC_SECCFGR_TSSEC_Msk (0x1UL << RTC_SECCFGR_TSSEC_Pos) |
| #define | RTC_SECCFGR_TSSEC RTC_SECCFGR_TSSEC_Msk |
| #define | RTC_SECCFGR_CALSEC_Pos (13U) |
| #define | RTC_SECCFGR_CALSEC_Msk (0x1UL << RTC_SECCFGR_CALSEC_Pos) |
| #define | RTC_SECCFGR_CALSEC RTC_SECCFGR_CALSEC_Msk |
| #define | RTC_SECCFGR_INITSEC_Pos (14U) |
| #define | RTC_SECCFGR_INITSEC_Msk (0x1UL << RTC_SECCFGR_INITSEC_Pos) |
| #define | RTC_SECCFGR_INITSEC RTC_SECCFGR_INITSEC_Msk |
| #define | RTC_SECCFGR_SEC_Pos (15U) |
| #define | RTC_SECCFGR_SEC_Msk (0x1UL << RTC_SECCFGR_SEC_Pos) |
| #define | RTC_SECCFGR_SEC RTC_SECCFGR_SEC_Msk |
| #define | RTC_WPR_KEY_Pos (0U) |
| #define | RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) |
| #define | RTC_WPR_KEY RTC_WPR_KEY_Msk |
| #define | RTC_CALR_CALM_Pos (0U) |
| #define | RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) |
| #define | RTC_CALR_CALM RTC_CALR_CALM_Msk |
| #define | RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) |
| #define | RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) |
| #define | RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) |
| #define | RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) |
| #define | RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) |
| #define | RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) |
| #define | RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) |
| #define | RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) |
| #define | RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) |
| #define | RTC_CALR_LPCAL_Pos (12U) |
| #define | RTC_CALR_LPCAL_Msk (0x1UL << RTC_CALR_LPCAL_Pos) |
| #define | RTC_CALR_CALW16 RTC_CALR_CALW16_Msk |
| #define | RTC_CALR_CALW16_Pos (13U) |
| #define | RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) |
| #define | RTC_CALR_LPCAL RTC_CALR_LPCAL_Msk |
| #define | RTC_CALR_CALW8_Pos (14U) |
| #define | RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) |
| #define | RTC_CALR_CALW8 RTC_CALR_CALW8_Msk |
| #define | RTC_CALR_CALP_Pos (15U) |
| #define | RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) |
| #define | RTC_CALR_CALP RTC_CALR_CALP_Msk |
| #define | RTC_SHIFTR_SUBFS_Pos (0U) |
| #define | RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) |
| #define | RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk |
| #define | RTC_SHIFTR_ADD1S_Pos (31U) |
| #define | RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) |
| #define | RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk |
| #define | RTC_TSTR_SU_Pos (0U) |
| #define | RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) |
| #define | RTC_TSTR_SU RTC_TSTR_SU_Msk |
| #define | RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) |
| #define | RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) |
| #define | RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) |
| #define | RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) |
| #define | RTC_TSTR_ST_Pos (4U) |
| #define | RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) |
| #define | RTC_TSTR_ST RTC_TSTR_ST_Msk |
| #define | RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) |
| #define | RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) |
| #define | RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) |
| #define | RTC_TSTR_MNU_Pos (8U) |
| #define | RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) |
| #define | RTC_TSTR_MNU RTC_TSTR_MNU_Msk |
| #define | RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) |
| #define | RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) |
| #define | RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) |
| #define | RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) |
| #define | RTC_TSTR_MNT_Pos (12U) |
| #define | RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) |
| #define | RTC_TSTR_MNT RTC_TSTR_MNT_Msk |
| #define | RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) |
| #define | RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) |
| #define | RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) |
| #define | RTC_TSTR_HU_Pos (16U) |
| #define | RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) |
| #define | RTC_TSTR_HU RTC_TSTR_HU_Msk |
| #define | RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) |
| #define | RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) |
| #define | RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) |
| #define | RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) |
| #define | RTC_TSTR_HT_Pos (20U) |
| #define | RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) |
| #define | RTC_TSTR_HT RTC_TSTR_HT_Msk |
| #define | RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) |
| #define | RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) |
| #define | RTC_TSTR_PM_Pos (22U) |
| #define | RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) |
| #define | RTC_TSTR_PM RTC_TSTR_PM_Msk |
| #define | RTC_TSDR_DU_Pos (0U) |
| #define | RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) |
| #define | RTC_TSDR_DU RTC_TSDR_DU_Msk |
| #define | RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) |
| #define | RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) |
| #define | RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) |
| #define | RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) |
| #define | RTC_TSDR_DT_Pos (4U) |
| #define | RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) |
| #define | RTC_TSDR_DT RTC_TSDR_DT_Msk |
| #define | RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) |
| #define | RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) |
| #define | RTC_TSDR_MU_Pos (8U) |
| #define | RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) |
| #define | RTC_TSDR_MU RTC_TSDR_MU_Msk |
| #define | RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) |
| #define | RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) |
| #define | RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) |
| #define | RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) |
| #define | RTC_TSDR_MT_Pos (12U) |
| #define | RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) |
| #define | RTC_TSDR_MT RTC_TSDR_MT_Msk |
| #define | RTC_TSDR_WDU_Pos (13U) |
| #define | RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) |
| #define | RTC_TSDR_WDU RTC_TSDR_WDU_Msk |
| #define | RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) |
| #define | RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) |
| #define | RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) |
| #define | RTC_TSSSR_SS_Pos (0U) |
| #define | RTC_TSSSR_SS_Msk (0xFFFFFFFFUL << RTC_TSSSR_SS_Pos) |
| #define | RTC_TSSSR_SS RTC_TSSSR_SS_Msk |
| #define | RTC_ALRMAR_SU_Pos (0U) |
| #define | RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) |
| #define | RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk |
| #define | RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) |
| #define | RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) |
| #define | RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) |
| #define | RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) |
| #define | RTC_ALRMAR_ST_Pos (4U) |
| #define | RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) |
| #define | RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk |
| #define | RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) |
| #define | RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) |
| #define | RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) |
| #define | RTC_ALRMAR_MSK1_Pos (7U) |
| #define | RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) |
| #define | RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk |
| #define | RTC_ALRMAR_MNU_Pos (8U) |
| #define | RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) |
| #define | RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk |
| #define | RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) |
| #define | RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) |
| #define | RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) |
| #define | RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) |
| #define | RTC_ALRMAR_MNT_Pos (12U) |
| #define | RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) |
| #define | RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk |
| #define | RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) |
| #define | RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) |
| #define | RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) |
| #define | RTC_ALRMAR_MSK2_Pos (15U) |
| #define | RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) |
| #define | RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk |
| #define | RTC_ALRMAR_HU_Pos (16U) |
| #define | RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) |
| #define | RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk |
| #define | RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) |
| #define | RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) |
| #define | RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) |
| #define | RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) |
| #define | RTC_ALRMAR_HT_Pos (20U) |
| #define | RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) |
| #define | RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk |
| #define | RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) |
| #define | RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) |
| #define | RTC_ALRMAR_PM_Pos (22U) |
| #define | RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) |
| #define | RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk |
| #define | RTC_ALRMAR_MSK3_Pos (23U) |
| #define | RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) |
| #define | RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk |
| #define | RTC_ALRMAR_DU_Pos (24U) |
| #define | RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) |
| #define | RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk |
| #define | RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) |
| #define | RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) |
| #define | RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) |
| #define | RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) |
| #define | RTC_ALRMAR_DT_Pos (28U) |
| #define | RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) |
| #define | RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk |
| #define | RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) |
| #define | RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) |
| #define | RTC_ALRMAR_WDSEL_Pos (30U) |
| #define | RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) |
| #define | RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk |
| #define | RTC_ALRMAR_MSK4_Pos (31U) |
| #define | RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) |
| #define | RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk |
| #define | RTC_ALRMASSR_SS_Pos (0U) |
| #define | RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) |
| #define | RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk |
| #define | RTC_ALRMASSR_MASKSS_Pos (24U) |
| #define | RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) |
| #define | RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk |
| #define | RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) |
| #define | RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) |
| #define | RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) |
| #define | RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) |
| #define | RTC_ALRMASSR_SSCLR_Pos (31U) |
| #define | RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) |
| #define | RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk |
| #define | RTC_ALRMBR_SU_Pos (0U) |
| #define | RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) |
| #define | RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk |
| #define | RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) |
| #define | RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) |
| #define | RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) |
| #define | RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) |
| #define | RTC_ALRMBR_ST_Pos (4U) |
| #define | RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) |
| #define | RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk |
| #define | RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) |
| #define | RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) |
| #define | RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) |
| #define | RTC_ALRMBR_MSK1_Pos (7U) |
| #define | RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) |
| #define | RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk |
| #define | RTC_ALRMBR_MNU_Pos (8U) |
| #define | RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) |
| #define | RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk |
| #define | RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) |
| #define | RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) |
| #define | RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) |
| #define | RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) |
| #define | RTC_ALRMBR_MNT_Pos (12U) |
| #define | RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) |
| #define | RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk |
| #define | RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) |
| #define | RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) |
| #define | RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) |
| #define | RTC_ALRMBR_MSK2_Pos (15U) |
| #define | RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) |
| #define | RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk |
| #define | RTC_ALRMBR_HU_Pos (16U) |
| #define | RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) |
| #define | RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk |
| #define | RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) |
| #define | RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) |
| #define | RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) |
| #define | RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) |
| #define | RTC_ALRMBR_HT_Pos (20U) |
| #define | RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) |
| #define | RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk |
| #define | RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) |
| #define | RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) |
| #define | RTC_ALRMBR_PM_Pos (22U) |
| #define | RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) |
| #define | RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk |
| #define | RTC_ALRMBR_MSK3_Pos (23U) |
| #define | RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) |
| #define | RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk |
| #define | RTC_ALRMBR_DU_Pos (24U) |
| #define | RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) |
| #define | RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk |
| #define | RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) |
| #define | RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) |
| #define | RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) |
| #define | RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) |
| #define | RTC_ALRMBR_DT_Pos (28U) |
| #define | RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) |
| #define | RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk |
| #define | RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) |
| #define | RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) |
| #define | RTC_ALRMBR_WDSEL_Pos (30U) |
| #define | RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) |
| #define | RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk |
| #define | RTC_ALRMBR_MSK4_Pos (31U) |
| #define | RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) |
| #define | RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk |
| #define | RTC_ALRMBSSR_SS_Pos (0U) |
| #define | RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) |
| #define | RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk |
| #define | RTC_ALRMBSSR_MASKSS_Pos (24U) |
| #define | RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) |
| #define | RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk |
| #define | RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) |
| #define | RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) |
| #define | RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) |
| #define | RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) |
| #define | RTC_ALRMBSSR_SSCLR_Pos (31U) |
| #define | RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) |
| #define | RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk |
| #define | RTC_SR_ALRAF_Pos (0U) |
| #define | RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) |
| #define | RTC_SR_ALRAF RTC_SR_ALRAF_Msk |
| #define | RTC_SR_ALRBF_Pos (1U) |
| #define | RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) |
| #define | RTC_SR_ALRBF RTC_SR_ALRBF_Msk |
| #define | RTC_SR_WUTF_Pos (2U) |
| #define | RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) |
| #define | RTC_SR_WUTF RTC_SR_WUTF_Msk |
| #define | RTC_SR_TSF_Pos (3U) |
| #define | RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) |
| #define | RTC_SR_TSF RTC_SR_TSF_Msk |
| #define | RTC_SR_TSOVF_Pos (4U) |
| #define | RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) |
| #define | RTC_SR_TSOVF RTC_SR_TSOVF_Msk |
| #define | RTC_SR_ITSF_Pos (5U) |
| #define | RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) |
| #define | RTC_SR_ITSF RTC_SR_ITSF_Msk |
| #define | RTC_SR_SSRUF_Pos (6U) |
| #define | RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) |
| #define | RTC_SR_SSRUF RTC_SR_SSRUF_Msk |
| #define | RTC_MISR_ALRAMF_Pos (0U) |
| #define | RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) |
| #define | RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk |
| #define | RTC_MISR_ALRBMF_Pos (1U) |
| #define | RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) |
| #define | RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk |
| #define | RTC_MISR_WUTMF_Pos (2U) |
| #define | RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) |
| #define | RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk |
| #define | RTC_MISR_TSMF_Pos (3U) |
| #define | RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) |
| #define | RTC_MISR_TSMF RTC_MISR_TSMF_Msk |
| #define | RTC_MISR_TSOVMF_Pos (4U) |
| #define | RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) |
| #define | RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk |
| #define | RTC_MISR_ITSMF_Pos (5U) |
| #define | RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) |
| #define | RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk |
| #define | RTC_MISR_SSRUMF_Pos (6U) |
| #define | RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) |
| #define | RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk |
| #define | RTC_SMISR_ALRAMF_Pos (0U) |
| #define | RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) |
| #define | RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk |
| #define | RTC_SMISR_ALRBMF_Pos (1U) |
| #define | RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) |
| #define | RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk |
| #define | RTC_SMISR_WUTMF_Pos (2U) |
| #define | RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) |
| #define | RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk |
| #define | RTC_SMISR_TSMF_Pos (3U) |
| #define | RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) |
| #define | RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk |
| #define | RTC_SMISR_TSOVMF_Pos (4U) |
| #define | RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) |
| #define | RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk |
| #define | RTC_SMISR_ITSMF_Pos (5U) |
| #define | RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) |
| #define | RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk |
| #define | RTC_SMISR_SSRUMF_Pos (6U) |
| #define | RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) |
| #define | RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk |
| #define | RTC_SCR_CALRAF_Pos (0U) |
| #define | RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) |
| #define | RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk |
| #define | RTC_SCR_CALRBF_Pos (1U) |
| #define | RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) |
| #define | RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk |
| #define | RTC_SCR_CWUTF_Pos (2U) |
| #define | RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) |
| #define | RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk |
| #define | RTC_SCR_CTSF_Pos (3U) |
| #define | RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) |
| #define | RTC_SCR_CTSF RTC_SCR_CTSF_Msk |
| #define | RTC_SCR_CTSOVF_Pos (4U) |
| #define | RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) |
| #define | RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk |
| #define | RTC_SCR_CITSF_Pos (5U) |
| #define | RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) |
| #define | RTC_SCR_CITSF RTC_SCR_CITSF_Msk |
| #define | RTC_SCR_CSSRUF_Pos (6U) |
| #define | RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) |
| #define | RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk |
| #define | RTC_ALRABINR_SS_Pos (0U) |
| #define | RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) |
| #define | RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk |
| #define | RTC_ALRBBINR_SS_Pos (0U) |
| #define | RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) |
| #define | RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk |
| #define | TAMP_CR1_TAMP1E_Pos (0U) |
| #define | TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) |
| #define | TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk |
| #define | TAMP_CR1_TAMP2E_Pos (1U) |
| #define | TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) |
| #define | TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk |
| #define | TAMP_CR1_TAMP3E_Pos (2U) |
| #define | TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) |
| #define | TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk |
| #define | TAMP_CR1_TAMP4E_Pos (3U) |
| #define | TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) |
| #define | TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk |
| #define | TAMP_CR1_TAMP5E_Pos (4U) |
| #define | TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) |
| #define | TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk |
| #define | TAMP_CR1_TAMP6E_Pos (5U) |
| #define | TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) |
| #define | TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk |
| #define | TAMP_CR1_TAMP7E_Pos (6U) |
| #define | TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) |
| #define | TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk |
| #define | TAMP_CR1_TAMP8E_Pos (7U) |
| #define | TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) |
| #define | TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk |
| #define | TAMP_CR1_ITAMP1E_Pos (16U) |
| #define | TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) |
| #define | TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk |
| #define | TAMP_CR1_ITAMP2E_Pos (17U) |
| #define | TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) |
| #define | TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk |
| #define | TAMP_CR1_ITAMP3E_Pos (18U) |
| #define | TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) |
| #define | TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk |
| #define | TAMP_CR1_ITAMP5E_Pos (20U) |
| #define | TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) |
| #define | TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk |
| #define | TAMP_CR1_ITAMP6E_Pos (21U) |
| #define | TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) |
| #define | TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk |
| #define | TAMP_CR1_ITAMP7E_Pos (22U) |
| #define | TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) |
| #define | TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk |
| #define | TAMP_CR1_ITAMP8E_Pos (23U) |
| #define | TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) |
| #define | TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk |
| #define | TAMP_CR1_ITAMP9E_Pos (24U) |
| #define | TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) |
| #define | TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk |
| #define | TAMP_CR1_ITAMP11E_Pos (26U) |
| #define | TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) |
| #define | TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk |
| #define | TAMP_CR1_ITAMP12E_Pos (27U) |
| #define | TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) |
| #define | TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk |
| #define | TAMP_CR1_ITAMP13E_Pos (28U) |
| #define | TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) |
| #define | TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk |
| #define | TAMP_CR2_TAMP1NOERASE_Pos (0U) |
| #define | TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) |
| #define | TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk |
| #define | TAMP_CR2_TAMP2NOERASE_Pos (1U) |
| #define | TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) |
| #define | TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk |
| #define | TAMP_CR2_TAMP3NOERASE_Pos (2U) |
| #define | TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) |
| #define | TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk |
| #define | TAMP_CR2_TAMP4NOERASE_Pos (3U) |
| #define | TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) |
| #define | TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk |
| #define | TAMP_CR2_TAMP5NOERASE_Pos (4U) |
| #define | TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) |
| #define | TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk |
| #define | TAMP_CR2_TAMP6NOERASE_Pos (5U) |
| #define | TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) |
| #define | TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk |
| #define | TAMP_CR2_TAMP7NOERASE_Pos (6U) |
| #define | TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) |
| #define | TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk |
| #define | TAMP_CR2_TAMP8NOERASE_Pos (7U) |
| #define | TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) |
| #define | TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk |
| #define | TAMP_CR2_TAMP1MSK_Pos (16U) |
| #define | TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) |
| #define | TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk |
| #define | TAMP_CR2_TAMP2MSK_Pos (17U) |
| #define | TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) |
| #define | TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk |
| #define | TAMP_CR2_TAMP3MSK_Pos (18U) |
| #define | TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) |
| #define | TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk |
| #define | TAMP_CR2_BKBLOCK_Pos (22U) |
| #define | TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) |
| #define | TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk |
| #define | TAMP_CR2_BKERASE_Pos (23U) |
| #define | TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) |
| #define | TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk |
| #define | TAMP_CR2_TAMP1TRG_Pos (24U) |
| #define | TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) |
| #define | TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk |
| #define | TAMP_CR2_TAMP2TRG_Pos (25U) |
| #define | TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) |
| #define | TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk |
| #define | TAMP_CR2_TAMP3TRG_Pos (26U) |
| #define | TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) |
| #define | TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk |
| #define | TAMP_CR2_TAMP4TRG_Pos (27U) |
| #define | TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) |
| #define | TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk |
| #define | TAMP_CR2_TAMP5TRG_Pos (28U) |
| #define | TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) |
| #define | TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk |
| #define | TAMP_CR2_TAMP6TRG_Pos (29U) |
| #define | TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) |
| #define | TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk |
| #define | TAMP_CR2_TAMP7TRG_Pos (30U) |
| #define | TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) |
| #define | TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk |
| #define | TAMP_CR2_TAMP8TRG_Pos (31U) |
| #define | TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) |
| #define | TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk |
| #define | TAMP_CR3_ITAMP1NOER_Pos (0U) |
| #define | TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) |
| #define | TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk |
| #define | TAMP_CR3_ITAMP2NOER_Pos (1U) |
| #define | TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) |
| #define | TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk |
| #define | TAMP_CR3_ITAMP3NOER_Pos (2U) |
| #define | TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) |
| #define | TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk |
| #define | TAMP_CR3_ITAMP5NOER_Pos (4U) |
| #define | TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) |
| #define | TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk |
| #define | TAMP_CR3_ITAMP6NOER_Pos (5U) |
| #define | TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) |
| #define | TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk |
| #define | TAMP_CR3_ITAMP7NOER_Pos (6U) |
| #define | TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) |
| #define | TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk |
| #define | TAMP_CR3_ITAMP8NOER_Pos (7U) |
| #define | TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) |
| #define | TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk |
| #define | TAMP_CR3_ITAMP9NOER_Pos (8U) |
| #define | TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) |
| #define | TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk |
| #define | TAMP_CR3_ITAMP11NOER_Pos (10U) |
| #define | TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) |
| #define | TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk |
| #define | TAMP_CR3_ITAMP12NOER_Pos (11U) |
| #define | TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) |
| #define | TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk |
| #define | TAMP_CR3_ITAMP13NOER_Pos (12U) |
| #define | TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) |
| #define | TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk |
| #define | TAMP_FLTCR_TAMPFREQ_Pos (0U) |
| #define | TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) |
| #define | TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk |
| #define | TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) |
| #define | TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) |
| #define | TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) |
| #define | TAMP_FLTCR_TAMPFLT_Pos (3U) |
| #define | TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) |
| #define | TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk |
| #define | TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) |
| #define | TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) |
| #define | TAMP_FLTCR_TAMPPRCH_Pos (5U) |
| #define | TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) |
| #define | TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk |
| #define | TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) |
| #define | TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) |
| #define | TAMP_FLTCR_TAMPPUDIS_Pos (7U) |
| #define | TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) |
| #define | TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk |
| #define | TAMP_ATCR1_TAMP1AM_Pos (0U) |
| #define | TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) |
| #define | TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk |
| #define | TAMP_ATCR1_TAMP2AM_Pos (1U) |
| #define | TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) |
| #define | TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk |
| #define | TAMP_ATCR1_TAMP3AM_Pos (2U) |
| #define | TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) |
| #define | TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk |
| #define | TAMP_ATCR1_TAMP4AM_Pos (3U) |
| #define | TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) |
| #define | TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk |
| #define | TAMP_ATCR1_TAMP5AM_Pos (4U) |
| #define | TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) |
| #define | TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk |
| #define | TAMP_ATCR1_TAMP6AM_Pos (5U) |
| #define | TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) |
| #define | TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk |
| #define | TAMP_ATCR1_TAMP7AM_Pos (6U) |
| #define | TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) |
| #define | TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk |
| #define | TAMP_ATCR1_TAMP8AM_Pos (7U) |
| #define | TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) |
| #define | TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk |
| #define | TAMP_ATCR1_ATOSEL1_Pos (8U) |
| #define | TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) |
| #define | TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk |
| #define | TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) |
| #define | TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) |
| #define | TAMP_ATCR1_ATOSEL2_Pos (10U) |
| #define | TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) |
| #define | TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk |
| #define | TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) |
| #define | TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) |
| #define | TAMP_ATCR1_ATOSEL3_Pos (12U) |
| #define | TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) |
| #define | TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk |
| #define | TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) |
| #define | TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) |
| #define | TAMP_ATCR1_ATOSEL4_Pos (14U) |
| #define | TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) |
| #define | TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk |
| #define | TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) |
| #define | TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) |
| #define | TAMP_ATCR1_ATCKSEL_Pos (16U) |
| #define | TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) |
| #define | TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk |
| #define | TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) |
| #define | TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) |
| #define | TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) |
| #define | TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) |
| #define | TAMP_ATCR1_ATPER_Pos (24U) |
| #define | TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) |
| #define | TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk |
| #define | TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) |
| #define | TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) |
| #define | TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) |
| #define | TAMP_ATCR1_ATOSHARE_Pos (30U) |
| #define | TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) |
| #define | TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk |
| #define | TAMP_ATCR1_FLTEN_Pos (31U) |
| #define | TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) |
| #define | TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk |
| #define | TAMP_ATSEEDR_SEED_Pos (0U) |
| #define | TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) |
| #define | TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk |
| #define | TAMP_ATOR_PRNG_Pos (0U) |
| #define | TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) |
| #define | TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk |
| #define | TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) |
| #define | TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) |
| #define | TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) |
| #define | TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) |
| #define | TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) |
| #define | TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) |
| #define | TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) |
| #define | TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) |
| #define | TAMP_ATOR_SEEDF_Pos (14U) |
| #define | TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) |
| #define | TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk |
| #define | TAMP_ATOR_INITS_Pos (15U) |
| #define | TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) |
| #define | TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk |
| #define | TAMP_ATCR2_ATOSEL1_Pos (8U) |
| #define | TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) |
| #define | TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk |
| #define | TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) |
| #define | TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) |
| #define | TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) |
| #define | TAMP_ATCR2_ATOSEL2_Pos (11U) |
| #define | TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) |
| #define | TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk |
| #define | TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) |
| #define | TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) |
| #define | TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) |
| #define | TAMP_ATCR2_ATOSEL3_Pos (14U) |
| #define | TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) |
| #define | TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk |
| #define | TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) |
| #define | TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) |
| #define | TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) |
| #define | TAMP_ATCR2_ATOSEL4_Pos (17U) |
| #define | TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) |
| #define | TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk |
| #define | TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) |
| #define | TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) |
| #define | TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) |
| #define | TAMP_ATCR2_ATOSEL5_Pos (20U) |
| #define | TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) |
| #define | TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk |
| #define | TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) |
| #define | TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) |
| #define | TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) |
| #define | TAMP_ATCR2_ATOSEL6_Pos (23U) |
| #define | TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) |
| #define | TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk |
| #define | TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) |
| #define | TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) |
| #define | TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) |
| #define | TAMP_ATCR2_ATOSEL7_Pos (26U) |
| #define | TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) |
| #define | TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk |
| #define | TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) |
| #define | TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) |
| #define | TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) |
| #define | TAMP_ATCR2_ATOSEL8_Pos (29U) |
| #define | TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) |
| #define | TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk |
| #define | TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) |
| #define | TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) |
| #define | TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) |
| #define | TAMP_SECCFGR_BKPRWSEC_Pos (0U) |
| #define | TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk |
| #define | TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) |
| #define | TAMP_SECCFGR_CNT1SEC_Pos (15U) |
| #define | TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) |
| #define | TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk |
| #define | TAMP_SECCFGR_BKPWSEC_Pos (16U) |
| #define | TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk |
| #define | TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) |
| #define | TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) |
| #define | TAMP_SECCFGR_BHKLOCK_Pos (30U) |
| #define | TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) |
| #define | TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk |
| #define | TAMP_SECCFGR_TAMPSEC_Pos (31U) |
| #define | TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) |
| #define | TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk |
| #define | TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) |
| #define | TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) |
| #define | TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk |
| #define | TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) |
| #define | TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) |
| #define | TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk |
| #define | TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) |
| #define | TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) |
| #define | TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk |
| #define | TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) |
| #define | TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) |
| #define | TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk |
| #define | TAMP_IER_TAMP1IE_Pos (0U) |
| #define | TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) |
| #define | TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk |
| #define | TAMP_IER_TAMP2IE_Pos (1U) |
| #define | TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) |
| #define | TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk |
| #define | TAMP_IER_TAMP3IE_Pos (2U) |
| #define | TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) |
| #define | TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk |
| #define | TAMP_IER_TAMP4IE_Pos (3U) |
| #define | TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) |
| #define | TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk |
| #define | TAMP_IER_TAMP5IE_Pos (4U) |
| #define | TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) |
| #define | TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk |
| #define | TAMP_IER_TAMP6IE_Pos (5U) |
| #define | TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) |
| #define | TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk |
| #define | TAMP_IER_TAMP7IE_Pos (6U) |
| #define | TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) |
| #define | TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk |
| #define | TAMP_IER_TAMP8IE_Pos (7U) |
| #define | TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) |
| #define | TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk |
| #define | TAMP_IER_ITAMP1IE_Pos (16U) |
| #define | TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) |
| #define | TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk |
| #define | TAMP_IER_ITAMP2IE_Pos (17U) |
| #define | TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) |
| #define | TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk |
| #define | TAMP_IER_ITAMP3IE_Pos (18U) |
| #define | TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) |
| #define | TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk |
| #define | TAMP_IER_ITAMP5IE_Pos (20U) |
| #define | TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) |
| #define | TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk |
| #define | TAMP_IER_ITAMP6IE_Pos (21U) |
| #define | TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) |
| #define | TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk |
| #define | TAMP_IER_ITAMP7IE_Pos (22U) |
| #define | TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) |
| #define | TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk |
| #define | TAMP_IER_ITAMP8IE_Pos (23U) |
| #define | TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) |
| #define | TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk |
| #define | TAMP_IER_ITAMP9IE_Pos (24U) |
| #define | TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) |
| #define | TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk |
| #define | TAMP_IER_ITAMP11IE_Pos (26U) |
| #define | TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) |
| #define | TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk |
| #define | TAMP_IER_ITAMP12IE_Pos (27U) |
| #define | TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) |
| #define | TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk |
| #define | TAMP_IER_ITAMP13IE_Pos (28U) |
| #define | TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) |
| #define | TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk |
| #define | TAMP_SR_TAMP1F_Pos (0U) |
| #define | TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) |
| #define | TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk |
| #define | TAMP_SR_TAMP2F_Pos (1U) |
| #define | TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) |
| #define | TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk |
| #define | TAMP_SR_TAMP3F_Pos (2U) |
| #define | TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) |
| #define | TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk |
| #define | TAMP_SR_TAMP4F_Pos (3U) |
| #define | TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) |
| #define | TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk |
| #define | TAMP_SR_TAMP5F_Pos (4U) |
| #define | TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) |
| #define | TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk |
| #define | TAMP_SR_TAMP6F_Pos (5U) |
| #define | TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) |
| #define | TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk |
| #define | TAMP_SR_TAMP7F_Pos (6U) |
| #define | TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) |
| #define | TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk |
| #define | TAMP_SR_TAMP8F_Pos (7U) |
| #define | TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) |
| #define | TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk |
| #define | TAMP_SR_ITAMP1F_Pos (16U) |
| #define | TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) |
| #define | TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk |
| #define | TAMP_SR_ITAMP2F_Pos (17U) |
| #define | TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) |
| #define | TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk |
| #define | TAMP_SR_ITAMP3F_Pos (18U) |
| #define | TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) |
| #define | TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk |
| #define | TAMP_SR_ITAMP5F_Pos (20U) |
| #define | TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) |
| #define | TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk |
| #define | TAMP_SR_ITAMP6F_Pos (21U) |
| #define | TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) |
| #define | TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk |
| #define | TAMP_SR_ITAMP7F_Pos (22U) |
| #define | TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) |
| #define | TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk |
| #define | TAMP_SR_ITAMP8F_Pos (23U) |
| #define | TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) |
| #define | TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk |
| #define | TAMP_SR_ITAMP9F_Pos (24U) |
| #define | TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) |
| #define | TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk |
| #define | TAMP_SR_ITAMP11F_Pos (26U) |
| #define | TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) |
| #define | TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk |
| #define | TAMP_SR_ITAMP12F_Pos (27U) |
| #define | TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) |
| #define | TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk |
| #define | TAMP_SR_ITAMP13F_Pos (28U) |
| #define | TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) |
| #define | TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk |
| #define | TAMP_MISR_TAMP1MF_Pos (0U) |
| #define | TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) |
| #define | TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk |
| #define | TAMP_MISR_TAMP2MF_Pos (1U) |
| #define | TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) |
| #define | TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk |
| #define | TAMP_MISR_TAMP3MF_Pos (2U) |
| #define | TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) |
| #define | TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk |
| #define | TAMP_MISR_TAMP4MF_Pos (3U) |
| #define | TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) |
| #define | TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk |
| #define | TAMP_MISR_TAMP5MF_Pos (4U) |
| #define | TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) |
| #define | TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk |
| #define | TAMP_MISR_TAMP6MF_Pos (5U) |
| #define | TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) |
| #define | TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk |
| #define | TAMP_MISR_TAMP7MF_Pos (6U) |
| #define | TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) |
| #define | TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk |
| #define | TAMP_MISR_TAMP8MF_Pos (7U) |
| #define | TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) |
| #define | TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk |
| #define | TAMP_MISR_ITAMP1MF_Pos (16U) |
| #define | TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) |
| #define | TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk |
| #define | TAMP_MISR_ITAMP2MF_Pos (17U) |
| #define | TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) |
| #define | TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk |
| #define | TAMP_MISR_ITAMP3MF_Pos (18U) |
| #define | TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) |
| #define | TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk |
| #define | TAMP_MISR_ITAMP5MF_Pos (20U) |
| #define | TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) |
| #define | TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk |
| #define | TAMP_MISR_ITAMP6MF_Pos (21U) |
| #define | TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) |
| #define | TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk |
| #define | TAMP_MISR_ITAMP7MF_Pos (22U) |
| #define | TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) |
| #define | TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk |
| #define | TAMP_MISR_ITAMP8MF_Pos (23U) |
| #define | TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) |
| #define | TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk |
| #define | TAMP_MISR_ITAMP9MF_Pos (24U) |
| #define | TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) |
| #define | TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk |
| #define | TAMP_MISR_ITAMP11MF_Pos (26U) |
| #define | TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) |
| #define | TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk |
| #define | TAMP_MISR_ITAMP12MF_Pos (27U) |
| #define | TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) |
| #define | TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk |
| #define | TAMP_MISR_ITAMP13MF_Pos (28U) |
| #define | TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) |
| #define | TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk |
| #define | TAMP_SMISR_TAMP1MF_Pos (0U) |
| #define | TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) |
| #define | TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk |
| #define | TAMP_SMISR_TAMP2MF_Pos (1U) |
| #define | TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) |
| #define | TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk |
| #define | TAMP_SMISR_TAMP3MF_Pos (2U) |
| #define | TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) |
| #define | TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk |
| #define | TAMP_SMISR_TAMP4MF_Pos (3U) |
| #define | TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) |
| #define | TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk |
| #define | TAMP_SMISR_TAMP5MF_Pos (4U) |
| #define | TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) |
| #define | TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk |
| #define | TAMP_SMISR_TAMP6MF_Pos (5U) |
| #define | TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) |
| #define | TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk |
| #define | TAMP_SMISR_TAMP7MF_Pos (6U) |
| #define | TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) |
| #define | TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk |
| #define | TAMP_SMISR_TAMP8MF_Pos (7U) |
| #define | TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) |
| #define | TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk |
| #define | TAMP_SMISR_ITAMP1MF_Pos (16U) |
| #define | TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) |
| #define | TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk |
| #define | TAMP_SMISR_ITAMP2MF_Pos (17U) |
| #define | TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) |
| #define | TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk |
| #define | TAMP_SMISR_ITAMP3MF_Pos (18U) |
| #define | TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) |
| #define | TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk |
| #define | TAMP_SMISR_ITAMP5MF_Pos (20U) |
| #define | TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) |
| #define | TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk |
| #define | TAMP_SMISR_ITAMP6MF_Pos (21U) |
| #define | TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) |
| #define | TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk |
| #define | TAMP_SMISR_ITAMP7MF_Pos (22U) |
| #define | TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) |
| #define | TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk |
| #define | TAMP_SMISR_ITAMP8MF_Pos (23U) |
| #define | TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) |
| #define | TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk |
| #define | TAMP_SMISR_ITAMP9MF_Pos (24U) |
| #define | TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) |
| #define | TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk |
| #define | TAMP_SMISR_ITAMP11MF_Pos (26U) |
| #define | TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) |
| #define | TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk |
| #define | TAMP_SMISR_ITAMP12MF_Pos (27U) |
| #define | TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) |
| #define | TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk |
| #define | TAMP_SMISR_ITAMP13MF_Pos (28U) |
| #define | TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) |
| #define | TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk |
| #define | TAMP_SCR_CTAMP1F_Pos (0U) |
| #define | TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) |
| #define | TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk |
| #define | TAMP_SCR_CTAMP2F_Pos (1U) |
| #define | TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) |
| #define | TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk |
| #define | TAMP_SCR_CTAMP3F_Pos (2U) |
| #define | TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) |
| #define | TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk |
| #define | TAMP_SCR_CTAMP4F_Pos (3U) |
| #define | TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) |
| #define | TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk |
| #define | TAMP_SCR_CTAMP5F_Pos (4U) |
| #define | TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) |
| #define | TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk |
| #define | TAMP_SCR_CTAMP6F_Pos (5U) |
| #define | TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) |
| #define | TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk |
| #define | TAMP_SCR_CTAMP7F_Pos (6U) |
| #define | TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) |
| #define | TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk |
| #define | TAMP_SCR_CTAMP8F_Pos (7U) |
| #define | TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) |
| #define | TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk |
| #define | TAMP_SCR_CITAMP1F_Pos (16U) |
| #define | TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) |
| #define | TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk |
| #define | TAMP_SCR_CITAMP2F_Pos (17U) |
| #define | TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) |
| #define | TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk |
| #define | TAMP_SCR_CITAMP3F_Pos (18U) |
| #define | TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) |
| #define | TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk |
| #define | TAMP_SCR_CITAMP5F_Pos (20U) |
| #define | TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) |
| #define | TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk |
| #define | TAMP_SCR_CITAMP6F_Pos (21U) |
| #define | TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) |
| #define | TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk |
| #define | TAMP_SCR_CITAMP7F_Pos (22U) |
| #define | TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) |
| #define | TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk |
| #define | TAMP_SCR_CITAMP8F_Pos (23U) |
| #define | TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) |
| #define | TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk |
| #define | TAMP_SCR_CITAMP9F_Pos (24U) |
| #define | TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) |
| #define | TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk |
| #define | TAMP_SCR_CITAMP11F_Pos (26U) |
| #define | TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) |
| #define | TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk |
| #define | TAMP_SCR_CITAMP12F_Pos (27U) |
| #define | TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) |
| #define | TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk |
| #define | TAMP_SCR_CITAMP13F_Pos (28U) |
| #define | TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) |
| #define | TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk |
| #define | TAMP_COUNTR_Pos (16U) |
| #define | TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) |
| #define | TAMP_COUNTR TAMP_COUNTR_Msk |
| #define | TAMP_ERCFGR0_Pos (0U) |
| #define | TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) |
| #define | TAMP_ERCFGR0 TAMP_ERCFGR0_Msk |
| #define | TAMP_BKP0R_Pos (0U) |
| #define | TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) |
| #define | TAMP_BKP0R TAMP_BKP0R_Msk |
| #define | TAMP_BKP1R_Pos (0U) |
| #define | TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) |
| #define | TAMP_BKP1R TAMP_BKP1R_Msk |
| #define | TAMP_BKP2R_Pos (0U) |
| #define | TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) |
| #define | TAMP_BKP2R TAMP_BKP2R_Msk |
| #define | TAMP_BKP3R_Pos (0U) |
| #define | TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) |
| #define | TAMP_BKP3R TAMP_BKP3R_Msk |
| #define | TAMP_BKP4R_Pos (0U) |
| #define | TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) |
| #define | TAMP_BKP4R TAMP_BKP4R_Msk |
| #define | TAMP_BKP5R_Pos (0U) |
| #define | TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) |
| #define | TAMP_BKP5R TAMP_BKP5R_Msk |
| #define | TAMP_BKP6R_Pos (0U) |
| #define | TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) |
| #define | TAMP_BKP6R TAMP_BKP6R_Msk |
| #define | TAMP_BKP7R_Pos (0U) |
| #define | TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) |
| #define | TAMP_BKP7R TAMP_BKP7R_Msk |
| #define | TAMP_BKP8R_Pos (0U) |
| #define | TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) |
| #define | TAMP_BKP8R TAMP_BKP8R_Msk |
| #define | TAMP_BKP9R_Pos (0U) |
| #define | TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) |
| #define | TAMP_BKP9R TAMP_BKP9R_Msk |
| #define | TAMP_BKP10R_Pos (0U) |
| #define | TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) |
| #define | TAMP_BKP10R TAMP_BKP10R_Msk |
| #define | TAMP_BKP11R_Pos (0U) |
| #define | TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) |
| #define | TAMP_BKP11R TAMP_BKP11R_Msk |
| #define | TAMP_BKP12R_Pos (0U) |
| #define | TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) |
| #define | TAMP_BKP12R TAMP_BKP12R_Msk |
| #define | TAMP_BKP13R_Pos (0U) |
| #define | TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) |
| #define | TAMP_BKP13R TAMP_BKP13R_Msk |
| #define | TAMP_BKP14R_Pos (0U) |
| #define | TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) |
| #define | TAMP_BKP14R TAMP_BKP14R_Msk |
| #define | TAMP_BKP15R_Pos (0U) |
| #define | TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) |
| #define | TAMP_BKP15R TAMP_BKP15R_Msk |
| #define | TAMP_BKP16R_Pos (0U) |
| #define | TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) |
| #define | TAMP_BKP16R TAMP_BKP16R_Msk |
| #define | TAMP_BKP17R_Pos (0U) |
| #define | TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) |
| #define | TAMP_BKP17R TAMP_BKP17R_Msk |
| #define | TAMP_BKP18R_Pos (0U) |
| #define | TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) |
| #define | TAMP_BKP18R TAMP_BKP18R_Msk |
| #define | TAMP_BKP19R_Pos (0U) |
| #define | TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) |
| #define | TAMP_BKP19R TAMP_BKP19R_Msk |
| #define | TAMP_BKP20R_Pos (0U) |
| #define | TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) |
| #define | TAMP_BKP20R TAMP_BKP20R_Msk |
| #define | TAMP_BKP21R_Pos (0U) |
| #define | TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) |
| #define | TAMP_BKP21R TAMP_BKP21R_Msk |
| #define | TAMP_BKP22R_Pos (0U) |
| #define | TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) |
| #define | TAMP_BKP22R TAMP_BKP22R_Msk |
| #define | TAMP_BKP23R_Pos (0U) |
| #define | TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) |
| #define | TAMP_BKP23R TAMP_BKP23R_Msk |
| #define | TAMP_BKP24R_Pos (0U) |
| #define | TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) |
| #define | TAMP_BKP24R TAMP_BKP24R_Msk |
| #define | TAMP_BKP25R_Pos (0U) |
| #define | TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) |
| #define | TAMP_BKP25R TAMP_BKP25R_Msk |
| #define | TAMP_BKP26R_Pos (0U) |
| #define | TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) |
| #define | TAMP_BKP26R TAMP_BKP26R_Msk |
| #define | TAMP_BKP27R_Pos (0U) |
| #define | TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) |
| #define | TAMP_BKP27R TAMP_BKP27R_Msk |
| #define | TAMP_BKP28R_Pos (0U) |
| #define | TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) |
| #define | TAMP_BKP28R TAMP_BKP28R_Msk |
| #define | TAMP_BKP29R_Pos (0U) |
| #define | TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) |
| #define | TAMP_BKP29R TAMP_BKP29R_Msk |
| #define | TAMP_BKP30R_Pos (0U) |
| #define | TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) |
| #define | TAMP_BKP30R TAMP_BKP30R_Msk |
| #define | TAMP_BKP31R_Pos (0U) |
| #define | TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) |
| #define | TAMP_BKP31R TAMP_BKP31R_Msk |
| #define | TSC_CR_TSCE_Pos (0U) |
| #define | TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) |
| #define | TSC_CR_TSCE TSC_CR_TSCE_Msk |
| #define | TSC_CR_START_Pos (1U) |
| #define | TSC_CR_START_Msk (0x1UL << TSC_CR_START_Pos) |
| #define | TSC_CR_START TSC_CR_START_Msk |
| #define | TSC_CR_AM_Pos (2U) |
| #define | TSC_CR_AM_Msk (0x1UL << TSC_CR_AM_Pos) |
| #define | TSC_CR_AM TSC_CR_AM_Msk |
| #define | TSC_CR_SYNCPOL_Pos (3U) |
| #define | TSC_CR_SYNCPOL_Msk (0x1UL << TSC_CR_SYNCPOL_Pos) |
| #define | TSC_CR_SYNCPOL TSC_CR_SYNCPOL_Msk |
| #define | TSC_CR_IODEF_Pos (4U) |
| #define | TSC_CR_IODEF_Msk (0x1UL << TSC_CR_IODEF_Pos) |
| #define | TSC_CR_IODEF TSC_CR_IODEF_Msk |
| #define | TSC_CR_MCV_Pos (5U) |
| #define | TSC_CR_MCV_Msk (0x7UL << TSC_CR_MCV_Pos) |
| #define | TSC_CR_MCV TSC_CR_MCV_Msk |
| #define | TSC_CR_MCV_0 (0x1UL << TSC_CR_MCV_Pos) |
| #define | TSC_CR_MCV_1 (0x2UL << TSC_CR_MCV_Pos) |
| #define | TSC_CR_MCV_2 (0x4UL << TSC_CR_MCV_Pos) |
| #define | TSC_CR_PGPSC_Pos (12U) |
| #define | TSC_CR_PGPSC_Msk (0x7UL << TSC_CR_PGPSC_Pos) |
| #define | TSC_CR_PGPSC TSC_CR_PGPSC_Msk |
| #define | TSC_CR_PGPSC_0 (0x1UL << TSC_CR_PGPSC_Pos) |
| #define | TSC_CR_PGPSC_1 (0x2UL << TSC_CR_PGPSC_Pos) |
| #define | TSC_CR_PGPSC_2 (0x4UL << TSC_CR_PGPSC_Pos) |
| #define | TSC_CR_SSPSC_Pos (15U) |
| #define | TSC_CR_SSPSC_Msk (0x1UL << TSC_CR_SSPSC_Pos) |
| #define | TSC_CR_SSPSC TSC_CR_SSPSC_Msk |
| #define | TSC_CR_SSE_Pos (16U) |
| #define | TSC_CR_SSE_Msk (0x1UL << TSC_CR_SSE_Pos) |
| #define | TSC_CR_SSE TSC_CR_SSE_Msk |
| #define | TSC_CR_SSD_Pos (17U) |
| #define | TSC_CR_SSD_Msk (0x7FUL << TSC_CR_SSD_Pos) |
| #define | TSC_CR_SSD TSC_CR_SSD_Msk |
| #define | TSC_CR_SSD_0 (0x01UL << TSC_CR_SSD_Pos) |
| #define | TSC_CR_SSD_1 (0x02UL << TSC_CR_SSD_Pos) |
| #define | TSC_CR_SSD_2 (0x04UL << TSC_CR_SSD_Pos) |
| #define | TSC_CR_SSD_3 (0x08UL << TSC_CR_SSD_Pos) |
| #define | TSC_CR_SSD_4 (0x10UL << TSC_CR_SSD_Pos) |
| #define | TSC_CR_SSD_5 (0x20UL << TSC_CR_SSD_Pos) |
| #define | TSC_CR_SSD_6 (0x40UL << TSC_CR_SSD_Pos) |
| #define | TSC_CR_CTPL_Pos (24U) |
| #define | TSC_CR_CTPL_Msk (0xFUL << TSC_CR_CTPL_Pos) |
| #define | TSC_CR_CTPL TSC_CR_CTPL_Msk |
| #define | TSC_CR_CTPL_0 (0x1UL << TSC_CR_CTPL_Pos) |
| #define | TSC_CR_CTPL_1 (0x2UL << TSC_CR_CTPL_Pos) |
| #define | TSC_CR_CTPL_2 (0x4UL << TSC_CR_CTPL_Pos) |
| #define | TSC_CR_CTPL_3 (0x8UL << TSC_CR_CTPL_Pos) |
| #define | TSC_CR_CTPH_Pos (28U) |
| #define | TSC_CR_CTPH_Msk (0xFUL << TSC_CR_CTPH_Pos) |
| #define | TSC_CR_CTPH TSC_CR_CTPH_Msk |
| #define | TSC_CR_CTPH_0 (0x1UL << TSC_CR_CTPH_Pos) |
| #define | TSC_CR_CTPH_1 (0x2UL << TSC_CR_CTPH_Pos) |
| #define | TSC_CR_CTPH_2 (0x4UL << TSC_CR_CTPH_Pos) |
| #define | TSC_CR_CTPH_3 (0x8UL << TSC_CR_CTPH_Pos) |
| #define | TSC_IER_EOAIE_Pos (0U) |
| #define | TSC_IER_EOAIE_Msk (0x1UL << TSC_IER_EOAIE_Pos) |
| #define | TSC_IER_EOAIE TSC_IER_EOAIE_Msk |
| #define | TSC_IER_MCEIE_Pos (1U) |
| #define | TSC_IER_MCEIE_Msk (0x1UL << TSC_IER_MCEIE_Pos) |
| #define | TSC_IER_MCEIE TSC_IER_MCEIE_Msk |
| #define | TSC_ICR_EOAIC_Pos (0U) |
| #define | TSC_ICR_EOAIC_Msk (0x1UL << TSC_ICR_EOAIC_Pos) |
| #define | TSC_ICR_EOAIC TSC_ICR_EOAIC_Msk |
| #define | TSC_ICR_MCEIC_Pos (1U) |
| #define | TSC_ICR_MCEIC_Msk (0x1UL << TSC_ICR_MCEIC_Pos) |
| #define | TSC_ICR_MCEIC TSC_ICR_MCEIC_Msk |
| #define | TSC_ISR_EOAF_Pos (0U) |
| #define | TSC_ISR_EOAF_Msk (0x1UL << TSC_ISR_EOAF_Pos) |
| #define | TSC_ISR_EOAF TSC_ISR_EOAF_Msk |
| #define | TSC_ISR_MCEF_Pos (1U) |
| #define | TSC_ISR_MCEF_Msk (0x1UL << TSC_ISR_MCEF_Pos) |
| #define | TSC_ISR_MCEF TSC_ISR_MCEF_Msk |
| #define | TSC_IOHCR_G1_IO1_Pos (0U) |
| #define | TSC_IOHCR_G1_IO1_Msk (0x1UL << TSC_IOHCR_G1_IO1_Pos) |
| #define | TSC_IOHCR_G1_IO1 TSC_IOHCR_G1_IO1_Msk |
| #define | TSC_IOHCR_G1_IO2_Pos (1U) |
| #define | TSC_IOHCR_G1_IO2_Msk (0x1UL << TSC_IOHCR_G1_IO2_Pos) |
| #define | TSC_IOHCR_G1_IO2 TSC_IOHCR_G1_IO2_Msk |
| #define | TSC_IOHCR_G1_IO3_Pos (2U) |
| #define | TSC_IOHCR_G1_IO3_Msk (0x1UL << TSC_IOHCR_G1_IO3_Pos) |
| #define | TSC_IOHCR_G1_IO3 TSC_IOHCR_G1_IO3_Msk |
| #define | TSC_IOHCR_G1_IO4_Pos (3U) |
| #define | TSC_IOHCR_G1_IO4_Msk (0x1UL << TSC_IOHCR_G1_IO4_Pos) |
| #define | TSC_IOHCR_G1_IO4 TSC_IOHCR_G1_IO4_Msk |
| #define | TSC_IOHCR_G2_IO1_Pos (4U) |
| #define | TSC_IOHCR_G2_IO1_Msk (0x1UL << TSC_IOHCR_G2_IO1_Pos) |
| #define | TSC_IOHCR_G2_IO1 TSC_IOHCR_G2_IO1_Msk |
| #define | TSC_IOHCR_G2_IO2_Pos (5U) |
| #define | TSC_IOHCR_G2_IO2_Msk (0x1UL << TSC_IOHCR_G2_IO2_Pos) |
| #define | TSC_IOHCR_G2_IO2 TSC_IOHCR_G2_IO2_Msk |
| #define | TSC_IOHCR_G2_IO3_Pos (6U) |
| #define | TSC_IOHCR_G2_IO3_Msk (0x1UL << TSC_IOHCR_G2_IO3_Pos) |
| #define | TSC_IOHCR_G2_IO3 TSC_IOHCR_G2_IO3_Msk |
| #define | TSC_IOHCR_G2_IO4_Pos (7U) |
| #define | TSC_IOHCR_G2_IO4_Msk (0x1UL << TSC_IOHCR_G2_IO4_Pos) |
| #define | TSC_IOHCR_G2_IO4 TSC_IOHCR_G2_IO4_Msk |
| #define | TSC_IOHCR_G3_IO1_Pos (8U) |
| #define | TSC_IOHCR_G3_IO1_Msk (0x1UL << TSC_IOHCR_G3_IO1_Pos) |
| #define | TSC_IOHCR_G3_IO1 TSC_IOHCR_G3_IO1_Msk |
| #define | TSC_IOHCR_G3_IO2_Pos (9U) |
| #define | TSC_IOHCR_G3_IO2_Msk (0x1UL << TSC_IOHCR_G3_IO2_Pos) |
| #define | TSC_IOHCR_G3_IO2 TSC_IOHCR_G3_IO2_Msk |
| #define | TSC_IOHCR_G3_IO3_Pos (10U) |
| #define | TSC_IOHCR_G3_IO3_Msk (0x1UL << TSC_IOHCR_G3_IO3_Pos) |
| #define | TSC_IOHCR_G3_IO3 TSC_IOHCR_G3_IO3_Msk |
| #define | TSC_IOHCR_G3_IO4_Pos (11U) |
| #define | TSC_IOHCR_G3_IO4_Msk (0x1UL << TSC_IOHCR_G3_IO4_Pos) |
| #define | TSC_IOHCR_G3_IO4 TSC_IOHCR_G3_IO4_Msk |
| #define | TSC_IOHCR_G4_IO1_Pos (12U) |
| #define | TSC_IOHCR_G4_IO1_Msk (0x1UL << TSC_IOHCR_G4_IO1_Pos) |
| #define | TSC_IOHCR_G4_IO1 TSC_IOHCR_G4_IO1_Msk |
| #define | TSC_IOHCR_G4_IO2_Pos (13U) |
| #define | TSC_IOHCR_G4_IO2_Msk (0x1UL << TSC_IOHCR_G4_IO2_Pos) |
| #define | TSC_IOHCR_G4_IO2 TSC_IOHCR_G4_IO2_Msk |
| #define | TSC_IOHCR_G4_IO3_Pos (14U) |
| #define | TSC_IOHCR_G4_IO3_Msk (0x1UL << TSC_IOHCR_G4_IO3_Pos) |
| #define | TSC_IOHCR_G4_IO3 TSC_IOHCR_G4_IO3_Msk |
| #define | TSC_IOHCR_G4_IO4_Pos (15U) |
| #define | TSC_IOHCR_G4_IO4_Msk (0x1UL << TSC_IOHCR_G4_IO4_Pos) |
| #define | TSC_IOHCR_G4_IO4 TSC_IOHCR_G4_IO4_Msk |
| #define | TSC_IOHCR_G5_IO1_Pos (16U) |
| #define | TSC_IOHCR_G5_IO1_Msk (0x1UL << TSC_IOHCR_G5_IO1_Pos) |
| #define | TSC_IOHCR_G5_IO1 TSC_IOHCR_G5_IO1_Msk |
| #define | TSC_IOHCR_G5_IO2_Pos (17U) |
| #define | TSC_IOHCR_G5_IO2_Msk (0x1UL << TSC_IOHCR_G5_IO2_Pos) |
| #define | TSC_IOHCR_G5_IO2 TSC_IOHCR_G5_IO2_Msk |
| #define | TSC_IOHCR_G5_IO3_Pos (18U) |
| #define | TSC_IOHCR_G5_IO3_Msk (0x1UL << TSC_IOHCR_G5_IO3_Pos) |
| #define | TSC_IOHCR_G5_IO3 TSC_IOHCR_G5_IO3_Msk |
| #define | TSC_IOHCR_G5_IO4_Pos (19U) |
| #define | TSC_IOHCR_G5_IO4_Msk (0x1UL << TSC_IOHCR_G5_IO4_Pos) |
| #define | TSC_IOHCR_G5_IO4 TSC_IOHCR_G5_IO4_Msk |
| #define | TSC_IOHCR_G6_IO1_Pos (20U) |
| #define | TSC_IOHCR_G6_IO1_Msk (0x1UL << TSC_IOHCR_G6_IO1_Pos) |
| #define | TSC_IOHCR_G6_IO1 TSC_IOHCR_G6_IO1_Msk |
| #define | TSC_IOHCR_G6_IO2_Pos (21U) |
| #define | TSC_IOHCR_G6_IO2_Msk (0x1UL << TSC_IOHCR_G6_IO2_Pos) |
| #define | TSC_IOHCR_G6_IO2 TSC_IOHCR_G6_IO2_Msk |
| #define | TSC_IOHCR_G6_IO3_Pos (22U) |
| #define | TSC_IOHCR_G6_IO3_Msk (0x1UL << TSC_IOHCR_G6_IO3_Pos) |
| #define | TSC_IOHCR_G6_IO3 TSC_IOHCR_G6_IO3_Msk |
| #define | TSC_IOHCR_G6_IO4_Pos (23U) |
| #define | TSC_IOHCR_G6_IO4_Msk (0x1UL << TSC_IOHCR_G6_IO4_Pos) |
| #define | TSC_IOHCR_G6_IO4 TSC_IOHCR_G6_IO4_Msk |
| #define | TSC_IOHCR_G7_IO1_Pos (24U) |
| #define | TSC_IOHCR_G7_IO1_Msk (0x1UL << TSC_IOHCR_G7_IO1_Pos) |
| #define | TSC_IOHCR_G7_IO1 TSC_IOHCR_G7_IO1_Msk |
| #define | TSC_IOHCR_G7_IO2_Pos (25U) |
| #define | TSC_IOHCR_G7_IO2_Msk (0x1UL << TSC_IOHCR_G7_IO2_Pos) |
| #define | TSC_IOHCR_G7_IO2 TSC_IOHCR_G7_IO2_Msk |
| #define | TSC_IOHCR_G7_IO3_Pos (26U) |
| #define | TSC_IOHCR_G7_IO3_Msk (0x1UL << TSC_IOHCR_G7_IO3_Pos) |
| #define | TSC_IOHCR_G7_IO3 TSC_IOHCR_G7_IO3_Msk |
| #define | TSC_IOHCR_G7_IO4_Pos (27U) |
| #define | TSC_IOHCR_G7_IO4_Msk (0x1UL << TSC_IOHCR_G7_IO4_Pos) |
| #define | TSC_IOHCR_G7_IO4 TSC_IOHCR_G7_IO4_Msk |
| #define | TSC_IOHCR_G8_IO1_Pos (28U) |
| #define | TSC_IOHCR_G8_IO1_Msk (0x1UL << TSC_IOHCR_G8_IO1_Pos) |
| #define | TSC_IOHCR_G8_IO1 TSC_IOHCR_G8_IO1_Msk |
| #define | TSC_IOHCR_G8_IO2_Pos (29U) |
| #define | TSC_IOHCR_G8_IO2_Msk (0x1UL << TSC_IOHCR_G8_IO2_Pos) |
| #define | TSC_IOHCR_G8_IO2 TSC_IOHCR_G8_IO2_Msk |
| #define | TSC_IOHCR_G8_IO3_Pos (30U) |
| #define | TSC_IOHCR_G8_IO3_Msk (0x1UL << TSC_IOHCR_G8_IO3_Pos) |
| #define | TSC_IOHCR_G8_IO3 TSC_IOHCR_G8_IO3_Msk |
| #define | TSC_IOHCR_G8_IO4_Pos (31U) |
| #define | TSC_IOHCR_G8_IO4_Msk (0x1UL << TSC_IOHCR_G8_IO4_Pos) |
| #define | TSC_IOHCR_G8_IO4 TSC_IOHCR_G8_IO4_Msk |
| #define | TSC_IOASCR_G1_IO1_Pos (0U) |
| #define | TSC_IOASCR_G1_IO1_Msk (0x1UL << TSC_IOASCR_G1_IO1_Pos) |
| #define | TSC_IOASCR_G1_IO1 TSC_IOASCR_G1_IO1_Msk |
| #define | TSC_IOASCR_G1_IO2_Pos (1U) |
| #define | TSC_IOASCR_G1_IO2_Msk (0x1UL << TSC_IOASCR_G1_IO2_Pos) |
| #define | TSC_IOASCR_G1_IO2 TSC_IOASCR_G1_IO2_Msk |
| #define | TSC_IOASCR_G1_IO3_Pos (2U) |
| #define | TSC_IOASCR_G1_IO3_Msk (0x1UL << TSC_IOASCR_G1_IO3_Pos) |
| #define | TSC_IOASCR_G1_IO3 TSC_IOASCR_G1_IO3_Msk |
| #define | TSC_IOASCR_G1_IO4_Pos (3U) |
| #define | TSC_IOASCR_G1_IO4_Msk (0x1UL << TSC_IOASCR_G1_IO4_Pos) |
| #define | TSC_IOASCR_G1_IO4 TSC_IOASCR_G1_IO4_Msk |
| #define | TSC_IOASCR_G2_IO1_Pos (4U) |
| #define | TSC_IOASCR_G2_IO1_Msk (0x1UL << TSC_IOASCR_G2_IO1_Pos) |
| #define | TSC_IOASCR_G2_IO1 TSC_IOASCR_G2_IO1_Msk |
| #define | TSC_IOASCR_G2_IO2_Pos (5U) |
| #define | TSC_IOASCR_G2_IO2_Msk (0x1UL << TSC_IOASCR_G2_IO2_Pos) |
| #define | TSC_IOASCR_G2_IO2 TSC_IOASCR_G2_IO2_Msk |
| #define | TSC_IOASCR_G2_IO3_Pos (6U) |
| #define | TSC_IOASCR_G2_IO3_Msk (0x1UL << TSC_IOASCR_G2_IO3_Pos) |
| #define | TSC_IOASCR_G2_IO3 TSC_IOASCR_G2_IO3_Msk |
| #define | TSC_IOASCR_G2_IO4_Pos (7U) |
| #define | TSC_IOASCR_G2_IO4_Msk (0x1UL << TSC_IOASCR_G2_IO4_Pos) |
| #define | TSC_IOASCR_G2_IO4 TSC_IOASCR_G2_IO4_Msk |
| #define | TSC_IOASCR_G3_IO1_Pos (8U) |
| #define | TSC_IOASCR_G3_IO1_Msk (0x1UL << TSC_IOASCR_G3_IO1_Pos) |
| #define | TSC_IOASCR_G3_IO1 TSC_IOASCR_G3_IO1_Msk |
| #define | TSC_IOASCR_G3_IO2_Pos (9U) |
| #define | TSC_IOASCR_G3_IO2_Msk (0x1UL << TSC_IOASCR_G3_IO2_Pos) |
| #define | TSC_IOASCR_G3_IO2 TSC_IOASCR_G3_IO2_Msk |
| #define | TSC_IOASCR_G3_IO3_Pos (10U) |
| #define | TSC_IOASCR_G3_IO3_Msk (0x1UL << TSC_IOASCR_G3_IO3_Pos) |
| #define | TSC_IOASCR_G3_IO3 TSC_IOASCR_G3_IO3_Msk |
| #define | TSC_IOASCR_G3_IO4_Pos (11U) |
| #define | TSC_IOASCR_G3_IO4_Msk (0x1UL << TSC_IOASCR_G3_IO4_Pos) |
| #define | TSC_IOASCR_G3_IO4 TSC_IOASCR_G3_IO4_Msk |
| #define | TSC_IOASCR_G4_IO1_Pos (12U) |
| #define | TSC_IOASCR_G4_IO1_Msk (0x1UL << TSC_IOASCR_G4_IO1_Pos) |
| #define | TSC_IOASCR_G4_IO1 TSC_IOASCR_G4_IO1_Msk |
| #define | TSC_IOASCR_G4_IO2_Pos (13U) |
| #define | TSC_IOASCR_G4_IO2_Msk (0x1UL << TSC_IOASCR_G4_IO2_Pos) |
| #define | TSC_IOASCR_G4_IO2 TSC_IOASCR_G4_IO2_Msk |
| #define | TSC_IOASCR_G4_IO3_Pos (14U) |
| #define | TSC_IOASCR_G4_IO3_Msk (0x1UL << TSC_IOASCR_G4_IO3_Pos) |
| #define | TSC_IOASCR_G4_IO3 TSC_IOASCR_G4_IO3_Msk |
| #define | TSC_IOASCR_G4_IO4_Pos (15U) |
| #define | TSC_IOASCR_G4_IO4_Msk (0x1UL << TSC_IOASCR_G4_IO4_Pos) |
| #define | TSC_IOASCR_G4_IO4 TSC_IOASCR_G4_IO4_Msk |
| #define | TSC_IOASCR_G5_IO1_Pos (16U) |
| #define | TSC_IOASCR_G5_IO1_Msk (0x1UL << TSC_IOASCR_G5_IO1_Pos) |
| #define | TSC_IOASCR_G5_IO1 TSC_IOASCR_G5_IO1_Msk |
| #define | TSC_IOASCR_G5_IO2_Pos (17U) |
| #define | TSC_IOASCR_G5_IO2_Msk (0x1UL << TSC_IOASCR_G5_IO2_Pos) |
| #define | TSC_IOASCR_G5_IO2 TSC_IOASCR_G5_IO2_Msk |
| #define | TSC_IOASCR_G5_IO3_Pos (18U) |
| #define | TSC_IOASCR_G5_IO3_Msk (0x1UL << TSC_IOASCR_G5_IO3_Pos) |
| #define | TSC_IOASCR_G5_IO3 TSC_IOASCR_G5_IO3_Msk |
| #define | TSC_IOASCR_G5_IO4_Pos (19U) |
| #define | TSC_IOASCR_G5_IO4_Msk (0x1UL << TSC_IOASCR_G5_IO4_Pos) |
| #define | TSC_IOASCR_G5_IO4 TSC_IOASCR_G5_IO4_Msk |
| #define | TSC_IOASCR_G6_IO1_Pos (20U) |
| #define | TSC_IOASCR_G6_IO1_Msk (0x1UL << TSC_IOASCR_G6_IO1_Pos) |
| #define | TSC_IOASCR_G6_IO1 TSC_IOASCR_G6_IO1_Msk |
| #define | TSC_IOASCR_G6_IO2_Pos (21U) |
| #define | TSC_IOASCR_G6_IO2_Msk (0x1UL << TSC_IOASCR_G6_IO2_Pos) |
| #define | TSC_IOASCR_G6_IO2 TSC_IOASCR_G6_IO2_Msk |
| #define | TSC_IOASCR_G6_IO3_Pos (22U) |
| #define | TSC_IOASCR_G6_IO3_Msk (0x1UL << TSC_IOASCR_G6_IO3_Pos) |
| #define | TSC_IOASCR_G6_IO3 TSC_IOASCR_G6_IO3_Msk |
| #define | TSC_IOASCR_G6_IO4_Pos (23U) |
| #define | TSC_IOASCR_G6_IO4_Msk (0x1UL << TSC_IOASCR_G6_IO4_Pos) |
| #define | TSC_IOASCR_G6_IO4 TSC_IOASCR_G6_IO4_Msk |
| #define | TSC_IOASCR_G7_IO1_Pos (24U) |
| #define | TSC_IOASCR_G7_IO1_Msk (0x1UL << TSC_IOASCR_G7_IO1_Pos) |
| #define | TSC_IOASCR_G7_IO1 TSC_IOASCR_G7_IO1_Msk |
| #define | TSC_IOASCR_G7_IO2_Pos (25U) |
| #define | TSC_IOASCR_G7_IO2_Msk (0x1UL << TSC_IOASCR_G7_IO2_Pos) |
| #define | TSC_IOASCR_G7_IO2 TSC_IOASCR_G7_IO2_Msk |
| #define | TSC_IOASCR_G7_IO3_Pos (26U) |
| #define | TSC_IOASCR_G7_IO3_Msk (0x1UL << TSC_IOASCR_G7_IO3_Pos) |
| #define | TSC_IOASCR_G7_IO3 TSC_IOASCR_G7_IO3_Msk |
| #define | TSC_IOASCR_G7_IO4_Pos (27U) |
| #define | TSC_IOASCR_G7_IO4_Msk (0x1UL << TSC_IOASCR_G7_IO4_Pos) |
| #define | TSC_IOASCR_G7_IO4 TSC_IOASCR_G7_IO4_Msk |
| #define | TSC_IOASCR_G8_IO1_Pos (28U) |
| #define | TSC_IOASCR_G8_IO1_Msk (0x1UL << TSC_IOASCR_G8_IO1_Pos) |
| #define | TSC_IOASCR_G8_IO1 TSC_IOASCR_G8_IO1_Msk |
| #define | TSC_IOASCR_G8_IO2_Pos (29U) |
| #define | TSC_IOASCR_G8_IO2_Msk (0x1UL << TSC_IOASCR_G8_IO2_Pos) |
| #define | TSC_IOASCR_G8_IO2 TSC_IOASCR_G8_IO2_Msk |
| #define | TSC_IOASCR_G8_IO3_Pos (30U) |
| #define | TSC_IOASCR_G8_IO3_Msk (0x1UL << TSC_IOASCR_G8_IO3_Pos) |
| #define | TSC_IOASCR_G8_IO3 TSC_IOASCR_G8_IO3_Msk |
| #define | TSC_IOASCR_G8_IO4_Pos (31U) |
| #define | TSC_IOASCR_G8_IO4_Msk (0x1UL << TSC_IOASCR_G8_IO4_Pos) |
| #define | TSC_IOASCR_G8_IO4 TSC_IOASCR_G8_IO4_Msk |
| #define | TSC_IOSCR_G1_IO1_Pos (0U) |
| #define | TSC_IOSCR_G1_IO1_Msk (0x1UL << TSC_IOSCR_G1_IO1_Pos) |
| #define | TSC_IOSCR_G1_IO1 TSC_IOSCR_G1_IO1_Msk |
| #define | TSC_IOSCR_G1_IO2_Pos (1U) |
| #define | TSC_IOSCR_G1_IO2_Msk (0x1UL << TSC_IOSCR_G1_IO2_Pos) |
| #define | TSC_IOSCR_G1_IO2 TSC_IOSCR_G1_IO2_Msk |
| #define | TSC_IOSCR_G1_IO3_Pos (2U) |
| #define | TSC_IOSCR_G1_IO3_Msk (0x1UL << TSC_IOSCR_G1_IO3_Pos) |
| #define | TSC_IOSCR_G1_IO3 TSC_IOSCR_G1_IO3_Msk |
| #define | TSC_IOSCR_G1_IO4_Pos (3U) |
| #define | TSC_IOSCR_G1_IO4_Msk (0x1UL << TSC_IOSCR_G1_IO4_Pos) |
| #define | TSC_IOSCR_G1_IO4 TSC_IOSCR_G1_IO4_Msk |
| #define | TSC_IOSCR_G2_IO1_Pos (4U) |
| #define | TSC_IOSCR_G2_IO1_Msk (0x1UL << TSC_IOSCR_G2_IO1_Pos) |
| #define | TSC_IOSCR_G2_IO1 TSC_IOSCR_G2_IO1_Msk |
| #define | TSC_IOSCR_G2_IO2_Pos (5U) |
| #define | TSC_IOSCR_G2_IO2_Msk (0x1UL << TSC_IOSCR_G2_IO2_Pos) |
| #define | TSC_IOSCR_G2_IO2 TSC_IOSCR_G2_IO2_Msk |
| #define | TSC_IOSCR_G2_IO3_Pos (6U) |
| #define | TSC_IOSCR_G2_IO3_Msk (0x1UL << TSC_IOSCR_G2_IO3_Pos) |
| #define | TSC_IOSCR_G2_IO3 TSC_IOSCR_G2_IO3_Msk |
| #define | TSC_IOSCR_G2_IO4_Pos (7U) |
| #define | TSC_IOSCR_G2_IO4_Msk (0x1UL << TSC_IOSCR_G2_IO4_Pos) |
| #define | TSC_IOSCR_G2_IO4 TSC_IOSCR_G2_IO4_Msk |
| #define | TSC_IOSCR_G3_IO1_Pos (8U) |
| #define | TSC_IOSCR_G3_IO1_Msk (0x1UL << TSC_IOSCR_G3_IO1_Pos) |
| #define | TSC_IOSCR_G3_IO1 TSC_IOSCR_G3_IO1_Msk |
| #define | TSC_IOSCR_G3_IO2_Pos (9U) |
| #define | TSC_IOSCR_G3_IO2_Msk (0x1UL << TSC_IOSCR_G3_IO2_Pos) |
| #define | TSC_IOSCR_G3_IO2 TSC_IOSCR_G3_IO2_Msk |
| #define | TSC_IOSCR_G3_IO3_Pos (10U) |
| #define | TSC_IOSCR_G3_IO3_Msk (0x1UL << TSC_IOSCR_G3_IO3_Pos) |
| #define | TSC_IOSCR_G3_IO3 TSC_IOSCR_G3_IO3_Msk |
| #define | TSC_IOSCR_G3_IO4_Pos (11U) |
| #define | TSC_IOSCR_G3_IO4_Msk (0x1UL << TSC_IOSCR_G3_IO4_Pos) |
| #define | TSC_IOSCR_G3_IO4 TSC_IOSCR_G3_IO4_Msk |
| #define | TSC_IOSCR_G4_IO1_Pos (12U) |
| #define | TSC_IOSCR_G4_IO1_Msk (0x1UL << TSC_IOSCR_G4_IO1_Pos) |
| #define | TSC_IOSCR_G4_IO1 TSC_IOSCR_G4_IO1_Msk |
| #define | TSC_IOSCR_G4_IO2_Pos (13U) |
| #define | TSC_IOSCR_G4_IO2_Msk (0x1UL << TSC_IOSCR_G4_IO2_Pos) |
| #define | TSC_IOSCR_G4_IO2 TSC_IOSCR_G4_IO2_Msk |
| #define | TSC_IOSCR_G4_IO3_Pos (14U) |
| #define | TSC_IOSCR_G4_IO3_Msk (0x1UL << TSC_IOSCR_G4_IO3_Pos) |
| #define | TSC_IOSCR_G4_IO3 TSC_IOSCR_G4_IO3_Msk |
| #define | TSC_IOSCR_G4_IO4_Pos (15U) |
| #define | TSC_IOSCR_G4_IO4_Msk (0x1UL << TSC_IOSCR_G4_IO4_Pos) |
| #define | TSC_IOSCR_G4_IO4 TSC_IOSCR_G4_IO4_Msk |
| #define | TSC_IOSCR_G5_IO1_Pos (16U) |
| #define | TSC_IOSCR_G5_IO1_Msk (0x1UL << TSC_IOSCR_G5_IO1_Pos) |
| #define | TSC_IOSCR_G5_IO1 TSC_IOSCR_G5_IO1_Msk |
| #define | TSC_IOSCR_G5_IO2_Pos (17U) |
| #define | TSC_IOSCR_G5_IO2_Msk (0x1UL << TSC_IOSCR_G5_IO2_Pos) |
| #define | TSC_IOSCR_G5_IO2 TSC_IOSCR_G5_IO2_Msk |
| #define | TSC_IOSCR_G5_IO3_Pos (18U) |
| #define | TSC_IOSCR_G5_IO3_Msk (0x1UL << TSC_IOSCR_G5_IO3_Pos) |
| #define | TSC_IOSCR_G5_IO3 TSC_IOSCR_G5_IO3_Msk |
| #define | TSC_IOSCR_G5_IO4_Pos (19U) |
| #define | TSC_IOSCR_G5_IO4_Msk (0x1UL << TSC_IOSCR_G5_IO4_Pos) |
| #define | TSC_IOSCR_G5_IO4 TSC_IOSCR_G5_IO4_Msk |
| #define | TSC_IOSCR_G6_IO1_Pos (20U) |
| #define | TSC_IOSCR_G6_IO1_Msk (0x1UL << TSC_IOSCR_G6_IO1_Pos) |
| #define | TSC_IOSCR_G6_IO1 TSC_IOSCR_G6_IO1_Msk |
| #define | TSC_IOSCR_G6_IO2_Pos (21U) |
| #define | TSC_IOSCR_G6_IO2_Msk (0x1UL << TSC_IOSCR_G6_IO2_Pos) |
| #define | TSC_IOSCR_G6_IO2 TSC_IOSCR_G6_IO2_Msk |
| #define | TSC_IOSCR_G6_IO3_Pos (22U) |
| #define | TSC_IOSCR_G6_IO3_Msk (0x1UL << TSC_IOSCR_G6_IO3_Pos) |
| #define | TSC_IOSCR_G6_IO3 TSC_IOSCR_G6_IO3_Msk |
| #define | TSC_IOSCR_G6_IO4_Pos (23U) |
| #define | TSC_IOSCR_G6_IO4_Msk (0x1UL << TSC_IOSCR_G6_IO4_Pos) |
| #define | TSC_IOSCR_G6_IO4 TSC_IOSCR_G6_IO4_Msk |
| #define | TSC_IOSCR_G7_IO1_Pos (24U) |
| #define | TSC_IOSCR_G7_IO1_Msk (0x1UL << TSC_IOSCR_G7_IO1_Pos) |
| #define | TSC_IOSCR_G7_IO1 TSC_IOSCR_G7_IO1_Msk |
| #define | TSC_IOSCR_G7_IO2_Pos (25U) |
| #define | TSC_IOSCR_G7_IO2_Msk (0x1UL << TSC_IOSCR_G7_IO2_Pos) |
| #define | TSC_IOSCR_G7_IO2 TSC_IOSCR_G7_IO2_Msk |
| #define | TSC_IOSCR_G7_IO3_Pos (26U) |
| #define | TSC_IOSCR_G7_IO3_Msk (0x1UL << TSC_IOSCR_G7_IO3_Pos) |
| #define | TSC_IOSCR_G7_IO3 TSC_IOSCR_G7_IO3_Msk |
| #define | TSC_IOSCR_G7_IO4_Pos (27U) |
| #define | TSC_IOSCR_G7_IO4_Msk (0x1UL << TSC_IOSCR_G7_IO4_Pos) |
| #define | TSC_IOSCR_G7_IO4 TSC_IOSCR_G7_IO4_Msk |
| #define | TSC_IOSCR_G8_IO1_Pos (28U) |
| #define | TSC_IOSCR_G8_IO1_Msk (0x1UL << TSC_IOSCR_G8_IO1_Pos) |
| #define | TSC_IOSCR_G8_IO1 TSC_IOSCR_G8_IO1_Msk |
| #define | TSC_IOSCR_G8_IO2_Pos (29U) |
| #define | TSC_IOSCR_G8_IO2_Msk (0x1UL << TSC_IOSCR_G8_IO2_Pos) |
| #define | TSC_IOSCR_G8_IO2 TSC_IOSCR_G8_IO2_Msk |
| #define | TSC_IOSCR_G8_IO3_Pos (30U) |
| #define | TSC_IOSCR_G8_IO3_Msk (0x1UL << TSC_IOSCR_G8_IO3_Pos) |
| #define | TSC_IOSCR_G8_IO3 TSC_IOSCR_G8_IO3_Msk |
| #define | TSC_IOSCR_G8_IO4_Pos (31U) |
| #define | TSC_IOSCR_G8_IO4_Msk (0x1UL << TSC_IOSCR_G8_IO4_Pos) |
| #define | TSC_IOSCR_G8_IO4 TSC_IOSCR_G8_IO4_Msk |
| #define | TSC_IOCCR_G1_IO1_Pos (0U) |
| #define | TSC_IOCCR_G1_IO1_Msk (0x1UL << TSC_IOCCR_G1_IO1_Pos) |
| #define | TSC_IOCCR_G1_IO1 TSC_IOCCR_G1_IO1_Msk |
| #define | TSC_IOCCR_G1_IO2_Pos (1U) |
| #define | TSC_IOCCR_G1_IO2_Msk (0x1UL << TSC_IOCCR_G1_IO2_Pos) |
| #define | TSC_IOCCR_G1_IO2 TSC_IOCCR_G1_IO2_Msk |
| #define | TSC_IOCCR_G1_IO3_Pos (2U) |
| #define | TSC_IOCCR_G1_IO3_Msk (0x1UL << TSC_IOCCR_G1_IO3_Pos) |
| #define | TSC_IOCCR_G1_IO3 TSC_IOCCR_G1_IO3_Msk |
| #define | TSC_IOCCR_G1_IO4_Pos (3U) |
| #define | TSC_IOCCR_G1_IO4_Msk (0x1UL << TSC_IOCCR_G1_IO4_Pos) |
| #define | TSC_IOCCR_G1_IO4 TSC_IOCCR_G1_IO4_Msk |
| #define | TSC_IOCCR_G2_IO1_Pos (4U) |
| #define | TSC_IOCCR_G2_IO1_Msk (0x1UL << TSC_IOCCR_G2_IO1_Pos) |
| #define | TSC_IOCCR_G2_IO1 TSC_IOCCR_G2_IO1_Msk |
| #define | TSC_IOCCR_G2_IO2_Pos (5U) |
| #define | TSC_IOCCR_G2_IO2_Msk (0x1UL << TSC_IOCCR_G2_IO2_Pos) |
| #define | TSC_IOCCR_G2_IO2 TSC_IOCCR_G2_IO2_Msk |
| #define | TSC_IOCCR_G2_IO3_Pos (6U) |
| #define | TSC_IOCCR_G2_IO3_Msk (0x1UL << TSC_IOCCR_G2_IO3_Pos) |
| #define | TSC_IOCCR_G2_IO3 TSC_IOCCR_G2_IO3_Msk |
| #define | TSC_IOCCR_G2_IO4_Pos (7U) |
| #define | TSC_IOCCR_G2_IO4_Msk (0x1UL << TSC_IOCCR_G2_IO4_Pos) |
| #define | TSC_IOCCR_G2_IO4 TSC_IOCCR_G2_IO4_Msk |
| #define | TSC_IOCCR_G3_IO1_Pos (8U) |
| #define | TSC_IOCCR_G3_IO1_Msk (0x1UL << TSC_IOCCR_G3_IO1_Pos) |
| #define | TSC_IOCCR_G3_IO1 TSC_IOCCR_G3_IO1_Msk |
| #define | TSC_IOCCR_G3_IO2_Pos (9U) |
| #define | TSC_IOCCR_G3_IO2_Msk (0x1UL << TSC_IOCCR_G3_IO2_Pos) |
| #define | TSC_IOCCR_G3_IO2 TSC_IOCCR_G3_IO2_Msk |
| #define | TSC_IOCCR_G3_IO3_Pos (10U) |
| #define | TSC_IOCCR_G3_IO3_Msk (0x1UL << TSC_IOCCR_G3_IO3_Pos) |
| #define | TSC_IOCCR_G3_IO3 TSC_IOCCR_G3_IO3_Msk |
| #define | TSC_IOCCR_G3_IO4_Pos (11U) |
| #define | TSC_IOCCR_G3_IO4_Msk (0x1UL << TSC_IOCCR_G3_IO4_Pos) |
| #define | TSC_IOCCR_G3_IO4 TSC_IOCCR_G3_IO4_Msk |
| #define | TSC_IOCCR_G4_IO1_Pos (12U) |
| #define | TSC_IOCCR_G4_IO1_Msk (0x1UL << TSC_IOCCR_G4_IO1_Pos) |
| #define | TSC_IOCCR_G4_IO1 TSC_IOCCR_G4_IO1_Msk |
| #define | TSC_IOCCR_G4_IO2_Pos (13U) |
| #define | TSC_IOCCR_G4_IO2_Msk (0x1UL << TSC_IOCCR_G4_IO2_Pos) |
| #define | TSC_IOCCR_G4_IO2 TSC_IOCCR_G4_IO2_Msk |
| #define | TSC_IOCCR_G4_IO3_Pos (14U) |
| #define | TSC_IOCCR_G4_IO3_Msk (0x1UL << TSC_IOCCR_G4_IO3_Pos) |
| #define | TSC_IOCCR_G4_IO3 TSC_IOCCR_G4_IO3_Msk |
| #define | TSC_IOCCR_G4_IO4_Pos (15U) |
| #define | TSC_IOCCR_G4_IO4_Msk (0x1UL << TSC_IOCCR_G4_IO4_Pos) |
| #define | TSC_IOCCR_G4_IO4 TSC_IOCCR_G4_IO4_Msk |
| #define | TSC_IOCCR_G5_IO1_Pos (16U) |
| #define | TSC_IOCCR_G5_IO1_Msk (0x1UL << TSC_IOCCR_G5_IO1_Pos) |
| #define | TSC_IOCCR_G5_IO1 TSC_IOCCR_G5_IO1_Msk |
| #define | TSC_IOCCR_G5_IO2_Pos (17U) |
| #define | TSC_IOCCR_G5_IO2_Msk (0x1UL << TSC_IOCCR_G5_IO2_Pos) |
| #define | TSC_IOCCR_G5_IO2 TSC_IOCCR_G5_IO2_Msk |
| #define | TSC_IOCCR_G5_IO3_Pos (18U) |
| #define | TSC_IOCCR_G5_IO3_Msk (0x1UL << TSC_IOCCR_G5_IO3_Pos) |
| #define | TSC_IOCCR_G5_IO3 TSC_IOCCR_G5_IO3_Msk |
| #define | TSC_IOCCR_G5_IO4_Pos (19U) |
| #define | TSC_IOCCR_G5_IO4_Msk (0x1UL << TSC_IOCCR_G5_IO4_Pos) |
| #define | TSC_IOCCR_G5_IO4 TSC_IOCCR_G5_IO4_Msk |
| #define | TSC_IOCCR_G6_IO1_Pos (20U) |
| #define | TSC_IOCCR_G6_IO1_Msk (0x1UL << TSC_IOCCR_G6_IO1_Pos) |
| #define | TSC_IOCCR_G6_IO1 TSC_IOCCR_G6_IO1_Msk |
| #define | TSC_IOCCR_G6_IO2_Pos (21U) |
| #define | TSC_IOCCR_G6_IO2_Msk (0x1UL << TSC_IOCCR_G6_IO2_Pos) |
| #define | TSC_IOCCR_G6_IO2 TSC_IOCCR_G6_IO2_Msk |
| #define | TSC_IOCCR_G6_IO3_Pos (22U) |
| #define | TSC_IOCCR_G6_IO3_Msk (0x1UL << TSC_IOCCR_G6_IO3_Pos) |
| #define | TSC_IOCCR_G6_IO3 TSC_IOCCR_G6_IO3_Msk |
| #define | TSC_IOCCR_G6_IO4_Pos (23U) |
| #define | TSC_IOCCR_G6_IO4_Msk (0x1UL << TSC_IOCCR_G6_IO4_Pos) |
| #define | TSC_IOCCR_G6_IO4 TSC_IOCCR_G6_IO4_Msk |
| #define | TSC_IOCCR_G7_IO1_Pos (24U) |
| #define | TSC_IOCCR_G7_IO1_Msk (0x1UL << TSC_IOCCR_G7_IO1_Pos) |
| #define | TSC_IOCCR_G7_IO1 TSC_IOCCR_G7_IO1_Msk |
| #define | TSC_IOCCR_G7_IO2_Pos (25U) |
| #define | TSC_IOCCR_G7_IO2_Msk (0x1UL << TSC_IOCCR_G7_IO2_Pos) |
| #define | TSC_IOCCR_G7_IO2 TSC_IOCCR_G7_IO2_Msk |
| #define | TSC_IOCCR_G7_IO3_Pos (26U) |
| #define | TSC_IOCCR_G7_IO3_Msk (0x1UL << TSC_IOCCR_G7_IO3_Pos) |
| #define | TSC_IOCCR_G7_IO3 TSC_IOCCR_G7_IO3_Msk |
| #define | TSC_IOCCR_G7_IO4_Pos (27U) |
| #define | TSC_IOCCR_G7_IO4_Msk (0x1UL << TSC_IOCCR_G7_IO4_Pos) |
| #define | TSC_IOCCR_G7_IO4 TSC_IOCCR_G7_IO4_Msk |
| #define | TSC_IOCCR_G8_IO1_Pos (28U) |
| #define | TSC_IOCCR_G8_IO1_Msk (0x1UL << TSC_IOCCR_G8_IO1_Pos) |
| #define | TSC_IOCCR_G8_IO1 TSC_IOCCR_G8_IO1_Msk |
| #define | TSC_IOCCR_G8_IO2_Pos (29U) |
| #define | TSC_IOCCR_G8_IO2_Msk (0x1UL << TSC_IOCCR_G8_IO2_Pos) |
| #define | TSC_IOCCR_G8_IO2 TSC_IOCCR_G8_IO2_Msk |
| #define | TSC_IOCCR_G8_IO3_Pos (30U) |
| #define | TSC_IOCCR_G8_IO3_Msk (0x1UL << TSC_IOCCR_G8_IO3_Pos) |
| #define | TSC_IOCCR_G8_IO3 TSC_IOCCR_G8_IO3_Msk |
| #define | TSC_IOCCR_G8_IO4_Pos (31U) |
| #define | TSC_IOCCR_G8_IO4_Msk (0x1UL << TSC_IOCCR_G8_IO4_Pos) |
| #define | TSC_IOCCR_G8_IO4 TSC_IOCCR_G8_IO4_Msk |
| #define | TSC_IOGCSR_G1E_Pos (0U) |
| #define | TSC_IOGCSR_G1E_Msk (0x1UL << TSC_IOGCSR_G1E_Pos) |
| #define | TSC_IOGCSR_G1E TSC_IOGCSR_G1E_Msk |
| #define | TSC_IOGCSR_G2E_Pos (1U) |
| #define | TSC_IOGCSR_G2E_Msk (0x1UL << TSC_IOGCSR_G2E_Pos) |
| #define | TSC_IOGCSR_G2E TSC_IOGCSR_G2E_Msk |
| #define | TSC_IOGCSR_G3E_Pos (2U) |
| #define | TSC_IOGCSR_G3E_Msk (0x1UL << TSC_IOGCSR_G3E_Pos) |
| #define | TSC_IOGCSR_G3E TSC_IOGCSR_G3E_Msk |
| #define | TSC_IOGCSR_G4E_Pos (3U) |
| #define | TSC_IOGCSR_G4E_Msk (0x1UL << TSC_IOGCSR_G4E_Pos) |
| #define | TSC_IOGCSR_G4E TSC_IOGCSR_G4E_Msk |
| #define | TSC_IOGCSR_G5E_Pos (4U) |
| #define | TSC_IOGCSR_G5E_Msk (0x1UL << TSC_IOGCSR_G5E_Pos) |
| #define | TSC_IOGCSR_G5E TSC_IOGCSR_G5E_Msk |
| #define | TSC_IOGCSR_G6E_Pos (5U) |
| #define | TSC_IOGCSR_G6E_Msk (0x1UL << TSC_IOGCSR_G6E_Pos) |
| #define | TSC_IOGCSR_G6E TSC_IOGCSR_G6E_Msk |
| #define | TSC_IOGCSR_G7E_Pos (6U) |
| #define | TSC_IOGCSR_G7E_Msk (0x1UL << TSC_IOGCSR_G7E_Pos) |
| #define | TSC_IOGCSR_G7E TSC_IOGCSR_G7E_Msk |
| #define | TSC_IOGCSR_G8E_Pos (7U) |
| #define | TSC_IOGCSR_G8E_Msk (0x1UL << TSC_IOGCSR_G8E_Pos) |
| #define | TSC_IOGCSR_G8E TSC_IOGCSR_G8E_Msk |
| #define | TSC_IOGCSR_G1S_Pos (16U) |
| #define | TSC_IOGCSR_G1S_Msk (0x1UL << TSC_IOGCSR_G1S_Pos) |
| #define | TSC_IOGCSR_G1S TSC_IOGCSR_G1S_Msk |
| #define | TSC_IOGCSR_G2S_Pos (17U) |
| #define | TSC_IOGCSR_G2S_Msk (0x1UL << TSC_IOGCSR_G2S_Pos) |
| #define | TSC_IOGCSR_G2S TSC_IOGCSR_G2S_Msk |
| #define | TSC_IOGCSR_G3S_Pos (18U) |
| #define | TSC_IOGCSR_G3S_Msk (0x1UL << TSC_IOGCSR_G3S_Pos) |
| #define | TSC_IOGCSR_G3S TSC_IOGCSR_G3S_Msk |
| #define | TSC_IOGCSR_G4S_Pos (19U) |
| #define | TSC_IOGCSR_G4S_Msk (0x1UL << TSC_IOGCSR_G4S_Pos) |
| #define | TSC_IOGCSR_G4S TSC_IOGCSR_G4S_Msk |
| #define | TSC_IOGCSR_G5S_Pos (20U) |
| #define | TSC_IOGCSR_G5S_Msk (0x1UL << TSC_IOGCSR_G5S_Pos) |
| #define | TSC_IOGCSR_G5S TSC_IOGCSR_G5S_Msk |
| #define | TSC_IOGCSR_G6S_Pos (21U) |
| #define | TSC_IOGCSR_G6S_Msk (0x1UL << TSC_IOGCSR_G6S_Pos) |
| #define | TSC_IOGCSR_G6S TSC_IOGCSR_G6S_Msk |
| #define | TSC_IOGCSR_G7S_Pos (22U) |
| #define | TSC_IOGCSR_G7S_Msk (0x1UL << TSC_IOGCSR_G7S_Pos) |
| #define | TSC_IOGCSR_G7S TSC_IOGCSR_G7S_Msk |
| #define | TSC_IOGCSR_G8S_Pos (23U) |
| #define | TSC_IOGCSR_G8S_Msk (0x1UL << TSC_IOGCSR_G8S_Pos) |
| #define | TSC_IOGCSR_G8S TSC_IOGCSR_G8S_Msk |
| #define | TSC_IOGXCR_CNT_Pos (0U) |
| #define | TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) |
| #define | TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk |
| #define | SAI_GCR_SYNCIN_Pos (0U) |
| #define | SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) |
| #define | SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk |
| #define | SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) |
| #define | SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) |
| #define | SAI_GCR_SYNCOUT_Pos (4U) |
| #define | SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) |
| #define | SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk |
| #define | SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) |
| #define | SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) |
| #define | SAI_xCR1_MODE_Pos (0U) |
| #define | SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) |
| #define | SAI_xCR1_MODE SAI_xCR1_MODE_Msk |
| #define | SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) |
| #define | SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) |
| #define | SAI_xCR1_PRTCFG_Pos (2U) |
| #define | SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) |
| #define | SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk |
| #define | SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) |
| #define | SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) |
| #define | SAI_xCR1_DS_Pos (5U) |
| #define | SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) |
| #define | SAI_xCR1_DS SAI_xCR1_DS_Msk |
| #define | SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) |
| #define | SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) |
| #define | SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) |
| #define | SAI_xCR1_LSBFIRST_Pos (8U) |
| #define | SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) |
| #define | SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk |
| #define | SAI_xCR1_CKSTR_Pos (9U) |
| #define | SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) |
| #define | SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk |
| #define | SAI_xCR1_SYNCEN_Pos (10U) |
| #define | SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) |
| #define | SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk |
| #define | SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) |
| #define | SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) |
| #define | SAI_xCR1_MONO_Pos (12U) |
| #define | SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) |
| #define | SAI_xCR1_MONO SAI_xCR1_MONO_Msk |
| #define | SAI_xCR1_OUTDRIV_Pos (13U) |
| #define | SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) |
| #define | SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk |
| #define | SAI_xCR1_SAIEN_Pos (16U) |
| #define | SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) |
| #define | SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk |
| #define | SAI_xCR1_DMAEN_Pos (17U) |
| #define | SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) |
| #define | SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk |
| #define | SAI_xCR1_NODIV_Pos (19U) |
| #define | SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) |
| #define | SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk |
| #define | SAI_xCR1_MCKDIV_Pos (20U) |
| #define | SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) |
| #define | SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk |
| #define | SAI_xCR1_MCKDIV_0 (0x00100000UL) |
| #define | SAI_xCR1_MCKDIV_1 (0x00200000UL) |
| #define | SAI_xCR1_MCKDIV_2 (0x00400000UL) |
| #define | SAI_xCR1_MCKDIV_3 (0x00800000UL) |
| #define | SAI_xCR1_MCKDIV_4 (0x01000000UL) |
| #define | SAI_xCR1_MCKDIV_5 (0x02000000UL) |
| #define | SAI_xCR1_OSR_Pos (26U) |
| #define | SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) |
| #define | SAI_xCR1_OSR SAI_xCR1_OSR_Msk |
| #define | SAI_xCR1_MCKEN_Pos (27U) |
| #define | SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) |
| #define | SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk |
| #define | SAI_xCR2_FTH_Pos (0U) |
| #define | SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) |
| #define | SAI_xCR2_FTH SAI_xCR2_FTH_Msk |
| #define | SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) |
| #define | SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) |
| #define | SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) |
| #define | SAI_xCR2_FFLUSH_Pos (3U) |
| #define | SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) |
| #define | SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk |
| #define | SAI_xCR2_TRIS_Pos (4U) |
| #define | SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) |
| #define | SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk |
| #define | SAI_xCR2_MUTE_Pos (5U) |
| #define | SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) |
| #define | SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk |
| #define | SAI_xCR2_MUTEVAL_Pos (6U) |
| #define | SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) |
| #define | SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk |
| #define | SAI_xCR2_MUTECNT_Pos (7U) |
| #define | SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) |
| #define | SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk |
| #define | SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) |
| #define | SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) |
| #define | SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) |
| #define | SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) |
| #define | SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) |
| #define | SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) |
| #define | SAI_xCR2_CPL_Pos (13U) |
| #define | SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) |
| #define | SAI_xCR2_CPL SAI_xCR2_CPL_Msk |
| #define | SAI_xCR2_COMP_Pos (14U) |
| #define | SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) |
| #define | SAI_xCR2_COMP SAI_xCR2_COMP_Msk |
| #define | SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) |
| #define | SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) |
| #define | SAI_xFRCR_FRL_Pos (0U) |
| #define | SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) |
| #define | SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk |
| #define | SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) |
| #define | SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) |
| #define | SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) |
| #define | SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) |
| #define | SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) |
| #define | SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) |
| #define | SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) |
| #define | SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) |
| #define | SAI_xFRCR_FSALL_Pos (8U) |
| #define | SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) |
| #define | SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk |
| #define | SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) |
| #define | SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) |
| #define | SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) |
| #define | SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) |
| #define | SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) |
| #define | SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) |
| #define | SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) |
| #define | SAI_xFRCR_FSDEF_Pos (16U) |
| #define | SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) |
| #define | SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk |
| #define | SAI_xFRCR_FSPOL_Pos (17U) |
| #define | SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) |
| #define | SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk |
| #define | SAI_xFRCR_FSOFF_Pos (18U) |
| #define | SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) |
| #define | SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk |
| #define | SAI_xSLOTR_FBOFF_Pos (0U) |
| #define | SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) |
| #define | SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk |
| #define | SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) |
| #define | SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) |
| #define | SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) |
| #define | SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) |
| #define | SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) |
| #define | SAI_xSLOTR_SLOTSZ_Pos (6U) |
| #define | SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) |
| #define | SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk |
| #define | SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) |
| #define | SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) |
| #define | SAI_xSLOTR_NBSLOT_Pos (8U) |
| #define | SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) |
| #define | SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk |
| #define | SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) |
| #define | SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) |
| #define | SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) |
| #define | SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) |
| #define | SAI_xSLOTR_SLOTEN_Pos (16U) |
| #define | SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) |
| #define | SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk |
| #define | SAI_xIMR_OVRUDRIE_Pos (0U) |
| #define | SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) |
| #define | SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk |
| #define | SAI_xIMR_MUTEDETIE_Pos (1U) |
| #define | SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) |
| #define | SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk |
| #define | SAI_xIMR_WCKCFGIE_Pos (2U) |
| #define | SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) |
| #define | SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk |
| #define | SAI_xIMR_FREQIE_Pos (3U) |
| #define | SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) |
| #define | SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk |
| #define | SAI_xIMR_CNRDYIE_Pos (4U) |
| #define | SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) |
| #define | SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk |
| #define | SAI_xIMR_AFSDETIE_Pos (5U) |
| #define | SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) |
| #define | SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk |
| #define | SAI_xIMR_LFSDETIE_Pos (6U) |
| #define | SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) |
| #define | SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk |
| #define | SAI_xSR_OVRUDR_Pos (0U) |
| #define | SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) |
| #define | SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk |
| #define | SAI_xSR_MUTEDET_Pos (1U) |
| #define | SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) |
| #define | SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk |
| #define | SAI_xSR_WCKCFG_Pos (2U) |
| #define | SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) |
| #define | SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk |
| #define | SAI_xSR_FREQ_Pos (3U) |
| #define | SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) |
| #define | SAI_xSR_FREQ SAI_xSR_FREQ_Msk |
| #define | SAI_xSR_CNRDY_Pos (4U) |
| #define | SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) |
| #define | SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk |
| #define | SAI_xSR_AFSDET_Pos (5U) |
| #define | SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) |
| #define | SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk |
| #define | SAI_xSR_LFSDET_Pos (6U) |
| #define | SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) |
| #define | SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk |
| #define | SAI_xSR_FLVL_Pos (16U) |
| #define | SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) |
| #define | SAI_xSR_FLVL SAI_xSR_FLVL_Msk |
| #define | SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) |
| #define | SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) |
| #define | SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) |
| #define | SAI_xCLRFR_COVRUDR_Pos (0U) |
| #define | SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) |
| #define | SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk |
| #define | SAI_xCLRFR_CMUTEDET_Pos (1U) |
| #define | SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) |
| #define | SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk |
| #define | SAI_xCLRFR_CWCKCFG_Pos (2U) |
| #define | SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) |
| #define | SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk |
| #define | SAI_xCLRFR_CFREQ_Pos (3U) |
| #define | SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) |
| #define | SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk |
| #define | SAI_xCLRFR_CCNRDY_Pos (4U) |
| #define | SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) |
| #define | SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk |
| #define | SAI_xCLRFR_CAFSDET_Pos (5U) |
| #define | SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) |
| #define | SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk |
| #define | SAI_xCLRFR_CLFSDET_Pos (6U) |
| #define | SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) |
| #define | SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk |
| #define | SAI_xDR_DATA_Pos (0U) |
| #define | SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) |
| #define | SAI_xDR_DATA SAI_xDR_DATA_Msk |
| #define | SAI_PDMCR_PDMEN_Pos (0U) |
| #define | SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) |
| #define | SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk |
| #define | SAI_PDMCR_MICNBR_Pos (4U) |
| #define | SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) |
| #define | SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk |
| #define | SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) |
| #define | SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) |
| #define | SAI_PDMCR_CKEN1_Pos (8U) |
| #define | SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) |
| #define | SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk |
| #define | SAI_PDMCR_CKEN2_Pos (9U) |
| #define | SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) |
| #define | SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk |
| #define | SAI_PDMCR_CKEN3_Pos (10U) |
| #define | SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) |
| #define | SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk |
| #define | SAI_PDMCR_CKEN4_Pos (11U) |
| #define | SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) |
| #define | SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk |
| #define | SAI_PDMDLY_DLYM1L_Pos (0U) |
| #define | SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) |
| #define | SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk |
| #define | SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) |
| #define | SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) |
| #define | SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) |
| #define | SAI_PDMDLY_DLYM1R_Pos (4U) |
| #define | SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) |
| #define | SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk |
| #define | SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) |
| #define | SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) |
| #define | SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) |
| #define | SAI_PDMDLY_DLYM2L_Pos (8U) |
| #define | SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) |
| #define | SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk |
| #define | SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) |
| #define | SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) |
| #define | SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) |
| #define | SAI_PDMDLY_DLYM2R_Pos (12U) |
| #define | SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) |
| #define | SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk |
| #define | SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) |
| #define | SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) |
| #define | SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) |
| #define | SAI_PDMDLY_DLYM3L_Pos (16U) |
| #define | SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) |
| #define | SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk |
| #define | SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) |
| #define | SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) |
| #define | SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) |
| #define | SAI_PDMDLY_DLYM3R_Pos (20U) |
| #define | SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) |
| #define | SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk |
| #define | SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) |
| #define | SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) |
| #define | SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) |
| #define | SAI_PDMDLY_DLYM4L_Pos (24U) |
| #define | SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) |
| #define | SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk |
| #define | SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) |
| #define | SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) |
| #define | SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) |
| #define | SAI_PDMDLY_DLYM4R_Pos (28U) |
| #define | SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) |
| #define | SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk |
| #define | SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) |
| #define | SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) |
| #define | SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) |
| #define | SYSCFG_SECCFGR_SYSCFGSEC_Pos (0U) |
| #define | SYSCFG_SECCFGR_SYSCFGSEC_Msk (0x1UL << SYSCFG_SECCFGR_SYSCFGSEC_Pos) |
| #define | SYSCFG_SECCFGR_SYSCFGSEC SYSCFG_SECCFGR_SYSCFGSEC_Msk |
| #define | SYSCFG_SECCFGR_CLASSBSEC_Pos (1U) |
| #define | SYSCFG_SECCFGR_CLASSBSEC_Msk (0x1UL << SYSCFG_SECCFGR_CLASSBSEC_Pos) |
| #define | SYSCFG_SECCFGR_CLASSBSEC SYSCFG_SECCFGR_CLASSBSEC_Msk |
| #define | SYSCFG_SECCFGR_FPUSEC_Pos (3U) |
| #define | SYSCFG_SECCFGR_FPUSEC_Msk (0x1UL << SYSCFG_SECCFGR_FPUSEC_Pos) |
| #define | SYSCFG_SECCFGR_FPUSEC SYSCFG_SECCFGR_FPUSEC_Msk |
| #define | SYSCFG_CFGR1_BOOSTEN_Pos (8U) |
| #define | SYSCFG_CFGR1_BOOSTEN_Msk (0x1UL << SYSCFG_CFGR1_BOOSTEN_Pos) |
| #define | SYSCFG_CFGR1_BOOSTEN SYSCFG_CFGR1_BOOSTEN_Msk |
| #define | SYSCFG_CFGR1_ANASWVDD_Pos (9U) |
| #define | SYSCFG_CFGR1_ANASWVDD_Msk (0x1UL << SYSCFG_CFGR1_ANASWVDD_Pos) |
| #define | SYSCFG_CFGR1_ANASWVDD SYSCFG_CFGR1_ANASWVDD_Msk |
| #define | SYSCFG_CFGR1_PB6_FMP_Pos (16U) |
| #define | SYSCFG_CFGR1_PB6_FMP_Msk (0x1UL << SYSCFG_CFGR1_PB6_FMP_Pos) |
| #define | SYSCFG_CFGR1_PB6_FMP SYSCFG_CFGR1_PB6_FMP_Msk |
| #define | SYSCFG_CFGR1_PB7_FMP_Pos (17U) |
| #define | SYSCFG_CFGR1_PB7_FMP_Msk (0x1UL << SYSCFG_CFGR1_PB7_FMP_Pos) |
| #define | SYSCFG_CFGR1_PB7_FMP SYSCFG_CFGR1_PB7_FMP_Msk |
| #define | SYSCFG_CFGR1_PB8_FMP_Pos (18U) |
| #define | SYSCFG_CFGR1_PB8_FMP_Msk (0x1UL << SYSCFG_CFGR1_PB8_FMP_Pos) |
| #define | SYSCFG_CFGR1_PB8_FMP SYSCFG_CFGR1_PB8_FMP_Msk |
| #define | SYSCFG_CFGR1_PB9_FMP_Pos (19U) |
| #define | SYSCFG_CFGR1_PB9_FMP_Msk (0x1UL << SYSCFG_CFGR1_PB9_FMP_Pos) |
| #define | SYSCFG_CFGR1_PB9_FMP SYSCFG_CFGR1_PB9_FMP_Msk |
| #define | SYSCFG_CFGR1_ENDCAP_Pos (24U) |
| #define | SYSCFG_CFGR1_ENDCAP_Msk (0x3UL << SYSCFG_CFGR1_ENDCAP_Pos) |
| #define | SYSCFG_CFGR1_ENDCAP SYSCFG_CFGR1_ENDCAP_Msk |
| #define | SYSCFG_CFGR1_ENDCAP_0 (0x1UL << SYSCFG_CFGR1_ENDCAP_Pos) |
| #define | SYSCFG_CFGR1_ENDCAP_1 (0x2UL << SYSCFG_CFGR1_ENDCAP_Pos) |
| #define | SYSCFG_CFGR1_SRAMCACHED_Pos (28U) |
| #define | SYSCFG_CFGR1_SRAMCACHED_Msk (0x1UL << SYSCFG_CFGR1_SRAMCACHED_Pos) |
| #define | SYSCFG_CFGR1_SRAMCACHED SYSCFG_CFGR1_SRAMCACHED_Msk |
| #define | SYSCFG_FPUIMR_FPU_IE_Pos (0U) |
| #define | SYSCFG_FPUIMR_FPU_IE_Msk (0x3FUL << SYSCFG_FPUIMR_FPU_IE_Pos) |
| #define | SYSCFG_FPUIMR_FPU_IE SYSCFG_FPUIMR_FPU_IE_Msk |
| #define | SYSCFG_FPUIMR_FPU_IE_0 (0x1UL << SYSCFG_FPUIMR_FPU_IE_Pos) |
| #define | SYSCFG_FPUIMR_FPU_IE_1 (0x2UL << SYSCFG_FPUIMR_FPU_IE_Pos) |
| #define | SYSCFG_FPUIMR_FPU_IE_2 (0x4UL << SYSCFG_FPUIMR_FPU_IE_Pos) |
| #define | SYSCFG_FPUIMR_FPU_IE_3 (0x8UL << SYSCFG_FPUIMR_FPU_IE_Pos) |
| #define | SYSCFG_FPUIMR_FPU_IE_4 (0x10UL << SYSCFG_FPUIMR_FPU_IE_Pos) |
| #define | SYSCFG_FPUIMR_FPU_IE_5 (0x20UL << SYSCFG_FPUIMR_FPU_IE_Pos) |
| #define | SYSCFG_CNSLCKR_LOCKNSVTOR_Pos (0U) |
| #define | SYSCFG_CNSLCKR_LOCKNSVTOR_Msk (0x1UL << SYSCFG_CNSLCKR_LOCKNSVTOR_Pos) |
| #define | SYSCFG_CNSLCKR_LOCKNSVTOR SYSCFG_CNSLCKR_LOCKNSVTOR_Msk |
| #define | SYSCFG_CNSLCKR_LOCKNSMPU_Pos (1U) |
| #define | SYSCFG_CNSLCKR_LOCKNSMPU_Msk (0x1UL << SYSCFG_CNSLCKR_LOCKNSMPU_Pos) |
| #define | SYSCFG_CNSLCKR_LOCKNSMPU SYSCFG_CNSLCKR_LOCKNSMPU_Msk |
| #define | SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos (0U) |
| #define | SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSVTAIRCR_Pos) |
| #define | SYSCFG_CSLCKR_LOCKSVTAIRCR SYSCFG_CSLCKR_LOCKSVTAIRCR_Msk |
| #define | SYSCFG_CSLCKR_LOCKSMPU_Pos (1U) |
| #define | SYSCFG_CSLCKR_LOCKSMPU_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSMPU_Pos) |
| #define | SYSCFG_CSLCKR_LOCKSMPU SYSCFG_CSLCKR_LOCKSMPU_Msk |
| #define | SYSCFG_CSLCKR_LOCKSAU_Pos (2U) |
| #define | SYSCFG_CSLCKR_LOCKSAU_Msk (0x1UL << SYSCFG_CSLCKR_LOCKSAU_Pos) |
| #define | SYSCFG_CSLCKR_LOCKSAU SYSCFG_CSLCKR_LOCKSAU_Msk |
| #define | SYSCFG_CFGR2_CLL_Pos (0U) |
| #define | SYSCFG_CFGR2_CLL_Msk (0x1UL << SYSCFG_CFGR2_CLL_Pos) |
| #define | SYSCFG_CFGR2_CLL SYSCFG_CFGR2_CLL_Msk |
| #define | SYSCFG_CFGR2_SPL_Pos (1U) |
| #define | SYSCFG_CFGR2_SPL_Msk (0x1UL << SYSCFG_CFGR2_SPL_Pos) |
| #define | SYSCFG_CFGR2_SPL SYSCFG_CFGR2_SPL_Msk |
| #define | SYSCFG_CFGR2_PVDL_Pos (2U) |
| #define | SYSCFG_CFGR2_PVDL_Msk (0x1UL << SYSCFG_CFGR2_PVDL_Pos) |
| #define | SYSCFG_CFGR2_PVDL SYSCFG_CFGR2_PVDL_Msk |
| #define | SYSCFG_CFGR2_ECCL_Pos (3U) |
| #define | SYSCFG_CFGR2_ECCL_Msk (0x1UL << SYSCFG_CFGR2_ECCL_Pos) |
| #define | SYSCFG_CFGR2_ECCL SYSCFG_CFGR2_ECCL_Msk |
| #define | SYSCFG_MESR_MCLR_Pos (0U) |
| #define | SYSCFG_MESR_MCLR_Msk (0x1UL << SYSCFG_MESR_MCLR_Pos) |
| #define | SYSCFG_MESR_MCLR SYSCFG_MESR_MCLR_Msk |
| #define | SYSCFG_MESR_IPMEE_Pos (16U) |
| #define | SYSCFG_MESR_IPMEE_Msk (0x1UL << SYSCFG_MESR_IPMEE_Pos) |
| #define | SYSCFG_MESR_IPMEE SYSCFG_MESR_IPMEE_Msk |
| #define | SYSCFG_CCCSR_EN1_Pos (0U) |
| #define | SYSCFG_CCCSR_EN1_Msk (0x1UL << SYSCFG_CCCSR_EN1_Pos) |
| #define | SYSCFG_CCCSR_EN1 SYSCFG_CCCSR_EN1_Msk |
| #define | SYSCFG_CCCSR_CS1_Pos (1U) |
| #define | SYSCFG_CCCSR_CS1_Msk (0x1UL << SYSCFG_CCCSR_CS1_Pos) |
| #define | SYSCFG_CCCSR_CS1 SYSCFG_CCCSR_CS1_Msk |
| #define | SYSCFG_CCCSR_EN2_Pos (2U) |
| #define | SYSCFG_CCCSR_EN2_Msk (0x1UL << SYSCFG_CCCSR_EN2_Pos) |
| #define | SYSCFG_CCCSR_EN2 SYSCFG_CCCSR_EN2_Msk |
| #define | SYSCFG_CCCSR_CS2_Pos (3U) |
| #define | SYSCFG_CCCSR_CS2_Msk (0x1UL << SYSCFG_CCCSR_CS2_Pos) |
| #define | SYSCFG_CCCSR_CS2 SYSCFG_CCCSR_CS2_Msk |
| #define | SYSCFG_CCCSR_EN3_Pos (4U) |
| #define | SYSCFG_CCCSR_EN3_Msk (0x1UL << SYSCFG_CCCSR_EN3_Pos) |
| #define | SYSCFG_CCCSR_EN3 SYSCFG_CCCSR_EN3_Msk |
| #define | SYSCFG_CCCSR_CS3_Pos (5U) |
| #define | SYSCFG_CCCSR_CS3_Msk (0x1UL << SYSCFG_CCCSR_CS3_Pos) |
| #define | SYSCFG_CCCSR_CS3 SYSCFG_CCCSR_CS3_Msk |
| #define | SYSCFG_CCCSR_RDY1_Pos (8U) |
| #define | SYSCFG_CCCSR_RDY1_Msk (0x1UL << SYSCFG_CCCSR_RDY1_Pos) |
| #define | SYSCFG_CCCSR_RDY1 SYSCFG_CCCSR_RDY1_Msk |
| #define | SYSCFG_CCCSR_RDY2_Pos (9U) |
| #define | SYSCFG_CCCSR_RDY2_Msk (0x1UL << SYSCFG_CCCSR_RDY2_Pos) |
| #define | SYSCFG_CCCSR_RDY2 SYSCFG_CCCSR_RDY2_Msk |
| #define | SYSCFG_CCCSR_RDY3_Pos (10U) |
| #define | SYSCFG_CCCSR_RDY3_Msk (0x1UL << SYSCFG_CCCSR_RDY3_Pos) |
| #define | SYSCFG_CCCSR_RDY3 SYSCFG_CCCSR_RDY3_Msk |
| #define | SYSCFG_CCVR_NCV1_Pos (0U) |
| #define | SYSCFG_CCVR_NCV1_Msk (0xFUL << SYSCFG_CCVR_NCV1_Pos) |
| #define | SYSCFG_CCVR_NCV1 SYSCFG_CCVR_NCV1_Msk |
| #define | SYSCFG_CCVR_PCV1_Pos (4U) |
| #define | SYSCFG_CCVR_PCV1_Msk (0xFUL << SYSCFG_CCVR_PCV1_Pos) |
| #define | SYSCFG_CCVR_PCV1 SYSCFG_CCVR_PCV1_Msk |
| #define | SYSCFG_CCVR_NCV2_Pos (8U) |
| #define | SYSCFG_CCVR_NCV2_Msk (0xFUL << SYSCFG_CCVR_NCV2_Pos) |
| #define | SYSCFG_CCVR_NCV2 SYSCFG_CCVR_NCV2_Msk |
| #define | SYSCFG_CCVR_PCV2_Pos (12U) |
| #define | SYSCFG_CCVR_PCV2_Msk (0xFUL << SYSCFG_CCVR_PCV2_Pos) |
| #define | SYSCFG_CCVR_PCV2 SYSCFG_CCVR_PCV2_Msk |
| #define | SYSCFG_CCVR_NCV3_Pos (16U) |
| #define | SYSCFG_CCVR_NCV3_Msk (0xFUL << SYSCFG_CCVR_NCV3_Pos) |
| #define | SYSCFG_CCVR_NCV3 SYSCFG_CCVR_NCV3_Msk |
| #define | SYSCFG_CCVR_PCV3_Pos (20U) |
| #define | SYSCFG_CCVR_PCV3_Msk (0xFUL << SYSCFG_CCVR_PCV3_Pos) |
| #define | SYSCFG_CCVR_PCV3 SYSCFG_CCVR_PCV3_Msk |
| #define | SYSCFG_CCCR_NCC1_Pos (0U) |
| #define | SYSCFG_CCCR_NCC1_Msk (0xFUL << SYSCFG_CCCR_NCC1_Pos) |
| #define | SYSCFG_CCCR_NCC1 SYSCFG_CCCR_NCC1_Msk |
| #define | SYSCFG_CCCR_PCC1_Pos (4U) |
| #define | SYSCFG_CCCR_PCC1_Msk (0xFUL << SYSCFG_CCCR_PCC1_Pos) |
| #define | SYSCFG_CCCR_PCC1 SYSCFG_CCCR_PCC1_Msk |
| #define | SYSCFG_CCCR_NCC2_Pos (8U) |
| #define | SYSCFG_CCCR_NCC2_Msk (0xFUL << SYSCFG_CCCR_NCC2_Pos) |
| #define | SYSCFG_CCCR_NCC2 SYSCFG_CCCR_NCC2_Msk |
| #define | SYSCFG_CCCR_PCC2_Pos (12U) |
| #define | SYSCFG_CCCR_PCC2_Msk (0xFUL << SYSCFG_CCCR_PCC2_Pos) |
| #define | SYSCFG_CCCR_PCC2 SYSCFG_CCCR_PCC2_Msk |
| #define | SYSCFG_CCCR_NCC3_Pos (16U) |
| #define | SYSCFG_CCCR_NCC3_Msk (0xFUL << SYSCFG_CCCR_NCC3_Pos) |
| #define | SYSCFG_CCCR_NCC3 SYSCFG_CCCR_NCC3_Msk |
| #define | SYSCFG_CCCR_PCC3_Pos (20U) |
| #define | SYSCFG_CCCR_PCC3_Msk (0xFUL << SYSCFG_CCCR_PCC3_Pos) |
| #define | SYSCFG_CCCR_PCC3 SYSCFG_CCCR_PCC3_Msk |
| #define | SYSCFG_RSSCMDR_RSSCMD_Pos (0U) |
| #define | SYSCFG_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SYSCFG_RSSCMDR_RSSCMD_Pos) |
| #define | SYSCFG_RSSCMDR_RSSCMD SYSCFG_RSSCMDR_RSSCMD_Msk |
| #define | SYSCFG_OTGHSPHYCR_EN_Pos (0U) |
| #define | SYSCFG_OTGHSPHYCR_EN_Msk (0x1UL << SYSCFG_OTGHSPHYCR_EN_Pos) |
| #define | SYSCFG_OTGHSPHYCR_EN SYSCFG_OTGHSPHYCR_EN_Msk |
| #define | SYSCFG_OTGHSPHYCR_PDCTRL_Pos (1U) |
| #define | SYSCFG_OTGHSPHYCR_PDCTRL_Msk (0x1UL << SYSCFG_OTGHSPHYCR_PDCTRL_Pos) |
| #define | SYSCFG_OTGHSPHYCR_PDCTRL SYSCFG_OTGHSPHYCR_PDCTRL_Msk |
| #define | SYSCFG_OTGHSPHYCR_CLKSEL_Pos (2U) |
| #define | SYSCFG_OTGHSPHYCR_CLKSEL_Msk (0xFUL << SYSCFG_OTGHSPHYCR_CLKSEL_Pos) |
| #define | SYSCFG_OTGHSPHYCR_CLKSEL SYSCFG_OTGHSPHYCR_CLKSEL_Msk |
| #define | SYSCFG_OTGHSPHYCR_CLKSEL_0 (0x1UL << SYSCFG_OTGHSPHYCR_CLKSEL_Pos) |
| #define | SYSCFG_OTGHSPHYCR_CLKSEL_1 (0x2UL << SYSCFG_OTGHSPHYCR_CLKSEL_Pos) |
| #define | SYSCFG_OTGHSPHYCR_CLKSEL_2 (0x4UL << SYSCFG_OTGHSPHYCR_CLKSEL_Pos) |
| #define | SYSCFG_OTGHSPHYCR_CLKSEL_3 (0x8UL << SYSCFG_OTGHSPHYCR_CLKSEL_Pos) |
| #define | SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_Pos (0U) |
| #define | SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_Msk (0x7UL << SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_Pos) |
| #define | SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_Msk |
| #define | SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 (0x1UL << SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_Pos) |
| #define | SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 (0x2UL << SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_Pos) |
| #define | SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_2 (0x4UL << SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_Pos) |
| #define | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_Pos (4U) |
| #define | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_Msk (0x7UL << SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_Pos) |
| #define | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_Msk |
| #define | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 (0x1UL << SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_Pos) |
| #define | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1 (0x2UL << SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_Pos) |
| #define | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_2 (0x4UL << SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_Pos) |
| #define | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_Pos (13U) |
| #define | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_Msk (0x3UL << SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_Pos) |
| #define | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_Msk |
| #define | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 (0x1UL << SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_Pos) |
| #define | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 (0x2UL << SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_Pos) |
| #define | GTZC_TZSC_CR_LCK_Pos (0U) |
| #define | GTZC_TZSC_CR_LCK_Msk (0x01UL << GTZC_TZSC_CR_LCK_Pos) |
| #define | GTZC_TZSC_MPCWM_CFGR_SREN_Pos (0U) |
| #define | GTZC_TZSC_MPCWM_CFGR_SREN_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SREN_Pos) |
| #define | GTZC_TZSC_MPCWM_CFGR_SREN GTZC_TZSC_MPCWM_CFGR_SREN_Msk |
| #define | GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos (1U) |
| #define | GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos) |
| #define | GTZC_TZSC_MPCWM_CFGR_SRLOCK GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk |
| #define | GTZC_TZSC_MPCWM_CFGR_SEC_Pos (8U) |
| #define | GTZC_TZSC_MPCWM_CFGR_SEC_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) |
| #define | GTZC_TZSC_MPCWM_CFGR_SEC GTZC_TZSC_MPCWM_CFGR_SEC_Msk |
| #define | GTZC_TZSC_MPCWM_CFGR_PRIV_Pos (9U) |
| #define | GTZC_TZSC_MPCWM_CFGR_PRIV_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_PRIV_Pos) |
| #define | GTZC_TZSC_MPCWM_CFGR_PRIV GTZC_TZSC_MPCWM_CFGR_PRIV_Msk |
| #define | GTZC_TZSC_MPCWMR_SUBZ_START_Pos (0U) |
| #define | GTZC_TZSC_MPCWMR_SUBZ_START_Msk (0x7FFUL << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) |
| #define | GTZC_TZSC_MPCWMR_SUBZ_START GTZC_TZSC_MPCWMR_SUBZ_START_Msk |
| #define | GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos (16U) |
| #define | GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) |
| #define | GTZC_TZSC_MPCWMR_SUBZ_LENGTH GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk |
| #define | GTZC_CFGR1_TIM2_Pos (0U) |
| #define | GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) |
| #define | GTZC_CFGR1_TIM3_Pos (1U) |
| #define | GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) |
| #define | GTZC_CFGR1_TIM4_Pos (2U) |
| #define | GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) |
| #define | GTZC_CFGR1_TIM5_Pos (3U) |
| #define | GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos) |
| #define | GTZC_CFGR1_TIM6_Pos (4U) |
| #define | GTZC_CFGR1_TIM6_Msk (0x01UL << GTZC_CFGR1_TIM6_Pos) |
| #define | GTZC_CFGR1_TIM7_Pos (5U) |
| #define | GTZC_CFGR1_TIM7_Msk (0x01UL << GTZC_CFGR1_TIM7_Pos) |
| #define | GTZC_CFGR1_WWDG_Pos (6U) |
| #define | GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) |
| #define | GTZC_CFGR1_IWDG_Pos (7U) |
| #define | GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) |
| #define | GTZC_CFGR1_SPI2_Pos (8U) |
| #define | GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos) |
| #define | GTZC_CFGR1_USART2_Pos (9U) |
| #define | GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) |
| #define | GTZC_CFGR1_USART3_Pos (10U) |
| #define | GTZC_CFGR1_USART3_Msk (0x01UL << GTZC_CFGR1_USART3_Pos) |
| #define | GTZC_CFGR1_UART4_Pos (11U) |
| #define | GTZC_CFGR1_UART4_Msk (0x01UL << GTZC_CFGR1_UART4_Pos) |
| #define | GTZC_CFGR1_UART5_Pos (12U) |
| #define | GTZC_CFGR1_UART5_Msk (0x01UL << GTZC_CFGR1_UART5_Pos) |
| #define | GTZC_CFGR1_I2C1_Pos (13U) |
| #define | GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) |
| #define | GTZC_CFGR1_I2C2_Pos (14U) |
| #define | GTZC_CFGR1_I2C2_Msk (0x01UL << GTZC_CFGR1_I2C2_Pos) |
| #define | GTZC_CFGR1_CRS_Pos (15U) |
| #define | GTZC_CFGR1_CRS_Msk (0x01UL << GTZC_CFGR1_CRS_Pos) |
| #define | GTZC_CFGR1_I2C4_Pos (16U) |
| #define | GTZC_CFGR1_I2C4_Msk (0x01UL << GTZC_CFGR1_I2C4_Pos) |
| #define | GTZC_CFGR1_LPTIM2_Pos (17U) |
| #define | GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) |
| #define | GTZC_CFGR1_FDCAN1_Pos (18U) |
| #define | GTZC_CFGR1_FDCAN1_Msk (0x01UL << GTZC_CFGR1_FDCAN1_Pos) |
| #define | GTZC_CFGR1_UCPD1_Pos (19U) |
| #define | GTZC_CFGR1_UCPD1_Msk (0x01UL << GTZC_CFGR1_UCPD1_Pos) |
| #define | GTZC_CFGR1_USART6_Pos (21U) |
| #define | GTZC_CFGR1_USART6_Msk (0x01UL << GTZC_CFGR1_USART6_Pos) |
| #define | GTZC_CFGR1_I2C5_Pos (22U) |
| #define | GTZC_CFGR1_I2C5_Msk (0x01UL << GTZC_CFGR1_I2C5_Pos) |
| #define | GTZC_CFGR1_I2C6_Pos (23U) |
| #define | GTZC_CFGR1_I2C6_Msk (0x01UL << GTZC_CFGR1_I2C6_Pos) |
| #define | GTZC_CFGR2_TIM1_Pos (0U) |
| #define | GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) |
| #define | GTZC_CFGR2_SPI1_Pos (1U) |
| #define | GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) |
| #define | GTZC_CFGR2_TIM8_Pos (2U) |
| #define | GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos) |
| #define | GTZC_CFGR2_USART1_Pos (3U) |
| #define | GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) |
| #define | GTZC_CFGR2_TIM15_Pos (4U) |
| #define | GTZC_CFGR2_TIM15_Msk (0x01UL << GTZC_CFGR2_TIM15_Pos) |
| #define | GTZC_CFGR2_TIM16_Pos (5U) |
| #define | GTZC_CFGR2_TIM16_Msk (0x01UL << GTZC_CFGR2_TIM16_Pos) |
| #define | GTZC_CFGR2_TIM17_Pos (6U) |
| #define | GTZC_CFGR2_TIM17_Msk (0x01UL << GTZC_CFGR2_TIM17_Pos) |
| #define | GTZC_CFGR2_SAI1_Pos (7U) |
| #define | GTZC_CFGR2_SAI1_Msk (0x01UL << GTZC_CFGR2_SAI1_Pos) |
| #define | GTZC_CFGR2_SAI2_Pos (8U) |
| #define | GTZC_CFGR2_SAI2_Msk (0x01UL << GTZC_CFGR2_SAI2_Pos) |
| #define | GTZC_CFGR2_LTDCUSB_Pos (9U) |
| #define | GTZC_CFGR2_LTDCUSB_Msk (0x01UL << GTZC_CFGR2_LTDCUSB_Pos) |
| #define | GTZC_CFGR2_DSI_Pos (10U) |
| #define | GTZC_CFGR2_DSI_Msk (0x01UL << GTZC_CFGR2_DSI_Pos) |
| #define | GTZC_CFGR2_GFXTIM_Pos (11U) |
| #define | GTZC_CFGR2_GFXTIM_Msk (0x01UL << GTZC_CFGR2_GFXTIM_Pos) |
| #define | GTZC_CFGR3_MDF1_Pos (0U) |
| #define | GTZC_CFGR3_MDF1_Msk (0x01UL << GTZC_CFGR3_MDF1_Pos) |
| #define | GTZC_CFGR3_CORDIC_Pos (1U) |
| #define | GTZC_CFGR3_CORDIC_Msk (0x01UL << GTZC_CFGR3_CORDIC_Pos) |
| #define | GTZC_CFGR3_FMAC_Pos (2U) |
| #define | GTZC_CFGR3_FMAC_Msk (0x01UL << GTZC_CFGR3_FMAC_Pos) |
| #define | GTZC_CFGR3_CRC_Pos (3U) |
| #define | GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) |
| #define | GTZC_CFGR3_TSC_Pos (4U) |
| #define | GTZC_CFGR3_TSC_Msk (0x01UL << GTZC_CFGR3_TSC_Pos) |
| #define | GTZC_CFGR3_DMA2D_Pos (5U) |
| #define | GTZC_CFGR3_DMA2D_Msk (0x01UL << GTZC_CFGR3_DMA2D_Pos) |
| #define | GTZC_CFGR3_ICACHE_REG_Pos (6U) |
| #define | GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) |
| #define | GTZC_CFGR3_DCACHE1_REG_Pos (7U) |
| #define | GTZC_CFGR3_DCACHE1_REG_Msk (0x01UL << GTZC_CFGR3_DCACHE1_REG_Pos) |
| #define | GTZC_CFGR3_ADC12_Pos (8U) |
| #define | GTZC_CFGR3_ADC12_Msk (0x01UL << GTZC_CFGR3_ADC12_Pos) |
| #define | GTZC_CFGR3_DCMI_Pos (9U) |
| #define | GTZC_CFGR3_DCMI_Msk (0x01UL << GTZC_CFGR3_DCMI_Pos) |
| #define | GTZC_CFGR3_OTG_Pos (10U) |
| #define | GTZC_CFGR3_OTG_Msk (0x01UL << GTZC_CFGR3_OTG_Pos) |
| #define | GTZC_CFGR3_AES_Pos (11U) |
| #define | GTZC_CFGR3_AES_Msk (0x01UL << GTZC_CFGR3_AES_Pos) |
| #define | GTZC_CFGR3_HASH_Pos (12U) |
| #define | GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) |
| #define | GTZC_CFGR3_RNG_Pos (13U) |
| #define | GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) |
| #define | GTZC_CFGR3_PKA_Pos (14U) |
| #define | GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos) |
| #define | GTZC_CFGR3_SAES_Pos (15U) |
| #define | GTZC_CFGR3_SAES_Msk (0x01UL << GTZC_CFGR3_SAES_Pos) |
| #define | GTZC_CFGR3_OCTOSPIM_Pos (16U) |
| #define | GTZC_CFGR3_OCTOSPIM_Msk (0x01UL << GTZC_CFGR3_OCTOSPIM_Pos) |
| #define | GTZC_CFGR3_SDMMC1_Pos (17U) |
| #define | GTZC_CFGR3_SDMMC1_Msk (0x01UL << GTZC_CFGR3_SDMMC1_Pos) |
| #define | GTZC_CFGR3_SDMMC2_Pos (18U) |
| #define | GTZC_CFGR3_SDMMC2_Msk (0x01UL << GTZC_CFGR3_SDMMC2_Pos) |
| #define | GTZC_CFGR3_FSMC_REG_Pos (19U) |
| #define | GTZC_CFGR3_FSMC_REG_Msk (0x01UL << GTZC_CFGR3_FSMC_REG_Pos) |
| #define | GTZC_CFGR3_OCTOSPI1_REG_Pos (20U) |
| #define | GTZC_CFGR3_OCTOSPI1_REG_Msk (0x01UL << GTZC_CFGR3_OCTOSPI1_REG_Pos) |
| #define | GTZC_CFGR3_OCTOSPI2_REG_Pos (21U) |
| #define | GTZC_CFGR3_OCTOSPI2_REG_Msk (0x01UL << GTZC_CFGR3_OCTOSPI2_REG_Pos) |
| #define | GTZC_CFGR3_RAMCFG_Pos (22U) |
| #define | GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) |
| #define | GTZC_CFGR3_GPU2D_Pos (23U) |
| #define | GTZC_CFGR3_GPU2D_Msk (0x01UL << GTZC_CFGR3_GPU2D_Pos) |
| #define | GTZC_CFGR3_GFXMMU_Pos (24U) |
| #define | GTZC_CFGR3_GFXMMU_Msk (0x01UL << GTZC_CFGR3_GFXMMU_Pos) |
| #define | GTZC_CFGR3_GFXMMU_REG_Pos (25U) |
| #define | GTZC_CFGR3_GFXMMU_REG_Msk (0x01UL << GTZC_CFGR3_GFXMMU_REG_Pos) |
| #define | GTZC_CFGR3_HSPI1_REG_Pos (26U) |
| #define | GTZC_CFGR3_HSPI1_REG_Msk (0x01UL << GTZC_CFGR3_HSPI1_REG_Pos) |
| #define | GTZC_CFGR3_DCACHE2_REG_Pos (27U) |
| #define | GTZC_CFGR3_DCACHE2_REG_Msk (0x01UL << GTZC_CFGR3_DCACHE2_REG_Pos) |
| #define | GTZC_CFGR3_JPEG_Pos (28U) |
| #define | GTZC_CFGR3_JPEG_Msk (0x01UL << GTZC_CFGR3_JPEG_Pos) |
| #define | GTZC_CFGR4_GPDMA1_Pos (0U) |
| #define | GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) |
| #define | GTZC_CFGR4_FLASH_REG_Pos (1U) |
| #define | GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) |
| #define | GTZC_CFGR4_FLASH_Pos (2U) |
| #define | GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) |
| #define | GTZC_CFGR4_OTFDEC1_Pos (3U) |
| #define | GTZC_CFGR4_OTFDEC1_Msk (0x01UL << GTZC_CFGR4_OTFDEC1_Pos) |
| #define | GTZC_CFGR4_OTFDEC2_Pos (4U) |
| #define | GTZC_CFGR4_OTFDEC2_Msk (0x01UL << GTZC_CFGR4_OTFDEC2_Pos) |
| #define | GTZC_CFGR4_TZSC1_Pos (14U) |
| #define | GTZC_CFGR4_TZSC1_Msk (0x01UL << GTZC_CFGR4_TZSC1_Pos) |
| #define | GTZC_CFGR4_TZIC1_Pos (15U) |
| #define | GTZC_CFGR4_TZIC1_Msk (0x01UL << GTZC_CFGR4_TZIC1_Pos) |
| #define | GTZC_CFGR4_OCTOSPI1_MEM_Pos (16U) |
| #define | GTZC_CFGR4_OCTOSPI1_MEM_Msk (0x01UL << GTZC_CFGR4_OCTOSPI1_MEM_Pos) |
| #define | GTZC_CFGR4_FSMC_MEM_Pos (17U) |
| #define | GTZC_CFGR4_FSMC_MEM_Msk (0x01UL << GTZC_CFGR4_FSMC_MEM_Pos) |
| #define | GTZC_CFGR4_BKPSRAM_Pos (18U) |
| #define | GTZC_CFGR4_BKPSRAM_Msk (0x01UL << GTZC_CFGR4_BKPSRAM_Pos) |
| #define | GTZC_CFGR4_OCTOSPI2_MEM_Pos (19U) |
| #define | GTZC_CFGR4_OCTOSPI2_MEM_Msk (0x01UL << GTZC_CFGR4_OCTOSPI2_MEM_Pos) |
| #define | GTZC_CFGR4_HSPI1_MEM_Pos (20U) |
| #define | GTZC_CFGR4_HSPI1_MEM_Msk (0x01UL << GTZC_CFGR4_HSPI1_MEM_Pos) |
| #define | GTZC_CFGR4_SRAM6_Pos (22U) |
| #define | GTZC_CFGR4_SRAM6_Msk (0x01UL << GTZC_CFGR4_SRAM6_Pos) |
| #define | GTZC_CFGR4_MPCBB6_REG_Pos (23U) |
| #define | GTZC_CFGR4_MPCBB6_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB6_REG_Pos) |
| #define | GTZC_CFGR4_SRAM1_Pos (24U) |
| #define | GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) |
| #define | GTZC_CFGR4_MPCBB1_REG_Pos (25U) |
| #define | GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) |
| #define | GTZC_CFGR4_SRAM2_Pos (26U) |
| #define | GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) |
| #define | GTZC_CFGR4_MPCBB2_REG_Pos (27U) |
| #define | GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) |
| #define | GTZC_CFGR4_SRAM3_Pos (28U) |
| #define | GTZC_CFGR4_SRAM3_Msk (0x01UL << GTZC_CFGR4_SRAM3_Pos) |
| #define | GTZC_CFGR4_MPCBB3_REG_Pos (29U) |
| #define | GTZC_CFGR4_MPCBB3_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB3_REG_Pos) |
| #define | GTZC_CFGR4_SRAM5_Pos (30U) |
| #define | GTZC_CFGR4_SRAM5_Msk (0x01UL << GTZC_CFGR4_SRAM5_Pos) |
| #define | GTZC_CFGR4_MPCBB5_REG_Pos (31U) |
| #define | GTZC_CFGR4_MPCBB5_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB5_REG_Pos) |
| #define | GTZC_CFGR1_SPI3_Pos (0U) |
| #define | GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos) |
| #define | GTZC_CFGR1_LPUART1_Pos (1U) |
| #define | GTZC_CFGR1_LPUART1_Msk (0x01UL << GTZC_CFGR1_LPUART1_Pos) |
| #define | GTZC_CFGR1_I2C3_Pos (2U) |
| #define | GTZC_CFGR1_I2C3_Msk (0x01UL << GTZC_CFGR1_I2C3_Pos) |
| #define | GTZC_CFGR1_LPTIM1_Pos (3U) |
| #define | GTZC_CFGR1_LPTIM1_Msk (0x01UL << GTZC_CFGR1_LPTIM1_Pos) |
| #define | GTZC_CFGR1_LPTIM3_Pos (4U) |
| #define | GTZC_CFGR1_LPTIM3_Msk (0x01UL << GTZC_CFGR1_LPTIM3_Pos) |
| #define | GTZC_CFGR1_LPTIM4_Pos (5U) |
| #define | GTZC_CFGR1_LPTIM4_Msk (0x01UL << GTZC_CFGR1_LPTIM4_Pos) |
| #define | GTZC_CFGR1_OPAMP_Pos (6U) |
| #define | GTZC_CFGR1_OPAMP_Msk (0x01UL << GTZC_CFGR1_OPAMP_Pos) |
| #define | GTZC_CFGR1_COMP_Pos (7U) |
| #define | GTZC_CFGR1_COMP_Msk (0x01UL << GTZC_CFGR1_COMP_Pos) |
| #define | GTZC_CFGR1_ADC4_Pos (8U) |
| #define | GTZC_CFGR1_ADC4_Msk (0x01UL << GTZC_CFGR1_ADC4_Pos) |
| #define | GTZC_CFGR1_VREFBUF_Pos (9U) |
| #define | GTZC_CFGR1_VREFBUF_Msk (0x01UL << GTZC_CFGR1_VREFBUF_Pos) |
| #define | GTZC_CFGR1_DAC1_Pos (11U) |
| #define | GTZC_CFGR1_DAC1_Msk (0x01UL << GTZC_CFGR1_DAC1_Pos) |
| #define | GTZC_CFGR1_ADF1_Pos (12U) |
| #define | GTZC_CFGR1_ADF1_Msk (0x01UL << GTZC_CFGR1_ADF1_Pos) |
| #define | GTZC_CFGR2_SYSCFG_Pos (0U) |
| #define | GTZC_CFGR2_SYSCFG_Msk (0x01UL << GTZC_CFGR2_SYSCFG_Pos) |
| #define | GTZC_CFGR2_RTC_Pos (1U) |
| #define | GTZC_CFGR2_RTC_Msk (0x01UL << GTZC_CFGR2_RTC_Pos) |
| #define | GTZC_CFGR2_TAMP_Pos (2U) |
| #define | GTZC_CFGR2_TAMP_Msk (0x01UL << GTZC_CFGR2_TAMP_Pos) |
| #define | GTZC_CFGR2_PWR_Pos (3U) |
| #define | GTZC_CFGR2_PWR_Msk (0x01UL << GTZC_CFGR2_PWR_Pos) |
| #define | GTZC_CFGR2_RCC_Pos (4U) |
| #define | GTZC_CFGR2_RCC_Msk (0x01UL << GTZC_CFGR2_RCC_Pos) |
| #define | GTZC_CFGR2_LPDMA1_Pos (5U) |
| #define | GTZC_CFGR2_LPDMA1_Msk (0x01UL << GTZC_CFGR2_LPDMA1_Pos) |
| #define | GTZC_CFGR2_EXTI_Pos (6U) |
| #define | GTZC_CFGR2_EXTI_Msk (0x01UL << GTZC_CFGR2_EXTI_Pos) |
| #define | GTZC_CFGR2_TZSC2_Pos (14U) |
| #define | GTZC_CFGR2_TZSC2_Msk (0x01UL << GTZC_CFGR2_TZSC2_Pos) |
| #define | GTZC_CFGR2_TZIC2_Pos (15U) |
| #define | GTZC_CFGR2_TZIC2_Msk (0x01UL << GTZC_CFGR2_TZIC2_Pos) |
| #define | GTZC_CFGR2_SRAM4_Pos (24U) |
| #define | GTZC_CFGR2_SRAM4_Msk (0x01UL << GTZC_CFGR2_SRAM4_Pos) |
| #define | GTZC_CFGR2_MPCBB4_REG_Pos (25U) |
| #define | GTZC_CFGR2_MPCBB4_REG_Msk (0x01UL << GTZC_CFGR2_MPCBB4_REG_Pos) |
| #define | GTZC_TZSC1_SECCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos |
| #define | GTZC_TZSC1_SECCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk |
| #define | GTZC_TZSC1_SECCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos |
| #define | GTZC_TZSC1_SECCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk |
| #define | GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos |
| #define | GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk |
| #define | GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos |
| #define | GTZC_TZSC1_SECCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk |
| #define | GTZC_TZSC1_SECCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos |
| #define | GTZC_TZSC1_SECCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk |
| #define | GTZC_TZSC1_SECCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos |
| #define | GTZC_TZSC1_SECCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk |
| #define | GTZC_TZSC1_SECCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos |
| #define | GTZC_TZSC1_SECCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk |
| #define | GTZC_TZSC1_SECCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos |
| #define | GTZC_TZSC1_SECCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk |
| #define | GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos |
| #define | GTZC_TZSC1_SECCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk |
| #define | GTZC_TZSC1_SECCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos |
| #define | GTZC_TZSC1_SECCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk |
| #define | GTZC_TZSC1_SECCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos |
| #define | GTZC_TZSC1_SECCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk |
| #define | GTZC_TZSC1_SECCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos |
| #define | GTZC_TZSC1_SECCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk |
| #define | GTZC_TZSC1_SECCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos |
| #define | GTZC_TZSC1_SECCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk |
| #define | GTZC_TZSC1_SECCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos |
| #define | GTZC_TZSC1_SECCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk |
| #define | GTZC_TZSC1_SECCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos |
| #define | GTZC_TZSC1_SECCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk |
| #define | GTZC_TZSC1_SECCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos |
| #define | GTZC_TZSC1_SECCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk |
| #define | GTZC_TZSC1_SECCFGR1_I2C4_Pos GTZC_CFGR1_I2C4_Pos |
| #define | GTZC_TZSC1_SECCFGR1_I2C4_Msk GTZC_CFGR1_I2C4_Msk |
| #define | GTZC_TZSC1_SECCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos |
| #define | GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk |
| #define | GTZC_TZSC1_SECCFGR1_FDCAN1_Pos GTZC_CFGR1_FDCAN1_Pos |
| #define | GTZC_TZSC1_SECCFGR1_FDCAN1_Msk GTZC_CFGR1_FDCAN1_Msk |
| #define | GTZC_TZSC1_SECCFGR1_UCPD1_Pos GTZC_CFGR1_UCPD1_Pos |
| #define | GTZC_TZSC1_SECCFGR1_UCPD1_Msk GTZC_CFGR1_UCPD1_Msk |
| #define | GTZC_TZSC1_SECCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos |
| #define | GTZC_TZSC1_SECCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk |
| #define | GTZC_TZSC1_SECCFGR1_I2C5_Pos GTZC_CFGR1_I2C5_Pos |
| #define | GTZC_TZSC1_SECCFGR1_I2C5_Msk GTZC_CFGR1_I2C5_Msk |
| #define | GTZC_TZSC1_SECCFGR1_I2C6_Pos GTZC_CFGR1_I2C6_Pos |
| #define | GTZC_TZSC1_SECCFGR1_I2C6_Msk GTZC_CFGR1_I2C6_Msk |
| #define | GTZC_TZSC1_SECCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos |
| #define | GTZC_TZSC1_SECCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk |
| #define | GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos |
| #define | GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk |
| #define | GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos |
| #define | GTZC_TZSC1_SECCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk |
| #define | GTZC_TZSC1_SECCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos |
| #define | GTZC_TZSC1_SECCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk |
| #define | GTZC_TZSC1_SECCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos |
| #define | GTZC_TZSC1_SECCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk |
| #define | GTZC_TZSC1_SECCFGR2_TIM16_Pos GTZC_CFGR2_TIM16_Pos |
| #define | GTZC_TZSC1_SECCFGR2_TIM16_Msk GTZC_CFGR2_TIM16_Msk |
| #define | GTZC_TZSC1_SECCFGR2_TIM17_Pos GTZC_CFGR2_TIM17_Pos |
| #define | GTZC_TZSC1_SECCFGR2_TIM17_Msk GTZC_CFGR2_TIM17_Msk |
| #define | GTZC_TZSC1_SECCFGR2_SAI1_Pos GTZC_CFGR2_SAI1_Pos |
| #define | GTZC_TZSC1_SECCFGR2_SAI1_Msk GTZC_CFGR2_SAI1_Msk |
| #define | GTZC_TZSC1_SECCFGR2_SAI2_Pos GTZC_CFGR2_SAI2_Pos |
| #define | GTZC_TZSC1_SECCFGR2_SAI2_Msk GTZC_CFGR2_SAI2_Msk |
| #define | GTZC_TZSC1_SECCFGR2_LTDCUSB_Pos GTZC_CFGR2_LTDCUSB_Pos |
| #define | GTZC_TZSC1_SECCFGR2_LTDCUSB_Msk GTZC_CFGR2_LTDCUSB_Msk |
| #define | GTZC_TZSC1_SECCFGR2_DSI_Pos GTZC_CFGR2_DSI_Pos |
| #define | GTZC_TZSC1_SECCFGR2_DSI_Msk GTZC_CFGR2_DSI_Msk |
| #define | GTZC_TZSC1_SECCFGR2_GFXTIM_Pos GTZC_CFGR2_GFXTIM_Pos |
| #define | GTZC_TZSC1_SECCFGR2_GFXTIM_Msk GTZC_CFGR2_GFXTIM_Msk |
| #define | GTZC_TZSC1_SECCFGR3_MDF1_Pos GTZC_CFGR3_MDF1_Pos |
| #define | GTZC_TZSC1_SECCFGR3_MDF1_Msk GTZC_CFGR3_MDF1_Msk |
| #define | GTZC_TZSC1_SECCFGR3_CORDIC_Pos GTZC_CFGR3_CORDIC_Pos |
| #define | GTZC_TZSC1_SECCFGR3_CORDIC_Msk GTZC_CFGR3_CORDIC_Msk |
| #define | GTZC_TZSC1_SECCFGR3_FMAC_Pos GTZC_CFGR3_FMAC_Pos |
| #define | GTZC_TZSC1_SECCFGR3_FMAC_Msk GTZC_CFGR3_FMAC_Msk |
| #define | GTZC_TZSC1_SECCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos |
| #define | GTZC_TZSC1_SECCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk |
| #define | GTZC_TZSC1_SECCFGR3_TSC_Pos GTZC_CFGR3_TSC_Pos |
| #define | GTZC_TZSC1_SECCFGR3_TSC_Msk GTZC_CFGR3_TSC_Msk |
| #define | GTZC_TZSC1_SECCFGR3_DMA2D_Pos GTZC_CFGR3_DMA2D_Pos |
| #define | GTZC_TZSC1_SECCFGR3_DMA2D_Msk GTZC_CFGR3_DMA2D_Msk |
| #define | GTZC_TZSC1_SECCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos |
| #define | GTZC_TZSC1_SECCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk |
| #define | GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos |
| #define | GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk |
| #define | GTZC_TZSC1_SECCFGR3_ADC12_Pos GTZC_CFGR3_ADC12_Pos |
| #define | GTZC_TZSC1_SECCFGR3_ADC12_Msk GTZC_CFGR3_ADC12_Msk |
| #define | GTZC_TZSC1_SECCFGR3_DCMI_Pos GTZC_CFGR3_DCMI_Pos |
| #define | GTZC_TZSC1_SECCFGR3_DCMI_Msk GTZC_CFGR3_DCMI_Msk |
| #define | GTZC_TZSC1_SECCFGR3_OTG_Pos GTZC_CFGR3_OTG_Pos |
| #define | GTZC_TZSC1_SECCFGR3_OTG_Msk GTZC_CFGR3_OTG_Msk |
| #define | GTZC_TZSC1_SECCFGR3_AES_Pos GTZC_CFGR3_AES_Pos |
| #define | GTZC_TZSC1_SECCFGR3_AES_Msk GTZC_CFGR3_AES_Msk |
| #define | GTZC_TZSC1_SECCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos |
| #define | GTZC_TZSC1_SECCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk |
| #define | GTZC_TZSC1_SECCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos |
| #define | GTZC_TZSC1_SECCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk |
| #define | GTZC_TZSC1_SECCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos |
| #define | GTZC_TZSC1_SECCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk |
| #define | GTZC_TZSC1_SECCFGR3_SAES_Pos GTZC_CFGR3_SAES_Pos |
| #define | GTZC_TZSC1_SECCFGR3_SAES_Msk GTZC_CFGR3_SAES_Msk |
| #define | GTZC_TZSC1_SECCFGR3_OCTOSPIM_Pos GTZC_CFGR3_OCTOSPIM_Pos |
| #define | GTZC_TZSC1_SECCFGR3_OCTOSPIM_Msk GTZC_CFGR3_OCTOSPIM_Msk |
| #define | GTZC_TZSC1_SECCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos |
| #define | GTZC_TZSC1_SECCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk |
| #define | GTZC_TZSC1_SECCFGR3_SDMMC2_Pos GTZC_CFGR3_SDMMC2_Pos |
| #define | GTZC_TZSC1_SECCFGR3_SDMMC2_Msk GTZC_CFGR3_SDMMC2_Msk |
| #define | GTZC_TZSC1_SECCFGR3_FSMC_REG_Pos GTZC_CFGR3_FSMC_REG_Pos |
| #define | GTZC_TZSC1_SECCFGR3_FSMC_REG_Msk GTZC_CFGR3_FSMC_REG_Msk |
| #define | GTZC_TZSC1_SECCFGR3_OCTOSPI1_REG_Pos GTZC_CFGR3_OCTOSPI1_REG_Pos |
| #define | GTZC_TZSC1_SECCFGR3_OCTOSPI1_REG_Msk GTZC_CFGR3_OCTOSPI1_REG_Msk |
| #define | GTZC_TZSC1_SECCFGR3_OCTOSPI2_REG_Pos GTZC_CFGR3_OCTOSPI2_REG_Pos |
| #define | GTZC_TZSC1_SECCFGR3_OCTOSPI2_REG_Msk GTZC_CFGR3_OCTOSPI2_REG_Msk |
| #define | GTZC_TZSC1_SECCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos |
| #define | GTZC_TZSC1_SECCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk |
| #define | GTZC_TZSC1_SECCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos |
| #define | GTZC_TZSC1_SECCFGR3_GPU2D_Msk GTZC_CFGR3_GPU2D_Msk |
| #define | GTZC_TZSC1_SECCFGR3_GFXMMU_Pos GTZC_CFGR3_GFXMMU_Pos |
| #define | GTZC_TZSC1_SECCFGR3_GFXMMU_Msk GTZC_CFGR3_GFXMMU_Msk |
| #define | GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos |
| #define | GTZC_TZSC1_SECCFGR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk |
| #define | GTZC_TZSC1_SECCFGR3_HSPI1_REG_Pos GTZC_CFGR3_HSPI1_REG_Pos |
| #define | GTZC_TZSC1_SECCFGR3_HSPI1_REG_Msk GTZC_CFGR3_HSPI1_REG_Msk |
| #define | GTZC_TZSC1_SECCFGR3_DCACHE2_REG_Pos GTZC_CFGR3_DCACHE2_REG_Pos |
| #define | GTZC_TZSC1_SECCFGR3_DCACHE2_REG_Msk GTZC_CFGR3_DCACHE2_REG_Msk |
| #define | GTZC_TZSC1_SECCFGR3_JPEG_Pos GTZC_CFGR3_JPEG_REG_Pos |
| #define | GTZC_TZSC1_SECCFGR3_JPEG_Msk GTZC_CFGR3_JPEG_REG_Msk |
| #define | GTZC_TZSC2_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos |
| #define | GTZC_TZSC2_SECCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk |
| #define | GTZC_TZSC2_SECCFGR1_LPUART1_Pos GTZC_CFGR1_LPUART1_Pos |
| #define | GTZC_TZSC2_SECCFGR1_LPUART1_Msk GTZC_CFGR1_LPUART1_Msk |
| #define | GTZC_TZSC2_SECCFGR1_I2C3_Pos GTZC_CFGR1_I2C3_Pos |
| #define | GTZC_TZSC2_SECCFGR1_I2C3_Msk GTZC_CFGR1_I2C3_Msk |
| #define | GTZC_TZSC2_SECCFGR1_LPTIM1_Pos GTZC_CFGR1_LPTIM1_Pos |
| #define | GTZC_TZSC2_SECCFGR1_LPTIM1_Msk GTZC_CFGR1_LPTIM1_Msk |
| #define | GTZC_TZSC2_SECCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos |
| #define | GTZC_TZSC2_SECCFGR1_LPTIM3_Msk GTZC_CFGR1_LPTIM3_Msk |
| #define | GTZC_TZSC2_SECCFGR1_LPTIM4_Pos GTZC_CFGR1_LPTIM4_Pos |
| #define | GTZC_TZSC2_SECCFGR1_LPTIM4_Msk GTZC_CFGR1_LPTIM4_Msk |
| #define | GTZC_TZSC2_SECCFGR1_OPAMP_Pos GTZC_CFGR1_OPAMP_Pos |
| #define | GTZC_TZSC2_SECCFGR1_OPAMP_Msk GTZC_CFGR1_OPAMP_Msk |
| #define | GTZC_TZSC2_SECCFGR1_COMP_Pos GTZC_CFGR1_COMP_Pos |
| #define | GTZC_TZSC2_SECCFGR1_COMP_Msk GTZC_CFGR1_COMP_Msk |
| #define | GTZC_TZSC2_SECCFGR1_ADC4_Pos GTZC_CFGR1_ADC4_Pos |
| #define | GTZC_TZSC2_SECCFGR1_ADC4_Msk GTZC_CFGR1_ADC4_Msk |
| #define | GTZC_TZSC2_SECCFGR1_VREFBUF_Pos GTZC_CFGR1_VREFBUF_Pos |
| #define | GTZC_TZSC2_SECCFGR1_VREFBUF_Msk GTZC_CFGR1_VREFBUF_Msk |
| #define | GTZC_TZSC2_SECCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos |
| #define | GTZC_TZSC2_SECCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk |
| #define | GTZC_TZSC2_SECCFGR1_ADF1_Pos GTZC_CFGR1_ADF1_Pos |
| #define | GTZC_TZSC2_SECCFGR1_ADF1_Msk GTZC_CFGR1_ADF1_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_I2C4_Pos GTZC_CFGR1_I2C4_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_I2C4_Msk GTZC_CFGR1_I2C4_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_FDCAN1_Pos GTZC_CFGR1_FDCAN1_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_FDCAN1_Msk GTZC_CFGR1_FDCAN1_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_UCPD1_Pos GTZC_CFGR1_UCPD1_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_UCPD1_Msk GTZC_CFGR1_UCPD1_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_I2C5_Pos GTZC_CFGR1_I2C5_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_I2C5_Msk GTZC_CFGR1_I2C5_Msk |
| #define | GTZC_TZSC1_PRIVCFGR1_I2C6_Pos GTZC_CFGR1_I2C6_Pos |
| #define | GTZC_TZSC1_PRIVCFGR1_I2C6_Msk GTZC_CFGR1_I2C6_Msk |
| #define | GTZC_TZSC1_PRIVCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos |
| #define | GTZC_TZSC1_PRIVCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk |
| #define | GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos |
| #define | GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk |
| #define | GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos |
| #define | GTZC_TZSC1_PRIVCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk |
| #define | GTZC_TZSC1_PRIVCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos |
| #define | GTZC_TZSC1_PRIVCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk |
| #define | GTZC_TZSC1_PRIVCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos |
| #define | GTZC_TZSC1_PRIVCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk |
| #define | GTZC_TZSC1_PRIVCFGR2_TIM16_Pos GTZC_CFGR2_TIM16_Pos |
| #define | GTZC_TZSC1_PRIVCFGR2_TIM16_Msk GTZC_CFGR2_TIM16_Msk |
| #define | GTZC_TZSC1_PRIVCFGR2_TIM17_Pos GTZC_CFGR2_TIM17_Pos |
| #define | GTZC_TZSC1_PRIVCFGR2_TIM17_Msk GTZC_CFGR2_TIM17_Msk |
| #define | GTZC_TZSC1_PRIVCFGR2_SAI1_Pos GTZC_CFGR2_SAI1_Pos |
| #define | GTZC_TZSC1_PRIVCFGR2_SAI1_Msk GTZC_CFGR2_SAI1_Msk |
| #define | GTZC_TZSC1_PRIVCFGR2_SAI2_Pos GTZC_CFGR2_SAI2_Pos |
| #define | GTZC_TZSC1_PRIVCFGR2_SAI2_Msk GTZC_CFGR2_SAI2_Msk |
| #define | GTZC_TZSC1_PRIVCFGR2_LTDCUSB_Pos GTZC_CFGR2_LTDCUSB_Pos |
| #define | GTZC_TZSC1_PRIVCFGR2_LTDCUSB_Msk GTZC_CFGR2_LTDCUSB_Msk |
| #define | GTZC_TZSC1_PRIVCFGR2_DSI_Pos GTZC_CFGR2_DSI_Pos |
| #define | GTZC_TZSC1_PRIVCFGR2_DSI_Msk GTZC_CFGR2_DSI_Msk |
| #define | GTZC_TZSC1_PRIVCFGR2_GFXTIM_Pos GTZC_CFGR2_GFXTIM_Pos |
| #define | GTZC_TZSC1_PRIVCFGR2_GFXTIM_Msk GTZC_CFGR2_GFXTIM_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_MDF1_Pos GTZC_CFGR3_MDF1_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_MDF1_Msk GTZC_CFGR3_MDF1_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_CORDIC_Pos GTZC_CFGR3_CORDIC_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_CORDIC_Msk GTZC_CFGR3_CORDIC_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_FMAC_Pos GTZC_CFGR3_FMAC_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_FMAC_Msk GTZC_CFGR3_FMAC_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_TSC_Pos GTZC_CFGR3_TSC_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_TSC_Msk GTZC_CFGR3_TSC_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_DMA2D_Pos GTZC_CFGR3_DMA2D_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_DMA2D_Msk GTZC_CFGR3_DMA2D_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_ADC12_Pos GTZC_CFGR3_ADC12_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_ADC12_Msk GTZC_CFGR3_ADC12_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_DCMI_Pos GTZC_CFGR3_DCMI_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_DCMI_Msk GTZC_CFGR3_DCMI_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_OTG_Pos GTZC_CFGR3_OTG_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_OTG_Msk GTZC_CFGR3_OTG_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_AES_Pos GTZC_CFGR3_AES_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_AES_Msk GTZC_CFGR3_AES_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_SAES_Pos GTZC_CFGR3_SAES_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_SAES_Msk GTZC_CFGR3_SAES_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_OCTOSPIM_Pos GTZC_CFGR3_OCTOSPIM_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_OCTOSPIM_Msk GTZC_CFGR3_OCTOSPIM_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_SDMMC2_Pos GTZC_CFGR3_SDMMC2_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_SDMMC2_Msk GTZC_CFGR3_SDMMC2_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_FSMC_REG_Pos GTZC_CFGR3_FSMC_REG_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_FSMC_REG_Msk GTZC_CFGR3_FSMC_REG_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_REG_Pos GTZC_CFGR3_OCTOSPI1_REG_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_REG_Msk GTZC_CFGR3_OCTOSPI1_REG_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_OCTOSPI2_REG_Pos GTZC_CFGR3_OCTOSPI2_REG_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_OCTOSPI2_REG_Msk GTZC_CFGR3_OCTOSPI2_REG_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_GPU2D_Msk GTZC_CFGR3_GPU2D_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_GFXMMU_Pos GTZC_CFGR3_GFXMMU_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_GFXMMU_Msk GTZC_CFGR3_GFXMMU_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_HSPI1_REG_Pos GTZC_CFGR3_HSPI1_REG_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_HSPI1_REG_Msk GTZC_CFGR3_HSPI1_REG_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_DCACHE2_REG_Pos GTZC_CFGR3_DCACHE2_REG_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_DCACHE2_REG_Msk GTZC_CFGR3_DCACHE2_REG_Msk |
| #define | GTZC_TZSC1_PRIVCFGR3_JPEG_Pos GTZC_CFGR3_JPEG_REG_Pos |
| #define | GTZC_TZSC1_PRIVCFGR3_JPEG_Msk GTZC_CFGR3_JPEG_REG_Msk |
| #define | GTZC_TZSC2_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos |
| #define | GTZC_TZSC2_PRIVCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk |
| #define | GTZC_TZSC2_PRIVCFGR1_LPUART1_Pos GTZC_CFGR1_LPUART1_Pos |
| #define | GTZC_TZSC2_PRIVCFGR1_LPUART1_Msk GTZC_CFGR1_LPUART1_Msk |
| #define | GTZC_TZSC2_PRIVCFGR1_I2C3_Pos GTZC_CFGR1_I2C3_Pos |
| #define | GTZC_TZSC2_PRIVCFGR1_I2C3_Msk GTZC_CFGR1_I2C3_Msk |
| #define | GTZC_TZSC2_PRIVCFGR1_LPTIM1_Pos GTZC_CFGR1_LPTIM1_Pos |
| #define | GTZC_TZSC2_PRIVCFGR1_LPTIM1_Msk GTZC_CFGR1_LPTIM1_Msk |
| #define | GTZC_TZSC2_PRIVCFGR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos |
| #define | GTZC_TZSC2_PRIVCFGR1_LPTIM3_Msk GTZC_CFGR1_LPTIM3_Msk |
| #define | GTZC_TZSC2_PRIVCFGR1_LPTIM4_Pos GTZC_CFGR1_LPTIM4_Pos |
| #define | GTZC_TZSC2_PRIVCFGR1_LPTIM4_Msk GTZC_CFGR1_LPTIM4_Msk |
| #define | GTZC_TZSC2_PRIVCFGR1_OPAMP_Pos GTZC_CFGR1_OPAMP_Pos |
| #define | GTZC_TZSC2_PRIVCFGR1_OPAMP_Msk GTZC_CFGR1_OPAMP_Msk |
| #define | GTZC_TZSC2_PRIVCFGR1_COMP_Pos GTZC_CFGR1_COMP_Pos |
| #define | GTZC_TZSC2_PRIVCFGR1_COMP_Msk GTZC_CFGR1_COMP_Msk |
| #define | GTZC_TZSC2_PRIVCFGR1_ADC4_Pos GTZC_CFGR1_ADC4_Pos |
| #define | GTZC_TZSC2_PRIVCFGR1_ADC4_Msk GTZC_CFGR1_ADC4_Msk |
| #define | GTZC_TZSC2_PRIVCFGR1_VREFBUF_Pos GTZC_CFGR1_VREFBUF_Pos |
| #define | GTZC_TZSC2_PRIVCFGR1_VREFBUF_Msk GTZC_CFGR1_VREFBUF_Msk |
| #define | GTZC_TZSC2_PRIVCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos |
| #define | GTZC_TZSC2_PRIVCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk |
| #define | GTZC_TZSC2_PRIVCFGR1_ADF1_Pos GTZC_CFGR1_ADF1_Pos |
| #define | GTZC_TZSC2_PRIVCFGR1_ADF1_Msk GTZC_CFGR1_ADF1_Msk |
| #define | GTZC_TZIC1_IER1_TIM2_Pos GTZC_CFGR1_TIM2_Pos |
| #define | GTZC_TZIC1_IER1_TIM2_Msk GTZC_CFGR1_TIM2_Msk |
| #define | GTZC_TZIC1_IER1_TIM3_Pos GTZC_CFGR1_TIM3_Pos |
| #define | GTZC_TZIC1_IER1_TIM3_Msk GTZC_CFGR1_TIM3_Msk |
| #define | GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos |
| #define | GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk |
| #define | GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos |
| #define | GTZC_TZIC1_IER1_TIM5_Msk GTZC_CFGR1_TIM5_Msk |
| #define | GTZC_TZIC1_IER1_TIM6_Pos GTZC_CFGR1_TIM6_Pos |
| #define | GTZC_TZIC1_IER1_TIM6_Msk GTZC_CFGR1_TIM6_Msk |
| #define | GTZC_TZIC1_IER1_TIM7_Pos GTZC_CFGR1_TIM7_Pos |
| #define | GTZC_TZIC1_IER1_TIM7_Msk GTZC_CFGR1_TIM7_Msk |
| #define | GTZC_TZIC1_IER1_WWDG_Pos GTZC_CFGR1_WWDG_Pos |
| #define | GTZC_TZIC1_IER1_WWDG_Msk GTZC_CFGR1_WWDG_Msk |
| #define | GTZC_TZIC1_IER1_IWDG_Pos GTZC_CFGR1_IWDG_Pos |
| #define | GTZC_TZIC1_IER1_IWDG_Msk GTZC_CFGR1_IWDG_Msk |
| #define | GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos |
| #define | GTZC_TZIC1_IER1_SPI2_Msk GTZC_CFGR1_SPI2_Msk |
| #define | GTZC_TZIC1_IER1_USART2_Pos GTZC_CFGR1_USART2_Pos |
| #define | GTZC_TZIC1_IER1_USART2_Msk GTZC_CFGR1_USART2_Msk |
| #define | GTZC_TZIC1_IER1_USART3_Pos GTZC_CFGR1_USART3_Pos |
| #define | GTZC_TZIC1_IER1_USART3_Msk GTZC_CFGR1_USART3_Msk |
| #define | GTZC_TZIC1_IER1_UART4_Pos GTZC_CFGR1_UART4_Pos |
| #define | GTZC_TZIC1_IER1_UART4_Msk GTZC_CFGR1_UART4_Msk |
| #define | GTZC_TZIC1_IER1_UART5_Pos GTZC_CFGR1_UART5_Pos |
| #define | GTZC_TZIC1_IER1_UART5_Msk GTZC_CFGR1_UART5_Msk |
| #define | GTZC_TZIC1_IER1_I2C1_Pos GTZC_CFGR1_I2C1_Pos |
| #define | GTZC_TZIC1_IER1_I2C1_Msk GTZC_CFGR1_I2C1_Msk |
| #define | GTZC_TZIC1_IER1_I2C2_Pos GTZC_CFGR1_I2C2_Pos |
| #define | GTZC_TZIC1_IER1_I2C2_Msk GTZC_CFGR1_I2C2_Msk |
| #define | GTZC_TZIC1_IER1_CRS_Pos GTZC_CFGR1_CRS_Pos |
| #define | GTZC_TZIC1_IER1_CRS_Msk GTZC_CFGR1_CRS_Msk |
| #define | GTZC_TZIC1_IER1_I2C4_Pos GTZC_CFGR1_I2C4_Pos |
| #define | GTZC_TZIC1_IER1_I2C4_Msk GTZC_CFGR1_I2C4_Msk |
| #define | GTZC_TZIC1_IER1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos |
| #define | GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk |
| #define | GTZC_TZIC1_IER1_FDCAN1_Pos GTZC_CFGR1_FDCAN1_Pos |
| #define | GTZC_TZIC1_IER1_FDCAN1_Msk GTZC_CFGR1_FDCAN1_Msk |
| #define | GTZC_TZIC1_IER1_UCPD1_Pos GTZC_CFGR1_UCPD1_Pos |
| #define | GTZC_TZIC1_IER1_UCPD1_Msk GTZC_CFGR1_UCPD1_Msk |
| #define | GTZC_TZIC1_IER1_USART6_Pos GTZC_CFGR1_USART6_Pos |
| #define | GTZC_TZIC1_IER1_USART6_Msk GTZC_CFGR1_USART6_Msk |
| #define | GTZC_TZIC1_IER1_I2C5_Pos GTZC_CFGR1_I2C5_Pos |
| #define | GTZC_TZIC1_IER1_I2C5_Msk GTZC_CFGR1_I2C5_Msk |
| #define | GTZC_TZIC1_IER1_I2C6_Pos GTZC_CFGR1_I2C6_Pos |
| #define | GTZC_TZIC1_IER1_I2C6_Msk GTZC_CFGR1_I2C6_Msk |
| #define | GTZC_TZIC1_IER2_TIM1_Pos GTZC_CFGR2_TIM1_Pos |
| #define | GTZC_TZIC1_IER2_TIM1_Msk GTZC_CFGR2_TIM1_Msk |
| #define | GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos |
| #define | GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk |
| #define | GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos |
| #define | GTZC_TZIC1_IER2_TIM8_Msk GTZC_CFGR2_TIM8_Msk |
| #define | GTZC_TZIC1_IER2_USART1_Pos GTZC_CFGR2_USART1_Pos |
| #define | GTZC_TZIC1_IER2_USART1_Msk GTZC_CFGR2_USART1_Msk |
| #define | GTZC_TZIC1_IER2_TIM15_Pos GTZC_CFGR2_TIM15_Pos |
| #define | GTZC_TZIC1_IER2_TIM15_Msk GTZC_CFGR2_TIM15_Msk |
| #define | GTZC_TZIC1_IER2_TIM16_Pos GTZC_CFGR2_TIM16_Pos |
| #define | GTZC_TZIC1_IER2_TIM16_Msk GTZC_CFGR2_TIM16_Msk |
| #define | GTZC_TZIC1_IER2_TIM17_Pos GTZC_CFGR2_TIM17_Pos |
| #define | GTZC_TZIC1_IER2_TIM17_Msk GTZC_CFGR2_TIM17_Msk |
| #define | GTZC_TZIC1_IER2_SAI1_Pos GTZC_CFGR2_SAI1_Pos |
| #define | GTZC_TZIC1_IER2_SAI1_Msk GTZC_CFGR2_SAI1_Msk |
| #define | GTZC_TZIC1_IER2_SAI2_Pos GTZC_CFGR2_SAI2_Pos |
| #define | GTZC_TZIC1_IER2_SAI2_Msk GTZC_CFGR2_SAI2_Msk |
| #define | GTZC_TZIC1_IER2_LTDCUSB_Pos GTZC_CFGR2_LTDCUSB_Pos |
| #define | GTZC_TZIC1_IER2_LTDCUSB_Msk GTZC_CFGR2_LTDCUSB_Msk |
| #define | GTZC_TZIC1_IER2_DSI_Pos GTZC_CFGR2_DSI_Pos |
| #define | GTZC_TZIC1_IER2_DSI_Msk GTZC_CFGR2_DSI_Msk |
| #define | GTZC_TZIC1_IER2_GFXTIM_Pos GTZC_CFGR2_GFXTIM_Pos |
| #define | GTZC_TZIC1_IER2_GFXTIM_Msk GTZC_CFGR2_GFXTIM_Msk |
| #define | GTZC_TZIC1_IER3_MDF1_Pos GTZC_CFGR3_MDF1_Pos |
| #define | GTZC_TZIC1_IER3_MDF1_Msk GTZC_CFGR3_MDF1_Msk |
| #define | GTZC_TZIC1_IER3_CORDIC_Pos GTZC_CFGR3_CORDIC_Pos |
| #define | GTZC_TZIC1_IER3_CORDIC_Msk GTZC_CFGR3_CORDIC_Msk |
| #define | GTZC_TZIC1_IER3_FMAC_Pos GTZC_CFGR3_FMAC_Pos |
| #define | GTZC_TZIC1_IER3_FMAC_Msk GTZC_CFGR3_FMAC_Msk |
| #define | GTZC_TZIC1_IER3_CRC_Pos GTZC_CFGR3_CRC_Pos |
| #define | GTZC_TZIC1_IER3_CRC_Msk GTZC_CFGR3_CRC_Msk |
| #define | GTZC_TZIC1_IER3_TSC_Pos GTZC_CFGR3_TSC_Pos |
| #define | GTZC_TZIC1_IER3_TSC_Msk GTZC_CFGR3_TSC_Msk |
| #define | GTZC_TZIC1_IER3_DMA2D_Pos GTZC_CFGR3_DMA2D_Pos |
| #define | GTZC_TZIC1_IER3_DMA2D_Msk GTZC_CFGR3_DMA2D_Msk |
| #define | GTZC_TZIC1_IER3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos |
| #define | GTZC_TZIC1_IER3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk |
| #define | GTZC_TZIC1_IER3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos |
| #define | GTZC_TZIC1_IER3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk |
| #define | GTZC_TZIC1_IER3_ADC12_Pos GTZC_CFGR3_ADC12_Pos |
| #define | GTZC_TZIC1_IER3_ADC12_Msk GTZC_CFGR3_ADC12_Msk |
| #define | GTZC_TZIC1_IER3_DCMI_Pos GTZC_CFGR3_DCMI_Pos |
| #define | GTZC_TZIC1_IER3_DCMI_Msk GTZC_CFGR3_DCMI_Msk |
| #define | GTZC_TZIC1_IER3_OTG_Pos GTZC_CFGR3_OTG_Pos |
| #define | GTZC_TZIC1_IER3_OTG_Msk GTZC_CFGR3_OTG_Msk |
| #define | GTZC_TZIC1_IER3_AES_Pos GTZC_CFGR3_AES_Pos |
| #define | GTZC_TZIC1_IER3_AES_Msk GTZC_CFGR3_AES_Msk |
| #define | GTZC_TZIC1_IER3_HASH_Pos GTZC_CFGR3_HASH_Pos |
| #define | GTZC_TZIC1_IER3_HASH_Msk GTZC_CFGR3_HASH_Msk |
| #define | GTZC_TZIC1_IER3_RNG_Pos GTZC_CFGR3_RNG_Pos |
| #define | GTZC_TZIC1_IER3_RNG_Msk GTZC_CFGR3_RNG_Msk |
| #define | GTZC_TZIC1_IER3_PKA_Pos GTZC_CFGR3_PKA_Pos |
| #define | GTZC_TZIC1_IER3_PKA_Msk GTZC_CFGR3_PKA_Msk |
| #define | GTZC_TZIC1_IER3_SAES_Pos GTZC_CFGR3_SAES_Pos |
| #define | GTZC_TZIC1_IER3_SAES_Msk GTZC_CFGR3_SAES_Msk |
| #define | GTZC_TZIC1_IER3_OCTOSPIM_Pos GTZC_CFGR3_OCTOSPIM_Pos |
| #define | GTZC_TZIC1_IER3_OCTOSPIM_Msk GTZC_CFGR3_OCTOSPIM_Msk |
| #define | GTZC_TZIC1_IER3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos |
| #define | GTZC_TZIC1_IER3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk |
| #define | GTZC_TZIC1_IER3_SDMMC2_Pos GTZC_CFGR3_SDMMC2_Pos |
| #define | GTZC_TZIC1_IER3_SDMMC2_Msk GTZC_CFGR3_SDMMC2_Msk |
| #define | GTZC_TZIC1_IER3_FSMC_REG_Pos GTZC_CFGR3_FSMC_REG_Pos |
| #define | GTZC_TZIC1_IER3_FSMC_REG_Msk GTZC_CFGR3_FSMC_REG_Msk |
| #define | GTZC_TZIC1_IER3_OCTOSPI1_REG_Pos GTZC_CFGR3_OCTOSPI1_REG_Pos |
| #define | GTZC_TZIC1_IER3_OCTOSPI1_REG_Msk GTZC_CFGR3_OCTOSPI1_REG_Msk |
| #define | GTZC_TZIC1_IER3_OCTOSPI2_REG_Pos GTZC_CFGR3_OCTOSPI2_REG_Pos |
| #define | GTZC_TZIC1_IER3_OCTOSPI2_REG_Msk GTZC_CFGR3_OCTOSPI2_REG_Msk |
| #define | GTZC_TZIC1_IER3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos |
| #define | GTZC_TZIC1_IER3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk |
| #define | GTZC_TZIC1_IER3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos |
| #define | GTZC_TZIC1_IER3_GPU2D_Msk GTZC_CFGR3_GPU2D_Msk |
| #define | GTZC_TZIC1_IER3_GFXMMU_Pos GTZC_CFGR3_GFXMMU_Pos |
| #define | GTZC_TZIC1_IER3_GFXMMU_Msk GTZC_CFGR3_GFXMMU_Msk |
| #define | GTZC_TZIC1_IER3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos |
| #define | GTZC_TZIC1_IER3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk |
| #define | GTZC_TZIC1_IER3_HSPI1_REG_Pos GTZC_CFGR3_HSPI1_REG_Pos |
| #define | GTZC_TZIC1_IER3_HSPI1_REG_Msk GTZC_CFGR3_HSPI1_REG_Msk |
| #define | GTZC_TZIC1_IER3_DCACHE2_REG_Pos GTZC_CFGR3_DCACHE2_REG_Pos |
| #define | GTZC_TZIC1_IER3_DCACHE2_REG_Msk GTZC_CFGR3_DCACHE2_REG_Msk |
| #define | GTZC_TZIC1_IER3_JPEG_Pos GTZC_CFGR3_JPEG_REG_Pos |
| #define | GTZC_TZIC1_IER3_JPEG_Msk GTZC_CFGR3_JPEG_REG_Msk |
| #define | GTZC_TZIC1_IER4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos |
| #define | GTZC_TZIC1_IER4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk |
| #define | GTZC_TZIC1_IER4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos |
| #define | GTZC_TZIC1_IER4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk |
| #define | GTZC_TZIC1_IER4_FLASH_Pos GTZC_CFGR4_FLASH_Pos |
| #define | GTZC_TZIC1_IER4_FLASH_Msk GTZC_CFGR4_FLASH_Msk |
| #define | GTZC_TZIC1_IER4_OTFDEC1_Pos GTZC_CFGR4_OTFDEC1_Pos |
| #define | GTZC_TZIC1_IER4_OTFDEC1_Msk GTZC_CFGR4_OTFDEC1_Msk |
| #define | GTZC_TZIC1_IER4_OTFDEC2_Pos GTZC_CFGR4_OTFDEC2_Pos |
| #define | GTZC_TZIC1_IER4_OTFDEC2_Msk GTZC_CFGR4_OTFDEC2_Msk |
| #define | GTZC_TZIC1_IER4_TZSC1_Pos GTZC_CFGR4_TZSC1_Pos |
| #define | GTZC_TZIC1_IER4_TZSC1_Msk GTZC_CFGR4_TZSC1_Msk |
| #define | GTZC_TZIC1_IER4_TZIC1_Pos GTZC_CFGR4_TZIC1_Pos |
| #define | GTZC_TZIC1_IER4_TZIC1_Msk GTZC_CFGR4_TZIC1_Msk |
| #define | GTZC_TZIC1_IER4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos |
| #define | GTZC_TZIC1_IER4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk |
| #define | GTZC_TZIC1_IER4_FSMC_MEM_Pos GTZC_CFGR4_FSMC_MEM_Pos |
| #define | GTZC_TZIC1_IER4_FSMC_MEM_Msk GTZC_CFGR4_FSMC_MEM_Msk |
| #define | GTZC_TZIC1_IER4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos |
| #define | GTZC_TZIC1_IER4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk |
| #define | GTZC_TZIC1_IER4_OCTOSPI2_MEM_Pos GTZC_CFGR4_OCTOSPI2_MEM_Pos |
| #define | GTZC_TZIC1_IER4_OCTOSPI2_MEM_Msk GTZC_CFGR4_OCTOSPI2_MEM_Msk |
| #define | GTZC_TZIC1_IER4_HSPI1_MEM_Pos GTZC_CFGR4_HSPI1_MEM_Pos |
| #define | GTZC_TZIC1_IER4_HSPI1_MEM_Msk GTZC_CFGR4_HSPI1_MEM_Msk |
| #define | GTZC_TZIC1_IER4_SRAM6_Pos GTZC_CFGR4_SRAM6_Pos |
| #define | GTZC_TZIC1_IER4_SRAM6_Msk GTZC_CFGR4_SRAM6_Msk |
| #define | GTZC_TZIC1_IER4_MPCBB6_REG_Pos GTZC_CFGR4_MPCBB6_REG_Pos |
| #define | GTZC_TZIC1_IER4_MPCBB6_REG_Msk GTZC_CFGR4_MPCBB6_REG_Msk |
| #define | GTZC_TZIC1_IER4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos |
| #define | GTZC_TZIC1_IER4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk |
| #define | GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos |
| #define | GTZC_TZIC1_IER4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk |
| #define | GTZC_TZIC1_IER4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos |
| #define | GTZC_TZIC1_IER4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk |
| #define | GTZC_TZIC1_IER4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos |
| #define | GTZC_TZIC1_IER4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk |
| #define | GTZC_TZIC1_IER4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos |
| #define | GTZC_TZIC1_IER4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk |
| #define | GTZC_TZIC1_IER4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos |
| #define | GTZC_TZIC1_IER4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk |
| #define | GTZC_TZIC1_IER4_SRAM5_Pos GTZC_CFGR4_SRAM5_Pos |
| #define | GTZC_TZIC1_IER4_SRAM5_Msk GTZC_CFGR4_SRAM5_Msk |
| #define | GTZC_TZIC1_IER4_MPCBB5_REG_Pos GTZC_CFGR4_MPCBB5_REG_Pos |
| #define | GTZC_TZIC1_IER4_MPCBB5_REG_Msk GTZC_CFGR4_MPCBB5_REG_Msk |
| #define | GTZC_TZIC2_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos |
| #define | GTZC_TZIC2_IER1_SPI3_Msk GTZC_CFGR1_SPI3_Msk |
| #define | GTZC_TZIC2_IER1_LPUART1_Pos GTZC_CFGR1_LPUART1_Pos |
| #define | GTZC_TZIC2_IER1_LPUART1_Msk GTZC_CFGR1_LPUART1_Msk |
| #define | GTZC_TZIC2_IER1_I2C3_Pos GTZC_CFGR1_I2C3_Pos |
| #define | GTZC_TZIC2_IER1_I2C3_Msk GTZC_CFGR1_I2C3_Msk |
| #define | GTZC_TZIC2_IER1_LPTIM1_Pos GTZC_CFGR1_LPTIM1_Pos |
| #define | GTZC_TZIC2_IER1_LPTIM1_Msk GTZC_CFGR1_LPTIM1_Msk |
| #define | GTZC_TZIC2_IER1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos |
| #define | GTZC_TZIC2_IER1_LPTIM3_Msk GTZC_CFGR1_LPTIM3_Msk |
| #define | GTZC_TZIC2_IER1_LPTIM4_Pos GTZC_CFGR1_LPTIM4_Pos |
| #define | GTZC_TZIC2_IER1_LPTIM4_Msk GTZC_CFGR1_LPTIM4_Msk |
| #define | GTZC_TZIC2_IER1_OPAMP_Pos GTZC_CFGR1_OPAMP_Pos |
| #define | GTZC_TZIC2_IER1_OPAMP_Msk GTZC_CFGR1_OPAMP_Msk |
| #define | GTZC_TZIC2_IER1_COMP_Pos GTZC_CFGR1_COMP_Pos |
| #define | GTZC_TZIC2_IER1_COMP_Msk GTZC_CFGR1_COMP_Msk |
| #define | GTZC_TZIC2_IER1_ADC4_Pos GTZC_CFGR1_ADC4_Pos |
| #define | GTZC_TZIC2_IER1_ADC4_Msk GTZC_CFGR1_ADC4_Msk |
| #define | GTZC_TZIC2_IER1_VREFBUF_Pos GTZC_CFGR1_VREFBUF_Pos |
| #define | GTZC_TZIC2_IER1_VREFBUF_Msk GTZC_CFGR1_VREFBUF_Msk |
| #define | GTZC_TZIC2_IER1_DAC1_Pos GTZC_CFGR1_DAC1_Pos |
| #define | GTZC_TZIC2_IER1_DAC1_Msk GTZC_CFGR1_DAC1_Msk |
| #define | GTZC_TZIC2_IER1_ADF1_Pos GTZC_CFGR1_ADF1_Pos |
| #define | GTZC_TZIC2_IER1_ADF1_Msk GTZC_CFGR1_ADF1_Msk |
| #define | GTZC_TZIC2_IER2_SYSCFG_Pos GTZC_CFGR2_SYSCFG_Pos |
| #define | GTZC_TZIC2_IER2_SYSCFG_Msk GTZC_CFGR2_SYSCFG_Msk |
| #define | GTZC_TZIC2_IER2_RTC_Pos GTZC_CFGR2_RTC_Pos |
| #define | GTZC_TZIC2_IER2_RTC_Msk GTZC_CFGR2_RTC_Msk |
| #define | GTZC_TZIC2_IER2_TAMP_Pos GTZC_CFGR2_TAMP_Pos |
| #define | GTZC_TZIC2_IER2_TAMP_Msk GTZC_CFGR2_TAMP_Msk |
| #define | GTZC_TZIC2_IER2_PWR_Pos GTZC_CFGR2_PWR_Pos |
| #define | GTZC_TZIC2_IER2_PWR_Msk GTZC_CFGR2_PWR_Msk |
| #define | GTZC_TZIC2_IER2_RCC_Pos GTZC_CFGR2_RCC_Pos |
| #define | GTZC_TZIC2_IER2_RCC_Msk GTZC_CFGR2_RCC_Msk |
| #define | GTZC_TZIC2_IER2_LPDMA1_Pos GTZC_CFGR2_LPDMA1_Pos |
| #define | GTZC_TZIC2_IER2_LPDMA1_Msk GTZC_CFGR2_LPDMA1_Msk |
| #define | GTZC_TZIC2_IER2_EXTI_Pos GTZC_CFGR2_EXTI_Pos |
| #define | GTZC_TZIC2_IER2_EXTI_Msk GTZC_CFGR2_EXTI_Msk |
| #define | GTZC_TZIC2_IER2_TZSC2_Pos GTZC_CFGR2_TZSC2_Pos |
| #define | GTZC_TZIC2_IER2_TZSC2_Msk GTZC_CFGR2_TZSC2_Msk |
| #define | GTZC_TZIC2_IER2_TZIC2_Pos GTZC_CFGR2_TZIC2_Pos |
| #define | GTZC_TZIC2_IER2_TZIC2_Msk GTZC_CFGR2_TZIC2_Msk |
| #define | GTZC_TZIC2_IER2_SRAM4_Pos GTZC_CFGR2_SRAM4_Pos |
| #define | GTZC_TZIC2_IER2_SRAM4_Msk GTZC_CFGR2_SRAM4_Msk |
| #define | GTZC_TZIC2_IER2_MPCBB4_REG_Pos GTZC_CFGR2_MPCBB4_REG_Pos |
| #define | GTZC_TZIC2_IER2_MPCBB4_REG_Msk GTZC_CFGR2_MPCBB4_REG_Msk |
| #define | GTZC_TZIC1_SR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos |
| #define | GTZC_TZIC1_SR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk |
| #define | GTZC_TZIC1_SR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos |
| #define | GTZC_TZIC1_SR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk |
| #define | GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos |
| #define | GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk |
| #define | GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos |
| #define | GTZC_TZIC1_SR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk |
| #define | GTZC_TZIC1_SR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos |
| #define | GTZC_TZIC1_SR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk |
| #define | GTZC_TZIC1_SR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos |
| #define | GTZC_TZIC1_SR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk |
| #define | GTZC_TZIC1_SR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos |
| #define | GTZC_TZIC1_SR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk |
| #define | GTZC_TZIC1_SR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos |
| #define | GTZC_TZIC1_SR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk |
| #define | GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos |
| #define | GTZC_TZIC1_SR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk |
| #define | GTZC_TZIC1_SR1_USART2_Pos GTZC_CFGR1_USART2_Pos |
| #define | GTZC_TZIC1_SR1_USART2_Msk GTZC_CFGR1_USART2_Msk |
| #define | GTZC_TZIC1_SR1_USART3_Pos GTZC_CFGR1_USART3_Pos |
| #define | GTZC_TZIC1_SR1_USART3_Msk GTZC_CFGR1_USART3_Msk |
| #define | GTZC_TZIC1_SR1_UART4_Pos GTZC_CFGR1_UART4_Pos |
| #define | GTZC_TZIC1_SR1_UART4_Msk GTZC_CFGR1_UART4_Msk |
| #define | GTZC_TZIC1_SR1_UART5_Pos GTZC_CFGR1_UART5_Pos |
| #define | GTZC_TZIC1_SR1_UART5_Msk GTZC_CFGR1_UART5_Msk |
| #define | GTZC_TZIC1_SR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos |
| #define | GTZC_TZIC1_SR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk |
| #define | GTZC_TZIC1_SR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos |
| #define | GTZC_TZIC1_SR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk |
| #define | GTZC_TZIC1_SR1_CRS_Pos GTZC_CFGR1_CRS_Pos |
| #define | GTZC_TZIC1_SR1_CRS_Msk GTZC_CFGR1_CRS_Msk |
| #define | GTZC_TZIC1_SR1_I2C4_Pos GTZC_CFGR1_I2C4_Pos |
| #define | GTZC_TZIC1_SR1_I2C4_Msk GTZC_CFGR1_I2C4_Msk |
| #define | GTZC_TZIC1_SR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos |
| #define | GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk |
| #define | GTZC_TZIC1_SR1_FDCAN1_Pos GTZC_CFGR1_FDCAN1_Pos |
| #define | GTZC_TZIC1_SR1_FDCAN1_Msk GTZC_CFGR1_FDCAN1_Msk |
| #define | GTZC_TZIC1_SR1_UCPD1_Pos GTZC_CFGR1_UCPD1_Pos |
| #define | GTZC_TZIC1_SR1_UCPD1_Msk GTZC_CFGR1_UCPD1_Msk |
| #define | GTZC_TZIC1_SR1_USART6_Pos GTZC_CFGR1_USART6_Pos |
| #define | GTZC_TZIC1_SR1_USART6_Msk GTZC_CFGR1_USART6_Msk |
| #define | GTZC_TZIC1_SR1_I2C5_Pos GTZC_CFGR1_I2C5_Pos |
| #define | GTZC_TZIC1_SR1_I2C5_Msk GTZC_CFGR1_I2C5_Msk |
| #define | GTZC_TZIC1_SR1_I2C6_Pos GTZC_CFGR1_I2C6_Pos |
| #define | GTZC_TZIC1_SR1_I2C6_Msk GTZC_CFGR1_I2C6_Msk |
| #define | GTZC_TZIC1_SR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos |
| #define | GTZC_TZIC1_SR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk |
| #define | GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos |
| #define | GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk |
| #define | GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos |
| #define | GTZC_TZIC1_SR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk |
| #define | GTZC_TZIC1_SR2_USART1_Pos GTZC_CFGR2_USART1_Pos |
| #define | GTZC_TZIC1_SR2_USART1_Msk GTZC_CFGR2_USART1_Msk |
| #define | GTZC_TZIC1_SR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos |
| #define | GTZC_TZIC1_SR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk |
| #define | GTZC_TZIC1_SR2_TIM16_Pos GTZC_CFGR2_TIM16_Pos |
| #define | GTZC_TZIC1_SR2_TIM16_Msk GTZC_CFGR2_TIM16_Msk |
| #define | GTZC_TZIC1_SR2_TIM17_Pos GTZC_CFGR2_TIM17_Pos |
| #define | GTZC_TZIC1_SR2_TIM17_Msk GTZC_CFGR2_TIM17_Msk |
| #define | GTZC_TZIC1_SR2_SAI1_Pos GTZC_CFGR2_SAI1_Pos |
| #define | GTZC_TZIC1_SR2_SAI1_Msk GTZC_CFGR2_SAI1_Msk |
| #define | GTZC_TZIC1_SR2_SAI2_Pos GTZC_CFGR2_SAI2_Pos |
| #define | GTZC_TZIC1_SR2_SAI2_Msk GTZC_CFGR2_SAI2_Msk |
| #define | GTZC_TZIC1_SR2_LTDCUSB_Pos GTZC_CFGR2_LTDCUSB_Pos |
| #define | GTZC_TZIC1_SR2_LTDCUSB_Msk GTZC_CFGR2_LTDCUSB_Msk |
| #define | GTZC_TZIC1_SR2_DSI_Pos GTZC_CFGR2_DSI_Pos |
| #define | GTZC_TZIC1_SR2_DSI_Msk GTZC_CFGR2_DSI_Msk |
| #define | GTZC_TZIC1_SR2_GFXTIM_Pos GTZC_CFGR2_GFXTIM_Pos |
| #define | GTZC_TZIC1_SR2_GFXTIM_Msk GTZC_CFGR2_GFXTIM_Msk |
| #define | GTZC_TZIC1_SR3_MDF1_Pos GTZC_CFGR3_MDF1_Pos |
| #define | GTZC_TZIC1_SR3_MDF1_Msk GTZC_CFGR3_MDF1_Msk |
| #define | GTZC_TZIC1_SR3_CORDIC_Pos GTZC_CFGR3_CORDIC_Pos |
| #define | GTZC_TZIC1_SR3_CORDIC_Msk GTZC_CFGR3_CORDIC_Msk |
| #define | GTZC_TZIC1_SR3_FMAC_Pos GTZC_CFGR3_FMAC_Pos |
| #define | GTZC_TZIC1_SR3_FMAC_Msk GTZC_CFGR3_FMAC_Msk |
| #define | GTZC_TZIC1_SR3_CRC_Pos GTZC_CFGR3_CRC_Pos |
| #define | GTZC_TZIC1_SR3_CRC_Msk GTZC_CFGR3_CRC_Msk |
| #define | GTZC_TZIC1_SR3_TSC_Pos GTZC_CFGR3_TSC_Pos |
| #define | GTZC_TZIC1_SR3_TSC_Msk GTZC_CFGR3_TSC_Msk |
| #define | GTZC_TZIC1_SR3_DMA2D_Pos GTZC_CFGR3_DMA2D_Pos |
| #define | GTZC_TZIC1_SR3_DMA2D_Msk GTZC_CFGR3_DMA2D_Msk |
| #define | GTZC_TZIC1_SR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos |
| #define | GTZC_TZIC1_SR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk |
| #define | GTZC_TZIC1_SR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos |
| #define | GTZC_TZIC1_SR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk |
| #define | GTZC_TZIC1_SR3_ADC12_Pos GTZC_CFGR3_ADC12_Pos |
| #define | GTZC_TZIC1_SR3_ADC12_Msk GTZC_CFGR3_ADC12_Msk |
| #define | GTZC_TZIC1_SR3_DCMI_Pos GTZC_CFGR3_DCMI_Pos |
| #define | GTZC_TZIC1_SR3_DCMI_Msk GTZC_CFGR3_DCMI_Msk |
| #define | GTZC_TZIC1_SR3_OTG_Pos GTZC_CFGR3_OTG_Pos |
| #define | GTZC_TZIC1_SR3_OTG_Msk GTZC_CFGR3_OTG_Msk |
| #define | GTZC_TZIC1_SR3_AES_Pos GTZC_CFGR3_AES_Pos |
| #define | GTZC_TZIC1_SR3_AES_Msk GTZC_CFGR3_AES_Msk |
| #define | GTZC_TZIC1_SR3_HASH_Pos GTZC_CFGR3_HASH_Pos |
| #define | GTZC_TZIC1_SR3_HASH_Msk GTZC_CFGR3_HASH_Msk |
| #define | GTZC_TZIC1_SR3_RNG_Pos GTZC_CFGR3_RNG_Pos |
| #define | GTZC_TZIC1_SR3_RNG_Msk GTZC_CFGR3_RNG_Msk |
| #define | GTZC_TZIC1_SR3_PKA_Pos GTZC_CFGR3_PKA_Pos |
| #define | GTZC_TZIC1_SR3_PKA_Msk GTZC_CFGR3_PKA_Msk |
| #define | GTZC_TZIC1_SR3_SAES_Pos GTZC_CFGR3_SAES_Pos |
| #define | GTZC_TZIC1_SR3_SAES_Msk GTZC_CFGR3_SAES_Msk |
| #define | GTZC_TZIC1_SR3_OCTOSPIM_Pos GTZC_CFGR3_OCTOSPIM_Pos |
| #define | GTZC_TZIC1_SR3_OCTOSPIM_Msk GTZC_CFGR3_OCTOSPIM_Msk |
| #define | GTZC_TZIC1_SR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos |
| #define | GTZC_TZIC1_SR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk |
| #define | GTZC_TZIC1_SR3_SDMMC2_Pos GTZC_CFGR3_SDMMC2_Pos |
| #define | GTZC_TZIC1_SR3_SDMMC2_Msk GTZC_CFGR3_SDMMC2_Msk |
| #define | GTZC_TZIC1_SR3_FSMC_REG_Pos GTZC_CFGR3_FSMC_REG_Pos |
| #define | GTZC_TZIC1_SR3_FSMC_REG_Msk GTZC_CFGR3_FSMC_REG_Msk |
| #define | GTZC_TZIC1_SR3_OCTOSPI1_REG_Pos GTZC_CFGR3_OCTOSPI1_REG_Pos |
| #define | GTZC_TZIC1_SR3_OCTOSPI1_REG_Msk GTZC_CFGR3_OCTOSPI1_REG_Msk |
| #define | GTZC_TZIC1_SR3_OCTOSPI2_REG_Pos GTZC_CFGR3_OCTOSPI2_REG_Pos |
| #define | GTZC_TZIC1_SR3_OCTOSPI2_REG_Msk GTZC_CFGR3_OCTOSPI2_REG_Msk |
| #define | GTZC_TZIC1_SR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos |
| #define | GTZC_TZIC1_SR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk |
| #define | GTZC_TZIC1_SR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos |
| #define | GTZC_TZIC1_SR3_GPU2D_Msk GTZC_CFGR3_GPU2D_Msk |
| #define | GTZC_TZIC1_SR3_GFXMMU_Pos GTZC_CFGR3_GFXMMU_Pos |
| #define | GTZC_TZIC1_SR3_GFXMMU_Msk GTZC_CFGR3_GFXMMU_Msk |
| #define | GTZC_TZIC1_SR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos |
| #define | GTZC_TZIC1_SR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk |
| #define | GTZC_TZIC1_SR3_HSPI1_REG_Pos GTZC_CFGR3_HSPI1_REG_Pos |
| #define | GTZC_TZIC1_SR3_HSPI1_REG_Msk GTZC_CFGR3_HSPI1_REG_Msk |
| #define | GTZC_TZIC1_SR3_DCACHE2_REG_Pos GTZC_CFGR3_DCACHE2_REG_Pos |
| #define | GTZC_TZIC1_SR3_DCACHE2_REG_Msk GTZC_CFGR3_DCACHE2_REG_Msk |
| #define | GTZC_TZIC1_SR3_JPEG_Pos GTZC_CFGR3_JPEG_REG_Pos |
| #define | GTZC_TZIC1_SR3_JPEG_Msk GTZC_CFGR3_JPEG_REG_Msk |
| #define | GTZC_TZIC1_SR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos |
| #define | GTZC_TZIC1_SR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk |
| #define | GTZC_TZIC1_SR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos |
| #define | GTZC_TZIC1_SR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk |
| #define | GTZC_TZIC1_SR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos |
| #define | GTZC_TZIC1_SR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk |
| #define | GTZC_TZIC1_SR4_OTFDEC1_Pos GTZC_CFGR4_OTFDEC1_Pos |
| #define | GTZC_TZIC1_SR4_OTFDEC1_Msk GTZC_CFGR4_OTFDEC1_Msk |
| #define | GTZC_TZIC1_SR4_OTFDEC2_Pos GTZC_CFGR4_OTFDEC2_Pos |
| #define | GTZC_TZIC1_SR4_OTFDEC2_Msk GTZC_CFGR4_OTFDEC2_Msk |
| #define | GTZC_TZIC1_SR4_TZSC1_Pos GTZC_CFGR4_TZSC1_Pos |
| #define | GTZC_TZIC1_SR4_TZSC1_Msk GTZC_CFGR4_TZSC1_Msk |
| #define | GTZC_TZIC1_SR4_TZIC1_Pos GTZC_CFGR4_TZIC1_Pos |
| #define | GTZC_TZIC1_SR4_TZIC1_Msk GTZC_CFGR4_TZIC1_Msk |
| #define | GTZC_TZIC1_SR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos |
| #define | GTZC_TZIC1_SR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk |
| #define | GTZC_TZIC1_SR4_FSMC_MEM_Pos GTZC_CFGR4_FSMC_MEM_Pos |
| #define | GTZC_TZIC1_SR4_FSMC_MEM_Msk GTZC_CFGR4_FSMC_MEM_Msk |
| #define | GTZC_TZIC1_SR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos |
| #define | GTZC_TZIC1_SR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk |
| #define | GTZC_TZIC1_SR4_OCTOSPI2_MEM_Pos GTZC_CFGR4_OCTOSPI2_MEM_Pos |
| #define | GTZC_TZIC1_SR4_OCTOSPI2_MEM_Msk GTZC_CFGR4_OCTOSPI2_MEM_Msk |
| #define | GTZC_TZIC1_SR4_HSPI1_MEM_Pos GTZC_CFGR4_HSPI1_MEM_Pos |
| #define | GTZC_TZIC1_SR4_HSPI1_MEM_Msk GTZC_CFGR4_HSPI1_MEM_Msk |
| #define | GTZC_TZIC1_SR4_SRAM6_Pos GTZC_CFGR4_SRAM6_Pos |
| #define | GTZC_TZIC1_SR4_SRAM6_Msk GTZC_CFGR4_SRAM6_Msk |
| #define | GTZC_TZIC1_SR4_MPCBB6_REG_Pos GTZC_CFGR4_MPCBB6_REG_Pos |
| #define | GTZC_TZIC1_SR4_MPCBB6_REG_Msk GTZC_CFGR4_MPCBB6_REG_Msk |
| #define | GTZC_TZIC1_SR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos |
| #define | GTZC_TZIC1_SR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk |
| #define | GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos |
| #define | GTZC_TZIC1_SR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk |
| #define | GTZC_TZIC1_SR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos |
| #define | GTZC_TZIC1_SR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk |
| #define | GTZC_TZIC1_SR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos |
| #define | GTZC_TZIC1_SR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk |
| #define | GTZC_TZIC1_SR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos |
| #define | GTZC_TZIC1_SR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk |
| #define | GTZC_TZIC1_SR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos |
| #define | GTZC_TZIC1_SR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk |
| #define | GTZC_TZIC1_SR4_SRAM5_Pos GTZC_CFGR4_SRAM5_Pos |
| #define | GTZC_TZIC1_SR4_SRAM5_Msk GTZC_CFGR4_SRAM5_Msk |
| #define | GTZC_TZIC1_SR4_MPCBB5_REG_Pos GTZC_CFGR4_MPCBB5_REG_Pos |
| #define | GTZC_TZIC1_SR4_MPCBB5_REG_Msk GTZC_CFGR4_MPCBB5_REG_Msk |
| #define | GTZC_TZIC2_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos |
| #define | GTZC_TZIC2_SR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk |
| #define | GTZC_TZIC2_SR1_LPUART1_Pos GTZC_CFGR1_LPUART1_Pos |
| #define | GTZC_TZIC2_SR1_LPUART1_Msk GTZC_CFGR1_LPUART1_Msk |
| #define | GTZC_TZIC2_SR1_I2C3_Pos GTZC_CFGR1_I2C3_Pos |
| #define | GTZC_TZIC2_SR1_I2C3_Msk GTZC_CFGR1_I2C3_Msk |
| #define | GTZC_TZIC2_SR1_LPTIM1_Pos GTZC_CFGR1_LPTIM1_Pos |
| #define | GTZC_TZIC2_SR1_LPTIM1_Msk GTZC_CFGR1_LPTIM1_Msk |
| #define | GTZC_TZIC2_SR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos |
| #define | GTZC_TZIC2_SR1_LPTIM3_Msk GTZC_CFGR1_LPTIM3_Msk |
| #define | GTZC_TZIC2_SR1_LPTIM4_Pos GTZC_CFGR1_LPTIM4_Pos |
| #define | GTZC_TZIC2_SR1_LPTIM4_Msk GTZC_CFGR1_LPTIM4_Msk |
| #define | GTZC_TZIC2_SR1_OPAMP_Pos GTZC_CFGR1_OPAMP_Pos |
| #define | GTZC_TZIC2_SR1_OPAMP_Msk GTZC_CFGR1_OPAMP_Msk |
| #define | GTZC_TZIC2_SR1_COMP_Pos GTZC_CFGR1_COMP_Pos |
| #define | GTZC_TZIC2_SR1_COMP_Msk GTZC_CFGR1_COMP_Msk |
| #define | GTZC_TZIC2_SR1_ADC4_Pos GTZC_CFGR1_ADC4_Pos |
| #define | GTZC_TZIC2_SR1_ADC4_Msk GTZC_CFGR1_ADC4_Msk |
| #define | GTZC_TZIC2_SR1_VREFBUF_Pos GTZC_CFGR1_VREFBUF_Pos |
| #define | GTZC_TZIC2_SR1_VREFBUF_Msk GTZC_CFGR1_VREFBUF_Msk |
| #define | GTZC_TZIC2_SR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos |
| #define | GTZC_TZIC2_SR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk |
| #define | GTZC_TZIC2_SR1_ADF1_Pos GTZC_CFGR1_ADF1_Pos |
| #define | GTZC_TZIC2_SR1_ADF1_Msk GTZC_CFGR1_ADF1_Msk |
| #define | GTZC_TZIC2_SR2_SYSCFG_Pos GTZC_CFGR2_SYSCFG_Pos |
| #define | GTZC_TZIC2_SR2_SYSCFG_Msk GTZC_CFGR2_SYSCFG_Msk |
| #define | GTZC_TZIC2_SR2_RTC_Pos GTZC_CFGR2_RTC_Pos |
| #define | GTZC_TZIC2_SR2_RTC_Msk GTZC_CFGR2_RTC_Msk |
| #define | GTZC_TZIC2_SR2_TAMP_Pos GTZC_CFGR2_TAMP_Pos |
| #define | GTZC_TZIC2_SR2_TAMP_Msk GTZC_CFGR2_TAMP_Msk |
| #define | GTZC_TZIC2_SR2_PWR_Pos GTZC_CFGR2_PWR_Pos |
| #define | GTZC_TZIC2_SR2_PWR_Msk GTZC_CFGR2_PWR_Msk |
| #define | GTZC_TZIC2_SR2_RCC_Pos GTZC_CFGR2_RCC_Pos |
| #define | GTZC_TZIC2_SR2_RCC_Msk GTZC_CFGR2_RCC_Msk |
| #define | GTZC_TZIC2_SR2_LPDMA1_Pos GTZC_CFGR2_LPDMA1_Pos |
| #define | GTZC_TZIC2_SR2_LPDMA1_Msk GTZC_CFGR2_LPDMA1_Msk |
| #define | GTZC_TZIC2_SR2_EXTI_Pos GTZC_CFGR2_EXTI_Pos |
| #define | GTZC_TZIC2_SR2_EXTI_Msk GTZC_CFGR2_EXTI_Msk |
| #define | GTZC_TZIC2_SR2_TZSC2_Pos GTZC_CFGR2_TZSC2_Pos |
| #define | GTZC_TZIC2_SR2_TZSC2_Msk GTZC_CFGR2_TZSC2_Msk |
| #define | GTZC_TZIC2_SR2_TZIC2_Pos GTZC_CFGR2_TZIC2_Pos |
| #define | GTZC_TZIC2_SR2_TZIC2_Msk GTZC_CFGR2_TZIC2_Msk |
| #define | GTZC_TZIC2_SR2_SRAM4_Pos GTZC_CFGR2_SRAM4_Pos |
| #define | GTZC_TZIC2_SR2_SRAM4_Msk GTZC_CFGR2_SRAM4_Msk |
| #define | GTZC_TZIC2_SR2_MPCBB4_REG_Pos GTZC_CFGR2_MPCBB4_REG_Pos |
| #define | GTZC_TZIC2_SR2_MPCBB4_REG_Msk GTZC_CFGR2_MPCBB4_REG_Msk |
| #define | GTZC_TZIC1_FCR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos |
| #define | GTZC_TZIC1_FCR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk |
| #define | GTZC_TZIC1_FCR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos |
| #define | GTZC_TZIC1_FCR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk |
| #define | GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos |
| #define | GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk |
| #define | GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos |
| #define | GTZC_TZIC1_FCR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk |
| #define | GTZC_TZIC1_FCR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos |
| #define | GTZC_TZIC1_FCR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk |
| #define | GTZC_TZIC1_FCR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos |
| #define | GTZC_TZIC1_FCR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk |
| #define | GTZC_TZIC1_FCR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos |
| #define | GTZC_TZIC1_FCR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk |
| #define | GTZC_TZIC1_FCR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos |
| #define | GTZC_TZIC1_FCR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk |
| #define | GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos |
| #define | GTZC_TZIC1_FCR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk |
| #define | GTZC_TZIC1_FCR1_USART2_Pos GTZC_CFGR1_USART2_Pos |
| #define | GTZC_TZIC1_FCR1_USART2_Msk GTZC_CFGR1_USART2_Msk |
| #define | GTZC_TZIC1_FCR1_USART3_Pos GTZC_CFGR1_USART3_Pos |
| #define | GTZC_TZIC1_FCR1_USART3_Msk GTZC_CFGR1_USART3_Msk |
| #define | GTZC_TZIC1_FCR1_UART4_Pos GTZC_CFGR1_UART4_Pos |
| #define | GTZC_TZIC1_FCR1_UART4_Msk GTZC_CFGR1_UART4_Msk |
| #define | GTZC_TZIC1_FCR1_UART5_Pos GTZC_CFGR1_UART5_Pos |
| #define | GTZC_TZIC1_FCR1_UART5_Msk GTZC_CFGR1_UART5_Msk |
| #define | GTZC_TZIC1_FCR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos |
| #define | GTZC_TZIC1_FCR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk |
| #define | GTZC_TZIC1_FCR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos |
| #define | GTZC_TZIC1_FCR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk |
| #define | GTZC_TZIC1_FCR1_CRS_Pos GTZC_CFGR1_CRS_Pos |
| #define | GTZC_TZIC1_FCR1_CRS_Msk GTZC_CFGR1_CRS_Msk |
| #define | GTZC_TZIC1_FCR1_I2C4_Pos GTZC_CFGR1_I2C4_Pos |
| #define | GTZC_TZIC1_FCR1_I2C4_Msk GTZC_CFGR1_I2C4_Msk |
| #define | GTZC_TZIC1_FCR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos |
| #define | GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk |
| #define | GTZC_TZIC1_FCR1_FDCAN1_Pos GTZC_CFGR1_FDCAN1_Pos |
| #define | GTZC_TZIC1_FCR1_FDCAN1_Msk GTZC_CFGR1_FDCAN1_Msk |
| #define | GTZC_TZIC1_FCR1_UCPD1_Pos GTZC_CFGR1_UCPD1_Pos |
| #define | GTZC_TZIC1_FCR1_UCPD1_Msk GTZC_CFGR1_UCPD1_Msk |
| #define | GTZC_TZIC1_FCR1_USART6_Pos GTZC_CFGR1_USART6_Pos |
| #define | GTZC_TZIC1_FCR1_USART6_Msk GTZC_CFGR1_USART6_Msk |
| #define | GTZC_TZIC1_FCR1_I2C5_Pos GTZC_CFGR1_I2C5_Pos |
| #define | GTZC_TZIC1_FCR1_I2C5_Msk GTZC_CFGR1_I2C5_Msk |
| #define | GTZC_TZIC1_FCR1_I2C6_Pos GTZC_CFGR1_I2C6_Pos |
| #define | GTZC_TZIC1_FCR1_I2C6_Msk GTZC_CFGR1_I2C6_Msk |
| #define | GTZC_TZIC1_FCR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos |
| #define | GTZC_TZIC1_FCR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk |
| #define | GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos |
| #define | GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk |
| #define | GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos |
| #define | GTZC_TZIC1_FCR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk |
| #define | GTZC_TZIC1_FCR2_USART1_Pos GTZC_CFGR2_USART1_Pos |
| #define | GTZC_TZIC1_FCR2_USART1_Msk GTZC_CFGR2_USART1_Msk |
| #define | GTZC_TZIC1_FCR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos |
| #define | GTZC_TZIC1_FCR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk |
| #define | GTZC_TZIC1_FCR2_TIM16_Pos GTZC_CFGR2_TIM16_Pos |
| #define | GTZC_TZIC1_FCR2_TIM16_Msk GTZC_CFGR2_TIM16_Msk |
| #define | GTZC_TZIC1_FCR2_TIM17_Pos GTZC_CFGR2_TIM17_Pos |
| #define | GTZC_TZIC1_FCR2_TIM17_Msk GTZC_CFGR2_TIM17_Msk |
| #define | GTZC_TZIC1_FCR2_SAI1_Pos GTZC_CFGR2_SAI1_Pos |
| #define | GTZC_TZIC1_FCR2_SAI1_Msk GTZC_CFGR2_SAI1_Msk |
| #define | GTZC_TZIC1_FCR2_SAI2_Pos GTZC_CFGR2_SAI2_Pos |
| #define | GTZC_TZIC1_FCR2_SAI2_Msk GTZC_CFGR2_SAI2_Msk |
| #define | GTZC_TZIC1_FCR2_LTDCUSB_Pos GTZC_CFGR2_LTDCUSB_Pos |
| #define | GTZC_TZIC1_FCR2_LTDCUSB_Msk GTZC_CFGR2_LTDCUSB_Msk |
| #define | GTZC_TZIC1_FCR2_DSI_Pos GTZC_CFGR2_DSI_Pos |
| #define | GTZC_TZIC1_FCR2_DSI_Msk GTZC_CFGR2_DSI_Msk |
| #define | GTZC_TZIC1_FCR2_GFXTIM_Pos GTZC_CFGR2_GFXTIM_Pos |
| #define | GTZC_TZIC1_FCR2_GFXTIM_Msk GTZC_CFGR2_GFXTIM_Msk |
| #define | GTZC_TZIC1_FCR3_MDF1_Pos GTZC_CFGR3_MDF1_Pos |
| #define | GTZC_TZIC1_FCR3_MDF1_Msk GTZC_CFGR3_MDF1_Msk |
| #define | GTZC_TZIC1_FCR3_CORDIC_Pos GTZC_CFGR3_CORDIC_Pos |
| #define | GTZC_TZIC1_FCR3_CORDIC_Msk GTZC_CFGR3_CORDIC_Msk |
| #define | GTZC_TZIC1_FCR3_FMAC_Pos GTZC_CFGR3_FMAC_Pos |
| #define | GTZC_TZIC1_FCR3_FMAC_Msk GTZC_CFGR3_FMAC_Msk |
| #define | GTZC_TZIC1_FCR3_CRC_Pos GTZC_CFGR3_CRC_Pos |
| #define | GTZC_TZIC1_FCR3_CRC_Msk GTZC_CFGR3_CRC_Msk |
| #define | GTZC_TZIC1_FCR3_TSC_Pos GTZC_CFGR3_TSC_Pos |
| #define | GTZC_TZIC1_FCR3_TSC_Msk GTZC_CFGR3_TSC_Msk |
| #define | GTZC_TZIC1_FCR3_DMA2D_Pos GTZC_CFGR3_DMA2D_Pos |
| #define | GTZC_TZIC1_FCR3_DMA2D_Msk GTZC_CFGR3_DMA2D_Msk |
| #define | GTZC_TZIC1_FCR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos |
| #define | GTZC_TZIC1_FCR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk |
| #define | GTZC_TZIC1_FCR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos |
| #define | GTZC_TZIC1_FCR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk |
| #define | GTZC_TZIC1_FCR3_ADC12_Pos GTZC_CFGR3_ADC12_Pos |
| #define | GTZC_TZIC1_FCR3_ADC12_Msk GTZC_CFGR3_ADC12_Msk |
| #define | GTZC_TZIC1_FCR3_DCMI_Pos GTZC_CFGR3_DCMI_Pos |
| #define | GTZC_TZIC1_FCR3_DCMI_Msk GTZC_CFGR3_DCMI_Msk |
| #define | GTZC_TZIC1_FCR3_OTG_Pos GTZC_CFGR3_OTG_Pos |
| #define | GTZC_TZIC1_FCR3_OTG_Msk GTZC_CFGR3_OTG_Msk |
| #define | GTZC_TZIC1_FCR3_AES_Pos GTZC_CFGR3_AES_Pos |
| #define | GTZC_TZIC1_FCR3_AES_Msk GTZC_CFGR3_AES_Msk |
| #define | GTZC_TZIC1_FCR3_HASH_Pos GTZC_CFGR3_HASH_Pos |
| #define | GTZC_TZIC1_FCR3_HASH_Msk GTZC_CFGR3_HASH_Msk |
| #define | GTZC_TZIC1_FCR3_RNG_Pos GTZC_CFGR3_RNG_Pos |
| #define | GTZC_TZIC1_FCR3_RNG_Msk GTZC_CFGR3_RNG_Msk |
| #define | GTZC_TZIC1_FCR3_PKA_Pos GTZC_CFGR3_PKA_Pos |
| #define | GTZC_TZIC1_FCR3_PKA_Msk GTZC_CFGR3_PKA_Msk |
| #define | GTZC_TZIC1_FCR3_SAES_Pos GTZC_CFGR3_SAES_Pos |
| #define | GTZC_TZIC1_FCR3_SAES_Msk GTZC_CFGR3_SAES_Msk |
| #define | GTZC_TZIC1_FCR3_OCTOSPIM_Pos GTZC_CFGR3_OCTOSPIM_Pos |
| #define | GTZC_TZIC1_FCR3_OCTOSPIM_Msk GTZC_CFGR3_OCTOSPIM_Msk |
| #define | GTZC_TZIC1_FCR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos |
| #define | GTZC_TZIC1_FCR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk |
| #define | GTZC_TZIC1_FCR3_SDMMC2_Pos GTZC_CFGR3_SDMMC2_Pos |
| #define | GTZC_TZIC1_FCR3_SDMMC2_Msk GTZC_CFGR3_SDMMC2_Msk |
| #define | GTZC_TZIC1_FCR3_FSMC_REG_Pos GTZC_CFGR3_FSMC_REG_Pos |
| #define | GTZC_TZIC1_FCR3_FSMC_REG_Msk GTZC_CFGR3_FSMC_REG_Msk |
| #define | GTZC_TZIC1_FCR3_OCTOSPI1_REG_Pos GTZC_CFGR3_OCTOSPI1_REG_Pos |
| #define | GTZC_TZIC1_FCR3_OCTOSPI1_REG_Msk GTZC_CFGR3_OCTOSPI1_REG_Msk |
| #define | GTZC_TZIC1_FCR3_OCTOSPI2_REG_Pos GTZC_CFGR3_OCTOSPI2_REG_Pos |
| #define | GTZC_TZIC1_FCR3_OCTOSPI2_REG_Msk GTZC_CFGR3_OCTOSPI2_REG_Msk |
| #define | GTZC_TZIC1_FCR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos |
| #define | GTZC_TZIC1_FCR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk |
| #define | GTZC_TZIC1_FCR3_GPU2D_Pos GTZC_CFGR3_GPU2D_Pos |
| #define | GTZC_TZIC1_FCR3_GPU2D_Msk GTZC_CFGR3_GPU2D_Msk |
| #define | GTZC_TZIC1_FCR3_GFXMMU_Pos GTZC_CFGR3_GFXMMU_Pos |
| #define | GTZC_TZIC1_FCR3_GFXMMU_Msk GTZC_CFGR3_GFXMMU_Msk |
| #define | GTZC_TZIC1_FCR3_GFXMMU_REG_Pos GTZC_CFGR3_GFXMMU_REG_Pos |
| #define | GTZC_TZIC1_FCR3_GFXMMU_REG_Msk GTZC_CFGR3_GFXMMU_REG_Msk |
| #define | GTZC_TZIC1_FCR3_HSPI1_REG_Pos GTZC_CFGR3_HSPI1_REG_Pos |
| #define | GTZC_TZIC1_FCR3_HSPI1_REG_Msk GTZC_CFGR3_HSPI1_REG_Msk |
| #define | GTZC_TZIC1_FCR3_DCACHE2_REG_Pos GTZC_CFGR3_DCACHE2_REG_Pos |
| #define | GTZC_TZIC1_FCR3_DCACHE2_REG_Msk GTZC_CFGR3_DCACHE2_REG_Msk |
| #define | GTZC_TZIC1_FCR3_JPEG_Pos GTZC_CFGR3_JPEG_REG_Pos |
| #define | GTZC_TZIC1_FCR3_JPEG_Msk GTZC_CFGR3_JPEG_REG_Msk |
| #define | GTZC_TZIC1_FCR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos |
| #define | GTZC_TZIC1_FCR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk |
| #define | GTZC_TZIC1_FCR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos |
| #define | GTZC_TZIC1_FCR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk |
| #define | GTZC_TZIC1_FCR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos |
| #define | GTZC_TZIC1_FCR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk |
| #define | GTZC_TZIC1_FCR4_OTFDEC1_Pos GTZC_CFGR4_OTFDEC1_Pos |
| #define | GTZC_TZIC1_FCR4_OTFDEC1_Msk GTZC_CFGR4_OTFDEC1_Msk |
| #define | GTZC_TZIC1_FCR4_OTFDEC2_Pos GTZC_CFGR4_OTFDEC2_Pos |
| #define | GTZC_TZIC1_FCR4_OTFDEC2_Msk GTZC_CFGR4_OTFDEC2_Msk |
| #define | GTZC_TZIC1_FCR4_TZSC1_Pos GTZC_CFGR4_TZSC1_Pos |
| #define | GTZC_TZIC1_FCR4_TZSC1_Msk GTZC_CFGR4_TZSC1_Msk |
| #define | GTZC_TZIC1_FCR4_TZIC1_Pos GTZC_CFGR4_TZIC1_Pos |
| #define | GTZC_TZIC1_FCR4_TZIC1_Msk GTZC_CFGR4_TZIC1_Msk |
| #define | GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos |
| #define | GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk |
| #define | GTZC_TZIC1_FCR4_FSMC_MEM_Pos GTZC_CFGR4_FSMC_MEM_Pos |
| #define | GTZC_TZIC1_FCR4_FSMC_MEM_Msk GTZC_CFGR4_FSMC_MEM_Msk |
| #define | GTZC_TZIC1_FCR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos |
| #define | GTZC_TZIC1_FCR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk |
| #define | GTZC_TZIC1_FCR4_OCTOSPI2_MEM_Pos GTZC_CFGR4_OCTOSPI2_MEM_Pos |
| #define | GTZC_TZIC1_FCR4_OCTOSPI2_MEM_Msk GTZC_CFGR4_OCTOSPI2_MEM_Msk |
| #define | GTZC_TZIC1_FCR4_HSPI1_MEM_Pos GTZC_CFGR4_HSPI1_MEM_Pos |
| #define | GTZC_TZIC1_FCR4_HSPI1_MEM_Msk GTZC_CFGR4_HSPI1_MEM_Msk |
| #define | GTZC_TZIC1_FCR4_SRAM6_Pos GTZC_CFGR4_SRAM6_Pos |
| #define | GTZC_TZIC1_FCR4_SRAM6_Msk GTZC_CFGR4_SRAM6_Msk |
| #define | GTZC_TZIC1_FCR4_MPCBB6_REG_Pos GTZC_CFGR4_MPCBB6_REG_Pos |
| #define | GTZC_TZIC1_FCR4_MPCBB6_REG_Msk GTZC_CFGR4_MPCBB6_REG_Msk |
| #define | GTZC_TZIC1_FCR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos |
| #define | GTZC_TZIC1_FCR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk |
| #define | GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos |
| #define | GTZC_TZIC1_FCR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk |
| #define | GTZC_TZIC1_FCR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos |
| #define | GTZC_TZIC1_FCR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk |
| #define | GTZC_TZIC1_FCR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos |
| #define | GTZC_TZIC1_FCR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk |
| #define | GTZC_TZIC1_FCR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos |
| #define | GTZC_TZIC1_FCR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk |
| #define | GTZC_TZIC1_FCR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos |
| #define | GTZC_TZIC1_FCR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk |
| #define | GTZC_TZIC1_FCR4_SRAM5_Pos GTZC_CFGR4_SRAM5_Pos |
| #define | GTZC_TZIC1_FCR4_SRAM5_Msk GTZC_CFGR4_SRAM5_Msk |
| #define | GTZC_TZIC1_FCR4_MPCBB5_REG_Pos GTZC_CFGR4_MPCBB5_REG_Pos |
| #define | GTZC_TZIC1_FCR4_MPCBB5_REG_Msk GTZC_CFGR4_MPCBB5_REG_Msk |
| #define | GTZC_TZIC2_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos |
| #define | GTZC_TZIC2_FCR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk |
| #define | GTZC_TZIC2_FCR1_LPUART1_Pos GTZC_CFGR1_LPUART1_Pos |
| #define | GTZC_TZIC2_FCR1_LPUART1_Msk GTZC_CFGR1_LPUART1_Msk |
| #define | GTZC_TZIC2_FCR1_I2C3_Pos GTZC_CFGR1_I2C3_Pos |
| #define | GTZC_TZIC2_FCR1_I2C3_Msk GTZC_CFGR1_I2C3_Msk |
| #define | GTZC_TZIC2_FCR1_LPTIM1_Pos GTZC_CFGR1_LPTIM1_Pos |
| #define | GTZC_TZIC2_FCR1_LPTIM1_Msk GTZC_CFGR1_LPTIM1_Msk |
| #define | GTZC_TZIC2_FCR1_LPTIM3_Pos GTZC_CFGR1_LPTIM3_Pos |
| #define | GTZC_TZIC2_FCR1_LPTIM3_Msk GTZC_CFGR1_LPTIM3_Msk |
| #define | GTZC_TZIC2_FCR1_LPTIM4_Pos GTZC_CFGR1_LPTIM4_Pos |
| #define | GTZC_TZIC2_FCR1_LPTIM4_Msk GTZC_CFGR1_LPTIM4_Msk |
| #define | GTZC_TZIC2_FCR1_OPAMP_Pos GTZC_CFGR1_OPAMP_Pos |
| #define | GTZC_TZIC2_FCR1_OPAMP_Msk GTZC_CFGR1_OPAMP_Msk |
| #define | GTZC_TZIC2_FCR1_COMP_Pos GTZC_CFGR1_COMP_Pos |
| #define | GTZC_TZIC2_FCR1_COMP_Msk GTZC_CFGR1_COMP_Msk |
| #define | GTZC_TZIC2_FCR1_ADC4_Pos GTZC_CFGR1_ADC4_Pos |
| #define | GTZC_TZIC2_FCR1_ADC4_Msk GTZC_CFGR1_ADC4_Msk |
| #define | GTZC_TZIC2_FCR1_VREFBUF_Pos GTZC_CFGR1_VREFBUF_Pos |
| #define | GTZC_TZIC2_FCR1_VREFBUF_Msk GTZC_CFGR1_VREFBUF_Msk |
| #define | GTZC_TZIC2_FCR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos |
| #define | GTZC_TZIC2_FCR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk |
| #define | GTZC_TZIC2_FCR1_ADF1_Pos GTZC_CFGR1_ADF1_Pos |
| #define | GTZC_TZIC2_FCR1_ADF1_Msk GTZC_CFGR1_ADF1_Msk |
| #define | GTZC_TZIC2_FCR2_SYSCFG_Pos GTZC_CFGR2_SYSCFG_Pos |
| #define | GTZC_TZIC2_FCR2_SYSCFG_Msk GTZC_CFGR2_SYSCFG_Msk |
| #define | GTZC_TZIC2_FCR2_RTC_Pos GTZC_CFGR2_RTC_Pos |
| #define | GTZC_TZIC2_FCR2_RTC_Msk GTZC_CFGR2_RTC_Msk |
| #define | GTZC_TZIC2_FCR2_TAMP_Pos GTZC_CFGR2_TAMP_Pos |
| #define | GTZC_TZIC2_FCR2_TAMP_Msk GTZC_CFGR2_TAMP_Msk |
| #define | GTZC_TZIC2_FCR2_PWR_Pos GTZC_CFGR2_PWR_Pos |
| #define | GTZC_TZIC2_FCR2_PWR_Msk GTZC_CFGR2_PWR_Msk |
| #define | GTZC_TZIC2_FCR2_RCC_Pos GTZC_CFGR2_RCC_Pos |
| #define | GTZC_TZIC2_FCR2_RCC_Msk GTZC_CFGR2_RCC_Msk |
| #define | GTZC_TZIC2_FCR2_LPDMA1_Pos GTZC_CFGR2_LPDMA1_Pos |
| #define | GTZC_TZIC2_FCR2_LPDMA1_Msk GTZC_CFGR2_LPDMA1_Msk |
| #define | GTZC_TZIC2_FCR2_EXTI_Pos GTZC_CFGR2_EXTI_Pos |
| #define | GTZC_TZIC2_FCR2_EXTI_Msk GTZC_CFGR2_EXTI_Msk |
| #define | GTZC_TZIC2_FCR2_TZSC2_Pos GTZC_CFGR2_TZSC2_Pos |
| #define | GTZC_TZIC2_FCR2_TZSC2_Msk GTZC_CFGR2_TZSC2_Msk |
| #define | GTZC_TZIC2_FCR2_TZIC2_Pos GTZC_CFGR2_TZIC2_Pos |
| #define | GTZC_TZIC2_FCR2_TZIC2_Msk GTZC_CFGR2_TZIC2_Msk |
| #define | GTZC_TZIC2_FCR2_SRAM4_Pos GTZC_CFGR2_SRAM4_Pos |
| #define | GTZC_TZIC2_FCR2_SRAM4_Msk GTZC_CFGR2_SRAM4_Msk |
| #define | GTZC_TZIC2_FCR2_MPCBB4_REG_Pos GTZC_CFGR2_MPCBB4_REG_Pos |
| #define | GTZC_TZIC2_FCR2_MPCBB4_REG_Msk GTZC_CFGR2_MPCBB4_REG_Msk |
| #define | GTZC_MPCBB_CR_GLOCK_Pos (0U) |
| #define | GTZC_MPCBB_CR_GLOCK_Msk (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos) |
| #define | GTZC_MPCBB_CR_INVSECSTATE_Pos (30U) |
| #define | GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) |
| #define | GTZC_MPCBB_CR_SRWILADIS_Pos (31U) |
| #define | GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos (0U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK0_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos (1U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK1_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos (2U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK2_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos (3U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK3_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos (4U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK4_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos (5U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK5_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos (6U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK6_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos (7U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK7_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos (8U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK8_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos (9U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK9_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos (10U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK10_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos (11U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK11_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos (12U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK12_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos (13U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK13_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos (14U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK14_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos (15U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK15_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos (16U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK16_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos (17U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK17_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos (18U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK18_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos (19U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK19_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos (20U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK20_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos (21U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK21_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos (22U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK22_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos (23U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK23_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos (24U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK24_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos (25U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK25_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos (26U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK26_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos (27U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK27_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos (28U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK28_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos (29U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK29_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos (30U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK30_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos (31U) |
| #define | GTZC_MPCBB_CFGLOCKR1_SPLCK31_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK32_Pos (0U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK32_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK33_Pos (1U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK33_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK33_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK34_Pos (2U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK34_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK34_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK35_Pos (3U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK35_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK35_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK36_Pos (4U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK36_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK36_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK37_Pos (5U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK37_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK37_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK38_Pos (6U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK38_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK38_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK39_Pos (7U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK39_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK39_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK40_Pos (8U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK40_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK40_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK41_Pos (9U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK41_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK41_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK42_Pos (10U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK42_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK42_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK43_Pos (11U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK43_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK43_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK44_Pos (12U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK44_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK44_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK45_Pos (13U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK45_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK45_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK46_Pos (14U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK46_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK46_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK47_Pos (15U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK47_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK47_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK48_Pos (16U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK48_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK48_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK49_Pos (17U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK49_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK49_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK50_Pos (18U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK50_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK50_Pos) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK51_Pos (19U) |
| #define | GTZC_MPCBB_CFGLOCKR2_SPLCK51_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR2_SPLCK51_Pos) |
| #define | UCPD_CFG1_HBITCLKDIV_Pos (0U) |
| #define | UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) |
| #define | UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk |
| #define | UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) |
| #define | UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) |
| #define | UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) |
| #define | UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) |
| #define | UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) |
| #define | UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) |
| #define | UCPD_CFG1_IFRGAP_Pos (6U) |
| #define | UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) |
| #define | UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk |
| #define | UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) |
| #define | UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) |
| #define | UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) |
| #define | UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) |
| #define | UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) |
| #define | UCPD_CFG1_TRANSWIN_Pos (11U) |
| #define | UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) |
| #define | UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk |
| #define | UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) |
| #define | UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) |
| #define | UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) |
| #define | UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) |
| #define | UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) |
| #define | UCPD_CFG1_PSC_UCPDCLK_Pos (17U) |
| #define | UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) |
| #define | UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk |
| #define | UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) |
| #define | UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) |
| #define | UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) |
| #define | UCPD_CFG1_RXORDSETEN_Pos (20U) |
| #define | UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos) |
| #define | UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk |
| #define | UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos) |
| #define | UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos) |
| #define | UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos) |
| #define | UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos) |
| #define | UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos) |
| #define | UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos) |
| #define | UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos) |
| #define | UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos) |
| #define | UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos) |
| #define | UCPD_CFG1_TXDMAEN_Pos (29U) |
| #define | UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) |
| #define | UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk |
| #define | UCPD_CFG1_RXDMAEN_Pos (30U) |
| #define | UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) |
| #define | UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk |
| #define | UCPD_CFG1_UCPDEN_Pos (31U) |
| #define | UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) |
| #define | UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk |
| #define | UCPD_CFG2_RXFILTDIS_Pos (0U) |
| #define | UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) |
| #define | UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk |
| #define | UCPD_CFG2_RXFILT2N3_Pos (1U) |
| #define | UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) |
| #define | UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk |
| #define | UCPD_CFG2_FORCECLK_Pos (2U) |
| #define | UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) |
| #define | UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk |
| #define | UCPD_CFG2_WUPEN_Pos (3U) |
| #define | UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) |
| #define | UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk |
| #define | UCPD_CFG2_RXAFILTEN_Pos (8U) |
| #define | UCPD_CFG2_RXAFILTEN_Msk (0x1UL << UCPD_CFG2_RXAFILTEN_Pos) |
| #define | UCPD_CFG2_RXAFILTEN UCPD_CFG2_RXAFILTEN_Msk |
| #define | UCPD_CFG3_TRIM_CC1_RD_Pos (0U) |
| #define | UCPD_CFG3_TRIM_CC1_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RD_Pos) |
| #define | UCPD_CFG3_TRIM_CC1_RD UCPD_CFG3_TRIM_CC1_RD_Msk |
| #define | UCPD_CFG3_TRIM_CC1_RP_Pos (9U) |
| #define | UCPD_CFG3_TRIM_CC1_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RP_Pos) |
| #define | UCPD_CFG3_TRIM_CC1_RP UCPD_CFG3_TRIM_CC1_RP_Msk |
| #define | UCPD_CFG3_TRIM_CC2_RD_Pos (16U) |
| #define | UCPD_CFG3_TRIM_CC2_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RD_Pos) |
| #define | UCPD_CFG3_TRIM_CC2_RD UCPD_CFG3_TRIM_CC2_RD_Msk |
| #define | UCPD_CFG3_TRIM_CC2_RP_Pos (25U) |
| #define | UCPD_CFG3_TRIM_CC2_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RP_Pos) |
| #define | UCPD_CFG3_TRIM_CC2_RP UCPD_CFG3_TRIM_CC2_RP_Msk |
| #define | UCPD_CR_TXMODE_Pos (0U) |
| #define | UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) |
| #define | UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk |
| #define | UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) |
| #define | UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) |
| #define | UCPD_CR_TXSEND_Pos (2U) |
| #define | UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) |
| #define | UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk |
| #define | UCPD_CR_TXHRST_Pos (3U) |
| #define | UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) |
| #define | UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk |
| #define | UCPD_CR_RXMODE_Pos (4U) |
| #define | UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) |
| #define | UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk |
| #define | UCPD_CR_PHYRXEN_Pos (5U) |
| #define | UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) |
| #define | UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk |
| #define | UCPD_CR_PHYCCSEL_Pos (6U) |
| #define | UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) |
| #define | UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk |
| #define | UCPD_CR_ANASUBMODE_Pos (7U) |
| #define | UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) |
| #define | UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk |
| #define | UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) |
| #define | UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) |
| #define | UCPD_CR_ANAMODE_Pos (9U) |
| #define | UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) |
| #define | UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk |
| #define | UCPD_CR_CCENABLE_Pos (10U) |
| #define | UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) |
| #define | UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk |
| #define | UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) |
| #define | UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) |
| #define | UCPD_CR_FRSRXEN_Pos (16U) |
| #define | UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) |
| #define | UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk |
| #define | UCPD_CR_FRSTX_Pos (17U) |
| #define | UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) |
| #define | UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk |
| #define | UCPD_CR_RDCH_Pos (18U) |
| #define | UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) |
| #define | UCPD_CR_RDCH UCPD_CR_RDCH_Msk |
| #define | UCPD_CR_CC1TCDIS_Pos (20U) |
| #define | UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) |
| #define | UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk |
| #define | UCPD_CR_CC2TCDIS_Pos (21U) |
| #define | UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) |
| #define | UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk |
| #define | UCPD_IMR_TXISIE_Pos (0U) |
| #define | UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) |
| #define | UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk |
| #define | UCPD_IMR_TXMSGDISCIE_Pos (1U) |
| #define | UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) |
| #define | UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk |
| #define | UCPD_IMR_TXMSGSENTIE_Pos (2U) |
| #define | UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) |
| #define | UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk |
| #define | UCPD_IMR_TXMSGABTIE_Pos (3U) |
| #define | UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) |
| #define | UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk |
| #define | UCPD_IMR_HRSTDISCIE_Pos (4U) |
| #define | UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) |
| #define | UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk |
| #define | UCPD_IMR_HRSTSENTIE_Pos (5U) |
| #define | UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) |
| #define | UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk |
| #define | UCPD_IMR_TXUNDIE_Pos (6U) |
| #define | UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) |
| #define | UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk |
| #define | UCPD_IMR_RXNEIE_Pos (8U) |
| #define | UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) |
| #define | UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk |
| #define | UCPD_IMR_RXORDDETIE_Pos (9U) |
| #define | UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) |
| #define | UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk |
| #define | UCPD_IMR_RXHRSTDETIE_Pos (10U) |
| #define | UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) |
| #define | UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk |
| #define | UCPD_IMR_RXOVRIE_Pos (11U) |
| #define | UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) |
| #define | UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk |
| #define | UCPD_IMR_RXMSGENDIE_Pos (12U) |
| #define | UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) |
| #define | UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk |
| #define | UCPD_IMR_TYPECEVT1IE_Pos (14U) |
| #define | UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) |
| #define | UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk |
| #define | UCPD_IMR_TYPECEVT2IE_Pos (15U) |
| #define | UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) |
| #define | UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk |
| #define | UCPD_IMR_FRSEVTIE_Pos (20U) |
| #define | UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) |
| #define | UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk |
| #define | UCPD_SR_TXIS_Pos (0U) |
| #define | UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) |
| #define | UCPD_SR_TXIS UCPD_SR_TXIS_Msk |
| #define | UCPD_SR_TXMSGDISC_Pos (1U) |
| #define | UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) |
| #define | UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk |
| #define | UCPD_SR_TXMSGSENT_Pos (2U) |
| #define | UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) |
| #define | UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk |
| #define | UCPD_SR_TXMSGABT_Pos (3U) |
| #define | UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) |
| #define | UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk |
| #define | UCPD_SR_HRSTDISC_Pos (4U) |
| #define | UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) |
| #define | UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk |
| #define | UCPD_SR_HRSTSENT_Pos (5U) |
| #define | UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) |
| #define | UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk |
| #define | UCPD_SR_TXUND_Pos (6U) |
| #define | UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) |
| #define | UCPD_SR_TXUND UCPD_SR_TXUND_Msk |
| #define | UCPD_SR_RXNE_Pos (8U) |
| #define | UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) |
| #define | UCPD_SR_RXNE UCPD_SR_RXNE_Msk |
| #define | UCPD_SR_RXORDDET_Pos (9U) |
| #define | UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) |
| #define | UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk |
| #define | UCPD_SR_RXHRSTDET_Pos (10U) |
| #define | UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) |
| #define | UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk |
| #define | UCPD_SR_RXOVR_Pos (11U) |
| #define | UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) |
| #define | UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk |
| #define | UCPD_SR_RXMSGEND_Pos (12U) |
| #define | UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) |
| #define | UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk |
| #define | UCPD_SR_RXERR_Pos (13U) |
| #define | UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) |
| #define | UCPD_SR_RXERR UCPD_SR_RXERR_Msk |
| #define | UCPD_SR_TYPECEVT1_Pos (14U) |
| #define | UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) |
| #define | UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk |
| #define | UCPD_SR_TYPECEVT2_Pos (15U) |
| #define | UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) |
| #define | UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk |
| #define | UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U) |
| #define | UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) |
| #define | UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk |
| #define | UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) |
| #define | UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) |
| #define | UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U) |
| #define | UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) |
| #define | UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk |
| #define | UCPD_SR_TYPEC_VSTATE_CC2_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) |
| #define | UCPD_SR_TYPEC_VSTATE_CC2_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) |
| #define | UCPD_SR_FRSEVT_Pos (20U) |
| #define | UCPD_SR_FRSEVT_Msk (0x1UL << UCPD_SR_FRSEVT_Pos) |
| #define | UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk |
| #define | UCPD_ICR_TXMSGDISCCF_Pos (1U) |
| #define | UCPD_ICR_TXMSGDISCCF_Msk (0x1UL << UCPD_ICR_TXMSGDISCCF_Pos) |
| #define | UCPD_ICR_TXMSGDISCCF UCPD_ICR_TXMSGDISCCF_Msk |
| #define | UCPD_ICR_TXMSGSENTCF_Pos (2U) |
| #define | UCPD_ICR_TXMSGSENTCF_Msk (0x1UL << UCPD_ICR_TXMSGSENTCF_Pos) |
| #define | UCPD_ICR_TXMSGSENTCF UCPD_ICR_TXMSGSENTCF_Msk |
| #define | UCPD_ICR_TXMSGABTCF_Pos (3U) |
| #define | UCPD_ICR_TXMSGABTCF_Msk (0x1UL << UCPD_ICR_TXMSGABTCF_Pos) |
| #define | UCPD_ICR_TXMSGABTCF UCPD_ICR_TXMSGABTCF_Msk |
| #define | UCPD_ICR_HRSTDISCCF_Pos (4U) |
| #define | UCPD_ICR_HRSTDISCCF_Msk (0x1UL << UCPD_ICR_HRSTDISCCF_Pos) |
| #define | UCPD_ICR_HRSTDISCCF UCPD_ICR_HRSTDISCCF_Msk |
| #define | UCPD_ICR_HRSTSENTCF_Pos (5U) |
| #define | UCPD_ICR_HRSTSENTCF_Msk (0x1UL << UCPD_ICR_HRSTSENTCF_Pos) |
| #define | UCPD_ICR_HRSTSENTCF UCPD_ICR_HRSTSENTCF_Msk |
| #define | UCPD_ICR_TXUNDCF_Pos (6U) |
| #define | UCPD_ICR_TXUNDCF_Msk (0x1UL << UCPD_ICR_TXUNDCF_Pos) |
| #define | UCPD_ICR_TXUNDCF UCPD_ICR_TXUNDCF_Msk |
| #define | UCPD_ICR_RXORDDETCF_Pos (9U) |
| #define | UCPD_ICR_RXORDDETCF_Msk (0x1UL << UCPD_ICR_RXORDDETCF_Pos) |
| #define | UCPD_ICR_RXORDDETCF UCPD_ICR_RXORDDETCF_Msk |
| #define | UCPD_ICR_RXHRSTDETCF_Pos (10U) |
| #define | UCPD_ICR_RXHRSTDETCF_Msk (0x1UL << UCPD_ICR_RXHRSTDETCF_Pos) |
| #define | UCPD_ICR_RXHRSTDETCF UCPD_ICR_RXHRSTDETCF_Msk |
| #define | UCPD_ICR_RXOVRCF_Pos (11U) |
| #define | UCPD_ICR_RXOVRCF_Msk (0x1UL << UCPD_ICR_RXOVRCF_Pos) |
| #define | UCPD_ICR_RXOVRCF UCPD_ICR_RXOVRCF_Msk |
| #define | UCPD_ICR_RXMSGENDCF_Pos (12U) |
| #define | UCPD_ICR_RXMSGENDCF_Msk (0x1UL << UCPD_ICR_RXMSGENDCF_Pos) |
| #define | UCPD_ICR_RXMSGENDCF UCPD_ICR_RXMSGENDCF_Msk |
| #define | UCPD_ICR_TYPECEVT1CF_Pos (14U) |
| #define | UCPD_ICR_TYPECEVT1CF_Msk (0x1UL << UCPD_ICR_TYPECEVT1CF_Pos) |
| #define | UCPD_ICR_TYPECEVT1CF UCPD_ICR_TYPECEVT1CF_Msk |
| #define | UCPD_ICR_TYPECEVT2CF_Pos (15U) |
| #define | UCPD_ICR_TYPECEVT2CF_Msk (0x1UL << UCPD_ICR_TYPECEVT2CF_Pos) |
| #define | UCPD_ICR_TYPECEVT2CF UCPD_ICR_TYPECEVT2CF_Msk |
| #define | UCPD_ICR_FRSEVTCF_Pos (20U) |
| #define | UCPD_ICR_FRSEVTCF_Msk (0x1UL << UCPD_ICR_FRSEVTCF_Pos) |
| #define | UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk |
| #define | UCPD_TX_ORDSET_TXORDSET_Pos (0U) |
| #define | UCPD_TX_ORDSET_TXORDSET_Msk (0xFFFFFUL << UCPD_TX_ORDSET_TXORDSET_Pos) |
| #define | UCPD_TX_ORDSET_TXORDSET UCPD_TX_ORDSET_TXORDSET_Msk |
| #define | UCPD_TX_PAYSZ_TXPAYSZ_Pos (0U) |
| #define | UCPD_TX_PAYSZ_TXPAYSZ_Msk (0x3FFUL << UCPD_TX_PAYSZ_TXPAYSZ_Pos) |
| #define | UCPD_TX_PAYSZ_TXPAYSZ UCPD_TX_PAYSZ_TXPAYSZ_Msk |
| #define | UCPD_TXDR_TXDATA_Pos (0U) |
| #define | UCPD_TXDR_TXDATA_Msk (0xFFUL << UCPD_TXDR_TXDATA_Pos) |
| #define | UCPD_TXDR_TXDATA UCPD_TXDR_TXDATA_Msk |
| #define | UCPD_RX_ORDSET_RXORDSET_Pos (0U) |
| #define | UCPD_RX_ORDSET_RXORDSET_Msk (0x7UL << UCPD_RX_ORDSET_RXORDSET_Pos) |
| #define | UCPD_RX_ORDSET_RXORDSET UCPD_RX_ORDSET_RXORDSET_Msk |
| #define | UCPD_RX_ORDSET_RXORDSET_0 (0x1UL << UCPD_RX_ORDSET_RXORDSET_Pos) |
| #define | UCPD_RX_ORDSET_RXORDSET_1 (0x2UL << UCPD_RX_ORDSET_RXORDSET_Pos) |
| #define | UCPD_RX_ORDSET_RXORDSET_2 (0x4UL << UCPD_RX_ORDSET_RXORDSET_Pos) |
| #define | UCPD_RX_ORDSET_RXSOP3OF4_Pos (3U) |
| #define | UCPD_RX_ORDSET_RXSOP3OF4_Msk (0x1UL << UCPD_RX_ORDSET_RXSOP3OF4_Pos) |
| #define | UCPD_RX_ORDSET_RXSOP3OF4 UCPD_RX_ORDSET_RXSOP3OF4_Msk |
| #define | UCPD_RX_ORDSET_RXSOPKINVALID_Pos (4U) |
| #define | UCPD_RX_ORDSET_RXSOPKINVALID_Msk (0x7UL << UCPD_RX_ORDSET_RXSOPKINVALID_Pos) |
| #define | UCPD_RX_ORDSET_RXSOPKINVALID UCPD_RX_ORDSET_RXSOPKINVALID_Msk |
| #define | UCPD_RX_PAYSZ_RXPAYSZ_Pos (0U) |
| #define | UCPD_RX_PAYSZ_RXPAYSZ_Msk (0x3FFUL << UCPD_RX_PAYSZ_RXPAYSZ_Pos) |
| #define | UCPD_RX_PAYSZ_RXPAYSZ UCPD_RX_PAYSZ_RXPAYSZ_Msk |
| #define | UCPD_RXDR_RXDATA_Pos (0U) |
| #define | UCPD_RXDR_RXDATA_Msk (0xFFUL << UCPD_RXDR_RXDATA_Pos) |
| #define | UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk |
| #define | UCPD_RX_ORDEXT1_RXSOPX1_Pos (0U) |
| #define | UCPD_RX_ORDEXT1_RXSOPX1_Msk (0xFFFFFUL << UCPD_RX_ORDEXT1_RXSOPX1_Pos) |
| #define | UCPD_RX_ORDEXT1_RXSOPX1 UCPD_RX_ORDEXT1_RXSOPX1_Msk |
| #define | UCPD_RX_ORDEXT2_RXSOPX2_Pos (0U) |
| #define | UCPD_RX_ORDEXT2_RXSOPX2_Msk (0xFFFFFUL << UCPD_RX_ORDEXT2_RXSOPX2_Pos) |
| #define | UCPD_RX_ORDEXT2_RXSOPX2 UCPD_RX_ORDEXT2_RXSOPX2_Msk |
| #define | USB_OTG_GOTGCTL_SRQSCS_Pos (0U) |
| #define | USB_OTG_GOTGCTL_SRQSCS_Msk (0x1U << USB_OTG_GOTGCTL_SRQSCS_Pos) |
| #define | USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk |
| #define | USB_OTG_GOTGCTL_SRQ_Pos (1U) |
| #define | USB_OTG_GOTGCTL_SRQ_Msk (0x1U << USB_OTG_GOTGCTL_SRQ_Pos) |
| #define | USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk |
| #define | USB_OTG_GOTGCTL_VBVALOEN_Pos (2U) |
| #define | USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOEN_Pos) |
| #define | USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk |
| #define | USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U) |
| #define | USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_VBVALOVAL_Pos) |
| #define | USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk |
| #define | USB_OTG_GOTGCTL_AVALOEN_Pos (4U) |
| #define | USB_OTG_GOTGCTL_AVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_AVALOEN_Pos) |
| #define | USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk |
| #define | USB_OTG_GOTGCTL_AVALOVAL_Pos (5U) |
| #define | USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_AVALOVAL_Pos) |
| #define | USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk |
| #define | USB_OTG_GOTGCTL_BVALOEN_Pos (6U) |
| #define | USB_OTG_GOTGCTL_BVALOEN_Msk (0x1U << USB_OTG_GOTGCTL_BVALOEN_Pos) |
| #define | USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk |
| #define | USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) |
| #define | USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1U << USB_OTG_GOTGCTL_BVALOVAL_Pos) |
| #define | USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk |
| #define | USB_OTG_GOTGCTL_BSESVLD_Pos (19U) |
| #define | USB_OTG_GOTGCTL_BSESVLD_Msk (0x1U << USB_OTG_GOTGCTL_BSESVLD_Pos) |
| #define | USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk |
| #define | USB_OTG_HCFG_FSLSPCS_Pos (0U) |
| #define | USB_OTG_HCFG_FSLSPCS_Msk (0x3U << USB_OTG_HCFG_FSLSPCS_Pos) |
| #define | USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk |
| #define | USB_OTG_HCFG_FSLSPCS_0 (0x1U << USB_OTG_HCFG_FSLSPCS_Pos) |
| #define | USB_OTG_HCFG_FSLSPCS_1 (0x2U << USB_OTG_HCFG_FSLSPCS_Pos) |
| #define | USB_OTG_HCFG_FSLSS_Pos (2U) |
| #define | USB_OTG_HCFG_FSLSS_Msk (0x1U << USB_OTG_HCFG_FSLSS_Pos) |
| #define | USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk |
| #define | USB_OTG_DCFG_DSPD_Pos (0U) |
| #define | USB_OTG_DCFG_DSPD_Msk (0x3U << USB_OTG_DCFG_DSPD_Pos) |
| #define | USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk |
| #define | USB_OTG_DCFG_DSPD_0 (0x1U << USB_OTG_DCFG_DSPD_Pos) |
| #define | USB_OTG_DCFG_DSPD_1 (0x2U << USB_OTG_DCFG_DSPD_Pos) |
| #define | USB_OTG_DCFG_NZLSOHSK_Pos (2U) |
| #define | USB_OTG_DCFG_NZLSOHSK_Msk (0x1U << USB_OTG_DCFG_NZLSOHSK_Pos) |
| #define | USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk |
| #define | USB_OTG_DCFG_DAD_Pos (4U) |
| #define | USB_OTG_DCFG_DAD_Msk (0x7FU << USB_OTG_DCFG_DAD_Pos) |
| #define | USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk |
| #define | USB_OTG_DCFG_DAD_0 (0x01U << USB_OTG_DCFG_DAD_Pos) |
| #define | USB_OTG_DCFG_DAD_1 (0x02U << USB_OTG_DCFG_DAD_Pos) |
| #define | USB_OTG_DCFG_DAD_2 (0x04U << USB_OTG_DCFG_DAD_Pos) |
| #define | USB_OTG_DCFG_DAD_3 (0x08U << USB_OTG_DCFG_DAD_Pos) |
| #define | USB_OTG_DCFG_DAD_4 (0x10U << USB_OTG_DCFG_DAD_Pos) |
| #define | USB_OTG_DCFG_DAD_5 (0x20U << USB_OTG_DCFG_DAD_Pos) |
| #define | USB_OTG_DCFG_DAD_6 (0x40U << USB_OTG_DCFG_DAD_Pos) |
| #define | USB_OTG_DCFG_PFIVL_Pos (11U) |
| #define | USB_OTG_DCFG_PFIVL_Msk (0x3U << USB_OTG_DCFG_PFIVL_Pos) |
| #define | USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk |
| #define | USB_OTG_DCFG_PFIVL_0 (0x1U << USB_OTG_DCFG_PFIVL_Pos) |
| #define | USB_OTG_DCFG_PFIVL_1 (0x2U << USB_OTG_DCFG_PFIVL_Pos) |
| #define | USB_OTG_DCFG_PERSCHIVL_Pos (24U) |
| #define | USB_OTG_DCFG_PERSCHIVL_Msk (0x3U << USB_OTG_DCFG_PERSCHIVL_Pos) |
| #define | USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk |
| #define | USB_OTG_DCFG_PERSCHIVL_0 (0x1U << USB_OTG_DCFG_PERSCHIVL_Pos) |
| #define | USB_OTG_DCFG_PERSCHIVL_1 (0x2U << USB_OTG_DCFG_PERSCHIVL_Pos) |
| #define | USB_OTG_PCGCR_STPPCLK_Pos (0U) |
| #define | USB_OTG_PCGCR_STPPCLK_Msk (0x1U << USB_OTG_PCGCR_STPPCLK_Pos) |
| #define | USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk |
| #define | USB_OTG_PCGCR_GATEHCLK_Pos (1U) |
| #define | USB_OTG_PCGCR_GATEHCLK_Msk (0x1U << USB_OTG_PCGCR_GATEHCLK_Pos) |
| #define | USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk |
| #define | USB_OTG_PCGCR_PHYSUSP_Pos (4U) |
| #define | USB_OTG_PCGCR_PHYSUSP_Msk (0x1U << USB_OTG_PCGCR_PHYSUSP_Pos) |
| #define | USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk |
| #define | USB_OTG_GOTGINT_SEDET_Pos (2U) |
| #define | USB_OTG_GOTGINT_SEDET_Msk (0x1U << USB_OTG_GOTGINT_SEDET_Pos) |
| #define | USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk |
| #define | USB_OTG_GOTGINT_SRSSCHG_Pos (8U) |
| #define | USB_OTG_GOTGINT_SRSSCHG_Msk (0x1U << USB_OTG_GOTGINT_SRSSCHG_Pos) |
| #define | USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk |
| #define | USB_OTG_GOTGINT_HNSSCHG_Pos (9U) |
| #define | USB_OTG_GOTGINT_HNSSCHG_Msk (0x1U << USB_OTG_GOTGINT_HNSSCHG_Pos) |
| #define | USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk |
| #define | USB_OTG_GOTGINT_HNGDET_Pos (17U) |
| #define | USB_OTG_GOTGINT_HNGDET_Msk (0x1U << USB_OTG_GOTGINT_HNGDET_Pos) |
| #define | USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk |
| #define | USB_OTG_GOTGINT_ADTOCHG_Pos (18U) |
| #define | USB_OTG_GOTGINT_ADTOCHG_Msk (0x1U << USB_OTG_GOTGINT_ADTOCHG_Pos) |
| #define | USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk |
| #define | USB_OTG_GOTGINT_DBCDNE_Pos (19U) |
| #define | USB_OTG_GOTGINT_DBCDNE_Msk (0x1U << USB_OTG_GOTGINT_DBCDNE_Pos) |
| #define | USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk |
| #define | USB_OTG_DCTL_RWUSIG_Pos (0U) |
| #define | USB_OTG_DCTL_RWUSIG_Msk (0x1U << USB_OTG_DCTL_RWUSIG_Pos) |
| #define | USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk |
| #define | USB_OTG_DCTL_SDIS_Pos (1U) |
| #define | USB_OTG_DCTL_SDIS_Msk (0x1U << USB_OTG_DCTL_SDIS_Pos) |
| #define | USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk |
| #define | USB_OTG_DCTL_GINSTS_Pos (2U) |
| #define | USB_OTG_DCTL_GINSTS_Msk (0x1U << USB_OTG_DCTL_GINSTS_Pos) |
| #define | USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk |
| #define | USB_OTG_DCTL_GONSTS_Pos (3U) |
| #define | USB_OTG_DCTL_GONSTS_Msk (0x1U << USB_OTG_DCTL_GONSTS_Pos) |
| #define | USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk |
| #define | USB_OTG_DCTL_TCTL_Pos (4U) |
| #define | USB_OTG_DCTL_TCTL_Msk (0x7U << USB_OTG_DCTL_TCTL_Pos) |
| #define | USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk |
| #define | USB_OTG_DCTL_TCTL_0 (0x1U << USB_OTG_DCTL_TCTL_Pos) |
| #define | USB_OTG_DCTL_TCTL_1 (0x2U << USB_OTG_DCTL_TCTL_Pos) |
| #define | USB_OTG_DCTL_TCTL_2 (0x4U << USB_OTG_DCTL_TCTL_Pos) |
| #define | USB_OTG_DCTL_SGINAK_Pos (7U) |
| #define | USB_OTG_DCTL_SGINAK_Msk (0x1U << USB_OTG_DCTL_SGINAK_Pos) |
| #define | USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk |
| #define | USB_OTG_DCTL_CGINAK_Pos (8U) |
| #define | USB_OTG_DCTL_CGINAK_Msk (0x1U << USB_OTG_DCTL_CGINAK_Pos) |
| #define | USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk |
| #define | USB_OTG_DCTL_SGONAK_Pos (9U) |
| #define | USB_OTG_DCTL_SGONAK_Msk (0x1U << USB_OTG_DCTL_SGONAK_Pos) |
| #define | USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk |
| #define | USB_OTG_DCTL_CGONAK_Pos (10U) |
| #define | USB_OTG_DCTL_CGONAK_Msk (0x1U << USB_OTG_DCTL_CGONAK_Pos) |
| #define | USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk |
| #define | USB_OTG_DCTL_POPRGDNE_Pos (11U) |
| #define | USB_OTG_DCTL_POPRGDNE_Msk (0x1U << USB_OTG_DCTL_POPRGDNE_Pos) |
| #define | USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk |
| #define | USB_OTG_HFIR_FRIVL_Pos (0U) |
| #define | USB_OTG_HFIR_FRIVL_Msk (0xFFFFU << USB_OTG_HFIR_FRIVL_Pos) |
| #define | USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk |
| #define | USB_OTG_HFNUM_FRNUM_Pos (0U) |
| #define | USB_OTG_HFNUM_FRNUM_Msk (0xFFFFU << USB_OTG_HFNUM_FRNUM_Pos) |
| #define | USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk |
| #define | USB_OTG_HFNUM_FTREM_Pos (16U) |
| #define | USB_OTG_HFNUM_FTREM_Msk (0xFFFFU << USB_OTG_HFNUM_FTREM_Pos) |
| #define | USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk |
| #define | USB_OTG_DSTS_SUSPSTS_Pos (0U) |
| #define | USB_OTG_DSTS_SUSPSTS_Msk (0x1U << USB_OTG_DSTS_SUSPSTS_Pos) |
| #define | USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk |
| #define | USB_OTG_DSTS_ENUMSPD_Pos (1U) |
| #define | USB_OTG_DSTS_ENUMSPD_Msk (0x3U << USB_OTG_DSTS_ENUMSPD_Pos) |
| #define | USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk |
| #define | USB_OTG_DSTS_ENUMSPD_0 (0x1U << USB_OTG_DSTS_ENUMSPD_Pos) |
| #define | USB_OTG_DSTS_ENUMSPD_1 (0x2U << USB_OTG_DSTS_ENUMSPD_Pos) |
| #define | USB_OTG_DSTS_EERR_Pos (3U) |
| #define | USB_OTG_DSTS_EERR_Msk (0x1U << USB_OTG_DSTS_EERR_Pos) |
| #define | USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk |
| #define | USB_OTG_DSTS_FNSOF_Pos (8U) |
| #define | USB_OTG_DSTS_FNSOF_Msk (0x3FFFU << USB_OTG_DSTS_FNSOF_Pos) |
| #define | USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk |
| #define | USB_OTG_GAHBCFG_GINT_Pos (0U) |
| #define | USB_OTG_GAHBCFG_GINT_Msk (0x1U << USB_OTG_GAHBCFG_GINT_Pos) |
| #define | USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk |
| #define | USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) |
| #define | USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFU << USB_OTG_GAHBCFG_HBSTLEN_Pos) |
| #define | USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk |
| #define | USB_OTG_GAHBCFG_HBSTLEN_0 (0x1U << USB_OTG_GAHBCFG_HBSTLEN_Pos) |
| #define | USB_OTG_GAHBCFG_HBSTLEN_1 (0x2U << USB_OTG_GAHBCFG_HBSTLEN_Pos) |
| #define | USB_OTG_GAHBCFG_HBSTLEN_2 (0x4U << USB_OTG_GAHBCFG_HBSTLEN_Pos) |
| #define | USB_OTG_GAHBCFG_HBSTLEN_3 (0x8U << USB_OTG_GAHBCFG_HBSTLEN_Pos) |
| #define | USB_OTG_GAHBCFG_DMAEN_Pos (5U) |
| #define | USB_OTG_GAHBCFG_DMAEN_Msk (0x1U << USB_OTG_GAHBCFG_DMAEN_Pos) |
| #define | USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk |
| #define | USB_OTG_GAHBCFG_TXFELVL_Pos (7U) |
| #define | USB_OTG_GAHBCFG_TXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_TXFELVL_Pos) |
| #define | USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk |
| #define | USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) |
| #define | USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1U << USB_OTG_GAHBCFG_PTXFELVL_Pos) |
| #define | USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk |
| #define | USB_OTG_GUSBCFG_TOCAL_Pos (0U) |
| #define | USB_OTG_GUSBCFG_TOCAL_Msk (0x7U << USB_OTG_GUSBCFG_TOCAL_Pos) |
| #define | USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk |
| #define | USB_OTG_GUSBCFG_TOCAL_0 (0x1U << USB_OTG_GUSBCFG_TOCAL_Pos) |
| #define | USB_OTG_GUSBCFG_TOCAL_1 (0x2U << USB_OTG_GUSBCFG_TOCAL_Pos) |
| #define | USB_OTG_GUSBCFG_TOCAL_2 (0x4U << USB_OTG_GUSBCFG_TOCAL_Pos) |
| #define | USB_OTG_GUSBCFG_PHYSEL_Pos (6U) |
| #define | USB_OTG_GUSBCFG_PHYSEL_Msk (0x1U << USB_OTG_GUSBCFG_PHYSEL_Pos) |
| #define | USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk |
| #define | USB_OTG_GUSBCFG_SRPCAP_Pos (8U) |
| #define | USB_OTG_GUSBCFG_SRPCAP_Msk (0x1U << USB_OTG_GUSBCFG_SRPCAP_Pos) |
| #define | USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk |
| #define | USB_OTG_GUSBCFG_HNPCAP_Pos (9U) |
| #define | USB_OTG_GUSBCFG_HNPCAP_Msk (0x1U << USB_OTG_GUSBCFG_HNPCAP_Pos) |
| #define | USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk |
| #define | USB_OTG_GUSBCFG_TRDT_Pos (10U) |
| #define | USB_OTG_GUSBCFG_TRDT_Msk (0xFU << USB_OTG_GUSBCFG_TRDT_Pos) |
| #define | USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk |
| #define | USB_OTG_GUSBCFG_TRDT_0 (0x1U << USB_OTG_GUSBCFG_TRDT_Pos) |
| #define | USB_OTG_GUSBCFG_TRDT_1 (0x2U << USB_OTG_GUSBCFG_TRDT_Pos) |
| #define | USB_OTG_GUSBCFG_TRDT_2 (0x4U << USB_OTG_GUSBCFG_TRDT_Pos) |
| #define | USB_OTG_GUSBCFG_TRDT_3 (0x8U << USB_OTG_GUSBCFG_TRDT_Pos) |
| #define | USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) |
| #define | USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1U << USB_OTG_GUSBCFG_PHYLPCS_Pos) |
| #define | USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk |
| #define | USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) |
| #define | USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1U << USB_OTG_GUSBCFG_ULPIFSLS_Pos) |
| #define | USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk |
| #define | USB_OTG_GUSBCFG_ULPIAR_Pos (18U) |
| #define | USB_OTG_GUSBCFG_ULPIAR_Msk (0x1U << USB_OTG_GUSBCFG_ULPIAR_Pos) |
| #define | USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk |
| #define | USB_OTG_GUSBCFG_ULPICSM_Pos (19U) |
| #define | USB_OTG_GUSBCFG_ULPICSM_Msk (0x1U << USB_OTG_GUSBCFG_ULPICSM_Pos) |
| #define | USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk |
| #define | USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) |
| #define | USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) |
| #define | USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk |
| #define | USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) |
| #define | USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1U << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) |
| #define | USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk |
| #define | USB_OTG_GUSBCFG_TSDPS_Pos (22U) |
| #define | USB_OTG_GUSBCFG_TSDPS_Msk (0x1U << USB_OTG_GUSBCFG_TSDPS_Pos) |
| #define | USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk |
| #define | USB_OTG_GUSBCFG_PCCI_Pos (23U) |
| #define | USB_OTG_GUSBCFG_PCCI_Msk (0x1U << USB_OTG_GUSBCFG_PCCI_Pos) |
| #define | USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk |
| #define | USB_OTG_GUSBCFG_PTCI_Pos (24U) |
| #define | USB_OTG_GUSBCFG_PTCI_Msk (0x1U << USB_OTG_GUSBCFG_PTCI_Pos) |
| #define | USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk |
| #define | USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) |
| #define | USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1U << USB_OTG_GUSBCFG_ULPIIPD_Pos) |
| #define | USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk |
| #define | USB_OTG_GUSBCFG_FHMOD_Pos (29U) |
| #define | USB_OTG_GUSBCFG_FHMOD_Msk (0x1U << USB_OTG_GUSBCFG_FHMOD_Pos) |
| #define | USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk |
| #define | USB_OTG_GUSBCFG_FDMOD_Pos (30U) |
| #define | USB_OTG_GUSBCFG_FDMOD_Msk (0x1U << USB_OTG_GUSBCFG_FDMOD_Pos) |
| #define | USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk |
| #define | USB_OTG_GUSBCFG_CTXPKT_Pos (31U) |
| #define | USB_OTG_GUSBCFG_CTXPKT_Msk (0x1U << USB_OTG_GUSBCFG_CTXPKT_Pos) |
| #define | USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk |
| #define | USB_OTG_GRSTCTL_CSRST_Pos (0U) |
| #define | USB_OTG_GRSTCTL_CSRST_Msk (0x1U << USB_OTG_GRSTCTL_CSRST_Pos) |
| #define | USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk |
| #define | USB_OTG_GRSTCTL_HSRST_Pos (1U) |
| #define | USB_OTG_GRSTCTL_HSRST_Msk (0x1U << USB_OTG_GRSTCTL_HSRST_Pos) |
| #define | USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk |
| #define | USB_OTG_GRSTCTL_FCRST_Pos (2U) |
| #define | USB_OTG_GRSTCTL_FCRST_Msk (0x1U << USB_OTG_GRSTCTL_FCRST_Pos) |
| #define | USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk |
| #define | USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) |
| #define | USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_RXFFLSH_Pos) |
| #define | USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk |
| #define | USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) |
| #define | USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1U << USB_OTG_GRSTCTL_TXFFLSH_Pos) |
| #define | USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk |
| #define | USB_OTG_GRSTCTL_TXFNUM_Pos (6U) |
| #define | USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FU << USB_OTG_GRSTCTL_TXFNUM_Pos) |
| #define | USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk |
| #define | USB_OTG_GRSTCTL_TXFNUM_0 (0x01U << USB_OTG_GRSTCTL_TXFNUM_Pos) |
| #define | USB_OTG_GRSTCTL_TXFNUM_1 (0x02U << USB_OTG_GRSTCTL_TXFNUM_Pos) |
| #define | USB_OTG_GRSTCTL_TXFNUM_2 (0x04U << USB_OTG_GRSTCTL_TXFNUM_Pos) |
| #define | USB_OTG_GRSTCTL_TXFNUM_3 (0x08U << USB_OTG_GRSTCTL_TXFNUM_Pos) |
| #define | USB_OTG_GRSTCTL_TXFNUM_4 (0x10U << USB_OTG_GRSTCTL_TXFNUM_Pos) |
| #define | USB_OTG_GRSTCTL_DMAREQ_Pos (30U) |
| #define | USB_OTG_GRSTCTL_DMAREQ_Msk (0x1U << USB_OTG_GRSTCTL_DMAREQ_Pos) |
| #define | USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk |
| #define | USB_OTG_GRSTCTL_AHBIDL_Pos (31U) |
| #define | USB_OTG_GRSTCTL_AHBIDL_Msk (0x1U << USB_OTG_GRSTCTL_AHBIDL_Pos) |
| #define | USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk |
| #define | USB_OTG_DIEPMSK_XFRCM_Pos (0U) |
| #define | USB_OTG_DIEPMSK_XFRCM_Msk (0x1U << USB_OTG_DIEPMSK_XFRCM_Pos) |
| #define | USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk |
| #define | USB_OTG_DIEPMSK_EPDM_Pos (1U) |
| #define | USB_OTG_DIEPMSK_EPDM_Msk (0x1U << USB_OTG_DIEPMSK_EPDM_Pos) |
| #define | USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk |
| #define | USB_OTG_DIEPMSK_TOM_Pos (3U) |
| #define | USB_OTG_DIEPMSK_TOM_Msk (0x1U << USB_OTG_DIEPMSK_TOM_Pos) |
| #define | USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk |
| #define | USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) |
| #define | USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) |
| #define | USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk |
| #define | USB_OTG_DIEPMSK_INEPNMM_Pos (5U) |
| #define | USB_OTG_DIEPMSK_INEPNMM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNMM_Pos) |
| #define | USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk |
| #define | USB_OTG_DIEPMSK_INEPNEM_Pos (6U) |
| #define | USB_OTG_DIEPMSK_INEPNEM_Msk (0x1U << USB_OTG_DIEPMSK_INEPNEM_Pos) |
| #define | USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk |
| #define | USB_OTG_DIEPMSK_TXFURM_Pos (8U) |
| #define | USB_OTG_DIEPMSK_TXFURM_Msk (0x1U << USB_OTG_DIEPMSK_TXFURM_Pos) |
| #define | USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk |
| #define | USB_OTG_DIEPMSK_BIM_Pos (9U) |
| #define | USB_OTG_DIEPMSK_BIM_Msk (0x1U << USB_OTG_DIEPMSK_BIM_Pos) |
| #define | USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk |
| #define | USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) |
| #define | USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFU << USB_OTG_HPTXSTS_PTXFSAVL_Pos) |
| #define | USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk |
| #define | USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk |
| #define | USB_OTG_HPTXSTS_PTXQSAV_0 (0x01U << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_1 (0x02U << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_2 (0x04U << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_3 (0x08U << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_4 (0x10U << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_5 (0x20U << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_6 (0x40U << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQSAV_7 (0x80U << USB_OTG_HPTXSTS_PTXQSAV_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFU << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk |
| #define | USB_OTG_HPTXSTS_PTXQTOP_0 (0x01U << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_1 (0x02U << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_2 (0x04U << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_3 (0x08U << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_4 (0x10U << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_5 (0x20U << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_6 (0x40U << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
| #define | USB_OTG_HPTXSTS_PTXQTOP_7 (0x80U << USB_OTG_HPTXSTS_PTXQTOP_Pos) |
| #define | USB_OTG_HAINT_HAINT_Pos (0U) |
| #define | USB_OTG_HAINT_HAINT_Msk (0xFFFFU << USB_OTG_HAINT_HAINT_Pos) |
| #define | USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk |
| #define | USB_OTG_DOEPMSK_XFRCM_Pos (0U) |
| #define | USB_OTG_DOEPMSK_XFRCM_Msk (0x1U << USB_OTG_DOEPMSK_XFRCM_Pos) |
| #define | USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk |
| #define | USB_OTG_DOEPMSK_EPDM_Pos (1U) |
| #define | USB_OTG_DOEPMSK_EPDM_Msk (0x1U << USB_OTG_DOEPMSK_EPDM_Pos) |
| #define | USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk |
| #define | USB_OTG_DOEPMSK_STUPM_Pos (3U) |
| #define | USB_OTG_DOEPMSK_STUPM_Msk (0x1U << USB_OTG_DOEPMSK_STUPM_Pos) |
| #define | USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk |
| #define | USB_OTG_DOEPMSK_OTEPDM_Pos (4U) |
| #define | USB_OTG_DOEPMSK_OTEPDM_Msk (0x1U << USB_OTG_DOEPMSK_OTEPDM_Pos) |
| #define | USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk |
| #define | USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) |
| #define | USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1U << USB_OTG_DOEPMSK_B2BSTUP_Pos) |
| #define | USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk |
| #define | USB_OTG_DOEPMSK_OPEM_Pos (8U) |
| #define | USB_OTG_DOEPMSK_OPEM_Msk (0x1U << USB_OTG_DOEPMSK_OPEM_Pos) |
| #define | USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk |
| #define | USB_OTG_DOEPMSK_BOIM_Pos (9U) |
| #define | USB_OTG_DOEPMSK_BOIM_Msk (0x1U << USB_OTG_DOEPMSK_BOIM_Pos) |
| #define | USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk |
| #define | USB_OTG_GINTSTS_CMOD_Pos (0U) |
| #define | USB_OTG_GINTSTS_CMOD_Msk (0x1U << USB_OTG_GINTSTS_CMOD_Pos) |
| #define | USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk |
| #define | USB_OTG_GINTSTS_MMIS_Pos (1U) |
| #define | USB_OTG_GINTSTS_MMIS_Msk (0x1U << USB_OTG_GINTSTS_MMIS_Pos) |
| #define | USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk |
| #define | USB_OTG_GINTSTS_OTGINT_Pos (2U) |
| #define | USB_OTG_GINTSTS_OTGINT_Msk (0x1U << USB_OTG_GINTSTS_OTGINT_Pos) |
| #define | USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk |
| #define | USB_OTG_GINTSTS_SOF_Pos (3U) |
| #define | USB_OTG_GINTSTS_SOF_Msk (0x1U << USB_OTG_GINTSTS_SOF_Pos) |
| #define | USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk |
| #define | USB_OTG_GINTSTS_RXFLVL_Pos (4U) |
| #define | USB_OTG_GINTSTS_RXFLVL_Msk (0x1U << USB_OTG_GINTSTS_RXFLVL_Pos) |
| #define | USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk |
| #define | USB_OTG_GINTSTS_NPTXFE_Pos (5U) |
| #define | USB_OTG_GINTSTS_NPTXFE_Msk (0x1U << USB_OTG_GINTSTS_NPTXFE_Pos) |
| #define | USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk |
| #define | USB_OTG_GINTSTS_GINAKEFF_Pos (6U) |
| #define | USB_OTG_GINTSTS_GINAKEFF_Msk (0x1U << USB_OTG_GINTSTS_GINAKEFF_Pos) |
| #define | USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk |
| #define | USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) |
| #define | USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1U << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) |
| #define | USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk |
| #define | USB_OTG_GINTSTS_ESUSP_Pos (10U) |
| #define | USB_OTG_GINTSTS_ESUSP_Msk (0x1U << USB_OTG_GINTSTS_ESUSP_Pos) |
| #define | USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk |
| #define | USB_OTG_GINTSTS_USBSUSP_Pos (11U) |
| #define | USB_OTG_GINTSTS_USBSUSP_Msk (0x1U << USB_OTG_GINTSTS_USBSUSP_Pos) |
| #define | USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk |
| #define | USB_OTG_GINTSTS_USBRST_Pos (12U) |
| #define | USB_OTG_GINTSTS_USBRST_Msk (0x1U << USB_OTG_GINTSTS_USBRST_Pos) |
| #define | USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk |
| #define | USB_OTG_GINTSTS_ENUMDNE_Pos (13U) |
| #define | USB_OTG_GINTSTS_ENUMDNE_Msk (0x1U << USB_OTG_GINTSTS_ENUMDNE_Pos) |
| #define | USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk |
| #define | USB_OTG_GINTSTS_ISOODRP_Pos (14U) |
| #define | USB_OTG_GINTSTS_ISOODRP_Msk (0x1U << USB_OTG_GINTSTS_ISOODRP_Pos) |
| #define | USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk |
| #define | USB_OTG_GINTSTS_EOPF_Pos (15U) |
| #define | USB_OTG_GINTSTS_EOPF_Msk (0x1U << USB_OTG_GINTSTS_EOPF_Pos) |
| #define | USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk |
| #define | USB_OTG_GINTSTS_IEPINT_Pos (18U) |
| #define | USB_OTG_GINTSTS_IEPINT_Msk (0x1U << USB_OTG_GINTSTS_IEPINT_Pos) |
| #define | USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk |
| #define | USB_OTG_GINTSTS_OEPINT_Pos (19U) |
| #define | USB_OTG_GINTSTS_OEPINT_Msk (0x1U << USB_OTG_GINTSTS_OEPINT_Pos) |
| #define | USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk |
| #define | USB_OTG_GINTSTS_IISOIXFR_Pos (20U) |
| #define | USB_OTG_GINTSTS_IISOIXFR_Msk (0x1U << USB_OTG_GINTSTS_IISOIXFR_Pos) |
| #define | USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk |
| #define | USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) |
| #define | USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1U << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) |
| #define | USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk |
| #define | USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) |
| #define | USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1U << USB_OTG_GINTSTS_DATAFSUSP_Pos) |
| #define | USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk |
| #define | USB_OTG_GINTSTS_HPRTINT_Pos (24U) |
| #define | USB_OTG_GINTSTS_HPRTINT_Msk (0x1U << USB_OTG_GINTSTS_HPRTINT_Pos) |
| #define | USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk |
| #define | USB_OTG_GINTSTS_HCINT_Pos (25U) |
| #define | USB_OTG_GINTSTS_HCINT_Msk (0x1U << USB_OTG_GINTSTS_HCINT_Pos) |
| #define | USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk |
| #define | USB_OTG_GINTSTS_PTXFE_Pos (26U) |
| #define | USB_OTG_GINTSTS_PTXFE_Msk (0x1U << USB_OTG_GINTSTS_PTXFE_Pos) |
| #define | USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk |
| #define | USB_OTG_GINTSTS_LPMINT_Pos (27U) |
| #define | USB_OTG_GINTSTS_LPMINT_Msk (0x1U << USB_OTG_GINTSTS_LPMINT_Pos) |
| #define | USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk |
| #define | USB_OTG_GINTSTS_CIDSCHG_Pos (28U) |
| #define | USB_OTG_GINTSTS_CIDSCHG_Msk (0x1U << USB_OTG_GINTSTS_CIDSCHG_Pos) |
| #define | USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk |
| #define | USB_OTG_GINTSTS_DISCINT_Pos (29U) |
| #define | USB_OTG_GINTSTS_DISCINT_Msk (0x1U << USB_OTG_GINTSTS_DISCINT_Pos) |
| #define | USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk |
| #define | USB_OTG_GINTSTS_SRQINT_Pos (30U) |
| #define | USB_OTG_GINTSTS_SRQINT_Msk (0x1U << USB_OTG_GINTSTS_SRQINT_Pos) |
| #define | USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk |
| #define | USB_OTG_GINTSTS_WKUINT_Pos (31U) |
| #define | USB_OTG_GINTSTS_WKUINT_Msk (0x1U << USB_OTG_GINTSTS_WKUINT_Pos) |
| #define | USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk |
| #define | USB_OTG_GINTMSK_MMISM_Pos (1U) |
| #define | USB_OTG_GINTMSK_MMISM_Msk (0x1U << USB_OTG_GINTMSK_MMISM_Pos) |
| #define | USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk |
| #define | USB_OTG_GINTMSK_OTGINT_Pos (2U) |
| #define | USB_OTG_GINTMSK_OTGINT_Msk (0x1U << USB_OTG_GINTMSK_OTGINT_Pos) |
| #define | USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk |
| #define | USB_OTG_GINTMSK_SOFM_Pos (3U) |
| #define | USB_OTG_GINTMSK_SOFM_Msk (0x1U << USB_OTG_GINTMSK_SOFM_Pos) |
| #define | USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk |
| #define | USB_OTG_GINTMSK_RXFLVLM_Pos (4U) |
| #define | USB_OTG_GINTMSK_RXFLVLM_Msk (0x1U << USB_OTG_GINTMSK_RXFLVLM_Pos) |
| #define | USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk |
| #define | USB_OTG_GINTMSK_NPTXFEM_Pos (5U) |
| #define | USB_OTG_GINTMSK_NPTXFEM_Msk (0x1U << USB_OTG_GINTMSK_NPTXFEM_Pos) |
| #define | USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk |
| #define | USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) |
| #define | USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GINAKEFFM_Pos) |
| #define | USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk |
| #define | USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) |
| #define | USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1U << USB_OTG_GINTMSK_GONAKEFFM_Pos) |
| #define | USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk |
| #define | USB_OTG_GINTMSK_ESUSPM_Pos (10U) |
| #define | USB_OTG_GINTMSK_ESUSPM_Msk (0x1U << USB_OTG_GINTMSK_ESUSPM_Pos) |
| #define | USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk |
| #define | USB_OTG_GINTMSK_USBSUSPM_Pos (11U) |
| #define | USB_OTG_GINTMSK_USBSUSPM_Msk (0x1U << USB_OTG_GINTMSK_USBSUSPM_Pos) |
| #define | USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk |
| #define | USB_OTG_GINTMSK_USBRST_Pos (12U) |
| #define | USB_OTG_GINTMSK_USBRST_Msk (0x1U << USB_OTG_GINTMSK_USBRST_Pos) |
| #define | USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk |
| #define | USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) |
| #define | USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1U << USB_OTG_GINTMSK_ENUMDNEM_Pos) |
| #define | USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk |
| #define | USB_OTG_GINTMSK_ISOODRPM_Pos (14U) |
| #define | USB_OTG_GINTMSK_ISOODRPM_Msk (0x1U << USB_OTG_GINTMSK_ISOODRPM_Pos) |
| #define | USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk |
| #define | USB_OTG_GINTMSK_EOPFM_Pos (15U) |
| #define | USB_OTG_GINTMSK_EOPFM_Msk (0x1U << USB_OTG_GINTMSK_EOPFM_Pos) |
| #define | USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk |
| #define | USB_OTG_GINTMSK_EPMISM_Pos (17U) |
| #define | USB_OTG_GINTMSK_EPMISM_Msk (0x1U << USB_OTG_GINTMSK_EPMISM_Pos) |
| #define | USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk |
| #define | USB_OTG_GINTMSK_IEPINT_Pos (18U) |
| #define | USB_OTG_GINTMSK_IEPINT_Msk (0x1U << USB_OTG_GINTMSK_IEPINT_Pos) |
| #define | USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk |
| #define | USB_OTG_GINTMSK_OEPINT_Pos (19U) |
| #define | USB_OTG_GINTMSK_OEPINT_Msk (0x1U << USB_OTG_GINTMSK_OEPINT_Pos) |
| #define | USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk |
| #define | USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) |
| #define | USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1U << USB_OTG_GINTMSK_IISOIXFRM_Pos) |
| #define | USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk |
| #define | USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) |
| #define | USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1U << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) |
| #define | USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk |
| #define | USB_OTG_GINTMSK_FSUSPM_Pos (22U) |
| #define | USB_OTG_GINTMSK_FSUSPM_Msk (0x1U << USB_OTG_GINTMSK_FSUSPM_Pos) |
| #define | USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk |
| #define | USB_OTG_GINTMSK_PRTIM_Pos (24U) |
| #define | USB_OTG_GINTMSK_PRTIM_Msk (0x1U << USB_OTG_GINTMSK_PRTIM_Pos) |
| #define | USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk |
| #define | USB_OTG_GINTMSK_HCIM_Pos (25U) |
| #define | USB_OTG_GINTMSK_HCIM_Msk (0x1U << USB_OTG_GINTMSK_HCIM_Pos) |
| #define | USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk |
| #define | USB_OTG_GINTMSK_PTXFEM_Pos (26U) |
| #define | USB_OTG_GINTMSK_PTXFEM_Msk (0x1U << USB_OTG_GINTMSK_PTXFEM_Pos) |
| #define | USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk |
| #define | USB_OTG_GINTMSK_LPMINTM_Pos (27U) |
| #define | USB_OTG_GINTMSK_LPMINTM_Msk (0x1U << USB_OTG_GINTMSK_LPMINTM_Pos) |
| #define | USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk |
| #define | USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) |
| #define | USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1U << USB_OTG_GINTMSK_CIDSCHGM_Pos) |
| #define | USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk |
| #define | USB_OTG_GINTMSK_DISCINT_Pos (29U) |
| #define | USB_OTG_GINTMSK_DISCINT_Msk (0x1U << USB_OTG_GINTMSK_DISCINT_Pos) |
| #define | USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk |
| #define | USB_OTG_GINTMSK_SRQIM_Pos (30U) |
| #define | USB_OTG_GINTMSK_SRQIM_Msk (0x1U << USB_OTG_GINTMSK_SRQIM_Pos) |
| #define | USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk |
| #define | USB_OTG_GINTMSK_WUIM_Pos (31U) |
| #define | USB_OTG_GINTMSK_WUIM_Msk (0x1U << USB_OTG_GINTMSK_WUIM_Pos) |
| #define | USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk |
| #define | USB_OTG_DAINT_IEPINT_Pos (0U) |
| #define | USB_OTG_DAINT_IEPINT_Msk (0xFFFFU << USB_OTG_DAINT_IEPINT_Pos) |
| #define | USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk |
| #define | USB_OTG_DAINT_OEPINT_Pos (16U) |
| #define | USB_OTG_DAINT_OEPINT_Msk (0xFFFFU << USB_OTG_DAINT_OEPINT_Pos) |
| #define | USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk |
| #define | USB_OTG_HAINTMSK_HAINTM_Pos (0U) |
| #define | USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFU << USB_OTG_HAINTMSK_HAINTM_Pos) |
| #define | USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk |
| #define | USB_OTG_GRXSTSP_EPNUM_Pos (0U) |
| #define | USB_OTG_GRXSTSP_EPNUM_Msk (0xFU << USB_OTG_GRXSTSP_EPNUM_Pos) |
| #define | USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk |
| #define | USB_OTG_GRXSTSP_BCNT_Pos (4U) |
| #define | USB_OTG_GRXSTSP_BCNT_Msk (0x7FFU << USB_OTG_GRXSTSP_BCNT_Pos) |
| #define | USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk |
| #define | USB_OTG_GRXSTSP_DPID_Pos (15U) |
| #define | USB_OTG_GRXSTSP_DPID_Msk (0x3U << USB_OTG_GRXSTSP_DPID_Pos) |
| #define | USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk |
| #define | USB_OTG_GRXSTSP_PKTSTS_Pos (17U) |
| #define | USB_OTG_GRXSTSP_PKTSTS_Msk (0xFU << USB_OTG_GRXSTSP_PKTSTS_Pos) |
| #define | USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk |
| #define | USB_OTG_DAINTMSK_IEPM_Pos (0U) |
| #define | USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_IEPM_Pos) |
| #define | USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk |
| #define | USB_OTG_DAINTMSK_OEPM_Pos (16U) |
| #define | USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) |
| #define | USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk |
| #define | USB_OTG_CHNUM_Pos (0U) |
| #define | USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) |
| #define | USB_OTG_CHNUM USB_OTG_CHNUM_Msk |
| #define | USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) |
| #define | USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) |
| #define | USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) |
| #define | USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) |
| #define | USB_OTG_BCNT_Pos (4U) |
| #define | USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) |
| #define | USB_OTG_BCNT USB_OTG_BCNT_Msk |
| #define | USB_OTG_DPID_Pos (15U) |
| #define | USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) |
| #define | USB_OTG_DPID USB_OTG_DPID_Msk |
| #define | USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) |
| #define | USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) |
| #define | USB_OTG_PKTSTS_Pos (17U) |
| #define | USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) |
| #define | USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk |
| #define | USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) |
| #define | USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) |
| #define | USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) |
| #define | USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) |
| #define | USB_OTG_EPNUM_Pos (0U) |
| #define | USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) |
| #define | USB_OTG_EPNUM USB_OTG_EPNUM_Msk |
| #define | USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) |
| #define | USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) |
| #define | USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) |
| #define | USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) |
| #define | USB_OTG_FRMNUM_Pos (21U) |
| #define | USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) |
| #define | USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk |
| #define | USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) |
| #define | USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) |
| #define | USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) |
| #define | USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) |
| #define | USB_OTG_GRXFSIZ_RXFD_Pos (0U) |
| #define | USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) |
| #define | USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk |
| #define | USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) |
| #define | USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFU << USB_OTG_DVBUSDIS_VBUSDT_Pos) |
| #define | USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk |
| #define | USB_OTG_NPTXFSA_Pos (0U) |
| #define | USB_OTG_NPTXFSA_Msk (0xFFFFU << USB_OTG_NPTXFSA_Pos) |
| #define | USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk |
| #define | USB_OTG_NPTXFD_Pos (16U) |
| #define | USB_OTG_NPTXFD_Msk (0xFFFFU << USB_OTG_NPTXFD_Pos) |
| #define | USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk |
| #define | USB_OTG_TX0FSA_Pos (0U) |
| #define | USB_OTG_TX0FSA_Msk (0xFFFFU << USB_OTG_TX0FSA_Pos) |
| #define | USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk |
| #define | USB_OTG_TX0FD_Pos (16U) |
| #define | USB_OTG_TX0FD_Msk (0xFFFFU << USB_OTG_TX0FD_Pos) |
| #define | USB_OTG_TX0FD USB_OTG_TX0FD_Msk |
| #define | USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) |
| #define | USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFU << USB_OTG_DVBUSPULSE_DVBUSP_Pos) |
| #define | USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk |
| #define | USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) |
| #define | USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFU << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFU << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80U << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FU << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
| #define | USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40U << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) |
| #define | USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) |
| #define | USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_NONISOTHREN_Pos) |
| #define | USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk |
| #define | USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) |
| #define | USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1U << USB_OTG_DTHRCTL_ISOTHREN_Pos) |
| #define | USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_TXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_RXTHREN_Pos (16U) |
| #define | USB_OTG_DTHRCTL_RXTHREN_Msk (0x1U << USB_OTG_DTHRCTL_RXTHREN_Pos) |
| #define | USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFU << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100U << USB_OTG_DTHRCTL_RXTHRLEN_Pos) |
| #define | USB_OTG_DTHRCTL_ARPEN_Pos (27U) |
| #define | USB_OTG_DTHRCTL_ARPEN_Msk (0x1U << USB_OTG_DTHRCTL_ARPEN_Pos) |
| #define | USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk |
| #define | USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) |
| #define | USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFU << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) |
| #define | USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk |
| #define | USB_OTG_DEACHINT_IEP1INT_Pos (1U) |
| #define | USB_OTG_DEACHINT_IEP1INT_Msk (0x1U << USB_OTG_DEACHINT_IEP1INT_Pos) |
| #define | USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk |
| #define | USB_OTG_DEACHINT_OEP1INT_Pos (17U) |
| #define | USB_OTG_DEACHINT_OEP1INT_Msk (0x1U << USB_OTG_DEACHINT_OEP1INT_Pos) |
| #define | USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk |
| #define | USB_OTG_GCCFG_CHGDET_Pos (0U) |
| #define | USB_OTG_GCCFG_CHGDET_Msk (0x1U << USB_OTG_GCCFG_CHGDET_Pos) |
| #define | USB_OTG_GCCFG_CHGDET USB_OTG_GCCFG_CHGDET_Msk |
| #define | USB_OTG_GCCFG_FSVPLUS_Pos (1U) |
| #define | USB_OTG_GCCFG_FSVPLUS_Msk (0x1U << USB_OTG_GCCFG_FSVPLUS_Pos) |
| #define | USB_OTG_GCCFG_FSVPLUS USB_OTG_GCCFG_FSVPLUS_Msk |
| #define | USB_OTG_GCCFG_FSVMINUS_Pos (2U) |
| #define | USB_OTG_GCCFG_FSVMINUS_Msk 0x1U << USB_OTG_GCCFG_FSVMINUS_Pos) |
| #define | USB_OTG_GCCFG_FSVMINUS USB_OTG_GCCFG_FSVMINUS_Msk |
| #define | USB_OTG_GCCFG_SESSVLD_Pos (3U) |
| #define | USB_OTG_GCCFG_SESSVLD_Msk (0x1U << USB_OTG_GCCFG_SESSVLD_Pos) |
| #define | USB_OTG_GCCFG_SESSVLD USB_OTG_GCCFG_SESSVLD_Msk |
| #define | USB_OTG_GCCFG_H_CDPEN_Pos (16U) |
| #define | USB_OTG_GCCFG_H_CDPEN_Msk (0x1U << USB_OTG_GCCFG_H_CDPEN_Pos) |
| #define | USB_OTG_GCCFG_H_CDPEN USB_OTG_GCCFG_H_CDPEN_Msk |
| #define | USB_OTG_GCCFG_H_CDPDETEN_Pos (17U) |
| #define | USB_OTG_GCCFG_H_CDPDETEN_Msk (0x1U << USB_OTG_GCCFG_H_CDPDETEN_Pos) |
| #define | USB_OTG_GCCFG_H_CDPDETEN USB_OTG_GCCFG_H_CDPDETEN_Msk |
| #define | USB_OTG_GCCFG_H_VDMSRCEN_Pos (18U) |
| #define | USB_OTG_GCCFG_H_VDMSRCEN_Msk (0x1U << USB_OTG_GCCFG_H_VDMSRCEN_Pos) |
| #define | USB_OTG_GCCFG_H_VDMSRCEN USB_OTG_GCCFG_H_VDMSRCEN_Msk |
| #define | USB_OTG_GCCFG_DCDEN_Pos (19U) |
| #define | USB_OTG_GCCFG_DCDEN_Msk (0x1U << USB_OTG_GCCFG_DCDEN_Pos) |
| #define | USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk |
| #define | USB_OTG_GCCFG_PDEN_Pos (20U) |
| #define | USB_OTG_GCCFG_PDEN_Msk (0x1U << USB_OTG_GCCFG_PDEN_Pos) |
| #define | USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk |
| #define | USB_OTG_GCCFG_VBDEN_Pos (21U) |
| #define | USB_OTG_GCCFG_VBDEN_Msk (0x1U << USB_OTG_GCCFG_VBDEN_Pos) |
| #define | USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk |
| #define | USB_OTG_GCCFG_SDEN_Pos (22U) |
| #define | USB_OTG_GCCFG_SDEN_Msk (0x1U << USB_OTG_GCCFG_SDEN_Pos) |
| #define | USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk |
| #define | USB_OTG_GCCFG_VBVALOVAL_Pos (23U) |
| #define | USB_OTG_GCCFG_VBVALOVAL_Msk (0x1U << USB_OTG_GCCFG_VBVALOVAL_Pos) |
| #define | USB_OTG_GCCFG_VBVALOVAL USB_OTG_GCCFG_VBVALOVAL_Msk |
| #define | USB_OTG_GCCFG_VBVALEXTOEN_Pos (24U) |
| #define | USB_OTG_GCCFG_VBVALEXTOEN_Msk (0x1U << USB_OTG_GCCFG_VBVALEXTOEN_Pos) |
| #define | USB_OTG_GCCFG_VBVALEXTOEN USB_OTG_GCCFG_VBVALEXTOEN_Msk |
| #define | USB_OTG_GCCFG_PULLDOWNEN_Pos (25U) |
| #define | USB_OTG_GCCFG_PULLDOWNEN_Msk (0x1U << USB_OTG_GCCFG_PULLDOWNEN_Pos) |
| #define | USB_OTG_GCCFG_PULLDOWNEN USB_OTG_GCCFG_PULLDOWNEN_Msk |
| #define | USB_OTG_GPWRDN_DISABLEVBUS_Pos (6U) |
| #define | USB_OTG_GPWRDN_DISABLEVBUS_Msk (0x1U << USB_OTG_GPWRDN_DISABLEVBUS_Pos) |
| #define | USB_OTG_GPWRDN_DISABLEVBUS USB_OTG_GPWRDN_DISABLEVBUS_Msk |
| #define | USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) |
| #define | USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) |
| #define | USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk |
| #define | USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) |
| #define | USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1U << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) |
| #define | USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk |
| #define | USB_OTG_CID_PRODUCT_ID_Pos (0U) |
| #define | USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFU << USB_OTG_CID_PRODUCT_ID_Pos) |
| #define | USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk |
| #define | USB_OTG_GHWCFG3_LPMMode_Pos (14U) |
| #define | USB_OTG_GHWCFG3_LPMMode_Msk (0x1U << USB_OTG_GHWCFG3_LPMMode_Pos) |
| #define | USB_OTG_GHWCFG3_LPMMode USB_OTG_GHWCFG3_LPMMode_Msk /* LPM mode specified for Mode of Operation */ |
| #define | USB_OTG_GLPMCFG_ENBESL_Pos (28U) |
| #define | USB_OTG_GLPMCFG_ENBESL_Msk (0x1U << USB_OTG_GLPMCFG_ENBESL_Pos) |
| #define | USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /* Enable best effort service latency */ |
| #define | USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) |
| #define | USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) |
| #define | USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /* LPM retry count status */ |
| #define | USB_OTG_GLPMCFG_SNDLPM_Pos (24U) |
| #define | USB_OTG_GLPMCFG_SNDLPM_Msk (0x1U << USB_OTG_GLPMCFG_SNDLPM_Pos) |
| #define | USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /* Send LPM transaction */ |
| #define | USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) |
| #define | USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7U << USB_OTG_GLPMCFG_LPMRCNT_Pos) |
| #define | USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /* LPM retry count */ |
| #define | USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) |
| #define | USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFU << USB_OTG_GLPMCFG_LPMCHIDX_Pos) |
| #define | USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /* LPMCHIDX: */ |
| #define | USB_OTG_GLPMCFG_L1ResumeOK_Pos (16U) |
| #define | USB_OTG_GLPMCFG_L1ResumeOK_Msk (0x1U << USB_OTG_GLPMCFG_L1ResumeOK_Pos) |
| #define | USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1ResumeOK_Msk /* Sleep State Resume OK */ |
| #define | USB_OTG_GLPMCFG_SLPSTS_Pos (15U) |
| #define | USB_OTG_GLPMCFG_SLPSTS_Msk (0x1U << USB_OTG_GLPMCFG_SLPSTS_Pos) |
| #define | USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /* Port sleep status */ |
| #define | USB_OTG_GLPMCFG_LPMRSP_Pos (13U) |
| #define | USB_OTG_GLPMCFG_LPMRSP_Msk (0x3U << USB_OTG_GLPMCFG_LPMRSP_Pos) |
| #define | USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /* LPM response */ |
| #define | USB_OTG_GLPMCFG_L1DSEN_Pos (12U) |
| #define | USB_OTG_GLPMCFG_L1DSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1DSEN_Pos) |
| #define | USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /* L1 deep sleep enable */ |
| #define | USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) |
| #define | USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFU << USB_OTG_GLPMCFG_BESLTHRS_Pos) |
| #define | USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /* BESL threshold */ |
| #define | USB_OTG_GLPMCFG_L1SSEN_Pos (7U) |
| #define | USB_OTG_GLPMCFG_L1SSEN_Msk (0x1U << USB_OTG_GLPMCFG_L1SSEN_Pos) |
| #define | USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /* L1 shallow sleep enable */ |
| #define | USB_OTG_GLPMCFG_REMWAKE_Pos (6U) |
| #define | USB_OTG_GLPMCFG_REMWAKE_Msk (0x1U << USB_OTG_GLPMCFG_REMWAKE_Pos) |
| #define | USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /* bRemoteWake value received with last ACKed LPM Token */ |
| #define | USB_OTG_GLPMCFG_BESL_Pos (2U) |
| #define | USB_OTG_GLPMCFG_BESL_Msk (0xFU << USB_OTG_GLPMCFG_BESL_Pos) |
| #define | USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /* BESL value received with last ACKed LPM Token */ |
| #define | USB_OTG_GLPMCFG_LPMACK_Pos (1U) |
| #define | USB_OTG_GLPMCFG_LPMACK_Msk (0x1U << USB_OTG_GLPMCFG_LPMACK_Pos) |
| #define | USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /* LPM Token acknowledge enable*/ |
| #define | USB_OTG_GLPMCFG_LPMEN_Pos (0U) |
| #define | USB_OTG_GLPMCFG_LPMEN_Msk (0x1U << USB_OTG_GLPMCFG_LPMEN_Pos) |
| #define | USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /* LPM support enable */ |
| #define | USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) |
| #define | USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) |
| #define | USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk |
| #define | USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) |
| #define | USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_EPDM_Pos) |
| #define | USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk |
| #define | USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) |
| #define | USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TOM_Pos) |
| #define | USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk |
| #define | USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) |
| #define | USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) |
| #define | USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk |
| #define | USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) |
| #define | USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) |
| #define | USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk |
| #define | USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) |
| #define | USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) |
| #define | USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk |
| #define | USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) |
| #define | USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) |
| #define | USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk |
| #define | USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) |
| #define | USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_BIM_Pos) |
| #define | USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk |
| #define | USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) |
| #define | USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DIEPEACHMSK1_NAKM_Pos) |
| #define | USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk |
| #define | USB_OTG_HPRT_PCSTS_Pos (0U) |
| #define | USB_OTG_HPRT_PCSTS_Msk (0x1U << USB_OTG_HPRT_PCSTS_Pos) |
| #define | USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk |
| #define | USB_OTG_HPRT_PCDET_Pos (1U) |
| #define | USB_OTG_HPRT_PCDET_Msk (0x1U << USB_OTG_HPRT_PCDET_Pos) |
| #define | USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk |
| #define | USB_OTG_HPRT_PENA_Pos (2U) |
| #define | USB_OTG_HPRT_PENA_Msk (0x1U << USB_OTG_HPRT_PENA_Pos) |
| #define | USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk |
| #define | USB_OTG_HPRT_PENCHNG_Pos (3U) |
| #define | USB_OTG_HPRT_PENCHNG_Msk (0x1U << USB_OTG_HPRT_PENCHNG_Pos) |
| #define | USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk |
| #define | USB_OTG_HPRT_POCA_Pos (4U) |
| #define | USB_OTG_HPRT_POCA_Msk (0x1U << USB_OTG_HPRT_POCA_Pos) |
| #define | USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk |
| #define | USB_OTG_HPRT_POCCHNG_Pos (5U) |
| #define | USB_OTG_HPRT_POCCHNG_Msk (0x1U << USB_OTG_HPRT_POCCHNG_Pos) |
| #define | USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk |
| #define | USB_OTG_HPRT_PRES_Pos (6U) |
| #define | USB_OTG_HPRT_PRES_Msk (0x1U << USB_OTG_HPRT_PRES_Pos) |
| #define | USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk |
| #define | USB_OTG_HPRT_PSUSP_Pos (7U) |
| #define | USB_OTG_HPRT_PSUSP_Msk (0x1U << USB_OTG_HPRT_PSUSP_Pos) |
| #define | USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk |
| #define | USB_OTG_HPRT_PRST_Pos (8U) |
| #define | USB_OTG_HPRT_PRST_Msk (0x1U << USB_OTG_HPRT_PRST_Pos) |
| #define | USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk |
| #define | USB_OTG_HPRT_PLSTS_Pos (10U) |
| #define | USB_OTG_HPRT_PLSTS_Msk (0x3U << USB_OTG_HPRT_PLSTS_Pos) |
| #define | USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk |
| #define | USB_OTG_HPRT_PLSTS_0 (0x1U << USB_OTG_HPRT_PLSTS_Pos) |
| #define | USB_OTG_HPRT_PLSTS_1 (0x2U << USB_OTG_HPRT_PLSTS_Pos) |
| #define | USB_OTG_HPRT_PPWR_Pos (12U) |
| #define | USB_OTG_HPRT_PPWR_Msk (0x1U << USB_OTG_HPRT_PPWR_Pos) |
| #define | USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk |
| #define | USB_OTG_HPRT_PTCTL_Pos (13U) |
| #define | USB_OTG_HPRT_PTCTL_Msk (0xFU << USB_OTG_HPRT_PTCTL_Pos) |
| #define | USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk |
| #define | USB_OTG_HPRT_PTCTL_0 (0x1U << USB_OTG_HPRT_PTCTL_Pos) |
| #define | USB_OTG_HPRT_PTCTL_1 (0x2U << USB_OTG_HPRT_PTCTL_Pos) |
| #define | USB_OTG_HPRT_PTCTL_2 (0x4U << USB_OTG_HPRT_PTCTL_Pos) |
| #define | USB_OTG_HPRT_PTCTL_3 (0x8U << USB_OTG_HPRT_PTCTL_Pos) |
| #define | USB_OTG_HPRT_PSPD_Pos (17U) |
| #define | USB_OTG_HPRT_PSPD_Msk (0x3U << USB_OTG_HPRT_PSPD_Pos) |
| #define | USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk |
| #define | USB_OTG_HPRT_PSPD_0 (0x1U << USB_OTG_HPRT_PSPD_Pos) |
| #define | USB_OTG_HPRT_PSPD_1 (0x2U << USB_OTG_HPRT_PSPD_Pos) |
| #define | USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) |
| #define | USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) |
| #define | USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk |
| #define | USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) |
| #define | USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_EPDM_Pos) |
| #define | USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk |
| #define | USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) |
| #define | USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TOM_Pos) |
| #define | USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk |
| #define | USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) |
| #define | USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1U << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) |
| #define | USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk |
| #define | USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) |
| #define | USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) |
| #define | USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk |
| #define | USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) |
| #define | USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) |
| #define | USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk |
| #define | USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) |
| #define | USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) |
| #define | USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk |
| #define | USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) |
| #define | USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BIM_Pos) |
| #define | USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk |
| #define | USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) |
| #define | USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_BERRM_Pos) |
| #define | USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk |
| #define | USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) |
| #define | USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NAKM_Pos) |
| #define | USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk |
| #define | USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) |
| #define | USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1U << USB_OTG_DOEPEACHMSK1_NYETM_Pos) |
| #define | USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk |
| #define | USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) |
| #define | USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXSA_Pos) |
| #define | USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk |
| #define | USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) |
| #define | USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFU << USB_OTG_HPTXFSIZ_PTXFD_Pos) |
| #define | USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk |
| #define | USB_OTG_DIEPCTL_MPSIZ_Pos (0U) |
| #define | USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DIEPCTL_MPSIZ_Pos) |
| #define | USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk |
| #define | USB_OTG_DIEPCTL_USBAEP_Pos (15U) |
| #define | USB_OTG_DIEPCTL_USBAEP_Msk (0x1U << USB_OTG_DIEPCTL_USBAEP_Pos) |
| #define | USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk |
| #define | USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) |
| #define | USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1U << USB_OTG_DIEPCTL_EONUM_DPID_Pos) |
| #define | USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk |
| #define | USB_OTG_DIEPCTL_NAKSTS_Pos (17U) |
| #define | USB_OTG_DIEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DIEPCTL_NAKSTS_Pos) |
| #define | USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk |
| #define | USB_OTG_DIEPCTL_EPTYP_Pos (18U) |
| #define | USB_OTG_DIEPCTL_EPTYP_Msk (0x3U << USB_OTG_DIEPCTL_EPTYP_Pos) |
| #define | USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk |
| #define | USB_OTG_DIEPCTL_EPTYP_0 (0x1U << USB_OTG_DIEPCTL_EPTYP_Pos) |
| #define | USB_OTG_DIEPCTL_EPTYP_1 (0x2U << USB_OTG_DIEPCTL_EPTYP_Pos) |
| #define | USB_OTG_DIEPCTL_STALL_Pos (21U) |
| #define | USB_OTG_DIEPCTL_STALL_Msk (0x1U << USB_OTG_DIEPCTL_STALL_Pos) |
| #define | USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk |
| #define | USB_OTG_DIEPCTL_TXFNUM_Pos (22U) |
| #define | USB_OTG_DIEPCTL_TXFNUM_Msk (0xFU << USB_OTG_DIEPCTL_TXFNUM_Pos) |
| #define | USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk |
| #define | USB_OTG_DIEPCTL_TXFNUM_0 (0x1U << USB_OTG_DIEPCTL_TXFNUM_Pos) |
| #define | USB_OTG_DIEPCTL_TXFNUM_1 (0x2U << USB_OTG_DIEPCTL_TXFNUM_Pos) |
| #define | USB_OTG_DIEPCTL_TXFNUM_2 (0x4U << USB_OTG_DIEPCTL_TXFNUM_Pos) |
| #define | USB_OTG_DIEPCTL_TXFNUM_3 (0x8U << USB_OTG_DIEPCTL_TXFNUM_Pos) |
| #define | USB_OTG_DIEPCTL_CNAK_Pos (26U) |
| #define | USB_OTG_DIEPCTL_CNAK_Msk (0x1U << USB_OTG_DIEPCTL_CNAK_Pos) |
| #define | USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk |
| #define | USB_OTG_DIEPCTL_SNAK_Pos (27U) |
| #define | USB_OTG_DIEPCTL_SNAK_Msk (0x1U << USB_OTG_DIEPCTL_SNAK_Pos) |
| #define | USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk |
| #define | USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) |
| #define | USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) |
| #define | USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk |
| #define | USB_OTG_DIEPCTL_SODDFRM_Pos (29U) |
| #define | USB_OTG_DIEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DIEPCTL_SODDFRM_Pos) |
| #define | USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk |
| #define | USB_OTG_DIEPCTL_EPDIS_Pos (30U) |
| #define | USB_OTG_DIEPCTL_EPDIS_Msk (0x1U << USB_OTG_DIEPCTL_EPDIS_Pos) |
| #define | USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk |
| #define | USB_OTG_DIEPCTL_EPENA_Pos (31U) |
| #define | USB_OTG_DIEPCTL_EPENA_Msk (0x1U << USB_OTG_DIEPCTL_EPENA_Pos) |
| #define | USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk |
| #define | USB_OTG_HCCHAR_MPSIZ_Pos (0U) |
| #define | USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFU << USB_OTG_HCCHAR_MPSIZ_Pos) |
| #define | USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk |
| #define | USB_OTG_HCCHAR_EPNUM_Pos (11U) |
| #define | USB_OTG_HCCHAR_EPNUM_Msk (0xFU << USB_OTG_HCCHAR_EPNUM_Pos) |
| #define | USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk |
| #define | USB_OTG_HCCHAR_EPNUM_0 (0x1U << USB_OTG_HCCHAR_EPNUM_Pos) |
| #define | USB_OTG_HCCHAR_EPNUM_1 (0x2U << USB_OTG_HCCHAR_EPNUM_Pos) |
| #define | USB_OTG_HCCHAR_EPNUM_2 (0x4U << USB_OTG_HCCHAR_EPNUM_Pos) |
| #define | USB_OTG_HCCHAR_EPNUM_3 (0x8U << USB_OTG_HCCHAR_EPNUM_Pos) |
| #define | USB_OTG_HCCHAR_EPDIR_Pos (15U) |
| #define | USB_OTG_HCCHAR_EPDIR_Msk (0x1U << USB_OTG_HCCHAR_EPDIR_Pos) |
| #define | USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk |
| #define | USB_OTG_HCCHAR_LSDEV_Pos (17U) |
| #define | USB_OTG_HCCHAR_LSDEV_Msk (0x1U << USB_OTG_HCCHAR_LSDEV_Pos) |
| #define | USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk |
| #define | USB_OTG_HCCHAR_EPTYP_Pos (18U) |
| #define | USB_OTG_HCCHAR_EPTYP_Msk (0x3U << USB_OTG_HCCHAR_EPTYP_Pos) |
| #define | USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk |
| #define | USB_OTG_HCCHAR_EPTYP_0 (0x1U << USB_OTG_HCCHAR_EPTYP_Pos) |
| #define | USB_OTG_HCCHAR_EPTYP_1 (0x2U << USB_OTG_HCCHAR_EPTYP_Pos) |
| #define | USB_OTG_HCCHAR_MC_Pos (20U) |
| #define | USB_OTG_HCCHAR_MC_Msk (0x3U << USB_OTG_HCCHAR_MC_Pos) |
| #define | USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk |
| #define | USB_OTG_HCCHAR_MC_0 (0x1U << USB_OTG_HCCHAR_MC_Pos) |
| #define | USB_OTG_HCCHAR_MC_1 (0x2U << USB_OTG_HCCHAR_MC_Pos) |
| #define | USB_OTG_HCCHAR_DAD_Pos (22U) |
| #define | USB_OTG_HCCHAR_DAD_Msk (0x7FU << USB_OTG_HCCHAR_DAD_Pos) |
| #define | USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk |
| #define | USB_OTG_HCCHAR_DAD_0 (0x01U << USB_OTG_HCCHAR_DAD_Pos) |
| #define | USB_OTG_HCCHAR_DAD_1 (0x02U << USB_OTG_HCCHAR_DAD_Pos) |
| #define | USB_OTG_HCCHAR_DAD_2 (0x04U << USB_OTG_HCCHAR_DAD_Pos) |
| #define | USB_OTG_HCCHAR_DAD_3 (0x08U << USB_OTG_HCCHAR_DAD_Pos) |
| #define | USB_OTG_HCCHAR_DAD_4 (0x10U << USB_OTG_HCCHAR_DAD_Pos) |
| #define | USB_OTG_HCCHAR_DAD_5 (0x20U << USB_OTG_HCCHAR_DAD_Pos) |
| #define | USB_OTG_HCCHAR_DAD_6 (0x40U << USB_OTG_HCCHAR_DAD_Pos) |
| #define | USB_OTG_HCCHAR_ODDFRM_Pos (29U) |
| #define | USB_OTG_HCCHAR_ODDFRM_Msk (0x1U << USB_OTG_HCCHAR_ODDFRM_Pos) |
| #define | USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk |
| #define | USB_OTG_HCCHAR_CHDIS_Pos (30U) |
| #define | USB_OTG_HCCHAR_CHDIS_Msk (0x1U << USB_OTG_HCCHAR_CHDIS_Pos) |
| #define | USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk |
| #define | USB_OTG_HCCHAR_CHENA_Pos (31U) |
| #define | USB_OTG_HCCHAR_CHENA_Msk (0x1U << USB_OTG_HCCHAR_CHENA_Pos) |
| #define | USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk |
| #define | USB_OTG_HCSPLT_PRTADDR_Pos (0U) |
| #define | USB_OTG_HCSPLT_PRTADDR_Msk (0x7FU << USB_OTG_HCSPLT_PRTADDR_Pos) |
| #define | USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk |
| #define | USB_OTG_HCSPLT_PRTADDR_0 (0x01U << USB_OTG_HCSPLT_PRTADDR_Pos) |
| #define | USB_OTG_HCSPLT_PRTADDR_1 (0x02U << USB_OTG_HCSPLT_PRTADDR_Pos) |
| #define | USB_OTG_HCSPLT_PRTADDR_2 (0x04U << USB_OTG_HCSPLT_PRTADDR_Pos) |
| #define | USB_OTG_HCSPLT_PRTADDR_3 (0x08U << USB_OTG_HCSPLT_PRTADDR_Pos) |
| #define | USB_OTG_HCSPLT_PRTADDR_4 (0x10U << USB_OTG_HCSPLT_PRTADDR_Pos) |
| #define | USB_OTG_HCSPLT_PRTADDR_5 (0x20U << USB_OTG_HCSPLT_PRTADDR_Pos) |
| #define | USB_OTG_HCSPLT_PRTADDR_6 (0x40U << USB_OTG_HCSPLT_PRTADDR_Pos) |
| #define | USB_OTG_HCSPLT_HUBADDR_Pos (7U) |
| #define | USB_OTG_HCSPLT_HUBADDR_Msk (0x7FU << USB_OTG_HCSPLT_HUBADDR_Pos) |
| #define | USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk |
| #define | USB_OTG_HCSPLT_HUBADDR_0 (0x01U << USB_OTG_HCSPLT_HUBADDR_Pos) |
| #define | USB_OTG_HCSPLT_HUBADDR_1 (0x02U << USB_OTG_HCSPLT_HUBADDR_Pos) |
| #define | USB_OTG_HCSPLT_HUBADDR_2 (0x04U << USB_OTG_HCSPLT_HUBADDR_Pos) |
| #define | USB_OTG_HCSPLT_HUBADDR_3 (0x08U << USB_OTG_HCSPLT_HUBADDR_Pos) |
| #define | USB_OTG_HCSPLT_HUBADDR_4 (0x10U << USB_OTG_HCSPLT_HUBADDR_Pos) |
| #define | USB_OTG_HCSPLT_HUBADDR_5 (0x20U << USB_OTG_HCSPLT_HUBADDR_Pos) |
| #define | USB_OTG_HCSPLT_HUBADDR_6 (0x40U << USB_OTG_HCSPLT_HUBADDR_Pos) |
| #define | USB_OTG_HCSPLT_XACTPOS_Pos (14U) |
| #define | USB_OTG_HCSPLT_XACTPOS_Msk (0x3U << USB_OTG_HCSPLT_XACTPOS_Pos) |
| #define | USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk |
| #define | USB_OTG_HCSPLT_XACTPOS_0 (0x1U << USB_OTG_HCSPLT_XACTPOS_Pos) |
| #define | USB_OTG_HCSPLT_XACTPOS_1 (0x2U << USB_OTG_HCSPLT_XACTPOS_Pos) |
| #define | USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) |
| #define | USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1U << USB_OTG_HCSPLT_COMPLSPLT_Pos) |
| #define | USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk |
| #define | USB_OTG_HCSPLT_SPLITEN_Pos (31U) |
| #define | USB_OTG_HCSPLT_SPLITEN_Msk (0x1U << USB_OTG_HCSPLT_SPLITEN_Pos) |
| #define | USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk |
| #define | USB_OTG_HCINT_XFRC_Pos (0U) |
| #define | USB_OTG_HCINT_XFRC_Msk (0x1U << USB_OTG_HCINT_XFRC_Pos) |
| #define | USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk |
| #define | USB_OTG_HCINT_CHH_Pos (1U) |
| #define | USB_OTG_HCINT_CHH_Msk (0x1U << USB_OTG_HCINT_CHH_Pos) |
| #define | USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk |
| #define | USB_OTG_HCINT_AHBERR_Pos (2U) |
| #define | USB_OTG_HCINT_AHBERR_Msk (0x1U << USB_OTG_HCINT_AHBERR_Pos) |
| #define | USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk |
| #define | USB_OTG_HCINT_STALL_Pos (3U) |
| #define | USB_OTG_HCINT_STALL_Msk (0x1U << USB_OTG_HCINT_STALL_Pos) |
| #define | USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk |
| #define | USB_OTG_HCINT_NAK_Pos (4U) |
| #define | USB_OTG_HCINT_NAK_Msk (0x1U << USB_OTG_HCINT_NAK_Pos) |
| #define | USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk |
| #define | USB_OTG_HCINT_ACK_Pos (5U) |
| #define | USB_OTG_HCINT_ACK_Msk (0x1U << USB_OTG_HCINT_ACK_Pos) |
| #define | USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk |
| #define | USB_OTG_HCINT_NYET_Pos (6U) |
| #define | USB_OTG_HCINT_NYET_Msk (0x1U << USB_OTG_HCINT_NYET_Pos) |
| #define | USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk |
| #define | USB_OTG_HCINT_TXERR_Pos (7U) |
| #define | USB_OTG_HCINT_TXERR_Msk (0x1U << USB_OTG_HCINT_TXERR_Pos) |
| #define | USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk |
| #define | USB_OTG_HCINT_BBERR_Pos (8U) |
| #define | USB_OTG_HCINT_BBERR_Msk (0x1U << USB_OTG_HCINT_BBERR_Pos) |
| #define | USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk |
| #define | USB_OTG_HCINT_FRMOR_Pos (9U) |
| #define | USB_OTG_HCINT_FRMOR_Msk (0x1U << USB_OTG_HCINT_FRMOR_Pos) |
| #define | USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk |
| #define | USB_OTG_HCINT_DTERR_Pos (10U) |
| #define | USB_OTG_HCINT_DTERR_Msk (0x1U << USB_OTG_HCINT_DTERR_Pos) |
| #define | USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk |
| #define | USB_OTG_DIEPINT_XFRC_Pos (0U) |
| #define | USB_OTG_DIEPINT_XFRC_Msk (0x1U << USB_OTG_DIEPINT_XFRC_Pos) |
| #define | USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk |
| #define | USB_OTG_DIEPINT_EPDISD_Pos (1U) |
| #define | USB_OTG_DIEPINT_EPDISD_Msk (0x1U << USB_OTG_DIEPINT_EPDISD_Pos) |
| #define | USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk |
| #define | USB_OTG_DIEPINT_TOC_Pos (3U) |
| #define | USB_OTG_DIEPINT_TOC_Msk (0x1U << USB_OTG_DIEPINT_TOC_Pos) |
| #define | USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk |
| #define | USB_OTG_DIEPINT_ITTXFE_Pos (4U) |
| #define | USB_OTG_DIEPINT_ITTXFE_Msk (0x1U << USB_OTG_DIEPINT_ITTXFE_Pos) |
| #define | USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk |
| #define | USB_OTG_DIEPINT_INEPNE_Pos (6U) |
| #define | USB_OTG_DIEPINT_INEPNE_Msk (0x1U << USB_OTG_DIEPINT_INEPNE_Pos) |
| #define | USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk |
| #define | USB_OTG_DIEPINT_TXFE_Pos (7U) |
| #define | USB_OTG_DIEPINT_TXFE_Msk (0x1U << USB_OTG_DIEPINT_TXFE_Pos) |
| #define | USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk |
| #define | USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) |
| #define | USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1U << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) |
| #define | USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk |
| #define | USB_OTG_DIEPINT_BNA_Pos (9U) |
| #define | USB_OTG_DIEPINT_BNA_Msk (0x1U << USB_OTG_DIEPINT_BNA_Pos) |
| #define | USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk |
| #define | USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) |
| #define | USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1U << USB_OTG_DIEPINT_PKTDRPSTS_Pos) |
| #define | USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk |
| #define | USB_OTG_DIEPINT_BERR_Pos (12U) |
| #define | USB_OTG_DIEPINT_BERR_Msk (0x1U << USB_OTG_DIEPINT_BERR_Pos) |
| #define | USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk |
| #define | USB_OTG_DIEPINT_NAK_Pos (13U) |
| #define | USB_OTG_DIEPINT_NAK_Msk (0x1U << USB_OTG_DIEPINT_NAK_Pos) |
| #define | USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk |
| #define | USB_OTG_HCINTMSK_XFRCM_Pos (0U) |
| #define | USB_OTG_HCINTMSK_XFRCM_Msk (0x1U << USB_OTG_HCINTMSK_XFRCM_Pos) |
| #define | USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk |
| #define | USB_OTG_HCINTMSK_CHHM_Pos (1U) |
| #define | USB_OTG_HCINTMSK_CHHM_Msk (0x1U << USB_OTG_HCINTMSK_CHHM_Pos) |
| #define | USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk |
| #define | USB_OTG_HCINTMSK_AHBERR_Pos (2U) |
| #define | USB_OTG_HCINTMSK_AHBERR_Msk (0x1U << USB_OTG_HCINTMSK_AHBERR_Pos) |
| #define | USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk |
| #define | USB_OTG_HCINTMSK_STALLM_Pos (3U) |
| #define | USB_OTG_HCINTMSK_STALLM_Msk (0x1U << USB_OTG_HCINTMSK_STALLM_Pos) |
| #define | USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk |
| #define | USB_OTG_HCINTMSK_NAKM_Pos (4U) |
| #define | USB_OTG_HCINTMSK_NAKM_Msk (0x1U << USB_OTG_HCINTMSK_NAKM_Pos) |
| #define | USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk |
| #define | USB_OTG_HCINTMSK_ACKM_Pos (5U) |
| #define | USB_OTG_HCINTMSK_ACKM_Msk (0x1U << USB_OTG_HCINTMSK_ACKM_Pos) |
| #define | USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk |
| #define | USB_OTG_HCINTMSK_NYET_Pos (6U) |
| #define | USB_OTG_HCINTMSK_NYET_Msk (0x1U << USB_OTG_HCINTMSK_NYET_Pos) |
| #define | USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk |
| #define | USB_OTG_HCINTMSK_TXERRM_Pos (7U) |
| #define | USB_OTG_HCINTMSK_TXERRM_Msk (0x1U << USB_OTG_HCINTMSK_TXERRM_Pos) |
| #define | USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk |
| #define | USB_OTG_HCINTMSK_BBERRM_Pos (8U) |
| #define | USB_OTG_HCINTMSK_BBERRM_Msk (0x1U << USB_OTG_HCINTMSK_BBERRM_Pos) |
| #define | USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk |
| #define | USB_OTG_HCINTMSK_FRMORM_Pos (9U) |
| #define | USB_OTG_HCINTMSK_FRMORM_Msk (0x1U << USB_OTG_HCINTMSK_FRMORM_Pos) |
| #define | USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk |
| #define | USB_OTG_HCINTMSK_DTERRM_Pos (10U) |
| #define | USB_OTG_HCINTMSK_DTERRM_Msk (0x1U << USB_OTG_HCINTMSK_DTERRM_Pos) |
| #define | USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk |
| #define | USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) |
| #define | USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) |
| #define | USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk |
| #define | USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) |
| #define | USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DIEPTSIZ_PKTCNT_Pos) |
| #define | USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk |
| #define | USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) |
| #define | USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3U << USB_OTG_DIEPTSIZ_MULCNT_Pos) |
| #define | USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk |
| #define | USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) |
| #define | USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_HCTSIZ_XFRSIZ_Pos) |
| #define | USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk |
| #define | USB_OTG_HCTSIZ_PKTCNT_Pos (19U) |
| #define | USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_HCTSIZ_PKTCNT_Pos) |
| #define | USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk |
| #define | USB_OTG_HCTSIZ_DOPING_Pos (31U) |
| #define | USB_OTG_HCTSIZ_DOPING_Msk (0x1U << USB_OTG_HCTSIZ_DOPING_Pos) |
| #define | USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk |
| #define | USB_OTG_HCTSIZ_DPID_Pos (29U) |
| #define | USB_OTG_HCTSIZ_DPID_Msk (0x3U << USB_OTG_HCTSIZ_DPID_Pos) |
| #define | USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk |
| #define | USB_OTG_HCTSIZ_DPID_0 (0x1U << USB_OTG_HCTSIZ_DPID_Pos) |
| #define | USB_OTG_HCTSIZ_DPID_1 (0x2U << USB_OTG_HCTSIZ_DPID_Pos) |
| #define | USB_OTG_DIEPDMA_DMAADDR_Pos (0U) |
| #define | USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_DIEPDMA_DMAADDR_Pos) |
| #define | USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk |
| #define | USB_OTG_HCDMA_DMAADDR_Pos (0U) |
| #define | USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFU << USB_OTG_HCDMA_DMAADDR_Pos) |
| #define | USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk |
| #define | USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) |
| #define | USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFU << USB_OTG_DTXFSTS_INEPTFSAV_Pos) |
| #define | USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk |
| #define | USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) |
| #define | USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXSA_Pos) |
| #define | USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk |
| #define | USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) |
| #define | USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFU << USB_OTG_DIEPTXF_INEPTXFD_Pos) |
| #define | USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk |
| #define | USB_OTG_DOEPCTL_MPSIZ_Pos (0U) |
| #define | USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFU << USB_OTG_DOEPCTL_MPSIZ_Pos) |
| #define | USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk |
| #define | USB_OTG_DOEPCTL_USBAEP_Pos (15U) |
| #define | USB_OTG_DOEPCTL_USBAEP_Msk (0x1U << USB_OTG_DOEPCTL_USBAEP_Pos) |
| #define | USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk |
| #define | USB_OTG_DOEPCTL_NAKSTS_Pos (17U) |
| #define | USB_OTG_DOEPCTL_NAKSTS_Msk (0x1U << USB_OTG_DOEPCTL_NAKSTS_Pos) |
| #define | USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk |
| #define | USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) |
| #define | USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1U << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) |
| #define | USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk |
| #define | USB_OTG_DOEPCTL_SODDFRM_Pos (29U) |
| #define | USB_OTG_DOEPCTL_SODDFRM_Msk (0x1U << USB_OTG_DOEPCTL_SODDFRM_Pos) |
| #define | USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk |
| #define | USB_OTG_DOEPCTL_EPTYP_Pos (18U) |
| #define | USB_OTG_DOEPCTL_EPTYP_Msk (0x3U << USB_OTG_DOEPCTL_EPTYP_Pos) |
| #define | USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk |
| #define | USB_OTG_DOEPCTL_EPTYP_0 (0x1U << USB_OTG_DOEPCTL_EPTYP_Pos) |
| #define | USB_OTG_DOEPCTL_EPTYP_1 (0x2U << USB_OTG_DOEPCTL_EPTYP_Pos) |
| #define | USB_OTG_DOEPCTL_SNPM_Pos (20U) |
| #define | USB_OTG_DOEPCTL_SNPM_Msk (0x1U << USB_OTG_DOEPCTL_SNPM_Pos) |
| #define | USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk |
| #define | USB_OTG_DOEPCTL_STALL_Pos (21U) |
| #define | USB_OTG_DOEPCTL_STALL_Msk (0x1U << USB_OTG_DOEPCTL_STALL_Pos) |
| #define | USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk |
| #define | USB_OTG_DOEPCTL_CNAK_Pos (26U) |
| #define | USB_OTG_DOEPCTL_CNAK_Msk (0x1U << USB_OTG_DOEPCTL_CNAK_Pos) |
| #define | USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk |
| #define | USB_OTG_DOEPCTL_SNAK_Pos (27U) |
| #define | USB_OTG_DOEPCTL_SNAK_Msk (0x1U << USB_OTG_DOEPCTL_SNAK_Pos) |
| #define | USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk |
| #define | USB_OTG_DOEPCTL_EPDIS_Pos (30U) |
| #define | USB_OTG_DOEPCTL_EPDIS_Msk (0x1U << USB_OTG_DOEPCTL_EPDIS_Pos) |
| #define | USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk |
| #define | USB_OTG_DOEPCTL_EPENA_Pos (31U) |
| #define | USB_OTG_DOEPCTL_EPENA_Msk (0x1U << USB_OTG_DOEPCTL_EPENA_Pos) |
| #define | USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk |
| #define | USB_OTG_DOEPINT_XFRC_Pos (0U) |
| #define | USB_OTG_DOEPINT_XFRC_Msk (0x1U << USB_OTG_DOEPINT_XFRC_Pos) |
| #define | USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk |
| #define | USB_OTG_DOEPINT_EPDISD_Pos (1U) |
| #define | USB_OTG_DOEPINT_EPDISD_Msk (0x1U << USB_OTG_DOEPINT_EPDISD_Pos) |
| #define | USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk |
| #define | USB_OTG_DOEPINT_STUP_Pos (3U) |
| #define | USB_OTG_DOEPINT_STUP_Msk (0x1U << USB_OTG_DOEPINT_STUP_Pos) |
| #define | USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk |
| #define | USB_OTG_DOEPINT_OTEPDIS_Pos (4U) |
| #define | USB_OTG_DOEPINT_OTEPDIS_Msk (0x1U << USB_OTG_DOEPINT_OTEPDIS_Pos) |
| #define | USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk |
| #define | USB_OTG_DOEPINT_B2BSTUP_Pos (6U) |
| #define | USB_OTG_DOEPINT_B2BSTUP_Msk (0x1U << USB_OTG_DOEPINT_B2BSTUP_Pos) |
| #define | USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk |
| #define | USB_OTG_DOEPINT_NYET_Pos (14U) |
| #define | USB_OTG_DOEPINT_NYET_Msk (0x1U << USB_OTG_DOEPINT_NYET_Pos) |
| #define | USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk |
| #define | USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) |
| #define | USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFU << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) |
| #define | USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk |
| #define | USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U) |
| #define | USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFU << USB_OTG_DOEPTSIZ_PKTCNT_Pos) |
| #define | USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk |
| #define | USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) |
| #define | USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) |
| #define | USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk |
| #define | USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) |
| #define | USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2U << USB_OTG_DOEPTSIZ_STUPCNT_Pos) |
| #define | USB_OTG_PCGCCTL_STOPCLK_Pos (0U) |
| #define | USB_OTG_PCGCCTL_STOPCLK_Msk (0x1U << USB_OTG_PCGCCTL_STOPCLK_Pos) |
| #define | USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk |
| #define | USB_OTG_PCGCCTL_GATECLK_Pos (1U) |
| #define | USB_OTG_PCGCCTL_GATECLK_Msk (0x1U << USB_OTG_PCGCCTL_GATECLK_Pos) |
| #define | USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk |
| #define | USB_OTG_PCGCCTL_PHYSUSP_Pos (4U) |
| #define | USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) |
| #define | USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk |
| #define | USART_CR1_UE_Pos (0U) |
| #define | USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) |
| #define | USART_CR1_UE USART_CR1_UE_Msk |
| #define | USART_CR1_UESM_Pos (1U) |
| #define | USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) |
| #define | USART_CR1_UESM USART_CR1_UESM_Msk |
| #define | USART_CR1_RE_Pos (2U) |
| #define | USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) |
| #define | USART_CR1_RE USART_CR1_RE_Msk |
| #define | USART_CR1_TE_Pos (3U) |
| #define | USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) |
| #define | USART_CR1_TE USART_CR1_TE_Msk |
| #define | USART_CR1_IDLEIE_Pos (4U) |
| #define | USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) |
| #define | USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk |
| #define | USART_CR1_RXNEIE_Pos (5U) |
| #define | USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) |
| #define | USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk |
| #define | USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos |
| #define | USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk |
| #define | USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk |
| #define | USART_CR1_TCIE_Pos (6U) |
| #define | USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) |
| #define | USART_CR1_TCIE USART_CR1_TCIE_Msk |
| #define | USART_CR1_TXEIE_Pos (7U) |
| #define | USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) |
| #define | USART_CR1_TXEIE USART_CR1_TXEIE_Msk |
| #define | USART_CR1_TXEIE_TXFNFIE_Pos (7U) |
| #define | USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) |
| #define | USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE |
| #define | USART_CR1_PEIE_Pos (8U) |
| #define | USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) |
| #define | USART_CR1_PEIE USART_CR1_PEIE_Msk |
| #define | USART_CR1_PS_Pos (9U) |
| #define | USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) |
| #define | USART_CR1_PS USART_CR1_PS_Msk |
| #define | USART_CR1_PCE_Pos (10U) |
| #define | USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) |
| #define | USART_CR1_PCE USART_CR1_PCE_Msk |
| #define | USART_CR1_WAKE_Pos (11U) |
| #define | USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) |
| #define | USART_CR1_WAKE USART_CR1_WAKE_Msk |
| #define | USART_CR1_M_Pos (12U) |
| #define | USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) |
| #define | USART_CR1_M USART_CR1_M_Msk |
| #define | USART_CR1_M0_Pos (12U) |
| #define | USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) |
| #define | USART_CR1_M0 USART_CR1_M0_Msk |
| #define | USART_CR1_MME_Pos (13U) |
| #define | USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) |
| #define | USART_CR1_MME USART_CR1_MME_Msk |
| #define | USART_CR1_CMIE_Pos (14U) |
| #define | USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) |
| #define | USART_CR1_CMIE USART_CR1_CMIE_Msk |
| #define | USART_CR1_OVER8_Pos (15U) |
| #define | USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) |
| #define | USART_CR1_OVER8 USART_CR1_OVER8_Msk |
| #define | USART_CR1_DEDT_Pos (16U) |
| #define | USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) |
| #define | USART_CR1_DEDT USART_CR1_DEDT_Msk |
| #define | USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) |
| #define | USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) |
| #define | USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) |
| #define | USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) |
| #define | USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) |
| #define | USART_CR1_DEAT_Pos (21U) |
| #define | USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) |
| #define | USART_CR1_DEAT USART_CR1_DEAT_Msk |
| #define | USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) |
| #define | USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) |
| #define | USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) |
| #define | USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) |
| #define | USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) |
| #define | USART_CR1_RTOIE_Pos (26U) |
| #define | USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) |
| #define | USART_CR1_RTOIE USART_CR1_RTOIE_Msk |
| #define | USART_CR1_EOBIE_Pos (27U) |
| #define | USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) |
| #define | USART_CR1_EOBIE USART_CR1_EOBIE_Msk |
| #define | USART_CR1_M1_Pos (28U) |
| #define | USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) |
| #define | USART_CR1_M1 USART_CR1_M1_Msk |
| #define | USART_CR1_FIFOEN_Pos (29U) |
| #define | USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) |
| #define | USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk |
| #define | USART_CR1_TXFEIE_Pos (30U) |
| #define | USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) |
| #define | USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk |
| #define | USART_CR1_RXFFIE_Pos (31U) |
| #define | USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) |
| #define | USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk |
| #define | USART_CR2_SLVEN_Pos (0U) |
| #define | USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) |
| #define | USART_CR2_SLVEN USART_CR2_SLVEN_Msk |
| #define | USART_CR2_DIS_NSS_Pos (3U) |
| #define | USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) |
| #define | USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk |
| #define | USART_CR2_ADDM7_Pos (4U) |
| #define | USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) |
| #define | USART_CR2_ADDM7 USART_CR2_ADDM7_Msk |
| #define | USART_CR2_LBDL_Pos (5U) |
| #define | USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) |
| #define | USART_CR2_LBDL USART_CR2_LBDL_Msk |
| #define | USART_CR2_LBDIE_Pos (6U) |
| #define | USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) |
| #define | USART_CR2_LBDIE USART_CR2_LBDIE_Msk |
| #define | USART_CR2_LBCL_Pos (8U) |
| #define | USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) |
| #define | USART_CR2_LBCL USART_CR2_LBCL_Msk |
| #define | USART_CR2_CPHA_Pos (9U) |
| #define | USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) |
| #define | USART_CR2_CPHA USART_CR2_CPHA_Msk |
| #define | USART_CR2_CPOL_Pos (10U) |
| #define | USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) |
| #define | USART_CR2_CPOL USART_CR2_CPOL_Msk |
| #define | USART_CR2_CLKEN_Pos (11U) |
| #define | USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) |
| #define | USART_CR2_CLKEN USART_CR2_CLKEN_Msk |
| #define | USART_CR2_STOP_Pos (12U) |
| #define | USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) |
| #define | USART_CR2_STOP USART_CR2_STOP_Msk |
| #define | USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) |
| #define | USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) |
| #define | USART_CR2_LINEN_Pos (14U) |
| #define | USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) |
| #define | USART_CR2_LINEN USART_CR2_LINEN_Msk |
| #define | USART_CR2_SWAP_Pos (15U) |
| #define | USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) |
| #define | USART_CR2_SWAP USART_CR2_SWAP_Msk |
| #define | USART_CR2_RXINV_Pos (16U) |
| #define | USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) |
| #define | USART_CR2_RXINV USART_CR2_RXINV_Msk |
| #define | USART_CR2_TXINV_Pos (17U) |
| #define | USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) |
| #define | USART_CR2_TXINV USART_CR2_TXINV_Msk |
| #define | USART_CR2_DATAINV_Pos (18U) |
| #define | USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) |
| #define | USART_CR2_DATAINV USART_CR2_DATAINV_Msk |
| #define | USART_CR2_MSBFIRST_Pos (19U) |
| #define | USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) |
| #define | USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk |
| #define | USART_CR2_ABREN_Pos (20U) |
| #define | USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) |
| #define | USART_CR2_ABREN USART_CR2_ABREN_Msk |
| #define | USART_CR2_ABRMODE_Pos (21U) |
| #define | USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) |
| #define | USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk |
| #define | USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) |
| #define | USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) |
| #define | USART_CR2_RTOEN_Pos (23U) |
| #define | USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) |
| #define | USART_CR2_RTOEN USART_CR2_RTOEN_Msk |
| #define | USART_CR2_ADD_Pos (24U) |
| #define | USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) |
| #define | USART_CR2_ADD USART_CR2_ADD_Msk |
| #define | USART_CR3_EIE_Pos (0U) |
| #define | USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) |
| #define | USART_CR3_EIE USART_CR3_EIE_Msk |
| #define | USART_CR3_IREN_Pos (1U) |
| #define | USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) |
| #define | USART_CR3_IREN USART_CR3_IREN_Msk |
| #define | USART_CR3_IRLP_Pos (2U) |
| #define | USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) |
| #define | USART_CR3_IRLP USART_CR3_IRLP_Msk |
| #define | USART_CR3_HDSEL_Pos (3U) |
| #define | USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) |
| #define | USART_CR3_HDSEL USART_CR3_HDSEL_Msk |
| #define | USART_CR3_NACK_Pos (4U) |
| #define | USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) |
| #define | USART_CR3_NACK USART_CR3_NACK_Msk |
| #define | USART_CR3_SCEN_Pos (5U) |
| #define | USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) |
| #define | USART_CR3_SCEN USART_CR3_SCEN_Msk |
| #define | USART_CR3_DMAR_Pos (6U) |
| #define | USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) |
| #define | USART_CR3_DMAR USART_CR3_DMAR_Msk |
| #define | USART_CR3_DMAT_Pos (7U) |
| #define | USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) |
| #define | USART_CR3_DMAT USART_CR3_DMAT_Msk |
| #define | USART_CR3_RTSE_Pos (8U) |
| #define | USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) |
| #define | USART_CR3_RTSE USART_CR3_RTSE_Msk |
| #define | USART_CR3_CTSE_Pos (9U) |
| #define | USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) |
| #define | USART_CR3_CTSE USART_CR3_CTSE_Msk |
| #define | USART_CR3_CTSIE_Pos (10U) |
| #define | USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) |
| #define | USART_CR3_CTSIE USART_CR3_CTSIE_Msk |
| #define | USART_CR3_ONEBIT_Pos (11U) |
| #define | USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) |
| #define | USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk |
| #define | USART_CR3_OVRDIS_Pos (12U) |
| #define | USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) |
| #define | USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk |
| #define | USART_CR3_DDRE_Pos (13U) |
| #define | USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) |
| #define | USART_CR3_DDRE USART_CR3_DDRE_Msk |
| #define | USART_CR3_DEM_Pos (14U) |
| #define | USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) |
| #define | USART_CR3_DEM USART_CR3_DEM_Msk |
| #define | USART_CR3_DEP_Pos (15U) |
| #define | USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) |
| #define | USART_CR3_DEP USART_CR3_DEP_Msk |
| #define | USART_CR3_SCARCNT_Pos (17U) |
| #define | USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) |
| #define | USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk |
| #define | USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) |
| #define | USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) |
| #define | USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) |
| #define | USART_CR3_TXFTIE_Pos (23U) |
| #define | USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) |
| #define | USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk |
| #define | USART_CR3_TCBGTIE_Pos (24U) |
| #define | USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) |
| #define | USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk |
| #define | USART_CR3_RXFTCFG_Pos (25U) |
| #define | USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) |
| #define | USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk |
| #define | USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) |
| #define | USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) |
| #define | USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) |
| #define | USART_CR3_RXFTIE_Pos (28U) |
| #define | USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) |
| #define | USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk |
| #define | USART_CR3_TXFTCFG_Pos (29U) |
| #define | USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) |
| #define | USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk |
| #define | USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) |
| #define | USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) |
| #define | USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) |
| #define | USART_BRR_LPUART_Pos (0U) |
| #define | USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos) |
| #define | USART_BRR_LPUART USART_BRR_LPUART_Msk |
| #define | USART_BRR_BRR ((uint16_t)0xFFFF) |
| #define | USART_GTPR_PSC_Pos (0U) |
| #define | USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) |
| #define | USART_GTPR_PSC USART_GTPR_PSC_Msk |
| #define | USART_GTPR_GT_Pos (8U) |
| #define | USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) |
| #define | USART_GTPR_GT USART_GTPR_GT_Msk |
| #define | USART_RTOR_RTO_Pos (0U) |
| #define | USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) |
| #define | USART_RTOR_RTO USART_RTOR_RTO_Msk |
| #define | USART_RTOR_BLEN_Pos (24U) |
| #define | USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) |
| #define | USART_RTOR_BLEN USART_RTOR_BLEN_Msk |
| #define | USART_RQR_ABRRQ ((uint16_t)0x0001) |
| #define | USART_RQR_SBKRQ ((uint16_t)0x0002) |
| #define | USART_RQR_MMRQ ((uint16_t)0x0004) |
| #define | USART_RQR_RXFRQ ((uint16_t)0x0008) |
| #define | USART_RQR_TXFRQ ((uint16_t)0x0010) |
| #define | USART_ISR_PE_Pos (0U) |
| #define | USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) |
| #define | USART_ISR_PE USART_ISR_PE_Msk |
| #define | USART_ISR_FE_Pos (1U) |
| #define | USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) |
| #define | USART_ISR_FE USART_ISR_FE_Msk |
| #define | USART_ISR_NE_Pos (2U) |
| #define | USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) |
| #define | USART_ISR_NE USART_ISR_NE_Msk |
| #define | USART_ISR_ORE_Pos (3U) |
| #define | USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) |
| #define | USART_ISR_ORE USART_ISR_ORE_Msk |
| #define | USART_ISR_IDLE_Pos (4U) |
| #define | USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) |
| #define | USART_ISR_IDLE USART_ISR_IDLE_Msk |
| #define | USART_ISR_RXNE_Pos (5U) |
| #define | USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) |
| #define | USART_ISR_RXNE USART_ISR_RXNE_Msk |
| #define | USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos |
| #define | USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk |
| #define | USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk |
| #define | USART_ISR_TC_Pos (6U) |
| #define | USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) |
| #define | USART_ISR_TC USART_ISR_TC_Msk |
| #define | USART_ISR_TXE_Pos (7U) |
| #define | USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) |
| #define | USART_ISR_TXE USART_ISR_TXE_Msk |
| #define | USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos |
| #define | USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk |
| #define | USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk |
| #define | USART_ISR_LBDF_Pos (8U) |
| #define | USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) |
| #define | USART_ISR_LBDF USART_ISR_LBDF_Msk |
| #define | USART_ISR_CTSIF_Pos (9U) |
| #define | USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) |
| #define | USART_ISR_CTSIF USART_ISR_CTSIF_Msk |
| #define | USART_ISR_CTS_Pos (10U) |
| #define | USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) |
| #define | USART_ISR_CTS USART_ISR_CTS_Msk |
| #define | USART_ISR_RTOF_Pos (11U) |
| #define | USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) |
| #define | USART_ISR_RTOF USART_ISR_RTOF_Msk |
| #define | USART_ISR_EOBF_Pos (12U) |
| #define | USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) |
| #define | USART_ISR_EOBF USART_ISR_EOBF_Msk |
| #define | USART_ISR_UDR_Pos (13U) |
| #define | USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) |
| #define | USART_ISR_UDR USART_ISR_UDR_Msk |
| #define | USART_ISR_ABRE_Pos (14U) |
| #define | USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) |
| #define | USART_ISR_ABRE USART_ISR_ABRE_Msk |
| #define | USART_ISR_ABRF_Pos (15U) |
| #define | USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) |
| #define | USART_ISR_ABRF USART_ISR_ABRF_Msk |
| #define | USART_ISR_BUSY_Pos (16U) |
| #define | USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) |
| #define | USART_ISR_BUSY USART_ISR_BUSY_Msk |
| #define | USART_ISR_CMF_Pos (17U) |
| #define | USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) |
| #define | USART_ISR_CMF USART_ISR_CMF_Msk |
| #define | USART_ISR_SBKF_Pos (18U) |
| #define | USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) |
| #define | USART_ISR_SBKF USART_ISR_SBKF_Msk |
| #define | USART_ISR_RWU_Pos (19U) |
| #define | USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) |
| #define | USART_ISR_RWU USART_ISR_RWU_Msk |
| #define | USART_ISR_TEACK_Pos (21U) |
| #define | USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) |
| #define | USART_ISR_TEACK USART_ISR_TEACK_Msk |
| #define | USART_ISR_REACK_Pos (22U) |
| #define | USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) |
| #define | USART_ISR_REACK USART_ISR_REACK_Msk |
| #define | USART_ISR_TXFE_Pos (23U) |
| #define | USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) |
| #define | USART_ISR_TXFE USART_ISR_TXFE_Msk |
| #define | USART_ISR_RXFF_Pos (24U) |
| #define | USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) |
| #define | USART_ISR_RXFF USART_ISR_RXFF_Msk |
| #define | USART_ISR_TCBGT_Pos (25U) |
| #define | USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) |
| #define | USART_ISR_TCBGT USART_ISR_TCBGT_Msk |
| #define | USART_ISR_RXFT_Pos (26U) |
| #define | USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) |
| #define | USART_ISR_RXFT USART_ISR_RXFT_Msk |
| #define | USART_ISR_TXFT_Pos (27U) |
| #define | USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) |
| #define | USART_ISR_TXFT USART_ISR_TXFT_Msk |
| #define | USART_ICR_PECF_Pos (0U) |
| #define | USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) |
| #define | USART_ICR_PECF USART_ICR_PECF_Msk |
| #define | USART_ICR_FECF_Pos (1U) |
| #define | USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) |
| #define | USART_ICR_FECF USART_ICR_FECF_Msk |
| #define | USART_ICR_NECF_Pos (2U) |
| #define | USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) |
| #define | USART_ICR_NECF USART_ICR_NECF_Msk |
| #define | USART_ICR_ORECF_Pos (3U) |
| #define | USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) |
| #define | USART_ICR_ORECF USART_ICR_ORECF_Msk |
| #define | USART_ICR_IDLECF_Pos (4U) |
| #define | USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) |
| #define | USART_ICR_IDLECF USART_ICR_IDLECF_Msk |
| #define | USART_ICR_TXFECF_Pos (5U) |
| #define | USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) |
| #define | USART_ICR_TXFECF USART_ICR_TXFECF_Msk |
| #define | USART_ICR_TCCF_Pos (6U) |
| #define | USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) |
| #define | USART_ICR_TCCF USART_ICR_TCCF_Msk |
| #define | USART_ICR_TCBGTCF_Pos (7U) |
| #define | USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) |
| #define | USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk |
| #define | USART_ICR_LBDCF_Pos (8U) |
| #define | USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) |
| #define | USART_ICR_LBDCF USART_ICR_LBDCF_Msk |
| #define | USART_ICR_CTSCF_Pos (9U) |
| #define | USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) |
| #define | USART_ICR_CTSCF USART_ICR_CTSCF_Msk |
| #define | USART_ICR_RTOCF_Pos (11U) |
| #define | USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) |
| #define | USART_ICR_RTOCF USART_ICR_RTOCF_Msk |
| #define | USART_ICR_EOBCF_Pos (12U) |
| #define | USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) |
| #define | USART_ICR_EOBCF USART_ICR_EOBCF_Msk |
| #define | USART_ICR_UDRCF_Pos (13U) |
| #define | USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) |
| #define | USART_ICR_UDRCF USART_ICR_UDRCF_Msk |
| #define | USART_ICR_CMCF_Pos (17U) |
| #define | USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) |
| #define | USART_ICR_CMCF USART_ICR_CMCF_Msk |
| #define | USART_RDR_RDR ((uint16_t)0x01FF) |
| #define | USART_TDR_TDR ((uint16_t)0x01FF) |
| #define | USART_PRESC_PRESCALER_Pos (0U) |
| #define | USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) |
| #define | USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk |
| #define | USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) |
| #define | USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) |
| #define | USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) |
| #define | USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) |
| #define | USART_AUTOCR_TDN_Pos (0U) |
| #define | USART_AUTOCR_TDN_Msk (0xFFFFUL << USART_AUTOCR_TDN_Pos) |
| #define | USART_AUTOCR_TDN USART_AUTOCR_TDN_Msk |
| #define | USART_AUTOCR_TRIGPOL_Pos (16U) |
| #define | USART_AUTOCR_TRIGPOL_Msk (0x1UL << USART_AUTOCR_TRIGPOL_Pos) |
| #define | USART_AUTOCR_TRIGPOL USART_AUTOCR_TRIGPOL_Msk |
| #define | USART_AUTOCR_TRIGEN_Pos (17U) |
| #define | USART_AUTOCR_TRIGEN_Msk (0x1UL << USART_AUTOCR_TRIGEN_Pos) |
| #define | USART_AUTOCR_TRIGEN USART_AUTOCR_TRIGEN_Msk |
| #define | USART_AUTOCR_IDLEDIS_Pos (18U) |
| #define | USART_AUTOCR_IDLEDIS_Msk (0x1UL << USART_AUTOCR_IDLEDIS_Pos) |
| #define | USART_AUTOCR_IDLEDIS USART_AUTOCR_IDLEDIS_Msk |
| #define | USART_AUTOCR_TRIGSEL_Pos (19U) |
| #define | USART_AUTOCR_TRIGSEL_Msk (0xFUL << USART_AUTOCR_TRIGSEL_Pos) |
| #define | USART_AUTOCR_TRIGSEL USART_AUTOCR_TRIGSEL_Msk |
| #define | USART_AUTOCR_TRIGSEL_0 (0x0001UL << USART_AUTOCR_TRIGSEL_Pos) |
| #define | USART_AUTOCR_TRIGSEL_1 (0x0002UL << USART_AUTOCR_TRIGSEL_Pos) |
| #define | USART_AUTOCR_TRIGSEL_2 (0x0004UL << USART_AUTOCR_TRIGSEL_Pos) |
| #define | USART_AUTOCR_TRIGSEL_3 (0x0008UL << USART_AUTOCR_TRIGSEL_Pos) |
| #define | USART_HWCFGR2_CFG1_Pos (0U) |
| #define | USART_HWCFGR2_CFG1_Msk (0xFUL << USART_HWCFGR2_CFG1_Pos) |
| #define | USART_HWCFGR2_CFG1 USART_HWCFGR2_CFG1_Msk |
| #define | USART_HWCFGR2_CFG2_Pos (4U) |
| #define | USART_HWCFGR2_CFG2_Msk (0xFUL << USART_HWCFGR2_CFG2_Pos) |
| #define | USART_HWCFGR2_CFG2 USART_HWCFGR2_CFG2_Msk |
| #define | USART_HWCFGR1_CFG1_Pos (0U) |
| #define | USART_HWCFGR1_CFG1_Msk (0xFUL << USART_HWCFGR1_CFG1_Pos) |
| #define | USART_HWCFGR1_CFG1 USART_HWCFGR1_CFG1_Msk |
| #define | USART_HWCFGR1_CFG2_Pos (4U) |
| #define | USART_HWCFGR1_CFG2_Msk (0xFUL << USART_HWCFGR1_CFG2_Pos) |
| #define | USART_HWCFGR1_CFG2 USART_HWCFGR1_CFG2_Msk |
| #define | USART_HWCFGR1_CFG3_Pos (8U) |
| #define | USART_HWCFGR1_CFG3_Msk (0xFUL << USART_HWCFGR1_CFG3_Pos) |
| #define | USART_HWCFGR1_CFG3 USART_HWCFGR1_CFG3_Msk |
| #define | USART_HWCFGR1_CFG4_Pos (12U) |
| #define | USART_HWCFGR1_CFG4_Msk (0xFUL << USART_HWCFGR1_CFG4_Pos) |
| #define | USART_HWCFGR1_CFG4 USART_HWCFGR1_CFG4_Msk |
| #define | USART_HWCFGR1_CFG5_Pos (16U) |
| #define | USART_HWCFGR1_CFG5_Msk (0xFUL << USART_HWCFGR1_CFG5_Pos) |
| #define | USART_HWCFGR1_CFG5 USART_HWCFGR1_CFG5_Msk |
| #define | USART_HWCFGR1_CFG6_Pos (20U) |
| #define | USART_HWCFGR1_CFG6_Msk (0xFUL << USART_HWCFGR1_CFG6_Pos) |
| #define | USART_HWCFGR1_CFG6 USART_HWCFGR1_CFG6_Msk |
| #define | USART_HWCFGR1_CFG7_Pos (24U) |
| #define | USART_HWCFGR1_CFG7_Msk (0xFUL << USART_HWCFGR1_CFG7_Pos) |
| #define | USART_HWCFGR1_CFG7 USART_HWCFGR1_CFG7_Msk |
| #define | USART_HWCFGR1_CFG8_Pos (28U) |
| #define | USART_HWCFGR1_CFG8_Msk (0xFUL << USART_HWCFGR1_CFG8_Pos) |
| #define | USART_HWCFGR1_CFG8 USART_HWCFGR1_CFG8_Msk |
| #define | USART_VERR_MINREV_Pos (0U) |
| #define | USART_VERR_MINREV_Msk (0xFUL << USART_VERR_MINREV_Pos) |
| #define | USART_VERR_MINREV USART_VERR_MINREV_Msk |
| #define | USART_VERR_MAJREV_Pos (4U) |
| #define | USART_VERR_MAJREV_Msk (0xFUL << USART_VERR_MAJREV_Pos) |
| #define | USART_VERR_MAJREV USART_VERR_MAJREV_Msk |
| #define | USART_IPIDR_ID_Pos (0U) |
| #define | USART_IPIDR_ID_Msk (0xFFFFFFFFUL << USART_IPIDR_ID_Pos) |
| #define | USART_IPIDR_ID USART_IPIDR_ID_Msk |
| #define | USART_SIDR_ID_Pos (0U) |
| #define | USART_SIDR_ID_Msk (0xFFFFFFFFUL << USART_SIDR_ID_Pos) |
| #define | USART_SIDR_ID USART_SIDR_ID_Msk |
| #define | I2C_CR1_PE_Pos (0U) |
| #define | I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) |
| #define | I2C_CR1_PE I2C_CR1_PE_Msk |
| #define | I2C_CR1_TXIE_Pos (1U) |
| #define | I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) |
| #define | I2C_CR1_TXIE I2C_CR1_TXIE_Msk |
| #define | I2C_CR1_RXIE_Pos (2U) |
| #define | I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) |
| #define | I2C_CR1_RXIE I2C_CR1_RXIE_Msk |
| #define | I2C_CR1_ADDRIE_Pos (3U) |
| #define | I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) |
| #define | I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk |
| #define | I2C_CR1_NACKIE_Pos (4U) |
| #define | I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) |
| #define | I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk |
| #define | I2C_CR1_STOPIE_Pos (5U) |
| #define | I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) |
| #define | I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk |
| #define | I2C_CR1_TCIE_Pos (6U) |
| #define | I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) |
| #define | I2C_CR1_TCIE I2C_CR1_TCIE_Msk |
| #define | I2C_CR1_ERRIE_Pos (7U) |
| #define | I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) |
| #define | I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk |
| #define | I2C_CR1_DNF_Pos (8U) |
| #define | I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) |
| #define | I2C_CR1_DNF I2C_CR1_DNF_Msk |
| #define | I2C_CR1_ANFOFF_Pos (12U) |
| #define | I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) |
| #define | I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk |
| #define | I2C_CR1_SWRST_Pos (13U) |
| #define | I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) |
| #define | I2C_CR1_SWRST I2C_CR1_SWRST_Msk |
| #define | I2C_CR1_TXDMAEN_Pos (14U) |
| #define | I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) |
| #define | I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk |
| #define | I2C_CR1_RXDMAEN_Pos (15U) |
| #define | I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) |
| #define | I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk |
| #define | I2C_CR1_SBC_Pos (16U) |
| #define | I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) |
| #define | I2C_CR1_SBC I2C_CR1_SBC_Msk |
| #define | I2C_CR1_NOSTRETCH_Pos (17U) |
| #define | I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) |
| #define | I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk |
| #define | I2C_CR1_WUPEN_Pos (18U) |
| #define | I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) |
| #define | I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk |
| #define | I2C_CR1_GCEN_Pos (19U) |
| #define | I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) |
| #define | I2C_CR1_GCEN I2C_CR1_GCEN_Msk |
| #define | I2C_CR1_SMBHEN_Pos (20U) |
| #define | I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) |
| #define | I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk |
| #define | I2C_CR1_SMBDEN_Pos (21U) |
| #define | I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) |
| #define | I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk |
| #define | I2C_CR1_ALERTEN_Pos (22U) |
| #define | I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) |
| #define | I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk |
| #define | I2C_CR1_PECEN_Pos (23U) |
| #define | I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) |
| #define | I2C_CR1_PECEN I2C_CR1_PECEN_Msk |
| #define | I2C_CR1_FMP_Pos (24U) |
| #define | I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) |
| #define | I2C_CR1_FMP I2C_CR1_FMP_Msk |
| #define | I2C_CR1_ADDRACLR_Pos (30U) |
| #define | I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) |
| #define | I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk |
| #define | I2C_CR1_STOPFACLR_Pos (31U) |
| #define | I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) |
| #define | I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk |
| #define | I2C_CR2_SADD_Pos (0U) |
| #define | I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) |
| #define | I2C_CR2_SADD I2C_CR2_SADD_Msk |
| #define | I2C_CR2_RD_WRN_Pos (10U) |
| #define | I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) |
| #define | I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk |
| #define | I2C_CR2_ADD10_Pos (11U) |
| #define | I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) |
| #define | I2C_CR2_ADD10 I2C_CR2_ADD10_Msk |
| #define | I2C_CR2_HEAD10R_Pos (12U) |
| #define | I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) |
| #define | I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk |
| #define | I2C_CR2_START_Pos (13U) |
| #define | I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) |
| #define | I2C_CR2_START I2C_CR2_START_Msk |
| #define | I2C_CR2_STOP_Pos (14U) |
| #define | I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) |
| #define | I2C_CR2_STOP I2C_CR2_STOP_Msk |
| #define | I2C_CR2_NACK_Pos (15U) |
| #define | I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) |
| #define | I2C_CR2_NACK I2C_CR2_NACK_Msk |
| #define | I2C_CR2_NBYTES_Pos (16U) |
| #define | I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) |
| #define | I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk |
| #define | I2C_CR2_RELOAD_Pos (24U) |
| #define | I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) |
| #define | I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk |
| #define | I2C_CR2_AUTOEND_Pos (25U) |
| #define | I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) |
| #define | I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk |
| #define | I2C_CR2_PECBYTE_Pos (26U) |
| #define | I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) |
| #define | I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk |
| #define | I2C_OAR1_OA1_Pos (0U) |
| #define | I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) |
| #define | I2C_OAR1_OA1 I2C_OAR1_OA1_Msk |
| #define | I2C_OAR1_OA1MODE_Pos (10U) |
| #define | I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) |
| #define | I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk |
| #define | I2C_OAR1_OA1EN_Pos (15U) |
| #define | I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) |
| #define | I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk |
| #define | I2C_OAR2_OA2_Pos (1U) |
| #define | I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) |
| #define | I2C_OAR2_OA2 I2C_OAR2_OA2_Msk |
| #define | I2C_OAR2_OA2MSK_Pos (8U) |
| #define | I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) |
| #define | I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk |
| #define | I2C_OAR2_OA2NOMASK (0x00000000UL) |
| #define | I2C_OAR2_OA2MASK01_Pos (8U) |
| #define | I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) |
| #define | I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk |
| #define | I2C_OAR2_OA2MASK02_Pos (9U) |
| #define | I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) |
| #define | I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk |
| #define | I2C_OAR2_OA2MASK03_Pos (8U) |
| #define | I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) |
| #define | I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk |
| #define | I2C_OAR2_OA2MASK04_Pos (10U) |
| #define | I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) |
| #define | I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk |
| #define | I2C_OAR2_OA2MASK05_Pos (8U) |
| #define | I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) |
| #define | I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk |
| #define | I2C_OAR2_OA2MASK06_Pos (9U) |
| #define | I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) |
| #define | I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk |
| #define | I2C_OAR2_OA2MASK07_Pos (8U) |
| #define | I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) |
| #define | I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk |
| #define | I2C_OAR2_OA2EN_Pos (15U) |
| #define | I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) |
| #define | I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk |
| #define | I2C_TIMINGR_SCLL_Pos (0U) |
| #define | I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) |
| #define | I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk |
| #define | I2C_TIMINGR_SCLH_Pos (8U) |
| #define | I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) |
| #define | I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk |
| #define | I2C_TIMINGR_SDADEL_Pos (16U) |
| #define | I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) |
| #define | I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk |
| #define | I2C_TIMINGR_SCLDEL_Pos (20U) |
| #define | I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) |
| #define | I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk |
| #define | I2C_TIMINGR_PRESC_Pos (28U) |
| #define | I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) |
| #define | I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk |
| #define | I2C_TIMEOUTR_TIMEOUTA_Pos (0U) |
| #define | I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) |
| #define | I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk |
| #define | I2C_TIMEOUTR_TIDLE_Pos (12U) |
| #define | I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) |
| #define | I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk |
| #define | I2C_TIMEOUTR_TIMOUTEN_Pos (15U) |
| #define | I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) |
| #define | I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk |
| #define | I2C_TIMEOUTR_TIMEOUTB_Pos (16U) |
| #define | I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) |
| #define | I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk |
| #define | I2C_TIMEOUTR_TEXTEN_Pos (31U) |
| #define | I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) |
| #define | I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk |
| #define | I2C_ISR_TXE_Pos (0U) |
| #define | I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) |
| #define | I2C_ISR_TXE I2C_ISR_TXE_Msk |
| #define | I2C_ISR_TXIS_Pos (1U) |
| #define | I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) |
| #define | I2C_ISR_TXIS I2C_ISR_TXIS_Msk |
| #define | I2C_ISR_RXNE_Pos (2U) |
| #define | I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) |
| #define | I2C_ISR_RXNE I2C_ISR_RXNE_Msk |
| #define | I2C_ISR_ADDR_Pos (3U) |
| #define | I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) |
| #define | I2C_ISR_ADDR I2C_ISR_ADDR_Msk |
| #define | I2C_ISR_NACKF_Pos (4U) |
| #define | I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) |
| #define | I2C_ISR_NACKF I2C_ISR_NACKF_Msk |
| #define | I2C_ISR_STOPF_Pos (5U) |
| #define | I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) |
| #define | I2C_ISR_STOPF I2C_ISR_STOPF_Msk |
| #define | I2C_ISR_TC_Pos (6U) |
| #define | I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) |
| #define | I2C_ISR_TC I2C_ISR_TC_Msk |
| #define | I2C_ISR_TCR_Pos (7U) |
| #define | I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) |
| #define | I2C_ISR_TCR I2C_ISR_TCR_Msk |
| #define | I2C_ISR_BERR_Pos (8U) |
| #define | I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) |
| #define | I2C_ISR_BERR I2C_ISR_BERR_Msk |
| #define | I2C_ISR_ARLO_Pos (9U) |
| #define | I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) |
| #define | I2C_ISR_ARLO I2C_ISR_ARLO_Msk |
| #define | I2C_ISR_OVR_Pos (10U) |
| #define | I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) |
| #define | I2C_ISR_OVR I2C_ISR_OVR_Msk |
| #define | I2C_ISR_PECERR_Pos (11U) |
| #define | I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) |
| #define | I2C_ISR_PECERR I2C_ISR_PECERR_Msk |
| #define | I2C_ISR_TIMEOUT_Pos (12U) |
| #define | I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) |
| #define | I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk |
| #define | I2C_ISR_ALERT_Pos (13U) |
| #define | I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) |
| #define | I2C_ISR_ALERT I2C_ISR_ALERT_Msk |
| #define | I2C_ISR_BUSY_Pos (15U) |
| #define | I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) |
| #define | I2C_ISR_BUSY I2C_ISR_BUSY_Msk |
| #define | I2C_ISR_DIR_Pos (16U) |
| #define | I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) |
| #define | I2C_ISR_DIR I2C_ISR_DIR_Msk |
| #define | I2C_ISR_ADDCODE_Pos (17U) |
| #define | I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) |
| #define | I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk |
| #define | I2C_ICR_ADDRCF_Pos (3U) |
| #define | I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) |
| #define | I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk |
| #define | I2C_ICR_NACKCF_Pos (4U) |
| #define | I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) |
| #define | I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk |
| #define | I2C_ICR_STOPCF_Pos (5U) |
| #define | I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) |
| #define | I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk |
| #define | I2C_ICR_BERRCF_Pos (8U) |
| #define | I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) |
| #define | I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk |
| #define | I2C_ICR_ARLOCF_Pos (9U) |
| #define | I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) |
| #define | I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk |
| #define | I2C_ICR_OVRCF_Pos (10U) |
| #define | I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) |
| #define | I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk |
| #define | I2C_ICR_PECCF_Pos (11U) |
| #define | I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) |
| #define | I2C_ICR_PECCF I2C_ICR_PECCF_Msk |
| #define | I2C_ICR_TIMOUTCF_Pos (12U) |
| #define | I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) |
| #define | I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk |
| #define | I2C_ICR_ALERTCF_Pos (13U) |
| #define | I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) |
| #define | I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk |
| #define | I2C_PECR_PEC_Pos (0U) |
| #define | I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) |
| #define | I2C_PECR_PEC I2C_PECR_PEC_Msk |
| #define | I2C_RXDR_RXDATA_Pos (0U) |
| #define | I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) |
| #define | I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk |
| #define | I2C_TXDR_TXDATA_Pos (0U) |
| #define | I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) |
| #define | I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk |
| #define | I2C_AUTOCR_TCDMAEN_Pos (6U) |
| #define | I2C_AUTOCR_TCDMAEN_Msk (0x1UL << I2C_AUTOCR_TCDMAEN_Pos) |
| #define | I2C_AUTOCR_TCDMAEN I2C_AUTOCR_TCDMAEN_Msk |
| #define | I2C_AUTOCR_TCRDMAEN_Pos (7U) |
| #define | I2C_AUTOCR_TCRDMAEN_Msk (0x1UL << I2C_AUTOCR_TCRDMAEN_Pos) |
| #define | I2C_AUTOCR_TCRDMAEN I2C_AUTOCR_TCRDMAEN_Msk |
| #define | I2C_AUTOCR_TRIGSEL_Pos (16U) |
| #define | I2C_AUTOCR_TRIGSEL_Msk (0xFUL << I2C_AUTOCR_TRIGSEL_Pos) |
| #define | I2C_AUTOCR_TRIGSEL I2C_AUTOCR_TRIGSEL_Msk |
| #define | I2C_AUTOCR_TRIGPOL_Pos (20U) |
| #define | I2C_AUTOCR_TRIGPOL_Msk (0x1UL << I2C_AUTOCR_TRIGPOL_Pos) |
| #define | I2C_AUTOCR_TRIGPOL I2C_AUTOCR_TRIGPOL_Msk |
| #define | I2C_AUTOCR_TRIGEN_Pos (21U) |
| #define | I2C_AUTOCR_TRIGEN_Msk (0x1UL << I2C_AUTOCR_TRIGEN_Pos) |
| #define | I2C_AUTOCR_TRIGEN I2C_AUTOCR_TRIGEN_Msk |
| #define | IWDG_KR_KEY_Pos (0U) |
| #define | IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) |
| #define | IWDG_KR_KEY IWDG_KR_KEY_Msk |
| #define | IWDG_PR_PR_Pos (0U) |
| #define | IWDG_PR_PR_Msk (0xFUL << IWDG_PR_PR_Pos) |
| #define | IWDG_PR_PR IWDG_PR_PR_Msk |
| #define | IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) |
| #define | IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) |
| #define | IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) |
| #define | IWDG_PR_PR_3 (0x8UL << IWDG_PR_PR_Pos) |
| #define | IWDG_RLR_RL_Pos (0U) |
| #define | IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) |
| #define | IWDG_RLR_RL IWDG_RLR_RL_Msk |
| #define | IWDG_SR_PVU_Pos (0U) |
| #define | IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) |
| #define | IWDG_SR_PVU IWDG_SR_PVU_Msk |
| #define | IWDG_SR_RVU_Pos (1U) |
| #define | IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) |
| #define | IWDG_SR_RVU IWDG_SR_RVU_Msk |
| #define | IWDG_SR_WVU_Pos (2U) |
| #define | IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) |
| #define | IWDG_SR_WVU IWDG_SR_WVU_Msk |
| #define | IWDG_SR_EWU_Pos (3U) |
| #define | IWDG_SR_EWU_Msk (0x1UL << IWDG_SR_EWU_Pos) |
| #define | IWDG_SR_EWU IWDG_SR_EWU_Msk |
| #define | IWDG_SR_EWIF_Pos (14U) |
| #define | IWDG_SR_EWIF_Msk (0x1UL << IWDG_SR_EWIF_Pos) |
| #define | IWDG_SR_EWIF IWDG_SR_EWIF_Msk |
| #define | IWDG_WINR_WIN_Pos (0U) |
| #define | IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) |
| #define | IWDG_WINR_WIN IWDG_WINR_WIN_Msk |
| #define | IWDG_EWCR_EWIT_Pos (0U) |
| #define | IWDG_EWCR_EWIT_Msk (0xFFFUL << IWDG_EWCR_EWIT_Pos) |
| #define | IWDG_EWCR_EWIT IWDG_EWCR_EWIT_Msk |
| #define | IWDG_EWCR_EWIC_Pos (14U) |
| #define | IWDG_EWCR_EWIC_Msk (0x1UL << IWDG_EWCR_EWIC_Pos) |
| #define | IWDG_EWCR_EWIC IWDG_EWCR_EWIC_Msk |
| #define | IWDG_EWCR_EWIE_Pos (15U) |
| #define | IWDG_EWCR_EWIE_Msk (0x1UL << IWDG_EWCR_EWIE_Pos) |
| #define | IWDG_EWCR_EWIE IWDG_EWCR_EWIE_Msk |
| #define | SPI_CR1_SPE_Pos (0U) |
| #define | SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) |
| #define | SPI_CR1_SPE SPI_CR1_SPE_Msk |
| #define | SPI_CR1_MASRX_Pos (8U) |
| #define | SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos) |
| #define | SPI_CR1_MASRX SPI_CR1_MASRX_Msk |
| #define | SPI_CR1_CSTART_Pos (9U) |
| #define | SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos) |
| #define | SPI_CR1_CSTART SPI_CR1_CSTART_Msk |
| #define | SPI_CR1_CSUSP_Pos (10U) |
| #define | SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos) |
| #define | SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk |
| #define | SPI_CR1_HDDIR_Pos (11U) |
| #define | SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos) |
| #define | SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk |
| #define | SPI_CR1_SSI_Pos (12U) |
| #define | SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) |
| #define | SPI_CR1_SSI SPI_CR1_SSI_Msk |
| #define | SPI_CR1_CRC33_17_Pos (13U) |
| #define | SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos) |
| #define | SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk |
| #define | SPI_CR1_RCRCINI_Pos (14U) |
| #define | SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos) |
| #define | SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk |
| #define | SPI_CR1_TCRCINI_Pos (15U) |
| #define | SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos) |
| #define | SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk |
| #define | SPI_CR1_IOLOCK_Pos (16U) |
| #define | SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos) |
| #define | SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk |
| #define | SPI_CR2_TSIZE_Pos (0U) |
| #define | SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos) |
| #define | SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk |
| #define | SPI_CFG1_DSIZE_Pos (0U) |
| #define | SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos) |
| #define | SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk |
| #define | SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos) |
| #define | SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos) |
| #define | SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos) |
| #define | SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos) |
| #define | SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos) |
| #define | SPI_CFG1_FTHLV_Pos (5U) |
| #define | SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos) |
| #define | SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk |
| #define | SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos) |
| #define | SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos) |
| #define | SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos) |
| #define | SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos) |
| #define | SPI_CFG1_UDRCFG_Pos (9U) |
| #define | SPI_CFG1_UDRCFG_Msk (0x1UL << SPI_CFG1_UDRCFG_Pos) |
| #define | SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk |
| #define | SPI_CFG1_RXDMAEN_Pos (14U) |
| #define | SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos) |
| #define | SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk |
| #define | SPI_CFG1_TXDMAEN_Pos (15U) |
| #define | SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos) |
| #define | SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk |
| #define | SPI_CFG1_CRCSIZE_Pos (16U) |
| #define | SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos) |
| #define | SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk |
| #define | SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos) |
| #define | SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos) |
| #define | SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos) |
| #define | SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos) |
| #define | SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos) |
| #define | SPI_CFG1_CRCEN_Pos (22U) |
| #define | SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos) |
| #define | SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk |
| #define | SPI_CFG1_MBR_Pos (28U) |
| #define | SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos) |
| #define | SPI_CFG1_MBR SPI_CFG1_MBR_Msk |
| #define | SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos) |
| #define | SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos) |
| #define | SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos) |
| #define | SPI_CFG1_BPASS_Pos (31U) |
| #define | SPI_CFG1_BPASS_Msk (0x1UL << SPI_CFG1_BPASS_Pos) |
| #define | SPI_CFG1_BPASS SPI_CFG1_BPASS_Msk |
| #define | SPI_CFG2_MSSI_Pos (0U) |
| #define | SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos) |
| #define | SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk |
| #define | SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos) |
| #define | SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos) |
| #define | SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos) |
| #define | SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos) |
| #define | SPI_CFG2_MIDI_Pos (4U) |
| #define | SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos) |
| #define | SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk |
| #define | SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos) |
| #define | SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos) |
| #define | SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos) |
| #define | SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos) |
| #define | SPI_CFG2_RDIMM_Pos (13U) |
| #define | SPI_CFG2_RDIMM_Msk (0x1UL << SPI_CFG2_RDIMM_Pos) |
| #define | SPI_CFG2_RDIMM SPI_CFG2_RDIMM_Msk |
| #define | SPI_CFG2_RDIOP_Pos (14U) |
| #define | SPI_CFG2_RDIOP_Msk (0x1UL << SPI_CFG2_RDIOP_Pos) |
| #define | SPI_CFG2_RDIOP SPI_CFG2_RDIOP_Msk |
| #define | SPI_CFG2_IOSWP_Pos (15U) |
| #define | SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos) |
| #define | SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk |
| #define | SPI_CFG2_COMM_Pos (17U) |
| #define | SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos) |
| #define | SPI_CFG2_COMM SPI_CFG2_COMM_Msk |
| #define | SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos) |
| #define | SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos) |
| #define | SPI_CFG2_SP_Pos (19U) |
| #define | SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos) |
| #define | SPI_CFG2_SP SPI_CFG2_SP_Msk |
| #define | SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos) |
| #define | SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos) |
| #define | SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos) |
| #define | SPI_CFG2_MASTER_Pos (22U) |
| #define | SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos) |
| #define | SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk |
| #define | SPI_CFG2_LSBFRST_Pos (23U) |
| #define | SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos) |
| #define | SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk |
| #define | SPI_CFG2_CPHA_Pos (24U) |
| #define | SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos) |
| #define | SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk |
| #define | SPI_CFG2_CPOL_Pos (25U) |
| #define | SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos) |
| #define | SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk |
| #define | SPI_CFG2_SSM_Pos (26U) |
| #define | SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos) |
| #define | SPI_CFG2_SSM SPI_CFG2_SSM_Msk |
| #define | SPI_CFG2_SSIOP_Pos (28U) |
| #define | SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos) |
| #define | SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk |
| #define | SPI_CFG2_SSOE_Pos (29U) |
| #define | SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos) |
| #define | SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk |
| #define | SPI_CFG2_SSOM_Pos (30U) |
| #define | SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos) |
| #define | SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk |
| #define | SPI_CFG2_AFCNTR_Pos (31U) |
| #define | SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos) |
| #define | SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk |
| #define | SPI_IER_RXPIE_Pos (0U) |
| #define | SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos) |
| #define | SPI_IER_RXPIE SPI_IER_RXPIE_Msk |
| #define | SPI_IER_TXPIE_Pos (1U) |
| #define | SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos) |
| #define | SPI_IER_TXPIE SPI_IER_TXPIE_Msk |
| #define | SPI_IER_DXPIE_Pos (2U) |
| #define | SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos) |
| #define | SPI_IER_DXPIE SPI_IER_DXPIE_Msk |
| #define | SPI_IER_EOTIE_Pos (3U) |
| #define | SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos) |
| #define | SPI_IER_EOTIE SPI_IER_EOTIE_Msk |
| #define | SPI_IER_TXTFIE_Pos (4U) |
| #define | SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos) |
| #define | SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk |
| #define | SPI_IER_UDRIE_Pos (5U) |
| #define | SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos) |
| #define | SPI_IER_UDRIE SPI_IER_UDRIE_Msk |
| #define | SPI_IER_OVRIE_Pos (6U) |
| #define | SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos) |
| #define | SPI_IER_OVRIE SPI_IER_OVRIE_Msk |
| #define | SPI_IER_CRCEIE_Pos (7U) |
| #define | SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos) |
| #define | SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk |
| #define | SPI_IER_TIFREIE_Pos (8U) |
| #define | SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos) |
| #define | SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk |
| #define | SPI_IER_MODFIE_Pos (9U) |
| #define | SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos) |
| #define | SPI_IER_MODFIE SPI_IER_MODFIE_Msk |
| #define | SPI_SR_RXP_Pos (0U) |
| #define | SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos) |
| #define | SPI_SR_RXP SPI_SR_RXP_Msk |
| #define | SPI_SR_TXP_Pos (1U) |
| #define | SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos) |
| #define | SPI_SR_TXP SPI_SR_TXP_Msk |
| #define | SPI_SR_DXP_Pos (2U) |
| #define | SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos) |
| #define | SPI_SR_DXP SPI_SR_DXP_Msk |
| #define | SPI_SR_EOT_Pos (3U) |
| #define | SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos) |
| #define | SPI_SR_EOT SPI_SR_EOT_Msk |
| #define | SPI_SR_TXTF_Pos (4U) |
| #define | SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos) |
| #define | SPI_SR_TXTF SPI_SR_TXTF_Msk |
| #define | SPI_SR_UDR_Pos (5U) |
| #define | SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) |
| #define | SPI_SR_UDR SPI_SR_UDR_Msk |
| #define | SPI_SR_OVR_Pos (6U) |
| #define | SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) |
| #define | SPI_SR_OVR SPI_SR_OVR_Msk |
| #define | SPI_SR_CRCE_Pos (7U) |
| #define | SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos) |
| #define | SPI_SR_CRCE SPI_SR_CRCE_Msk |
| #define | SPI_SR_TIFRE_Pos (8U) |
| #define | SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos) |
| #define | SPI_SR_TIFRE SPI_SR_TIFRE_Msk |
| #define | SPI_SR_MODF_Pos (9U) |
| #define | SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) |
| #define | SPI_SR_MODF SPI_SR_MODF_Msk |
| #define | SPI_SR_SUSP_Pos (11U) |
| #define | SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos) |
| #define | SPI_SR_SUSP SPI_SR_SUSP_Msk |
| #define | SPI_SR_TXC_Pos (12U) |
| #define | SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos) |
| #define | SPI_SR_TXC SPI_SR_TXC_Msk |
| #define | SPI_SR_RXPLVL_Pos (13U) |
| #define | SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos) |
| #define | SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk |
| #define | SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos) |
| #define | SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos) |
| #define | SPI_SR_RXWNE_Pos (15U) |
| #define | SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos) |
| #define | SPI_SR_RXWNE SPI_SR_RXWNE_Msk |
| #define | SPI_SR_CTSIZE_Pos (16U) |
| #define | SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos) |
| #define | SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk |
| #define | SPI_IFCR_EOTC_Pos (3U) |
| #define | SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) |
| #define | SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk |
| #define | SPI_IFCR_TXTFC_Pos (4U) |
| #define | SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos) |
| #define | SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk |
| #define | SPI_IFCR_UDRC_Pos (5U) |
| #define | SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos) |
| #define | SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk |
| #define | SPI_IFCR_OVRC_Pos (6U) |
| #define | SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos) |
| #define | SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk |
| #define | SPI_IFCR_CRCEC_Pos (7U) |
| #define | SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos) |
| #define | SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk |
| #define | SPI_IFCR_TIFREC_Pos (8U) |
| #define | SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos) |
| #define | SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk |
| #define | SPI_IFCR_MODFC_Pos (9U) |
| #define | SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos) |
| #define | SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk |
| #define | SPI_IFCR_SUSPC_Pos (11U) |
| #define | SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos) |
| #define | SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk |
| #define | SPI_AUTOCR_TRIGSEL_Pos (16U) |
| #define | SPI_AUTOCR_TRIGSEL_Msk (0xFUL << SPI_AUTOCR_TRIGSEL_Pos) |
| #define | SPI_AUTOCR_TRIGSEL SPI_AUTOCR_TRIGSEL_Msk |
| #define | SPI_AUTOCR_TRIGSEL_0 (0x01UL << SPI_AUTOCR_TRIGSEL_Pos) |
| #define | SPI_AUTOCR_TRIGSEL_1 (0x02UL << SPI_AUTOCR_TRIGSEL_Pos) |
| #define | SPI_AUTOCR_TRIGSEL_2 (0x04UL << SPI_AUTOCR_TRIGSEL_Pos) |
| #define | SPI_AUTOCR_TRIGSEL_3 (0x08UL << SPI_AUTOCR_TRIGSEL_Pos) |
| #define | SPI_AUTOCR_TRIGPOL_Pos (20U) |
| #define | SPI_AUTOCR_TRIGPOL_Msk (0x1UL << SPI_AUTOCR_TRIGPOL_Pos) |
| #define | SPI_AUTOCR_TRIGPOL SPI_AUTOCR_TRIGPOL_Msk |
| #define | SPI_AUTOCR_TRIGEN_Pos (21U) |
| #define | SPI_AUTOCR_TRIGEN_Msk (0x1UL << SPI_AUTOCR_TRIGEN_Pos) |
| #define | SPI_AUTOCR_TRIGEN SPI_AUTOCR_TRIGEN_Msk |
| #define | SPI_TXDR_TXDR_Pos (0U) |
| #define | SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos) |
| #define | SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */ |
| #define | SPI_RXDR_RXDR_Pos (0U) |
| #define | SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos) |
| #define | SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */ |
| #define | SPI_CRCPOLY_CRCPOLY_Pos (0U) |
| #define | SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) |
| #define | SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */ |
| #define | SPI_TXCRC_TXCRC_Pos (0U) |
| #define | SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos) |
| #define | SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */ |
| #define | SPI_RXCRC_RXCRC_Pos (0U) |
| #define | SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos) |
| #define | SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */ |
| #define | SPI_UDRDR_UDRDR_Pos (0U) |
| #define | SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos) |
| #define | SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */ |
| #define | VREFBUF_CSR_ENVR_Pos (0U) |
| #define | VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) |
| #define | VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk |
| #define | VREFBUF_CSR_HIZ_Pos (1U) |
| #define | VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) |
| #define | VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk |
| #define | VREFBUF_CSR_VRS_Pos (4U) |
| #define | VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) |
| #define | VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk |
| #define | VREFBUF_CSR_VRS_0 (0x01UL<< VREFBUF_CSR_VRS_Pos) |
| #define | VREFBUF_CSR_VRS_1 (0x02UL<< VREFBUF_CSR_VRS_Pos) |
| #define | VREFBUF_CSR_VRS_2 (0x04UL<< VREFBUF_CSR_VRS_Pos) |
| #define | VREFBUF_CSR_VRR_Pos (3U) |
| #define | VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) |
| #define | VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk |
| #define | VREFBUF_CCR_TRIM_Pos (0U) |
| #define | VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) |
| #define | VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk |
| #define | WWDG_CR_T_Pos (0U) |
| #define | WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) |
| #define | WWDG_CR_T WWDG_CR_T_Msk |
| #define | WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) |
| #define | WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) |
| #define | WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) |
| #define | WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) |
| #define | WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) |
| #define | WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) |
| #define | WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) |
| #define | WWDG_CR_WDGA_Pos (7U) |
| #define | WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) |
| #define | WWDG_CR_WDGA WWDG_CR_WDGA_Msk |
| #define | WWDG_CFR_W_Pos (0U) |
| #define | WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) |
| #define | WWDG_CFR_W WWDG_CFR_W_Msk |
| #define | WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) |
| #define | WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) |
| #define | WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) |
| #define | WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) |
| #define | WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) |
| #define | WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) |
| #define | WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) |
| #define | WWDG_CFR_WDGTB_Pos (11U) |
| #define | WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) |
| #define | WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk |
| #define | WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) |
| #define | WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) |
| #define | WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) |
| #define | WWDG_CFR_EWI_Pos (9U) |
| #define | WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) |
| #define | WWDG_CFR_EWI WWDG_CFR_EWI_Msk |
| #define | WWDG_SR_EWIF_Pos (0U) |
| #define | WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) |
| #define | WWDG_SR_EWIF WWDG_SR_EWIF_Msk |
| #define | PKA_CR_EN_Pos (0U) |
| #define | PKA_CR_EN_Msk (0x1UL << PKA_CR_EN_Pos) |
| #define | PKA_CR_EN PKA_CR_EN_Msk |
| #define | PKA_CR_START_Pos (1U) |
| #define | PKA_CR_START_Msk (0x1UL << PKA_CR_START_Pos) |
| #define | PKA_CR_START PKA_CR_START_Msk |
| #define | PKA_CR_MODE_Pos (8U) |
| #define | PKA_CR_MODE_Msk (0x3FUL << PKA_CR_MODE_Pos) |
| #define | PKA_CR_MODE PKA_CR_MODE_Msk |
| #define | PKA_CR_MODE_0 (0x01UL << PKA_CR_MODE_Pos) |
| #define | PKA_CR_MODE_1 (0x02UL << PKA_CR_MODE_Pos) |
| #define | PKA_CR_MODE_2 (0x04UL << PKA_CR_MODE_Pos) |
| #define | PKA_CR_MODE_3 (0x08UL << PKA_CR_MODE_Pos) |
| #define | PKA_CR_MODE_4 (0x10UL << PKA_CR_MODE_Pos) |
| #define | PKA_CR_MODE_5 (0x20UL << PKA_CR_MODE_Pos) |
| #define | PKA_CR_PROCENDIE_Pos (17U) |
| #define | PKA_CR_PROCENDIE_Msk (0x1UL << PKA_CR_PROCENDIE_Pos) |
| #define | PKA_CR_PROCENDIE PKA_CR_PROCENDIE_Msk |
| #define | PKA_CR_RAMERRIE_Pos (19U) |
| #define | PKA_CR_RAMERRIE_Msk (0x1UL << PKA_CR_RAMERRIE_Pos) |
| #define | PKA_CR_RAMERRIE PKA_CR_RAMERRIE_Msk |
| #define | PKA_CR_ADDRERRIE_Pos (20U) |
| #define | PKA_CR_ADDRERRIE_Msk (0x1UL << PKA_CR_ADDRERRIE_Pos) |
| #define | PKA_CR_ADDRERRIE PKA_CR_ADDRERRIE_Msk |
| #define | PKA_CR_OPERRIE_Pos (21U) |
| #define | PKA_CR_OPERRIE_Msk (0x1UL << PKA_CR_OPERRIE_Pos) |
| #define | PKA_CR_OPERRIE PKA_CR_OPERRIE_Msk |
| #define | PKA_SR_INITOK_Pos (0U) |
| #define | PKA_SR_INITOK_Msk (0x1UL << PKA_SR_INITOK_Pos) |
| #define | PKA_SR_INITOK PKA_SR_INITOK_Msk |
| #define | PKA_SR_BUSY_Pos (16U) |
| #define | PKA_SR_BUSY_Msk (0x1UL << PKA_SR_BUSY_Pos) |
| #define | PKA_SR_BUSY PKA_SR_BUSY_Msk |
| #define | PKA_SR_PROCENDF_Pos (17U) |
| #define | PKA_SR_PROCENDF_Msk (0x1UL << PKA_SR_PROCENDF_Pos) |
| #define | PKA_SR_PROCENDF PKA_SR_PROCENDF_Msk |
| #define | PKA_SR_RAMERRF_Pos (19U) |
| #define | PKA_SR_RAMERRF_Msk (0x1UL << PKA_SR_RAMERRF_Pos) |
| #define | PKA_SR_RAMERRF PKA_SR_RAMERRF_Msk |
| #define | PKA_SR_ADDRERRF_Pos (20U) |
| #define | PKA_SR_ADDRERRF_Msk (0x1UL << PKA_SR_ADDRERRF_Pos) |
| #define | PKA_SR_ADDRERRF PKA_SR_ADDRERRF_Msk |
| #define | PKA_SR_OPERRF_Pos (21U) |
| #define | PKA_SR_OPERRF_Msk (0x1UL << PKA_SR_OPERRF_Pos) |
| #define | PKA_SR_OPERRF PKA_SR_OPERRF_Msk |
| #define | PKA_CLRFR_PROCENDFC_Pos (17U) |
| #define | PKA_CLRFR_PROCENDFC_Msk (0x1UL << PKA_CLRFR_PROCENDFC_Pos) |
| #define | PKA_CLRFR_PROCENDFC PKA_CLRFR_PROCENDFC_Msk |
| #define | PKA_CLRFR_RAMERRFC_Pos (19U) |
| #define | PKA_CLRFR_RAMERRFC_Msk (0x1UL << PKA_CLRFR_RAMERRFC_Pos) |
| #define | PKA_CLRFR_RAMERRFC PKA_CLRFR_RAMERRFC_Msk |
| #define | PKA_CLRFR_ADDRERRFC_Pos (20U) |
| #define | PKA_CLRFR_ADDRERRFC_Msk (0x1UL << PKA_CLRFR_ADDRERRFC_Pos) |
| #define | PKA_CLRFR_ADDRERRFC PKA_CLRFR_ADDRERRFC_Msk |
| #define | PKA_CLRFR_OPERRFC_Pos (21U) |
| #define | PKA_CLRFR_OPERRFC_Msk (0x1UL << PKA_CLRFR_OPERRFC_Pos) |
| #define | PKA_CLRFR_OPERRFC PKA_CLRFR_OPERRFC_Msk |
| #define | PKA_RAM_OFFSET (0x0400UL) |
| #define | PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) |
| #define | PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| #define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| #define | IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) |
| #define | IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) |
| #define | IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S)) |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| #define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) |
| #define | IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) |
| #define | IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) |
| #define | IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| #define | IS_GPDMA_INSTANCE(INSTANCE) |
| #define | IS_LPDMA_INSTANCE(INSTANCE) |
| #define | IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) |
| #define | IS_OTFDEC_ALL_INSTANCE(INSTANCE) |
| #define | IS_RAMCFG_ALL_INSTANCE(INSTANCE) |
| #define | IS_RAMCFG_ECC_INSTANCE(INSTANCE) |
| #define | IS_RAMCFG_IT_INSTANCE(INSTANCE) |
| #define | IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) |
| #define | IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) |
| #define | IS_GFXMMU_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXMMU_NS) || ((INSTANCE) == GFXMMU_S)) |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| #define | IS_LPGPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) |
| #define | IS_LTDC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == LTDC_NS) || ((__INSTANCE__) == LTDC_S)) |
| #define | IS_DSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DSI_NS) || ((__INSTANCE__) == DSI_S)) |
| #define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA2D_NS) || ((__INSTANCE__) == DMA2D_S)) |
| #define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) |
| #define | IS_DCACHE_ALL_INSTANCE(INSTANCE) |
| #define | IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) |
| #define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| #define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| #define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| #define | IS_I2C_GRP1_INSTANCE(INSTANCE) |
| #define | IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| #define | IS_OSPI_ALL_INSTANCE(INSTANCE) |
| #define | IS_HSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HSPI1_NS) || ((INSTANCE) == HSPI1_S)) |
| #define | IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) |
| #define | IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| #define | IS_SDMMC_ALL_INSTANCE(INSTANCE) |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| #define | IS_SMBUS_GRP1_INSTANCE(INSTANCE) |
| #define | IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| #define | IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) |
| #define | IS_SPI_FULL_INSTANCE(INSTANCE) |
| #define | IS_SPI_GRP1_INSTANCE(INSTANCE) |
| #define | IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| #define | IS_LPTIM_DMA_INSTANCE(INSTANCE) |
| #define | IS_LPTIM_CC1_INSTANCE(INSTANCE) |
| #define | IS_LPTIM_CC2_INSTANCE(INSTANCE) |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| #define | IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| #define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| #define | IS_TIM_HSE32_INSTANCE(INSTANCE) |
| #define | IS_TIM_ADVANCED_INSTANCE(INSTANCE) |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| #define | IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) |
| #define | IS_USART_INSTANCE(INSTANCE) |
| #define | IS_UART_INSTANCE(INSTANCE) |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| #define | IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) |
| #define | IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) |
| #define | IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) |
| #define | IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) |
| #define | IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) |
| #define | IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) |
| #define | IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) |
| #define | IS_MDF_ALL_INSTANCE(INSTANCE) |
| #define | IS_GPU2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPU2D_BASE_NS) || ((__INSTANCE__) == GPU2D_BASE_S)) |
| #define | IS_JPEG_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == JPEG_NS) || ((__INSTANCE__) == JPEG_S)) |
| #define | IS_GFXTIM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GFXTIM_NS) || ((__INSTANCE__) == GFXTIM_S)) |
Typedefs | |
| typedef XSPI_TypeDef | OCTOSPI_TypeDef |
| typedef XSPI_TypeDef | HSPI_TypeDef |
| typedef XSPIM_TypeDef | OCTOSPIM_TypeDef |
| typedef uint32_t(* | RSSLIB_S_CloseExitHDP_TypeDef) (uint32_t HdpArea, uint32_t VectorTableAddr) |
| Prototype of RSSLIB Close and exit HDP Function @detail This function close the requested hdp area passed in input parameter and jump to the reset handler present within the Vector table. The function does not return on successful execution. | |
CMSIS STM32U5G9xx Device Peripheral Access Layer Header File.
Copyright (c) 2023 STMicroelectronics. All rights reserved.
This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.
1.9.6