MIPI DSI D-PHY configuration. More...

#include <fsl_mipi_dsi.h>

Data Fields
uint32_t	txHsBitClk_Hz

uint8_t	tClkPre_ByteClk

uint8_t	tClkPost_ByteClk

uint8_t	tHsExit_ByteClk

uint32_t	tWakeup_EscClk

uint8_t	tHsPrepare_HalfEscClk

uint8_t	tClkPrepare_HalfEscClk

uint8_t	tHsZero_ByteClk

uint8_t	tClkZero_ByteClk

uint8_t	tHsTrail_ByteClk

uint8_t	tClkTrail_ByteClk

Detailed Description

MIPI DSI D-PHY configuration.

Field Documentation

◆ tClkPost_ByteClk

uint8_t _dsi_dphy_config::tClkPost_ByteClk

TCLK-POST + T_CLK-TRAIL in byte clock. Set how long the controller will wait before putting clock lane into LP mode after data lanes detected in stop state.

◆ tClkPre_ByteClk

uint8_t _dsi_dphy_config::tClkPre_ByteClk

TLPX + TCLK-PREPARE + TCLK-ZERO + TCLK-PRE in byte clock. Set how long the controller will wait after enabling clock lane for HS before enabling data lanes for HS.

◆ tClkPrepare_HalfEscClk

uint8_t _dsi_dphy_config::tClkPrepare_HalfEscClk

TCLK-PREPARE in clk_esc/2. Set how long to drive the LP-00 state before HS transmissions, available values are 2, 3.

◆ tClkTrail_ByteClk

uint8_t _dsi_dphy_config::tClkTrail_ByteClk

TCLK-TRAIL + 4*UI in clk_byte. Set the time of the flipped differential state after last payload data bit of HS transmission burst. Available values are 0, 1, ..., 15.

◆ tClkZero_ByteClk

uint8_t _dsi_dphy_config::tClkZero_ByteClk

TCLK-ZERO in clk_byte. Set how long that controller drives clock lane HS-0 state before transmit the Sync sequence. Available values are 3, 4, ..., 66.

◆ tHsExit_ByteClk

uint8_t _dsi_dphy_config::tHsExit_ByteClk

THS-EXIT in byte clock. Set how long the controller will wait after the clock lane has been put into LP mode before enabling clock lane for HS again.

◆ tHsPrepare_HalfEscClk

uint8_t _dsi_dphy_config::tHsPrepare_HalfEscClk

THS-PREPARE in clk_esc/2. Set how long to drive the LP-00 state before HS transmissions, available values are 2, 3, 4, 5.

◆ tHsTrail_ByteClk

uint8_t _dsi_dphy_config::tHsTrail_ByteClk

THS-TRAIL + 4*UI in clk_byte. Set the time of the flipped differential state after last payload data bit of HS transmission burst. Available values are 0, 1, ..., 15.

◆ tHsZero_ByteClk

uint8_t _dsi_dphy_config::tHsZero_ByteClk

THS-ZERO in clk_byte. Set how long that controller drives data lane HS-0 state before transmit the Sync sequence. Available values are 6, 7, ..., 37.

◆ tWakeup_EscClk

uint32_t _dsi_dphy_config::tWakeup_EscClk

Number of clk_esc clock periods to keep a clock or data lane in Mark-1 state after exiting ULPS.

◆ txHsBitClk_Hz

uint32_t _dsi_dphy_config::txHsBitClk_Hz

The generated HS TX bit clock in Hz.

The documentation for this struct was generated from the following file:

bsps/arm/imxrt/mcux-sdk/drivers/mipi_dsi_split/fsl_mipi_dsi.h

Data Fields