fsl_mipi_dsi.h

/*
 * Copyright 2020-2022 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef _FSL_MIPI_DSI_H_
#define _FSL_MIPI_DSI_H_
 
#include "fsl_common.h"
 
/*******************************************************************************
 * Definitions
 ******************************************************************************/
 
#define FSL_MIPI_DSI_DRIVER_VERSION (MAKE_VERSION(2, 2, 3))
/* The max APB transfer size. */
#define FSL_DSI_TX_MAX_PAYLOAD_BYTE (64U * 4U)
#define FSL_DSI_RX_MAX_PAYLOAD_BYTE (64U * 4U)
 
typedef struct
{
    DSI_HOST_Type *host;                        
    DSI_HOST_APB_PKT_IF_Type *apb;              
    DSI_HOST_DPI_INTFC_Type *dpi;               
    DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type *dphy; 
} MIPI_DSI_Type;
 
enum
{
    kStatus_DSI_Busy        = MAKE_STATUS((int32_t)kStatusGroup_MIPI_DSI, 0), 
    kStatus_DSI_RxDataError = MAKE_STATUS((int32_t)kStatusGroup_MIPI_DSI, 1), 
    kStatus_DSI_ErrorReportReceived =
        MAKE_STATUS((int32_t)kStatusGroup_MIPI_DSI, 2),                        
    kStatus_DSI_NotSupported = MAKE_STATUS((int32_t)kStatusGroup_MIPI_DSI, 3), 
};
 
typedef struct _dsi_config
{
    uint8_t numLanes;              
    bool enableNonContinuousHsClk; 
    bool enableTxUlps;             
    bool autoInsertEoTp;           
    uint8_t numExtraEoTp;          
    uint32_t htxTo_ByteClk;        
    uint32_t lrxHostTo_ByteClk;    
    uint32_t btaTo_ByteClk;        
} dsi_config_t;
 
typedef enum _dsi_dpi_color_coding
{
    kDSI_Dpi16BitConfig1 = 0U, 
    kDSI_Dpi16BitConfig2 = 1U, 
    kDSI_Dpi16BitConfig3 = 2U, 
    kDSI_Dpi18BitConfig1 = 3U, 
    kDSI_Dpi18BitConfig2 = 4U, 
    kDSI_Dpi24Bit        = 5U, 
} dsi_dpi_color_coding_t;
 
typedef enum _dsi_dpi_pixel_packet
{
    kDSI_PixelPacket16Bit        = 0U, 
    kDSI_PixelPacket18Bit        = 1U, 
    kDSI_PixelPacket18BitLoosely = 2U, 
    kDSI_PixelPacket24Bit        = 3U, 
} dsi_dpi_pixel_packet_t;
 
enum
{
    kDSI_DpiVsyncActiveLow  = 0U,         
    kDSI_DpiHsyncActiveLow  = 0U,         
    kDSI_DpiVsyncActiveHigh = (1U << 0U), 
    kDSI_DpiHsyncActiveHigh = (1U << 1U), 
};
 
typedef enum _dsi_dpi_video_mode
{
    kDSI_DpiNonBurstWithSyncPulse = 0U, 
    kDSI_DpiNonBurstWithSyncEvent = 1U, 
    kDSI_DpiBurst                 = 2U, 
} dsi_dpi_video_mode_t;
 
typedef enum _dsi_dpi_bllp_mode
{
    kDSI_DpiBllpLowPower, 
    kDSI_DpiBllpBlanking, 
    kDSI_DpiBllpNull,     
} dsi_dpi_bllp_mode_t;
 
typedef struct _dsi_dpi_config
{
    uint16_t pixelPayloadSize;             
    dsi_dpi_color_coding_t dpiColorCoding; 
    dsi_dpi_pixel_packet_t pixelPacket;    
    dsi_dpi_video_mode_t videoMode; 
    dsi_dpi_bllp_mode_t bllpMode;   
    uint8_t polarityFlags; 
    uint16_t hfp;          
    uint16_t hbp;          
    uint16_t hsw;          
    uint8_t vfp;           
    uint8_t vbp;           
    uint16_t panelHeight;  
    uint8_t virtualChannel; 
} dsi_dpi_config_t;
 
typedef struct _dsi_dphy_config
{
    uint32_t txHsBitClk_Hz; 
    uint8_t tClkPre_ByteClk;        
    uint8_t tClkPost_ByteClk;       
    uint8_t tHsExit_ByteClk;        
    uint32_t tWakeup_EscClk;        
    uint8_t tHsPrepare_HalfEscClk;  
    uint8_t tClkPrepare_HalfEscClk; 
    uint8_t tHsZero_ByteClk;        
    uint8_t tClkZero_ByteClk;       
    uint8_t tHsTrail_ByteClk;       
    uint8_t tClkTrail_ByteClk;      
} dsi_dphy_config_t;
 
enum
{
    kDSI_ApbNotIdle          = (1UL << 0U), 
    kDSI_ApbTxDone           = (1UL << 1U), 
    kDSI_ApbRxControl        = (1UL << 2U), 
    kDSI_ApbTxOverflow       = (1UL << 3U), 
    kDSI_ApbTxUnderflow      = (1UL << 4U), 
    kDSI_ApbRxOverflow       = (1UL << 5U), 
    kDSI_ApbRxUnderflow      = (1UL << 6U), 
    kDSI_ApbRxHeaderReceived = (1UL << 7U), 
    kDSI_ApbRxPacketReceived = (1UL << 8U), 
};
 
enum
{
    kDSI_RxErrorEccOneBit   = (1UL << 0U), 
    kDSI_RxErrorEccMultiBit = (1UL << 1U), 
    kDSI_RxErrorCrc         = (1UL << 7U), 
    kDSI_RxErrorHtxTo       = (1UL << 8U), 
    kDSI_RxErrorLrxTo       = (1UL << 9U), 
    kDSI_RxErrorBtaTo       = (1UL << 10U) 
};
 
enum _dsi_host_status
{
    kDSI_HostSoTError           = (1UL << 0U), 
    kDSI_HostSoTSyncError       = (1UL << 1U), 
    kDSI_HostEoTSyncError       = (1UL << 2U), 
    kDSI_HostEscEntryCmdError   = (1UL << 3U), 
    kDSI_HostLpTxSyncError      = (1UL << 4U), 
    kDSI_HostPeriphToError      = (1UL << 5U), 
    kDSI_HostFalseControlError  = (1UL << 6U), 
    kDSI_HostContentionDetected = (1UL << 7U), 
    kDSI_HostEccErrorOneBit     = (1UL << 8U), 
    kDSI_HostEccErrorMultiBit   = (1UL << 9U), 
    kDSI_HostChecksumError      = (1UL << 10U),   
    kDSI_HostInvalidDataType    = (1UL << 11U),   
    kDSI_HostInvalidVcId        = (1UL << 12U),   
    kDSI_HostInvalidTxLength    = (1UL << 13U),   
    kDSI_HostProtocalViolation  = (1UL << 15U),   
    kDSI_HostResetTriggerReceived = (1UL << 16U), 
    kDSI_HostTearTriggerReceived  = (1UL << 17U), 
    kDSI_HostAckTriggerReceived   = (1UL << 18U), 
};
 
enum
{
    kDSI_InterruptGroup1ApbNotIdle          = (1UL << 0U),   
    kDSI_InterruptGroup1ApbTxDone           = (1UL << 1U),   
    kDSI_InterruptGroup1ApbRxControl        = (1UL << 2U),   
    kDSI_InterruptGroup1ApbTxOverflow       = (1UL << 3U),   
    kDSI_InterruptGroup1ApbTxUnderflow      = (1UL << 4U),   
    kDSI_InterruptGroup1ApbRxOverflow       = (1UL << 5U),   
    kDSI_InterruptGroup1ApbRxUnderflow      = (1UL << 6U),   
    kDSI_InterruptGroup1ApbRxHeaderReceived = (1UL << 7U),   
    kDSI_InterruptGroup1ApbRxPacketReceived = (1UL << 8U),   
    kDSI_InterruptGroup1SoTError            = (1UL << 9U),   
    kDSI_InterruptGroup1SoTSyncError        = (1UL << 10U),  
    kDSI_InterruptGroup1EoTSyncError        = (1UL << 11U),  
    kDSI_InterruptGroup1EscEntryCmdError    = (1UL << 12U),  
    kDSI_InterruptGroup1LpTxSyncError = (1UL << 13U),        
    kDSI_InterruptGroup1PeriphToError = (1UL << 14U),        
    kDSI_InterruptGroup1FalseControlError  = (1UL << 15U),   
    kDSI_InterruptGroup1ContentionDetected = (1UL << 16U),   
    kDSI_InterruptGroup1EccErrorOneBit     = (1UL << 17U),   
    kDSI_InterruptGroup1EccErrorMultiBit = (1UL << 18U),     
    kDSI_InterruptGroup1ChecksumError        = (1UL << 19U), 
    kDSI_InterruptGroup1InvalidDataType      = (1UL << 20U), 
    kDSI_InterruptGroup1InvalidVcId          = (1UL << 21U), 
    kDSI_InterruptGroup1InvalidTxLength      = (1UL << 22U), 
    kDSI_InterruptGroup1ProtocalViolation    = (1UL << 24U), 
    kDSI_InterruptGroup1ResetTriggerReceived = (1UL << 25U), 
    kDSI_InterruptGroup1TearTriggerReceived  = (1UL << 26U), 
    kDSI_InterruptGroup1AckTriggerReceived   = (1UL << 27U), 
    kDSI_InterruptGroup1HtxTo                = (1UL << 29U), 
    kDSI_InterruptGroup1LrxTo                = (1UL << 30U), 
    kDSI_InterruptGroup1BtaTo                = (1UL << 31U), 
    kDSI_InterruptGroup2EccOneBit            = (1UL << 0U),  
    kDSI_InterruptGroup2EccMultiBit          = (1UL << 1U),  
    kDSI_InterruptGroup2CrcError             = (1UL << 2U),  
};
 
typedef enum _dsi_tx_data_type
{
    kDSI_TxDataVsyncStart          = 0x01U, 
    kDSI_TxDataVsyncEnd            = 0x11U, 
    kDSI_TxDataHsyncStart          = 0x21U, 
    kDSI_TxDataHsyncEnd            = 0x31U, 
    kDSI_TxDataEoTp                = 0x08U, 
    kDSI_TxDataCmOff               = 0x02U, 
    kDSI_TxDataCmOn                = 0x12U, 
    kDSI_TxDataShutDownPeriph      = 0x22U, 
    kDSI_TxDataTurnOnPeriph        = 0x32U, 
    kDSI_TxDataGenShortWrNoParam   = 0x03U, 
    kDSI_TxDataGenShortWrOneParam  = 0x13U, 
    kDSI_TxDataGenShortWrTwoParam  = 0x23U, 
    kDSI_TxDataGenShortRdNoParam   = 0x04U, 
    kDSI_TxDataGenShortRdOneParam  = 0x14U, 
    kDSI_TxDataGenShortRdTwoParam  = 0x24U, 
    kDSI_TxDataDcsShortWrNoParam   = 0x05U, 
    kDSI_TxDataDcsShortWrOneParam  = 0x15U, 
    kDSI_TxDataDcsShortRdNoParam   = 0x06U, 
    kDSI_TxDataSetMaxReturnPktSize = 0x37U, 
    kDSI_TxDataNull                         = 0x09U, 
    kDSI_TxDataBlanking                     = 0x19U, 
    kDSI_TxDataGenLongWr                    = 0x29U, 
    kDSI_TxDataDcsLongWr                    = 0x39U, 
    kDSI_TxDataLooselyPackedPixel20BitYCbCr = 0x0CU, 
    kDSI_TxDataPackedPixel24BitYCbCr        = 0x1CU, 
    kDSI_TxDataPackedPixel16BitYCbCr        = 0x2CU, 
    kDSI_TxDataPackedPixel30BitRGB          = 0x0DU, 
    kDSI_TxDataPackedPixel36BitRGB          = 0x1DU, 
    kDSI_TxDataPackedPixel12BitYCrCb        = 0x3DU, 
    kDSI_TxDataPackedPixel16BitRGB          = 0x0EU, 
    kDSI_TxDataPackedPixel18BitRGB          = 0x1EU, 
    kDSI_TxDataLooselyPackedPixel18BitRGB   = 0x2EU, 
    kDSI_TxDataPackedPixel24BitRGB          = 0x3EU, 
} dsi_tx_data_type_t;
 
typedef enum _dsi_rx_data_type
{
    kDSI_RxDataAckAndErrorReport         = 0x02U, 
    kDSI_RxDataEoTp                      = 0x08U, 
    kDSI_RxDataGenShortRdResponseOneByte = 0x11U, 
    kDSI_RxDataGenShortRdResponseTwoByte = 0x12U, 
    kDSI_RxDataGenLongRdResponse         = 0x1AU, 
    kDSI_RxDataDcsLongRdResponse         = 0x1CU, 
    kDSI_RxDataDcsShortRdResponseOneByte = 0x21U, 
    kDSI_RxDataDcsShortRdResponseTwoByte = 0x22U, 
} dsi_rx_data_type_t;
 
enum
{
    kDSI_TransferUseHighSpeed = (1U << 0U), 
    kDSI_TransferPerformBTA   = (1U << 1U), 
};
 
typedef struct _dsi_transfer
{
    uint8_t virtualChannel;        
    dsi_tx_data_type_t txDataType; 
    uint8_t flags;                 
    const uint8_t *txData;         
    uint8_t *rxData;               
    uint16_t txDataSize;           
    uint16_t rxDataSize;           
    bool sendDscCmd;               
    uint8_t dscCmd;                
} dsi_transfer_t;
 
typedef struct _dsi_handle dsi_handle_t;
 
typedef void (*dsi_callback_t)(const MIPI_DSI_Type *base, dsi_handle_t *handle, status_t status, void *userData);
 
struct _dsi_handle
{
    volatile bool isBusy;     
    dsi_transfer_t xfer;      
    dsi_callback_t callback;  
    void *userData;           
    const MIPI_DSI_Type *dsi; 
};
 
/*******************************************************************************
 * API
 ******************************************************************************/
 
#if defined(__cplusplus)
extern "C" {
#endif
 
void DSI_Init(const MIPI_DSI_Type *base, const dsi_config_t *config);
 
void DSI_Deinit(const MIPI_DSI_Type *base);
 
void DSI_GetDefaultConfig(dsi_config_t *config);
 
void DSI_SetDpiConfig(const MIPI_DSI_Type *base,
                      const dsi_dpi_config_t *config,
                      uint8_t numLanes,
                      uint32_t dpiPixelClkFreq_Hz,
                      uint32_t dsiHsBitClkFreq_Hz);
 
uint32_t DSI_InitDphy(const MIPI_DSI_Type *base, const dsi_dphy_config_t *config, uint32_t refClkFreq_Hz);
 
void DSI_DeinitDphy(const MIPI_DSI_Type *base);
 
void DSI_GetDphyDefaultConfig(dsi_dphy_config_t *config, uint32_t txHsBitClk_Hz, uint32_t txEscClk_Hz);
 
static inline void DSI_EnableInterrupts(const MIPI_DSI_Type *base, uint32_t intGroup1, uint32_t intGroup2)
{
    base->apb->IRQ_MASK &= ~intGroup1;
    base->apb->IRQ_MASK2 &= ~intGroup2;
}
 
static inline void DSI_DisableInterrupts(const MIPI_DSI_Type *base, uint32_t intGroup1, uint32_t intGroup2)
{
    base->apb->IRQ_MASK |= intGroup1;
    base->apb->IRQ_MASK2 |= intGroup2;
}
 
static inline void DSI_GetAndClearInterruptStatus(const MIPI_DSI_Type *base, uint32_t *intGroup1, uint32_t *intGroup2)
{
    *intGroup2 = base->apb->IRQ_STATUS2;
    *intGroup1 = base->apb->IRQ_STATUS;
}
 
void DSI_SetApbPacketControl(
    const MIPI_DSI_Type *base, uint16_t wordCount, uint8_t virtualChannel, dsi_tx_data_type_t dataType, uint8_t flags);
 
void DSI_WriteApbTxPayload(const MIPI_DSI_Type *base, const uint8_t *payload, uint16_t payloadSize);
 
void DSI_WriteApbTxPayloadExt(
    const MIPI_DSI_Type *base, const uint8_t *payload, uint16_t payloadSize, bool sendDscCmd, uint8_t dscCmd);
 
void DSI_ReadApbRxPayload(const MIPI_DSI_Type *base, uint8_t *payload, uint16_t payloadSize);
 
static inline void DSI_SendApbPacket(const MIPI_DSI_Type *base)
{
    base->apb->SEND_PACKET = 0x1U;
}
 
static inline uint32_t DSI_GetApbStatus(const MIPI_DSI_Type *base)
{
    return base->apb->PKT_STATUS;
}
 
static inline uint32_t DSI_GetRxErrorStatus(const MIPI_DSI_Type *base)
{
    return base->host->RX_ERROR_STATUS;
}
 
static inline uint8_t DSI_GetEccRxErrorPosition(uint32_t rxErrorStatus)
{
    return (uint8_t)((rxErrorStatus >> 2U) & 0x1FU);
}
 
static inline uint32_t DSI_GetAndClearHostStatus(const MIPI_DSI_Type *base)
{
    return base->host->CFG_STATUS_OUT;
}
 
static inline uint32_t DSI_GetRxPacketHeader(const MIPI_DSI_Type *base)
{
    return base->apb->PKT_RX_PKT_HEADER;
}
 
static inline dsi_rx_data_type_t DSI_GetRxPacketType(uint32_t rxPktHeader)
{
    return (dsi_rx_data_type_t)(uint8_t)((rxPktHeader >> 16U) & 0x3FU);
}
 
static inline uint16_t DSI_GetRxPacketWordCount(uint32_t rxPktHeader)
{
    return (uint16_t)(rxPktHeader & 0xFFFFU);
}
 
static inline uint8_t DSI_GetRxPacketVirtualChannel(uint32_t rxPktHeader)
{
    return (uint8_t)((rxPktHeader >> 22U) & 0x3U);
}
 
status_t DSI_TransferBlocking(const MIPI_DSI_Type *base, dsi_transfer_t *xfer);
 
status_t DSI_TransferCreateHandle(const MIPI_DSI_Type *base,
                                  dsi_handle_t *handle,
                                  dsi_callback_t callback,
                                  void *userData);
 
status_t DSI_TransferNonBlocking(const MIPI_DSI_Type *base, dsi_handle_t *handle, dsi_transfer_t *xfer);
 
void DSI_TransferAbort(const MIPI_DSI_Type *base, dsi_handle_t *handle);
 
void DSI_TransferHandleIRQ(const MIPI_DSI_Type *base, dsi_handle_t *handle);
 
#if defined(__cplusplus)
}
#endif
 
#endif /* _FSL_MIPI_DSI_H_ */