RTEMS 6.1-rc5
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stm32h742xx.h
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1
33#ifndef STM32H742xx_H
34#define STM32H742xx_H
35
36#ifdef __cplusplus
37 extern "C" {
38#endif /* __cplusplus */
39
48typedef enum
49{
50/****** Cortex-M Processor Exceptions Numbers *****************************************************************/
51 NonMaskableInt_IRQn = -14,
52 HardFault_IRQn = -13,
53 MemoryManagement_IRQn = -12,
54 BusFault_IRQn = -11,
55 UsageFault_IRQn = -10,
56 SVCall_IRQn = -5,
57 DebugMonitor_IRQn = -4,
58 PendSV_IRQn = -2,
59 SysTick_IRQn = -1,
60/****** STM32 specific Interrupt Numbers **********************************************************************/
61 WWDG_IRQn = 0,
62 PVD_AVD_IRQn = 1,
63 TAMP_STAMP_IRQn = 2,
64 RTC_WKUP_IRQn = 3,
65 FLASH_IRQn = 4,
66 RCC_IRQn = 5,
67 EXTI0_IRQn = 6,
68 EXTI1_IRQn = 7,
69 EXTI2_IRQn = 8,
70 EXTI3_IRQn = 9,
71 EXTI4_IRQn = 10,
72 DMA1_Stream0_IRQn = 11,
73 DMA1_Stream1_IRQn = 12,
74 DMA1_Stream2_IRQn = 13,
75 DMA1_Stream3_IRQn = 14,
76 DMA1_Stream4_IRQn = 15,
77 DMA1_Stream5_IRQn = 16,
78 DMA1_Stream6_IRQn = 17,
79 ADC_IRQn = 18,
80 FDCAN1_IT0_IRQn = 19,
81 FDCAN2_IT0_IRQn = 20,
82 FDCAN1_IT1_IRQn = 21,
83 FDCAN2_IT1_IRQn = 22,
84 EXTI9_5_IRQn = 23,
85 TIM1_BRK_IRQn = 24,
86 TIM1_UP_IRQn = 25,
87 TIM1_TRG_COM_IRQn = 26,
88 TIM1_CC_IRQn = 27,
89 TIM2_IRQn = 28,
90 TIM3_IRQn = 29,
91 TIM4_IRQn = 30,
92 I2C1_EV_IRQn = 31,
93 I2C1_ER_IRQn = 32,
94 I2C2_EV_IRQn = 33,
95 I2C2_ER_IRQn = 34,
96 SPI1_IRQn = 35,
97 SPI2_IRQn = 36,
98 USART1_IRQn = 37,
99 USART2_IRQn = 38,
100 USART3_IRQn = 39,
101 EXTI15_10_IRQn = 40,
102 RTC_Alarm_IRQn = 41,
103 TIM8_BRK_TIM12_IRQn = 43,
104 TIM8_UP_TIM13_IRQn = 44,
105 TIM8_TRG_COM_TIM14_IRQn = 45,
106 TIM8_CC_IRQn = 46,
107 DMA1_Stream7_IRQn = 47,
108 FMC_IRQn = 48,
109 SDMMC1_IRQn = 49,
110 TIM5_IRQn = 50,
111 SPI3_IRQn = 51,
112 UART4_IRQn = 52,
113 UART5_IRQn = 53,
114 TIM6_DAC_IRQn = 54,
115 TIM7_IRQn = 55,
116 DMA2_Stream0_IRQn = 56,
117 DMA2_Stream1_IRQn = 57,
118 DMA2_Stream2_IRQn = 58,
119 DMA2_Stream3_IRQn = 59,
120 DMA2_Stream4_IRQn = 60,
121 ETH_IRQn = 61,
122 ETH_WKUP_IRQn = 62,
123 FDCAN_CAL_IRQn = 63,
124 DMA2_Stream5_IRQn = 68,
125 DMA2_Stream6_IRQn = 69,
126 DMA2_Stream7_IRQn = 70,
127 USART6_IRQn = 71,
128 I2C3_EV_IRQn = 72,
129 I2C3_ER_IRQn = 73,
130 OTG_HS_EP1_OUT_IRQn = 74,
131 OTG_HS_EP1_IN_IRQn = 75,
132 OTG_HS_WKUP_IRQn = 76,
133 OTG_HS_IRQn = 77,
134 DCMI_IRQn = 78,
135 RNG_IRQn = 80,
136 FPU_IRQn = 81,
137 UART7_IRQn = 82,
138 UART8_IRQn = 83,
139 SPI4_IRQn = 84,
140 SPI5_IRQn = 85,
141 SPI6_IRQn = 86,
142 SAI1_IRQn = 87,
143 DMA2D_IRQn = 90,
144 SAI2_IRQn = 91,
145 QUADSPI_IRQn = 92,
146 LPTIM1_IRQn = 93,
147 CEC_IRQn = 94,
148 I2C4_EV_IRQn = 95,
149 I2C4_ER_IRQn = 96,
150 SPDIF_RX_IRQn = 97,
151 OTG_FS_EP1_OUT_IRQn = 98,
152 OTG_FS_EP1_IN_IRQn = 99,
153 OTG_FS_WKUP_IRQn = 100,
154 OTG_FS_IRQn = 101,
155 DMAMUX1_OVR_IRQn = 102,
156 HRTIM1_Master_IRQn = 103,
157 HRTIM1_TIMA_IRQn = 104,
158 HRTIM1_TIMB_IRQn = 105,
159 HRTIM1_TIMC_IRQn = 106,
160 HRTIM1_TIMD_IRQn = 107,
161 HRTIM1_TIME_IRQn = 108,
162 HRTIM1_FLT_IRQn = 109,
163 DFSDM1_FLT0_IRQn = 110,
164 DFSDM1_FLT1_IRQn = 111,
165 DFSDM1_FLT2_IRQn = 112,
166 DFSDM1_FLT3_IRQn = 113,
167 SAI3_IRQn = 114,
168 SWPMI1_IRQn = 115,
169 TIM15_IRQn = 116,
170 TIM16_IRQn = 117,
171 TIM17_IRQn = 118,
172 MDIOS_WKUP_IRQn = 119,
173 MDIOS_IRQn = 120,
174 MDMA_IRQn = 122,
175 SDMMC2_IRQn = 124,
176 HSEM1_IRQn = 125,
177 ADC3_IRQn = 127,
178 DMAMUX2_OVR_IRQn = 128,
179 BDMA_Channel0_IRQn = 129,
180 BDMA_Channel1_IRQn = 130,
181 BDMA_Channel2_IRQn = 131,
182 BDMA_Channel3_IRQn = 132,
183 BDMA_Channel4_IRQn = 133,
184 BDMA_Channel5_IRQn = 134,
185 BDMA_Channel6_IRQn = 135,
186 BDMA_Channel7_IRQn = 136,
187 COMP_IRQn = 137 ,
188 LPTIM2_IRQn = 138,
189 LPTIM3_IRQn = 139,
190 LPTIM4_IRQn = 140,
191 LPTIM5_IRQn = 141,
192 LPUART1_IRQn = 142,
193 CRS_IRQn = 144,
194 ECC_IRQn = 145,
195 SAI4_IRQn = 146,
196 WAKEUP_PIN_IRQn = 149,
197} IRQn_Type;
198
213#define __CM7_REV 0x0101U
214#define __MPU_PRESENT 1U
215#define __NVIC_PRIO_BITS 4U
216#define __Vendor_SysTickConfig 0U
217#define __FPU_PRESENT 1U
218#define __ICACHE_PRESENT 1U
219#define __DCACHE_PRESENT 1U
220#include "core_cm7.h"
228#include "system_stm32h7xx.h"
229#include <stdint.h>
230
239typedef struct
240{
241 __IO uint32_t ISR;
242 __IO uint32_t IER;
243 __IO uint32_t CR;
244 __IO uint32_t CFGR;
245 __IO uint32_t CFGR2;
246 __IO uint32_t SMPR1;
247 __IO uint32_t SMPR2;
248 __IO uint32_t PCSEL;
249 __IO uint32_t LTR1;
250 __IO uint32_t HTR1;
251 uint32_t RESERVED1;
252 uint32_t RESERVED2;
253 __IO uint32_t SQR1;
254 __IO uint32_t SQR2;
255 __IO uint32_t SQR3;
256 __IO uint32_t SQR4;
257 __IO uint32_t DR;
258 uint32_t RESERVED3;
259 uint32_t RESERVED4;
260 __IO uint32_t JSQR;
261 uint32_t RESERVED5[4];
262 __IO uint32_t OFR1;
263 __IO uint32_t OFR2;
264 __IO uint32_t OFR3;
265 __IO uint32_t OFR4;
266 uint32_t RESERVED6[4];
267 __IO uint32_t JDR1;
268 __IO uint32_t JDR2;
269 __IO uint32_t JDR3;
270 __IO uint32_t JDR4;
271 uint32_t RESERVED7[4];
272 __IO uint32_t AWD2CR;
273 __IO uint32_t AWD3CR;
274 uint32_t RESERVED8;
275 uint32_t RESERVED9;
276 __IO uint32_t LTR2;
277 __IO uint32_t HTR2;
278 __IO uint32_t LTR3;
279 __IO uint32_t HTR3;
280 __IO uint32_t DIFSEL;
281 __IO uint32_t CALFACT;
282 __IO uint32_t CALFACT2;
283} ADC_TypeDef;
284
285
286typedef struct
287{
288__IO uint32_t CSR;
289uint32_t RESERVED;
290__IO uint32_t CCR;
291__IO uint32_t CDR;
292__IO uint32_t CDR2;
294} ADC_Common_TypeDef;
295
296
301typedef struct
302{
303 __IO uint32_t CSR;
304 __IO uint32_t CCR;
305} VREFBUF_TypeDef;
306
307
312typedef struct
313{
314 __IO uint32_t CREL;
315 __IO uint32_t ENDN;
316 __IO uint32_t RESERVED1;
317 __IO uint32_t DBTP;
318 __IO uint32_t TEST;
319 __IO uint32_t RWD;
320 __IO uint32_t CCCR;
321 __IO uint32_t NBTP;
322 __IO uint32_t TSCC;
323 __IO uint32_t TSCV;
324 __IO uint32_t TOCC;
325 __IO uint32_t TOCV;
326 __IO uint32_t RESERVED2[4];
327 __IO uint32_t ECR;
328 __IO uint32_t PSR;
329 __IO uint32_t TDCR;
330 __IO uint32_t RESERVED3;
331 __IO uint32_t IR;
332 __IO uint32_t IE;
333 __IO uint32_t ILS;
334 __IO uint32_t ILE;
335 __IO uint32_t RESERVED4[8];
336 __IO uint32_t GFC;
337 __IO uint32_t SIDFC;
338 __IO uint32_t XIDFC;
339 __IO uint32_t RESERVED5;
340 __IO uint32_t XIDAM;
341 __IO uint32_t HPMS;
342 __IO uint32_t NDAT1;
343 __IO uint32_t NDAT2;
344 __IO uint32_t RXF0C;
345 __IO uint32_t RXF0S;
346 __IO uint32_t RXF0A;
347 __IO uint32_t RXBC;
348 __IO uint32_t RXF1C;
349 __IO uint32_t RXF1S;
350 __IO uint32_t RXF1A;
351 __IO uint32_t RXESC;
352 __IO uint32_t TXBC;
353 __IO uint32_t TXFQS;
354 __IO uint32_t TXESC;
355 __IO uint32_t TXBRP;
356 __IO uint32_t TXBAR;
357 __IO uint32_t TXBCR;
358 __IO uint32_t TXBTO;
359 __IO uint32_t TXBCF;
360 __IO uint32_t TXBTIE;
361 __IO uint32_t TXBCIE;
362 __IO uint32_t RESERVED6[2];
363 __IO uint32_t TXEFC;
364 __IO uint32_t TXEFS;
365 __IO uint32_t TXEFA;
366 __IO uint32_t RESERVED7;
367} FDCAN_GlobalTypeDef;
368
373typedef struct
374{
375 __IO uint32_t TTTMC;
376 __IO uint32_t TTRMC;
377 __IO uint32_t TTOCF;
378 __IO uint32_t TTMLM;
379 __IO uint32_t TURCF;
380 __IO uint32_t TTOCN;
381 __IO uint32_t TTGTP;
382 __IO uint32_t TTTMK;
383 __IO uint32_t TTIR;
384 __IO uint32_t TTIE;
385 __IO uint32_t TTILS;
386 __IO uint32_t TTOST;
387 __IO uint32_t TURNA;
388 __IO uint32_t TTLGT;
389 __IO uint32_t TTCTC;
390 __IO uint32_t TTCPT;
391 __IO uint32_t TTCSM;
392 __IO uint32_t RESERVED1[111];
393 __IO uint32_t TTTS;
394} TTCAN_TypeDef;
395
400typedef struct
401{
402 __IO uint32_t CREL;
403 __IO uint32_t CCFG;
404 __IO uint32_t CSTAT;
405 __IO uint32_t CWD;
406 __IO uint32_t IR;
407 __IO uint32_t IE;
408} FDCAN_ClockCalibrationUnit_TypeDef;
409
410
415typedef struct
416{
417 __IO uint32_t CR;
418 __IO uint32_t CFGR;
419 __IO uint32_t TXDR;
420 __IO uint32_t RXDR;
421 __IO uint32_t ISR;
422 __IO uint32_t IER;
423}CEC_TypeDef;
424
429typedef struct
430{
431 __IO uint32_t DR;
432 __IO uint32_t IDR;
433 __IO uint32_t CR;
434 uint32_t RESERVED2;
435 __IO uint32_t INIT;
436 __IO uint32_t POL;
437} CRC_TypeDef;
438
439
443typedef struct
444{
445__IO uint32_t CR;
446__IO uint32_t CFGR;
447__IO uint32_t ISR;
448__IO uint32_t ICR;
449} CRS_TypeDef;
450
451
456typedef struct
457{
458 __IO uint32_t CR;
459 __IO uint32_t SWTRIGR;
460 __IO uint32_t DHR12R1;
461 __IO uint32_t DHR12L1;
462 __IO uint32_t DHR8R1;
463 __IO uint32_t DHR12R2;
464 __IO uint32_t DHR12L2;
465 __IO uint32_t DHR8R2;
466 __IO uint32_t DHR12RD;
467 __IO uint32_t DHR12LD;
468 __IO uint32_t DHR8RD;
469 __IO uint32_t DOR1;
470 __IO uint32_t DOR2;
471 __IO uint32_t SR;
472 __IO uint32_t CCR;
473 __IO uint32_t MCR;
474 __IO uint32_t SHSR1;
475 __IO uint32_t SHSR2;
476 __IO uint32_t SHHR;
477 __IO uint32_t SHRR;
478} DAC_TypeDef;
479
483typedef struct
484{
485 __IO uint32_t FLTCR1;
486 __IO uint32_t FLTCR2;
487 __IO uint32_t FLTISR;
488 __IO uint32_t FLTICR;
489 __IO uint32_t FLTJCHGR;
490 __IO uint32_t FLTFCR;
491 __IO uint32_t FLTJDATAR;
492 __IO uint32_t FLTRDATAR;
493 __IO uint32_t FLTAWHTR;
494 __IO uint32_t FLTAWLTR;
495 __IO uint32_t FLTAWSR;
496 __IO uint32_t FLTAWCFR;
497 __IO uint32_t FLTEXMAX;
498 __IO uint32_t FLTEXMIN;
499 __IO uint32_t FLTCNVTIMR;
500} DFSDM_Filter_TypeDef;
501
505typedef struct
506{
507 __IO uint32_t CHCFGR1;
508 __IO uint32_t CHCFGR2;
509 __IO uint32_t CHAWSCDR;
511 __IO uint32_t CHWDATAR;
512 __IO uint32_t CHDATINR;
513} DFSDM_Channel_TypeDef;
514
518typedef struct
519{
520 __IO uint32_t IDCODE;
521 __IO uint32_t CR;
522 uint32_t RESERVED4[11];
523 __IO uint32_t APB3FZ1;
524 uint32_t RESERVED5;
525 __IO uint32_t APB1LFZ1;
526 uint32_t RESERVED6;
527 __IO uint32_t APB1HFZ1;
528 uint32_t RESERVED7;
529 __IO uint32_t APB2FZ1;
530 uint32_t RESERVED8;
531 __IO uint32_t APB4FZ1;
532}DBGMCU_TypeDef;
537typedef struct
538{
539 __IO uint32_t CR;
540 __IO uint32_t SR;
541 __IO uint32_t RISR;
542 __IO uint32_t IER;
543 __IO uint32_t MISR;
544 __IO uint32_t ICR;
545 __IO uint32_t ESCR;
546 __IO uint32_t ESUR;
547 __IO uint32_t CWSTRTR;
548 __IO uint32_t CWSIZER;
549 __IO uint32_t DR;
550} DCMI_TypeDef;
551
556typedef struct
557{
558 __IO uint32_t CR;
559 __IO uint32_t NDTR;
560 __IO uint32_t PAR;
561 __IO uint32_t M0AR;
562 __IO uint32_t M1AR;
563 __IO uint32_t FCR;
564} DMA_Stream_TypeDef;
565
566typedef struct
567{
568 __IO uint32_t LISR;
569 __IO uint32_t HISR;
570 __IO uint32_t LIFCR;
571 __IO uint32_t HIFCR;
572} DMA_TypeDef;
573
574typedef struct
575{
576 __IO uint32_t CCR;
577 __IO uint32_t CNDTR;
578 __IO uint32_t CPAR;
579 __IO uint32_t CM0AR;
580 __IO uint32_t CM1AR;
581} BDMA_Channel_TypeDef;
582
583typedef struct
584{
585 __IO uint32_t ISR;
586 __IO uint32_t IFCR;
587} BDMA_TypeDef;
588
589typedef struct
590{
591 __IO uint32_t CCR;
592}DMAMUX_Channel_TypeDef;
593
594typedef struct
595{
596 __IO uint32_t CSR;
597 __IO uint32_t CFR;
598}DMAMUX_ChannelStatus_TypeDef;
599
600typedef struct
601{
602 __IO uint32_t RGCR;
603}DMAMUX_RequestGen_TypeDef;
604
605typedef struct
606{
607 __IO uint32_t RGSR;
608 __IO uint32_t RGCFR;
609}DMAMUX_RequestGenStatus_TypeDef;
610
614typedef struct
615{
616 __IO uint32_t GISR0;
617}MDMA_TypeDef;
618
619typedef struct
620{
621 __IO uint32_t CISR;
622 __IO uint32_t CIFCR;
623 __IO uint32_t CESR;
624 __IO uint32_t CCR;
625 __IO uint32_t CTCR;
626 __IO uint32_t CBNDTR;
627 __IO uint32_t CSAR;
628 __IO uint32_t CDAR;
629 __IO uint32_t CBRUR;
630 __IO uint32_t CLAR;
631 __IO uint32_t CTBR;
632 uint32_t RESERVED0;
633 __IO uint32_t CMAR;
634 __IO uint32_t CMDR;
635}MDMA_Channel_TypeDef;
636
641typedef struct
642{
643 __IO uint32_t CR;
644 __IO uint32_t ISR;
645 __IO uint32_t IFCR;
646 __IO uint32_t FGMAR;
647 __IO uint32_t FGOR;
648 __IO uint32_t BGMAR;
649 __IO uint32_t BGOR;
650 __IO uint32_t FGPFCCR;
651 __IO uint32_t FGCOLR;
652 __IO uint32_t BGPFCCR;
653 __IO uint32_t BGCOLR;
654 __IO uint32_t FGCMAR;
655 __IO uint32_t BGCMAR;
656 __IO uint32_t OPFCCR;
657 __IO uint32_t OCOLR;
658 __IO uint32_t OMAR;
659 __IO uint32_t OOR;
660 __IO uint32_t NLR;
661 __IO uint32_t LWR;
662 __IO uint32_t AMTCR;
663 uint32_t RESERVED[236];
664 __IO uint32_t FGCLUT[256];
665 __IO uint32_t BGCLUT[256];
666} DMA2D_TypeDef;
667
668
672typedef struct
673{
674 __IO uint32_t MACCR;
675 __IO uint32_t MACECR;
676 __IO uint32_t MACPFR;
677 __IO uint32_t MACWTR;
678 __IO uint32_t MACHT0R;
679 __IO uint32_t MACHT1R;
680 uint32_t RESERVED1[14];
681 __IO uint32_t MACVTR;
682 uint32_t RESERVED2;
683 __IO uint32_t MACVHTR;
684 uint32_t RESERVED3;
685 __IO uint32_t MACVIR;
686 __IO uint32_t MACIVIR;
687 uint32_t RESERVED4[2];
688 __IO uint32_t MACTFCR;
689 uint32_t RESERVED5[7];
690 __IO uint32_t MACRFCR;
691 uint32_t RESERVED6[7];
692 __IO uint32_t MACISR;
693 __IO uint32_t MACIER;
694 __IO uint32_t MACRXTXSR;
695 uint32_t RESERVED7;
696 __IO uint32_t MACPCSR;
697 __IO uint32_t MACRWKPFR;
698 uint32_t RESERVED8[2];
699 __IO uint32_t MACLCSR;
700 __IO uint32_t MACLTCR;
701 __IO uint32_t MACLETR;
702 __IO uint32_t MAC1USTCR;
703 uint32_t RESERVED9[12];
704 __IO uint32_t MACVR;
705 __IO uint32_t MACDR;
706 uint32_t RESERVED10;
707 __IO uint32_t MACHWF0R;
708 __IO uint32_t MACHWF1R;
709 __IO uint32_t MACHWF2R;
710 uint32_t RESERVED11[54];
711 __IO uint32_t MACMDIOAR;
712 __IO uint32_t MACMDIODR;
713 uint32_t RESERVED12[2];
714 __IO uint32_t MACARPAR;
715 uint32_t RESERVED13[59];
716 __IO uint32_t MACA0HR;
717 __IO uint32_t MACA0LR;
718 __IO uint32_t MACA1HR;
719 __IO uint32_t MACA1LR;
720 __IO uint32_t MACA2HR;
721 __IO uint32_t MACA2LR;
722 __IO uint32_t MACA3HR;
723 __IO uint32_t MACA3LR;
724 uint32_t RESERVED14[248];
725 __IO uint32_t MMCCR;
726 __IO uint32_t MMCRIR;
727 __IO uint32_t MMCTIR;
728 __IO uint32_t MMCRIMR;
729 __IO uint32_t MMCTIMR;
730 uint32_t RESERVED15[14];
731 __IO uint32_t MMCTSCGPR;
732 __IO uint32_t MMCTMCGPR;
733 uint32_t RESERVED16[5];
734 __IO uint32_t MMCTPCGR;
735 uint32_t RESERVED17[10];
736 __IO uint32_t MMCRCRCEPR;
737 __IO uint32_t MMCRAEPR;
738 uint32_t RESERVED18[10];
739 __IO uint32_t MMCRUPGR;
740 uint32_t RESERVED19[9];
741 __IO uint32_t MMCTLPIMSTR;
742 __IO uint32_t MMCTLPITCR;
743 __IO uint32_t MMCRLPIMSTR;
744 __IO uint32_t MMCRLPITCR;
745 uint32_t RESERVED20[65];
746 __IO uint32_t MACL3L4C0R;
747 __IO uint32_t MACL4A0R;
748 uint32_t RESERVED21[2];
749 __IO uint32_t MACL3A0R0R;
750 __IO uint32_t MACL3A1R0R;
751 __IO uint32_t MACL3A2R0R;
752 __IO uint32_t MACL3A3R0R;
753 uint32_t RESERVED22[4];
754 __IO uint32_t MACL3L4C1R;
755 __IO uint32_t MACL4A1R;
756 uint32_t RESERVED23[2];
757 __IO uint32_t MACL3A0R1R;
758 __IO uint32_t MACL3A1R1R;
759 __IO uint32_t MACL3A2R1R;
760 __IO uint32_t MACL3A3R1R;
761 uint32_t RESERVED24[108];
762 __IO uint32_t MACTSCR;
763 __IO uint32_t MACSSIR;
764 __IO uint32_t MACSTSR;
765 __IO uint32_t MACSTNR;
766 __IO uint32_t MACSTSUR;
767 __IO uint32_t MACSTNUR;
768 __IO uint32_t MACTSAR;
769 uint32_t RESERVED25;
770 __IO uint32_t MACTSSR;
771 uint32_t RESERVED26[3];
772 __IO uint32_t MACTTSSNR;
773 __IO uint32_t MACTTSSSR;
774 uint32_t RESERVED27[2];
775 __IO uint32_t MACACR;
776 uint32_t RESERVED28;
777 __IO uint32_t MACATSNR;
778 __IO uint32_t MACATSSR;
779 __IO uint32_t MACTSIACR;
780 __IO uint32_t MACTSEACR;
781 __IO uint32_t MACTSICNR;
782 __IO uint32_t MACTSECNR;
783 uint32_t RESERVED29[4];
784 __IO uint32_t MACPPSCR;
785 uint32_t RESERVED30[3];
786 __IO uint32_t MACPPSTTSR;
787 __IO uint32_t MACPPSTTNR;
788 __IO uint32_t MACPPSIR;
789 __IO uint32_t MACPPSWR;
790 uint32_t RESERVED31[12];
791 __IO uint32_t MACPOCR;
792 __IO uint32_t MACSPI0R;
793 __IO uint32_t MACSPI1R;
794 __IO uint32_t MACSPI2R;
795 __IO uint32_t MACLMIR;
796 uint32_t RESERVED32[11];
797 __IO uint32_t MTLOMR;
798 uint32_t RESERVED33[7];
799 __IO uint32_t MTLISR;
800 uint32_t RESERVED34[55];
801 __IO uint32_t MTLTQOMR;
802 __IO uint32_t MTLTQUR;
803 __IO uint32_t MTLTQDR;
804 uint32_t RESERVED35[8];
805 __IO uint32_t MTLQICSR;
806 __IO uint32_t MTLRQOMR;
807 __IO uint32_t MTLRQMPOCR;
808 __IO uint32_t MTLRQDR;
809 uint32_t RESERVED36[177];
810 __IO uint32_t DMAMR;
811 __IO uint32_t DMASBMR;
812 __IO uint32_t DMAISR;
813 __IO uint32_t DMADSR;
814 uint32_t RESERVED37[60];
815 __IO uint32_t DMACCR;
816 __IO uint32_t DMACTCR;
817 __IO uint32_t DMACRCR;
818 uint32_t RESERVED38[2];
819 __IO uint32_t DMACTDLAR;
820 uint32_t RESERVED39;
821 __IO uint32_t DMACRDLAR;
822 __IO uint32_t DMACTDTPR;
823 uint32_t RESERVED40;
824 __IO uint32_t DMACRDTPR;
825 __IO uint32_t DMACTDRLR;
826 __IO uint32_t DMACRDRLR;
827 __IO uint32_t DMACIER;
828 __IO uint32_t DMACRIWTR;
829__IO uint32_t DMACSFCSR;
830 uint32_t RESERVED41;
831 __IO uint32_t DMACCATDR;
832 uint32_t RESERVED42;
833 __IO uint32_t DMACCARDR;
834 uint32_t RESERVED43;
835 __IO uint32_t DMACCATBR;
836 uint32_t RESERVED44;
837 __IO uint32_t DMACCARBR;
838 __IO uint32_t DMACSR;
839uint32_t RESERVED45[2];
840__IO uint32_t DMACMFCR;
841}ETH_TypeDef;
846typedef struct
847{
848__IO uint32_t RTSR1;
849__IO uint32_t FTSR1;
850__IO uint32_t SWIER1;
851__IO uint32_t D3PMR1;
852__IO uint32_t D3PCR1L;
853__IO uint32_t D3PCR1H;
854uint32_t RESERVED1[2];
855__IO uint32_t RTSR2;
856__IO uint32_t FTSR2;
857__IO uint32_t SWIER2;
858__IO uint32_t D3PMR2;
859__IO uint32_t D3PCR2L;
860__IO uint32_t D3PCR2H;
861uint32_t RESERVED2[2];
862__IO uint32_t RTSR3;
863__IO uint32_t FTSR3;
864__IO uint32_t SWIER3;
865__IO uint32_t D3PMR3;
866__IO uint32_t D3PCR3L;
867__IO uint32_t D3PCR3H;
868uint32_t RESERVED3[10];
869__IO uint32_t IMR1;
870__IO uint32_t EMR1;
871__IO uint32_t PR1;
872uint32_t RESERVED4;
873__IO uint32_t IMR2;
874__IO uint32_t EMR2;
875__IO uint32_t PR2;
876uint32_t RESERVED5;
877__IO uint32_t IMR3;
878__IO uint32_t EMR3;
879__IO uint32_t PR3;
880}EXTI_TypeDef;
881
891typedef struct
892{
893__IO uint32_t IMR1;
894__IO uint32_t EMR1;
895__IO uint32_t PR1;
896uint32_t RESERVED1;
897__IO uint32_t IMR2;
898__IO uint32_t EMR2;
899__IO uint32_t PR2;
900uint32_t RESERVED2;
901__IO uint32_t IMR3;
902__IO uint32_t EMR3;
903__IO uint32_t PR3;
904}EXTI_Core_TypeDef;
905
906
911typedef struct
912{
913 __IO uint32_t ACR;
914 __IO uint32_t KEYR1;
915 __IO uint32_t OPTKEYR;
916 __IO uint32_t CR1;
917 __IO uint32_t SR1;
918 __IO uint32_t CCR1;
919 __IO uint32_t OPTCR;
920 __IO uint32_t OPTSR_CUR;
921 __IO uint32_t OPTSR_PRG;
922 __IO uint32_t OPTCCR;
923 __IO uint32_t PRAR_CUR1;
924 __IO uint32_t PRAR_PRG1;
925 __IO uint32_t SCAR_CUR1;
926 __IO uint32_t SCAR_PRG1;
927 __IO uint32_t WPSN_CUR1;
928 __IO uint32_t WPSN_PRG1;
929 __IO uint32_t BOOT_CUR;
930 __IO uint32_t BOOT_PRG;
931 uint32_t RESERVED0[2];
932 __IO uint32_t CRCCR1;
933 __IO uint32_t CRCSADD1;
934 __IO uint32_t CRCEADD1;
935 __IO uint32_t CRCDATA;
936 __IO uint32_t ECC_FA1;
937 uint32_t RESERVED1[40];
938 __IO uint32_t KEYR2;
939 uint32_t RESERVED2;
940 __IO uint32_t CR2;
941 __IO uint32_t SR2;
942 __IO uint32_t CCR2;
943 uint32_t RESERVED3[4];
944 __IO uint32_t PRAR_CUR2;
945 __IO uint32_t PRAR_PRG2;
946 __IO uint32_t SCAR_CUR2;
947 __IO uint32_t SCAR_PRG2;
948 __IO uint32_t WPSN_CUR2;
949 __IO uint32_t WPSN_PRG2;
950 uint32_t RESERVED4[4];
951 __IO uint32_t CRCCR2;
952 __IO uint32_t CRCSADD2;
953 __IO uint32_t CRCEADD2;
954 __IO uint32_t CRCDATA2;
955 __IO uint32_t ECC_FA2;
956} FLASH_TypeDef;
957
962typedef struct
963{
964 __IO uint32_t BTCR[8];
965} FMC_Bank1_TypeDef;
966
971typedef struct
972{
973 __IO uint32_t BWTR[7];
974} FMC_Bank1E_TypeDef;
975
980typedef struct
981{
982 __IO uint32_t PCR2;
983 __IO uint32_t SR2;
984 __IO uint32_t PMEM2;
985 __IO uint32_t PATT2;
986 uint32_t RESERVED0;
987 __IO uint32_t ECCR2;
988} FMC_Bank2_TypeDef;
989
994typedef struct
995{
996 __IO uint32_t PCR;
997 __IO uint32_t SR;
998 __IO uint32_t PMEM;
999 __IO uint32_t PATT;
1000 uint32_t RESERVED;
1001 __IO uint32_t ECCR;
1002} FMC_Bank3_TypeDef;
1003
1009typedef struct
1010{
1011 __IO uint32_t SDCR[2];
1012 __IO uint32_t SDTR[2];
1013 __IO uint32_t SDCMR;
1014 __IO uint32_t SDRTR;
1015 __IO uint32_t SDSR;
1016} FMC_Bank5_6_TypeDef;
1017
1022typedef struct
1023{
1024 __IO uint32_t MODER;
1025 __IO uint32_t OTYPER;
1026 __IO uint32_t OSPEEDR;
1027 __IO uint32_t PUPDR;
1028 __IO uint32_t IDR;
1029 __IO uint32_t ODR;
1030 __IO uint32_t BSRR;
1031 __IO uint32_t LCKR;
1032 __IO uint32_t AFR[2];
1033} GPIO_TypeDef;
1034
1039typedef struct
1040{
1041 __IO uint32_t CSR;
1042 __IO uint32_t OTR;
1043 __IO uint32_t HSOTR;
1044} OPAMP_TypeDef;
1045
1050typedef struct
1051{
1052 uint32_t RESERVED1;
1053 __IO uint32_t PMCR;
1054 __IO uint32_t EXTICR[4];
1055 __IO uint32_t CFGR;
1056 uint32_t RESERVED2;
1057 __IO uint32_t CCCSR;
1058 __IO uint32_t CCVR;
1059 __IO uint32_t CCCR;
1060 __IO uint32_t PWRCR;
1061 uint32_t RESERVED3[61];
1062 __IO uint32_t PKGR;
1063 uint32_t RESERVED4[118];
1064 __IO uint32_t UR0;
1065 __IO uint32_t UR1;
1066 __IO uint32_t UR2;
1067 __IO uint32_t UR3;
1068 __IO uint32_t UR4;
1069 __IO uint32_t UR5;
1070 __IO uint32_t UR6;
1071 __IO uint32_t UR7;
1072 __IO uint32_t UR8;
1073 __IO uint32_t UR9;
1074 __IO uint32_t UR10;
1075 __IO uint32_t UR11;
1076 __IO uint32_t UR12;
1077 __IO uint32_t UR13;
1078 __IO uint32_t UR14;
1079 __IO uint32_t UR15;
1080 __IO uint32_t UR16;
1081 __IO uint32_t UR17;
1083} SYSCFG_TypeDef;
1084
1089typedef struct
1090{
1091 __IO uint32_t CR1;
1092 __IO uint32_t CR2;
1093 __IO uint32_t OAR1;
1094 __IO uint32_t OAR2;
1095 __IO uint32_t TIMINGR;
1096 __IO uint32_t TIMEOUTR;
1097 __IO uint32_t ISR;
1098 __IO uint32_t ICR;
1099 __IO uint32_t PECR;
1100 __IO uint32_t RXDR;
1101 __IO uint32_t TXDR;
1102} I2C_TypeDef;
1103
1108typedef struct
1109{
1110 __IO uint32_t KR;
1111 __IO uint32_t PR;
1112 __IO uint32_t RLR;
1113 __IO uint32_t SR;
1114 __IO uint32_t WINR;
1115} IWDG_TypeDef;
1116
1117
1118
1123typedef struct
1124{
1125 __IO uint32_t CR1;
1126 __IO uint32_t CSR1;
1127 __IO uint32_t CR2;
1128 __IO uint32_t CR3;
1129 __IO uint32_t CPUCR;
1130 uint32_t RESERVED0;
1131 __IO uint32_t D3CR;
1132 uint32_t RESERVED1;
1133 __IO uint32_t WKUPCR;
1134 __IO uint32_t WKUPFR;
1135 __IO uint32_t WKUPEPR;
1136} PWR_TypeDef;
1137
1142typedef struct
1143{
1144 __IO uint32_t CR;
1145 __IO uint32_t HSICFGR;
1146 __IO uint32_t CRRCR;
1147 __IO uint32_t CSICFGR;
1148 __IO uint32_t CFGR;
1149 uint32_t RESERVED1;
1150 __IO uint32_t D1CFGR;
1151 __IO uint32_t D2CFGR;
1152 __IO uint32_t D3CFGR;
1153 uint32_t RESERVED2;
1154 __IO uint32_t PLLCKSELR;
1155 __IO uint32_t PLLCFGR;
1156 __IO uint32_t PLL1DIVR;
1157 __IO uint32_t PLL1FRACR;
1158 __IO uint32_t PLL2DIVR;
1159 __IO uint32_t PLL2FRACR;
1160 __IO uint32_t PLL3DIVR;
1161 __IO uint32_t PLL3FRACR;
1162 uint32_t RESERVED3;
1163 __IO uint32_t D1CCIPR;
1164 __IO uint32_t D2CCIP1R;
1165 __IO uint32_t D2CCIP2R;
1166 __IO uint32_t D3CCIPR;
1167 uint32_t RESERVED4;
1168 __IO uint32_t CIER;
1169 __IO uint32_t CIFR;
1170 __IO uint32_t CICR;
1171 uint32_t RESERVED5;
1172 __IO uint32_t BDCR;
1173 __IO uint32_t CSR;
1174 uint32_t RESERVED6;
1175 __IO uint32_t AHB3RSTR;
1176 __IO uint32_t AHB1RSTR;
1177 __IO uint32_t AHB2RSTR;
1178 __IO uint32_t AHB4RSTR;
1179 __IO uint32_t APB3RSTR;
1180 __IO uint32_t APB1LRSTR;
1181 __IO uint32_t APB1HRSTR;
1182 __IO uint32_t APB2RSTR;
1183 __IO uint32_t APB4RSTR;
1184 __IO uint32_t GCR;
1185 uint32_t RESERVED8;
1186 __IO uint32_t D3AMR;
1187 uint32_t RESERVED11[9];
1188 __IO uint32_t RSR;
1189 __IO uint32_t AHB3ENR;
1190 __IO uint32_t AHB1ENR;
1191 __IO uint32_t AHB2ENR;
1192 __IO uint32_t AHB4ENR;
1193 __IO uint32_t APB3ENR;
1194 __IO uint32_t APB1LENR;
1195 __IO uint32_t APB1HENR;
1196 __IO uint32_t APB2ENR;
1197 __IO uint32_t APB4ENR;
1198 uint32_t RESERVED12;
1199 __IO uint32_t AHB3LPENR;
1200 __IO uint32_t AHB1LPENR;
1201 __IO uint32_t AHB2LPENR;
1202 __IO uint32_t AHB4LPENR;
1203 __IO uint32_t APB3LPENR;
1204 __IO uint32_t APB1LLPENR;
1205 __IO uint32_t APB1HLPENR;
1206 __IO uint32_t APB2LPENR;
1207 __IO uint32_t APB4LPENR;
1208 uint32_t RESERVED13[4];
1210} RCC_TypeDef;
1211
1212
1216typedef struct
1217{
1218 __IO uint32_t TR;
1219 __IO uint32_t DR;
1220 __IO uint32_t CR;
1221 __IO uint32_t ISR;
1222 __IO uint32_t PRER;
1223 __IO uint32_t WUTR;
1224 uint32_t RESERVED;
1225 __IO uint32_t ALRMAR;
1226 __IO uint32_t ALRMBR;
1227 __IO uint32_t WPR;
1228 __IO uint32_t SSR;
1229 __IO uint32_t SHIFTR;
1230 __IO uint32_t TSTR;
1231 __IO uint32_t TSDR;
1232 __IO uint32_t TSSSR;
1233 __IO uint32_t CALR;
1234 __IO uint32_t TAMPCR;
1235 __IO uint32_t ALRMASSR;
1236 __IO uint32_t ALRMBSSR;
1237 __IO uint32_t OR;
1238 __IO uint32_t BKP0R;
1239 __IO uint32_t BKP1R;
1240 __IO uint32_t BKP2R;
1241 __IO uint32_t BKP3R;
1242 __IO uint32_t BKP4R;
1243 __IO uint32_t BKP5R;
1244 __IO uint32_t BKP6R;
1245 __IO uint32_t BKP7R;
1246 __IO uint32_t BKP8R;
1247 __IO uint32_t BKP9R;
1248 __IO uint32_t BKP10R;
1249 __IO uint32_t BKP11R;
1250 __IO uint32_t BKP12R;
1251 __IO uint32_t BKP13R;
1252 __IO uint32_t BKP14R;
1253 __IO uint32_t BKP15R;
1254 __IO uint32_t BKP16R;
1255 __IO uint32_t BKP17R;
1256 __IO uint32_t BKP18R;
1257 __IO uint32_t BKP19R;
1258 __IO uint32_t BKP20R;
1259 __IO uint32_t BKP21R;
1260 __IO uint32_t BKP22R;
1261 __IO uint32_t BKP23R;
1262 __IO uint32_t BKP24R;
1263 __IO uint32_t BKP25R;
1264 __IO uint32_t BKP26R;
1265 __IO uint32_t BKP27R;
1266 __IO uint32_t BKP28R;
1267 __IO uint32_t BKP29R;
1268 __IO uint32_t BKP30R;
1269 __IO uint32_t BKP31R;
1270} RTC_TypeDef;
1271
1276typedef struct
1277{
1278 __IO uint32_t GCR;
1279 uint32_t RESERVED0[16];
1280 __IO uint32_t PDMCR;
1281 __IO uint32_t PDMDLY;
1282} SAI_TypeDef;
1283
1284typedef struct
1285{
1286 __IO uint32_t CR1;
1287 __IO uint32_t CR2;
1288 __IO uint32_t FRCR;
1289 __IO uint32_t SLOTR;
1290 __IO uint32_t IMR;
1291 __IO uint32_t SR;
1292 __IO uint32_t CLRFR;
1293 __IO uint32_t DR;
1294} SAI_Block_TypeDef;
1295
1300typedef struct
1301{
1302 __IO uint32_t CR;
1303 __IO uint32_t IMR;
1304 __IO uint32_t SR;
1305 __IO uint32_t IFCR;
1306 __IO uint32_t DR;
1307 __IO uint32_t CSR;
1308 __IO uint32_t DIR;
1309 uint32_t RESERVED2;
1310} SPDIFRX_TypeDef;
1311
1312
1317typedef struct
1318{
1319 __IO uint32_t POWER;
1320 __IO uint32_t CLKCR;
1321 __IO uint32_t ARG;
1322 __IO uint32_t CMD;
1323 __I uint32_t RESPCMD;
1324 __I uint32_t RESP1;
1325 __I uint32_t RESP2;
1326 __I uint32_t RESP3;
1327 __I uint32_t RESP4;
1328 __IO uint32_t DTIMER;
1329 __IO uint32_t DLEN;
1330 __IO uint32_t DCTRL;
1331 __I uint32_t DCOUNT;
1332 __I uint32_t STA;
1333 __IO uint32_t ICR;
1334 __IO uint32_t MASK;
1335 __IO uint32_t ACKTIME;
1336 uint32_t RESERVED0[3];
1337 __IO uint32_t IDMACTRL;
1338 __IO uint32_t IDMABSIZE;
1339 __IO uint32_t IDMABASE0;
1340 __IO uint32_t IDMABASE1;
1341 uint32_t RESERVED1[8];
1342 __IO uint32_t FIFO;
1343 uint32_t RESERVED2[222];
1344 __IO uint32_t IPVR;
1345} SDMMC_TypeDef;
1346
1347
1352typedef struct
1353{
1354 __IO uint32_t CR;
1355 __IO uint32_t CFGR;
1356} DLYB_TypeDef;
1357
1362typedef struct
1363{
1364 __IO uint32_t R[32];
1365 __IO uint32_t RLR[32];
1366 __IO uint32_t C1IER;
1367 __IO uint32_t C1ICR;
1368 __IO uint32_t C1ISR;
1369 __IO uint32_t C1MISR;
1370 uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */
1371 __IO uint32_t CR;
1372 __IO uint32_t KEYR;
1374} HSEM_TypeDef;
1375
1376typedef struct
1377{
1378 __IO uint32_t IER;
1379 __IO uint32_t ICR;
1380 __IO uint32_t ISR;
1381 __IO uint32_t MISR;
1382} HSEM_Common_TypeDef;
1383
1388typedef struct
1389{
1390 __IO uint32_t CR1;
1391 __IO uint32_t CR2;
1392 __IO uint32_t CFG1;
1393 __IO uint32_t CFG2;
1394 __IO uint32_t IER;
1395 __IO uint32_t SR;
1396 __IO uint32_t IFCR;
1397 uint32_t RESERVED0;
1398 __IO uint32_t TXDR;
1399 uint32_t RESERVED1[3];
1400 __IO uint32_t RXDR;
1401 uint32_t RESERVED2[3];
1402 __IO uint32_t CRCPOLY;
1403 __IO uint32_t TXCRC;
1404 __IO uint32_t RXCRC;
1405 __IO uint32_t UDRDR;
1406 __IO uint32_t I2SCFGR;
1408} SPI_TypeDef;
1413typedef struct
1414{
1415 __IO uint32_t CR;
1416 __IO uint32_t DCR;
1417 __IO uint32_t SR;
1418 __IO uint32_t FCR;
1419 __IO uint32_t DLR;
1420 __IO uint32_t CCR;
1421 __IO uint32_t AR;
1422 __IO uint32_t ABR;
1423 __IO uint32_t DR;
1424 __IO uint32_t PSMKR;
1425 __IO uint32_t PSMAR;
1426 __IO uint32_t PIR;
1427 __IO uint32_t LPTR;
1428} QUADSPI_TypeDef;
1429
1434typedef struct
1435{
1436 __IO uint32_t CR1;
1437 __IO uint32_t CR2;
1438 __IO uint32_t SMCR;
1439 __IO uint32_t DIER;
1440 __IO uint32_t SR;
1441 __IO uint32_t EGR;
1442 __IO uint32_t CCMR1;
1443 __IO uint32_t CCMR2;
1444 __IO uint32_t CCER;
1445 __IO uint32_t CNT;
1446 __IO uint32_t PSC;
1447 __IO uint32_t ARR;
1448 __IO uint32_t RCR;
1449 __IO uint32_t CCR1;
1450 __IO uint32_t CCR2;
1451 __IO uint32_t CCR3;
1452 __IO uint32_t CCR4;
1453 __IO uint32_t BDTR;
1454 __IO uint32_t DCR;
1455 __IO uint32_t DMAR;
1456 uint32_t RESERVED1;
1457 __IO uint32_t CCMR3;
1458 __IO uint32_t CCR5;
1459 __IO uint32_t CCR6;
1460 __IO uint32_t AF1;
1461 __IO uint32_t AF2;
1462 __IO uint32_t TISEL;
1463} TIM_TypeDef;
1464
1468typedef struct
1469{
1470 __IO uint32_t ISR;
1471 __IO uint32_t ICR;
1472 __IO uint32_t IER;
1473 __IO uint32_t CFGR;
1474 __IO uint32_t CR;
1475 __IO uint32_t CMP;
1476 __IO uint32_t ARR;
1477 __IO uint32_t CNT;
1478 uint32_t RESERVED1;
1479 __IO uint32_t CFGR2;
1480} LPTIM_TypeDef;
1481
1485typedef struct
1486{
1487 __IO uint32_t SR;
1488 __IO uint32_t ICFR;
1489 __IO uint32_t OR;
1490} COMPOPT_TypeDef;
1491
1492typedef struct
1493{
1494 __IO uint32_t CFGR;
1495} COMP_TypeDef;
1496
1497typedef struct
1498{
1499 __IO uint32_t CFGR;
1500} COMP_Common_TypeDef;
1505typedef struct
1506{
1507 __IO uint32_t CR1;
1508 __IO uint32_t CR2;
1509 __IO uint32_t CR3;
1510 __IO uint32_t BRR;
1511 __IO uint32_t GTPR;
1512 __IO uint32_t RTOR;
1513 __IO uint32_t RQR;
1514 __IO uint32_t ISR;
1515 __IO uint32_t ICR;
1516 __IO uint32_t RDR;
1517 __IO uint32_t TDR;
1518 __IO uint32_t PRESC;
1519} USART_TypeDef;
1520
1524typedef struct
1525{
1526 __IO uint32_t CR;
1527 __IO uint32_t BRR;
1528 uint32_t RESERVED1;
1529 __IO uint32_t ISR;
1530 __IO uint32_t ICR;
1531 __IO uint32_t IER;
1532 __IO uint32_t RFL;
1533 __IO uint32_t TDR;
1534 __IO uint32_t RDR;
1535 __IO uint32_t OR;
1536} SWPMI_TypeDef;
1537
1542typedef struct
1543{
1544 __IO uint32_t CR;
1545 __IO uint32_t CFR;
1546 __IO uint32_t SR;
1547} WWDG_TypeDef;
1548
1549
1553typedef struct
1554{
1555 __IO uint32_t CR;
1556 __IO uint32_t SR;
1557 __IO uint32_t FAR;
1558 __IO uint32_t FDRL;
1559 __IO uint32_t FDRH;
1560 __IO uint32_t FECR;
1561} RAMECC_MonitorTypeDef;
1562
1563typedef struct
1564{
1565 __IO uint32_t IER;
1566} RAMECC_TypeDef;
1576/* HRTIM master registers definition */
1577typedef struct
1578{
1579 __IO uint32_t MCR;
1580 __IO uint32_t MISR;
1581 __IO uint32_t MICR;
1582 __IO uint32_t MDIER;
1583 __IO uint32_t MCNTR;
1584 __IO uint32_t MPER;
1585 __IO uint32_t MREP;
1586 __IO uint32_t MCMP1R;
1587 uint32_t RESERVED0;
1588 __IO uint32_t MCMP2R;
1589 __IO uint32_t MCMP3R;
1590 __IO uint32_t MCMP4R;
1591 uint32_t RESERVED1[20];
1592}HRTIM_Master_TypeDef;
1593
1594/* HRTIM Timer A to E registers definition */
1595typedef struct
1596{
1597 __IO uint32_t TIMxCR;
1598 __IO uint32_t TIMxISR;
1599 __IO uint32_t TIMxICR;
1600 __IO uint32_t TIMxDIER;
1601 __IO uint32_t CNTxR;
1602 __IO uint32_t PERxR;
1603 __IO uint32_t REPxR;
1604 __IO uint32_t CMP1xR;
1605 __IO uint32_t CMP1CxR;
1606 __IO uint32_t CMP2xR;
1607 __IO uint32_t CMP3xR;
1608 __IO uint32_t CMP4xR;
1609 __IO uint32_t CPT1xR;
1610 __IO uint32_t CPT2xR;
1611 __IO uint32_t DTxR;
1612 __IO uint32_t SETx1R;
1613 __IO uint32_t RSTx1R;
1614 __IO uint32_t SETx2R;
1615 __IO uint32_t RSTx2R;
1616 __IO uint32_t EEFxR1;
1617 __IO uint32_t EEFxR2;
1618 __IO uint32_t RSTxR;
1619 __IO uint32_t CHPxR;
1620 __IO uint32_t CPT1xCR;
1621 __IO uint32_t CPT2xCR;
1622 __IO uint32_t OUTxR;
1623 __IO uint32_t FLTxR;
1624 uint32_t RESERVED0[5];
1625}HRTIM_Timerx_TypeDef;
1626
1627/* HRTIM common register definition */
1628typedef struct
1629{
1630 __IO uint32_t CR1;
1631 __IO uint32_t CR2;
1632 __IO uint32_t ISR;
1633 __IO uint32_t ICR;
1634 __IO uint32_t IER;
1635 __IO uint32_t OENR;
1636 __IO uint32_t ODISR;
1637 __IO uint32_t ODSR;
1638 __IO uint32_t BMCR;
1639 __IO uint32_t BMTRGR;
1640 __IO uint32_t BMCMPR;
1641 __IO uint32_t BMPER;
1642 __IO uint32_t EECR1;
1643 __IO uint32_t EECR2;
1644 __IO uint32_t EECR3;
1645 __IO uint32_t ADC1R;
1646 __IO uint32_t ADC2R;
1647 __IO uint32_t ADC3R;
1648 __IO uint32_t ADC4R;
1649 __IO uint32_t RESERVED0;
1650 __IO uint32_t FLTINR1;
1651 __IO uint32_t FLTINR2;
1652 __IO uint32_t BDMUPR;
1653 __IO uint32_t BDTAUPR;
1654 __IO uint32_t BDTBUPR;
1655 __IO uint32_t BDTCUPR;
1656 __IO uint32_t BDTDUPR;
1657 __IO uint32_t BDTEUPR;
1658 __IO uint32_t BDMADR;
1659}HRTIM_Common_TypeDef;
1660
1661/* HRTIM register definition */
1662typedef struct {
1663 HRTIM_Master_TypeDef sMasterRegs;
1664 HRTIM_Timerx_TypeDef sTimerxRegs[5];
1665 uint32_t RESERVED0[32];
1666 HRTIM_Common_TypeDef sCommonRegs;
1667}HRTIM_TypeDef;
1672typedef struct
1673{
1674 __IO uint32_t CR;
1675 __IO uint32_t SR;
1676 __IO uint32_t DR;
1677} RNG_TypeDef;
1678
1683typedef struct
1684{
1685 __IO uint32_t CR;
1686 __IO uint32_t WRFR;
1687 __IO uint32_t CWRFR;
1688 __IO uint32_t RDFR;
1689 __IO uint32_t CRDFR;
1690 __IO uint32_t SR;
1691 __IO uint32_t CLRFR;
1692 uint32_t RESERVED[57];
1693 __IO uint32_t DINR0;
1694 __IO uint32_t DINR1;
1695 __IO uint32_t DINR2;
1696 __IO uint32_t DINR3;
1697 __IO uint32_t DINR4;
1698 __IO uint32_t DINR5;
1699 __IO uint32_t DINR6;
1700 __IO uint32_t DINR7;
1701 __IO uint32_t DINR8;
1702 __IO uint32_t DINR9;
1703 __IO uint32_t DINR10;
1704 __IO uint32_t DINR11;
1705 __IO uint32_t DINR12;
1706 __IO uint32_t DINR13;
1707 __IO uint32_t DINR14;
1708 __IO uint32_t DINR15;
1709 __IO uint32_t DINR16;
1710 __IO uint32_t DINR17;
1711 __IO uint32_t DINR18;
1712 __IO uint32_t DINR19;
1713 __IO uint32_t DINR20;
1714 __IO uint32_t DINR21;
1715 __IO uint32_t DINR22;
1716 __IO uint32_t DINR23;
1717 __IO uint32_t DINR24;
1718 __IO uint32_t DINR25;
1719 __IO uint32_t DINR26;
1720 __IO uint32_t DINR27;
1721 __IO uint32_t DINR28;
1722 __IO uint32_t DINR29;
1723 __IO uint32_t DINR30;
1724 __IO uint32_t DINR31;
1725 __IO uint32_t DOUTR0;
1726 __IO uint32_t DOUTR1;
1727 __IO uint32_t DOUTR2;
1728 __IO uint32_t DOUTR3;
1729 __IO uint32_t DOUTR4;
1730 __IO uint32_t DOUTR5;
1731 __IO uint32_t DOUTR6;
1732 __IO uint32_t DOUTR7;
1733 __IO uint32_t DOUTR8;
1734 __IO uint32_t DOUTR9;
1735 __IO uint32_t DOUTR10;
1736 __IO uint32_t DOUTR11;
1737 __IO uint32_t DOUTR12;
1738 __IO uint32_t DOUTR13;
1739 __IO uint32_t DOUTR14;
1740 __IO uint32_t DOUTR15;
1741 __IO uint32_t DOUTR16;
1742 __IO uint32_t DOUTR17;
1743 __IO uint32_t DOUTR18;
1744 __IO uint32_t DOUTR19;
1745 __IO uint32_t DOUTR20;
1746 __IO uint32_t DOUTR21;
1747 __IO uint32_t DOUTR22;
1748 __IO uint32_t DOUTR23;
1749 __IO uint32_t DOUTR24;
1750 __IO uint32_t DOUTR25;
1751 __IO uint32_t DOUTR26;
1752 __IO uint32_t DOUTR27;
1753 __IO uint32_t DOUTR28;
1754 __IO uint32_t DOUTR29;
1755 __IO uint32_t DOUTR30;
1756 __IO uint32_t DOUTR31;
1757} MDIOS_TypeDef;
1758
1759
1763typedef struct
1764{
1765 __IO uint32_t GOTGCTL;
1766 __IO uint32_t GOTGINT;
1767 __IO uint32_t GAHBCFG;
1768 __IO uint32_t GUSBCFG;
1769 __IO uint32_t GRSTCTL;
1770 __IO uint32_t GINTSTS;
1771 __IO uint32_t GINTMSK;
1772 __IO uint32_t GRXSTSR;
1773 __IO uint32_t GRXSTSP;
1774 __IO uint32_t GRXFSIZ;
1775 __IO uint32_t DIEPTXF0_HNPTXFSIZ;
1776 __IO uint32_t HNPTXSTS;
1777 uint32_t Reserved30[2];
1778 __IO uint32_t GCCFG;
1779 __IO uint32_t CID;
1780 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1781 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1782 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1783 __IO uint32_t GHWCFG3;
1784 uint32_t Reserved6;
1785 __IO uint32_t GLPMCFG;
1786 __IO uint32_t GPWRDN;
1787 __IO uint32_t GDFIFOCFG;
1788 __IO uint32_t GADPCTL;
1789 uint32_t Reserved43[39];
1790 __IO uint32_t HPTXFSIZ;
1791 __IO uint32_t DIEPTXF[0x0F];
1792} USB_OTG_GlobalTypeDef;
1793
1794
1798typedef struct
1799{
1800 __IO uint32_t DCFG;
1801 __IO uint32_t DCTL;
1802 __IO uint32_t DSTS;
1803 uint32_t Reserved0C;
1804 __IO uint32_t DIEPMSK;
1805 __IO uint32_t DOEPMSK;
1806 __IO uint32_t DAINT;
1807 __IO uint32_t DAINTMSK;
1808 uint32_t Reserved20;
1809 uint32_t Reserved9;
1810 __IO uint32_t DVBUSDIS;
1811 __IO uint32_t DVBUSPULSE;
1812 __IO uint32_t DTHRCTL;
1813 __IO uint32_t DIEPEMPMSK;
1814 __IO uint32_t DEACHINT;
1815 __IO uint32_t DEACHMSK;
1816 uint32_t Reserved40;
1817 __IO uint32_t DINEP1MSK;
1818 uint32_t Reserved44[15];
1819 __IO uint32_t DOUTEP1MSK;
1820} USB_OTG_DeviceTypeDef;
1821
1822
1826typedef struct
1827{
1828 __IO uint32_t DIEPCTL;
1829 uint32_t Reserved04;
1830 __IO uint32_t DIEPINT;
1831 uint32_t Reserved0C;
1832 __IO uint32_t DIEPTSIZ;
1833 __IO uint32_t DIEPDMA;
1834 __IO uint32_t DTXFSTS;
1835 uint32_t Reserved18;
1836} USB_OTG_INEndpointTypeDef;
1837
1838
1842typedef struct
1843{
1844 __IO uint32_t DOEPCTL;
1845 uint32_t Reserved04;
1846 __IO uint32_t DOEPINT;
1847 uint32_t Reserved0C;
1848 __IO uint32_t DOEPTSIZ;
1849 __IO uint32_t DOEPDMA;
1850 uint32_t Reserved18[2];
1851} USB_OTG_OUTEndpointTypeDef;
1852
1853
1857typedef struct
1858{
1859 __IO uint32_t HCFG;
1860 __IO uint32_t HFIR;
1861 __IO uint32_t HFNUM;
1862 uint32_t Reserved40C;
1863 __IO uint32_t HPTXSTS;
1864 __IO uint32_t HAINT;
1865 __IO uint32_t HAINTMSK;
1866} USB_OTG_HostTypeDef;
1867
1871typedef struct
1872{
1873 __IO uint32_t HCCHAR;
1874 __IO uint32_t HCSPLT;
1875 __IO uint32_t HCINT;
1876 __IO uint32_t HCINTMSK;
1877 __IO uint32_t HCTSIZ;
1878 __IO uint32_t HCDMA;
1879 uint32_t Reserved[2];
1880} USB_OTG_HostChannelTypeDef;
1890typedef struct
1891{
1892 uint32_t RESERVED0[2036];
1893 __IO uint32_t AXI_PERIPH_ID_4;
1894 uint32_t AXI_PERIPH_ID_5;
1895 uint32_t AXI_PERIPH_ID_6;
1896 uint32_t AXI_PERIPH_ID_7;
1897 __IO uint32_t AXI_PERIPH_ID_0;
1898 __IO uint32_t AXI_PERIPH_ID_1;
1899 __IO uint32_t AXI_PERIPH_ID_2;
1900 __IO uint32_t AXI_PERIPH_ID_3;
1901 __IO uint32_t AXI_COMP_ID_0;
1902 __IO uint32_t AXI_COMP_ID_1;
1903 __IO uint32_t AXI_COMP_ID_2;
1904 __IO uint32_t AXI_COMP_ID_3;
1905 uint32_t RESERVED1[2];
1906 __IO uint32_t AXI_TARG1_FN_MOD_ISS_BM;
1907 uint32_t RESERVED2[6];
1908 __IO uint32_t AXI_TARG1_FN_MOD2;
1909 uint32_t RESERVED3;
1910 __IO uint32_t AXI_TARG1_FN_MOD_LB;
1911 uint32_t RESERVED4[54];
1912 __IO uint32_t AXI_TARG1_FN_MOD;
1913 uint32_t RESERVED5[959];
1914 __IO uint32_t AXI_TARG2_FN_MOD_ISS_BM;
1915 uint32_t RESERVED6[6];
1916 __IO uint32_t AXI_TARG2_FN_MOD2;
1917 uint32_t RESERVED7;
1918 __IO uint32_t AXI_TARG2_FN_MOD_LB;
1919 uint32_t RESERVED8[54];
1920 __IO uint32_t AXI_TARG2_FN_MOD;
1921 uint32_t RESERVED9[959];
1922 __IO uint32_t AXI_TARG3_FN_MOD_ISS_BM;
1923 uint32_t RESERVED10[1023];
1924 __IO uint32_t AXI_TARG4_FN_MOD_ISS_BM;
1925 uint32_t RESERVED11[1023];
1926 __IO uint32_t AXI_TARG5_FN_MOD_ISS_BM;
1927 uint32_t RESERVED12[1023];
1928 __IO uint32_t AXI_TARG6_FN_MOD_ISS_BM;
1929 uint32_t RESERVED13[1023];
1930 __IO uint32_t AXI_TARG7_FN_MOD_ISS_BM;
1931 uint32_t RESERVED14[6];
1932 __IO uint32_t AXI_TARG7_FN_MOD2;
1933 uint32_t RESERVED15;
1934 __IO uint32_t AXI_TARG7_FN_MOD_LB;
1935 uint32_t RESERVED16[54];
1936 __IO uint32_t AXI_TARG7_FN_MOD;
1937 uint32_t RESERVED17[59334];
1938 __IO uint32_t AXI_INI1_FN_MOD2;
1939 __IO uint32_t AXI_INI1_FN_MOD_AHB;
1940 uint32_t RESERVED18[53];
1941 __IO uint32_t AXI_INI1_READ_QOS;
1942 __IO uint32_t AXI_INI1_WRITE_QOS;
1943 __IO uint32_t AXI_INI1_FN_MOD;
1944 uint32_t RESERVED19[1021];
1945 __IO uint32_t AXI_INI2_READ_QOS;
1946 __IO uint32_t AXI_INI2_WRITE_QOS;
1947 __IO uint32_t AXI_INI2_FN_MOD;
1948 uint32_t RESERVED20[966];
1949 __IO uint32_t AXI_INI3_FN_MOD2;
1950 __IO uint32_t AXI_INI3_FN_MOD_AHB;
1951 uint32_t RESERVED21[53];
1952 __IO uint32_t AXI_INI3_READ_QOS;
1953 __IO uint32_t AXI_INI3_WRITE_QOS;
1954 __IO uint32_t AXI_INI3_FN_MOD;
1955 uint32_t RESERVED22[1021];
1956 __IO uint32_t AXI_INI4_READ_QOS;
1957 __IO uint32_t AXI_INI4_WRITE_QOS;
1958 __IO uint32_t AXI_INI4_FN_MOD;
1959 uint32_t RESERVED23[1021];
1960 __IO uint32_t AXI_INI5_READ_QOS;
1961 __IO uint32_t AXI_INI5_WRITE_QOS;
1962 __IO uint32_t AXI_INI5_FN_MOD;
1963 uint32_t RESERVED24[1021];
1964 __IO uint32_t AXI_INI6_READ_QOS;
1965 __IO uint32_t AXI_INI6_WRITE_QOS;
1966 __IO uint32_t AXI_INI6_FN_MOD;
1968} GPV_TypeDef;
1969
1973#define D1_ITCMRAM_BASE (0x00000000UL)
1974#define D1_ITCMICP_BASE (0x00100000UL)
1975#define D1_DTCMRAM_BASE (0x20000000UL)
1976#define D1_AXIFLASH_BASE (0x08000000UL)
1977#define D1_AXIICP_BASE (0x1FF00000UL)
1978#define D1_AXISRAM_BASE (0x24000000UL)
1980#define D2_AXISRAM_BASE (0x10000000UL)
1981#define D2_AHBSRAM_BASE (0x30000000UL)
1983#define D3_BKPSRAM_BASE (0x38800000UL)
1984#define D3_SRAM_BASE (0x38000000UL)
1986#define PERIPH_BASE (0x40000000UL)
1987#define QSPI_BASE (0x90000000UL)
1989#define FLASH_BANK1_BASE (0x08000000UL)
1990#define FLASH_BANK2_BASE (0x08100000UL)
1991#define FLASH_END (0x081FFFFFUL)
1993/* Legacy define */
1994#define FLASH_BASE FLASH_BANK1_BASE
1995
1997#define UID_BASE (0x1FF1E800UL)
1998#define FLASHSIZE_BASE (0x1FF1E880UL)
2002#define D2_APB1PERIPH_BASE PERIPH_BASE
2003#define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2004#define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2005#define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
2006
2007#define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
2008#define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
2009
2010#define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
2011#define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
2012
2014#define APB1PERIPH_BASE PERIPH_BASE
2015#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2016#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2017#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
2018
2019
2022#define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)
2023#define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)
2024#define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)
2025#define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)
2026#define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)
2027#define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)
2028#define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)
2029#define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)
2030#define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)
2031
2034#define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)
2035#define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)
2036#define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)
2037#define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
2038#define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
2039#define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
2040#define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
2041#define ETH_MAC_BASE (ETH_BASE)
2042
2044#define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
2045#define USB2_OTG_FS_PERIPH_BASE (0x40080000UL)
2046#define USB_OTG_GLOBAL_BASE (0x000UL)
2047#define USB_OTG_DEVICE_BASE (0x800UL)
2048#define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
2049#define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
2050#define USB_OTG_EP_REG_SIZE (0x20UL)
2051#define USB_OTG_HOST_BASE (0x400UL)
2052#define USB_OTG_HOST_PORT_BASE (0x440UL)
2053#define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
2054#define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
2055#define USB_OTG_PCGCCTL_BASE (0xE00UL)
2056#define USB_OTG_FIFO_BASE (0x1000UL)
2057#define USB_OTG_FIFO_SIZE (0x1000UL)
2058
2061#define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)
2062#define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)
2063#define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)
2064#define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)
2065#define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)
2066
2068#define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)
2069#define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)
2070#define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)
2071#define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)
2072#define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)
2073#define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)
2074#define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)
2075#define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)
2076#define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL)
2077#define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
2078#define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
2079#define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
2080#define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
2081#define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
2082#define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
2083#define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)
2084#define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)
2085#define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)
2086#define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)
2087#define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)
2088
2090#define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)
2091
2093#define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)
2094#define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)
2095#define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)
2096#define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)
2097#define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)
2098#define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)
2099#define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)
2100#define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)
2101#define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)
2102#define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)
2103
2104
2105#define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)
2106#define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)
2107#define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)
2108#define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)
2109#define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)
2110#define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)
2111#define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)
2112#define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)
2113#define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)
2114#define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)
2115#define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)
2116#define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)
2117#define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)
2118#define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)
2119#define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)
2120#define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)
2121#define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2122#define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2123#define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)
2124#define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)
2125#define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)
2126#define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
2127#define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)
2128#define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)
2129
2132#define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)
2133#define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)
2134#define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)
2135#define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)
2136#define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)
2137#define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)
2138#define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)
2139#define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)
2140#define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)
2141#define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)
2142#define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)
2143#define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2144#define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2145#define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL)
2146#define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
2147#define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
2148#define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL)
2149#define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL)
2150#define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL)
2151#define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL)
2152#define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2153#define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2154#define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2155#define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2156#define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2157#define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2158#define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2159#define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2160#define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2161#define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2162#define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2163#define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2164#define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL)
2165#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL)
2166#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL)
2167#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL)
2168#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL)
2169#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL)
2170#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL)
2171
2172
2174#define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)
2175#define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2176#define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)
2177#define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)
2178#define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)
2179#define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)
2180#define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)
2181#define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)
2182#define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)
2183#define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)
2184#define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)
2185#define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)
2186#define COMP1_BASE (COMP12_BASE + 0x0CUL)
2187#define COMP2_BASE (COMP12_BASE + 0x10UL)
2188#define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)
2189#define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)
2190#define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)
2191
2192
2193#define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)
2194#define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)
2195#define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)
2196
2197
2198
2199
2200#define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)
2201#define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)
2202#define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)
2203#define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)
2204#define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)
2205#define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)
2206#define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)
2207#define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)
2208
2209#define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2210#define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2211#define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2212#define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2213#define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2214#define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2215#define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2216#define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2217
2218#define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2219#define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2220#define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2221#define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2222#define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2223#define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2224#define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2225#define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2226
2227#define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2228#define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2229
2230#define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2231#define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2232#define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2233#define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2234#define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2235#define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2236#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2237#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2238
2239#define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2240#define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2241#define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2242#define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2243#define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2244#define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2245#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2246#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2247
2248#define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2249#define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2250#define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2251#define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2252#define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2253#define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2254#define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2255#define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2256#define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2257#define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2258#define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2259#define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2260#define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2261#define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2262#define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2263#define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2264
2265#define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2266#define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2267#define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2268#define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2269#define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2270#define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2271#define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2272#define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2273
2274#define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2275#define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2276
2278#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2279#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2280#define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2281#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2282#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2283
2284/* Debug MCU registers base address */
2285#define DBGMCU_BASE (0x5C001000UL)
2286
2287#define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2288#define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2289#define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2290#define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2291#define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2292#define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2293#define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2294#define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2295#define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2296#define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2297#define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2298#define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2299#define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2300#define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2301#define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2302#define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2303
2304#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
2305#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
2306#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
2307#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
2308#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
2309
2310#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
2311#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
2312#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
2313#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
2314#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
2315
2316#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
2317#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
2318
2319
2320
2321#define GPV_BASE (PERIPH_BASE + 0x11000000UL)
2330#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2331#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2332#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2333#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2334#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2335#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2336#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2337#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2338#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2339#define RTC ((RTC_TypeDef *) RTC_BASE)
2340#define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2341
2342
2343#define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2344#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2345#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2346#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2347#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2348#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2349#define USART2 ((USART_TypeDef *) USART2_BASE)
2350#define USART3 ((USART_TypeDef *) USART3_BASE)
2351#define USART6 ((USART_TypeDef *) USART6_BASE)
2352#define UART7 ((USART_TypeDef *) UART7_BASE)
2353#define UART8 ((USART_TypeDef *) UART8_BASE)
2354#define CRS ((CRS_TypeDef *) CRS_BASE)
2355#define UART4 ((USART_TypeDef *) UART4_BASE)
2356#define UART5 ((USART_TypeDef *) UART5_BASE)
2357#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2358#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2359#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2360#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2361#define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2362#define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2363#define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2364#define CEC ((CEC_TypeDef *) CEC_BASE)
2365#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2366#define PWR ((PWR_TypeDef *) PWR_BASE)
2367#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2368#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2369#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2370#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2371#define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2372#define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
2373#define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
2374
2375#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2376#define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2377#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2378#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2379#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2380#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2381#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2382#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2383
2384
2385#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2386#define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2387#define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
2388#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2389#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2390#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2391#define USART1 ((USART_TypeDef *) USART1_BASE)
2392#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2393#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2394#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2395#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2396#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
2397#define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
2398#define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
2399#define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
2400#define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
2401#define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
2402#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
2403#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2404#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2405#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2406#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
2407#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2408#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2409#define SAI3 ((SAI_TypeDef *) SAI3_BASE)
2410#define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
2411#define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
2412#define SAI4 ((SAI_TypeDef *) SAI4_BASE)
2413#define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
2414#define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
2415
2416#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2417#define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2418#define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2419#define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2420#define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2421#define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2422#define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2423#define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2424#define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2425#define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2426#define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2427#define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2428#define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2429#define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2430#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2431#define RCC ((RCC_TypeDef *) RCC_BASE)
2432#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2433#define CRC ((CRC_TypeDef *) CRC_BASE)
2434
2435#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2436#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2437#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2438#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2439#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2440#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2441#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2442#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2443#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
2444#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2445#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2446
2447#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2448#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2449#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
2450#define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
2451#define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2452
2453#define RNG ((RNG_TypeDef *) RNG_BASE)
2454#define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2455#define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2456
2457#define BDMA ((BDMA_TypeDef *) BDMA_BASE)
2458#define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
2459#define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
2460#define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
2461#define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
2462#define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
2463#define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
2464#define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
2465#define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
2466
2467#define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)
2468#define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
2469#define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
2470#define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
2471#define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
2472#define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
2473
2474#define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)
2475#define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
2476#define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
2477#define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
2478#define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
2479#define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
2480
2481#define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)
2482#define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
2483#define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
2484
2485#define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2486#define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2487#define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2488#define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2489#define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2490#define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2491#define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2492#define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2493#define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2494
2495
2496#define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2497#define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2498#define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2499#define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2500#define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2501#define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2502#define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2503#define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2504
2505#define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2506#define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2507
2508#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2509#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2510#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2511#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2512#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2513#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2514#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2515#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2516#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2517
2518#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2519#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2520#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2521#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2522#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2523#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2524#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2525#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2526#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2527
2528
2529#define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2530#define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2531#define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2532#define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2533#define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2534#define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2535#define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2536#define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2537#define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2538#define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2539#define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2540#define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2541#define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2542#define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2543#define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2544#define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2545#define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2546
2547#define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2548#define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2549#define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2550#define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2551#define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2552#define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2553#define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2554#define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2555
2556#define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2557#define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2558
2559
2560#define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2561#define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2562#define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2563#define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2564#define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2565
2566
2567#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
2568#define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
2569#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2570#define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2571
2572#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2573
2574#define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2575#define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2576
2577
2578#define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2579
2580#define ETH ((ETH_TypeDef *)ETH_BASE)
2581#define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2582#define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2583#define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2584#define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2585#define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2586#define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2587#define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2588#define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2589#define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2590#define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2591#define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2592#define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2593#define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2594#define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2595#define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2596#define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2597#define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2598
2599
2600#define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2601#define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
2602
2603/* Legacy defines */
2604#define USB_OTG_HS USB1_OTG_HS
2605#define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2606#define USB_OTG_FS USB2_OTG_FS
2607#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
2608
2609#define GPV ((GPV_TypeDef *) GPV_BASE)
2610
2622#define LSI_STARTUP_TIME 130U
2632/******************************************************************************/
2633/* Peripheral Registers_Bits_Definition */
2634/******************************************************************************/
2635
2636/******************************************************************************/
2637/* */
2638/* Analog to Digital Converter */
2639/* */
2640/******************************************************************************/
2641/******************************* ADC VERSION ********************************/
2642#define ADC_VER_V5_X
2643/******************** Bit definition for ADC_ISR register ********************/
2644#define ADC_ISR_ADRDY_Pos (0U)
2645#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos)
2646#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk
2647#define ADC_ISR_EOSMP_Pos (1U)
2648#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos)
2649#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk
2650#define ADC_ISR_EOC_Pos (2U)
2651#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos)
2652#define ADC_ISR_EOC ADC_ISR_EOC_Msk
2653#define ADC_ISR_EOS_Pos (3U)
2654#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos)
2655#define ADC_ISR_EOS ADC_ISR_EOS_Msk
2656#define ADC_ISR_OVR_Pos (4U)
2657#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos)
2658#define ADC_ISR_OVR ADC_ISR_OVR_Msk
2659#define ADC_ISR_JEOC_Pos (5U)
2660#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos)
2661#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk
2662#define ADC_ISR_JEOS_Pos (6U)
2663#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos)
2664#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk
2665#define ADC_ISR_AWD1_Pos (7U)
2666#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos)
2667#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk
2668#define ADC_ISR_AWD2_Pos (8U)
2669#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos)
2670#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk
2671#define ADC_ISR_AWD3_Pos (9U)
2672#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos)
2673#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk
2674#define ADC_ISR_JQOVF_Pos (10U)
2675#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos)
2676#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk
2677#define ADC_ISR_LDORDY_Pos (12U)
2678#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos)
2679#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk
2681/******************** Bit definition for ADC_IER register ********************/
2682#define ADC_IER_ADRDYIE_Pos (0U)
2683#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos)
2684#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk
2685#define ADC_IER_EOSMPIE_Pos (1U)
2686#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos)
2687#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk
2688#define ADC_IER_EOCIE_Pos (2U)
2689#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos)
2690#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk
2691#define ADC_IER_EOSIE_Pos (3U)
2692#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos)
2693#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk
2694#define ADC_IER_OVRIE_Pos (4U)
2695#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos)
2696#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk
2697#define ADC_IER_JEOCIE_Pos (5U)
2698#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos)
2699#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk
2700#define ADC_IER_JEOSIE_Pos (6U)
2701#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos)
2702#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk
2703#define ADC_IER_AWD1IE_Pos (7U)
2704#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos)
2705#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk
2706#define ADC_IER_AWD2IE_Pos (8U)
2707#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos)
2708#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk
2709#define ADC_IER_AWD3IE_Pos (9U)
2710#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos)
2711#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk
2712#define ADC_IER_JQOVFIE_Pos (10U)
2713#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos)
2714#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk
2716/******************** Bit definition for ADC_CR register ********************/
2717#define ADC_CR_ADEN_Pos (0U)
2718#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos)
2719#define ADC_CR_ADEN ADC_CR_ADEN_Msk
2720#define ADC_CR_ADDIS_Pos (1U)
2721#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos)
2722#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk
2723#define ADC_CR_ADSTART_Pos (2U)
2724#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos)
2725#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk
2726#define ADC_CR_JADSTART_Pos (3U)
2727#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos)
2728#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk
2729#define ADC_CR_ADSTP_Pos (4U)
2730#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos)
2731#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk
2732#define ADC_CR_JADSTP_Pos (5U)
2733#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos)
2734#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk
2735#define ADC_CR_BOOST_Pos (8U)
2736#define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos)
2737#define ADC_CR_BOOST ADC_CR_BOOST_Msk
2738#define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos)
2739#define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos)
2740#define ADC_CR_ADCALLIN_Pos (16U)
2741#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos)
2742#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk
2743#define ADC_CR_LINCALRDYW1_Pos (22U)
2744#define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos)
2745#define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk
2746#define ADC_CR_LINCALRDYW2_Pos (23U)
2747#define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos)
2748#define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk
2749#define ADC_CR_LINCALRDYW3_Pos (24U)
2750#define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos)
2751#define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk
2752#define ADC_CR_LINCALRDYW4_Pos (25U)
2753#define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos)
2754#define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk
2755#define ADC_CR_LINCALRDYW5_Pos (26U)
2756#define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos)
2757#define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk
2758#define ADC_CR_LINCALRDYW6_Pos (27U)
2759#define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos)
2760#define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk
2761#define ADC_CR_ADVREGEN_Pos (28U)
2762#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos)
2763#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk
2764#define ADC_CR_DEEPPWD_Pos (29U)
2765#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos)
2766#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk
2767#define ADC_CR_ADCALDIF_Pos (30U)
2768#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos)
2769#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk
2770#define ADC_CR_ADCAL_Pos (31U)
2771#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos)
2772#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk
2774/******************** Bit definition for ADC_CFGR register ********************/
2775#define ADC_CFGR_DMNGT_Pos (0U)
2776#define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos)
2777#define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk
2778#define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos)
2779#define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos)
2781#define ADC_CFGR_RES_Pos (2U)
2782#define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos)
2783#define ADC_CFGR_RES ADC_CFGR_RES_Msk
2784#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos)
2785#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos)
2786#define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos)
2788#define ADC_CFGR_EXTSEL_Pos (5U)
2789#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos)
2790#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk
2791#define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos)
2792#define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos)
2793#define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos)
2794#define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos)
2795#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos)
2797#define ADC_CFGR_EXTEN_Pos (10U)
2798#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos)
2799#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk
2800#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos)
2801#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos)
2803#define ADC_CFGR_OVRMOD_Pos (12U)
2804#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos)
2805#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk
2806#define ADC_CFGR_CONT_Pos (13U)
2807#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos)
2808#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk
2809#define ADC_CFGR_AUTDLY_Pos (14U)
2810#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos)
2811#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk
2813#define ADC_CFGR_DISCEN_Pos (16U)
2814#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos)
2815#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk
2817#define ADC_CFGR_DISCNUM_Pos (17U)
2818#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos)
2819#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk
2820#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos)
2821#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos)
2822#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos)
2824#define ADC_CFGR_JDISCEN_Pos (20U)
2825#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos)
2826#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk
2827#define ADC_CFGR_JQM_Pos (21U)
2828#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos)
2829#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk
2830#define ADC_CFGR_AWD1SGL_Pos (22U)
2831#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos)
2832#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk
2833#define ADC_CFGR_AWD1EN_Pos (23U)
2834#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos)
2835#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk
2836#define ADC_CFGR_JAWD1EN_Pos (24U)
2837#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos)
2838#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk
2839#define ADC_CFGR_JAUTO_Pos (25U)
2840#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos)
2841#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk
2843#define ADC_CFGR_AWD1CH_Pos (26U)
2844#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos)
2845#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk
2846#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos)
2847#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos)
2848#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos)
2849#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos)
2850#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos)
2852#define ADC_CFGR_JQDIS_Pos (31U)
2853#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos)
2854#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk
2856/******************** Bit definition for ADC_CFGR2 register ********************/
2857#define ADC_CFGR2_ROVSE_Pos (0U)
2858#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos)
2859#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk
2860#define ADC_CFGR2_JOVSE_Pos (1U)
2861#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos)
2862#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk
2864#define ADC_CFGR2_OVSS_Pos (5U)
2865#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos)
2866#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk
2867#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos)
2868#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos)
2869#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos)
2870#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos)
2872#define ADC_CFGR2_TROVS_Pos (9U)
2873#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos)
2874#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk
2875#define ADC_CFGR2_ROVSM_Pos (10U)
2876#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos)
2877#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk
2879#define ADC_CFGR2_RSHIFT1_Pos (11U)
2880#define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos)
2881#define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk
2882#define ADC_CFGR2_RSHIFT2_Pos (12U)
2883#define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos)
2884#define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk
2885#define ADC_CFGR2_RSHIFT3_Pos (13U)
2886#define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos)
2887#define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk
2888#define ADC_CFGR2_RSHIFT4_Pos (14U)
2889#define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos)
2890#define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk
2892#define ADC_CFGR2_OVSR_Pos (16U)
2893#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos)
2894#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk
2895#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos)
2896#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos)
2897#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos)
2898#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos)
2899#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos)
2900#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos)
2901#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos)
2902#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos)
2903#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos)
2904#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos)
2906#define ADC_CFGR2_LSHIFT_Pos (28U)
2907#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos)
2908#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk
2909#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos)
2910#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos)
2911#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos)
2912#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos)
2914/******************** Bit definition for ADC_SMPR1 register ********************/
2915#define ADC_SMPR1_SMP0_Pos (0U)
2916#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos)
2917#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk
2918#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos)
2919#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos)
2920#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos)
2922#define ADC_SMPR1_SMP1_Pos (3U)
2923#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos)
2924#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk
2925#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos)
2926#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos)
2927#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos)
2929#define ADC_SMPR1_SMP2_Pos (6U)
2930#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos)
2931#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk
2932#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos)
2933#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos)
2934#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos)
2936#define ADC_SMPR1_SMP3_Pos (9U)
2937#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos)
2938#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk
2939#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos)
2940#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos)
2941#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos)
2943#define ADC_SMPR1_SMP4_Pos (12U)
2944#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos)
2945#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk
2946#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos)
2947#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos)
2948#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos)
2950#define ADC_SMPR1_SMP5_Pos (15U)
2951#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos)
2952#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk
2953#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos)
2954#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos)
2955#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos)
2957#define ADC_SMPR1_SMP6_Pos (18U)
2958#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos)
2959#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk
2960#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos)
2961#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos)
2962#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos)
2964#define ADC_SMPR1_SMP7_Pos (21U)
2965#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos)
2966#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk
2967#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos)
2968#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos)
2969#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos)
2971#define ADC_SMPR1_SMP8_Pos (24U)
2972#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos)
2973#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk
2974#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos)
2975#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos)
2976#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos)
2978#define ADC_SMPR1_SMP9_Pos (27U)
2979#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos)
2980#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk
2981#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos)
2982#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos)
2983#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos)
2985/******************** Bit definition for ADC_SMPR2 register ********************/
2986#define ADC_SMPR2_SMP10_Pos (0U)
2987#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos)
2988#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk
2989#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos)
2990#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos)
2991#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos)
2993#define ADC_SMPR2_SMP11_Pos (3U)
2994#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos)
2995#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk
2996#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos)
2997#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos)
2998#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos)
3000#define ADC_SMPR2_SMP12_Pos (6U)
3001#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos)
3002#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk
3003#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos)
3004#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos)
3005#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos)
3007#define ADC_SMPR2_SMP13_Pos (9U)
3008#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos)
3009#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk
3010#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos)
3011#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos)
3012#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos)
3014#define ADC_SMPR2_SMP14_Pos (12U)
3015#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos)
3016#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk
3017#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos)
3018#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos)
3019#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos)
3021#define ADC_SMPR2_SMP15_Pos (15U)
3022#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos)
3023#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk
3024#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos)
3025#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos)
3026#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos)
3028#define ADC_SMPR2_SMP16_Pos (18U)
3029#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos)
3030#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk
3031#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos)
3032#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos)
3033#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos)
3035#define ADC_SMPR2_SMP17_Pos (21U)
3036#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos)
3037#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk
3038#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos)
3039#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos)
3040#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos)
3042#define ADC_SMPR2_SMP18_Pos (24U)
3043#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos)
3044#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk
3045#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos)
3046#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos)
3047#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos)
3049#define ADC_SMPR2_SMP19_Pos (27U)
3050#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos)
3051#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk
3052#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos)
3053#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos)
3054#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos)
3056/******************** Bit definition for ADC_PCSEL register ********************/
3057#define ADC_PCSEL_PCSEL_Pos (0U)
3058#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)
3059#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk
3060#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos)
3061#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos)
3062#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos)
3063#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos)
3064#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos)
3065#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos)
3066#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos)
3067#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos)
3068#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos)
3069#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos)
3070#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos)
3071#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos)
3072#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos)
3073#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos)
3074#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos)
3075#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos)
3076#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos)
3077#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos)
3078#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos)
3079#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos)
3081/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
3082#define ADC_LTR_LT_Pos (0U)
3083#define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos)
3084#define ADC_LTR_LT ADC_LTR_LT_Msk
3086/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
3087#define ADC_HTR_HT_Pos (0U)
3088#define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos)
3089#define ADC_HTR_HT ADC_HTR_HT_Msk
3092/******************** Bit definition for ADC_SQR1 register ********************/
3093#define ADC_SQR1_L_Pos (0U)
3094#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)
3095#define ADC_SQR1_L ADC_SQR1_L_Msk
3096#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)
3097#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)
3098#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)
3099#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)
3101#define ADC_SQR1_SQ1_Pos (6U)
3102#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos)
3103#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk
3104#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos)
3105#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos)
3106#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos)
3107#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos)
3108#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos)
3110#define ADC_SQR1_SQ2_Pos (12U)
3111#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos)
3112#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk
3113#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos)
3114#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos)
3115#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos)
3116#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos)
3117#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos)
3119#define ADC_SQR1_SQ3_Pos (18U)
3120#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos)
3121#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk
3122#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos)
3123#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos)
3124#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos)
3125#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos)
3126#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos)
3128#define ADC_SQR1_SQ4_Pos (24U)
3129#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos)
3130#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk
3131#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos)
3132#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos)
3133#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos)
3134#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos)
3135#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos)
3137/******************** Bit definition for ADC_SQR2 register ********************/
3138#define ADC_SQR2_SQ5_Pos (0U)
3139#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos)
3140#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk
3141#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos)
3142#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos)
3143#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos)
3144#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos)
3145#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos)
3147#define ADC_SQR2_SQ6_Pos (6U)
3148#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos)
3149#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk
3150#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos)
3151#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos)
3152#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos)
3153#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos)
3154#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos)
3156#define ADC_SQR2_SQ7_Pos (12U)
3157#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)
3158#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk
3159#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)
3160#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)
3161#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)
3162#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)
3163#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)
3165#define ADC_SQR2_SQ8_Pos (18U)
3166#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)
3167#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk
3168#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)
3169#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)
3170#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)
3171#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)
3172#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)
3174#define ADC_SQR2_SQ9_Pos (24U)
3175#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)
3176#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk
3177#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)
3178#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)
3179#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)
3180#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)
3181#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)
3183/******************** Bit definition for ADC_SQR3 register ********************/
3184#define ADC_SQR3_SQ10_Pos (0U)
3185#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos)
3186#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk
3187#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos)
3188#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos)
3189#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos)
3190#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos)
3191#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos)
3193#define ADC_SQR3_SQ11_Pos (6U)
3194#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos)
3195#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk
3196#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos)
3197#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos)
3198#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos)
3199#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos)
3200#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos)
3202#define ADC_SQR3_SQ12_Pos (12U)
3203#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos)
3204#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk
3205#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos)
3206#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos)
3207#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos)
3208#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos)
3209#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos)
3211#define ADC_SQR3_SQ13_Pos (18U)
3212#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos)
3213#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk
3214#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos)
3215#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos)
3216#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos)
3217#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos)
3218#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos)
3220#define ADC_SQR3_SQ14_Pos (24U)
3221#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos)
3222#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk
3223#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos)
3224#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos)
3225#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos)
3226#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos)
3227#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos)
3229/******************** Bit definition for ADC_SQR4 register ********************/
3230#define ADC_SQR4_SQ15_Pos (0U)
3231#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos)
3232#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk
3233#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos)
3234#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos)
3235#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos)
3236#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos)
3237#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos)
3239#define ADC_SQR4_SQ16_Pos (6U)
3240#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos)
3241#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk
3242#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos)
3243#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos)
3244#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos)
3245#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos)
3246#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos)
3247/******************** Bit definition for ADC_DR register ********************/
3248#define ADC_DR_RDATA_Pos (0U)
3249#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)
3250#define ADC_DR_RDATA ADC_DR_RDATA_Msk
3252/******************** Bit definition for ADC_JSQR register ********************/
3253#define ADC_JSQR_JL_Pos (0U)
3254#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)
3255#define ADC_JSQR_JL ADC_JSQR_JL_Msk
3256#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)
3257#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)
3259#define ADC_JSQR_JEXTSEL_Pos (2U)
3260#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos)
3261#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk
3262#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos)
3263#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos)
3264#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos)
3265#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos)
3266#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos)
3268#define ADC_JSQR_JEXTEN_Pos (7U)
3269#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos)
3270#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk
3271#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos)
3272#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos)
3274#define ADC_JSQR_JSQ1_Pos (9U)
3275#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)
3276#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk
3277#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)
3278#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)
3279#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)
3280#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)
3281#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)
3283#define ADC_JSQR_JSQ2_Pos (15U)
3284#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)
3285#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk
3286#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)
3287#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)
3288#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)
3289#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)
3290#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)
3292#define ADC_JSQR_JSQ3_Pos (21U)
3293#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)
3294#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk
3295#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)
3296#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)
3297#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)
3298#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)
3299#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)
3301#define ADC_JSQR_JSQ4_Pos (27U)
3302#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)
3303#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk
3304#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)
3305#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)
3306#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)
3307#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)
3308#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)
3310/******************** Bit definition for ADC_OFR1 register ********************/
3311#define ADC_OFR1_OFFSET1_Pos (0U)
3312#define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos)
3313#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk
3314#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos)
3315#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos)
3316#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos)
3317#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos)
3318#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos)
3319#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos)
3320#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos)
3321#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos)
3322#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos)
3323#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos)
3324#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos)
3325#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos)
3326#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos)
3327#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos)
3328#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos)
3329#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos)
3330#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos)
3331#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos)
3332#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos)
3333#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos)
3334#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos)
3335#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos)
3336#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos)
3337#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos)
3338#define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos)
3339#define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos)
3341#define ADC_OFR1_OFFSET1_CH_Pos (26U)
3342#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)
3343#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk
3344#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)
3345#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)
3346#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)
3347#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)
3348#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)
3350#define ADC_OFR1_SSATE_Pos (31U)
3351#define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos)
3352#define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk
3355/******************** Bit definition for ADC_OFR2 register ********************/
3356#define ADC_OFR2_OFFSET2_Pos (0U)
3357#define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos)
3358#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk
3359#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos)
3360#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos)
3361#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos)
3362#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos)
3363#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos)
3364#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos)
3365#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos)
3366#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos)
3367#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos)
3368#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos)
3369#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos)
3370#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos)
3371#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos)
3372#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos)
3373#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos)
3374#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos)
3375#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos)
3376#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos)
3377#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos)
3378#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos)
3379#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos)
3380#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos)
3381#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos)
3382#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos)
3383#define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos)
3384#define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos)
3386#define ADC_OFR2_OFFSET2_CH_Pos (26U)
3387#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)
3388#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk
3389#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)
3390#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)
3391#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)
3392#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)
3393#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)
3395#define ADC_OFR2_SSATE_Pos (31U)
3396#define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos)
3397#define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk
3400/******************** Bit definition for ADC_OFR3 register ********************/
3401#define ADC_OFR3_OFFSET3_Pos (0U)
3402#define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos)
3403#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk
3404#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos)
3405#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos)
3406#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos)
3407#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos)
3408#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos)
3409#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos)
3410#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos)
3411#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos)
3412#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos)
3413#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos)
3414#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos)
3415#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos)
3416#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos)
3417#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos)
3418#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos)
3419#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos)
3420#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos)
3421#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos)
3422#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos)
3423#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos)
3424#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos)
3425#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos)
3426#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos)
3427#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos)
3428#define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos)
3429#define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos)
3431#define ADC_OFR3_OFFSET3_CH_Pos (26U)
3432#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)
3433#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk
3434#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)
3435#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)
3436#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)
3437#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)
3438#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)
3440#define ADC_OFR3_SSATE_Pos (31U)
3441#define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos)
3442#define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk
3445/******************** Bit definition for ADC_OFR4 register ********************/
3446#define ADC_OFR4_OFFSET4_Pos (0U)
3447#define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos)
3448#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk
3449#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos)
3450#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos)
3451#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos)
3452#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos)
3453#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos)
3454#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos)
3455#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos)
3456#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos)
3457#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos)
3458#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos)
3459#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos)
3460#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos)
3461#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos)
3462#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos)
3463#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos)
3464#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos)
3465#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos)
3466#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos)
3467#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos)
3468#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos)
3469#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos)
3470#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos)
3471#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos)
3472#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos)
3473#define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos)
3474#define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos)
3476#define ADC_OFR4_OFFSET4_CH_Pos (26U)
3477#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)
3478#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk
3479#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)
3480#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)
3481#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)
3482#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)
3483#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)
3485#define ADC_OFR4_SSATE_Pos (31U)
3486#define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos)
3487#define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk
3490/******************** Bit definition for ADC_JDR1 register ********************/
3491#define ADC_JDR1_JDATA_Pos (0U)
3492#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)
3493#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk
3494#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos)
3495#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos)
3496#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos)
3497#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos)
3498#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos)
3499#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos)
3500#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos)
3501#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos)
3502#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos)
3503#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos)
3504#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos)
3505#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos)
3506#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos)
3507#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos)
3508#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos)
3509#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos)
3510#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos)
3511#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos)
3512#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos)
3513#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos)
3514#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos)
3515#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos)
3516#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos)
3517#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos)
3518#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos)
3519#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos)
3520#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos)
3521#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos)
3522#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos)
3523#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos)
3524#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos)
3525#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos)
3527/******************** Bit definition for ADC_JDR2 register ********************/
3528#define ADC_JDR2_JDATA_Pos (0U)
3529#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)
3530#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk
3531#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos)
3532#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos)
3533#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos)
3534#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos)
3535#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos)
3536#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos)
3537#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos)
3538#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos)
3539#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos)
3540#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos)
3541#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos)
3542#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos)
3543#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos)
3544#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos)
3545#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos)
3546#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos)
3547#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos)
3548#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos)
3549#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos)
3550#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos)
3551#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos)
3552#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos)
3553#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos)
3554#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos)
3555#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos)
3556#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos)
3557#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos)
3558#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos)
3559#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos)
3560#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos)
3561#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos)
3562#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos)
3564/******************** Bit definition for ADC_JDR3 register ********************/
3565#define ADC_JDR3_JDATA_Pos (0U)
3566#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)
3567#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk
3568#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos)
3569#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos)
3570#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos)
3571#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos)
3572#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos)
3573#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos)
3574#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos)
3575#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos)
3576#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos)
3577#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos)
3578#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos)
3579#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos)
3580#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos)
3581#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos)
3582#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos)
3583#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos)
3584#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos)
3585#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos)
3586#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos)
3587#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos)
3588#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos)
3589#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos)
3590#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos)
3591#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos)
3592#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos)
3593#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos)
3594#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos)
3595#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos)
3596#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos)
3597#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos)
3598#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos)
3599#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos)
3601/******************** Bit definition for ADC_JDR4 register ********************/
3602#define ADC_JDR4_JDATA_Pos (0U)
3603#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)
3604#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk
3605#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos)
3606#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos)
3607#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos)
3608#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos)
3609#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos)
3610#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos)
3611#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos)
3612#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos)
3613#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos)
3614#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos)
3615#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos)
3616#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos)
3617#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos)
3618#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos)
3619#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos)
3620#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos)
3621#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos)
3622#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos)
3623#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos)
3624#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos)
3625#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos)
3626#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos)
3627#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos)
3628#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos)
3629#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos)
3630#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos)
3631#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos)
3632#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos)
3633#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos)
3634#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos)
3635#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos)
3636#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos)
3638/******************** Bit definition for ADC_AWD2CR register ********************/
3639#define ADC_AWD2CR_AWD2CH_Pos (0U)
3640#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)
3641#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk
3642#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)
3643#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)
3644#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)
3645#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)
3646#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)
3647#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)
3648#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)
3649#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)
3650#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)
3651#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)
3652#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)
3653#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)
3654#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)
3655#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)
3656#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)
3657#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)
3658#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)
3659#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)
3660#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)
3661#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)
3663/******************** Bit definition for ADC_AWD3CR register ********************/
3664#define ADC_AWD3CR_AWD3CH_Pos (0U)
3665#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)
3666#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk
3667#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)
3668#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)
3669#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)
3670#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)
3671#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)
3672#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)
3673#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)
3674#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)
3675#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)
3676#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)
3677#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)
3678#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)
3679#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)
3680#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)
3681#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)
3682#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)
3683#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)
3684#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)
3685#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)
3686#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)
3688/******************** Bit definition for ADC_DIFSEL register ********************/
3689#define ADC_DIFSEL_DIFSEL_Pos (0U)
3690#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)
3691#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk
3692#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)
3693#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)
3694#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)
3695#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)
3696#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)
3697#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)
3698#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)
3699#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)
3700#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)
3701#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)
3702#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)
3703#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)
3704#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)
3705#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)
3706#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)
3707#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)
3708#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)
3709#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)
3710#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)
3711#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)
3713/******************** Bit definition for ADC_CALFACT register ********************/
3714#define ADC_CALFACT_CALFACT_S_Pos (0U)
3715#define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos)
3716#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk
3717#define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos)
3718#define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos)
3719#define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos)
3720#define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos)
3721#define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos)
3722#define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos)
3723#define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos)
3724#define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos)
3725#define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos)
3726#define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos)
3727#define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos)
3728#define ADC_CALFACT_CALFACT_D_Pos (16U)
3729#define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos)
3730#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk
3731#define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos)
3732#define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos)
3733#define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos)
3734#define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos)
3735#define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos)
3736#define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos)
3737#define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos)
3738#define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos)
3739#define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos)
3740#define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos)
3741#define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos)
3743/******************** Bit definition for ADC_CALFACT2 register ********************/
3744#define ADC_CALFACT2_LINCALFACT_Pos (0U)
3745#define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos)
3746#define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk
3747#define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos)
3748#define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos)
3749#define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos)
3750#define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos)
3751#define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos)
3752#define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos)
3753#define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos)
3754#define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos)
3755#define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos)
3756#define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos)
3757#define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos)
3758#define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos)
3759#define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos)
3760#define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos)
3761#define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos)
3762#define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos)
3763#define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos)
3764#define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos)
3765#define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos)
3766#define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos)
3767#define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos)
3768#define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos)
3769#define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos)
3770#define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos)
3771#define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3772#define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3773#define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3774#define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3775#define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3776#define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos)
3778/************************* ADC Common registers *****************************/
3779/******************** Bit definition for ADC_CSR register ********************/
3780#define ADC_CSR_ADRDY_MST_Pos (0U)
3781#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos)
3782#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk
3783#define ADC_CSR_EOSMP_MST_Pos (1U)
3784#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos)
3785#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk
3786#define ADC_CSR_EOC_MST_Pos (2U)
3787#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos)
3788#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk
3789#define ADC_CSR_EOS_MST_Pos (3U)
3790#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos)
3791#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk
3792#define ADC_CSR_OVR_MST_Pos (4U)
3793#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos)
3794#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk
3795#define ADC_CSR_JEOC_MST_Pos (5U)
3796#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos)
3797#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk
3798#define ADC_CSR_JEOS_MST_Pos (6U)
3799#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos)
3800#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk
3801#define ADC_CSR_AWD1_MST_Pos (7U)
3802#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos)
3803#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk
3804#define ADC_CSR_AWD2_MST_Pos (8U)
3805#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos)
3806#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk
3807#define ADC_CSR_AWD3_MST_Pos (9U)
3808#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos)
3809#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk
3810#define ADC_CSR_JQOVF_MST_Pos (10U)
3811#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos)
3812#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk
3813#define ADC_CSR_ADRDY_SLV_Pos (16U)
3814#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos)
3815#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk
3816#define ADC_CSR_EOSMP_SLV_Pos (17U)
3817#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos)
3818#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk
3819#define ADC_CSR_EOC_SLV_Pos (18U)
3820#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos)
3821#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk
3822#define ADC_CSR_EOS_SLV_Pos (19U)
3823#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos)
3824#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk
3825#define ADC_CSR_OVR_SLV_Pos (20U)
3826#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos)
3827#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk
3828#define ADC_CSR_JEOC_SLV_Pos (21U)
3829#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos)
3830#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk
3831#define ADC_CSR_JEOS_SLV_Pos (22U)
3832#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos)
3833#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk
3834#define ADC_CSR_AWD1_SLV_Pos (23U)
3835#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos)
3836#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk
3837#define ADC_CSR_AWD2_SLV_Pos (24U)
3838#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos)
3839#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk
3840#define ADC_CSR_AWD3_SLV_Pos (25U)
3841#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos)
3842#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk
3843#define ADC_CSR_JQOVF_SLV_Pos (26U)
3844#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos)
3845#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk
3847/******************** Bit definition for ADC_CCR register ********************/
3848#define ADC_CCR_DUAL_Pos (0U)
3849#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos)
3850#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk
3851#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos)
3852#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos)
3853#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos)
3854#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos)
3855#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos)
3857#define ADC_CCR_DELAY_Pos (8U)
3858#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos)
3859#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk
3860#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos)
3861#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos)
3862#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos)
3863#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos)
3866#define ADC_CCR_DAMDF_Pos (14U)
3867#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos)
3868#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk
3869#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos)
3870#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos)
3872#define ADC_CCR_CKMODE_Pos (16U)
3873#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos)
3874#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk
3875#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos)
3876#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos)
3878#define ADC_CCR_PRESC_Pos (18U)
3879#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos)
3880#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk
3881#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos)
3882#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos)
3883#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos)
3884#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos)
3886#define ADC_CCR_VREFEN_Pos (22U)
3887#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos)
3888#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk
3889#define ADC_CCR_TSEN_Pos (23U)
3890#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos)
3891#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk
3892#define ADC_CCR_VBATEN_Pos (24U)
3893#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos)
3894#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk
3896/******************** Bit definition for ADC_CDR register *******************/
3897#define ADC_CDR_RDATA_MST_Pos (0U)
3898#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)
3899#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk
3901#define ADC_CDR_RDATA_SLV_Pos (16U)
3902#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)
3903#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk
3905/******************** Bit definition for ADC_CDR2 register ******************/
3906#define ADC_CDR2_RDATA_ALT_Pos (0U)
3907#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos)
3908#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk
3911/******************************************************************************/
3912/* */
3913/* VREFBUF */
3914/* */
3915/******************************************************************************/
3916/******************* Bit definition for VREFBUF_CSR register ****************/
3917#define VREFBUF_CSR_ENVR_Pos (0U)
3918#define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos)
3919#define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk
3920#define VREFBUF_CSR_HIZ_Pos (1U)
3921#define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos)
3922#define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk
3923#define VREFBUF_CSR_VRR_Pos (3U)
3924#define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos)
3925#define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk
3926#define VREFBUF_CSR_VRS_Pos (4U)
3927#define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos)
3928#define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk
3930#define VREFBUF_CSR_VRS_OUT1 (0U)
3931#define VREFBUF_CSR_VRS_OUT2_Pos (4U)
3932#define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)
3933#define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk
3934#define VREFBUF_CSR_VRS_OUT3_Pos (5U)
3935#define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)
3936#define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk
3937#define VREFBUF_CSR_VRS_OUT4_Pos (4U)
3938#define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)
3939#define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk
3941/******************* Bit definition for VREFBUF_CCR register ****************/
3942#define VREFBUF_CCR_TRIM_Pos (0U)
3943#define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos)
3944#define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk
3946/******************************************************************************/
3947/* */
3948/* Flexible Datarate Controller Area Network */
3949/* */
3950/******************************************************************************/
3952/***************** Bit definition for FDCAN_CREL register *******************/
3953#define FDCAN_CREL_DAY_Pos (0U)
3954#define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos)
3955#define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk
3956#define FDCAN_CREL_MON_Pos (8U)
3957#define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos)
3958#define FDCAN_CREL_MON FDCAN_CREL_MON_Msk
3959#define FDCAN_CREL_YEAR_Pos (16U)
3960#define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos)
3961#define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk
3962#define FDCAN_CREL_SUBSTEP_Pos (20U)
3963#define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos)
3964#define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk
3965#define FDCAN_CREL_STEP_Pos (24U)
3966#define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos)
3967#define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk
3968#define FDCAN_CREL_REL_Pos (28U)
3969#define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos)
3970#define FDCAN_CREL_REL FDCAN_CREL_REL_Msk
3972/***************** Bit definition for FDCAN_ENDN register *******************/
3973#define FDCAN_ENDN_ETV_Pos (0U)
3974#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)
3975#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk
3977/***************** Bit definition for FDCAN_DBTP register *******************/
3978#define FDCAN_DBTP_DSJW_Pos (0U)
3979#define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos)
3980#define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk
3981#define FDCAN_DBTP_DTSEG2_Pos (4U)
3982#define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos)
3983#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk
3984#define FDCAN_DBTP_DTSEG1_Pos (8U)
3985#define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)
3986#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk
3987#define FDCAN_DBTP_DBRP_Pos (16U)
3988#define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos)
3989#define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk
3990#define FDCAN_DBTP_TDC_Pos (23U)
3991#define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos)
3992#define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk
3994/***************** Bit definition for FDCAN_TEST register *******************/
3995#define FDCAN_TEST_LBCK_Pos (4U)
3996#define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos)
3997#define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk
3998#define FDCAN_TEST_TX_Pos (5U)
3999#define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos)
4000#define FDCAN_TEST_TX FDCAN_TEST_TX_Msk
4001#define FDCAN_TEST_RX_Pos (7U)
4002#define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos)
4003#define FDCAN_TEST_RX FDCAN_TEST_RX_Msk
4005/***************** Bit definition for FDCAN_RWD register ********************/
4006#define FDCAN_RWD_WDC_Pos (0U)
4007#define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos)
4008#define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk
4009#define FDCAN_RWD_WDV_Pos (8U)
4010#define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos)
4011#define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk
4013/***************** Bit definition for FDCAN_CCCR register ********************/
4014#define FDCAN_CCCR_INIT_Pos (0U)
4015#define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos)
4016#define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk
4017#define FDCAN_CCCR_CCE_Pos (1U)
4018#define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos)
4019#define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk
4020#define FDCAN_CCCR_ASM_Pos (2U)
4021#define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos)
4022#define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk
4023#define FDCAN_CCCR_CSA_Pos (3U)
4024#define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos)
4025#define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk
4026#define FDCAN_CCCR_CSR_Pos (4U)
4027#define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos)
4028#define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk
4029#define FDCAN_CCCR_MON_Pos (5U)
4030#define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos)
4031#define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk
4032#define FDCAN_CCCR_DAR_Pos (6U)
4033#define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos)
4034#define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk
4035#define FDCAN_CCCR_TEST_Pos (7U)
4036#define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos)
4037#define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk
4038#define FDCAN_CCCR_FDOE_Pos (8U)
4039#define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos)
4040#define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk
4041#define FDCAN_CCCR_BRSE_Pos (9U)
4042#define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos)
4043#define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk
4044#define FDCAN_CCCR_PXHD_Pos (12U)
4045#define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos)
4046#define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk
4047#define FDCAN_CCCR_EFBI_Pos (13U)
4048#define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos)
4049#define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk
4050#define FDCAN_CCCR_TXP_Pos (14U)
4051#define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos)
4052#define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk
4053#define FDCAN_CCCR_NISO_Pos (15U)
4054#define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos)
4055#define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk
4057/***************** Bit definition for FDCAN_NBTP register ********************/
4058#define FDCAN_NBTP_NTSEG2_Pos (0U)
4059#define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)
4060#define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk
4061#define FDCAN_NBTP_NTSEG1_Pos (8U)
4062#define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)
4063#define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk
4064#define FDCAN_NBTP_NBRP_Pos (16U)
4065#define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos)
4066#define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk
4067#define FDCAN_NBTP_NSJW_Pos (25U)
4068#define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos)
4069#define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk
4071/***************** Bit definition for FDCAN_TSCC register ********************/
4072#define FDCAN_TSCC_TSS_Pos (0U)
4073#define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos)
4074#define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk
4075#define FDCAN_TSCC_TCP_Pos (16U)
4076#define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos)
4077#define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk
4079/***************** Bit definition for FDCAN_TSCV register ********************/
4080#define FDCAN_TSCV_TSC_Pos (0U)
4081#define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos)
4082#define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk
4084/***************** Bit definition for FDCAN_TOCC register ********************/
4085#define FDCAN_TOCC_ETOC_Pos (0U)
4086#define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos)
4087#define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk
4088#define FDCAN_TOCC_TOS_Pos (1U)
4089#define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos)
4090#define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk
4091#define FDCAN_TOCC_TOP_Pos (16U)
4092#define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos)
4093#define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk
4095/***************** Bit definition for FDCAN_TOCV register ********************/
4096#define FDCAN_TOCV_TOC_Pos (0U)
4097#define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos)
4098#define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk
4100/***************** Bit definition for FDCAN_ECR register *********************/
4101#define FDCAN_ECR_TEC_Pos (0U)
4102#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos)
4103#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk
4104#define FDCAN_ECR_REC_Pos (8U)
4105#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos)
4106#define FDCAN_ECR_REC FDCAN_ECR_REC_Msk
4107#define FDCAN_ECR_RP_Pos (15U)
4108#define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos)
4109#define FDCAN_ECR_RP FDCAN_ECR_RP_Msk
4110#define FDCAN_ECR_CEL_Pos (16U)
4111#define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos)
4112#define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk
4114/***************** Bit definition for FDCAN_PSR register *********************/
4115#define FDCAN_PSR_LEC_Pos (0U)
4116#define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos)
4117#define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk
4118#define FDCAN_PSR_ACT_Pos (3U)
4119#define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos)
4120#define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk
4121#define FDCAN_PSR_EP_Pos (5U)
4122#define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos)
4123#define FDCAN_PSR_EP FDCAN_PSR_EP_Msk
4124#define FDCAN_PSR_EW_Pos (6U)
4125#define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos)
4126#define FDCAN_PSR_EW FDCAN_PSR_EW_Msk
4127#define FDCAN_PSR_BO_Pos (7U)
4128#define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos)
4129#define FDCAN_PSR_BO FDCAN_PSR_BO_Msk
4130#define FDCAN_PSR_DLEC_Pos (8U)
4131#define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos)
4132#define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk
4133#define FDCAN_PSR_RESI_Pos (11U)
4134#define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos)
4135#define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk
4136#define FDCAN_PSR_RBRS_Pos (12U)
4137#define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos)
4138#define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk
4139#define FDCAN_PSR_REDL_Pos (13U)
4140#define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos)
4141#define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk
4142#define FDCAN_PSR_PXE_Pos (14U)
4143#define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos)
4144#define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk
4145#define FDCAN_PSR_TDCV_Pos (16U)
4146#define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos)
4147#define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk
4149/***************** Bit definition for FDCAN_TDCR register ********************/
4150#define FDCAN_TDCR_TDCF_Pos (0U)
4151#define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos)
4152#define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk
4153#define FDCAN_TDCR_TDCO_Pos (8U)
4154#define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos)
4155#define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk
4157/***************** Bit definition for FDCAN_IR register **********************/
4158#define FDCAN_IR_RF0N_Pos (0U)
4159#define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos)
4160#define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk
4161#define FDCAN_IR_RF0W_Pos (1U)
4162#define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos)
4163#define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk
4164#define FDCAN_IR_RF0F_Pos (2U)
4165#define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos)
4166#define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk
4167#define FDCAN_IR_RF0L_Pos (3U)
4168#define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos)
4169#define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk
4170#define FDCAN_IR_RF1N_Pos (4U)
4171#define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos)
4172#define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk
4173#define FDCAN_IR_RF1W_Pos (5U)
4174#define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos)
4175#define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk
4176#define FDCAN_IR_RF1F_Pos (6U)
4177#define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos)
4178#define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk
4179#define FDCAN_IR_RF1L_Pos (7U)
4180#define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos)
4181#define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk
4182#define FDCAN_IR_HPM_Pos (8U)
4183#define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos)
4184#define FDCAN_IR_HPM FDCAN_IR_HPM_Msk
4185#define FDCAN_IR_TC_Pos (9U)
4186#define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos)
4187#define FDCAN_IR_TC FDCAN_IR_TC_Msk
4188#define FDCAN_IR_TCF_Pos (10U)
4189#define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos)
4190#define FDCAN_IR_TCF FDCAN_IR_TCF_Msk
4191#define FDCAN_IR_TFE_Pos (11U)
4192#define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos)
4193#define FDCAN_IR_TFE FDCAN_IR_TFE_Msk
4194#define FDCAN_IR_TEFN_Pos (12U)
4195#define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos)
4196#define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk
4197#define FDCAN_IR_TEFW_Pos (13U)
4198#define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos)
4199#define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk
4200#define FDCAN_IR_TEFF_Pos (14U)
4201#define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos)
4202#define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk
4203#define FDCAN_IR_TEFL_Pos (15U)
4204#define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos)
4205#define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk
4206#define FDCAN_IR_TSW_Pos (16U)
4207#define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos)
4208#define FDCAN_IR_TSW FDCAN_IR_TSW_Msk
4209#define FDCAN_IR_MRAF_Pos (17U)
4210#define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos)
4211#define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk
4212#define FDCAN_IR_TOO_Pos (18U)
4213#define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos)
4214#define FDCAN_IR_TOO FDCAN_IR_TOO_Msk
4215#define FDCAN_IR_DRX_Pos (19U)
4216#define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos)
4217#define FDCAN_IR_DRX FDCAN_IR_DRX_Msk
4218#define FDCAN_IR_ELO_Pos (22U)
4219#define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos)
4220#define FDCAN_IR_ELO FDCAN_IR_ELO_Msk
4221#define FDCAN_IR_EP_Pos (23U)
4222#define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos)
4223#define FDCAN_IR_EP FDCAN_IR_EP_Msk
4224#define FDCAN_IR_EW_Pos (24U)
4225#define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos)
4226#define FDCAN_IR_EW FDCAN_IR_EW_Msk
4227#define FDCAN_IR_BO_Pos (25U)
4228#define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos)
4229#define FDCAN_IR_BO FDCAN_IR_BO_Msk
4230#define FDCAN_IR_WDI_Pos (26U)
4231#define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos)
4232#define FDCAN_IR_WDI FDCAN_IR_WDI_Msk
4233#define FDCAN_IR_PEA_Pos (27U)
4234#define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos)
4235#define FDCAN_IR_PEA FDCAN_IR_PEA_Msk
4236#define FDCAN_IR_PED_Pos (28U)
4237#define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos)
4238#define FDCAN_IR_PED FDCAN_IR_PED_Msk
4239#define FDCAN_IR_ARA_Pos (29U)
4240#define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos)
4241#define FDCAN_IR_ARA FDCAN_IR_ARA_Msk
4243/***************** Bit definition for FDCAN_IE register **********************/
4244#define FDCAN_IE_RF0NE_Pos (0U)
4245#define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos)
4246#define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk
4247#define FDCAN_IE_RF0WE_Pos (1U)
4248#define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos)
4249#define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk
4250#define FDCAN_IE_RF0FE_Pos (2U)
4251#define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos)
4252#define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk
4253#define FDCAN_IE_RF0LE_Pos (3U)
4254#define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos)
4255#define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk
4256#define FDCAN_IE_RF1NE_Pos (4U)
4257#define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos)
4258#define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk
4259#define FDCAN_IE_RF1WE_Pos (5U)
4260#define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos)
4261#define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk
4262#define FDCAN_IE_RF1FE_Pos (6U)
4263#define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos)
4264#define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk
4265#define FDCAN_IE_RF1LE_Pos (7U)
4266#define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos)
4267#define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk
4268#define FDCAN_IE_HPME_Pos (8U)
4269#define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos)
4270#define FDCAN_IE_HPME FDCAN_IE_HPME_Msk
4271#define FDCAN_IE_TCE_Pos (9U)
4272#define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos)
4273#define FDCAN_IE_TCE FDCAN_IE_TCE_Msk
4274#define FDCAN_IE_TCFE_Pos (10U)
4275#define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos)
4276#define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk
4277#define FDCAN_IE_TFEE_Pos (11U)
4278#define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos)
4279#define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk
4280#define FDCAN_IE_TEFNE_Pos (12U)
4281#define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos)
4282#define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk
4283#define FDCAN_IE_TEFWE_Pos (13U)
4284#define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos)
4285#define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk
4286#define FDCAN_IE_TEFFE_Pos (14U)
4287#define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos)
4288#define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk
4289#define FDCAN_IE_TEFLE_Pos (15U)
4290#define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos)
4291#define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk
4292#define FDCAN_IE_TSWE_Pos (16U)
4293#define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos)
4294#define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk
4295#define FDCAN_IE_MRAFE_Pos (17U)
4296#define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos)
4297#define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk
4298#define FDCAN_IE_TOOE_Pos (18U)
4299#define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos)
4300#define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk
4301#define FDCAN_IE_DRXE_Pos (19U)
4302#define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos)
4303#define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk
4304#define FDCAN_IE_BECE_Pos (20U)
4305#define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos)
4306#define FDCAN_IE_BECE FDCAN_IE_BECE_Msk
4307#define FDCAN_IE_BEUE_Pos (21U)
4308#define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos)
4309#define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk
4310#define FDCAN_IE_ELOE_Pos (22U)
4311#define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos)
4312#define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk
4313#define FDCAN_IE_EPE_Pos (23U)
4314#define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos)
4315#define FDCAN_IE_EPE FDCAN_IE_EPE_Msk
4316#define FDCAN_IE_EWE_Pos (24U)
4317#define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos)
4318#define FDCAN_IE_EWE FDCAN_IE_EWE_Msk
4319#define FDCAN_IE_BOE_Pos (25U)
4320#define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos)
4321#define FDCAN_IE_BOE FDCAN_IE_BOE_Msk
4322#define FDCAN_IE_WDIE_Pos (26U)
4323#define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos)
4324#define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk
4325#define FDCAN_IE_PEAE_Pos (27U)
4326#define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos)
4327#define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk
4328#define FDCAN_IE_PEDE_Pos (28U)
4329#define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos)
4330#define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk
4331#define FDCAN_IE_ARAE_Pos (29U)
4332#define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos)
4333#define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk
4335/***************** Bit definition for FDCAN_ILS register **********************/
4336#define FDCAN_ILS_RF0NL_Pos (0U)
4337#define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos)
4338#define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk
4339#define FDCAN_ILS_RF0WL_Pos (1U)
4340#define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos)
4341#define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk
4342#define FDCAN_ILS_RF0FL_Pos (2U)
4343#define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos)
4344#define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk
4345#define FDCAN_ILS_RF0LL_Pos (3U)
4346#define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos)
4347#define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk
4348#define FDCAN_ILS_RF1NL_Pos (4U)
4349#define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos)
4350#define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk
4351#define FDCAN_ILS_RF1WL_Pos (5U)
4352#define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos)
4353#define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk
4354#define FDCAN_ILS_RF1FL_Pos (6U)
4355#define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos)
4356#define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk
4357#define FDCAN_ILS_RF1LL_Pos (7U)
4358#define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos)
4359#define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk
4360#define FDCAN_ILS_HPML_Pos (8U)
4361#define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos)
4362#define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk
4363#define FDCAN_ILS_TCL_Pos (9U)
4364#define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos)
4365#define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk
4366#define FDCAN_ILS_TCFL_Pos (10U)
4367#define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos)
4368#define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk
4369#define FDCAN_ILS_TFEL_Pos (11U)
4370#define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos)
4371#define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk
4372#define FDCAN_ILS_TEFNL_Pos (12U)
4373#define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos)
4374#define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk
4375#define FDCAN_ILS_TEFWL_Pos (13U)
4376#define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos)
4377#define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk
4378#define FDCAN_ILS_TEFFL_Pos (14U)
4379#define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos)
4380#define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk
4381#define FDCAN_ILS_TEFLL_Pos (15U)
4382#define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos)
4383#define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk
4384#define FDCAN_ILS_TSWL_Pos (16U)
4385#define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos)
4386#define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk
4387#define FDCAN_ILS_MRAFE_Pos (17U)
4388#define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos)
4389#define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk
4390#define FDCAN_ILS_TOOE_Pos (18U)
4391#define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos)
4392#define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk
4393#define FDCAN_ILS_DRXE_Pos (19U)
4394#define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos)
4395#define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk
4396#define FDCAN_ILS_BECE_Pos (20U)
4397#define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos)
4398#define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk
4399#define FDCAN_ILS_BEUE_Pos (21U)
4400#define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos)
4401#define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk
4402#define FDCAN_ILS_ELOE_Pos (22U)
4403#define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos)
4404#define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk
4405#define FDCAN_ILS_EPE_Pos (23U)
4406#define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos)
4407#define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk
4408#define FDCAN_ILS_EWE_Pos (24U)
4409#define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos)
4410#define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk
4411#define FDCAN_ILS_BOE_Pos (25U)
4412#define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos)
4413#define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk
4414#define FDCAN_ILS_WDIE_Pos (26U)
4415#define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos)
4416#define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk
4417#define FDCAN_ILS_PEAE_Pos (27U)
4418#define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos)
4419#define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk
4420#define FDCAN_ILS_PEDE_Pos (28U)
4421#define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos)
4422#define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk
4423#define FDCAN_ILS_ARAE_Pos (29U)
4424#define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos)
4425#define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk
4427/***************** Bit definition for FDCAN_ILE register **********************/
4428#define FDCAN_ILE_EINT0_Pos (0U)
4429#define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos)
4430#define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk
4431#define FDCAN_ILE_EINT1_Pos (1U)
4432#define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos)
4433#define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk
4435/***************** Bit definition for FDCAN_GFC register **********************/
4436#define FDCAN_GFC_RRFE_Pos (0U)
4437#define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos)
4438#define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk
4439#define FDCAN_GFC_RRFS_Pos (1U)
4440#define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos)
4441#define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk
4442#define FDCAN_GFC_ANFE_Pos (2U)
4443#define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos)
4444#define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk
4445#define FDCAN_GFC_ANFS_Pos (4U)
4446#define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos)
4447#define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk
4449/***************** Bit definition for FDCAN_SIDFC register ********************/
4450#define FDCAN_SIDFC_FLSSA_Pos (2U)
4451#define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)
4452#define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk
4453#define FDCAN_SIDFC_LSS_Pos (16U)
4454#define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos)
4455#define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk
4457/***************** Bit definition for FDCAN_XIDFC register ********************/
4458#define FDCAN_XIDFC_FLESA_Pos (2U)
4459#define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)
4460#define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk
4461#define FDCAN_XIDFC_LSE_Pos (16U)
4462#define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos)
4463#define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk
4465/***************** Bit definition for FDCAN_XIDAM register ********************/
4466#define FDCAN_XIDAM_EIDM_Pos (0U)
4467#define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)
4468#define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk
4470/***************** Bit definition for FDCAN_HPMS register *********************/
4471#define FDCAN_HPMS_BIDX_Pos (0U)
4472#define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos)
4473#define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk
4474#define FDCAN_HPMS_MSI_Pos (6U)
4475#define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos)
4476#define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk
4477#define FDCAN_HPMS_FIDX_Pos (8U)
4478#define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos)
4479#define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk
4480#define FDCAN_HPMS_FLST_Pos (15U)
4481#define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos)
4482#define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk
4484/***************** Bit definition for FDCAN_NDAT1 register ********************/
4485#define FDCAN_NDAT1_ND0_Pos (0U)
4486#define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos)
4487#define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk
4488#define FDCAN_NDAT1_ND1_Pos (1U)
4489#define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos)
4490#define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk
4491#define FDCAN_NDAT1_ND2_Pos (2U)
4492#define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos)
4493#define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk
4494#define FDCAN_NDAT1_ND3_Pos (3U)
4495#define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos)
4496#define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk
4497#define FDCAN_NDAT1_ND4_Pos (4U)
4498#define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos)
4499#define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk
4500#define FDCAN_NDAT1_ND5_Pos (5U)
4501#define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos)
4502#define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk
4503#define FDCAN_NDAT1_ND6_Pos (6U)
4504#define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos)
4505#define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk
4506#define FDCAN_NDAT1_ND7_Pos (7U)
4507#define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos)
4508#define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk
4509#define FDCAN_NDAT1_ND8_Pos (8U)
4510#define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos)
4511#define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk
4512#define FDCAN_NDAT1_ND9_Pos (9U)
4513#define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos)
4514#define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk
4515#define FDCAN_NDAT1_ND10_Pos (10U)
4516#define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos)
4517#define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk
4518#define FDCAN_NDAT1_ND11_Pos (11U)
4519#define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos)
4520#define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk
4521#define FDCAN_NDAT1_ND12_Pos (12U)
4522#define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos)
4523#define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk
4524#define FDCAN_NDAT1_ND13_Pos (13U)
4525#define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos)
4526#define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk
4527#define FDCAN_NDAT1_ND14_Pos (14U)
4528#define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos)
4529#define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk
4530#define FDCAN_NDAT1_ND15_Pos (15U)
4531#define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos)
4532#define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk
4533#define FDCAN_NDAT1_ND16_Pos (16U)
4534#define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos)
4535#define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk
4536#define FDCAN_NDAT1_ND17_Pos (17U)
4537#define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos)
4538#define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk
4539#define FDCAN_NDAT1_ND18_Pos (18U)
4540#define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos)
4541#define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk
4542#define FDCAN_NDAT1_ND19_Pos (19U)
4543#define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos)
4544#define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk
4545#define FDCAN_NDAT1_ND20_Pos (20U)
4546#define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos)
4547#define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk
4548#define FDCAN_NDAT1_ND21_Pos (21U)
4549#define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos)
4550#define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk
4551#define FDCAN_NDAT1_ND22_Pos (22U)
4552#define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos)
4553#define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk
4554#define FDCAN_NDAT1_ND23_Pos (23U)
4555#define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos)
4556#define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk
4557#define FDCAN_NDAT1_ND24_Pos (24U)
4558#define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos)
4559#define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk
4560#define FDCAN_NDAT1_ND25_Pos (25U)
4561#define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos)
4562#define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk
4563#define FDCAN_NDAT1_ND26_Pos (26U)
4564#define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos)
4565#define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk
4566#define FDCAN_NDAT1_ND27_Pos (27U)
4567#define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos)
4568#define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk
4569#define FDCAN_NDAT1_ND28_Pos (28U)
4570#define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos)
4571#define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk
4572#define FDCAN_NDAT1_ND29_Pos (29U)
4573#define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos)
4574#define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk
4575#define FDCAN_NDAT1_ND30_Pos (30U)
4576#define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos)
4577#define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk
4578#define FDCAN_NDAT1_ND31_Pos (31U)
4579#define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos)
4580#define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk
4582/***************** Bit definition for FDCAN_NDAT2 register ********************/
4583#define FDCAN_NDAT2_ND32_Pos (0U)
4584#define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos)
4585#define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk
4586#define FDCAN_NDAT2_ND33_Pos (1U)
4587#define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos)
4588#define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk
4589#define FDCAN_NDAT2_ND34_Pos (2U)
4590#define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos)
4591#define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk
4592#define FDCAN_NDAT2_ND35_Pos (3U)
4593#define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos)
4594#define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk
4595#define FDCAN_NDAT2_ND36_Pos (4U)
4596#define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos)
4597#define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk
4598#define FDCAN_NDAT2_ND37_Pos (5U)
4599#define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos)
4600#define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk
4601#define FDCAN_NDAT2_ND38_Pos (6U)
4602#define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos)
4603#define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk
4604#define FDCAN_NDAT2_ND39_Pos (7U)
4605#define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos)
4606#define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk
4607#define FDCAN_NDAT2_ND40_Pos (8U)
4608#define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos)
4609#define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk
4610#define FDCAN_NDAT2_ND41_Pos (9U)
4611#define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos)
4612#define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk
4613#define FDCAN_NDAT2_ND42_Pos (10U)
4614#define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos)
4615#define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk
4616#define FDCAN_NDAT2_ND43_Pos (11U)
4617#define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos)
4618#define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk
4619#define FDCAN_NDAT2_ND44_Pos (12U)
4620#define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos)
4621#define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk
4622#define FDCAN_NDAT2_ND45_Pos (13U)
4623#define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos)
4624#define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk
4625#define FDCAN_NDAT2_ND46_Pos (14U)
4626#define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos)
4627#define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk
4628#define FDCAN_NDAT2_ND47_Pos (15U)
4629#define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos)
4630#define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk
4631#define FDCAN_NDAT2_ND48_Pos (16U)
4632#define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos)
4633#define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk
4634#define FDCAN_NDAT2_ND49_Pos (17U)
4635#define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos)
4636#define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk
4637#define FDCAN_NDAT2_ND50_Pos (18U)
4638#define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos)
4639#define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk
4640#define FDCAN_NDAT2_ND51_Pos (19U)
4641#define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos)
4642#define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk
4643#define FDCAN_NDAT2_ND52_Pos (20U)
4644#define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos)
4645#define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk
4646#define FDCAN_NDAT2_ND53_Pos (21U)
4647#define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos)
4648#define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk
4649#define FDCAN_NDAT2_ND54_Pos (22U)
4650#define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos)
4651#define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk
4652#define FDCAN_NDAT2_ND55_Pos (23U)
4653#define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos)
4654#define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk
4655#define FDCAN_NDAT2_ND56_Pos (24U)
4656#define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos)
4657#define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk
4658#define FDCAN_NDAT2_ND57_Pos (25U)
4659#define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos)
4660#define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk
4661#define FDCAN_NDAT2_ND58_Pos (26U)
4662#define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos)
4663#define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk
4664#define FDCAN_NDAT2_ND59_Pos (27U)
4665#define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos)
4666#define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk
4667#define FDCAN_NDAT2_ND60_Pos (28U)
4668#define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos)
4669#define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk
4670#define FDCAN_NDAT2_ND61_Pos (29U)
4671#define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos)
4672#define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk
4673#define FDCAN_NDAT2_ND62_Pos (30U)
4674#define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos)
4675#define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk
4676#define FDCAN_NDAT2_ND63_Pos (31U)
4677#define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos)
4678#define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk
4680/***************** Bit definition for FDCAN_RXF0C register ********************/
4681#define FDCAN_RXF0C_F0SA_Pos (2U)
4682#define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)
4683#define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk
4684#define FDCAN_RXF0C_F0S_Pos (16U)
4685#define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos)
4686#define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk
4687#define FDCAN_RXF0C_F0WM_Pos (24U)
4688#define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos)
4689#define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk
4690#define FDCAN_RXF0C_F0OM_Pos (31U)
4691#define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos)
4692#define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk
4694/***************** Bit definition for FDCAN_RXF0S register ********************/
4695#define FDCAN_RXF0S_F0FL_Pos (0U)
4696#define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos)
4697#define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk
4698#define FDCAN_RXF0S_F0GI_Pos (8U)
4699#define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos)
4700#define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk
4701#define FDCAN_RXF0S_F0PI_Pos (16U)
4702#define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos)
4703#define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk
4704#define FDCAN_RXF0S_F0F_Pos (24U)
4705#define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos)
4706#define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk
4707#define FDCAN_RXF0S_RF0L_Pos (25U)
4708#define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos)
4709#define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk
4711/***************** Bit definition for FDCAN_RXF0A register ********************/
4712#define FDCAN_RXF0A_F0AI_Pos (0U)
4713#define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos)
4714#define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk
4716/***************** Bit definition for FDCAN_RXBC register ********************/
4717#define FDCAN_RXBC_RBSA_Pos (2U)
4718#define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)
4719#define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk
4721/***************** Bit definition for FDCAN_RXF1C register ********************/
4722#define FDCAN_RXF1C_F1SA_Pos (2U)
4723#define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)
4724#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk
4725#define FDCAN_RXF1C_F1S_Pos (16U)
4726#define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos)
4727#define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk
4728#define FDCAN_RXF1C_F1WM_Pos (24U)
4729#define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos)
4730#define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk
4731#define FDCAN_RXF1C_F1OM_Pos (31U)
4732#define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos)
4733#define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk
4735/***************** Bit definition for FDCAN_RXF1S register ********************/
4736#define FDCAN_RXF1S_F1FL_Pos (0U)
4737#define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos)
4738#define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk
4739#define FDCAN_RXF1S_F1GI_Pos (8U)
4740#define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos)
4741#define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk
4742#define FDCAN_RXF1S_F1PI_Pos (16U)
4743#define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos)
4744#define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk
4745#define FDCAN_RXF1S_F1F_Pos (24U)
4746#define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos)
4747#define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk
4748#define FDCAN_RXF1S_RF1L_Pos (25U)
4749#define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos)
4750#define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk
4752/***************** Bit definition for FDCAN_RXF1A register ********************/
4753#define FDCAN_RXF1A_F1AI_Pos (0U)
4754#define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos)
4755#define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk
4757/***************** Bit definition for FDCAN_RXESC register ********************/
4758#define FDCAN_RXESC_F0DS_Pos (0U)
4759#define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos)
4760#define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk
4761#define FDCAN_RXESC_F1DS_Pos (4U)
4762#define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos)
4763#define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk
4764#define FDCAN_RXESC_RBDS_Pos (8U)
4765#define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos)
4766#define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk
4768/***************** Bit definition for FDCAN_TXBC register *********************/
4769#define FDCAN_TXBC_TBSA_Pos (2U)
4770#define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)
4771#define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk
4772#define FDCAN_TXBC_NDTB_Pos (16U)
4773#define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos)
4774#define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk
4775#define FDCAN_TXBC_TFQS_Pos (24U)
4776#define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos)
4777#define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk
4778#define FDCAN_TXBC_TFQM_Pos (30U)
4779#define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos)
4780#define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk
4782/***************** Bit definition for FDCAN_TXFQS register *********************/
4783#define FDCAN_TXFQS_TFFL_Pos (0U)
4784#define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos)
4785#define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk
4786#define FDCAN_TXFQS_TFGI_Pos (8U)
4787#define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos)
4788#define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk
4789#define FDCAN_TXFQS_TFQPI_Pos (16U)
4790#define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)
4791#define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk
4792#define FDCAN_TXFQS_TFQF_Pos (21U)
4793#define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos)
4794#define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk
4796/***************** Bit definition for FDCAN_TXESC register *********************/
4797#define FDCAN_TXESC_TBDS_Pos (0U)
4798#define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos)
4799#define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk
4801/***************** Bit definition for FDCAN_TXBRP register *********************/
4802#define FDCAN_TXBRP_TRP_Pos (0U)
4803#define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)
4804#define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk
4806/***************** Bit definition for FDCAN_TXBAR register *********************/
4807#define FDCAN_TXBAR_AR_Pos (0U)
4808#define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)
4809#define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk
4811/***************** Bit definition for FDCAN_TXBCR register *********************/
4812#define FDCAN_TXBCR_CR_Pos (0U)
4813#define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)
4814#define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk
4816/***************** Bit definition for FDCAN_TXBTO register *********************/
4817#define FDCAN_TXBTO_TO_Pos (0U)
4818#define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)
4819#define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk
4821/***************** Bit definition for FDCAN_TXBCF register *********************/
4822#define FDCAN_TXBCF_CF_Pos (0U)
4823#define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)
4824#define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk
4826/***************** Bit definition for FDCAN_TXBTIE register ********************/
4827#define FDCAN_TXBTIE_TIE_Pos (0U)
4828#define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)
4829#define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk
4831/***************** Bit definition for FDCAN_ TXBCIE register *******************/
4832#define FDCAN_TXBCIE_CFIE_Pos (0U)
4833#define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)
4834#define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk
4836/***************** Bit definition for FDCAN_TXEFC register *********************/
4837#define FDCAN_TXEFC_EFSA_Pos (2U)
4838#define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)
4839#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk
4840#define FDCAN_TXEFC_EFS_Pos (16U)
4841#define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos)
4842#define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk
4843#define FDCAN_TXEFC_EFWM_Pos (24U)
4844#define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos)
4845#define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk
4847/***************** Bit definition for FDCAN_TXEFS register *********************/
4848#define FDCAN_TXEFS_EFFL_Pos (0U)
4849#define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos)
4850#define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk
4851#define FDCAN_TXEFS_EFGI_Pos (8U)
4852#define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos)
4853#define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk
4854#define FDCAN_TXEFS_EFPI_Pos (16U)
4855#define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos)
4856#define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk
4857#define FDCAN_TXEFS_EFF_Pos (24U)
4858#define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos)
4859#define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk
4860#define FDCAN_TXEFS_TEFL_Pos (25U)
4861#define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos)
4862#define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk
4864/***************** Bit definition for FDCAN_TXEFA register *********************/
4865#define FDCAN_TXEFA_EFAI_Pos (0U)
4866#define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos)
4867#define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk
4869/***************** Bit definition for FDCAN_TTTMC register *********************/
4870#define FDCAN_TTTMC_TMSA_Pos (2U)
4871#define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)
4872#define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk
4873#define FDCAN_TTTMC_TME_Pos (16U)
4874#define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos)
4875#define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk
4877/***************** Bit definition for FDCAN_TTRMC register *********************/
4878#define FDCAN_TTRMC_RID_Pos (0U)
4879#define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)
4880#define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk
4881#define FDCAN_TTRMC_XTD_Pos (30U)
4882#define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos)
4883#define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk
4884#define FDCAN_TTRMC_RMPS_Pos (31U)
4885#define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos)
4886#define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk
4888/***************** Bit definition for FDCAN_TTOCF register *********************/
4889#define FDCAN_TTOCF_OM_Pos (0U)
4890#define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos)
4891#define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk
4892#define FDCAN_TTOCF_GEN_Pos (3U)
4893#define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos)
4894#define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk
4895#define FDCAN_TTOCF_TM_Pos (4U)
4896#define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos)
4897#define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk
4898#define FDCAN_TTOCF_LDSDL_Pos (5U)
4899#define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos)
4900#define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk
4901#define FDCAN_TTOCF_IRTO_Pos (8U)
4902#define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos)
4903#define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk
4904#define FDCAN_TTOCF_EECS_Pos (15U)
4905#define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos)
4906#define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk
4907#define FDCAN_TTOCF_AWL_Pos (16U)
4908#define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos)
4909#define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk
4910#define FDCAN_TTOCF_EGTF_Pos (24U)
4911#define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos)
4912#define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk
4913#define FDCAN_TTOCF_ECC_Pos (25U)
4914#define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos)
4915#define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk
4916#define FDCAN_TTOCF_EVTP_Pos (26U)
4917#define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos)
4918#define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk
4920/***************** Bit definition for FDCAN_TTMLM register *********************/
4921#define FDCAN_TTMLM_CCM_Pos (0U)
4922#define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos)
4923#define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk
4924#define FDCAN_TTMLM_CSS_Pos (6U)
4925#define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos)
4926#define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk
4927#define FDCAN_TTMLM_TXEW_Pos (8U)
4928#define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos)
4929#define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk
4930#define FDCAN_TTMLM_ENTT_Pos (16U)
4931#define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)
4932#define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk
4934/***************** Bit definition for FDCAN_TURCF register *********************/
4935#define FDCAN_TURCF_NCL_Pos (0U)
4936#define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos)
4937#define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk
4938#define FDCAN_TURCF_DC_Pos (16U)
4939#define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos)
4940#define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk
4941#define FDCAN_TURCF_ELT_Pos (31U)
4942#define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos)
4943#define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk
4945/***************** Bit definition for FDCAN_TTOCN register ********************/
4946#define FDCAN_TTOCN_SGT_Pos (0U)
4947#define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos)
4948#define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk
4949#define FDCAN_TTOCN_ECS_Pos (1U)
4950#define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos)
4951#define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk
4952#define FDCAN_TTOCN_SWP_Pos (2U)
4953#define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos)
4954#define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk
4955#define FDCAN_TTOCN_SWS_Pos (3U)
4956#define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos)
4957#define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk
4958#define FDCAN_TTOCN_RTIE_Pos (5U)
4959#define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos)
4960#define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk
4961#define FDCAN_TTOCN_TMC_Pos (6U)
4962#define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos)
4963#define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk
4964#define FDCAN_TTOCN_TTIE_Pos (8U)
4965#define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos)
4966#define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk
4967#define FDCAN_TTOCN_GCS_Pos (9U)
4968#define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos)
4969#define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk
4970#define FDCAN_TTOCN_FGP_Pos (10U)
4971#define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos)
4972#define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk
4973#define FDCAN_TTOCN_TMG_Pos (11U)
4974#define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos)
4975#define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk
4976#define FDCAN_TTOCN_NIG_Pos (12U)
4977#define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos)
4978#define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk
4979#define FDCAN_TTOCN_ESCN_Pos (13U)
4980#define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos)
4981#define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk
4982#define FDCAN_TTOCN_LCKC_Pos (15U)
4983#define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos)
4984#define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk
4986/***************** Bit definition for FDCAN_TTGTP register ********************/
4987#define FDCAN_TTGTP_TP_Pos (0U)
4988#define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos)
4989#define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk
4990#define FDCAN_TTGTP_CTP_Pos (16U)
4991#define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)
4992#define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk
4994/***************** Bit definition for FDCAN_TTTMK register ********************/
4995#define FDCAN_TTTMK_TM_Pos (0U)
4996#define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos)
4997#define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk
4998#define FDCAN_TTTMK_TICC_Pos (16U)
4999#define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos)
5000#define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk
5001#define FDCAN_TTTMK_LCKM_Pos (31U)
5002#define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos)
5003#define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk
5005/***************** Bit definition for FDCAN_TTIR register ********************/
5006#define FDCAN_TTIR_SBC_Pos (0U)
5007#define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos)
5008#define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk
5009#define FDCAN_TTIR_SMC_Pos (1U)
5010#define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos)
5011#define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk
5012#define FDCAN_TTIR_CSM_Pos (2U)
5013#define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos)
5014#define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk
5015#define FDCAN_TTIR_SOG_Pos (3U)
5016#define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos)
5017#define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk
5018#define FDCAN_TTIR_RTMI_Pos (4U)
5019#define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos)
5020#define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk
5021#define FDCAN_TTIR_TTMI_Pos (5U)
5022#define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos)
5023#define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk
5024#define FDCAN_TTIR_SWE_Pos (6U)
5025#define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos)
5026#define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk
5027#define FDCAN_TTIR_GTW_Pos (7U)
5028#define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos)
5029#define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk
5030#define FDCAN_TTIR_GTD_Pos (8U)
5031#define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos)
5032#define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk
5033#define FDCAN_TTIR_GTE_Pos (9U)
5034#define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos)
5035#define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk
5036#define FDCAN_TTIR_TXU_Pos (10U)
5037#define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos)
5038#define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk
5039#define FDCAN_TTIR_TXO_Pos (11U)
5040#define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos)
5041#define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk
5042#define FDCAN_TTIR_SE1_Pos (12U)
5043#define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos)
5044#define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk
5045#define FDCAN_TTIR_SE2_Pos (13U)
5046#define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos)
5047#define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk
5048#define FDCAN_TTIR_ELC_Pos (14U)
5049#define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos)
5050#define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk
5051#define FDCAN_TTIR_IWT_Pos (15U)
5052#define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos)
5053#define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk
5054#define FDCAN_TTIR_WT_Pos (16U)
5055#define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos)
5056#define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk
5057#define FDCAN_TTIR_AW_Pos (17U)
5058#define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos)
5059#define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk
5060#define FDCAN_TTIR_CER_Pos (18U)
5061#define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos)
5062#define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk
5064/***************** Bit definition for FDCAN_TTIE register ********************/
5065#define FDCAN_TTIE_SBCE_Pos (0U)
5066#define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos)
5067#define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk
5068#define FDCAN_TTIE_SMCE_Pos (1U)
5069#define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos)
5070#define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk
5071#define FDCAN_TTIE_CSME_Pos (2U)
5072#define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos)
5073#define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk
5074#define FDCAN_TTIE_SOGE_Pos (3U)
5075#define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos)
5076#define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk
5077#define FDCAN_TTIE_RTMIE_Pos (4U)
5078#define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos)
5079#define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk
5080#define FDCAN_TTIE_TTMIE_Pos (5U)
5081#define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos)
5082#define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk
5083#define FDCAN_TTIE_SWEE_Pos (6U)
5084#define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos)
5085#define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk
5086#define FDCAN_TTIE_GTWE_Pos (7U)
5087#define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos)
5088#define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk
5089#define FDCAN_TTIE_GTDE_Pos (8U)
5090#define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos)
5091#define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk
5092#define FDCAN_TTIE_GTEE_Pos (9U)
5093#define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos)
5094#define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk
5095#define FDCAN_TTIE_TXUE_Pos (10U)
5096#define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos)
5097#define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk
5098#define FDCAN_TTIE_TXOE_Pos (11U)
5099#define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos)
5100#define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk
5101#define FDCAN_TTIE_SE1E_Pos (12U)
5102#define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos)
5103#define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk
5104#define FDCAN_TTIE_SE2E_Pos (13U)
5105#define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos)
5106#define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk
5107#define FDCAN_TTIE_ELCE_Pos (14U)
5108#define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos)
5109#define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk
5110#define FDCAN_TTIE_IWTE_Pos (15U)
5111#define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos)
5112#define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk
5113#define FDCAN_TTIE_WTE_Pos (16U)
5114#define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos)
5115#define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk
5116#define FDCAN_TTIE_AWE_Pos (17U)
5117#define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos)
5118#define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk
5119#define FDCAN_TTIE_CERE_Pos (18U)
5120#define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos)
5121#define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk
5123/***************** Bit definition for FDCAN_TTILS register ********************/
5124#define FDCAN_TTILS_SBCS_Pos (0U)
5125#define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos)
5126#define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk
5127#define FDCAN_TTILS_SMCS_Pos (1U)
5128#define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos)
5129#define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk
5130#define FDCAN_TTILS_CSMS_Pos (2U)
5131#define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos)
5132#define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk
5133#define FDCAN_TTILS_SOGS_Pos (3U)
5134#define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos)
5135#define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk
5136#define FDCAN_TTILS_RTMIS_Pos (4U)
5137#define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos)
5138#define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk
5139#define FDCAN_TTILS_TTMIS_Pos (5U)
5140#define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos)
5141#define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk
5142#define FDCAN_TTILS_SWES_Pos (6U)
5143#define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos)
5144#define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk
5145#define FDCAN_TTILS_GTWS_Pos (7U)
5146#define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos)
5147#define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk
5148#define FDCAN_TTILS_GTDS_Pos (8U)
5149#define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos)
5150#define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk
5151#define FDCAN_TTILS_GTES_Pos (9U)
5152#define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos)
5153#define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk
5154#define FDCAN_TTILS_TXUS_Pos (10U)
5155#define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos)
5156#define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk
5157#define FDCAN_TTILS_TXOS_Pos (11U)
5158#define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos)
5159#define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk
5160#define FDCAN_TTILS_SE1S_Pos (12U)
5161#define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos)
5162#define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk
5163#define FDCAN_TTILS_SE2S_Pos (13U)
5164#define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos)
5165#define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk
5166#define FDCAN_TTILS_ELCS_Pos (14U)
5167#define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos)
5168#define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk
5169#define FDCAN_TTILS_IWTS_Pos (15U)
5170#define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos)
5171#define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk
5172#define FDCAN_TTILS_WTS_Pos (16U)
5173#define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos)
5174#define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk
5175#define FDCAN_TTILS_AWS_Pos (17U)
5176#define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos)
5177#define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk
5178#define FDCAN_TTILS_CERS_Pos (18U)
5179#define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos)
5180#define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk
5182/***************** Bit definition for FDCAN_TTOST register ********************/
5183#define FDCAN_TTOST_EL_Pos (0U)
5184#define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos)
5185#define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk
5186#define FDCAN_TTOST_MS_Pos (2U)
5187#define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos)
5188#define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk
5189#define FDCAN_TTOST_SYS_Pos (4U)
5190#define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos)
5191#define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk
5192#define FDCAN_TTOST_QGTP_Pos (6U)
5193#define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos)
5194#define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk
5195#define FDCAN_TTOST_QCS_Pos (7U)
5196#define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos)
5197#define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk
5198#define FDCAN_TTOST_RTO_Pos (8U)
5199#define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos)
5200#define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk
5201#define FDCAN_TTOST_WGTD_Pos (22U)
5202#define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos)
5203#define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk
5204#define FDCAN_TTOST_GFI_Pos (23U)
5205#define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos)
5206#define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk
5207#define FDCAN_TTOST_TMP_Pos (24U)
5208#define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos)
5209#define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk
5210#define FDCAN_TTOST_GSI_Pos (27U)
5211#define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos)
5212#define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk
5213#define FDCAN_TTOST_WFE_Pos (28U)
5214#define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos)
5215#define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk
5216#define FDCAN_TTOST_AWE_Pos (29U)
5217#define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos)
5218#define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk
5219#define FDCAN_TTOST_WECS_Pos (30U)
5220#define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos)
5221#define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk
5222#define FDCAN_TTOST_SPL_Pos (31U)
5223#define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos)
5224#define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk
5226/***************** Bit definition for FDCAN_TURNA register ********************/
5227#define FDCAN_TURNA_NAV_Pos (0U)
5228#define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)
5229#define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk
5231/***************** Bit definition for FDCAN_TTLGT register ********************/
5232#define FDCAN_TTLGT_LT_Pos (0U)
5233#define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos)
5234#define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk
5235#define FDCAN_TTLGT_GT_Pos (16U)
5236#define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos)
5237#define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk
5239/***************** Bit definition for FDCAN_TTCTC register ********************/
5240#define FDCAN_TTCTC_CT_Pos (0U)
5241#define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos)
5242#define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk
5243#define FDCAN_TTCTC_CC_Pos (16U)
5244#define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos)
5245#define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk
5247/***************** Bit definition for FDCAN_TTCPT register ********************/
5248#define FDCAN_TTCPT_CCV_Pos (0U)
5249#define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos)
5250#define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk
5251#define FDCAN_TTCPT_SWV_Pos (16U)
5252#define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)
5253#define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk
5255/***************** Bit definition for FDCAN_TTCSM register ********************/
5256#define FDCAN_TTCSM_CSM_Pos (0U)
5257#define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)
5258#define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk
5260/***************** Bit definition for FDCAN_TTTS register *********************/
5261#define FDCAN_TTTS_SWTSEL_Pos (0U)
5262#define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos)
5263#define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk
5264#define FDCAN_TTTS_EVTSEL_Pos (4U)
5265#define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos)
5266#define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk
5268/********************************************************************************/
5269/* */
5270/* FDCANCCU (Clock Calibration unit) */
5271/* */
5272/********************************************************************************/
5273
5274/***************** Bit definition for FDCANCCU_CREL register ******************/
5275#define FDCANCCU_CREL_DAY_Pos (0U)
5276#define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos)
5277#define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk
5278#define FDCANCCU_CREL_MON_Pos (8U)
5279#define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos)
5280#define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk
5281#define FDCANCCU_CREL_YEAR_Pos (16U)
5282#define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos)
5283#define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk
5284#define FDCANCCU_CREL_SUBSTEP_Pos (20U)
5285#define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)
5286#define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk
5287#define FDCANCCU_CREL_STEP_Pos (24U)
5288#define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos)
5289#define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk
5290#define FDCANCCU_CREL_REL_Pos (28U)
5291#define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos)
5292#define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk
5294/***************** Bit definition for FDCANCCU_CCFG register ******************/
5295#define FDCANCCU_CCFG_TQBT_Pos (0U)
5296#define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)
5297#define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk
5298#define FDCANCCU_CCFG_BCC_Pos (6U)
5299#define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos)
5300#define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk
5301#define FDCANCCU_CCFG_CFL_Pos (7U)
5302#define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos)
5303#define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk
5304#define FDCANCCU_CCFG_OCPM_Pos (8U)
5305#define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)
5306#define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk
5307#define FDCANCCU_CCFG_CDIV_Pos (16U)
5308#define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos)
5309#define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk
5310#define FDCANCCU_CCFG_SWR_Pos (31U)
5311#define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos)
5312#define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk
5314/***************** Bit definition for FDCANCCU_CSTAT register *****************/
5315#define FDCANCCU_CSTAT_OCPC_Pos (0U)
5316#define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)
5317#define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk
5318#define FDCANCCU_CSTAT_TQC_Pos (18U)
5319#define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)
5320#define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk
5321#define FDCANCCU_CSTAT_CALS_Pos (30U)
5322#define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos)
5323#define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk
5325/****************** Bit definition for FDCANCCU_CWD register ******************/
5326#define FDCANCCU_CWD_WDC_Pos (0U)
5327#define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)
5328#define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk
5329#define FDCANCCU_CWD_WDV_Pos (16U)
5330#define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)
5331#define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk
5333/****************** Bit definition for FDCANCCU_IR register *******************/
5334#define FDCANCCU_IR_CWE_Pos (0U)
5335#define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos)
5336#define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk
5337#define FDCANCCU_IR_CSC_Pos (1U)
5338#define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos)
5339#define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk
5341/****************** Bit definition for FDCANCCU_IE register *******************/
5342#define FDCANCCU_IE_CWEE_Pos (0U)
5343#define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos)
5344#define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk
5345#define FDCANCCU_IE_CSCE_Pos (1U)
5346#define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos)
5347#define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk
5349/******************************************************************************/
5350/* */
5351/* HDMI-CEC (CEC) */
5352/* */
5353/******************************************************************************/
5354
5355/******************* Bit definition for CEC_CR register *********************/
5356#define CEC_CR_CECEN_Pos (0U)
5357#define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos)
5358#define CEC_CR_CECEN CEC_CR_CECEN_Msk
5359#define CEC_CR_TXSOM_Pos (1U)
5360#define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos)
5361#define CEC_CR_TXSOM CEC_CR_TXSOM_Msk
5362#define CEC_CR_TXEOM_Pos (2U)
5363#define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos)
5364#define CEC_CR_TXEOM CEC_CR_TXEOM_Msk
5366/******************* Bit definition for CEC_CFGR register *******************/
5367#define CEC_CFGR_SFT_Pos (0U)
5368#define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos)
5369#define CEC_CFGR_SFT CEC_CFGR_SFT_Msk
5370#define CEC_CFGR_RXTOL_Pos (3U)
5371#define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos)
5372#define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk
5373#define CEC_CFGR_BRESTP_Pos (4U)
5374#define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos)
5375#define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk
5376#define CEC_CFGR_BREGEN_Pos (5U)
5377#define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos)
5378#define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk
5379#define CEC_CFGR_LBPEGEN_Pos (6U)
5380#define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos)
5381#define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk
5382#define CEC_CFGR_SFTOPT_Pos (8U)
5383#define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos)
5384#define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk
5385#define CEC_CFGR_BRDNOGEN_Pos (7U)
5386#define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos)
5387#define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk
5388#define CEC_CFGR_OAR_Pos (16U)
5389#define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos)
5390#define CEC_CFGR_OAR CEC_CFGR_OAR_Msk
5391#define CEC_CFGR_LSTN_Pos (31U)
5392#define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos)
5393#define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk
5395/******************* Bit definition for CEC_TXDR register *******************/
5396#define CEC_TXDR_TXD_Pos (0U)
5397#define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos)
5398#define CEC_TXDR_TXD CEC_TXDR_TXD_Msk
5400/******************* Bit definition for CEC_RXDR register *******************/
5401#define CEC_RXDR_RXD_Pos (0U)
5402#define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos)
5403#define CEC_RXDR_RXD CEC_RXDR_RXD_Msk
5405/******************* Bit definition for CEC_ISR register ********************/
5406#define CEC_ISR_RXBR_Pos (0U)
5407#define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos)
5408#define CEC_ISR_RXBR CEC_ISR_RXBR_Msk
5409#define CEC_ISR_RXEND_Pos (1U)
5410#define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos)
5411#define CEC_ISR_RXEND CEC_ISR_RXEND_Msk
5412#define CEC_ISR_RXOVR_Pos (2U)
5413#define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos)
5414#define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk
5415#define CEC_ISR_BRE_Pos (3U)
5416#define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos)
5417#define CEC_ISR_BRE CEC_ISR_BRE_Msk
5418#define CEC_ISR_SBPE_Pos (4U)
5419#define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos)
5420#define CEC_ISR_SBPE CEC_ISR_SBPE_Msk
5421#define CEC_ISR_LBPE_Pos (5U)
5422#define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos)
5423#define CEC_ISR_LBPE CEC_ISR_LBPE_Msk
5424#define CEC_ISR_RXACKE_Pos (6U)
5425#define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos)
5426#define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk
5427#define CEC_ISR_ARBLST_Pos (7U)
5428#define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos)
5429#define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk
5430#define CEC_ISR_TXBR_Pos (8U)
5431#define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos)
5432#define CEC_ISR_TXBR CEC_ISR_TXBR_Msk
5433#define CEC_ISR_TXEND_Pos (9U)
5434#define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos)
5435#define CEC_ISR_TXEND CEC_ISR_TXEND_Msk
5436#define CEC_ISR_TXUDR_Pos (10U)
5437#define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos)
5438#define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk
5439#define CEC_ISR_TXERR_Pos (11U)
5440#define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos)
5441#define CEC_ISR_TXERR CEC_ISR_TXERR_Msk
5442#define CEC_ISR_TXACKE_Pos (12U)
5443#define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos)
5444#define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk
5446/******************* Bit definition for CEC_IER register ********************/
5447#define CEC_IER_RXBRIE_Pos (0U)
5448#define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos)
5449#define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk
5450#define CEC_IER_RXENDIE_Pos (1U)
5451#define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos)
5452#define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk
5453#define CEC_IER_RXOVRIE_Pos (2U)
5454#define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos)
5455#define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk
5456#define CEC_IER_BREIE_Pos (3U)
5457#define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos)
5458#define CEC_IER_BREIE CEC_IER_BREIE_Msk
5459#define CEC_IER_SBPEIE_Pos (4U)
5460#define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos)
5461#define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk
5462#define CEC_IER_LBPEIE_Pos (5U)
5463#define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos)
5464#define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk
5465#define CEC_IER_RXACKEIE_Pos (6U)
5466#define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos)
5467#define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk
5468#define CEC_IER_ARBLSTIE_Pos (7U)
5469#define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos)
5470#define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk
5471#define CEC_IER_TXBRIE_Pos (8U)
5472#define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos)
5473#define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk
5474#define CEC_IER_TXENDIE_Pos (9U)
5475#define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos)
5476#define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk
5477#define CEC_IER_TXUDRIE_Pos (10U)
5478#define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos)
5479#define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk
5480#define CEC_IER_TXERRIE_Pos (11U)
5481#define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos)
5482#define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk
5483#define CEC_IER_TXACKEIE_Pos (12U)
5484#define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos)
5485#define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk
5487/******************************************************************************/
5488/* */
5489/* CRC calculation unit */
5490/* */
5491/******************************************************************************/
5492/******************* Bit definition for CRC_DR register *********************/
5493#define CRC_DR_DR_Pos (0U)
5494#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)
5495#define CRC_DR_DR CRC_DR_DR_Msk
5497/******************* Bit definition for CRC_IDR register ********************/
5498#define CRC_IDR_IDR_Pos (0U)
5499#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)
5500#define CRC_IDR_IDR CRC_IDR_IDR_Msk
5502/******************** Bit definition for CRC_CR register ********************/
5503#define CRC_CR_RESET_Pos (0U)
5504#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)
5505#define CRC_CR_RESET CRC_CR_RESET_Msk
5506#define CRC_CR_POLYSIZE_Pos (3U)
5507#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos)
5508#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk
5509#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos)
5510#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos)
5511#define CRC_CR_REV_IN_Pos (5U)
5512#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos)
5513#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk
5514#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos)
5515#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos)
5516#define CRC_CR_REV_OUT_Pos (7U)
5517#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos)
5518#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk
5520/******************* Bit definition for CRC_INIT register *******************/
5521#define CRC_INIT_INIT_Pos (0U)
5522#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)
5523#define CRC_INIT_INIT CRC_INIT_INIT_Msk
5525/******************* Bit definition for CRC_POL register ********************/
5526#define CRC_POL_POL_Pos (0U)
5527#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos)
5528#define CRC_POL_POL CRC_POL_POL_Msk
5530/******************************************************************************/
5531/* */
5532/* CRS Clock Recovery System */
5533/******************************************************************************/
5534
5535/******************* Bit definition for CRS_CR register *********************/
5536#define CRS_CR_SYNCOKIE_Pos (0U)
5537#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos)
5538#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk
5539#define CRS_CR_SYNCWARNIE_Pos (1U)
5540#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos)
5541#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk
5542#define CRS_CR_ERRIE_Pos (2U)
5543#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos)
5544#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk
5545#define CRS_CR_ESYNCIE_Pos (3U)
5546#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos)
5547#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk
5548#define CRS_CR_CEN_Pos (5U)
5549#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos)
5550#define CRS_CR_CEN CRS_CR_CEN_Msk
5551#define CRS_CR_AUTOTRIMEN_Pos (6U)
5552#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos)
5553#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk
5554#define CRS_CR_SWSYNC_Pos (7U)
5555#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos)
5556#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk
5557#define CRS_CR_TRIM_Pos (8U)
5558#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos)
5559#define CRS_CR_TRIM CRS_CR_TRIM_Msk
5561/******************* Bit definition for CRS_CFGR register *********************/
5562#define CRS_CFGR_RELOAD_Pos (0U)
5563#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos)
5564#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk
5565#define CRS_CFGR_FELIM_Pos (16U)
5566#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos)
5567#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk
5569#define CRS_CFGR_SYNCDIV_Pos (24U)
5570#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos)
5571#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk
5572#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos)
5573#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos)
5574#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos)
5576#define CRS_CFGR_SYNCSRC_Pos (28U)
5577#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos)
5578#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk
5579#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos)
5580#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos)
5582#define CRS_CFGR_SYNCPOL_Pos (31U)
5583#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos)
5584#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk
5586/******************* Bit definition for CRS_ISR register *********************/
5587#define CRS_ISR_SYNCOKF_Pos (0U)
5588#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos)
5589#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk
5590#define CRS_ISR_SYNCWARNF_Pos (1U)
5591#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos)
5592#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk
5593#define CRS_ISR_ERRF_Pos (2U)
5594#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos)
5595#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk
5596#define CRS_ISR_ESYNCF_Pos (3U)
5597#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos)
5598#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk
5599#define CRS_ISR_SYNCERR_Pos (8U)
5600#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos)
5601#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk
5602#define CRS_ISR_SYNCMISS_Pos (9U)
5603#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos)
5604#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk
5605#define CRS_ISR_TRIMOVF_Pos (10U)
5606#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos)
5607#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk
5608#define CRS_ISR_FEDIR_Pos (15U)
5609#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos)
5610#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk
5611#define CRS_ISR_FECAP_Pos (16U)
5612#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos)
5613#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk
5615/******************* Bit definition for CRS_ICR register *********************/
5616#define CRS_ICR_SYNCOKC_Pos (0U)
5617#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos)
5618#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk
5619#define CRS_ICR_SYNCWARNC_Pos (1U)
5620#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos)
5621#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk
5622#define CRS_ICR_ERRC_Pos (2U)
5623#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos)
5624#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk
5625#define CRS_ICR_ESYNCC_Pos (3U)
5626#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos)
5627#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk
5629/******************************************************************************/
5630/* */
5631/* Digital to Analog Converter */
5632/* */
5633/******************************************************************************/
5634/******************** Bit definition for DAC_CR register ********************/
5635#define DAC_CR_EN1_Pos (0U)
5636#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)
5637#define DAC_CR_EN1 DAC_CR_EN1_Msk
5638#define DAC_CR_TEN1_Pos (1U)
5639#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)
5640#define DAC_CR_TEN1 DAC_CR_TEN1_Msk
5642#define DAC_CR_TSEL1_Pos (2U)
5643#define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos)
5644#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk
5645#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)
5646#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)
5647#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)
5648#define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos)
5651#define DAC_CR_WAVE1_Pos (6U)
5652#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)
5653#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk
5654#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)
5655#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)
5657#define DAC_CR_MAMP1_Pos (8U)
5658#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)
5659#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk
5660#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)
5661#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)
5662#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)
5663#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)
5665#define DAC_CR_DMAEN1_Pos (12U)
5666#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)
5667#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk
5668#define DAC_CR_DMAUDRIE1_Pos (13U)
5669#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos)
5670#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk
5671#define DAC_CR_CEN1_Pos (14U)
5672#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos)
5673#define DAC_CR_CEN1 DAC_CR_CEN1_Msk
5675#define DAC_CR_EN2_Pos (16U)
5676#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)
5677#define DAC_CR_EN2 DAC_CR_EN2_Msk
5678#define DAC_CR_TEN2_Pos (17U)
5679#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)
5680#define DAC_CR_TEN2 DAC_CR_TEN2_Msk
5682#define DAC_CR_TSEL2_Pos (18U)
5683#define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos)
5684#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk
5685#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)
5686#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)
5687#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)
5688#define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos)
5691#define DAC_CR_WAVE2_Pos (22U)
5692#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)
5693#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk
5694#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)
5695#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)
5697#define DAC_CR_MAMP2_Pos (24U)
5698#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)
5699#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk
5700#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)
5701#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)
5702#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)
5703#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)
5705#define DAC_CR_DMAEN2_Pos (28U)
5706#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)
5707#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk
5708#define DAC_CR_DMAUDRIE2_Pos (29U)
5709#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos)
5710#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk
5711#define DAC_CR_CEN2_Pos (30U)
5712#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos)
5713#define DAC_CR_CEN2 DAC_CR_CEN2_Msk
5715/***************** Bit definition for DAC_SWTRIGR register ******************/
5716#define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5717#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)
5718#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk
5719#define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5720#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)
5721#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk
5723/***************** Bit definition for DAC_DHR12R1 register ******************/
5724#define DAC_DHR12R1_DACC1DHR_Pos (0U)
5725#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)
5726#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk
5728/***************** Bit definition for DAC_DHR12L1 register ******************/
5729#define DAC_DHR12L1_DACC1DHR_Pos (4U)
5730#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)
5731#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk
5733/****************** Bit definition for DAC_DHR8R1 register ******************/
5734#define DAC_DHR8R1_DACC1DHR_Pos (0U)
5735#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)
5736#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk
5738/***************** Bit definition for DAC_DHR12R2 register ******************/
5739#define DAC_DHR12R2_DACC2DHR_Pos (0U)
5740#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)
5741#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk
5743/***************** Bit definition for DAC_DHR12L2 register ******************/
5744#define DAC_DHR12L2_DACC2DHR_Pos (4U)
5745#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)
5746#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk
5748/****************** Bit definition for DAC_DHR8R2 register ******************/
5749#define DAC_DHR8R2_DACC2DHR_Pos (0U)
5750#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)
5751#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk
5753/***************** Bit definition for DAC_DHR12RD register ******************/
5754#define DAC_DHR12RD_DACC1DHR_Pos (0U)
5755#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)
5756#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk
5757#define DAC_DHR12RD_DACC2DHR_Pos (16U)
5758#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)
5759#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk
5761/***************** Bit definition for DAC_DHR12LD register ******************/
5762#define DAC_DHR12LD_DACC1DHR_Pos (4U)
5763#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)
5764#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk
5765#define DAC_DHR12LD_DACC2DHR_Pos (20U)
5766#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)
5767#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk
5769/****************** Bit definition for DAC_DHR8RD register ******************/
5770#define DAC_DHR8RD_DACC1DHR_Pos (0U)
5771#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)
5772#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk
5773#define DAC_DHR8RD_DACC2DHR_Pos (8U)
5774#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)
5775#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk
5777/******************* Bit definition for DAC_DOR1 register *******************/
5778#define DAC_DOR1_DACC1DOR_Pos (0U)
5779#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)
5780#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk
5782/******************* Bit definition for DAC_DOR2 register *******************/
5783#define DAC_DOR2_DACC2DOR_Pos (0U)
5784#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)
5785#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk
5787/******************** Bit definition for DAC_SR register ********************/
5788#define DAC_SR_DMAUDR1_Pos (13U)
5789#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos)
5790#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk
5791#define DAC_SR_CAL_FLAG1_Pos (14U)
5792#define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos)
5793#define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk
5794#define DAC_SR_BWST1_Pos (15U)
5795#define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos)
5796#define DAC_SR_BWST1 DAC_SR_BWST1_Msk
5798#define DAC_SR_DMAUDR2_Pos (29U)
5799#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos)
5800#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk
5801#define DAC_SR_CAL_FLAG2_Pos (30U)
5802#define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos)
5803#define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk
5804#define DAC_SR_BWST2_Pos (31U)
5805#define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos)
5806#define DAC_SR_BWST2 DAC_SR_BWST2_Msk
5808/******************* Bit definition for DAC_CCR register ********************/
5809#define DAC_CCR_OTRIM1_Pos (0U)
5810#define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos)
5811#define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk
5812#define DAC_CCR_OTRIM2_Pos (16U)
5813#define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos)
5814#define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk
5816/******************* Bit definition for DAC_MCR register *******************/
5817#define DAC_MCR_MODE1_Pos (0U)
5818#define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos)
5819#define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk
5820#define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos)
5821#define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos)
5822#define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos)
5824#define DAC_MCR_MODE2_Pos (16U)
5825#define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos)
5826#define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk
5827#define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos)
5828#define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos)
5829#define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos)
5831/****************** Bit definition for DAC_SHSR1 register ******************/
5832#define DAC_SHSR1_TSAMPLE1_Pos (0U)
5833#define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)
5834#define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk
5836/****************** Bit definition for DAC_SHSR2 register ******************/
5837#define DAC_SHSR2_TSAMPLE2_Pos (0U)
5838#define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)
5839#define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk
5841/****************** Bit definition for DAC_SHHR register ******************/
5842#define DAC_SHHR_THOLD1_Pos (0U)
5843#define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos)
5844#define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk
5845#define DAC_SHHR_THOLD2_Pos (16U)
5846#define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos)
5847#define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk
5849/****************** Bit definition for DAC_SHRR register ******************/
5850#define DAC_SHRR_TREFRESH1_Pos (0U)
5851#define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos)
5852#define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk
5853#define DAC_SHRR_TREFRESH2_Pos (16U)
5854#define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos)
5855#define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk
5857/******************************************************************************/
5858/* */
5859/* DCMI */
5860/* */
5861/******************************************************************************/
5862/******************** Bits definition for DCMI_CR register ******************/
5863#define DCMI_CR_CAPTURE_Pos (0U)
5864#define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos)
5865#define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5866#define DCMI_CR_CM_Pos (1U)
5867#define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos)
5868#define DCMI_CR_CM DCMI_CR_CM_Msk
5869#define DCMI_CR_CROP_Pos (2U)
5870#define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos)
5871#define DCMI_CR_CROP DCMI_CR_CROP_Msk
5872#define DCMI_CR_JPEG_Pos (3U)
5873#define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos)
5874#define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5875#define DCMI_CR_ESS_Pos (4U)
5876#define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos)
5877#define DCMI_CR_ESS DCMI_CR_ESS_Msk
5878#define DCMI_CR_PCKPOL_Pos (5U)
5879#define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos)
5880#define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5881#define DCMI_CR_HSPOL_Pos (6U)
5882#define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos)
5883#define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5884#define DCMI_CR_VSPOL_Pos (7U)
5885#define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos)
5886#define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5887#define DCMI_CR_FCRC_0 (0x00000100U)
5888#define DCMI_CR_FCRC_1 (0x00000200U)
5889#define DCMI_CR_EDM_0 (0x00000400U)
5890#define DCMI_CR_EDM_1 (0x00000800U)
5891#define DCMI_CR_CRE_Pos (12U)
5892#define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos)
5893#define DCMI_CR_CRE DCMI_CR_CRE_Msk
5894#define DCMI_CR_ENABLE_Pos (14U)
5895#define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos)
5896#define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5897#define DCMI_CR_BSM_Pos (16U)
5898#define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos)
5899#define DCMI_CR_BSM DCMI_CR_BSM_Msk
5900#define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos)
5901#define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos)
5902#define DCMI_CR_OEBS_Pos (18U)
5903#define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos)
5904#define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
5905#define DCMI_CR_LSM_Pos (19U)
5906#define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos)
5907#define DCMI_CR_LSM DCMI_CR_LSM_Msk
5908#define DCMI_CR_OELS_Pos (20U)
5909#define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos)
5910#define DCMI_CR_OELS DCMI_CR_OELS_Msk
5911
5912/******************** Bits definition for DCMI_SR register ******************/
5913#define DCMI_SR_HSYNC_Pos (0U)
5914#define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos)
5915#define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5916#define DCMI_SR_VSYNC_Pos (1U)
5917#define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos)
5918#define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5919#define DCMI_SR_FNE_Pos (2U)
5920#define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos)
5921#define DCMI_SR_FNE DCMI_SR_FNE_Msk
5922
5923/******************** Bits definition for DCMI_RIS register ****************/
5924#define DCMI_RIS_FRAME_RIS_Pos (0U)
5925#define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos)
5926#define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5927#define DCMI_RIS_OVR_RIS_Pos (1U)
5928#define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos)
5929#define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5930#define DCMI_RIS_ERR_RIS_Pos (2U)
5931#define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos)
5932#define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5933#define DCMI_RIS_VSYNC_RIS_Pos (3U)
5934#define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)
5935#define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5936#define DCMI_RIS_LINE_RIS_Pos (4U)
5937#define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos)
5938#define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5939
5940/******************** Bits definition for DCMI_IER register *****************/
5941#define DCMI_IER_FRAME_IE_Pos (0U)
5942#define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos)
5943#define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5944#define DCMI_IER_OVR_IE_Pos (1U)
5945#define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos)
5946#define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5947#define DCMI_IER_ERR_IE_Pos (2U)
5948#define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos)
5949#define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5950#define DCMI_IER_VSYNC_IE_Pos (3U)
5951#define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos)
5952#define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5953#define DCMI_IER_LINE_IE_Pos (4U)
5954#define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos)
5955#define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5956
5957
5958/******************** Bits definition for DCMI_MIS register *****************/
5959#define DCMI_MIS_FRAME_MIS_Pos (0U)
5960#define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos)
5961#define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5962#define DCMI_MIS_OVR_MIS_Pos (1U)
5963#define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos)
5964#define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5965#define DCMI_MIS_ERR_MIS_Pos (2U)
5966#define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos)
5967#define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5968#define DCMI_MIS_VSYNC_MIS_Pos (3U)
5969#define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)
5970#define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5971#define DCMI_MIS_LINE_MIS_Pos (4U)
5972#define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos)
5973#define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5974
5975
5976/******************** Bits definition for DCMI_ICR register *****************/
5977#define DCMI_ICR_FRAME_ISC_Pos (0U)
5978#define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos)
5979#define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5980#define DCMI_ICR_OVR_ISC_Pos (1U)
5981#define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos)
5982#define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5983#define DCMI_ICR_ERR_ISC_Pos (2U)
5984#define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos)
5985#define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5986#define DCMI_ICR_VSYNC_ISC_Pos (3U)
5987#define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)
5988#define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
5989#define DCMI_ICR_LINE_ISC_Pos (4U)
5990#define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos)
5991#define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
5992
5993
5994/******************** Bits definition for DCMI_ESCR register ******************/
5995#define DCMI_ESCR_FSC_Pos (0U)
5996#define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos)
5997#define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
5998#define DCMI_ESCR_LSC_Pos (8U)
5999#define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos)
6000#define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6001#define DCMI_ESCR_LEC_Pos (16U)
6002#define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos)
6003#define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6004#define DCMI_ESCR_FEC_Pos (24U)
6005#define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos)
6006#define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6007
6008/******************** Bits definition for DCMI_ESUR register ******************/
6009#define DCMI_ESUR_FSU_Pos (0U)
6010#define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos)
6011#define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6012#define DCMI_ESUR_LSU_Pos (8U)
6013#define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos)
6014#define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6015#define DCMI_ESUR_LEU_Pos (16U)
6016#define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos)
6017#define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6018#define DCMI_ESUR_FEU_Pos (24U)
6019#define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos)
6020#define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6021
6022/******************** Bits definition for DCMI_CWSTRT register ******************/
6023#define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6024#define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)
6025#define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6026#define DCMI_CWSTRT_VST_Pos (16U)
6027#define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos)
6028#define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6029
6030/******************** Bits definition for DCMI_CWSIZE register ******************/
6031#define DCMI_CWSIZE_CAPCNT_Pos (0U)
6032#define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)
6033#define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6034#define DCMI_CWSIZE_VLINE_Pos (16U)
6035#define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)
6036#define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6037
6038/******************** Bits definition for DCMI_DR register ******************/
6039#define DCMI_DR_BYTE0_Pos (0U)
6040#define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos)
6041#define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6042#define DCMI_DR_BYTE1_Pos (8U)
6043#define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos)
6044#define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6045#define DCMI_DR_BYTE2_Pos (16U)
6046#define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos)
6047#define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6048#define DCMI_DR_BYTE3_Pos (24U)
6049#define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos)
6050#define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6051
6052/******************************************************************************/
6053/* */
6054/* Digital Filter for Sigma Delta Modulators */
6055/* */
6056/******************************************************************************/
6057
6058/**************** DFSDM channel configuration registers ********************/
6059
6060/*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6061#define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6062#define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)
6063#define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk
6064#define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6065#define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)
6066#define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk
6067#define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6068#define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos)
6069#define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk
6070#define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6071#define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)
6072#define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk
6073#define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)
6074#define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)
6075#define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6076#define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)
6077#define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk
6078#define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)
6079#define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)
6080#define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6081#define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)
6082#define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk
6083#define DFSDM_CHCFGR1_CHEN_Pos (7U)
6084#define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)
6085#define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk
6086#define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6087#define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)
6088#define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk
6089#define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6090#define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)
6091#define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk
6092#define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6093#define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6094#define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk
6095#define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6096#define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)
6097#define DFSDM_CHCFGR1_SITP_Pos (0U)
6098#define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos)
6099#define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk
6100#define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos)
6101#define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos)
6103/*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6104#define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6105#define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos)
6106#define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk
6107#define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6108#define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)
6109#define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk
6111/****************** Bit definition for DFSDM_CHAWSCDR register *****************/
6112#define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6113#define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6114#define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk
6115#define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6116#define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)
6117#define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6118#define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)
6119#define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk
6120#define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6121#define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)
6122#define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk
6123#define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6124#define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)
6125#define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk
6127/**************** Bit definition for DFSDM_CHWDATR register *******************/
6128#define DFSDM_CHWDATR_WDATA_Pos (0U)
6129#define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)
6130#define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk
6132/**************** Bit definition for DFSDM_CHDATINR register *****************/
6133#define DFSDM_CHDATINR_INDAT0_Pos (0U)
6134#define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos)
6135#define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk
6136#define DFSDM_CHDATINR_INDAT1_Pos (16U)
6137#define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos)
6138#define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk
6140/************************ DFSDM module registers ****************************/
6141
6142/******************** Bit definition for DFSDM_FLTCR1 register *******************/
6143#define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6144#define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)
6145#define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk
6146#define DFSDM_FLTCR1_FAST_Pos (29U)
6147#define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos)
6148#define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk
6149#define DFSDM_FLTCR1_RCH_Pos (24U)
6150#define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos)
6151#define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk
6152#define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6153#define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)
6154#define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk
6155#define DFSDM_FLTCR1_RSYNC_Pos (19U)
6156#define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)
6157#define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk
6158#define DFSDM_FLTCR1_RCONT_Pos (18U)
6159#define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos)
6160#define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk
6161#define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6162#define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)
6163#define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk
6164#define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6165#define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)
6166#define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk
6167#define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)
6168#define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)
6169#define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6170#define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)
6171#define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk
6172#define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6173#define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6174#define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6175#define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6176#define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)
6178#define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6179#define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)
6180#define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk
6181#define DFSDM_FLTCR1_JSCAN_Pos (4U)
6182#define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)
6183#define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk
6184#define DFSDM_FLTCR1_JSYNC_Pos (3U)
6185#define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)
6186#define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk
6187#define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6188#define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)
6189#define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk
6190#define DFSDM_FLTCR1_DFEN_Pos (0U)
6191#define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos)
6192#define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk
6194/******************** Bit definition for DFSDM_FLTCR2 register *******************/
6195#define DFSDM_FLTCR2_AWDCH_Pos (16U)
6196#define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)
6197#define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk
6198#define DFSDM_FLTCR2_EXCH_Pos (8U)
6199#define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)
6200#define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk
6201#define DFSDM_FLTCR2_CKABIE_Pos (6U)
6202#define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)
6203#define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk
6204#define DFSDM_FLTCR2_SCDIE_Pos (5U)
6205#define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)
6206#define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk
6207#define DFSDM_FLTCR2_AWDIE_Pos (4U)
6208#define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)
6209#define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk
6210#define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6211#define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)
6212#define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk
6213#define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6214#define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)
6215#define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk
6216#define DFSDM_FLTCR2_REOCIE_Pos (1U)
6217#define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)
6218#define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk
6219#define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6220#define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)
6221#define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk
6223/******************** Bit definition for DFSDM_FLTISR register *******************/
6224#define DFSDM_FLTISR_SCDF_Pos (24U)
6225#define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos)
6226#define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk
6227#define DFSDM_FLTISR_CKABF_Pos (16U)
6228#define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos)
6229#define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk
6230#define DFSDM_FLTISR_RCIP_Pos (14U)
6231#define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos)
6232#define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk
6233#define DFSDM_FLTISR_JCIP_Pos (13U)
6234#define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos)
6235#define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk
6236#define DFSDM_FLTISR_AWDF_Pos (4U)
6237#define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos)
6238#define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk
6239#define DFSDM_FLTISR_ROVRF_Pos (3U)
6240#define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos)
6241#define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk
6242#define DFSDM_FLTISR_JOVRF_Pos (2U)
6243#define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos)
6244#define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk
6245#define DFSDM_FLTISR_REOCF_Pos (1U)
6246#define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos)
6247#define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk
6248#define DFSDM_FLTISR_JEOCF_Pos (0U)
6249#define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos)
6250#define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk
6252/******************** Bit definition for DFSDM_FLTICR register *******************/
6253#define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6254#define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)
6255#define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk
6256#define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6257#define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)
6258#define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk
6259#define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6260#define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)
6261#define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk
6262#define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6263#define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)
6264#define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk
6266/******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6267#define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6268#define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)
6269#define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk
6271/******************** Bit definition for DFSDM_FLTFCR register *******************/
6272#define DFSDM_FLTFCR_FORD_Pos (29U)
6273#define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos)
6274#define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk
6275#define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos)
6276#define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos)
6277#define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos)
6278#define DFSDM_FLTFCR_FOSR_Pos (16U)
6279#define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)
6280#define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk
6281#define DFSDM_FLTFCR_IOSR_Pos (0U)
6282#define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)
6283#define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk
6285/****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6286#define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6287#define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos)
6288#define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk
6289#define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6290#define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos)
6291#define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk
6293/****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6294#define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6295#define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos)
6296#define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk
6297#define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6298#define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)
6299#define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk
6300#define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6301#define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos)
6302#define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk
6304/****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6305#define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6306#define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos)
6307#define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk
6308#define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6309#define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)
6310#define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk
6312/****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6313#define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6314#define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos)
6315#define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk
6316#define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6317#define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)
6318#define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk
6320/****************** Bit definition for DFSDM_FLTAWSR register ******************/
6321#define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6322#define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)
6323#define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk
6324#define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6325#define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)
6326#define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk
6328/****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
6329#define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6330#define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos)
6331#define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk
6332#define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6333#define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos)
6334#define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk
6336/****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6337#define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6338#define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos)
6339#define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk
6340#define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6341#define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)
6342#define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk
6344/****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6345#define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6346#define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos)
6347#define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk
6348#define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6349#define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)
6350#define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk
6352/****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6353#define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6354#define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos)
6355#define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk
6357/******************************************************************************/
6358/* */
6359/* BDMA Controller */
6360/* */
6361/******************************************************************************/
6362
6363/******************* Bit definition for BDMA_ISR register ********************/
6364#define BDMA_ISR_GIF0_Pos (0U)
6365#define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos)
6366#define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk
6367#define BDMA_ISR_TCIF0_Pos (1U)
6368#define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos)
6369#define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk
6370#define BDMA_ISR_HTIF0_Pos (2U)
6371#define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos)
6372#define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk
6373#define BDMA_ISR_TEIF0_Pos (3U)
6374#define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos)
6375#define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk
6376#define BDMA_ISR_GIF1_Pos (4U)
6377#define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos)
6378#define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk
6379#define BDMA_ISR_TCIF1_Pos (5U)
6380#define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos)
6381#define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk
6382#define BDMA_ISR_HTIF1_Pos (6U)
6383#define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos)
6384#define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk
6385#define BDMA_ISR_TEIF1_Pos (7U)
6386#define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos)
6387#define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk
6388#define BDMA_ISR_GIF2_Pos (8U)
6389#define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos)
6390#define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk
6391#define BDMA_ISR_TCIF2_Pos (9U)
6392#define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos)
6393#define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk
6394#define BDMA_ISR_HTIF2_Pos (10U)
6395#define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos)
6396#define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk
6397#define BDMA_ISR_TEIF2_Pos (11U)
6398#define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos)
6399#define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk
6400#define BDMA_ISR_GIF3_Pos (12U)
6401#define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos)
6402#define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk
6403#define BDMA_ISR_TCIF3_Pos (13U)
6404#define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos)
6405#define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk
6406#define BDMA_ISR_HTIF3_Pos (14U)
6407#define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos)
6408#define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk
6409#define BDMA_ISR_TEIF3_Pos (15U)
6410#define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos)
6411#define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk
6412#define BDMA_ISR_GIF4_Pos (16U)
6413#define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos)
6414#define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk
6415#define BDMA_ISR_TCIF4_Pos (17U)
6416#define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos)
6417#define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk
6418#define BDMA_ISR_HTIF4_Pos (18U)
6419#define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos)
6420#define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk
6421#define BDMA_ISR_TEIF4_Pos (19U)
6422#define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos)
6423#define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk
6424#define BDMA_ISR_GIF5_Pos (20U)
6425#define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos)
6426#define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk
6427#define BDMA_ISR_TCIF5_Pos (21U)
6428#define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos)
6429#define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk
6430#define BDMA_ISR_HTIF5_Pos (22U)
6431#define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos)
6432#define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk
6433#define BDMA_ISR_TEIF5_Pos (23U)
6434#define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos)
6435#define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk
6436#define BDMA_ISR_GIF6_Pos (24U)
6437#define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos)
6438#define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk
6439#define BDMA_ISR_TCIF6_Pos (25U)
6440#define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos)
6441#define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk
6442#define BDMA_ISR_HTIF6_Pos (26U)
6443#define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos)
6444#define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk
6445#define BDMA_ISR_TEIF6_Pos (27U)
6446#define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos)
6447#define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk
6448#define BDMA_ISR_GIF7_Pos (28U)
6449#define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos)
6450#define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk
6451#define BDMA_ISR_TCIF7_Pos (29U)
6452#define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos)
6453#define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk
6454#define BDMA_ISR_HTIF7_Pos (30U)
6455#define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos)
6456#define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk
6457#define BDMA_ISR_TEIF7_Pos (31U)
6458#define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos)
6459#define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk
6461/******************* Bit definition for BDMA_IFCR register *******************/
6462#define BDMA_IFCR_CGIF0_Pos (0U)
6463#define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos)
6464#define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk
6465#define BDMA_IFCR_CTCIF0_Pos (1U)
6466#define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos)
6467#define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk
6468#define BDMA_IFCR_CHTIF0_Pos (2U)
6469#define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos)
6470#define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk
6471#define BDMA_IFCR_CTEIF0_Pos (3U)
6472#define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos)
6473#define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk
6474#define BDMA_IFCR_CGIF1_Pos (4U)
6475#define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos)
6476#define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk
6477#define BDMA_IFCR_CTCIF1_Pos (5U)
6478#define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos)
6479#define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk
6480#define BDMA_IFCR_CHTIF1_Pos (6U)
6481#define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos)
6482#define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk
6483#define BDMA_IFCR_CTEIF1_Pos (7U)
6484#define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos)
6485#define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk
6486#define BDMA_IFCR_CGIF2_Pos (8U)
6487#define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos)
6488#define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk
6489#define BDMA_IFCR_CTCIF2_Pos (9U)
6490#define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos)
6491#define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk
6492#define BDMA_IFCR_CHTIF2_Pos (10U)
6493#define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos)
6494#define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk
6495#define BDMA_IFCR_CTEIF2_Pos (11U)
6496#define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos)
6497#define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk
6498#define BDMA_IFCR_CGIF3_Pos (12U)
6499#define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos)
6500#define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk
6501#define BDMA_IFCR_CTCIF3_Pos (13U)
6502#define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos)
6503#define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk
6504#define BDMA_IFCR_CHTIF3_Pos (14U)
6505#define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos)
6506#define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk
6507#define BDMA_IFCR_CTEIF3_Pos (15U)
6508#define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos)
6509#define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk
6510#define BDMA_IFCR_CGIF4_Pos (16U)
6511#define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos)
6512#define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk
6513#define BDMA_IFCR_CTCIF4_Pos (17U)
6514#define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos)
6515#define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk
6516#define BDMA_IFCR_CHTIF4_Pos (18U)
6517#define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos)
6518#define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk
6519#define BDMA_IFCR_CTEIF4_Pos (19U)
6520#define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos)
6521#define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk
6522#define BDMA_IFCR_CGIF5_Pos (20U)
6523#define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos)
6524#define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk
6525#define BDMA_IFCR_CTCIF5_Pos (21U)
6526#define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos)
6527#define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk
6528#define BDMA_IFCR_CHTIF5_Pos (22U)
6529#define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos)
6530#define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk
6531#define BDMA_IFCR_CTEIF5_Pos (23U)
6532#define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos)
6533#define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk
6534#define BDMA_IFCR_CGIF6_Pos (24U)
6535#define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos)
6536#define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk
6537#define BDMA_IFCR_CTCIF6_Pos (25U)
6538#define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos)
6539#define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk
6540#define BDMA_IFCR_CHTIF6_Pos (26U)
6541#define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos)
6542#define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk
6543#define BDMA_IFCR_CTEIF6_Pos (27U)
6544#define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos)
6545#define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk
6546#define BDMA_IFCR_CGIF7_Pos (28U)
6547#define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos)
6548#define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk
6549#define BDMA_IFCR_CTCIF7_Pos (29U)
6550#define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos)
6551#define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk
6552#define BDMA_IFCR_CHTIF7_Pos (30U)
6553#define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos)
6554#define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk
6555#define BDMA_IFCR_CTEIF7_Pos (31U)
6556#define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos)
6557#define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk
6559/******************* Bit definition for BDMA_CCR register ********************/
6560#define BDMA_CCR_EN_Pos (0U)
6561#define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos)
6562#define BDMA_CCR_EN BDMA_CCR_EN_Msk
6563#define BDMA_CCR_TCIE_Pos (1U)
6564#define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos)
6565#define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk
6566#define BDMA_CCR_HTIE_Pos (2U)
6567#define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos)
6568#define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk
6569#define BDMA_CCR_TEIE_Pos (3U)
6570#define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos)
6571#define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk
6572#define BDMA_CCR_DIR_Pos (4U)
6573#define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos)
6574#define BDMA_CCR_DIR BDMA_CCR_DIR_Msk
6575#define BDMA_CCR_CIRC_Pos (5U)
6576#define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos)
6577#define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk
6578#define BDMA_CCR_PINC_Pos (6U)
6579#define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos)
6580#define BDMA_CCR_PINC BDMA_CCR_PINC_Msk
6581#define BDMA_CCR_MINC_Pos (7U)
6582#define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos)
6583#define BDMA_CCR_MINC BDMA_CCR_MINC_Msk
6585#define BDMA_CCR_PSIZE_Pos (8U)
6586#define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos)
6587#define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk
6588#define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos)
6589#define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos)
6591#define BDMA_CCR_MSIZE_Pos (10U)
6592#define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos)
6593#define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk
6594#define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos)
6595#define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos)
6597#define BDMA_CCR_PL_Pos (12U)
6598#define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos)
6599#define BDMA_CCR_PL BDMA_CCR_PL_Msk
6600#define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos)
6601#define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos)
6603#define BDMA_CCR_MEM2MEM_Pos (14U)
6604#define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos)
6605#define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk
6606#define BDMA_CCR_DBM_Pos (15U)
6607#define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos)
6608#define BDMA_CCR_DBM BDMA_CCR_DBM_Msk
6609#define BDMA_CCR_CT_Pos (16U)
6610#define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos)
6611#define BDMA_CCR_CT BDMA_CCR_CT_Msk
6613/****************** Bit definition for BDMA_CNDTR register *******************/
6614#define BDMA_CNDTR_NDT_Pos (0U)
6615#define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos)
6616#define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk
6618/****************** Bit definition for BDMA_CPAR register ********************/
6619#define BDMA_CPAR_PA_Pos (0U)
6620#define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)
6621#define BDMA_CPAR_PA BDMA_CPAR_PA_Msk
6623/****************** Bit definition for BDMA_CM0AR register ********************/
6624#define BDMA_CM0AR_MA_Pos (0U)
6625#define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)
6626#define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk
6628/****************** Bit definition for BDMA_CM1AR register ********************/
6629#define BDMA_CM1AR_MA_Pos (0U)
6630#define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)
6631#define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk
6633/******************************************************************************/
6634/* */
6635/* Ethernet MAC Registers bits definitions */
6636/* */
6637/******************************************************************************/
6638/* Bit definition for Ethernet MAC Configuration Register register */
6639#define ETH_MACCR_ARP_Pos (31U)
6640#define ETH_MACCR_ARP_Msk (0x1UL << ETH_MACCR_ARP_Pos)
6641#define ETH_MACCR_ARP ETH_MACCR_ARP_Msk /* ARP Offload Enable */
6642#define ETH_MACCR_SARC_Pos (28U)
6643#define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos)
6644#define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
6645#define ETH_MACCR_SARC_MTIATI (0U) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
6646#define ETH_MACCR_SARC_INSADDR0_Pos (29U)
6647#define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos)
6648#define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
6649#define ETH_MACCR_SARC_INSADDR1_Pos (29U)
6650#define ETH_MACCR_SARC_INSADDR1_Msk (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos)
6651#define ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
6652#define ETH_MACCR_SARC_REPADDR0_Pos (28U)
6653#define ETH_MACCR_SARC_REPADDR0_Msk (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos)
6654#define ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
6655#define ETH_MACCR_SARC_REPADDR1_Pos (28U)
6656#define ETH_MACCR_SARC_REPADDR1_Msk (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos)
6657#define ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
6658#define ETH_MACCR_IPC_Pos (27U)
6659#define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos)
6660#define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /* Checksum Offload */
6661#define ETH_MACCR_IPG_Pos (24U)
6662#define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos)
6663#define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
6664#define ETH_MACCR_IPG_96BIT (0U) /* Minimum IFG between Packets during transmission is 96Bit */
6665#define ETH_MACCR_IPG_88BIT (0x01000000U) /* Minimum IFG between Packets during transmission is 88Bit */
6666#define ETH_MACCR_IPG_80BIT (0x02000000U) /* Minimum IFG between Packets during transmission is 80Bit */
6667#define ETH_MACCR_IPG_72BIT (0x03000000U) /* Minimum IFG between Packets during transmission is 72Bit */
6668#define ETH_MACCR_IPG_64BIT (0x04000000U) /* Minimum IFG between Packets during transmission is 64Bit */
6669#define ETH_MACCR_IPG_56BIT (0x05000000U) /* Minimum IFG between Packets during transmission is 56Bit */
6670#define ETH_MACCR_IPG_48BIT (0x06000000U) /* Minimum IFG between Packets during transmission is 48Bit */
6671#define ETH_MACCR_IPG_40BIT (0x07000000U) /* Minimum IFG between Packets during transmission is 40Bit */
6672#define ETH_MACCR_GPSLCE_Pos (23U)
6673#define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos)
6674#define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
6675#define ETH_MACCR_S2KP_Pos (22U)
6676#define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos)
6677#define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */
6678#define ETH_MACCR_CST_Pos (21U)
6679#define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos)
6680#define ETH_MACCR_CST ETH_MACCR_CST_Msk /* CRC stripping for Type packets */
6681#define ETH_MACCR_ACS_Pos (20U)
6682#define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos)
6683#define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */
6684#define ETH_MACCR_WD_Pos (19U)
6685#define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)
6686#define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
6687#define ETH_MACCR_JD_Pos (17U)
6688#define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)
6689#define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
6690#define ETH_MACCR_JE_Pos (16U)
6691#define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos)
6692#define ETH_MACCR_JE ETH_MACCR_JE_Msk /* Jumbo Packet Enable */
6693#define ETH_MACCR_FES_Pos (14U)
6694#define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)
6695#define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
6696#define ETH_MACCR_DM_Pos (13U)
6697#define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)
6698#define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
6699#define ETH_MACCR_LM_Pos (12U)
6700#define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)
6701#define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
6702#define ETH_MACCR_ECRSFD_Pos (11U)
6703#define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos)
6704#define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
6705#define ETH_MACCR_DO_Pos (10U)
6706#define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos)
6707#define ETH_MACCR_DO ETH_MACCR_DO_Msk /* Disable Receive own */
6708#define ETH_MACCR_DCRS_Pos (9U)
6709#define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos)
6710#define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */
6711#define ETH_MACCR_DR_Pos (8U)
6712#define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos)
6713#define ETH_MACCR_DR ETH_MACCR_DR_Msk /* Disable Retry */
6714#define ETH_MACCR_BL_Pos (5U)
6715#define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)
6716#define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit mask */
6717#define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos)
6718#define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos)
6719#define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos)
6720#define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos)
6721#define ETH_MACCR_DC_Pos (4U)
6722#define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)
6723#define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
6724#define ETH_MACCR_PRELEN_Pos (2U)
6725#define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos)
6726#define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */
6727#define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos)
6728#define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos)
6729#define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos)
6730#define ETH_MACCR_TE_Pos (1U)
6731#define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)
6732#define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
6733#define ETH_MACCR_RE_Pos (0U)
6734#define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)
6735#define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
6736
6737/* Bit definition for Ethernet MAC Extended Configuration Register register */
6738#define ETH_MACECR_EIPG_Pos (25U)
6739#define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos)
6740#define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */
6741#define ETH_MACECR_EIPGEN_Pos (24U)
6742#define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos)
6743#define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */
6744#define ETH_MACECR_USP_Pos (18U)
6745#define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos)
6746#define ETH_MACECR_USP ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */
6747#define ETH_MACECR_SPEN_Pos (17U)
6748#define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos)
6749#define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */
6750#define ETH_MACECR_DCRCC_Pos (16U)
6751#define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos)
6752#define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */
6753#define ETH_MACECR_GPSL_Pos (0U)
6754#define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos)
6755#define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */
6756
6757/* Bit definition for Ethernet MAC Packet Filter Register */
6758#define ETH_MACPFR_RA_Pos (31U)
6759#define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos)
6760#define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /* Receive all */
6761#define ETH_MACPFR_DNTU_Pos (21U)
6762#define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos)
6763#define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */
6764#define ETH_MACPFR_IPFE_Pos (20U)
6765#define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos)
6766#define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */
6767#define ETH_MACPFR_VTFE_Pos (16U)
6768#define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos)
6769#define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */
6770#define ETH_MACPFR_HPF_Pos (10U)
6771#define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos)
6772#define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /* Hash or perfect filter */
6773#define ETH_MACPFR_SAF_Pos (9U)
6774#define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos)
6775#define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /* Source address filter enable */
6776#define ETH_MACPFR_SAIF_Pos (8U)
6777#define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos)
6778#define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /* SA inverse filtering */
6779#define ETH_MACPFR_PCF_Pos (6U)
6780#define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos)
6781#define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
6782#define ETH_MACPFR_PCF_BLOCKALL (0U) /* MAC filters all control frames from reaching the application */
6783#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
6784#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos)
6785#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
6786#define ETH_MACPFR_PCF_FORWARDALL_Pos (7U)
6787#define ETH_MACPFR_PCF_FORWARDALL_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos)
6788#define ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
6789#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U)
6790#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos)
6791#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
6792#define ETH_MACPFR_DBF_Pos (5U)
6793#define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos)
6794#define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */
6795#define ETH_MACPFR_PM_Pos (4U)
6796#define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos)
6797#define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /* Pass all mutlicast */
6798#define ETH_MACPFR_DAIF_Pos (3U)
6799#define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos)
6800#define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */
6801#define ETH_MACPFR_HMC_Pos (2U)
6802#define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos)
6803#define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /* Hash multicast */
6804#define ETH_MACPFR_HUC_Pos (1U)
6805#define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos)
6806#define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /* Hash unicast */
6807#define ETH_MACPFR_PR_Pos (0U)
6808#define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos)
6809#define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /* Promiscuous mode */
6810
6811/* Bit definition for Ethernet MAC Watchdog Timeout Register */
6812#define ETH_MACWTR_PWE_Pos (8U)
6813#define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos)
6814#define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */
6815#define ETH_MACWTR_WTO_Pos (0U)
6816#define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos)
6817#define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
6818#define ETH_MACWTR_WTO_2KB (0U) /* Maximum received packet length 2KB*/
6819#define ETH_MACWTR_WTO_3KB (0x00000001U) /* Maximum received packet length 3KB */
6820#define ETH_MACWTR_WTO_4KB (0x00000002U) /* Maximum received packet length 4KB */
6821#define ETH_MACWTR_WTO_5KB (0x00000003U) /* Maximum received packet length 5KB */
6822#define ETH_MACWTR_WTO_6KB (0x00000004U) /* Maximum received packet length 6KB */
6823#define ETH_MACWTR_WTO_7KB (0x00000005U) /* Maximum received packet length 7KB */
6824#define ETH_MACWTR_WTO_8KB (0x00000006U) /* Maximum received packet length 8KB */
6825#define ETH_MACWTR_WTO_9KB (0x00000007U) /* Maximum received packet length 9KB */
6826#define ETH_MACWTR_WTO_10KB (0x00000008U) /* Maximum received packet length 10KB */
6827#define ETH_MACWTR_WTO_11KB (0x00000009U) /* Maximum received packet length 11KB */
6828#define ETH_MACWTR_WTO_12KB (0x0000000AU) /* Maximum received packet length 12KB */
6829#define ETH_MACWTR_WTO_13KB (0x0000000BU) /* Maximum received packet length 13KB */
6830#define ETH_MACWTR_WTO_14KB (0x0000000CU) /* Maximum received packet length 14KB */
6831#define ETH_MACWTR_WTO_15KB (0x0000000DU) /* Maximum received packet length 15KB */
6832#define ETH_MACWTR_WTO_16KB (0x0000000EU) /* Maximum received packet length 16KB */
6833
6834/* Bit definition for Ethernet MAC Hash Table High Register */
6835#define ETH_MACHTHR_HTH_Pos (0U)
6836#define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)
6837#define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
6838
6839/* Bit definition for Ethernet MAC Hash Table Low Register */
6840#define ETH_MACHTLR_HTL_Pos (0U)
6841#define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)
6842#define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
6843
6844/* Bit definition for Ethernet MAC VLAN Tag Register */
6845#define ETH_MACVTR_EIVLRXS_Pos (31U)
6846#define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos)
6847#define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */
6848#define ETH_MACVTR_EIVLS_Pos (28U)
6849#define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos)
6850#define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
6851#define ETH_MACVTR_EIVLS_DONOTSTRIP (0U) /* Do not strip */
6852#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
6853#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos)
6854#define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
6855#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U)
6856#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos)
6857#define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
6858#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U)
6859#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos)
6860#define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
6861#define ETH_MACVTR_ERIVLT_Pos (27U)
6862#define ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos)
6863#define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /* Enable Inner VLAN Tag */
6864#define ETH_MACVTR_EDVLP_Pos (26U)
6865#define ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos)
6866#define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /* Enable Double VLAN Processing */
6867#define ETH_MACVTR_VTHM_Pos (25U)
6868#define ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos)
6869#define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */
6870#define ETH_MACVTR_EVLRXS_Pos (24U)
6871#define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos)
6872#define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */
6873#define ETH_MACVTR_EVLS_Pos (21U)
6874#define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos)
6875#define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
6876#define ETH_MACVTR_EVLS_DONOTSTRIP (0U) /* Do not strip */
6877#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
6878#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos)
6879#define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
6880#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U)
6881#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos)
6882#define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
6883#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U)
6884#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos)
6885#define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
6886#define ETH_MACVTR_DOVLTC_Pos (20U)
6887#define ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos)
6888#define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /* Disable VLAN Type Check */
6889#define ETH_MACVTR_ERSVLM_Pos (19U)
6890#define ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos)
6891#define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-VLAN Match */
6892#define ETH_MACVTR_ESVL_Pos (18U)
6893#define ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos)
6894#define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
6895#define ETH_MACVTR_VTIM_Pos (17U)
6896#define ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos)
6897#define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /* VLAN Tag Inverse Match Enable */
6898#define ETH_MACVTR_ETV_Pos (16U)
6899#define ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos)
6900#define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */
6901#define ETH_MACVTR_VL_Pos (0U)
6902#define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos)
6903#define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /* VLAN Tag Identifier for Receive Packets */
6904#define ETH_MACVTR_VL_UP_Pos (13U)
6905#define ETH_MACVTR_VL_UP_Msk (0x7UL << ETH_MACVTR_VL_UP_Pos)
6906#define ETH_MACVTR_VL_UP ETH_MACVTR_VL_UP_Msk /* User Priority */
6907#define ETH_MACVTR_VL_CFIDEI_Pos (12U)
6908#define ETH_MACVTR_VL_CFIDEI_Msk (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos)
6909#define ETH_MACVTR_VL_CFIDEI ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
6910#define ETH_MACVTR_VL_VID_Pos (0U)
6911#define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos)
6912#define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /* VLAN Identifier field of VLAN tag */
6913
6914/* Bit definition for Ethernet MAC VLAN Hash Table Register */
6915#define ETH_MACVHTR_VLHT_Pos (0U)
6916#define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos)
6917#define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */
6918
6919/* Bit definition for Ethernet MAC VLAN Incl Register */
6920#define ETH_MACVIR_VLTI_Pos (20U)
6921#define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos)
6922#define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */
6923#define ETH_MACVIR_CSVL_Pos (19U)
6924#define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos)
6925#define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */
6926#define ETH_MACVIR_VLP_Pos (18U)
6927#define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos)
6928#define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /* VLAN Priority Control */
6929#define ETH_MACVIR_VLC_Pos (16U)
6930#define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos)
6931#define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
6932#define ETH_MACVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
6933#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
6934#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos)
6935#define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
6936#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U)
6937#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos)
6938#define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
6939#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U)
6940#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos)
6941#define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
6942#define ETH_MACVIR_VLT_Pos (0U)
6943#define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos)
6944#define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
6945#define ETH_MACVIR_VLT_UP_Pos (13U)
6946#define ETH_MACVIR_VLT_UP_Msk (0x7UL << ETH_MACVIR_VLT_UP_Pos)
6947#define ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk /* User Priority */
6948#define ETH_MACVIR_VLT_CFIDEI_Pos (12U)
6949#define ETH_MACVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos)
6950#define ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
6951#define ETH_MACVIR_VLT_VID_Pos (0U)
6952#define ETH_MACVIR_VLT_VID_Msk (0xFFFUL << ETH_MACVIR_VLT_VID_Pos)
6953#define ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
6954
6955/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
6956#define ETH_MACIVIR_VLTI_Pos (20U)
6957#define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos)
6958#define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */
6959#define ETH_MACIVIR_CSVL_Pos (19U)
6960#define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos)
6961#define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */
6962#define ETH_MACIVIR_VLP_Pos (18U)
6963#define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos)
6964#define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */
6965#define ETH_MACIVIR_VLC_Pos (16U)
6966#define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos)
6967#define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
6968#define ETH_MACIVIR_VLC_NOVLANTAG (0U) /* No VLAN tag deletion, insertion, or replacement */
6969#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
6970#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos)
6971#define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
6972#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U)
6973#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos)
6974#define ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
6975#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U)
6976#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos)
6977#define ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
6978#define ETH_MACIVIR_VLT_Pos (0U)
6979#define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos)
6980#define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
6981#define ETH_MACIVIR_VLT_UP_Pos (13U)
6982#define ETH_MACIVIR_VLT_UP_Msk (0x7UL << ETH_MACIVIR_VLT_UP_Pos)
6983#define ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk /* User Priority */
6984#define ETH_MACIVIR_VLT_CFIDEI_Pos (12U)
6985#define ETH_MACIVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos)
6986#define ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
6987#define ETH_MACIVIR_VLT_VID_Pos (0U)
6988#define ETH_MACIVIR_VLT_VID_Msk (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos)
6989#define ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
6990
6991/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
6992#define ETH_MACTFCR_PT_Pos (16U)
6993#define ETH_MACTFCR_PT_Msk (0xFFFFUL << ETH_MACTFCR_PT_Pos)
6994#define ETH_MACTFCR_PT ETH_MACTFCR_PT_Msk /* Pause Time */
6995#define ETH_MACTFCR_DZPQ_Pos (7U)
6996#define ETH_MACTFCR_DZPQ_Msk (0x1UL << ETH_MACTFCR_DZPQ_Pos)
6997#define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */
6998#define ETH_MACTFCR_PLT_Pos (4U)
6999#define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos)
7000#define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
7001#define ETH_MACTFCR_PLT_MINUS4 (0U) /* Pause time minus 4 slot times */
7002#define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
7003#define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos)
7004#define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
7005#define ETH_MACTFCR_PLT_MINUS36_Pos (5U)
7006#define ETH_MACTFCR_PLT_MINUS36_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos)
7007#define ETH_MACTFCR_PLT_MINUS36 ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
7008#define ETH_MACTFCR_PLT_MINUS144_Pos (4U)
7009#define ETH_MACTFCR_PLT_MINUS144_Msk (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos)
7010#define ETH_MACTFCR_PLT_MINUS144 ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
7011#define ETH_MACTFCR_PLT_MINUS256_Pos (6U)
7012#define ETH_MACTFCR_PLT_MINUS256_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos)
7013#define ETH_MACTFCR_PLT_MINUS256 ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
7014#define ETH_MACTFCR_PLT_MINUS512_Pos (4U)
7015#define ETH_MACTFCR_PLT_MINUS512_Msk (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos)
7016#define ETH_MACTFCR_PLT_MINUS512 ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
7017#define ETH_MACTFCR_TFE_Pos (1U)
7018#define ETH_MACTFCR_TFE_Msk (0x1UL << ETH_MACTFCR_TFE_Pos)
7019#define ETH_MACTFCR_TFE ETH_MACTFCR_TFE_Msk /* Transmit Flow Control Enable */
7020#define ETH_MACTFCR_FCB_Pos (0U)
7021#define ETH_MACTFCR_FCB_Msk (0x1UL << ETH_MACTFCR_FCB_Pos)
7022#define ETH_MACTFCR_FCB ETH_MACTFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */
7023
7024/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
7025#define ETH_MACRFCR_UP_Pos (1U)
7026#define ETH_MACRFCR_UP_Msk (0x1UL << ETH_MACRFCR_UP_Pos)
7027#define ETH_MACRFCR_UP ETH_MACRFCR_UP_Msk /* Unicast Pause Packet Detect */
7028#define ETH_MACRFCR_RFE_Pos (0U)
7029#define ETH_MACRFCR_RFE_Msk (0x1UL << ETH_MACRFCR_RFE_Pos)
7030#define ETH_MACRFCR_RFE ETH_MACRFCR_RFE_Msk /* Receive Flow Control Enable */
7031
7032/* Bit definition for Ethernet MAC Interrupt Status Register */
7033#define ETH_MACISR_RXSTSIS_Pos (14U)
7034#define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos)
7035#define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */
7036#define ETH_MACISR_TXSTSIS_Pos (13U)
7037#define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos)
7038#define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */
7039#define ETH_MACISR_TSIS_Pos (12U)
7040#define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos)
7041#define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */
7042#define ETH_MACISR_MMCTXIS_Pos (10U)
7043#define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos)
7044#define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */
7045#define ETH_MACISR_MMCRXIS_Pos (9U)
7046#define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos)
7047#define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */
7048#define ETH_MACISR_MMCIS_Pos (8U)
7049#define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos)
7050#define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */
7051#define ETH_MACISR_LPIIS_Pos (5U)
7052#define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos)
7053#define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */
7054#define ETH_MACISR_PMTIS_Pos (4U)
7055#define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos)
7056#define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */
7057#define ETH_MACISR_PHYIS_Pos (3U)
7058#define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos)
7059#define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /* PHY Interrupt */
7060
7061/* Bit definition for Ethernet MAC Interrupt Enable Register */
7062#define ETH_MACIER_RXSTSIE_Pos (14U)
7063#define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos)
7064#define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */
7065#define ETH_MACIER_TXSTSIE_Pos (13U)
7066#define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos)
7067#define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */
7068#define ETH_MACIER_TSIE_Pos (12U)
7069#define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos)
7070#define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */
7071#define ETH_MACIER_LPIIE_Pos (5U)
7072#define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos)
7073#define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */
7074#define ETH_MACIER_PMTIE_Pos (4U)
7075#define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos)
7076#define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */
7077#define ETH_MACIER_PHYIE_Pos (3U)
7078#define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos)
7079#define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */
7080
7081/* Bit definition for Ethernet MAC Rx Tx Status Register */
7082#define ETH_MACRXTXSR_RWT_Pos (8U)
7083#define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos)
7084#define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */
7085#define ETH_MACRXTXSR_EXCOL_Pos (5U)
7086#define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos)
7087#define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */
7088#define ETH_MACRXTXSR_LCOL_Pos (4U)
7089#define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos)
7090#define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /* Late Collision */
7091#define ETH_MACRXTXSR_EXDEF_Pos (3U)
7092#define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos)
7093#define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */
7094#define ETH_MACRXTXSR_LCARR_Pos (2U)
7095#define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos)
7096#define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */
7097#define ETH_MACRXTXSR_NCARR_Pos (1U)
7098#define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos)
7099#define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /* No Carrier */
7100#define ETH_MACRXTXSR_TJT_Pos (0U)
7101#define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos)
7102#define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */
7103
7104/* Bit definition for Ethernet MAC PMT Control Status Register */
7105#define ETH_MACPCSR_RWKFILTRST_Pos (31U)
7106#define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos)
7107#define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
7108#define ETH_MACPCSR_RWKPTR_Pos (24U)
7109#define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos)
7110#define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */
7111#define ETH_MACPCSR_RWKPFE_Pos (10U)
7112#define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos)
7113#define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */
7114#define ETH_MACPCSR_GLBLUCAST_Pos (9U)
7115#define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos)
7116#define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
7117#define ETH_MACPCSR_RWKPRCVD_Pos (6U)
7118#define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos)
7119#define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
7120#define ETH_MACPCSR_MGKPRCVD_Pos (5U)
7121#define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos)
7122#define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
7123#define ETH_MACPCSR_RWKPKTEN_Pos (2U)
7124#define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos)
7125#define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
7126#define ETH_MACPCSR_MGKPKTEN_Pos (1U)
7127#define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos)
7128#define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
7129#define ETH_MACPCSR_PWRDWN_Pos (0U)
7130#define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos)
7131#define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /* Power Down */
7132
7133/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
7134#define ETH_MACRWUPFR_D_Pos (0U)
7135#define ETH_MACRWUPFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos)
7136#define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet filter register data */
7137
7138/* Bit definition for Ethernet MAC LPI Control Status Register */
7139#define ETH_MACLCSR_LPITCSE_Pos (21U)
7140#define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos)
7141#define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */
7142#define ETH_MACLCSR_LPITE_Pos (20U)
7143#define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos)
7144#define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */
7145#define ETH_MACLCSR_LPITXA_Pos (19U)
7146#define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos)
7147#define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */
7148#define ETH_MACLCSR_PLS_Pos (17U)
7149#define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos)
7150#define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /* PHY Link Status */
7151#define ETH_MACLCSR_LPIEN_Pos (16U)
7152#define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos)
7153#define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /* LPI Enable */
7154#define ETH_MACLCSR_RLPIST_Pos (9U)
7155#define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos)
7156#define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */
7157#define ETH_MACLCSR_TLPIST_Pos (8U)
7158#define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos)
7159#define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */
7160#define ETH_MACLCSR_RLPIEX_Pos (3U)
7161#define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos)
7162#define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */
7163#define ETH_MACLCSR_RLPIEN_Pos (2U)
7164#define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos)
7165#define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */
7166#define ETH_MACLCSR_TLPIEX_Pos (1U)
7167#define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos)
7168#define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */
7169#define ETH_MACLCSR_TLPIEN_Pos (0U)
7170#define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos)
7171#define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */
7172
7173/* Bit definition for Ethernet MAC LPI Timers Control Register */
7174#define ETH_MACLTCR_LST_Pos (16U)
7175#define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos)
7176#define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /* LPI LS TIMER */
7177#define ETH_MACLTCR_TWT_Pos (0U)
7178#define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos)
7179#define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */
7180
7181/* Bit definition for Ethernet MAC LPI Entry Timer Register */
7182#define ETH_MACLETR_LPIET_Pos (0U)
7183#define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos)
7184#define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */
7185
7186/* Bit definition for Ethernet MAC 1US Tic Counter Register */
7187#define ETH_MAC1USTCR_TIC1USCNTR_Pos (0U)
7188#define ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos)
7189#define ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
7190
7191/* Bit definition for Ethernet MAC Version Register */
7192#define ETH_MACVR_USERVER_Pos (8U)
7193#define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos)
7194#define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Version */
7195#define ETH_MACVR_SNPSVER_Pos (0U)
7196#define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos)
7197#define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */
7198
7199/* Bit definition for Ethernet MAC Debug Register */
7200#define ETH_MACDR_TFCSTS_Pos (17U)
7201#define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos)
7202#define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
7203#define ETH_MACDR_TFCSTS_IDLE (0U) /* Idle state */
7204#define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
7205#define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos)
7206#define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
7207#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U)
7208#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos)
7209#define ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
7210#define ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U)
7211#define ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos)
7212#define ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
7213#define ETH_MACDR_TPESTS_Pos (16U)
7214#define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos)
7215#define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */
7216#define ETH_MACDR_RFCFCSTS_Pos (1U)
7217#define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos)
7218#define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */
7219#define ETH_MACDR_RPESTS_Pos (0U)
7220#define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos)
7221#define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */
7222
7223/* Bit definition for Ethernet MAC HW Feature0 Register */
7224#define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
7225#define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos)
7226#define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
7227#define ETH_MACHWF0R_ACTPHYSEL_MII (0U) /* MII */
7228#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
7229#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos)
7230#define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
7231#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos (28U)
7232#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos)
7233#define ETH_MACHWF0R_ACTPHYSEL_REVMII ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
7234#define ETH_MACHWF0R_SAVLANINS_Pos (27U)
7235#define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos)
7236#define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
7237#define ETH_MACHWF0R_TSSTSSEL_Pos (25U)
7238#define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos)
7239#define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
7240#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U)
7241#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos)
7242#define ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
7243#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U)
7244#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos)
7245#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
7246#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U)
7247#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos)
7248#define ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
7249#define ETH_MACHWF0R_MACADR64SEL_Pos (24U)
7250#define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos)
7251#define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
7252#define ETH_MACHWF0R_MACADR32SEL_Pos (23U)
7253#define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos)
7254#define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
7255#define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U)
7256#define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos)
7257#define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
7258#define ETH_MACHWF0R_RXCOESEL_Pos (16U)
7259#define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos)
7260#define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
7261#define ETH_MACHWF0R_TXCOESEL_Pos (14U)
7262#define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos)
7263#define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
7264#define ETH_MACHWF0R_EEESEL_Pos (13U)
7265#define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos)
7266#define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */
7267#define ETH_MACHWF0R_TSSEL_Pos (12U)
7268#define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos)
7269#define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */
7270#define ETH_MACHWF0R_ARPOFFSEL_Pos (9U)
7271#define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos)
7272#define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
7273#define ETH_MACHWF0R_MMCSEL_Pos (8U)
7274#define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos)
7275#define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */
7276#define ETH_MACHWF0R_MGKSEL_Pos (7U)
7277#define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos)
7278#define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */
7279#define ETH_MACHWF0R_RWKSEL_Pos (6U)
7280#define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos)
7281#define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */
7282#define ETH_MACHWF0R_SMASEL_Pos (5U)
7283#define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos)
7284#define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */
7285#define ETH_MACHWF0R_VLHASH_Pos (4U)
7286#define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos)
7287#define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */
7288#define ETH_MACHWF0R_PCSSEL_Pos (3U)
7289#define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos)
7290#define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
7291#define ETH_MACHWF0R_HDSEL_Pos (2U)
7292#define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos)
7293#define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */
7294#define ETH_MACHWF0R_GMIISEL_Pos (1U)
7295#define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos)
7296#define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
7297#define ETH_MACHWF0R_MIISEL_Pos (0U)
7298#define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos)
7299#define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */
7300
7301/* Bit definition for Ethernet MAC HW Feature1 Register */
7302#define ETH_MACHWF1R_L3L4FNUM_Pos (27U)
7303#define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos)
7304#define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
7305#define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)
7306#define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos)
7307#define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
7308#define ETH_MACHWF1R_AVSEL_Pos (20U)
7309#define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos)
7310#define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */
7311#define ETH_MACHWF1R_DBGMEMA_Pos (19U)
7312#define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos)
7313#define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
7314#define ETH_MACHWF1R_TSOEN_Pos (18U)
7315#define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos)
7316#define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */
7317#define ETH_MACHWF1R_SPHEN_Pos (17U)
7318#define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos)
7319#define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */
7320#define ETH_MACHWF1R_DCBEN_Pos (16U)
7321#define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos)
7322#define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */
7323#define ETH_MACHWF1R_ADDR64_Pos (14U)
7324#define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos)
7325#define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /* Address Width */
7326#define ETH_MACHWF1R_ADDR64_32 (0x0UL << ETH_MACHWF1R_ADDR64_Pos)
7327#define ETH_MACHWF1R_ADDR64_40 (0x1UL << ETH_MACHWF1R_ADDR64_Pos)
7328#define ETH_MACHWF1R_ADDR64_48 (0x2UL << ETH_MACHWF1R_ADDR64_Pos)
7329#define ETH_MACHWF1R_ADVTHWORD_Pos (13U)
7330#define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos)
7331#define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
7332#define ETH_MACHWF1R_PTOEN_Pos (12U)
7333#define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos)
7334#define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */
7335#define ETH_MACHWF1R_OSTEN_Pos (11U)
7336#define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos)
7337#define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */
7338#define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)
7339#define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos)
7340#define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
7341#define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)
7342#define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos)
7343#define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
7344
7345/* Bit definition for Ethernet MAC HW Feature2 Register */
7346#define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)
7347#define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos)
7348#define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
7349#define ETH_MACHWF2R_PPSOUTNUM_Pos (24U)
7350#define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos)
7351#define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /* Number of PPS Outputs */
7352#define ETH_MACHWF2R_TXCHCNT_Pos (18U)
7353#define ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos)
7354#define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
7355#define ETH_MACHWF2R_RXCHCNT_Pos (13U)
7356#define ETH_MACHWF2R_RXCHCNT_Msk (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos)
7357#define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
7358#define ETH_MACHWF2R_TXQCNT_Pos (6U)
7359#define ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos)
7360#define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /* Number of MTL Transmit Queues */
7361#define ETH_MACHWF2R_RXQCNT_Pos (0U)
7362#define ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos)
7363#define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /* Number of MTL Receive Queues */
7364
7365/* Bit definition for Ethernet MAC MDIO Address Register */
7366#define ETH_MACMDIOAR_PSE_Pos (27U)
7367#define ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos)
7368#define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /* Preamble Suppression Enable */
7369#define ETH_MACMDIOAR_BTB_Pos (26U)
7370#define ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos)
7371#define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /* Back to Back transactions */
7372#define ETH_MACMDIOAR_PA_Pos (21U)
7373#define ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos)
7374#define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /* Physical Layer Address */
7375#define ETH_MACMDIOAR_RDA_Pos (16U)
7376#define ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos)
7377#define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /* Register/Device Address */
7378#define ETH_MACMDIOAR_NTC_Pos (12U)
7379#define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos)
7380#define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /* Number of Trailing Clocks */
7381#define ETH_MACMDIOAR_CR_Pos (8U)
7382#define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos)
7383#define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
7384#define ETH_MACMDIOAR_CR_DIV42 (0U) /* CSR clock/42 */
7385#define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
7386#define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos)
7387#define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
7388#define ETH_MACMDIOAR_CR_DIV16_Pos (9U)
7389#define ETH_MACMDIOAR_CR_DIV16_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos)
7390#define ETH_MACMDIOAR_CR_DIV16 ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
7391#define ETH_MACMDIOAR_CR_DIV26_Pos (8U)
7392#define ETH_MACMDIOAR_CR_DIV26_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos)
7393#define ETH_MACMDIOAR_CR_DIV26 ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
7394#define ETH_MACMDIOAR_CR_DIV102_Pos (10U)
7395#define ETH_MACMDIOAR_CR_DIV102_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos)
7396#define ETH_MACMDIOAR_CR_DIV102 ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
7397#define ETH_MACMDIOAR_CR_DIV124_Pos (8U)
7398#define ETH_MACMDIOAR_CR_DIV124_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos)
7399#define ETH_MACMDIOAR_CR_DIV124 ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
7400#define ETH_MACMDIOAR_CR_DIV4AR_Pos (11U)
7401#define ETH_MACMDIOAR_CR_DIV4AR_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos)
7402#define ETH_MACMDIOAR_CR_DIV4AR ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
7403#define ETH_MACMDIOAR_CR_DIV6AR_Pos (8U)
7404#define ETH_MACMDIOAR_CR_DIV6AR_Msk (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos)
7405#define ETH_MACMDIOAR_CR_DIV6AR ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
7406#define ETH_MACMDIOAR_CR_DIV8AR_Pos (9U)
7407#define ETH_MACMDIOAR_CR_DIV8AR_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos)
7408#define ETH_MACMDIOAR_CR_DIV8AR ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
7409#define ETH_MACMDIOAR_CR_DIV10AR_Pos (8U)
7410#define ETH_MACMDIOAR_CR_DIV10AR_Msk (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos)
7411#define ETH_MACMDIOAR_CR_DIV10AR ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
7412#define ETH_MACMDIOAR_CR_DIV12AR_Pos (10U)
7413#define ETH_MACMDIOAR_CR_DIV12AR_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos)
7414#define ETH_MACMDIOAR_CR_DIV12AR ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
7415#define ETH_MACMDIOAR_CR_DIV14AR_Pos (8U)
7416#define ETH_MACMDIOAR_CR_DIV14AR_Msk (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos)
7417#define ETH_MACMDIOAR_CR_DIV14AR ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
7418#define ETH_MACMDIOAR_CR_DIV16AR_Pos (9U)
7419#define ETH_MACMDIOAR_CR_DIV16AR_Msk (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos)
7420#define ETH_MACMDIOAR_CR_DIV16AR ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
7421#define ETH_MACMDIOAR_CR_DIV18AR_Pos (8U)
7422#define ETH_MACMDIOAR_CR_DIV18AR_Msk (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos)
7423#define ETH_MACMDIOAR_CR_DIV18AR ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
7424#define ETH_MACMDIOAR_SKAP_Pos (4U)
7425#define ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos)
7426#define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /* Skip Address Packet */
7427#define ETH_MACMDIOAR_MOC_Pos (2U)
7428#define ETH_MACMDIOAR_MOC_Msk (0x3UL << ETH_MACMDIOAR_MOC_Pos)
7429#define ETH_MACMDIOAR_MOC ETH_MACMDIOAR_MOC_Msk /* MII Operation Command */
7430#define ETH_MACMDIOAR_MOC_WR_Pos (2U)
7431#define ETH_MACMDIOAR_MOC_WR_Msk (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos)
7432#define ETH_MACMDIOAR_MOC_WR ETH_MACMDIOAR_MOC_WR_Msk /* Write */
7433#define ETH_MACMDIOAR_MOC_PRDIA_Pos (3U)
7434#define ETH_MACMDIOAR_MOC_PRDIA_Msk (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos)
7435#define ETH_MACMDIOAR_MOC_PRDIA ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
7436#define ETH_MACMDIOAR_MOC_RD_Pos (2U)
7437#define ETH_MACMDIOAR_MOC_RD_Msk (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos)
7438#define ETH_MACMDIOAR_MOC_RD ETH_MACMDIOAR_MOC_RD_Msk /* Read */
7439#define ETH_MACMDIOAR_C45E_Pos (1U)
7440#define ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos)
7441#define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /* Clause 45 PHY Enable */
7442#define ETH_MACMDIOAR_MB_Pos (0U)
7443#define ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos)
7444#define ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /* MII Busy */
7445
7446/* Bit definition for Ethernet MAC MDIO Data Register */
7447#define ETH_MACMDIODR_RA_Pos (16U)
7448#define ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos)
7449#define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /* Register Address */
7450#define ETH_MACMDIODR_MD_Pos (0U)
7451#define ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos)
7452#define ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /* MII Data */
7453
7454/* Bit definition for Ethernet ARP Address Register */
7455#define ETH_MACARPAR_ARPPA_Pos (0U)
7456#define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos)
7457#define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /* ARP Protocol Address */
7458
7459/* Bit definition for Ethernet MAC Address 0 High Register */
7460#define ETH_MACA0HR_AE_Pos (31U)
7461#define ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos)
7462#define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /* Address Enable*/
7463#define ETH_MACA0HR_ADDRHI_Pos (0U)
7464#define ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos)
7465#define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /* MAC Address 0*/
7466
7467/* Bit definition for Ethernet MAC Address 0 Low Register */
7468#define ETH_MACA0LR_ADDRLO_Pos (0U)
7469#define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos)
7470#define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /* MAC Address 0*/
7471
7472/* Bit definition for Ethernet MAC Address 1 High Register */
7473#define ETH_MACA1HR_AE_Pos (31U)
7474#define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)
7475#define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address Enable*/
7476#define ETH_MACA1HR_SA_Pos (30U)
7477#define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)
7478#define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source Address */
7479#define ETH_MACA1HR_MBC_Pos (24U)
7480#define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)
7481#define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
7482#define ETH_MACA1HR_ADDRHI_Pos (0U)
7483#define ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos)
7484#define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /* MAC Address 1*/
7485
7486/* Bit definition for Ethernet MAC Address 1 Low Register */
7487#define ETH_MACA1LR_ADDRLO_Pos (0U)
7488#define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos)
7489#define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /* MAC Address 1*/
7490
7491/* Bit definition for Ethernet MAC Address 2 High Register */
7492#define ETH_MACA2HR_AE_Pos (31U)
7493#define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)
7494#define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address Enable*/
7495#define ETH_MACA2HR_SA_Pos (30U)
7496#define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)
7497#define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source Address */
7498#define ETH_MACA2HR_MBC_Pos (24U)
7499#define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)
7500#define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
7501#define ETH_MACA2HR_ADDRHI_Pos (0U)
7502#define ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos)
7503#define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /* MAC Address 1*/
7504
7505/* Bit definition for Ethernet MAC Address 2 Low Register */
7506#define ETH_MACA2LR_ADDRLO_Pos (0U)
7507#define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos)
7508#define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /* MAC Address 2*/
7509
7510/* Bit definition for Ethernet MAC Address 3 High Register */
7511#define ETH_MACA3HR_AE_Pos (31U)
7512#define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)
7513#define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address Enable*/
7514#define ETH_MACA3HR_SA_Pos (30U)
7515#define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)
7516#define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source Address */
7517#define ETH_MACA3HR_MBC_Pos (24U)
7518#define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)
7519#define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
7520#define ETH_MACA3HR_ADDRHI_Pos (0U)
7521#define ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos)
7522#define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /* MAC Address 1*/
7523
7524/* Bit definition for Ethernet MAC Address 3 Low Register */
7525#define ETH_MACA3LR_ADDRLO_Pos (0U)
7526#define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos)
7527#define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /* MAC Address 3*/
7528
7529/* Bit definition for Ethernet MAC Address High Register */
7530#define ETH_MACAHR_AE_Pos (31U)
7531#define ETH_MACAHR_AE_Msk (0x1UL << ETH_MACAHR_AE_Pos)
7532#define ETH_MACAHR_AE ETH_MACAHR_AE_Msk /* Address enable */
7533#define ETH_MACAHR_SA_Pos (30U)
7534#define ETH_MACAHR_SA_Msk (0x1UL << ETH_MACAHR_SA_Pos)
7535#define ETH_MACAHR_SA ETH_MACAHR_SA_Msk /* Source address */
7536#define ETH_MACAHR_MBC_Pos (24U)
7537#define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos)
7538#define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7539#define ETH_MACAHR_MBC_HBITS15_8 (0x20000000U) /* Mask MAC Address high reg bits [15:8] */
7540#define ETH_MACAHR_MBC_HBITS7_0 (0x10000000U) /* Mask MAC Address high reg bits [7:0] */
7541#define ETH_MACAHR_MBC_LBITS31_24 (0x08000000U) /* Mask MAC Address low reg bits [31:24] */
7542#define ETH_MACAHR_MBC_LBITS23_16 (0x04000000U) /* Mask MAC Address low reg bits [23:16] */
7543#define ETH_MACAHR_MBC_LBITS15_8 (0x02000000U) /* Mask MAC Address low reg bits [15:8] */
7544#define ETH_MACAHR_MBC_LBITS7_0 (0x01000000U) /* Mask MAC Address low reg bits [7:0] */
7545#define ETH_MACAHR_MACAH_Pos (0U)
7546#define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos)
7547#define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
7548
7549/* Bit definition for Ethernet MAC Address Low Register */
7550#define ETH_MACALR_MACAL_Pos (0U)
7551#define ETH_MACALR_MACAL_Msk (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos)
7552#define ETH_MACALR_MACAL ETH_MACALR_MACAL_Msk /* MAC address low */
7553
7554/* Bit definition for Ethernet MMC Control Register */
7555#define ETH_MMCCR_UCDBC_Pos (8U)
7556#define ETH_MMCCR_UCDBC_Msk (0x1UL << ETH_MMCCR_UCDBC_Pos)
7557#define ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk /* Update MMC Counters for Dropped Broadcast Packets */
7558#define ETH_MMCCR_CNTPRSTLVL_Pos (5U)
7559#define ETH_MMCCR_CNTPRSTLVL_Msk (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos)
7560#define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset */
7561#define ETH_MMCCR_CNTPRST_Pos (4U)
7562#define ETH_MMCCR_CNTPRST_Msk (0x1UL << ETH_MMCCR_CNTPRST_Pos)
7563#define ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk /* Counters Reset */
7564#define ETH_MMCCR_CNTFREEZ_Pos (3U)
7565#define ETH_MMCCR_CNTFREEZ_Msk (0x1UL << ETH_MMCCR_CNTFREEZ_Pos)
7566#define ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk /* MMC Counter Freeze */
7567#define ETH_MMCCR_RSTONRD_Pos (2U)
7568#define ETH_MMCCR_RSTONRD_Msk (0x1UL << ETH_MMCCR_RSTONRD_Pos)
7569#define ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk /* Reset On Read */
7570#define ETH_MMCCR_CNTSTOPRO_Pos (1U)
7571#define ETH_MMCCR_CNTSTOPRO_Msk (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos)
7572#define ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk /* Counter Stop Rollover */
7573#define ETH_MMCCR_CNTRST_Pos (0U)
7574#define ETH_MMCCR_CNTRST_Msk (0x1UL << ETH_MMCCR_CNTRST_Pos)
7575#define ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk /* Counters Reset */
7576
7577/* Bit definition for Ethernet MMC Rx Interrupt Register */
7578#define ETH_MMCRIR_RXLPITRCIS_Pos (27U)
7579#define ETH_MMCRIR_RXLPITRCIS_Msk (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos)
7580#define ETH_MMCRIR_RXLPITRCIS ETH_MMCRIR_RXLPITRCIS_Msk /* MMC Receive LPI transition counter interrupt status */
7581#define ETH_MMCRIR_RXLPIUSCIS_Pos (26U)
7582#define ETH_MMCRIR_RXLPIUSCIS_Msk (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos)
7583#define ETH_MMCRIR_RXLPIUSCIS ETH_MMCRIR_RXLPIUSCIS_Msk /* MMC Receive LPI microsecond counter interrupt status */
7584#define ETH_MMCRIR_RXUCGPIS_Pos (17U)
7585#define ETH_MMCRIR_RXUCGPIS_Msk (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos)
7586#define ETH_MMCRIR_RXUCGPIS ETH_MMCRIR_RXUCGPIS_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Status */
7587#define ETH_MMCRIR_RXALGNERPIS_Pos (6U)
7588#define ETH_MMCRIR_RXALGNERPIS_Msk (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos)
7589#define ETH_MMCRIR_RXALGNERPIS ETH_MMCRIR_RXALGNERPIS_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Status */
7590#define ETH_MMCRIR_RXCRCERPIS_Pos (5U)
7591#define ETH_MMCRIR_RXCRCERPIS_Msk (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos)
7592#define ETH_MMCRIR_RXCRCERPIS ETH_MMCRIR_RXCRCERPIS_Msk /* MMC Receive CRC Error Packet Counter Interrupt Status */
7593
7594/* Bit definition for Ethernet MMC Tx Interrupt Register */
7595#define ETH_MMCTIR_TXLPITRCIS_Pos (27U)
7596#define ETH_MMCTIR_TXLPITRCIS_Msk (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos)
7597#define ETH_MMCTIR_TXLPITRCIS ETH_MMCTIR_TXLPITRCIS_Msk /* MMC Transmit LPI transition counter interrupt status */
7598#define ETH_MMCTIR_TXLPIUSCIS_Pos (26U)
7599#define ETH_MMCTIR_TXLPIUSCIS_Msk (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos)
7600#define ETH_MMCTIR_TXLPIUSCIS ETH_MMCTIR_TXLPIUSCIS_Msk /* MMC Transmit LPI microsecond counter interrupt status */
7601#define ETH_MMCTIR_TXGPKTIS_Pos (21U)
7602#define ETH_MMCTIR_TXGPKTIS_Msk (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos)
7603#define ETH_MMCTIR_TXGPKTIS ETH_MMCTIR_TXGPKTIS_Msk /* MMC Transmit Good Packet Counter Interrupt Status */
7604#define ETH_MMCTIR_TXMCOLGPIS_Pos (15U)
7605#define ETH_MMCTIR_TXMCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos)
7606#define ETH_MMCTIR_TXMCOLGPIS ETH_MMCTIR_TXMCOLGPIS_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
7607#define ETH_MMCTIR_TXSCOLGPIS_Pos (14U)
7608#define ETH_MMCTIR_TXSCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos)
7609#define ETH_MMCTIR_TXSCOLGPIS ETH_MMCTIR_TXSCOLGPIS_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
7610
7611/* Bit definition for Ethernet MMC Rx interrupt Mask register */
7612#define ETH_MMCRIMR_RXLPITRCIM_Pos (27U)
7613#define ETH_MMCRIMR_RXLPITRCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos)
7614#define ETH_MMCRIMR_RXLPITRCIM ETH_MMCRIMR_RXLPITRCIM_Msk /* MMC Receive LPI transition counter interrupt Mask */
7615#define ETH_MMCRIMR_RXLPIUSCIM_Pos (26U)
7616#define ETH_MMCRIMR_RXLPIUSCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos)
7617#define ETH_MMCRIMR_RXLPIUSCIM ETH_MMCRIMR_RXLPIUSCIM_Msk /* MMC Receive LPI microsecond counter interrupt Mask */
7618#define ETH_MMCRIMR_RXUCGPIM_Pos (17U)
7619#define ETH_MMCRIMR_RXUCGPIM_Msk (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos)
7620#define ETH_MMCRIMR_RXUCGPIM ETH_MMCRIMR_RXUCGPIM_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
7621#define ETH_MMCRIMR_RXALGNERPIM_Pos (6U)
7622#define ETH_MMCRIMR_RXALGNERPIM_Msk (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos)
7623#define ETH_MMCRIMR_RXALGNERPIM ETH_MMCRIMR_RXALGNERPIM_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
7624#define ETH_MMCRIMR_RXCRCERPIM_Pos (5U)
7625#define ETH_MMCRIMR_RXCRCERPIM_Msk (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos)
7626#define ETH_MMCRIMR_RXCRCERPIM ETH_MMCRIMR_RXCRCERPIM_Msk /* MMC Receive CRC Error Packet Counter Interrupt Mask */
7627
7628/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
7629#define ETH_MMCTIMR_TXLPITRCIM_Pos (27U)
7630#define ETH_MMCTIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos)
7631#define ETH_MMCTIMR_TXLPITRCIM ETH_MMCTIMR_TXLPITRCIM_Msk /* MMC Transmit LPI transition counter interrupt Mask*/
7632#define ETH_MMCTIMR_TXLPIUSCIM_Pos (26U)
7633#define ETH_MMCTIMR_TXLPIUSCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos)
7634#define ETH_MMCTIMR_TXLPIUSCIM ETH_MMCTIMR_TXLPIUSCIM_Msk /* MMC Transmit LPI microsecond counter interrupt Mask*/
7635#define ETH_MMCTIMR_TXGPKTIM_Pos (21U)
7636#define ETH_MMCTIMR_TXGPKTIM_Msk (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos)
7637#define ETH_MMCTIMR_TXGPKTIM ETH_MMCTIMR_TXGPKTIM_Msk /* MMC Transmit Good Packet Counter Interrupt Mask*/
7638#define ETH_MMCTIMR_TXMCOLGPIM_Pos (15U)
7639#define ETH_MMCTIMR_TXMCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos)
7640#define ETH_MMCTIMR_TXMCOLGPIM ETH_MMCTIMR_TXMCOLGPIM_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
7641#define ETH_MMCTIMR_TXSCOLGPIM_Pos (14U)
7642#define ETH_MMCTIMR_TXSCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos)
7643#define ETH_MMCTIMR_TXSCOLGPIM ETH_MMCTIMR_TXSCOLGPIM_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
7644
7645/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
7646#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos (0U)
7647#define ETH_MMCTSCGPR_TXSNGLCOLG_msk (0xFFFFFFFFUL << ETH_MMCTSCGPR_TXSNGLCOLG_Pos)
7648#define ETH_MMCTSCGPR_TXSNGLCOLG ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
7649
7650/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
7651#define ETH_MMCTMCGPR_TXMULTCOLG_Pos (0U)
7652#define ETH_MMCTMCGPR_TXMULTCOLG_msk (0xFFFFFFFFUL << ETH_MMCTMCGPR_TXMULTCOLG_Pos)
7653#define ETH_MMCTMCGPR_TXMULTCOLG ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
7654
7655/* Bit definition for Ethernet MMC Tx Packet Count Good Register */
7656#define ETH_MMCTPCGR_TXPKTG_Pos (0U)
7657#define ETH_MMCTPCGR_TXPKTG_msk (0xFFFFFFFFUL << ETH_MMCTPCGR_TXPKTG_Pos)
7658#define ETH_MMCTPCGR_TXPKTG ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
7659
7660/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
7661#define ETH_MMCRCRCEPR_RXCRCERR_Pos (0U)
7662#define ETH_MMCRCRCEPR_RXCRCERR_msk (0xFFFFFFFFUL << ETH_MMCRCRCEPR_RXCRCERR_Pos)
7663#define ETH_MMCRCRCEPR_RXCRCERR ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
7664
7665/* Bit definition for Ethernet MMC Rx alignment error packets register */
7666#define ETH_MMCRAEPR_RXALGNERR_Pos (0U)
7667#define ETH_MMCRAEPR_RXALGNERR_msk (0xFFFFFFFFUL << ETH_MMCRAEPR_RXALGNERR_Pos)
7668#define ETH_MMCRAEPR_RXALGNERR ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
7669
7670/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
7671#define ETH_MMCRUPGR_RXUCASTG_Pos (0U)
7672#define ETH_MMCRUPGR_RXUCASTG_msk (0xFFFFFFFFUL << ETH_MMCRUPGR_RXUCASTG_Pos)
7673#define ETH_MMCRUPGR_RXUCASTG ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
7674
7675/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
7676#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos (0U)
7677#define ETH_MMCTLPIMSTR_TXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCTLPIMSTR_TXLPIUSC_Pos)
7678#define ETH_MMCTLPIMSTR_TXLPIUSC ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
7679
7680/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
7681#define ETH_MMCTLPITCR_TXLPITRC_Pos (0U)
7682#define ETH_MMCTLPITCR_TXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCTLPITCR_TXLPITRC_Pos)
7683#define ETH_MMCTLPITCR_TXLPITRC ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
7684
7685/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
7686#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos (0U)
7687#define ETH_MMCRLPIMSTR_RXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCRLPIMSTR_RXLPIUSC_Pos)
7688#define ETH_MMCRLPIMSTR_RXLPIUSC ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
7689
7690/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
7691#define ETH_MMCRLPITCR_RXLPITRC_Pos (0U)
7692#define ETH_MMCRLPITCR_RXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCRLPITCR_RXLPITRC_Pos)
7693#define ETH_MMCRLPITCR_RXLPITRC ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
7694
7695/* Bit definition for Ethernet MAC L3 L4 Control Register */
7696#define ETH_MACL3L4CR_L4DPIM_Pos (21U)
7697#define ETH_MACL3L4CR_L4DPIM_Msk (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos)
7698#define ETH_MACL3L4CR_L4DPIM ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
7699#define ETH_MACL3L4CR_L4DPM_Pos (20U)
7700#define ETH_MACL3L4CR_L4DPM_Msk (0x1UL << ETH_MACL3L4CR_L4DPM_Pos)
7701#define ETH_MACL3L4CR_L4DPM ETH_MACL3L4CR_L4DPM_Msk /* Layer 4 Destination Port Match Enable */
7702#define ETH_MACL3L4CR_L4SPIM_Pos (19U)
7703#define ETH_MACL3L4CR_L4SPIM_Msk (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos)
7704#define ETH_MACL3L4CR_L4SPIM ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
7705#define ETH_MACL3L4CR_L4SPM_Pos (18U)
7706#define ETH_MACL3L4CR_L4SPM_Msk (0x1UL << ETH_MACL3L4CR_L4SPM_Pos)
7707#define ETH_MACL3L4CR_L4SPM ETH_MACL3L4CR_L4SPM_Msk /* Layer 4 Source Port Match Enable */
7708#define ETH_MACL3L4CR_L4PEN_Pos (16U)
7709#define ETH_MACL3L4CR_L4PEN_Msk (0x1UL << ETH_MACL3L4CR_L4PEN_Pos)
7710#define ETH_MACL3L4CR_L4PEN ETH_MACL3L4CR_L4PEN_Msk /* Layer 4 Protocol Enable */
7711#define ETH_MACL3L4CR_L3HDBM_Pos (11U)
7712#define ETH_MACL3L4CR_L3HDBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos)
7713#define ETH_MACL3L4CR_L3HDBM ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
7714#define ETH_MACL3L4CR_L3HSBM_Pos (6U)
7715#define ETH_MACL3L4CR_L3HSBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos)
7716#define ETH_MACL3L4CR_L3HSBM ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
7717#define ETH_MACL3L4CR_L3DAIM_Pos (5U)
7718#define ETH_MACL3L4CR_L3DAIM_Msk (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos)
7719#define ETH_MACL3L4CR_L3DAIM ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
7720#define ETH_MACL3L4CR_L3DAM_Pos (4U)
7721#define ETH_MACL3L4CR_L3DAM_Msk (0x1UL << ETH_MACL3L4CR_L3DAM_Pos)
7722#define ETH_MACL3L4CR_L3DAM ETH_MACL3L4CR_L3DAM_Msk /* Layer 3 IP DA Match Enable */
7723#define ETH_MACL3L4CR_L3SAIM_Pos (3U)
7724#define ETH_MACL3L4CR_L3SAIM_Msk (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos)
7725#define ETH_MACL3L4CR_L3SAIM ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
7726#define ETH_MACL3L4CR_L3SAM_Pos (2U)
7727#define ETH_MACL3L4CR_L3SAM_Msk (0x1UL << ETH_MACL3L4CR_L3SAM_Pos)
7728#define ETH_MACL3L4CR_L3SAM ETH_MACL3L4CR_L3SAM_Msk /* Layer 3 IP SA Match Enable*/
7729#define ETH_MACL3L4CR_L3PEN_Pos (0U)
7730#define ETH_MACL3L4CR_L3PEN_Msk (0x1UL << ETH_MACL3L4CR_L3PEN_Pos)
7731#define ETH_MACL3L4CR_L3PEN ETH_MACL3L4CR_L3PEN_Msk /* Layer 3 Protocol Enable */
7732
7733/* Bit definition for Ethernet MAC L4 Address Register */
7734#define ETH_MACL4AR_L4DP_Pos (16U)
7735#define ETH_MACL4AR_L4DP_Msk (0xFFFFUL << ETH_MACL4AR_L4DP_Pos)
7736#define ETH_MACL4AR_L4DP ETH_MACL4AR_L4DP_Msk /* Layer 4 Destination Port Number Field */
7737#define ETH_MACL4AR_L4SP_Pos (0U)
7738#define ETH_MACL4AR_L4SP_Msk (0xFFFFUL << ETH_MACL4AR_L4SP_Pos)
7739#define ETH_MACL4AR_L4SP ETH_MACL4AR_L4SP_Msk /* Layer 4 Source Port Number Field */
7740
7741/* Bit definition for Ethernet MAC L3 Address0 Register */
7742#define ETH_MACL3A0R_L3A0_Pos (0U)
7743#define ETH_MACL3A0R_L3A0_Msk (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos)
7744#define ETH_MACL3A0R_L3A0 ETH_MACL3A0R_L3A0_Msk /* Layer 3 Address 0 Field */
7745
7746/* Bit definition for Ethernet MAC L4 Address1 Register */
7747#define ETH_MACL3A1R_L3A1_Pos (0U)
7748#define ETH_MACL3A1R_L3A1_Msk (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos)
7749#define ETH_MACL3A1R_L3A1 ETH_MACL3A1R_L3A1_Msk /* Layer 3 Address 1 Field */
7750
7751/* Bit definition for Ethernet MAC L4 Address2 Register */
7752#define ETH_MACL3A2R_L3A2_Pos (0U)
7753#define ETH_MACL3A2R_L3A2_Msk (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos)
7754#define ETH_MACL3A2R_L3A2 ETH_MACL3A2R_L3A2_Msk /* Layer 3 Address 2 Field */
7755
7756/* Bit definition for Ethernet MAC L4 Address3 Register */
7757#define ETH_MACL3A3R_L3A3_Pos (0U)
7758#define ETH_MACL3A3R_L3A3_Msk (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos)
7759#define ETH_MACL3A3R_L3A3 ETH_MACL3A3R_L3A3_Msk /* Layer 3 Address 3 Field */
7760
7761/* Bit definition for Ethernet MAC Timestamp Control Register */
7762#define ETH_MACTSCR_TXTSSTSM_Pos (24U)
7763#define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos)
7764#define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /* Transmit Timestamp Status Mode */
7765#define ETH_MACTSCR_CSC_Pos (19U)
7766#define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos)
7767#define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
7768#define ETH_MACTSCR_TSENMACADDR_Pos (18U)
7769#define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos)
7770#define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /* Enable MAC Address for PTP Packet Filtering */
7771#define ETH_MACTSCR_SNAPTYPSEL_Pos (16U)
7772#define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos)
7773#define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /* Select PTP packets for Taking Snapshots */
7774#define ETH_MACTSCR_TSMSTRENA_Pos (15U)
7775#define ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos)
7776#define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /* Enable Snapshot for Messages Relevant to Master */
7777#define ETH_MACTSCR_TSEVNTENA_Pos (14U)
7778#define ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos)
7779#define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /* Enable Timestamp Snapshot for Event Messages */
7780#define ETH_MACTSCR_TSIPV4ENA_Pos (13U)
7781#define ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos)
7782#define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
7783#define ETH_MACTSCR_TSIPV6ENA_Pos (12U)
7784#define ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos)
7785#define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
7786#define ETH_MACTSCR_TSIPENA_Pos (11U)
7787#define ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos)
7788#define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /* Enable Processing of PTP over Ethernet Packets */
7789#define ETH_MACTSCR_TSVER2ENA_Pos (10U)
7790#define ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos)
7791#define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /* Enable PTP Packet Processing for Version 2 Format */
7792#define ETH_MACTSCR_TSCTRLSSR_Pos (9U)
7793#define ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos)
7794#define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /* Timestamp Digital or Binary Rollover Control */
7795#define ETH_MACTSCR_TSENALL_Pos (8U)
7796#define ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos)
7797#define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /* Enable Timestamp for All Packets */
7798#define ETH_MACTSCR_TSADDREG_Pos (5U)
7799#define ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos)
7800#define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /* Update Addend Register */
7801#define ETH_MACTSCR_TSUPDT_Pos (3U)
7802#define ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos)
7803#define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /* Update Timestamp */
7804#define ETH_MACTSCR_TSINIT_Pos (2U)
7805#define ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos)
7806#define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /* Initialize Timestamp */
7807#define ETH_MACTSCR_TSCFUPDT_Pos (1U)
7808#define ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos)
7809#define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /* Fine or Coarse Timestamp Update*/
7810#define ETH_MACTSCR_TSENA_Pos (0U)
7811#define ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos)
7812#define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /* Enable Timestamp */
7813
7814/* Bit definition for Ethernet MAC Sub-second Increment Register */
7815#define ETH_MACMACSSIR_SSINC_Pos (16U)
7816#define ETH_MACMACSSIR_SSINC_Msk (0xFFUL << ETH_MACMACSSIR_SSINC_Pos)
7817#define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Increment Value */
7818#define ETH_MACMACSSIR_SNSINC_Pos (8U)
7819#define ETH_MACMACSSIR_SNSINC_Msk (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos)
7820#define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond Increment Value */
7821
7822/* Bit definition for Ethernet MAC System Time Seconds Register */
7823#define ETH_MACSTSR_TSS_Pos (0U)
7824#define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos)
7825#define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /* Timestamp Second */
7826
7827/* Bit definition for Ethernet MAC System Time Nanoseconds Register */
7828#define ETH_MACSTNR_TSSS_Pos (0U)
7829#define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos)
7830#define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-seconds */
7831
7832/* Bit definition for Ethernet MAC System Time Seconds Update Register */
7833#define ETH_MACSTSUR_TSS_Pos (0U)
7834#define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos)
7835#define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /* Timestamp Seconds */
7836
7837/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
7838#define ETH_MACSTNUR_ADDSUB_Pos (31U)
7839#define ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos)
7840#define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /* Add or Subtract Time */
7841#define ETH_MACSTNUR_TSSS_Pos (0U)
7842#define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos)
7843#define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-seconds */
7844
7845/* Bit definition for Ethernet MAC Timestamp Addend Register */
7846#define ETH_MACTSAR_TSAR_Pos (0U)
7847#define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos)
7848#define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /* Timestamp Addend Register */
7849
7850/* Bit definition for Ethernet MAC Timestamp Status Register */
7851#define ETH_MACTSSR_ATSNS_Pos (25U)
7852#define ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos)
7853#define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /* Number of Auxiliary Timestamp Snapshots */
7854#define ETH_MACTSSR_ATSSTM_Pos (24U)
7855#define ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos)
7856#define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /* Auxiliary Timestamp Snapshot Trigger Missed */
7857#define ETH_MACTSSR_ATSSTN_Pos (16U)
7858#define ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos)
7859#define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /* Auxiliary Timestamp Snapshot Trigger Identifier */
7860#define ETH_MACTSSR_TXTSSIS_Pos (15U)
7861#define ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos)
7862#define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /* Tx Timestamp Status Interrupt Status */
7863#define ETH_MACTSSR_TSTRGTERR0_Pos (3U)
7864#define ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos)
7865#define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /* Timestamp Target Time Error */
7866#define ETH_MACTSSR_AUXTSTRIG_Pos (2U)
7867#define ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos)
7868#define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /* Auxiliary Timestamp Trigger Snapshot*/
7869#define ETH_MACTSSR_TSTARGT0_Pos (1U)
7870#define ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos)
7871#define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /* Timestamp Target Time Reached */
7872#define ETH_MACTSSR_TSSOVF_Pos (0U)
7873#define ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos)
7874#define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /* Timestamp Seconds Overflow */
7875
7876/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
7877#define ETH_MACTTSSNR_TXTSSMIS_Pos (31U)
7878#define ETH_MACTTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos)
7879#define ETH_MACTTSSNR_TXTSSMIS ETH_MACTTSSNR_TXTSSMIS_Msk /* Transmit Timestamp Status Missed */
7880#define ETH_MACTTSSNR_TXTSSLO_Pos (0U)
7881#define ETH_MACTTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos)
7882#define ETH_MACTTSSNR_TXTSSLO ETH_MACTTSSNR_TXTSSLO_Msk /* Transmit Timestamp Status Low */
7883
7884/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
7885#define ETH_MACTTSSSR_TXTSSHI_Pos (0U)
7886#define ETH_MACTTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos)
7887#define ETH_MACTTSSSR_TXTSSHI ETH_MACTTSSSR_TXTSSHI_Msk /* Transmit Timestamp Status High */
7888
7889/* Bit definition for Ethernet MAC Auxiliary Control Register*/
7890#define ETH_MACACR_ATSEN3_Pos (7U)
7891#define ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos)
7892#define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /* Auxiliary Snapshot 3 Enable */
7893#define ETH_MACACR_ATSEN2_Pos (6U)
7894#define ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos)
7895#define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /* Auxiliary Snapshot 2 Enable */
7896#define ETH_MACACR_ATSEN1_Pos (5U)
7897#define ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos)
7898#define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /* Auxiliary Snapshot 1 Enable */
7899#define ETH_MACACR_ATSEN0_Pos (4U)
7900#define ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos)
7901#define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /* Auxiliary Snapshot 0 Enable */
7902#define ETH_MACACR_ATSFC_Pos (0U)
7903#define ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos)
7904#define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /* Auxiliary Snapshot FIFO Clear */
7905
7906/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
7907#define ETH_MACATSNR_AUXTSLO_Pos (0U)
7908#define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos)
7909#define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /* Auxiliary Timestamp */
7910
7911/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
7912#define ETH_MACATSSR_AUXTSHI_Pos (0U)
7913#define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos)
7914#define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /* Auxiliary Timestamp */
7915
7916/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
7917#define ETH_MACTSIACR_OSTIAC_Pos (0U)
7918#define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos)
7919#define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timestamp Ingress Asymmetry Correction */
7920
7921/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
7922#define ETH_MACTSEACR_OSTEAC_Pos (0U)
7923#define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos)
7924#define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timestamp Egress Asymmetry Correction */
7925
7926/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
7927#define ETH_MACTSICNR_TSIC_Pos (0U)
7928#define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos)
7929#define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /* Timestamp Ingress Correction */
7930
7931/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
7932#define ETH_MACTSECNR_TSEC_Pos (0U)
7933#define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos)
7934#define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /* Timestamp Egress Correction */
7935
7936/* Bit definition for Ethernet MAC PPS Control Register */
7937#define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)
7938#define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos)
7939#define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /* Target Time Register Mode for PPS Output */
7940#define ETH_MACPPSCR_PPSEN0_Pos (4U)
7941#define ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos)
7942#define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /* Flexible PPS Output Mode Enable */
7943#define ETH_MACPPSCR_PPSCTRL_Pos (0U)
7944#define ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos)
7945#define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /* PPS Output Frequency Control */
7946
7947/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
7948#define ETH_MACPPSTTSR_TSTRH0_Pos (0U)
7949#define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos)
7950#define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /* PPS Target Time Seconds Register */
7951
7952/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
7953#define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U)
7954#define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos)
7955#define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /* PPS Target Time Register Busy */
7956#define ETH_MACPPSTTNR_TTSL0_Pos (0U)
7957#define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos)
7958#define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /* Target Time Low for PPS Register */
7959
7960/* Bit definition for Ethernet MAC PPS Interval Register */
7961#define ETH_MACPPSIR_PPSINT0_Pos (0U)
7962#define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos)
7963#define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /* PPS Output Signal Interval */
7964
7965/* Bit definition for Ethernet MAC PPS Width Register */
7966#define ETH_MACPPSWR_PPSWIDTH0_Pos (0U)
7967#define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos)
7968#define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /* PPS Output Signal Width */
7969
7970/* Bit definition for Ethernet MAC PTP Offload Control Register */
7971#define ETH_MACPOCR_DN_Pos (8U)
7972#define ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos)
7973#define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /* Domain Number */
7974#define ETH_MACPOCR_DRRDIS_Pos (6U)
7975#define ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos)
7976#define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /* Disable PTO Delay Request/Response response generation */
7977#define ETH_MACPOCR_APDREQTRIG_Pos (5U)
7978#define ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos)
7979#define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /* Automatic PTP Pdelay_Req message Trigger */
7980#define ETH_MACPOCR_ASYNCTRIG_Pos (4U)
7981#define ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos)
7982#define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /* Automatic PTP SYNC message Trigger */
7983#define ETH_MACPOCR_APDREQEN_Pos (2U)
7984#define ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos)
7985#define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /* Automatic PTP Pdelay_Req message Enable */
7986#define ETH_MACPOCR_ASYNCEN_Pos (1U)
7987#define ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos)
7988#define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /* Automatic PTP SYNC message Enable */
7989#define ETH_MACPOCR_PTOEN_Pos (0U)
7990#define ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos)
7991#define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /* PTP Offload Enable */
7992
7993/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
7994#define ETH_MACSPI0R_SPI0_Pos (0U)
7995#define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos)
7996#define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /* Source Port Identity 0 */
7997
7998/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
7999#define ETH_MACSPI1R_SPI1_Pos (0U)
8000#define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos)
8001#define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /* Source Port Identity 1 */
8002
8003/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
8004#define ETH_MACSPI2R_SPI2_Pos (0U)
8005#define ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos)
8006#define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /* Source Port Identity 2 */
8007
8008/* Bit definition for Ethernet MAC Log Message Interval Register */
8009#define ETH_MACLMIR_LMPDRI_Pos (24U)
8010#define ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos)
8011#define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /* Log Min Pdelay_Req Interval */
8012#define ETH_MACLMIR_DRSYNCR_Pos (8U)
8013#define ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos)
8014#define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /* Delay_Req to SYNC Ratio */
8015#define ETH_MACLMIR_LSI_Pos (0U)
8016#define ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos)
8017#define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /* Log Sync Interval */
8018
8019/* Bit definition for Ethernet MTL Operation Mode Register */
8020#define ETH_MTLOMR_CNTCLR_Pos (9U)
8021#define ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos)
8022#define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /* Counters Reset */
8023#define ETH_MTLOMR_CNTPRST_Pos (8U)
8024#define ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos)
8025#define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /* Counters Preset */
8026#define ETH_MTLOMR_DTXSTS_Pos (1U)
8027#define ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos)
8028#define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /* Drop Transmit Status */
8029
8030/* Bit definition for Ethernet MTL Interrupt Status Register */
8031#define ETH_MTLISR_MACIS_Pos (16U)
8032#define ETH_MTLISR_MACIS_Msk (0x1UL << ETH_MTLISR_MACIS_Pos)
8033#define ETH_MTLISR_MACIS ETH_MTLISR_MACIS_Msk /* MAC Interrupt Status */
8034#define ETH_MTLISR_QIS_Pos (0U)
8035#define ETH_MTLISR_QIS_Msk (0x1UL << ETH_MTLISR_QIS_Pos)
8036#define ETH_MTLISR_QIS ETH_MTLISR_QIS_Msk /* Queue Interrupt status */
8037
8038/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
8039#define ETH_MTLTQOMR_TTC_Pos (4U)
8040#define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos)
8041#define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
8042#define ETH_MTLTQOMR_TTC_32BITS (0U) /* 32 bits Threshold */
8043#define ETH_MTLTQOMR_TTC_64BITS (0x00000010U) /* 64 bits Threshold */
8044#define ETH_MTLTQOMR_TTC_96BITS (0x00000020U) /* 96 bits Threshold */
8045#define ETH_MTLTQOMR_TTC_128BITS (0x00000030U) /* 128 bits Threshold */
8046#define ETH_MTLTQOMR_TTC_192BITS (0x00000040U) /* 192 bits Threshold */
8047#define ETH_MTLTQOMR_TTC_256BITS (0x00000050U) /* 256 bits Threshold */
8048#define ETH_MTLTQOMR_TTC_384BITS (0x00000060U) /* 384 bits Threshold */
8049#define ETH_MTLTQOMR_TTC_512BITS (0x00000070U) /* 512 bits Threshold */
8050#define ETH_MTLTQOMR_TSF_Pos (1U)
8051#define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos)
8052#define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
8053#define ETH_MTLTQOMR_FTQ_Pos (0U)
8054#define ETH_MTLTQOMR_FTQ_Msk (0x1UL << ETH_MTLTQOMR_FTQ_Pos)
8055#define ETH_MTLTQOMR_FTQ ETH_MTLTQOMR_FTQ_Msk /* Flush Transmit Queue */
8056
8057/* Bit definition for Ethernet MTL Tx Queue Underflow Register */
8058#define ETH_MTLTQUR_UFCNTOVF_Pos (11U)
8059#define ETH_MTLTQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos)
8060#define ETH_MTLTQUR_UFCNTOVF ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
8061#define ETH_MTLTQUR_UFPKTCNT_Pos (0U)
8062#define ETH_MTLTQUR_UFPKTCNT_Msk (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos)
8063#define ETH_MTLTQUR_UFPKTCNT ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
8064
8065/* Bit definition for Ethernet MTL Tx Queue Debug Register */
8066#define ETH_MTLTQDR_STXSTSF_Pos (20U)
8067#define ETH_MTLTQDR_STXSTSF_Msk (0x7UL << ETH_MTLTQDR_STXSTSF_Pos)
8068#define ETH_MTLTQDR_STXSTSF ETH_MTLTQDR_STXSTSF_Msk /* Number of Status Words in the Tx Status FIFO of Queue */
8069#define ETH_MTLTQDR_PTXQ_Pos (16U)
8070#define ETH_MTLTQDR_PTXQ_Msk (0x7UL << ETH_MTLTQDR_PTXQ_Pos)
8071#define ETH_MTLTQDR_PTXQ ETH_MTLTQDR_PTXQ_Msk /* Number of Packets in the Transmit Queue */
8072#define ETH_MTLTQDR_TXSTSFSTS_Pos (5U)
8073#define ETH_MTLTQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos)
8074#define ETH_MTLTQDR_TXSTSFSTS ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
8075#define ETH_MTLTQDR_TXQSTS_Pos (4U)
8076#define ETH_MTLTQDR_TXQSTS_Msk (0x1UL << ETH_MTLTQDR_TXQSTS_Pos)
8077#define ETH_MTLTQDR_TXQSTS ETH_MTLTQDR_TXQSTS_Msk /* MTL Tx Queue Not Empty Status */
8078#define ETH_MTLTQDR_TWCSTS_Pos (3U)
8079#define ETH_MTLTQDR_TWCSTS_Msk (0x1UL << ETH_MTLTQDR_TWCSTS_Pos)
8080#define ETH_MTLTQDR_TWCSTS ETH_MTLTQDR_TWCSTS_Msk /* MTL Tx Queue Write Controller Status */
8081#define ETH_MTLTQDR_TRCSTS_Pos (1U)
8082#define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos)
8083#define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
8084#define ETH_MTLTQDR_TRCSTS_IDLE (0U) /* Idle state */
8085#define ETH_MTLTQDR_TRCSTS_READ (0x00000002U) /* Read state (transferring data to the MAC transmitter) */
8086#define ETH_MTLTQDR_TRCSTS_WAITING (0x00000004U) /* Waiting for pending Tx Status from the MAC transmitter */
8087#define ETH_MTLTQDR_TRCSTS_FLUSHING (0x00000006U) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
8088#define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
8089#define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos)
8090#define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
8091
8092/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
8093#define ETH_MTLQICSR_RXOIE_Pos (24U)
8094#define ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos)
8095#define ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /* Receive Queue Overflow Interrupt Enable */
8096#define ETH_MTLQICSR_RXOVFIS_Pos (16U)
8097#define ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos)
8098#define ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
8099#define ETH_MTLQICSR_TXUIE_Pos (8U)
8100#define ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos)
8101#define ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /* Transmit Queue Underflow Interrupt Enable */
8102#define ETH_MTLQICSR_TXUNFIS_Pos (0U)
8103#define ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos)
8104#define ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
8105
8106/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
8107#define ETH_MTLRQOMR_RQS_Pos (20U)
8108#define ETH_MTLRQOMR_RQS_Msk (0x7UL << ETH_MTLRQOMR_RQS_Pos)
8109#define ETH_MTLRQOMR_RQS ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
8110#define ETH_MTLRQOMR_RFD_Pos (14U)
8111#define ETH_MTLRQOMR_RFD_Msk (0x7UL << ETH_MTLRQOMR_RFD_Pos)
8112#define ETH_MTLRQOMR_RFD ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
8113#define ETH_MTLRQOMR_RFA_Pos (8U)
8114#define ETH_MTLRQOMR_RFA_Msk (0x7UL << ETH_MTLRQOMR_RFA_Pos)
8115#define ETH_MTLRQOMR_RFA ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
8116#define ETH_MTLRQOMR_EHFC_Pos (7U)
8117#define ETH_MTLRQOMR_EHFC_Msk (0x1UL << ETH_MTLRQOMR_EHFC_Pos)
8118#define ETH_MTLRQOMR_EHFC ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
8119#define ETH_MTLRQOMR_DISTCPEF_Pos (6U)
8120#define ETH_MTLRQOMR_DISTCPEF_Msk (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos)
8121#define ETH_MTLRQOMR_DISTCPEF ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
8122#define ETH_MTLRQOMR_RSF_Pos (5U)
8123#define ETH_MTLRQOMR_RSF_Msk (0x1UL << ETH_MTLRQOMR_RSF_Pos)
8124#define ETH_MTLRQOMR_RSF ETH_MTLRQOMR_RSF_Msk /* Receive Queue Store and Forward */
8125#define ETH_MTLRQOMR_FEP_Pos (4U)
8126#define ETH_MTLRQOMR_FEP_Msk (0x1UL << ETH_MTLRQOMR_FEP_Pos)
8127#define ETH_MTLRQOMR_FEP ETH_MTLRQOMR_FEP_Msk /* Forward Error Packets */
8128#define ETH_MTLRQOMR_FUP_Pos (3U)
8129#define ETH_MTLRQOMR_FUP_Msk (0x1UL << ETH_MTLRQOMR_FUP_Pos)
8130#define ETH_MTLRQOMR_FUP ETH_MTLRQOMR_FUP_Msk /* Forward Undersized Good Packets */
8131#define ETH_MTLRQOMR_RTC_Pos (0U)
8132#define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos)
8133#define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
8134#define ETH_MTLRQOMR_RTC_64BITS (0U) /* 64 bits Threshold */
8135#define ETH_MTLRQOMR_RTC_32BITS (0x00000001U) /* 32 bits Threshold */
8136#define ETH_MTLRQOMR_RTC_96BITS (0x00000002U) /* 96 bits Threshold */
8137#define ETH_MTLRQOMR_RTC_128BITS (0x00000003U) /* 128 bits Threshold */
8138
8139/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
8140#define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
8141#define ETH_MTLRQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos)
8142#define ETH_MTLRQMPOCR_MISCNTOVF ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
8143#define ETH_MTLRQMPOCR_MISPKTCNT_Pos (16U)
8144#define ETH_MTLRQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos)
8145#define ETH_MTLRQMPOCR_MISPKTCNT ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
8146#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos (11U)
8147#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos)
8148#define ETH_MTLRQMPOCR_OVFCNTOVF ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
8149#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos (0U)
8150#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos)
8151#define ETH_MTLRQMPOCR_OVFPKTCNT ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
8152
8153/* Bit definition for Ethernet MTL Rx Queue Debug Register */
8154#define ETH_MTLRQDR_PRXQ_Pos (16U)
8155#define ETH_MTLRQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos)
8156#define ETH_MTLRQDR_PRXQ ETH_MTLRQDR_PRXQ_Msk /* Number of Packets in Receive Queue */
8157#define ETH_MTLRQDR_RXQSTS_Pos (4U)
8158#define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos)
8159#define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
8160#define ETH_MTLRQDR_RXQSTS_EMPTY (0U) /* Rx Queue empty */
8161#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
8162#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos)
8163#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
8164#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos (5U)
8165#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos)
8166#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
8167#define ETH_MTLRQDR_RXQSTS_FULL_Pos (4U)
8168#define ETH_MTLRQDR_RXQSTS_FULL_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos)
8169#define ETH_MTLRQDR_RXQSTS_FULL ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
8170#define ETH_MTLRQDR_RRCSTS_Pos (1U)
8171#define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos)
8172#define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
8173#define ETH_MTLRQDR_RRCSTS_IDLE (0U) /* Idle state */
8174#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
8175#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos)
8176#define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
8177#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos (2U)
8178#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos)
8179#define ETH_MTLRQDR_RRCSTS_READINGSTATUS ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
8180#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos (1U)
8181#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos)
8182#define ETH_MTLRQDR_RRCSTS_FLUSHING ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
8183#define ETH_MTLRQDR_RWCSTS_Pos (0U)
8184#define ETH_MTLRQDR_RWCSTS_Msk (0x1UL << ETH_MTLRQDR_RWCSTS_Pos)
8185#define ETH_MTLRQDR_RWCSTS ETH_MTLRQDR_RWCSTS_Msk /* MTL Rx Queue Write Controller Active Status */
8186
8187/* Bit definition for Ethernet MTL Rx Queue Control Register */
8188#define ETH_MTLRQCR_RQPA_Pos (3U)
8189#define ETH_MTLRQCR_RQPA_Msk (0x1UL << ETH_MTLRQCR_RQPA_Pos)
8190#define ETH_MTLRQCR_RQPA ETH_MTLRQCR_RQPA_Msk /* Receive Queue Packet Arbitration */
8191#define ETH_MTLRQCR_RQW_Pos (0U)
8192#define ETH_MTLRQCR_RQW_Msk (0x7UL << ETH_MTLRQCR_RQW_Pos)
8193#define ETH_MTLRQCR_RQW ETH_MTLRQCR_RQW_Msk /* Receive Queue Weight */
8194
8195/* Bit definition for Ethernet DMA Mode Register */
8196#define ETH_DMAMR_INTM_Pos (16U)
8197#define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos)
8198#define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /* This field defines the interrupt mode */
8199#define ETH_DMAMR_INTM_0 (0x0UL << ETH_DMAMR_INTM_Pos)
8200#define ETH_DMAMR_INTM_1 (0x1UL << ETH_DMAMR_INTM_Pos)
8201#define ETH_DMAMR_INTM_2 (0x2UL << ETH_DMAMR_INTM_Pos)
8202#define ETH_DMAMR_PR_Pos (12U)
8203#define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos)
8204#define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
8205#define ETH_DMAMR_PR_1_1 (0U) /* The priority ratio is 1:1 */
8206#define ETH_DMAMR_PR_2_1 (0x00001000U) /* The priority ratio is 2:1 */
8207#define ETH_DMAMR_PR_3_1 (0x00002000U) /* The priority ratio is 3:1 */
8208#define ETH_DMAMR_PR_4_1 (0x00003000U) /* The priority ratio is 4:1 */
8209#define ETH_DMAMR_PR_5_1 (0x00004000U) /* The priority ratio is 5:1 */
8210#define ETH_DMAMR_PR_6_1 (0x00005000U) /* The priority ratio is 6:1 */
8211#define ETH_DMAMR_PR_7_1 (0x00006000U) /* The priority ratio is 7:1 */
8212#define ETH_DMAMR_PR_8_1 (0x00007000U) /* The priority ratio is 8:1 */
8213#define ETH_DMAMR_TXPR_Pos (11U)
8214#define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos)
8215#define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
8216#define ETH_DMAMR_DA_Pos (1U)
8217#define ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos)
8218#define ETH_DMAMR_DA ETH_DMAMR_DA_Msk /* DMA Tx or Rx Arbitration Scheme */
8219#define ETH_DMAMR_SWR_Pos (0U)
8220#define ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos)
8221#define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /* Software Reset */
8222
8223/* Bit definition for Ethernet DMA SysBus Mode Register */
8224#define ETH_DMASBMR_RB_Pos (15U)
8225#define ETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos)
8226#define ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /* Rebuild INCRx Burst */
8227#define ETH_DMASBMR_MB_Pos (14U)
8228#define ETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos)
8229#define ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /* Mixed Burst */
8230#define ETH_DMASBMR_AAL_Pos (12U)
8231#define ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos)
8232#define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned Beats */
8233#define ETH_DMASBMR_FB_Pos (0U)
8234#define ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos)
8235#define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /* Fixed Burst Length */
8236
8237/* Bit definition for Ethernet DMA Interrupt Status Register */
8238#define ETH_DMAISR_MACIS_Pos (17U)
8239#define ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos)
8240#define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /* MAC Interrupt Status */
8241#define ETH_DMAISR_MTLIS_Pos (16U)
8242#define ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos)
8243#define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /* MAC Interrupt Status */
8244#define ETH_DMAISR_DMACIS_Pos (0U)
8245#define ETH_DMAISR_DMACIS_Msk (0x1UL << ETH_DMAISR_DMACIS_Pos)
8246#define ETH_DMAISR_DMACIS ETH_DMAISR_DMACIS_Msk /* DMA Channel Interrupt Status */
8247
8248/* Bit definition for Ethernet DMA Debug Status Register */
8249#define ETH_DMADSR_TPS_Pos (12U)
8250#define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos)
8251#define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
8252#define ETH_DMADSR_TPS_STOPPED (0U) /* Stopped (Reset or Stop Transmit Command issued) */
8253#define ETH_DMADSR_TPS_FETCHING_Pos (12U)
8254#define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos)
8255#define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
8256#define ETH_DMADSR_TPS_WAITING_Pos (13U)
8257#define ETH_DMADSR_TPS_WAITING_Msk (0x1UL << ETH_DMADSR_TPS_WAITING_Pos)
8258#define ETH_DMADSR_TPS_WAITING ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
8259#define ETH_DMADSR_TPS_READING_Pos (12U)
8260#define ETH_DMADSR_TPS_READING_Msk (0x3UL << ETH_DMADSR_TPS_READING_Pos)
8261#define ETH_DMADSR_TPS_READING ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
8262#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos (14U)
8263#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos)
8264#define ETH_DMADSR_TPS_TIMESTAMP_WR ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8265#define ETH_DMADSR_TPS_SUSPENDED_Pos (13U)
8266#define ETH_DMADSR_TPS_SUSPENDED_Msk (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos)
8267#define ETH_DMADSR_TPS_SUSPENDED ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
8268#define ETH_DMADSR_TPS_CLOSING_Pos (12U)
8269#define ETH_DMADSR_TPS_CLOSING_Msk (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos)
8270#define ETH_DMADSR_TPS_CLOSING ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
8271#define ETH_DMADSR_RPS_Pos (8U)
8272#define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos)
8273#define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
8274#define ETH_DMADSR_RPS_STOPPED (0U) /* Stopped (Reset or Stop Receive Command issued) */
8275#define ETH_DMADSR_RPS_FETCHING_Pos (12U)
8276#define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos)
8277#define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
8278#define ETH_DMADSR_RPS_WAITING_Pos (12U)
8279#define ETH_DMADSR_RPS_WAITING_Msk (0x3UL << ETH_DMADSR_RPS_WAITING_Pos)
8280#define ETH_DMADSR_RPS_WAITING ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
8281#define ETH_DMADSR_RPS_SUSPENDED_Pos (14U)
8282#define ETH_DMADSR_RPS_SUSPENDED_Msk (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos)
8283#define ETH_DMADSR_RPS_SUSPENDED ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
8284#define ETH_DMADSR_RPS_CLOSING_Pos (12U)
8285#define ETH_DMADSR_RPS_CLOSING_Msk (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos)
8286#define ETH_DMADSR_RPS_CLOSING ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
8287#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos (13U)
8288#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos)
8289#define ETH_DMADSR_RPS_TIMESTAMP_WR ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8290#define ETH_DMADSR_RPS_TRANSFERRING_Pos (12U)
8291#define ETH_DMADSR_RPS_TRANSFERRING_Msk (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos)
8292#define ETH_DMADSR_RPS_TRANSFERRING ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
8293
8294/* Bit definition for Ethernet DMA Channel Control Register */
8295#define ETH_DMACCR_DSL_Pos (18U)
8296#define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos)
8297#define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
8298#define ETH_DMACCR_DSL_0BIT (0U)
8299#define ETH_DMACCR_DSL_32BIT (0x00040000U)
8300#define ETH_DMACCR_DSL_64BIT (0x00080000U)
8301#define ETH_DMACCR_DSL_128BIT (0x00100000U)
8302#define ETH_DMACCR_8PBL (0x00010000U) /* 8xPBL mode */
8303#define ETH_DMACCR_MSS_Pos (0U)
8304#define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos)
8305#define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
8306
8307/* Bit definition for Ethernet DMA Channel Tx Control Register */
8308#define ETH_DMACTCR_TPBL_Pos (16U)
8309#define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos)
8310#define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
8311#define ETH_DMACTCR_TPBL_1PBL (0x00010000U) /* Transmit Programmable Burst Length 1 */
8312#define ETH_DMACTCR_TPBL_2PBL (0x00020000U) /* Transmit Programmable Burst Length 2 */
8313#define ETH_DMACTCR_TPBL_4PBL (0x00040000U) /* Transmit Programmable Burst Length 4 */
8314#define ETH_DMACTCR_TPBL_8PBL (0x00080000U) /* Transmit Programmable Burst Length 8 */
8315#define ETH_DMACTCR_TPBL_16PBL (0x00100000U) /* Transmit Programmable Burst Length 16 */
8316#define ETH_DMACTCR_TPBL_32PBL (0x00200000U) /* Transmit Programmable Burst Length 32 */
8317#define ETH_DMACTCR_TSE_Pos (12U)
8318#define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos)
8319#define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
8320#define ETH_DMACTCR_OSP_Pos (4U)
8321#define ETH_DMACTCR_OSP_Msk (0x1UL << ETH_DMACTCR_OSP_Pos)
8322#define ETH_DMACTCR_OSP ETH_DMACTCR_OSP_Msk /* Operate on Second Packet */
8323#define ETH_DMACTCR_ST_Pos (0U)
8324#define ETH_DMACTCR_ST_Msk (0x1UL << ETH_DMACTCR_ST_Pos)
8325#define ETH_DMACTCR_ST ETH_DMACTCR_ST_Msk /* Start or Stop Transmission Command */
8326
8327/* Bit definition for Ethernet DMA Channel Rx Control Register */
8328#define ETH_DMACRCR_RPF_Pos (31U)
8329#define ETH_DMACRCR_RPF_Msk (0x1UL << ETH_DMACRCR_RPF_Pos)
8330#define ETH_DMACRCR_RPF ETH_DMACRCR_RPF_Msk /* Rx Packet Flush */
8331#define ETH_DMACRCR_RPBL_Pos (16U)
8332#define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos)
8333#define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
8334#define ETH_DMACRCR_RPBL_1PBL (0x00010000U) /* Receive Programmable Burst Length 1 */
8335#define ETH_DMACRCR_RPBL_2PBL (0x00020000U) /* Receive Programmable Burst Length 2 */
8336#define ETH_DMACRCR_RPBL_4PBL (0x00040000U) /* Receive Programmable Burst Length 4 */
8337#define ETH_DMACRCR_RPBL_8PBL (0x00080000U) /* Receive Programmable Burst Length 8 */
8338#define ETH_DMACRCR_RPBL_16PBL (0x00100000U) /* Receive Programmable Burst Length 16 */
8339#define ETH_DMACRCR_RPBL_32PBL (0x00200000U) /* Receive Programmable Burst Length 32 */
8340#define ETH_DMACRCR_RBSZ_Pos (1U)
8341#define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos)
8342#define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
8343#define ETH_DMACRCR_SR_Pos (0U)
8344#define ETH_DMACRCR_SR_Msk (0x1UL << ETH_DMACRCR_SR_Pos)
8345#define ETH_DMACRCR_SR ETH_DMACRCR_SR_Msk /* Start or Stop Receive */
8346
8347/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
8348#define ETH_DMACTDLAR_TDESLA_Pos (2U)
8349#define ETH_DMACTDLAR_TDESLA_Msk (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos)
8350#define ETH_DMACTDLAR_TDESLA ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
8351
8352/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
8353#define ETH_DMACRDLAR_RDESLA_Pos (2U)
8354#define ETH_DMACRDLAR_RDESLA_Msk (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos)
8355#define ETH_DMACRDLAR_RDESLA ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
8356
8357/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
8358#define ETH_DMACTDTPR_TDT_Pos (2U)
8359#define ETH_DMACTDTPR_TDT_Msk (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos)
8360#define ETH_DMACTDTPR_TDT ETH_DMACTDTPR_TDT_Msk /* Transmit Descriptor Tail Pointer */
8361
8362/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
8363#define ETH_DMACRDTPR_RDT_Pos (2U)
8364#define ETH_DMACRDTPR_RDT_Msk (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos)
8365#define ETH_DMACRDTPR_RDT ETH_DMACRDTPR_RDT_Msk /* Receive Descriptor Tail Pointer */
8366
8367/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
8368#define ETH_DMACTDRLR_TDRL_Pos (0U)
8369#define ETH_DMACTDRLR_TDRL_Msk (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos)
8370#define ETH_DMACTDRLR_TDRL ETH_DMACTDRLR_TDRL_Msk /* Transmit Descriptor Ring Length */
8371
8372/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
8373#define ETH_DMACRDRLR_RDRL_Pos (0U)
8374#define ETH_DMACRDRLR_RDRL_Msk (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos)
8375#define ETH_DMACRDRLR_RDRL ETH_DMACRDRLR_RDRL_Msk /* Receive Descriptor Ring Length */
8376
8377/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
8378#define ETH_DMACIER_NIE_Pos (15U)
8379#define ETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos)
8380#define ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /* Normal Interrupt Summary Enable */
8381#define ETH_DMACIER_AIE_Pos (14U)
8382#define ETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos)
8383#define ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /* Abnormal Interrupt Summary Enable */
8384#define ETH_DMACIER_CDEE_Pos (13U)
8385#define ETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos)
8386#define ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /* Context Descriptor Error Enable */
8387#define ETH_DMACIER_FBEE_Pos (12U)
8388#define ETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos)
8389#define ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /* Fatal Bus Error Enable */
8390#define ETH_DMACIER_ERIE_Pos (11U)
8391#define ETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos)
8392#define ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /* Early Receive Interrupt Enable */
8393#define ETH_DMACIER_ETIE_Pos (10U)
8394#define ETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos)
8395#define ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /* Early Transmit Interrupt Enable */
8396#define ETH_DMACIER_RWTE_Pos (9U)
8397#define ETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos)
8398#define ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /* Receive Watchdog Timeout Enable */
8399#define ETH_DMACIER_RSE_Pos (8U)
8400#define ETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos)
8401#define ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /* Receive Stopped Enable */
8402#define ETH_DMACIER_RBUE_Pos (7U)
8403#define ETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos)
8404#define ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /* Receive Buffer Unavailable Enable */
8405#define ETH_DMACIER_RIE_Pos (6U)
8406#define ETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos)
8407#define ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /* Receive Interrupt Enable */
8408#define ETH_DMACIER_TBUE_Pos (2U)
8409#define ETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos)
8410#define ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /* Transmit Buffer Unavailable Enable */
8411#define ETH_DMACIER_TXSE_Pos (1U)
8412#define ETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos)
8413#define ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /* Transmit Stopped Enable */
8414#define ETH_DMACIER_TIE_Pos (0U)
8415#define ETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos)
8416#define ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /* Transmit Interrupt Enable */
8417
8418/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
8419#define ETH_DMACRIWTR_RWT_Pos (0U)
8420#define ETH_DMACRIWTR_RWT_Msk (0xFFUL << ETH_DMACRIWTR_RWT_Pos)
8421#define ETH_DMACRIWTR_RWT ETH_DMACRIWTR_RWT_Msk /* Receive Interrupt Watchdog Timer Count */
8422
8423/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
8424#define ETH_DMACCATDR_CURTDESAPTR_Pos (0U)
8425#define ETH_DMACCATDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos)
8426#define ETH_DMACCATDR_CURTDESAPTR ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
8427
8428/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
8429#define ETH_DMACCARDR_CURRDESAPTR_Pos (0U)
8430#define ETH_DMACCARDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos)
8431#define ETH_DMACCARDR_CURRDESAPTR ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
8432
8433/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
8434#define ETH_DMACCATBR_CURTBUFAPTR_Pos (0U)
8435#define ETH_DMACCATBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos)
8436#define ETH_DMACCATBR_CURTBUFAPTR ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
8437
8438/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
8439#define ETH_DMACCARBR_CURRBUFAPTR_Pos (0U)
8440#define ETH_DMACCARBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos)
8441#define ETH_DMACCARBR_CURRBUFAPTR ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
8442
8443/* Bit definition for Ethernet DMA Channel Status Register */
8444#define ETH_DMACSR_REB_Pos (19U)
8445#define ETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos)
8446#define ETH_DMACSR_REB ETH_DMACSR_REB_Msk /* Rx DMA Error Bits */
8447#define ETH_DMACSR_TEB_Pos (16U)
8448#define ETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos)
8449#define ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /* Tx DMA Error Bits */
8450#define ETH_DMACSR_NIS_Pos (15U)
8451#define ETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos)
8452#define ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /* Normal Interrupt Summary */
8453#define ETH_DMACSR_AIS_Pos (14U)
8454#define ETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos)
8455#define ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /* Abnormal Interrupt Summary */
8456#define ETH_DMACSR_CDE_Pos (13U)
8457#define ETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos)
8458#define ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /* Context Descriptor Error */
8459#define ETH_DMACSR_FBE_Pos (12U)
8460#define ETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos)
8461#define ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /* Fatal Bus Error */
8462#define ETH_DMACSR_ERI_Pos (11U)
8463#define ETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos)
8464#define ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /* Early Receive Interrupt */
8465#define ETH_DMACSR_ETI_Pos (10U)
8466#define ETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos)
8467#define ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /* Early Transmit Interrupt */
8468#define ETH_DMACSR_RWT_Pos (9U)
8469#define ETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos)
8470#define ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /* Receive Watchdog Timeout */
8471#define ETH_DMACSR_RPS_Pos (8U)
8472#define ETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos)
8473#define ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /* Receive Process Stopped */
8474#define ETH_DMACSR_RBU_Pos (7U)
8475#define ETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos)
8476#define ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /* Receive Buffer Unavailable */
8477#define ETH_DMACSR_RI_Pos (6U)
8478#define ETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos)
8479#define ETH_DMACSR_RI ETH_DMACSR_RI_Msk /* Receive Interrupt */
8480#define ETH_DMACSR_TBU_Pos (2U)
8481#define ETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos)
8482#define ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /* Transmit Buffer Unavailable */
8483#define ETH_DMACSR_TPS_Pos (1U)
8484#define ETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos)
8485#define ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /* Transmit Process Stopped */
8486#define ETH_DMACSR_TI_Pos (0U)
8487#define ETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos)
8488#define ETH_DMACSR_TI ETH_DMACSR_TI_Msk /* Transmit Interrupt */
8489
8490/* Bit definition for Ethernet DMA Channel missed frame count register */
8491#define ETH_DMACMFCR_MFCO_Pos (15U)
8492#define ETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos)
8493#define ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /* Overflow status of the MFC Counter */
8494#define ETH_DMACMFCR_MFC_Pos (0U)
8495#define ETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos)
8496#define ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /* The number of packet counters dropped by the DMA */
8497
8498/******************************************************************************/
8499/* */
8500/* DMA Controller */
8501/* */
8502/******************************************************************************/
8503/******************** Bits definition for DMA_SxCR register *****************/
8504#define DMA_SxCR_MBURST_Pos (23U)
8505#define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos)
8506#define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk
8507#define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos)
8508#define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos)
8509#define DMA_SxCR_PBURST_Pos (21U)
8510#define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos)
8511#define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk
8512#define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos)
8513#define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos)
8514#define DMA_SxCR_TRBUFF_Pos (20U)
8515#define DMA_SxCR_TRBUFF_Msk (0x1UL << DMA_SxCR_TRBUFF_Pos)
8516#define DMA_SxCR_TRBUFF DMA_SxCR_TRBUFF_Msk
8517#define DMA_SxCR_CT_Pos (19U)
8518#define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos)
8519#define DMA_SxCR_CT DMA_SxCR_CT_Msk
8520#define DMA_SxCR_DBM_Pos (18U)
8521#define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos)
8522#define DMA_SxCR_DBM DMA_SxCR_DBM_Msk
8523#define DMA_SxCR_PL_Pos (16U)
8524#define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos)
8525#define DMA_SxCR_PL DMA_SxCR_PL_Msk
8526#define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos)
8527#define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos)
8528#define DMA_SxCR_PINCOS_Pos (15U)
8529#define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos)
8530#define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk
8531#define DMA_SxCR_MSIZE_Pos (13U)
8532#define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos)
8533#define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk
8534#define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos)
8535#define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos)
8536#define DMA_SxCR_PSIZE_Pos (11U)
8537#define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos)
8538#define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
8539#define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos)
8540#define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos)
8541#define DMA_SxCR_MINC_Pos (10U)
8542#define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos)
8543#define DMA_SxCR_MINC DMA_SxCR_MINC_Msk
8544#define DMA_SxCR_PINC_Pos (9U)
8545#define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos)
8546#define DMA_SxCR_PINC DMA_SxCR_PINC_Msk
8547#define DMA_SxCR_CIRC_Pos (8U)
8548#define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos)
8549#define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk
8550#define DMA_SxCR_DIR_Pos (6U)
8551#define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos)
8552#define DMA_SxCR_DIR DMA_SxCR_DIR_Msk
8553#define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos)
8554#define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos)
8555#define DMA_SxCR_PFCTRL_Pos (5U)
8556#define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos)
8557#define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk
8558#define DMA_SxCR_TCIE_Pos (4U)
8559#define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos)
8560#define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk
8561#define DMA_SxCR_HTIE_Pos (3U)
8562#define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos)
8563#define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk
8564#define DMA_SxCR_TEIE_Pos (2U)
8565#define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos)
8566#define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk
8567#define DMA_SxCR_DMEIE_Pos (1U)
8568#define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos)
8569#define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk
8570#define DMA_SxCR_EN_Pos (0U)
8571#define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos)
8572#define DMA_SxCR_EN DMA_SxCR_EN_Msk
8574/******************** Bits definition for DMA_SxCNDTR register **************/
8575#define DMA_SxNDT_Pos (0U)
8576#define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos)
8577#define DMA_SxNDT DMA_SxNDT_Msk
8578#define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos)
8579#define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos)
8580#define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos)
8581#define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos)
8582#define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos)
8583#define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos)
8584#define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos)
8585#define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos)
8586#define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos)
8587#define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos)
8588#define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos)
8589#define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos)
8590#define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos)
8591#define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos)
8592#define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos)
8593#define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos)
8595/******************** Bits definition for DMA_SxFCR register ****************/
8596#define DMA_SxFCR_FEIE_Pos (7U)
8597#define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos)
8598#define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk
8599#define DMA_SxFCR_FS_Pos (3U)
8600#define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos)
8601#define DMA_SxFCR_FS DMA_SxFCR_FS_Msk
8602#define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos)
8603#define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos)
8604#define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos)
8605#define DMA_SxFCR_DMDIS_Pos (2U)
8606#define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos)
8607#define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk
8608#define DMA_SxFCR_FTH_Pos (0U)
8609#define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos)
8610#define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk
8611#define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos)
8612#define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos)
8614/******************** Bits definition for DMA_LISR register *****************/
8615#define DMA_LISR_TCIF3_Pos (27U)
8616#define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos)
8617#define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk
8618#define DMA_LISR_HTIF3_Pos (26U)
8619#define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos)
8620#define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk
8621#define DMA_LISR_TEIF3_Pos (25U)
8622#define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos)
8623#define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk
8624#define DMA_LISR_DMEIF3_Pos (24U)
8625#define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos)
8626#define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk
8627#define DMA_LISR_FEIF3_Pos (22U)
8628#define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos)
8629#define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk
8630#define DMA_LISR_TCIF2_Pos (21U)
8631#define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos)
8632#define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk
8633#define DMA_LISR_HTIF2_Pos (20U)
8634#define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos)
8635#define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk
8636#define DMA_LISR_TEIF2_Pos (19U)
8637#define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos)
8638#define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk
8639#define DMA_LISR_DMEIF2_Pos (18U)
8640#define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos)
8641#define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk
8642#define DMA_LISR_FEIF2_Pos (16U)
8643#define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos)
8644#define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk
8645#define DMA_LISR_TCIF1_Pos (11U)
8646#define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos)
8647#define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk
8648#define DMA_LISR_HTIF1_Pos (10U)
8649#define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos)
8650#define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk
8651#define DMA_LISR_TEIF1_Pos (9U)
8652#define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos)
8653#define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk
8654#define DMA_LISR_DMEIF1_Pos (8U)
8655#define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos)
8656#define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk
8657#define DMA_LISR_FEIF1_Pos (6U)
8658#define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos)
8659#define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk
8660#define DMA_LISR_TCIF0_Pos (5U)
8661#define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos)
8662#define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk
8663#define DMA_LISR_HTIF0_Pos (4U)
8664#define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos)
8665#define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk
8666#define DMA_LISR_TEIF0_Pos (3U)
8667#define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos)
8668#define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk
8669#define DMA_LISR_DMEIF0_Pos (2U)
8670#define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos)
8671#define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk
8672#define DMA_LISR_FEIF0_Pos (0U)
8673#define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos)
8674#define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk
8676/******************** Bits definition for DMA_HISR register *****************/
8677#define DMA_HISR_TCIF7_Pos (27U)
8678#define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos)
8679#define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk
8680#define DMA_HISR_HTIF7_Pos (26U)
8681#define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos)
8682#define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk
8683#define DMA_HISR_TEIF7_Pos (25U)
8684#define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos)
8685#define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk
8686#define DMA_HISR_DMEIF7_Pos (24U)
8687#define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos)
8688#define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk
8689#define DMA_HISR_FEIF7_Pos (22U)
8690#define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos)
8691#define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk
8692#define DMA_HISR_TCIF6_Pos (21U)
8693#define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos)
8694#define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk
8695#define DMA_HISR_HTIF6_Pos (20U)
8696#define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos)
8697#define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk
8698#define DMA_HISR_TEIF6_Pos (19U)
8699#define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos)
8700#define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk
8701#define DMA_HISR_DMEIF6_Pos (18U)
8702#define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos)
8703#define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk
8704#define DMA_HISR_FEIF6_Pos (16U)
8705#define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos)
8706#define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk
8707#define DMA_HISR_TCIF5_Pos (11U)
8708#define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos)
8709#define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk
8710#define DMA_HISR_HTIF5_Pos (10U)
8711#define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos)
8712#define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk
8713#define DMA_HISR_TEIF5_Pos (9U)
8714#define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos)
8715#define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk
8716#define DMA_HISR_DMEIF5_Pos (8U)
8717#define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos)
8718#define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk
8719#define DMA_HISR_FEIF5_Pos (6U)
8720#define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos)
8721#define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk
8722#define DMA_HISR_TCIF4_Pos (5U)
8723#define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos)
8724#define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk
8725#define DMA_HISR_HTIF4_Pos (4U)
8726#define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos)
8727#define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk
8728#define DMA_HISR_TEIF4_Pos (3U)
8729#define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos)
8730#define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk
8731#define DMA_HISR_DMEIF4_Pos (2U)
8732#define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos)
8733#define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk
8734#define DMA_HISR_FEIF4_Pos (0U)
8735#define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos)
8736#define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk
8738/******************** Bits definition for DMA_LIFCR register ****************/
8739#define DMA_LIFCR_CTCIF3_Pos (27U)
8740#define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos)
8741#define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk
8742#define DMA_LIFCR_CHTIF3_Pos (26U)
8743#define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos)
8744#define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk
8745#define DMA_LIFCR_CTEIF3_Pos (25U)
8746#define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos)
8747#define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk
8748#define DMA_LIFCR_CDMEIF3_Pos (24U)
8749#define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos)
8750#define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk
8751#define DMA_LIFCR_CFEIF3_Pos (22U)
8752#define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos)
8753#define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk
8754#define DMA_LIFCR_CTCIF2_Pos (21U)
8755#define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos)
8756#define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk
8757#define DMA_LIFCR_CHTIF2_Pos (20U)
8758#define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos)
8759#define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk
8760#define DMA_LIFCR_CTEIF2_Pos (19U)
8761#define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos)
8762#define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk
8763#define DMA_LIFCR_CDMEIF2_Pos (18U)
8764#define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos)
8765#define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk
8766#define DMA_LIFCR_CFEIF2_Pos (16U)
8767#define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos)
8768#define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk
8769#define DMA_LIFCR_CTCIF1_Pos (11U)
8770#define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos)
8771#define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk
8772#define DMA_LIFCR_CHTIF1_Pos (10U)
8773#define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos)
8774#define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk
8775#define DMA_LIFCR_CTEIF1_Pos (9U)
8776#define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos)
8777#define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk
8778#define DMA_LIFCR_CDMEIF1_Pos (8U)
8779#define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos)
8780#define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk
8781#define DMA_LIFCR_CFEIF1_Pos (6U)
8782#define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos)
8783#define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk
8784#define DMA_LIFCR_CTCIF0_Pos (5U)
8785#define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos)
8786#define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk
8787#define DMA_LIFCR_CHTIF0_Pos (4U)
8788#define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos)
8789#define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk
8790#define DMA_LIFCR_CTEIF0_Pos (3U)
8791#define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos)
8792#define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk
8793#define DMA_LIFCR_CDMEIF0_Pos (2U)
8794#define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos)
8795#define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk
8796#define DMA_LIFCR_CFEIF0_Pos (0U)
8797#define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos)
8798#define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk
8800/******************** Bits definition for DMA_HIFCR register ****************/
8801#define DMA_HIFCR_CTCIF7_Pos (27U)
8802#define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos)
8803#define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk
8804#define DMA_HIFCR_CHTIF7_Pos (26U)
8805#define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos)
8806#define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk
8807#define DMA_HIFCR_CTEIF7_Pos (25U)
8808#define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos)
8809#define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk
8810#define DMA_HIFCR_CDMEIF7_Pos (24U)
8811#define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos)
8812#define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk
8813#define DMA_HIFCR_CFEIF7_Pos (22U)
8814#define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos)
8815#define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk
8816#define DMA_HIFCR_CTCIF6_Pos (21U)
8817#define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos)
8818#define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk
8819#define DMA_HIFCR_CHTIF6_Pos (20U)
8820#define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos)
8821#define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk
8822#define DMA_HIFCR_CTEIF6_Pos (19U)
8823#define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos)
8824#define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk
8825#define DMA_HIFCR_CDMEIF6_Pos (18U)
8826#define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos)
8827#define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk
8828#define DMA_HIFCR_CFEIF6_Pos (16U)
8829#define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos)
8830#define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk
8831#define DMA_HIFCR_CTCIF5_Pos (11U)
8832#define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos)
8833#define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk
8834#define DMA_HIFCR_CHTIF5_Pos (10U)
8835#define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos)
8836#define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk
8837#define DMA_HIFCR_CTEIF5_Pos (9U)
8838#define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos)
8839#define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk
8840#define DMA_HIFCR_CDMEIF5_Pos (8U)
8841#define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos)
8842#define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk
8843#define DMA_HIFCR_CFEIF5_Pos (6U)
8844#define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos)
8845#define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk
8846#define DMA_HIFCR_CTCIF4_Pos (5U)
8847#define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos)
8848#define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk
8849#define DMA_HIFCR_CHTIF4_Pos (4U)
8850#define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos)
8851#define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk
8852#define DMA_HIFCR_CTEIF4_Pos (3U)
8853#define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos)
8854#define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk
8855#define DMA_HIFCR_CDMEIF4_Pos (2U)
8856#define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos)
8857#define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk
8858#define DMA_HIFCR_CFEIF4_Pos (0U)
8859#define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos)
8860#define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk
8862/****************** Bit definition for DMA_SxPAR register ********************/
8863#define DMA_SxPAR_PA_Pos (0U)
8864#define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)
8865#define DMA_SxPAR_PA DMA_SxPAR_PA_Msk
8867/****************** Bit definition for DMA_SxM0AR register ********************/
8868#define DMA_SxM0AR_M0A_Pos (0U)
8869#define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)
8870#define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk
8872/****************** Bit definition for DMA_SxM1AR register ********************/
8873#define DMA_SxM1AR_M1A_Pos (0U)
8874#define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)
8875#define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk
8877/******************************************************************************/
8878/* */
8879/* DMAMUX Controller */
8880/* */
8881/******************************************************************************/
8882/******************** Bits definition for DMAMUX_CxCR register **************/
8883#define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
8884#define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)
8885#define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk
8886#define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
8887#define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
8888#define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
8889#define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
8890#define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
8891#define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
8892#define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
8893#define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)
8894#define DMAMUX_CxCR_SOIE_Pos (8U)
8895#define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos)
8896#define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk
8897#define DMAMUX_CxCR_EGE_Pos (9U)
8898#define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos)
8899#define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk
8900#define DMAMUX_CxCR_SE_Pos (16U)
8901#define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos)
8902#define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk
8903#define DMAMUX_CxCR_SPOL_Pos (17U)
8904#define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos)
8905#define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk
8906#define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos)
8907#define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos)
8908#define DMAMUX_CxCR_NBREQ_Pos (19U)
8909#define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)
8910#define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk
8911#define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos)
8912#define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos)
8913#define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos)
8914#define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos)
8915#define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos)
8916#define DMAMUX_CxCR_SYNC_ID_Pos (24U)
8917#define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)
8918#define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk
8919#define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)
8920#define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)
8921#define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)
8922#define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)
8923#define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)
8925/******************** Bits definition for DMAMUX_CSR register **************/
8926#define DMAMUX_CSR_SOF0_Pos (0U)
8927#define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos)
8928#define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk
8929#define DMAMUX_CSR_SOF1_Pos (1U)
8930#define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos)
8931#define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk
8932#define DMAMUX_CSR_SOF2_Pos (2U)
8933#define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos)
8934#define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk
8935#define DMAMUX_CSR_SOF3_Pos (3U)
8936#define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos)
8937#define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk
8938#define DMAMUX_CSR_SOF4_Pos (4U)
8939#define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos)
8940#define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk
8941#define DMAMUX_CSR_SOF5_Pos (5U)
8942#define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos)
8943#define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk
8944#define DMAMUX_CSR_SOF6_Pos (6U)
8945#define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos)
8946#define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk
8947#define DMAMUX_CSR_SOF7_Pos (7U)
8948#define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos)
8949#define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk
8950#define DMAMUX_CSR_SOF8_Pos (8U)
8951#define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos)
8952#define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk
8953#define DMAMUX_CSR_SOF9_Pos (9U)
8954#define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos)
8955#define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk
8956#define DMAMUX_CSR_SOF10_Pos (10U)
8957#define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos)
8958#define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk
8959#define DMAMUX_CSR_SOF11_Pos (11U)
8960#define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos)
8961#define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk
8962#define DMAMUX_CSR_SOF12_Pos (12U)
8963#define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos)
8964#define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk
8965#define DMAMUX_CSR_SOF13_Pos (13U)
8966#define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos)
8967#define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk
8968#define DMAMUX_CSR_SOF14_Pos (14U)
8969#define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos)
8970#define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk
8971#define DMAMUX_CSR_SOF15_Pos (15U)
8972#define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos)
8973#define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk
8975/******************** Bits definition for DMAMUX_CFR register **************/
8976#define DMAMUX_CFR_CSOF0_Pos (0U)
8977#define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos)
8978#define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk
8979#define DMAMUX_CFR_CSOF1_Pos (1U)
8980#define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos)
8981#define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk
8982#define DMAMUX_CFR_CSOF2_Pos (2U)
8983#define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos)
8984#define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk
8985#define DMAMUX_CFR_CSOF3_Pos (3U)
8986#define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos)
8987#define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk
8988#define DMAMUX_CFR_CSOF4_Pos (4U)
8989#define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos)
8990#define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk
8991#define DMAMUX_CFR_CSOF5_Pos (5U)
8992#define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos)
8993#define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk
8994#define DMAMUX_CFR_CSOF6_Pos (6U)
8995#define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos)
8996#define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk
8997#define DMAMUX_CFR_CSOF7_Pos (7U)
8998#define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos)
8999#define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk
9000#define DMAMUX_CFR_CSOF8_Pos (8U)
9001#define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos)
9002#define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk
9003#define DMAMUX_CFR_CSOF9_Pos (9U)
9004#define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos)
9005#define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk
9006#define DMAMUX_CFR_CSOF10_Pos (10U)
9007#define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos)
9008#define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk
9009#define DMAMUX_CFR_CSOF11_Pos (11U)
9010#define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos)
9011#define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk
9012#define DMAMUX_CFR_CSOF12_Pos (12U)
9013#define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos)
9014#define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk
9015#define DMAMUX_CFR_CSOF13_Pos (13U)
9016#define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos)
9017#define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk
9018#define DMAMUX_CFR_CSOF14_Pos (14U)
9019#define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos)
9020#define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk
9021#define DMAMUX_CFR_CSOF15_Pos (15U)
9022#define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos)
9023#define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk
9025/******************** Bits definition for DMAMUX_RGxCR register ************/
9026#define DMAMUX_RGxCR_SIG_ID_Pos (0U)
9027#define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)
9028#define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk
9029#define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)
9030#define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)
9031#define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)
9032#define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)
9033#define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)
9034#define DMAMUX_RGxCR_OIE_Pos (8U)
9035#define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos)
9036#define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk
9037#define DMAMUX_RGxCR_GE_Pos (16U)
9038#define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos)
9039#define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk
9040#define DMAMUX_RGxCR_GPOL_Pos (17U)
9041#define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos)
9042#define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk
9043#define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos)
9044#define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos)
9045#define DMAMUX_RGxCR_GNBREQ_Pos (19U)
9046#define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)
9047#define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk
9048#define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)
9049#define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)
9050#define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)
9051#define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)
9052#define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)
9054/******************** Bits definition for DMAMUX_RGSR register **************/
9055#define DMAMUX_RGSR_OF0_Pos (0U)
9056#define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos)
9057#define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk
9058#define DMAMUX_RGSR_OF1_Pos (1U)
9059#define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos)
9060#define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk
9061#define DMAMUX_RGSR_OF2_Pos (2U)
9062#define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos)
9063#define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk
9064#define DMAMUX_RGSR_OF3_Pos (3U)
9065#define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos)
9066#define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk
9067#define DMAMUX_RGSR_OF4_Pos (4U)
9068#define DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos)
9069#define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk
9070#define DMAMUX_RGSR_OF5_Pos (5U)
9071#define DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos)
9072#define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk
9073#define DMAMUX_RGSR_OF6_Pos (6U)
9074#define DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos)
9075#define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk
9076#define DMAMUX_RGSR_OF7_Pos (7U)
9077#define DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos)
9078#define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk
9080/******************** Bits definition for DMAMUX_RGCFR register **************/
9081#define DMAMUX_RGCFR_COF0_Pos (0U)
9082#define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos)
9083#define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk
9084#define DMAMUX_RGCFR_COF1_Pos (1U)
9085#define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos)
9086#define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk
9087#define DMAMUX_RGCFR_COF2_Pos (2U)
9088#define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos)
9089#define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk
9090#define DMAMUX_RGCFR_COF3_Pos (3U)
9091#define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos)
9092#define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk
9093#define DMAMUX_RGCFR_COF4_Pos (4U)
9094#define DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos)
9095#define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk
9096#define DMAMUX_RGCFR_COF5_Pos (5U)
9097#define DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos)
9098#define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk
9099#define DMAMUX_RGCFR_COF6_Pos (6U)
9100#define DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos)
9101#define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk
9102#define DMAMUX_RGCFR_COF7_Pos (7U)
9103#define DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos)
9104#define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk
9106/******************************************************************************/
9107/* */
9108/* AHB Master DMA2D Controller (DMA2D) */
9109/* */
9110/******************************************************************************/
9111
9112/******************** Bit definition for DMA2D_CR register ******************/
9113
9114#define DMA2D_CR_START_Pos (0U)
9115#define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos)
9116#define DMA2D_CR_START DMA2D_CR_START_Msk
9117#define DMA2D_CR_SUSP_Pos (1U)
9118#define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos)
9119#define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk
9120#define DMA2D_CR_ABORT_Pos (2U)
9121#define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos)
9122#define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk
9123#define DMA2D_CR_LOM_Pos (6U)
9124#define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos)
9125#define DMA2D_CR_LOM DMA2D_CR_LOM_Msk
9126#define DMA2D_CR_TEIE_Pos (8U)
9127#define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos)
9128#define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk
9129#define DMA2D_CR_TCIE_Pos (9U)
9130#define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos)
9131#define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk
9132#define DMA2D_CR_TWIE_Pos (10U)
9133#define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos)
9134#define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk
9135#define DMA2D_CR_CAEIE_Pos (11U)
9136#define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos)
9137#define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk
9138#define DMA2D_CR_CTCIE_Pos (12U)
9139#define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos)
9140#define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk
9141#define DMA2D_CR_CEIE_Pos (13U)
9142#define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos)
9143#define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk
9144#define DMA2D_CR_MODE_Pos (16U)
9145#define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos)
9146#define DMA2D_CR_MODE DMA2D_CR_MODE_Msk
9147#define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos)
9148#define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos)
9149#define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos)
9151/******************** Bit definition for DMA2D_ISR register *****************/
9152
9153#define DMA2D_ISR_TEIF_Pos (0U)
9154#define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos)
9155#define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk
9156#define DMA2D_ISR_TCIF_Pos (1U)
9157#define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos)
9158#define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk
9159#define DMA2D_ISR_TWIF_Pos (2U)
9160#define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos)
9161#define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk
9162#define DMA2D_ISR_CAEIF_Pos (3U)
9163#define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos)
9164#define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk
9165#define DMA2D_ISR_CTCIF_Pos (4U)
9166#define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos)
9167#define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk
9168#define DMA2D_ISR_CEIF_Pos (5U)
9169#define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos)
9170#define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk
9172/******************** Bit definition for DMA2D_IFCR register ****************/
9173
9174#define DMA2D_IFCR_CTEIF_Pos (0U)
9175#define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos)
9176#define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk
9177#define DMA2D_IFCR_CTCIF_Pos (1U)
9178#define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos)
9179#define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk
9180#define DMA2D_IFCR_CTWIF_Pos (2U)
9181#define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos)
9182#define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk
9183#define DMA2D_IFCR_CAECIF_Pos (3U)
9184#define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos)
9185#define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk
9186#define DMA2D_IFCR_CCTCIF_Pos (4U)
9187#define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos)
9188#define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk
9189#define DMA2D_IFCR_CCEIF_Pos (5U)
9190#define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos)
9191#define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk
9193/******************** Bit definition for DMA2D_FGMAR register ***************/
9194
9195#define DMA2D_FGMAR_MA_Pos (0U)
9196#define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)
9197#define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk
9199/******************** Bit definition for DMA2D_FGOR register ****************/
9200
9201#define DMA2D_FGOR_LO_Pos (0U)
9202#define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos)
9203#define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk
9205/******************** Bit definition for DMA2D_BGMAR register ***************/
9206
9207#define DMA2D_BGMAR_MA_Pos (0U)
9208#define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)
9209#define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk
9211/******************** Bit definition for DMA2D_BGOR register ****************/
9212
9213#define DMA2D_BGOR_LO_Pos (0U)
9214#define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos)
9215#define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk
9217/******************** Bit definition for DMA2D_FGPFCCR register *************/
9218
9219#define DMA2D_FGPFCCR_CM_Pos (0U)
9220#define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos)
9221#define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk
9222#define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos)
9223#define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos)
9224#define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos)
9225#define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos)
9226#define DMA2D_FGPFCCR_CCM_Pos (4U)
9227#define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos)
9228#define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk
9229#define DMA2D_FGPFCCR_START_Pos (5U)
9230#define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos)
9231#define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk
9232#define DMA2D_FGPFCCR_CS_Pos (8U)
9233#define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos)
9234#define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk
9235#define DMA2D_FGPFCCR_AM_Pos (16U)
9236#define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos)
9237#define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk
9238#define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos)
9239#define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos)
9240#define DMA2D_FGPFCCR_CSS_Pos (18U)
9241#define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos)
9242#define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
9243#define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos)
9244#define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos)
9245#define DMA2D_FGPFCCR_AI_Pos (20U)
9246#define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos)
9247#define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk
9248#define DMA2D_FGPFCCR_RBS_Pos (21U)
9249#define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos)
9250#define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk
9251#define DMA2D_FGPFCCR_ALPHA_Pos (24U)
9252#define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)
9253#define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk
9255/******************** Bit definition for DMA2D_FGCOLR register **************/
9256
9257#define DMA2D_FGCOLR_BLUE_Pos (0U)
9258#define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)
9259#define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk
9260#define DMA2D_FGCOLR_GREEN_Pos (8U)
9261#define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)
9262#define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk
9263#define DMA2D_FGCOLR_RED_Pos (16U)
9264#define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos)
9265#define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk
9267/******************** Bit definition for DMA2D_BGPFCCR register *************/
9268
9269#define DMA2D_BGPFCCR_CM_Pos (0U)
9270#define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos)
9271#define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk
9272#define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos)
9273#define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos)
9274#define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos)
9275#define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos)
9276#define DMA2D_BGPFCCR_CCM_Pos (4U)
9277#define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos)
9278#define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk
9279#define DMA2D_BGPFCCR_START_Pos (5U)
9280#define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos)
9281#define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk
9282#define DMA2D_BGPFCCR_CS_Pos (8U)
9283#define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos)
9284#define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk
9285#define DMA2D_BGPFCCR_AM_Pos (16U)
9286#define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos)
9287#define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk
9288#define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos)
9289#define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos)
9290#define DMA2D_BGPFCCR_AI_Pos (20U)
9291#define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos)
9292#define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk
9293#define DMA2D_BGPFCCR_RBS_Pos (21U)
9294#define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos)
9295#define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk
9296#define DMA2D_BGPFCCR_ALPHA_Pos (24U)
9297#define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)
9298#define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk
9300/******************** Bit definition for DMA2D_BGCOLR register **************/
9301
9302#define DMA2D_BGCOLR_BLUE_Pos (0U)
9303#define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)
9304#define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk
9305#define DMA2D_BGCOLR_GREEN_Pos (8U)
9306#define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)
9307#define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk
9308#define DMA2D_BGCOLR_RED_Pos (16U)
9309#define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos)
9310#define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk
9312/******************** Bit definition for DMA2D_FGCMAR register **************/
9313
9314#define DMA2D_FGCMAR_MA_Pos (0U)
9315#define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)
9316#define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk
9318/******************** Bit definition for DMA2D_BGCMAR register **************/
9319
9320#define DMA2D_BGCMAR_MA_Pos (0U)
9321#define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)
9322#define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk
9324/******************** Bit definition for DMA2D_OPFCCR register **************/
9325
9326#define DMA2D_OPFCCR_CM_Pos (0U)
9327#define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos)
9328#define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk
9329#define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos)
9330#define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos)
9331#define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos)
9332#define DMA2D_OPFCCR_SB_Pos (8U)
9333#define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos)
9334#define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk
9335#define DMA2D_OPFCCR_AI_Pos (20U)
9336#define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos)
9337#define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk
9338#define DMA2D_OPFCCR_RBS_Pos (21U)
9339#define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos)
9340#define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk
9342/******************** Bit definition for DMA2D_OCOLR register ***************/
9343
9346#define DMA2D_OCOLR_BLUE_1_Pos (0U)
9347#define DMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/
9348#define DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk
9349#define DMA2D_OCOLR_GREEN_1_Pos (8U)
9350#define DMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/
9351#define DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk
9352#define DMA2D_OCOLR_RED_1_Pos (16U)
9353#define DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */
9354#define DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk
9355#define DMA2D_OCOLR_ALPHA_1_Pos (24U)
9356#define DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/
9357#define DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk
9360#define DMA2D_OCOLR_BLUE_2_Pos (0U)
9361#define DMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/
9362#define DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk
9363#define DMA2D_OCOLR_GREEN_2_Pos (5U)
9364#define DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */
9365#define DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk
9366#define DMA2D_OCOLR_RED_2_Pos (11U)
9367#define DMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/
9368#define DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk
9371#define DMA2D_OCOLR_BLUE_3_Pos (0U)
9372#define DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/
9373#define DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk
9374#define DMA2D_OCOLR_GREEN_3_Pos (5U)
9375#define DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/
9376#define DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk
9377#define DMA2D_OCOLR_RED_3_Pos (10U)
9378#define DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/
9379#define DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk
9380#define DMA2D_OCOLR_ALPHA_3_Pos (15U)
9381#define DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/
9382#define DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk
9385#define DMA2D_OCOLR_BLUE_4_Pos (0U)
9386#define DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/
9387#define DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk
9388#define DMA2D_OCOLR_GREEN_4_Pos (4U)
9389#define DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/
9390#define DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk
9391#define DMA2D_OCOLR_RED_4_Pos (8U)
9392#define DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/
9393#define DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk
9394#define DMA2D_OCOLR_ALPHA_4_Pos (12U)
9395#define DMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/
9396#define DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk
9398/******************** Bit definition for DMA2D_OMAR register ****************/
9399
9400#define DMA2D_OMAR_MA_Pos (0U)
9401#define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)
9402#define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk
9404/******************** Bit definition for DMA2D_OOR register *****************/
9405
9406#define DMA2D_OOR_LO_Pos (0U)
9407#define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos)
9408#define DMA2D_OOR_LO DMA2D_OOR_LO_Msk
9410/******************** Bit definition for DMA2D_NLR register *****************/
9411
9412#define DMA2D_NLR_NL_Pos (0U)
9413#define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos)
9414#define DMA2D_NLR_NL DMA2D_NLR_NL_Msk
9415#define DMA2D_NLR_PL_Pos (16U)
9416#define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos)
9417#define DMA2D_NLR_PL DMA2D_NLR_PL_Msk
9419/******************** Bit definition for DMA2D_LWR register *****************/
9420
9421#define DMA2D_LWR_LW_Pos (0U)
9422#define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos)
9423#define DMA2D_LWR_LW DMA2D_LWR_LW_Msk
9425/******************** Bit definition for DMA2D_AMTCR register ***************/
9426
9427#define DMA2D_AMTCR_EN_Pos (0U)
9428#define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos)
9429#define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk
9430#define DMA2D_AMTCR_DT_Pos (8U)
9431#define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos)
9432#define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk
9435/******************** Bit definition for DMA2D_FGCLUT register **************/
9436
9437/******************** Bit definition for DMA2D_BGCLUT register **************/
9438
9439
9440/******************************************************************************/
9441/* */
9442/* External Interrupt/Event Controller */
9443/* */
9444/******************************************************************************/
9445/****************** Bit definition for EXTI_RTSR1 register *******************/
9446#define EXTI_RTSR1_TR_Pos (0U)
9447#define EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)
9448#define EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk
9449#define EXTI_RTSR1_TR0_Pos (0U)
9450#define EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos)
9451#define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk
9452#define EXTI_RTSR1_TR1_Pos (1U)
9453#define EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos)
9454#define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk
9455#define EXTI_RTSR1_TR2_Pos (2U)
9456#define EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos)
9457#define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk
9458#define EXTI_RTSR1_TR3_Pos (3U)
9459#define EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos)
9460#define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk
9461#define EXTI_RTSR1_TR4_Pos (4U)
9462#define EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos)
9463#define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk
9464#define EXTI_RTSR1_TR5_Pos (5U)
9465#define EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos)
9466#define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk
9467#define EXTI_RTSR1_TR6_Pos (6U)
9468#define EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos)
9469#define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk
9470#define EXTI_RTSR1_TR7_Pos (7U)
9471#define EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos)
9472#define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk
9473#define EXTI_RTSR1_TR8_Pos (8U)
9474#define EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos)
9475#define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk
9476#define EXTI_RTSR1_TR9_Pos (9U)
9477#define EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos)
9478#define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk
9479#define EXTI_RTSR1_TR10_Pos (10U)
9480#define EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos)
9481#define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk
9482#define EXTI_RTSR1_TR11_Pos (11U)
9483#define EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos)
9484#define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk
9485#define EXTI_RTSR1_TR12_Pos (12U)
9486#define EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos)
9487#define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk
9488#define EXTI_RTSR1_TR13_Pos (13U)
9489#define EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos)
9490#define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk
9491#define EXTI_RTSR1_TR14_Pos (14U)
9492#define EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos)
9493#define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk
9494#define EXTI_RTSR1_TR15_Pos (15U)
9495#define EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos)
9496#define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk
9497#define EXTI_RTSR1_TR16_Pos (16U)
9498#define EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos)
9499#define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk
9500#define EXTI_RTSR1_TR17_Pos (17U)
9501#define EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos)
9502#define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk
9503#define EXTI_RTSR1_TR18_Pos (18U)
9504#define EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos)
9505#define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk
9506#define EXTI_RTSR1_TR19_Pos (19U)
9507#define EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos)
9508#define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk
9509#define EXTI_RTSR1_TR20_Pos (20U)
9510#define EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos)
9511#define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk
9512#define EXTI_RTSR1_TR21_Pos (21U)
9513#define EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos)
9514#define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk
9516/****************** Bit definition for EXTI_FTSR1 register *******************/
9517#define EXTI_FTSR1_TR_Pos (0U)
9518#define EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)
9519#define EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk
9520#define EXTI_FTSR1_TR0_Pos (0U)
9521#define EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos)
9522#define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk
9523#define EXTI_FTSR1_TR1_Pos (1U)
9524#define EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos)
9525#define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk
9526#define EXTI_FTSR1_TR2_Pos (2U)
9527#define EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos)
9528#define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk
9529#define EXTI_FTSR1_TR3_Pos (3U)
9530#define EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos)
9531#define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk
9532#define EXTI_FTSR1_TR4_Pos (4U)
9533#define EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos)
9534#define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk
9535#define EXTI_FTSR1_TR5_Pos (5U)
9536#define EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos)
9537#define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk
9538#define EXTI_FTSR1_TR6_Pos (6U)
9539#define EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos)
9540#define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk
9541#define EXTI_FTSR1_TR7_Pos (7U)
9542#define EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos)
9543#define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk
9544#define EXTI_FTSR1_TR8_Pos (8U)
9545#define EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos)
9546#define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk
9547#define EXTI_FTSR1_TR9_Pos (9U)
9548#define EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos)
9549#define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk
9550#define EXTI_FTSR1_TR10_Pos (10U)
9551#define EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos)
9552#define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk
9553#define EXTI_FTSR1_TR11_Pos (11U)
9554#define EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos)
9555#define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk
9556#define EXTI_FTSR1_TR12_Pos (12U)
9557#define EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos)
9558#define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk
9559#define EXTI_FTSR1_TR13_Pos (13U)
9560#define EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos)
9561#define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk
9562#define EXTI_FTSR1_TR14_Pos (14U)
9563#define EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos)
9564#define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk
9565#define EXTI_FTSR1_TR15_Pos (15U)
9566#define EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos)
9567#define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk
9568#define EXTI_FTSR1_TR16_Pos (16U)
9569#define EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos)
9570#define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk
9571#define EXTI_FTSR1_TR17_Pos (17U)
9572#define EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos)
9573#define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk
9574#define EXTI_FTSR1_TR18_Pos (18U)
9575#define EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos)
9576#define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk
9577#define EXTI_FTSR1_TR19_Pos (19U)
9578#define EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos)
9579#define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk
9580#define EXTI_FTSR1_TR20_Pos (20U)
9581#define EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos)
9582#define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk
9583#define EXTI_FTSR1_TR21_Pos (21U)
9584#define EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos)
9585#define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk
9587/****************** Bit definition for EXTI_SWIER1 register ******************/
9588#define EXTI_SWIER1_SWIER0_Pos (0U)
9589#define EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos)
9590#define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk
9591#define EXTI_SWIER1_SWIER1_Pos (1U)
9592#define EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos)
9593#define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk
9594#define EXTI_SWIER1_SWIER2_Pos (2U)
9595#define EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos)
9596#define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk
9597#define EXTI_SWIER1_SWIER3_Pos (3U)
9598#define EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos)
9599#define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk
9600#define EXTI_SWIER1_SWIER4_Pos (4U)
9601#define EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos)
9602#define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk
9603#define EXTI_SWIER1_SWIER5_Pos (5U)
9604#define EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos)
9605#define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk
9606#define EXTI_SWIER1_SWIER6_Pos (6U)
9607#define EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos)
9608#define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk
9609#define EXTI_SWIER1_SWIER7_Pos (7U)
9610#define EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos)
9611#define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk
9612#define EXTI_SWIER1_SWIER8_Pos (8U)
9613#define EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos)
9614#define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk
9615#define EXTI_SWIER1_SWIER9_Pos (9U)
9616#define EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos)
9617#define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk
9618#define EXTI_SWIER1_SWIER10_Pos (10U)
9619#define EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos)
9620#define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk
9621#define EXTI_SWIER1_SWIER11_Pos (11U)
9622#define EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos)
9623#define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk
9624#define EXTI_SWIER1_SWIER12_Pos (12U)
9625#define EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos)
9626#define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk
9627#define EXTI_SWIER1_SWIER13_Pos (13U)
9628#define EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos)
9629#define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk
9630#define EXTI_SWIER1_SWIER14_Pos (14U)
9631#define EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos)
9632#define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk
9633#define EXTI_SWIER1_SWIER15_Pos (15U)
9634#define EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos)
9635#define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk
9636#define EXTI_SWIER1_SWIER16_Pos (16U)
9637#define EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos)
9638#define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk
9639#define EXTI_SWIER1_SWIER17_Pos (17U)
9640#define EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos)
9641#define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk
9642#define EXTI_SWIER1_SWIER18_Pos (18U)
9643#define EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos)
9644#define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk
9645#define EXTI_SWIER1_SWIER19_Pos (19U)
9646#define EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos)
9647#define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk
9648#define EXTI_SWIER1_SWIER20_Pos (20U)
9649#define EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos)
9650#define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk
9651#define EXTI_SWIER1_SWIER21_Pos (21U)
9652#define EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos)
9653#define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk
9655/****************** Bit definition for EXTI_D3PMR1 register ******************/
9656#define EXTI_D3PMR1_MR0_Pos (0U)
9657#define EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos)
9658#define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk
9659#define EXTI_D3PMR1_MR1_Pos (1U)
9660#define EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos)
9661#define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk
9662#define EXTI_D3PMR1_MR2_Pos (2U)
9663#define EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos)
9664#define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk
9665#define EXTI_D3PMR1_MR3_Pos (3U)
9666#define EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos)
9667#define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk
9668#define EXTI_D3PMR1_MR4_Pos (4U)
9669#define EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos)
9670#define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk
9671#define EXTI_D3PMR1_MR5_Pos (5U)
9672#define EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos)
9673#define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk
9674#define EXTI_D3PMR1_MR6_Pos (6U)
9675#define EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos)
9676#define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk
9677#define EXTI_D3PMR1_MR7_Pos (7U)
9678#define EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos)
9679#define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk
9680#define EXTI_D3PMR1_MR8_Pos (8U)
9681#define EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos)
9682#define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk
9683#define EXTI_D3PMR1_MR9_Pos (9U)
9684#define EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos)
9685#define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk
9686#define EXTI_D3PMR1_MR10_Pos (10U)
9687#define EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos)
9688#define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk
9689#define EXTI_D3PMR1_MR11_Pos (11U)
9690#define EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos)
9691#define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk
9692#define EXTI_D3PMR1_MR12_Pos (12U)
9693#define EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos)
9694#define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk
9695#define EXTI_D3PMR1_MR13_Pos (13U)
9696#define EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos)
9697#define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk
9698#define EXTI_D3PMR1_MR14_Pos (14U)
9699#define EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos)
9700#define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk
9701#define EXTI_D3PMR1_MR15_Pos (15U)
9702#define EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos)
9703#define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk
9704#define EXTI_D3PMR1_MR19_Pos (19U)
9705#define EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos)
9706#define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk
9707#define EXTI_D3PMR1_MR20_Pos (20U)
9708#define EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos)
9709#define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk
9710#define EXTI_D3PMR1_MR21_Pos (21U)
9711#define EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos)
9712#define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk
9713#define EXTI_D3PMR1_MR25_Pos (24U)
9714#define EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos)
9715#define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk
9717/******************* Bit definition for EXTI_D3PCR1L register ****************/
9718#define EXTI_D3PCR1L_PCS0_Pos (0U)
9719#define EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos)
9720#define EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk
9721#define EXTI_D3PCR1L_PCS1_Pos (2U)
9722#define EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos)
9723#define EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk
9724#define EXTI_D3PCR1L_PCS2_Pos (4U)
9725#define EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos)
9726#define EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk
9727#define EXTI_D3PCR1L_PCS3_Pos (6U)
9728#define EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos)
9729#define EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk
9730#define EXTI_D3PCR1L_PCS4_Pos (8U)
9731#define EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos)
9732#define EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk
9733#define EXTI_D3PCR1L_PCS5_Pos (10U)
9734#define EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos)
9735#define EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk
9736#define EXTI_D3PCR1L_PCS6_Pos (12U)
9737#define EXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos)
9738#define EXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk
9739#define EXTI_D3PCR1L_PCS7_Pos (14U)
9740#define EXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos)
9741#define EXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk
9742#define EXTI_D3PCR1L_PCS8_Pos (16U)
9743#define EXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos)
9744#define EXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk
9745#define EXTI_D3PCR1L_PCS9_Pos (18U)
9746#define EXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos)
9747#define EXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk
9748#define EXTI_D3PCR1L_PCS10_Pos (20U)
9749#define EXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos)
9750#define EXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk
9751#define EXTI_D3PCR1L_PCS11_Pos (22U)
9752#define EXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos)
9753#define EXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk
9754#define EXTI_D3PCR1L_PCS12_Pos (24U)
9755#define EXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos)
9756#define EXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk
9757#define EXTI_D3PCR1L_PCS13_Pos (26U)
9758#define EXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos)
9759#define EXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk
9760#define EXTI_D3PCR1L_PCS14_Pos (28U)
9761#define EXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos)
9762#define EXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk
9763#define EXTI_D3PCR1L_PCS15_Pos (30U)
9764#define EXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos)
9765#define EXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk
9767/******************* Bit definition for EXTI_D3PCR1H register ****************/
9768#define EXTI_D3PCR1H_PCS19_Pos (6U)
9769#define EXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos)
9770#define EXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk
9771#define EXTI_D3PCR1H_PCS20_Pos (8U)
9772#define EXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos)
9773#define EXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk
9774#define EXTI_D3PCR1H_PCS21_Pos (10U)
9775#define EXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos)
9776#define EXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk
9777#define EXTI_D3PCR1H_PCS25_Pos (18U)
9778#define EXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos)
9779#define EXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk
9781/****************** Bit definition for EXTI_RTSR2 register *******************/
9782#define EXTI_RTSR2_TR_Pos (17U)
9783#define EXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos)
9784#define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk
9785#define EXTI_RTSR2_TR49_Pos (17U)
9786#define EXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos)
9787#define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk
9788#define EXTI_RTSR2_TR51_Pos (19U)
9789#define EXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos)
9790#define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk
9792/****************** Bit definition for EXTI_FTSR2 register *******************/
9793#define EXTI_FTSR2_TR_Pos (17U)
9794#define EXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos)
9795#define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk
9796#define EXTI_FTSR2_TR49_Pos (17U)
9797#define EXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos)
9798#define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk
9799#define EXTI_FTSR2_TR51_Pos (19U)
9800#define EXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos)
9801#define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk
9803/****************** Bit definition for EXTI_SWIER2 register ******************/
9804#define EXTI_SWIER2_SWIER49_Pos (17U)
9805#define EXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos)
9806#define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk
9807#define EXTI_SWIER2_SWIER51_Pos (19U)
9808#define EXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos)
9809#define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk
9811/****************** Bit definition for EXTI_D3PMR2 register ******************/
9812#define EXTI_D3PMR2_MR34_Pos (2U)
9813#define EXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos)
9814#define EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk
9815#define EXTI_D3PMR2_MR35_Pos (3U)
9816#define EXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos)
9817#define EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk
9818#define EXTI_D3PMR2_MR41_Pos (9U)
9819#define EXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos)
9820#define EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk
9821#define EXTI_D3PMR2_MR48_Pos (16U)
9822#define EXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos)
9823#define EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk
9824#define EXTI_D3PMR2_MR49_Pos (17U)
9825#define EXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos)
9826#define EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk
9827#define EXTI_D3PMR2_MR50_Pos (18U)
9828#define EXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos)
9829#define EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk
9830#define EXTI_D3PMR2_MR51_Pos (19U)
9831#define EXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos)
9832#define EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk
9833#define EXTI_D3PMR2_MR52_Pos (20U)
9834#define EXTI_D3PMR2_MR52_Msk (0x1UL << EXTI_D3PMR2_MR52_Pos)
9835#define EXTI_D3PMR2_MR52 EXTI_D3PMR2_MR52_Msk
9836#define EXTI_D3PMR2_MR53_Pos (21U)
9837#define EXTI_D3PMR2_MR53_Msk (0x1UL << EXTI_D3PMR2_MR53_Pos)
9838#define EXTI_D3PMR2_MR53 EXTI_D3PMR2_MR53_Msk
9839/******************* Bit definition for EXTI_D3PCR2L register ****************/
9840#define EXTI_D3PCR2L_PCS34_Pos (4U)
9841#define EXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos)
9842#define EXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk
9843#define EXTI_D3PCR2L_PCS35_Pos (6U)
9844#define EXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos)
9845#define EXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk
9846#define EXTI_D3PCR2L_PCS41_Pos (18U)
9847#define EXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos)
9848#define EXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk
9851/******************* Bit definition for EXTI_D3PCR2H register ****************/
9852#define EXTI_D3PCR2H_PCS48_Pos (0U)
9853#define EXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos)
9854#define EXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk
9855#define EXTI_D3PCR2H_PCS49_Pos (2U)
9856#define EXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos)
9857#define EXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk
9858#define EXTI_D3PCR2H_PCS50_Pos (4U)
9859#define EXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos)
9860#define EXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk
9861#define EXTI_D3PCR2H_PCS51_Pos (6U)
9862#define EXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos)
9863#define EXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk
9864#define EXTI_D3PCR2H_PCS52_Pos (8U)
9865#define EXTI_D3PCR2H_PCS52_Msk (0x3UL << EXTI_D3PCR2H_PCS52_Pos)
9866#define EXTI_D3PCR2H_PCS52 EXTI_D3PCR2H_PCS52_Msk
9867#define EXTI_D3PCR2H_PCS53_Pos (10U)
9868#define EXTI_D3PCR2H_PCS53_Msk (0x3UL << EXTI_D3PCR2H_PCS53_Pos)
9869#define EXTI_D3PCR2H_PCS53 EXTI_D3PCR2H_PCS53_Msk
9870/****************** Bit definition for EXTI_RTSR3 register *******************/
9871#define EXTI_RTSR3_TR_Pos (18U)
9872#define EXTI_RTSR3_TR_Msk (0x1DUL << EXTI_RTSR3_TR_Pos)
9873#define EXTI_RTSR3_TR EXTI_RTSR3_TR_Msk
9874#define EXTI_RTSR3_TR82_Pos (18U)
9875#define EXTI_RTSR3_TR82_Msk (0x1UL << EXTI_RTSR3_TR82_Pos)
9876#define EXTI_RTSR3_TR82 EXTI_RTSR3_TR82_Msk
9877#define EXTI_RTSR3_TR84_Pos (20U)
9878#define EXTI_RTSR3_TR84_Msk (0x1UL << EXTI_RTSR3_TR84_Pos)
9879#define EXTI_RTSR3_TR84 EXTI_RTSR3_TR84_Msk
9880#define EXTI_RTSR3_TR85_Pos (21U)
9881#define EXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos)
9882#define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk
9883#define EXTI_RTSR3_TR86_Pos (22U)
9884#define EXTI_RTSR3_TR86_Msk (0x1UL << EXTI_RTSR3_TR86_Pos)
9885#define EXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk
9887/****************** Bit definition for EXTI_FTSR3 register *******************/
9888#define EXTI_FTSR3_TR_Pos (18U)
9889#define EXTI_FTSR3_TR_Msk (0x1DUL << EXTI_FTSR3_TR_Pos)
9890#define EXTI_FTSR3_TR EXTI_FTSR3_TR_Msk
9891#define EXTI_FTSR3_TR82_Pos (18U)
9892#define EXTI_FTSR3_TR82_Msk (0x1UL << EXTI_FTSR3_TR82_Pos)
9893#define EXTI_FTSR3_TR82 EXTI_FTSR3_TR82_Msk
9894#define EXTI_FTSR3_TR84_Pos (20U)
9895#define EXTI_FTSR3_TR84_Msk (0x1UL << EXTI_FTSR3_TR84_Pos)
9896#define EXTI_FTSR3_TR84 EXTI_FTSR3_TR84_Msk
9897#define EXTI_FTSR3_TR85_Pos (21U)
9898#define EXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos)
9899#define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk
9900#define EXTI_FTSR3_TR86_Pos (22U)
9901#define EXTI_FTSR3_TR86_Msk (0x1UL << EXTI_FTSR3_TR86_Pos)
9902#define EXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk
9904/****************** Bit definition for EXTI_SWIER3 register ******************/
9905#define EXTI_SWIER3_SWI_Pos (18U)
9906#define EXTI_SWIER3_SWI_Msk (0x1DUL << EXTI_SWIER3_SWI_Pos)
9907#define EXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk
9908#define EXTI_SWIER3_SWIER82_Pos (18U)
9909#define EXTI_SWIER3_SWIER82_Msk (0x1UL << EXTI_SWIER3_SWIER82_Pos)
9910#define EXTI_SWIER3_SWIER82 EXTI_SWIER3_SWIER82_Msk
9911#define EXTI_SWIER3_SWIER84_Pos (20U)
9912#define EXTI_SWIER3_SWIER84_Msk (0x1UL << EXTI_SWIER3_SWIER84_Pos)
9913#define EXTI_SWIER3_SWIER84 EXTI_SWIER3_SWIER84_Msk
9914#define EXTI_SWIER3_SWIER85_Pos (21U)
9915#define EXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos)
9916#define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk
9917#define EXTI_SWIER3_SWIER86_Pos (22U)
9918#define EXTI_SWIER3_SWIER86_Msk (0x1UL << EXTI_SWIER3_SWIER86_Pos)
9919#define EXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk
9921/******************* Bit definition for EXTI_IMR1 register *******************/
9922#define EXTI_IMR1_IM_Pos (0U)
9923#define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)
9924#define EXTI_IMR1_IM EXTI_IMR1_IM_Msk
9925#define EXTI_IMR1_IM0_Pos (0U)
9926#define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos)
9927#define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk
9928#define EXTI_IMR1_IM1_Pos (1U)
9929#define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos)
9930#define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk
9931#define EXTI_IMR1_IM2_Pos (2U)
9932#define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos)
9933#define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk
9934#define EXTI_IMR1_IM3_Pos (3U)
9935#define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos)
9936#define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk
9937#define EXTI_IMR1_IM4_Pos (4U)
9938#define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos)
9939#define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk
9940#define EXTI_IMR1_IM5_Pos (5U)
9941#define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos)
9942#define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk
9943#define EXTI_IMR1_IM6_Pos (6U)
9944#define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos)
9945#define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk
9946#define EXTI_IMR1_IM7_Pos (7U)
9947#define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos)
9948#define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk
9949#define EXTI_IMR1_IM8_Pos (8U)
9950#define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos)
9951#define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk
9952#define EXTI_IMR1_IM9_Pos (9U)
9953#define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos)
9954#define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk
9955#define EXTI_IMR1_IM10_Pos (10U)
9956#define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos)
9957#define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk
9958#define EXTI_IMR1_IM11_Pos (11U)
9959#define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos)
9960#define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk
9961#define EXTI_IMR1_IM12_Pos (12U)
9962#define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos)
9963#define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk
9964#define EXTI_IMR1_IM13_Pos (13U)
9965#define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos)
9966#define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk
9967#define EXTI_IMR1_IM14_Pos (14U)
9968#define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos)
9969#define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk
9970#define EXTI_IMR1_IM15_Pos (15U)
9971#define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos)
9972#define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk
9973#define EXTI_IMR1_IM16_Pos (16U)
9974#define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos)
9975#define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk
9976#define EXTI_IMR1_IM17_Pos (17U)
9977#define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos)
9978#define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk
9979#define EXTI_IMR1_IM18_Pos (18U)
9980#define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos)
9981#define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk
9982#define EXTI_IMR1_IM19_Pos (19U)
9983#define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos)
9984#define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk
9985#define EXTI_IMR1_IM20_Pos (20U)
9986#define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos)
9987#define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk
9988#define EXTI_IMR1_IM21_Pos (21U)
9989#define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos)
9990#define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk
9991#define EXTI_IMR1_IM22_Pos (22U)
9992#define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos)
9993#define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk
9994#define EXTI_IMR1_IM23_Pos (23U)
9995#define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos)
9996#define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk
9997#define EXTI_IMR1_IM24_Pos (24U)
9998#define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos)
9999#define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk
10000#define EXTI_IMR1_IM25_Pos (25U)
10001#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos)
10002#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk
10003#define EXTI_IMR1_IM26_Pos (26U)
10004#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos)
10005#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk
10006#define EXTI_IMR1_IM27_Pos (27U)
10007#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos)
10008#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk
10009#define EXTI_IMR1_IM28_Pos (28U)
10010#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos)
10011#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk
10012#define EXTI_IMR1_IM29_Pos (29U)
10013#define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos)
10014#define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk
10015#define EXTI_IMR1_IM30_Pos (30U)
10016#define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos)
10017#define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk
10018#define EXTI_IMR1_IM31_Pos (31U)
10019#define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos)
10020#define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk
10022/******************* Bit definition for EXTI_EMR1 register *******************/
10023#define EXTI_EMR1_EM_Pos (0U)
10024#define EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)
10025#define EXTI_EMR1_EM EXTI_EMR1_EM_Msk
10026#define EXTI_EMR1_EM0_Pos (0U)
10027#define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos)
10028#define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk
10029#define EXTI_EMR1_EM1_Pos (1U)
10030#define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos)
10031#define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk
10032#define EXTI_EMR1_EM2_Pos (2U)
10033#define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos)
10034#define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk
10035#define EXTI_EMR1_EM3_Pos (3U)
10036#define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos)
10037#define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk
10038#define EXTI_EMR1_EM4_Pos (4U)
10039#define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos)
10040#define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk
10041#define EXTI_EMR1_EM5_Pos (5U)
10042#define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos)
10043#define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk
10044#define EXTI_EMR1_EM6_Pos (6U)
10045#define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos)
10046#define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk
10047#define EXTI_EMR1_EM7_Pos (7U)
10048#define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos)
10049#define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk
10050#define EXTI_EMR1_EM8_Pos (8U)
10051#define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos)
10052#define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk
10053#define EXTI_EMR1_EM9_Pos (9U)
10054#define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos)
10055#define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk
10056#define EXTI_EMR1_EM10_Pos (10U)
10057#define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos)
10058#define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk
10059#define EXTI_EMR1_EM11_Pos (11U)
10060#define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos)
10061#define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk
10062#define EXTI_EMR1_EM12_Pos (12U)
10063#define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos)
10064#define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk
10065#define EXTI_EMR1_EM13_Pos (13U)
10066#define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos)
10067#define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk
10068#define EXTI_EMR1_EM14_Pos (14U)
10069#define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos)
10070#define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk
10071#define EXTI_EMR1_EM15_Pos (15U)
10072#define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos)
10073#define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk
10074#define EXTI_EMR1_EM16_Pos (16U)
10075#define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos)
10076#define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk
10077#define EXTI_EMR1_EM17_Pos (17U)
10078#define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos)
10079#define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk
10080#define EXTI_EMR1_EM18_Pos (18U)
10081#define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos)
10082#define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk
10083#define EXTI_EMR1_EM20_Pos (20U)
10084#define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos)
10085#define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk
10086#define EXTI_EMR1_EM21_Pos (21U)
10087#define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos)
10088#define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk
10089#define EXTI_EMR1_EM22_Pos (22U)
10090#define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos)
10091#define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk
10092#define EXTI_EMR1_EM23_Pos (23U)
10093#define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos)
10094#define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk
10095#define EXTI_EMR1_EM24_Pos (24U)
10096#define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos)
10097#define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk
10098#define EXTI_EMR1_EM25_Pos (25U)
10099#define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos)
10100#define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk
10101#define EXTI_EMR1_EM26_Pos (26U)
10102#define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos)
10103#define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk
10104#define EXTI_EMR1_EM27_Pos (27U)
10105#define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos)
10106#define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk
10107#define EXTI_EMR1_EM28_Pos (28U)
10108#define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos)
10109#define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk
10110#define EXTI_EMR1_EM29_Pos (29U)
10111#define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos)
10112#define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk
10113#define EXTI_EMR1_EM30_Pos (30U)
10114#define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos)
10115#define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk
10116#define EXTI_EMR1_EM31_Pos (31U)
10117#define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos)
10118#define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk
10120/******************* Bit definition for EXTI_PR1 register ********************/
10121#define EXTI_PR1_PR_Pos (0U)
10122#define EXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos)
10123#define EXTI_PR1_PR EXTI_PR1_PR_Msk
10124#define EXTI_PR1_PR0_Pos (0U)
10125#define EXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos)
10126#define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk
10127#define EXTI_PR1_PR1_Pos (1U)
10128#define EXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos)
10129#define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk
10130#define EXTI_PR1_PR2_Pos (2U)
10131#define EXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos)
10132#define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk
10133#define EXTI_PR1_PR3_Pos (3U)
10134#define EXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos)
10135#define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk
10136#define EXTI_PR1_PR4_Pos (4U)
10137#define EXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos)
10138#define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk
10139#define EXTI_PR1_PR5_Pos (5U)
10140#define EXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos)
10141#define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk
10142#define EXTI_PR1_PR6_Pos (6U)
10143#define EXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos)
10144#define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk
10145#define EXTI_PR1_PR7_Pos (7U)
10146#define EXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos)
10147#define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk
10148#define EXTI_PR1_PR8_Pos (8U)
10149#define EXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos)
10150#define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk
10151#define EXTI_PR1_PR9_Pos (9U)
10152#define EXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos)
10153#define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk
10154#define EXTI_PR1_PR10_Pos (10U)
10155#define EXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos)
10156#define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk
10157#define EXTI_PR1_PR11_Pos (11U)
10158#define EXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos)
10159#define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk
10160#define EXTI_PR1_PR12_Pos (12U)
10161#define EXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos)
10162#define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk
10163#define EXTI_PR1_PR13_Pos (13U)
10164#define EXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos)
10165#define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk
10166#define EXTI_PR1_PR14_Pos (14U)
10167#define EXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos)
10168#define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk
10169#define EXTI_PR1_PR15_Pos (15U)
10170#define EXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos)
10171#define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk
10172#define EXTI_PR1_PR16_Pos (16U)
10173#define EXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos)
10174#define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk
10175#define EXTI_PR1_PR17_Pos (17U)
10176#define EXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos)
10177#define EXTI_PR1_PR17 EXTI_PR1_PR17_Msk
10178#define EXTI_PR1_PR18_Pos (18U)
10179#define EXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos)
10180#define EXTI_PR1_PR18 EXTI_PR1_PR18_Msk
10181#define EXTI_PR1_PR19_Pos (19U)
10182#define EXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos)
10183#define EXTI_PR1_PR19 EXTI_PR1_PR19_Msk
10184#define EXTI_PR1_PR20_Pos (20U)
10185#define EXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos)
10186#define EXTI_PR1_PR20 EXTI_PR1_PR20_Msk
10187#define EXTI_PR1_PR21_Pos (21U)
10188#define EXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos)
10189#define EXTI_PR1_PR21 EXTI_PR1_PR21_Msk
10191/******************* Bit definition for EXTI_IMR2 register *******************/
10192#define EXTI_IMR2_IM_Pos (0U)
10193#define EXTI_IMR2_IM_Msk (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)
10194#define EXTI_IMR2_IM EXTI_IMR2_IM_Msk
10195#define EXTI_IMR2_IM32_Pos (0U)
10196#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos)
10197#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk
10198#define EXTI_IMR2_IM33_Pos (1U)
10199#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos)
10200#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk
10201#define EXTI_IMR2_IM34_Pos (2U)
10202#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos)
10203#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk
10204#define EXTI_IMR2_IM35_Pos (3U)
10205#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos)
10206#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk
10207#define EXTI_IMR2_IM36_Pos (4U)
10208#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos)
10209#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk
10210#define EXTI_IMR2_IM37_Pos (5U)
10211#define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos)
10212#define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk
10213#define EXTI_IMR2_IM38_Pos (6U)
10214#define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos)
10215#define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk
10216#define EXTI_IMR2_IM39_Pos (7U)
10217#define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos)
10218#define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk
10219#define EXTI_IMR2_IM40_Pos (8U)
10220#define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos)
10221#define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk
10222#define EXTI_IMR2_IM41_Pos (9U)
10223#define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos)
10224#define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk
10225#define EXTI_IMR2_IM42_Pos (10U)
10226#define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos)
10227#define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk
10228#define EXTI_IMR2_IM43_Pos (11U)
10229#define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos)
10230#define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk
10231#define EXTI_IMR2_IM44_Pos (12U)
10232#define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos)
10233#define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk
10234#define EXTI_IMR2_IM46_Pos (14U)
10235#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos)
10236#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk
10237#define EXTI_IMR2_IM47_Pos (15U)
10238#define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos)
10239#define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk
10240#define EXTI_IMR2_IM48_Pos (16U)
10241#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos)
10242#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk
10243#define EXTI_IMR2_IM49_Pos (17U)
10244#define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos)
10245#define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk
10246#define EXTI_IMR2_IM50_Pos (18U)
10247#define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos)
10248#define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk
10249#define EXTI_IMR2_IM51_Pos (19U)
10250#define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos)
10251#define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk
10252#define EXTI_IMR2_IM52_Pos (20U)
10253#define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos)
10254#define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk
10255#define EXTI_IMR2_IM53_Pos (21U)
10256#define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos)
10257#define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk
10258#define EXTI_IMR2_IM54_Pos (22U)
10259#define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos)
10260#define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk
10261#define EXTI_IMR2_IM55_Pos (23U)
10262#define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos)
10263#define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk
10264#define EXTI_IMR2_IM56_Pos (24U)
10265#define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos)
10266#define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk
10267#define EXTI_IMR2_IM57_Pos (25U)
10268#define EXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos)
10269#define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk
10270#define EXTI_IMR2_IM58_Pos (26U)
10271#define EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos)
10272#define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk
10273#define EXTI_IMR2_IM59_Pos (27U)
10274#define EXTI_IMR2_IM59_Msk (0x1UL << EXTI_IMR2_IM59_Pos)
10275#define EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk
10276#define EXTI_IMR2_IM60_Pos (28U)
10277#define EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos)
10278#define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk
10279#define EXTI_IMR2_IM61_Pos (29U)
10280#define EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos)
10281#define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk
10282#define EXTI_IMR2_IM62_Pos (30U)
10283#define EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos)
10284#define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk
10285#define EXTI_IMR2_IM63_Pos (31U)
10286#define EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos)
10287#define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk
10289/******************* Bit definition for EXTI_EMR2 register *******************/
10290#define EXTI_EMR2_EM_Pos (0U)
10291#define EXTI_EMR2_EM_Msk (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)
10292#define EXTI_EMR2_EM EXTI_EMR2_EM_Msk
10293#define EXTI_EMR2_EM32_Pos (0U)
10294#define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos)
10295#define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk
10296#define EXTI_EMR2_EM33_Pos (1U)
10297#define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos)
10298#define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk
10299#define EXTI_EMR2_EM34_Pos (2U)
10300#define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos)
10301#define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk
10302#define EXTI_EMR2_EM35_Pos (3U)
10303#define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos)
10304#define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk
10305#define EXTI_EMR2_EM36_Pos (4U)
10306#define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos)
10307#define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk
10308#define EXTI_EMR2_EM37_Pos (5U)
10309#define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos)
10310#define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk
10311#define EXTI_EMR2_EM38_Pos (6U)
10312#define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos)
10313#define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk
10314#define EXTI_EMR2_EM39_Pos (7U)
10315#define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos)
10316#define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk
10317#define EXTI_EMR2_EM40_Pos (8U)
10318#define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos)
10319#define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk
10320#define EXTI_EMR2_EM41_Pos (9U)
10321#define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos)
10322#define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk
10323#define EXTI_EMR2_EM42_Pos (10U)
10324#define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos)
10325#define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk
10326#define EXTI_EMR2_EM43_Pos (11U)
10327#define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos)
10328#define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk
10329#define EXTI_EMR2_EM44_Pos (12U)
10330#define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos)
10331#define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk
10332#define EXTI_EMR2_EM46_Pos (14U)
10333#define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos)
10334#define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk
10335#define EXTI_EMR2_EM47_Pos (15U)
10336#define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos)
10337#define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk
10338#define EXTI_EMR2_EM48_Pos (16U)
10339#define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos)
10340#define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk
10341#define EXTI_EMR2_EM49_Pos (17U)
10342#define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos)
10343#define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk
10344#define EXTI_EMR2_EM50_Pos (18U)
10345#define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos)
10346#define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk
10347#define EXTI_EMR2_EM51_Pos (19U)
10348#define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos)
10349#define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk
10350#define EXTI_EMR2_EM52_Pos (20U)
10351#define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos)
10352#define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk
10353#define EXTI_EMR2_EM53_Pos (21U)
10354#define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos)
10355#define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk
10356#define EXTI_EMR2_EM54_Pos (22U)
10357#define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos)
10358#define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk
10359#define EXTI_EMR2_EM55_Pos (23U)
10360#define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos)
10361#define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk
10362#define EXTI_EMR2_EM56_Pos (24U)
10363#define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos)
10364#define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk
10365#define EXTI_EMR2_EM57_Pos (25U)
10366#define EXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos)
10367#define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk
10368#define EXTI_EMR2_EM58_Pos (26U)
10369#define EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos)
10370#define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk
10371#define EXTI_EMR2_EM59_Pos (27U)
10372#define EXTI_EMR2_EM59_Msk (0x1UL << EXTI_EMR2_EM59_Pos)
10373#define EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk
10374#define EXTI_EMR2_EM60_Pos (28U)
10375#define EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos)
10376#define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk
10377#define EXTI_EMR2_EM61_Pos (29U)
10378#define EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos)
10379#define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk
10380#define EXTI_EMR2_EM62_Pos (30U)
10381#define EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos)
10382#define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk
10383#define EXTI_EMR2_EM63_Pos (31U)
10384#define EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos)
10385#define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk
10387/******************* Bit definition for EXTI_PR2 register ********************/
10388#define EXTI_PR2_PR_Pos (17U)
10389#define EXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos)
10390#define EXTI_PR2_PR EXTI_PR2_PR_Msk
10391#define EXTI_PR2_PR49_Pos (17U)
10392#define EXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos)
10393#define EXTI_PR2_PR49 EXTI_PR2_PR49_Msk
10394#define EXTI_PR2_PR51_Pos (19U)
10395#define EXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos)
10396#define EXTI_PR2_PR51 EXTI_PR2_PR51_Msk
10398/******************* Bit definition for EXTI_IMR3 register *******************/
10399#define EXTI_IMR3_IM_Pos (0U)
10400#define EXTI_IMR3_IM_Msk (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)
10401#define EXTI_IMR3_IM EXTI_IMR3_IM_Msk
10402#define EXTI_IMR3_IM64_Pos (0U)
10403#define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos)
10404#define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk
10405#define EXTI_IMR3_IM65_Pos (1U)
10406#define EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos)
10407#define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk
10408#define EXTI_IMR3_IM66_Pos (2U)
10409#define EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos)
10410#define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk
10411#define EXTI_IMR3_IM67_Pos (3U)
10412#define EXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos)
10413#define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk
10414#define EXTI_IMR3_IM68_Pos (4U)
10415#define EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos)
10416#define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk
10417#define EXTI_IMR3_IM69_Pos (5U)
10418#define EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos)
10419#define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk
10420#define EXTI_IMR3_IM70_Pos (6U)
10421#define EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos)
10422#define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk
10423#define EXTI_IMR3_IM71_Pos (7U)
10424#define EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos)
10425#define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk
10426#define EXTI_IMR3_IM72_Pos (8U)
10427#define EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos)
10428#define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk
10429#define EXTI_IMR3_IM73_Pos (9U)
10430#define EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos)
10431#define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk
10432#define EXTI_IMR3_IM74_Pos (10U)
10433#define EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos)
10434#define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk
10435#define EXTI_IMR3_IM75_Pos (11U)
10436#define EXTI_IMR3_IM75_Msk (0x1UL << EXTI_IMR3_IM75_Pos)
10437#define EXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk
10438#define EXTI_IMR3_IM76_Pos (12U)
10439#define EXTI_IMR3_IM76_Msk (0x1UL << EXTI_IMR3_IM76_Pos)
10440#define EXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk
10441#define EXTI_IMR3_IM77_Pos (13U)
10442#define EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos)
10443#define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk
10444#define EXTI_IMR3_IM78_Pos (14U)
10445#define EXTI_IMR3_IM78_Msk (0x1UL << EXTI_IMR3_IM78_Pos)
10446#define EXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk
10447#define EXTI_IMR3_IM79_Pos (15U)
10448#define EXTI_IMR3_IM79_Msk (0x1UL << EXTI_IMR3_IM79_Pos)
10449#define EXTI_IMR3_IM79 EXTI_IMR3_IM79_Msk
10450#define EXTI_IMR3_IM80_Pos (16U)
10451#define EXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos)
10452#define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk
10453#define EXTI_IMR3_IM82_Pos (18U)
10454#define EXTI_IMR3_IM82_Msk (0x1UL << EXTI_IMR3_IM82_Pos)
10455#define EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk
10456#define EXTI_IMR3_IM84_Pos (20U)
10457#define EXTI_IMR3_IM84_Msk (0x1UL << EXTI_IMR3_IM84_Pos)
10458#define EXTI_IMR3_IM84 EXTI_IMR3_IM84_Msk
10459#define EXTI_IMR3_IM85_Pos (21U)
10460#define EXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos)
10461#define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk
10462#define EXTI_IMR3_IM86_Pos (22U)
10463#define EXTI_IMR3_IM86_Msk (0x1UL << EXTI_IMR3_IM86_Pos)
10464#define EXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk
10465#define EXTI_IMR3_IM87_Pos (23U)
10466#define EXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos)
10467#define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk
10470/******************* Bit definition for EXTI_EMR3 register *******************/
10471#define EXTI_EMR3_EM_Pos (0U)
10472#define EXTI_EMR3_EM_Msk (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)
10473#define EXTI_EMR3_EM EXTI_EMR3_EM_Msk
10474#define EXTI_EMR3_EM64_Pos (0U)
10475#define EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos)
10476#define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk
10477#define EXTI_EMR3_EM65_Pos (1U)
10478#define EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos)
10479#define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk
10480#define EXTI_EMR3_EM66_Pos (2U)
10481#define EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos)
10482#define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk
10483#define EXTI_EMR3_EM67_Pos (3U)
10484#define EXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos)
10485#define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk
10486#define EXTI_EMR3_EM68_Pos (4U)
10487#define EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos)
10488#define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk
10489#define EXTI_EMR3_EM69_Pos (5U)
10490#define EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos)
10491#define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk
10492#define EXTI_EMR3_EM70_Pos (6U)
10493#define EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos)
10494#define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk
10495#define EXTI_EMR3_EM71_Pos (7U)
10496#define EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos)
10497#define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk
10498#define EXTI_EMR3_EM72_Pos (8U)
10499#define EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos)
10500#define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk
10501#define EXTI_EMR3_EM73_Pos (9U)
10502#define EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos)
10503#define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk
10504#define EXTI_EMR3_EM74_Pos (10U)
10505#define EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos)
10506#define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk
10507#define EXTI_EMR3_EM75_Pos (11U)
10508#define EXTI_EMR3_EM75_Msk (0x1UL << EXTI_EMR3_EM75_Pos)
10509#define EXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk
10510#define EXTI_EMR3_EM76_Pos (12U)
10511#define EXTI_EMR3_EM76_Msk (0x1UL << EXTI_EMR3_EM76_Pos)
10512#define EXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk
10513#define EXTI_EMR3_EM77_Pos (13U)
10514#define EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos)
10515#define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk
10516#define EXTI_EMR3_EM78_Pos (14U)
10517#define EXTI_EMR3_EM78_Msk (0x1UL << EXTI_EMR3_EM78_Pos)
10518#define EXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk
10519#define EXTI_EMR3_EM79_Pos (15U)
10520#define EXTI_EMR3_EM79_Msk (0x1UL << EXTI_EMR3_EM79_Pos)
10521#define EXTI_EMR3_EM79 EXTI_EMR3_EM79_Msk
10522#define EXTI_EMR3_EM80_Pos (16U)
10523#define EXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos)
10524#define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk
10525#define EXTI_EMR3_EM81_Pos (17U)
10526#define EXTI_EMR3_EM81_Msk (0x1UL << EXTI_EMR3_EM81_Pos)
10527#define EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk
10528#define EXTI_EMR3_EM82_Pos (18U)
10529#define EXTI_EMR3_EM82_Msk (0x1UL << EXTI_EMR3_EM82_Pos)
10530#define EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk
10531#define EXTI_EMR3_EM84_Pos (20U)
10532#define EXTI_EMR3_EM84_Msk (0x1UL << EXTI_EMR3_EM84_Pos)
10533#define EXTI_EMR3_EM84 EXTI_EMR3_EM84_Msk
10534#define EXTI_EMR3_EM85_Pos (21U)
10535#define EXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos)
10536#define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk
10537#define EXTI_EMR3_EM86_Pos (22U)
10538#define EXTI_EMR3_EM86_Msk (0x1UL << EXTI_EMR3_EM86_Pos)
10539#define EXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk
10540#define EXTI_EMR3_EM87_Pos (23U)
10541#define EXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos)
10542#define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk
10544/******************* Bit definition for EXTI_PR3 register ********************/
10545#define EXTI_PR3_PR_Pos (18U)
10546#define EXTI_PR3_PR_Msk (0x1DUL << EXTI_PR3_PR_Pos)
10547#define EXTI_PR3_PR EXTI_PR3_PR_Msk
10548#define EXTI_PR3_PR82_Pos (18U)
10549#define EXTI_PR3_PR82_Msk (0x1UL << EXTI_PR3_PR82_Pos)
10550#define EXTI_PR3_PR82 EXTI_PR3_PR82_Msk
10551#define EXTI_PR3_PR84_Pos (20U)
10552#define EXTI_PR3_PR84_Msk (0x1UL << EXTI_PR3_PR84_Pos)
10553#define EXTI_PR3_PR84 EXTI_PR3_PR84_Msk
10554#define EXTI_PR3_PR85_Pos (21U)
10555#define EXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos)
10556#define EXTI_PR3_PR85 EXTI_PR3_PR85_Msk
10557#define EXTI_PR3_PR86_Pos (22U)
10558#define EXTI_PR3_PR86_Msk (0x1UL << EXTI_PR3_PR86_Pos)
10559#define EXTI_PR3_PR86 EXTI_PR3_PR86_Msk
10560/******************************************************************************/
10561/* */
10562/* FLASH */
10563/* */
10564/******************************************************************************/
10565/*
10566* @brief FLASH Global Defines
10567*/
10568#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
10569#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
10570#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
10571 ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
10572 (((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
10573#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
10574#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
10575#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
10576#define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
10577#define DUAL_BANK /* Dual-bank Flash */
10578
10579/******************* Bits definition for FLASH_ACR register **********************/
10580#define FLASH_ACR_LATENCY_Pos (0U)
10581#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos)
10582#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk
10583#define FLASH_ACR_LATENCY_0WS (0x00000000UL)
10584#define FLASH_ACR_LATENCY_1WS (0x00000001UL)
10585#define FLASH_ACR_LATENCY_2WS (0x00000002UL)
10586#define FLASH_ACR_LATENCY_3WS (0x00000003UL)
10587#define FLASH_ACR_LATENCY_4WS (0x00000004UL)
10588#define FLASH_ACR_LATENCY_5WS (0x00000005UL)
10589#define FLASH_ACR_LATENCY_6WS (0x00000006UL)
10590#define FLASH_ACR_LATENCY_7WS (0x00000007UL)
10591
10592#define FLASH_ACR_WRHIGHFREQ_Pos (4U)
10593#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)
10594#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk
10595#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)
10596#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)
10598/* Legacy FLASH Latency defines */
10599#define FLASH_ACR_LATENCY_8WS (0x00000008UL)
10600#define FLASH_ACR_LATENCY_9WS (0x00000009UL)
10601#define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
10602#define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
10603#define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
10604#define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
10605#define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
10606#define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
10607/******************* Bits definition for FLASH_CR register ***********************/
10608#define FLASH_CR_LOCK_Pos (0U)
10609#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)
10610#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
10611#define FLASH_CR_PG_Pos (1U)
10612#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)
10613#define FLASH_CR_PG FLASH_CR_PG_Msk
10614#define FLASH_CR_SER_Pos (2U)
10615#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos)
10616#define FLASH_CR_SER FLASH_CR_SER_Msk
10617#define FLASH_CR_BER_Pos (3U)
10618#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos)
10619#define FLASH_CR_BER FLASH_CR_BER_Msk
10620#define FLASH_CR_PSIZE_Pos (4U)
10621#define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos)
10622#define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk
10623#define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos)
10624#define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos)
10625#define FLASH_CR_FW_Pos (6U)
10626#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos)
10627#define FLASH_CR_FW FLASH_CR_FW_Msk
10628#define FLASH_CR_START_Pos (7U)
10629#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos)
10630#define FLASH_CR_START FLASH_CR_START_Msk
10631#define FLASH_CR_SNB_Pos (8U)
10632#define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos)
10633#define FLASH_CR_SNB FLASH_CR_SNB_Msk
10634#define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos)
10635#define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos)
10636#define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos)
10637#define FLASH_CR_CRC_EN_Pos (15U)
10638#define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos)
10639#define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk
10640#define FLASH_CR_EOPIE_Pos (16U)
10641#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)
10642#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
10643#define FLASH_CR_WRPERRIE_Pos (17U)
10644#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos)
10645#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk
10646#define FLASH_CR_PGSERRIE_Pos (18U)
10647#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos)
10648#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk
10649#define FLASH_CR_STRBERRIE_Pos (19U)
10650#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos)
10651#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk
10652#define FLASH_CR_INCERRIE_Pos (21U)
10653#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos)
10654#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk
10655#define FLASH_CR_OPERRIE_Pos (22U)
10656#define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos)
10657#define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk
10658#define FLASH_CR_RDPERRIE_Pos (23U)
10659#define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos)
10660#define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk
10661#define FLASH_CR_RDSERRIE_Pos (24U)
10662#define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos)
10663#define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk
10664#define FLASH_CR_SNECCERRIE_Pos (25U)
10665#define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos)
10666#define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk
10667#define FLASH_CR_DBECCERRIE_Pos (26U)
10668#define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos)
10669#define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk
10670#define FLASH_CR_CRCENDIE_Pos (27U)
10671#define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos)
10672#define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk
10673#define FLASH_CR_CRCRDERRIE_Pos (28U)
10674#define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos)
10675#define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk
10677/******************* Bits definition for FLASH_SR register ***********************/
10678#define FLASH_SR_BSY_Pos (0U)
10679#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)
10680#define FLASH_SR_BSY FLASH_SR_BSY_Msk
10681#define FLASH_SR_WBNE_Pos (1U)
10682#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos)
10683#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk
10684#define FLASH_SR_QW_Pos (2U)
10685#define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos)
10686#define FLASH_SR_QW FLASH_SR_QW_Msk
10687#define FLASH_SR_CRC_BUSY_Pos (3U)
10688#define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos)
10689#define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk
10690#define FLASH_SR_EOP_Pos (16U)
10691#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)
10692#define FLASH_SR_EOP FLASH_SR_EOP_Msk
10693#define FLASH_SR_WRPERR_Pos (17U)
10694#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos)
10695#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
10696#define FLASH_SR_PGSERR_Pos (18U)
10697#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos)
10698#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk
10699#define FLASH_SR_STRBERR_Pos (19U)
10700#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos)
10701#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk
10702#define FLASH_SR_INCERR_Pos (21U)
10703#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos)
10704#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk
10705#define FLASH_SR_OPERR_Pos (22U)
10706#define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos)
10707#define FLASH_SR_OPERR FLASH_SR_OPERR_Msk
10708#define FLASH_SR_RDPERR_Pos (23U)
10709#define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos)
10710#define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk
10711#define FLASH_SR_RDSERR_Pos (24U)
10712#define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos)
10713#define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk
10714#define FLASH_SR_SNECCERR_Pos (25U)
10715#define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos)
10716#define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk
10717#define FLASH_SR_DBECCERR_Pos (26U)
10718#define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos)
10719#define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk
10720#define FLASH_SR_CRCEND_Pos (27U)
10721#define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos)
10722#define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk
10723#define FLASH_SR_CRCRDERR_Pos (28U)
10724#define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos)
10725#define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk
10727/******************* Bits definition for FLASH_CCR register *******************/
10728#define FLASH_CCR_CLR_EOP_Pos (16U)
10729#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos)
10730#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk
10731#define FLASH_CCR_CLR_WRPERR_Pos (17U)
10732#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos)
10733#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk
10734#define FLASH_CCR_CLR_PGSERR_Pos (18U)
10735#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos)
10736#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk
10737#define FLASH_CCR_CLR_STRBERR_Pos (19U)
10738#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos)
10739#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk
10740#define FLASH_CCR_CLR_INCERR_Pos (21U)
10741#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos)
10742#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk
10743#define FLASH_CCR_CLR_OPERR_Pos (22U)
10744#define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos)
10745#define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk
10746#define FLASH_CCR_CLR_RDPERR_Pos (23U)
10747#define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos)
10748#define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk
10749#define FLASH_CCR_CLR_RDSERR_Pos (24U)
10750#define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos)
10751#define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk
10752#define FLASH_CCR_CLR_SNECCERR_Pos (25U)
10753#define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos)
10754#define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk
10755#define FLASH_CCR_CLR_DBECCERR_Pos (26U)
10756#define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos)
10757#define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk
10758#define FLASH_CCR_CLR_CRCEND_Pos (27U)
10759#define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos)
10760#define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk
10761#define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
10762#define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos)
10763#define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk
10765/******************* Bits definition for FLASH_OPTCR register *******************/
10766#define FLASH_OPTCR_OPTLOCK_Pos (0U)
10767#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)
10768#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk
10769#define FLASH_OPTCR_OPTSTART_Pos (1U)
10770#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos)
10771#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk
10772#define FLASH_OPTCR_MER_Pos (4U)
10773#define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos)
10774#define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk
10775#define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
10776#define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos)
10777#define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk
10778#define FLASH_OPTCR_SWAP_BANK_Pos (31U)
10779#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos)
10780#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk
10782/******************* Bits definition for FLASH_OPTSR register ***************/
10783#define FLASH_OPTSR_OPT_BUSY_Pos (0U)
10784#define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos)
10785#define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk
10786#define FLASH_OPTSR_BOR_LEV_Pos (2U)
10787#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos)
10788#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk
10789#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos)
10790#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos)
10791#define FLASH_OPTSR_IWDG1_SW_Pos (4U)
10792#define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos)
10793#define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk
10794#define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
10795#define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos)
10796#define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk
10797#define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
10798#define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos)
10799#define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk
10800#define FLASH_OPTSR_RDP_Pos (8U)
10801#define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos)
10802#define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk
10803#define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
10804#define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos)
10805#define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk
10806#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
10807#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos)
10808#define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk
10809#define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
10810#define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
10811#define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk
10812#define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
10813#define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos)
10814#define FLASH_OPTSR_SECURITY_Pos (21U)
10815#define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos)
10816#define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk
10817#define FLASH_OPTSR_IO_HSLV_Pos (29U)
10818#define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos)
10819#define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk
10820#define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
10821#define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos)
10822#define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk
10823#define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
10824#define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos)
10825#define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk
10827/******************* Bits definition for FLASH_OPTCCR register *******************/
10828#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
10829#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos)
10830#define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk
10832/******************* Bits definition for FLASH_PRAR register *********************/
10833#define FLASH_PRAR_PROT_AREA_START_Pos (0U)
10834#define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos)
10835#define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk
10836#define FLASH_PRAR_PROT_AREA_END_Pos (16U)
10837#define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos)
10838#define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk
10839#define FLASH_PRAR_DMEP_Pos (31U)
10840#define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos)
10841#define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk
10843/******************* Bits definition for FLASH_SCAR register *********************/
10844#define FLASH_SCAR_SEC_AREA_START_Pos (0U)
10845#define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos)
10846#define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk
10847#define FLASH_SCAR_SEC_AREA_END_Pos (16U)
10848#define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos)
10849#define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk
10850#define FLASH_SCAR_DMES_Pos (31U)
10851#define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos)
10852#define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk
10854/******************* Bits definition for FLASH_WPSN register *********************/
10855#define FLASH_WPSN_WRPSN_Pos (0U)
10856#define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos)
10857#define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk
10859/******************* Bits definition for FLASH_BOOT_CUR register ****************/
10860#define FLASH_BOOT_ADD0_Pos (0U)
10861#define FLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos)
10862#define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk
10863#define FLASH_BOOT_ADD1_Pos (16U)
10864#define FLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos)
10865#define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk
10868/******************* Bits definition for FLASH_CRCCR register ********************/
10869#define FLASH_CRCCR_CRC_SECT_Pos (0U)
10870#define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos)
10871#define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk
10872#define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
10873#define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos)
10874#define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk
10875#define FLASH_CRCCR_ADD_SECT_Pos (9U)
10876#define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos)
10877#define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk
10878#define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
10879#define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos)
10880#define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk
10881#define FLASH_CRCCR_START_CRC_Pos (16U)
10882#define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos)
10883#define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk
10884#define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
10885#define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos)
10886#define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk
10887#define FLASH_CRCCR_CRC_BURST_Pos (20U)
10888#define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos)
10889#define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk
10890#define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos)
10891#define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos)
10892#define FLASH_CRCCR_ALL_BANK_Pos (22U)
10893#define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos)
10894#define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk
10896/******************* Bits definition for FLASH_CRCSADD register ****************/
10897#define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
10898#define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos)
10899#define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk
10901/******************* Bits definition for FLASH_CRCEADD register ****************/
10902#define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
10903#define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos)
10904#define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk
10906/******************* Bits definition for FLASH_CRCDATA register ***************/
10907#define FLASH_CRCDATA_CRC_DATA_Pos (0U)
10908#define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos)
10909#define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk
10911/******************* Bits definition for FLASH_ECC_FA register *******************/
10912#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
10913#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos)
10914#define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk
10916/******************************************************************************/
10917/* */
10918/* Flexible Memory Controller */
10919/* */
10920/******************************************************************************/
10921/****************** Bit definition for FMC_BCR1 register *******************/
10922#define FMC_BCR1_CCLKEN_Pos (20U)
10923#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos)
10924#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk
10925#define FMC_BCR1_WFDIS_Pos (21U)
10926#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos)
10927#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk
10929#define FMC_BCR1_BMAP_Pos (24U)
10930#define FMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos)
10931#define FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk
10932#define FMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos)
10933#define FMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos)
10935#define FMC_BCR1_FMCEN_Pos (31U)
10936#define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos)
10937#define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk
10938/****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
10939#define FMC_BCRx_MBKEN_Pos (0U)
10940#define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos)
10941#define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk
10942#define FMC_BCRx_MUXEN_Pos (1U)
10943#define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos)
10944#define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk
10946#define FMC_BCRx_MTYP_Pos (2U)
10947#define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos)
10948#define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk
10949#define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos)
10950#define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos)
10952#define FMC_BCRx_MWID_Pos (4U)
10953#define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos)
10954#define FMC_BCRx_MWID FMC_BCRx_MWID_Msk
10955#define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos)
10956#define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos)
10958#define FMC_BCRx_FACCEN_Pos (6U)
10959#define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos)
10960#define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk
10961#define FMC_BCRx_BURSTEN_Pos (8U)
10962#define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos)
10963#define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk
10964#define FMC_BCRx_WAITPOL_Pos (9U)
10965#define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos)
10966#define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk
10967#define FMC_BCRx_WAITCFG_Pos (11U)
10968#define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos)
10969#define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk
10970#define FMC_BCRx_WREN_Pos (12U)
10971#define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos)
10972#define FMC_BCRx_WREN FMC_BCRx_WREN_Msk
10973#define FMC_BCRx_WAITEN_Pos (13U)
10974#define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos)
10975#define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk
10976#define FMC_BCRx_EXTMOD_Pos (14U)
10977#define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos)
10978#define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk
10979#define FMC_BCRx_ASYNCWAIT_Pos (15U)
10980#define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)
10981#define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk
10983#define FMC_BCRx_CPSIZE_Pos (16U)
10984#define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos)
10985#define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk
10986#define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos)
10987#define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos)
10988#define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos)
10990#define FMC_BCRx_CBURSTRW_Pos (19U)
10991#define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos)
10992#define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk
10994/****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
10995#define FMC_BTRx_ADDSET_Pos (0U)
10996#define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos)
10997#define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk
10998#define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos)
10999#define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos)
11000#define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos)
11001#define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos)
11003#define FMC_BTRx_ADDHLD_Pos (4U)
11004#define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos)
11005#define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk
11006#define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos)
11007#define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos)
11008#define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos)
11009#define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos)
11011#define FMC_BTRx_DATAST_Pos (8U)
11012#define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos)
11013#define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk
11014#define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos)
11015#define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos)
11016#define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos)
11017#define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos)
11018#define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos)
11019#define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos)
11020#define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos)
11021#define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos)
11023#define FMC_BTRx_BUSTURN_Pos (16U)
11024#define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos)
11025#define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk
11026#define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos)
11027#define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos)
11028#define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos)
11029#define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos)
11031#define FMC_BTRx_CLKDIV_Pos (20U)
11032#define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos)
11033#define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk
11034#define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos)
11035#define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos)
11036#define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos)
11037#define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos)
11039#define FMC_BTRx_DATLAT_Pos (24U)
11040#define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos)
11041#define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk
11042#define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos)
11043#define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos)
11044#define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos)
11045#define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos)
11047#define FMC_BTRx_ACCMOD_Pos (28U)
11048#define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos)
11049#define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk
11050#define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos)
11051#define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos)
11053/****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
11054#define FMC_BWTRx_ADDSET_Pos (0U)
11055#define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos)
11056#define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk
11057#define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos)
11058#define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos)
11059#define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos)
11060#define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos)
11062#define FMC_BWTRx_ADDHLD_Pos (4U)
11063#define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos)
11064#define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk
11065#define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos)
11066#define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos)
11067#define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos)
11068#define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos)
11070#define FMC_BWTRx_DATAST_Pos (8U)
11071#define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos)
11072#define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk
11073#define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos)
11074#define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos)
11075#define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos)
11076#define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos)
11077#define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos)
11078#define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos)
11079#define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos)
11080#define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos)
11082#define FMC_BWTRx_BUSTURN_Pos (16U)
11083#define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos)
11084#define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk
11085#define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos)
11086#define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos)
11087#define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos)
11088#define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos)
11090#define FMC_BWTRx_ACCMOD_Pos (28U)
11091#define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos)
11092#define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk
11093#define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos)
11094#define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos)
11096/****************** Bit definition for FMC_PCR register *******************/
11097#define FMC_PCR_PWAITEN_Pos (1U)
11098#define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos)
11099#define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk
11100#define FMC_PCR_PBKEN_Pos (2U)
11101#define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos)
11102#define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk
11104#define FMC_PCR_PWID_Pos (4U)
11105#define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos)
11106#define FMC_PCR_PWID FMC_PCR_PWID_Msk
11107#define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos)
11108#define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos)
11110#define FMC_PCR_ECCEN_Pos (6U)
11111#define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos)
11112#define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk
11114#define FMC_PCR_TCLR_Pos (9U)
11115#define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos)
11116#define FMC_PCR_TCLR FMC_PCR_TCLR_Msk
11117#define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos)
11118#define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos)
11119#define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos)
11120#define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos)
11122#define FMC_PCR_TAR_Pos (13U)
11123#define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos)
11124#define FMC_PCR_TAR FMC_PCR_TAR_Msk
11125#define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos)
11126#define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos)
11127#define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos)
11128#define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos)
11130#define FMC_PCR_ECCPS_Pos (17U)
11131#define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos)
11132#define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk
11133#define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos)
11134#define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos)
11135#define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos)
11137/******************* Bit definition for FMC_SR register *******************/
11138#define FMC_SR_IRS_Pos (0U)
11139#define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos)
11140#define FMC_SR_IRS FMC_SR_IRS_Msk
11141#define FMC_SR_ILS_Pos (1U)
11142#define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos)
11143#define FMC_SR_ILS FMC_SR_ILS_Msk
11144#define FMC_SR_IFS_Pos (2U)
11145#define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos)
11146#define FMC_SR_IFS FMC_SR_IFS_Msk
11147#define FMC_SR_IREN_Pos (3U)
11148#define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos)
11149#define FMC_SR_IREN FMC_SR_IREN_Msk
11150#define FMC_SR_ILEN_Pos (4U)
11151#define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos)
11152#define FMC_SR_ILEN FMC_SR_ILEN_Msk
11153#define FMC_SR_IFEN_Pos (5U)
11154#define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos)
11155#define FMC_SR_IFEN FMC_SR_IFEN_Msk
11156#define FMC_SR_FEMPT_Pos (6U)
11157#define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos)
11158#define FMC_SR_FEMPT FMC_SR_FEMPT_Msk
11160/****************** Bit definition for FMC_PMEM register ******************/
11161#define FMC_PMEM_MEMSET_Pos (0U)
11162#define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos)
11163#define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk
11164#define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos)
11165#define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos)
11166#define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos)
11167#define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos)
11168#define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos)
11169#define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos)
11170#define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos)
11171#define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos)
11173#define FMC_PMEM_MEMWAIT_Pos (8U)
11174#define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos)
11175#define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk
11176#define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos)
11177#define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos)
11178#define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos)
11179#define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos)
11180#define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos)
11181#define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos)
11182#define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos)
11183#define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos)
11185#define FMC_PMEM_MEMHOLD_Pos (16U)
11186#define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos)
11187#define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk
11188#define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos)
11189#define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos)
11190#define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos)
11191#define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos)
11192#define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos)
11193#define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos)
11194#define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos)
11195#define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos)
11197#define FMC_PMEM_MEMHIZ_Pos (24U)
11198#define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos)
11199#define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk
11200#define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos)
11201#define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos)
11202#define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos)
11203#define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos)
11204#define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos)
11205#define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos)
11206#define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos)
11207#define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos)
11209/****************** Bit definition for FMC_PATT register ******************/
11210#define FMC_PATT_ATTSET_Pos (0U)
11211#define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos)
11212#define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk
11213#define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos)
11214#define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos)
11215#define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos)
11216#define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos)
11217#define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos)
11218#define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos)
11219#define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos)
11220#define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos)
11222#define FMC_PATT_ATTWAIT_Pos (8U)
11223#define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos)
11224#define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk
11225#define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos)
11226#define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos)
11227#define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos)
11228#define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos)
11229#define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos)
11230#define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos)
11231#define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos)
11232#define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos)
11234#define FMC_PATT_ATTHOLD_Pos (16U)
11235#define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos)
11236#define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk
11237#define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos)
11238#define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos)
11239#define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos)
11240#define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos)
11241#define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos)
11242#define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos)
11243#define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos)
11244#define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos)
11246#define FMC_PATT_ATTHIZ_Pos (24U)
11247#define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos)
11248#define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk
11249#define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos)
11250#define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos)
11251#define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos)
11252#define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos)
11253#define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos)
11254#define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos)
11255#define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos)
11256#define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos)
11258/****************** Bit definition for FMC_ECCR3 register ******************/
11259#define FMC_ECCR3_ECC3_Pos (0U)
11260#define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)
11261#define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk
11263/****************** Bit definition for FMC_SDCRx registers (x=1..4) *********/
11264#define FMC_SDCRx_NC_Pos (0U)
11265#define FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos)
11266#define FMC_SDCRx_NC FMC_SDCRx_NC_Msk
11267#define FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos)
11268#define FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos)
11270#define FMC_SDCRx_NR_Pos (2U)
11271#define FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos)
11272#define FMC_SDCRx_NR FMC_SDCRx_NR_Msk
11273#define FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos)
11274#define FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos)
11276#define FMC_SDCRx_MWID_Pos (4U)
11277#define FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos)
11278#define FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk
11279#define FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos)
11280#define FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos)
11282#define FMC_SDCRx_NB_Pos (6U)
11283#define FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos)
11284#define FMC_SDCRx_NB FMC_SDCRx_NB_Msk
11286#define FMC_SDCRx_CAS_Pos (7U)
11287#define FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos)
11288#define FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk
11289#define FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos)
11290#define FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos)
11292#define FMC_SDCRx_WP_Pos (9U)
11293#define FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos)
11294#define FMC_SDCRx_WP FMC_SDCRx_WP_Msk
11296#define FMC_SDCRx_SDCLK_Pos (10U)
11297#define FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos)
11298#define FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk
11299#define FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos)
11300#define FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos)
11302#define FMC_SDCRx_RBURST_Pos (12U)
11303#define FMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos)
11304#define FMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk
11306#define FMC_SDCRx_RPIPE_Pos (13U)
11307#define FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos)
11308#define FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk
11309#define FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos)
11310#define FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos)
11312/****************** Bit definition for FMC_SDTRx(1,2) register ******************/
11313#define FMC_SDTRx_TMRD_Pos (0U)
11314#define FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos)
11315#define FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk
11316#define FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos)
11317#define FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos)
11318#define FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos)
11319#define FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos)
11321#define FMC_SDTRx_TXSR_Pos (4U)
11322#define FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos)
11323#define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk
11324#define FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos)
11325#define FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos)
11326#define FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos)
11327#define FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos)
11329#define FMC_SDTRx_TRAS_Pos (8U)
11330#define FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos)
11331#define FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk
11332#define FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos)
11333#define FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos)
11334#define FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos)
11335#define FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos)
11337#define FMC_SDTRx_TRC_Pos (12U)
11338#define FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos)
11339#define FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk
11340#define FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos)
11341#define FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos)
11342#define FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos)
11344#define FMC_SDTRx_TWR_Pos (16U)
11345#define FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos)
11346#define FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk
11347#define FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos)
11348#define FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos)
11349#define FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos)
11351#define FMC_SDTRx_TRP_Pos (20U)
11352#define FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos)
11353#define FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk
11354#define FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos)
11355#define FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos)
11356#define FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos)
11358#define FMC_SDTRx_TRCD_Pos (24U)
11359#define FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos)
11360#define FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk
11361#define FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos)
11362#define FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos)
11363#define FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos)
11365/****************** Bit definition for FMC_SDCMR register ******************/
11366#define FMC_SDCMR_MODE_Pos (0U)
11367#define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos)
11368#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk
11369#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos)
11370#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos)
11371#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos)
11373#define FMC_SDCMR_CTB2_Pos (3U)
11374#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos)
11375#define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk
11377#define FMC_SDCMR_CTB1_Pos (4U)
11378#define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos)
11379#define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk
11381#define FMC_SDCMR_NRFS_Pos (5U)
11382#define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos)
11383#define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk
11384#define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos)
11385#define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos)
11386#define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos)
11387#define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos)
11389#define FMC_SDCMR_MRD_Pos (9U)
11390#define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos)
11391#define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk
11393/****************** Bit definition for FMC_SDRTR register ******************/
11394#define FMC_SDRTR_CRE_Pos (0U)
11395#define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos)
11396#define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk
11398#define FMC_SDRTR_COUNT_Pos (1U)
11399#define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos)
11400#define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk
11402#define FMC_SDRTR_REIE_Pos (14U)
11403#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos)
11404#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk
11406/****************** Bit definition for FMC_SDSR register ******************/
11407#define FMC_SDSR_RE_Pos (0U)
11408#define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos)
11409#define FMC_SDSR_RE FMC_SDSR_RE_Msk
11411#define FMC_SDSR_MODES1_Pos (1U)
11412#define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos)
11413#define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk
11414#define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos)
11415#define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos)
11417#define FMC_SDSR_MODES2_Pos (3U)
11418#define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos)
11419#define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk
11420#define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos)
11421#define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos)
11423/******************************************************************************/
11424/* */
11425/* General Purpose I/O */
11426/* */
11427/******************************************************************************/
11428/****************** Bits definition for GPIO_MODER register *****************/
11429#define GPIO_MODER_MODE0_Pos (0U)
11430#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos)
11431#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
11432#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos)
11433#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos)
11435#define GPIO_MODER_MODE1_Pos (2U)
11436#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos)
11437#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
11438#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos)
11439#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos)
11441#define GPIO_MODER_MODE2_Pos (4U)
11442#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos)
11443#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
11444#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos)
11445#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos)
11447#define GPIO_MODER_MODE3_Pos (6U)
11448#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos)
11449#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
11450#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos)
11451#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos)
11453#define GPIO_MODER_MODE4_Pos (8U)
11454#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos)
11455#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
11456#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos)
11457#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos)
11459#define GPIO_MODER_MODE5_Pos (10U)
11460#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos)
11461#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
11462#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos)
11463#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos)
11465#define GPIO_MODER_MODE6_Pos (12U)
11466#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos)
11467#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
11468#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos)
11469#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos)
11471#define GPIO_MODER_MODE7_Pos (14U)
11472#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos)
11473#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
11474#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos)
11475#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos)
11477#define GPIO_MODER_MODE8_Pos (16U)
11478#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos)
11479#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
11480#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos)
11481#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos)
11483#define GPIO_MODER_MODE9_Pos (18U)
11484#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos)
11485#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
11486#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos)
11487#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos)
11489#define GPIO_MODER_MODE10_Pos (20U)
11490#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos)
11491#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
11492#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos)
11493#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos)
11495#define GPIO_MODER_MODE11_Pos (22U)
11496#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos)
11497#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
11498#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos)
11499#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos)
11501#define GPIO_MODER_MODE12_Pos (24U)
11502#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos)
11503#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
11504#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos)
11505#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos)
11507#define GPIO_MODER_MODE13_Pos (26U)
11508#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos)
11509#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
11510#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos)
11511#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos)
11513#define GPIO_MODER_MODE14_Pos (28U)
11514#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos)
11515#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
11516#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos)
11517#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos)
11519#define GPIO_MODER_MODE15_Pos (30U)
11520#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos)
11521#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
11522#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos)
11523#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos)
11525/****************** Bits definition for GPIO_OTYPER register ****************/
11526#define GPIO_OTYPER_OT0_Pos (0U)
11527#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos)
11528#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
11529#define GPIO_OTYPER_OT1_Pos (1U)
11530#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos)
11531#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
11532#define GPIO_OTYPER_OT2_Pos (2U)
11533#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos)
11534#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
11535#define GPIO_OTYPER_OT3_Pos (3U)
11536#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos)
11537#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
11538#define GPIO_OTYPER_OT4_Pos (4U)
11539#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos)
11540#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
11541#define GPIO_OTYPER_OT5_Pos (5U)
11542#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos)
11543#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
11544#define GPIO_OTYPER_OT6_Pos (6U)
11545#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos)
11546#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
11547#define GPIO_OTYPER_OT7_Pos (7U)
11548#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos)
11549#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
11550#define GPIO_OTYPER_OT8_Pos (8U)
11551#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos)
11552#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
11553#define GPIO_OTYPER_OT9_Pos (9U)
11554#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos)
11555#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
11556#define GPIO_OTYPER_OT10_Pos (10U)
11557#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos)
11558#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
11559#define GPIO_OTYPER_OT11_Pos (11U)
11560#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos)
11561#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
11562#define GPIO_OTYPER_OT12_Pos (12U)
11563#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos)
11564#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
11565#define GPIO_OTYPER_OT13_Pos (13U)
11566#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos)
11567#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
11568#define GPIO_OTYPER_OT14_Pos (14U)
11569#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos)
11570#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
11571#define GPIO_OTYPER_OT15_Pos (15U)
11572#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos)
11573#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
11574
11575/****************** Bits definition for GPIO_OSPEEDR register ***************/
11576#define GPIO_OSPEEDR_OSPEED0_Pos (0U)
11577#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)
11578#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
11579#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)
11580#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)
11582#define GPIO_OSPEEDR_OSPEED1_Pos (2U)
11583#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)
11584#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
11585#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)
11586#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)
11588#define GPIO_OSPEEDR_OSPEED2_Pos (4U)
11589#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)
11590#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
11591#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)
11592#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)
11594#define GPIO_OSPEEDR_OSPEED3_Pos (6U)
11595#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)
11596#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
11597#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)
11598#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)
11600#define GPIO_OSPEEDR_OSPEED4_Pos (8U)
11601#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)
11602#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
11603#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)
11604#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)
11606#define GPIO_OSPEEDR_OSPEED5_Pos (10U)
11607#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)
11608#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
11609#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)
11610#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)
11612#define GPIO_OSPEEDR_OSPEED6_Pos (12U)
11613#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)
11614#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
11615#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)
11616#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)
11618#define GPIO_OSPEEDR_OSPEED7_Pos (14U)
11619#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)
11620#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
11621#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)
11622#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)
11624#define GPIO_OSPEEDR_OSPEED8_Pos (16U)
11625#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)
11626#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
11627#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)
11628#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)
11630#define GPIO_OSPEEDR_OSPEED9_Pos (18U)
11631#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)
11632#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
11633#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)
11634#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)
11636#define GPIO_OSPEEDR_OSPEED10_Pos (20U)
11637#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)
11638#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
11639#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)
11640#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)
11642#define GPIO_OSPEEDR_OSPEED11_Pos (22U)
11643#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)
11644#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
11645#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)
11646#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)
11648#define GPIO_OSPEEDR_OSPEED12_Pos (24U)
11649#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)
11650#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
11651#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)
11652#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)
11654#define GPIO_OSPEEDR_OSPEED13_Pos (26U)
11655#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)
11656#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
11657#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)
11658#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)
11660#define GPIO_OSPEEDR_OSPEED14_Pos (28U)
11661#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)
11662#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
11663#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)
11664#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)
11666#define GPIO_OSPEEDR_OSPEED15_Pos (30U)
11667#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)
11668#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
11669#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)
11670#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)
11672/****************** Bits definition for GPIO_PUPDR register *****************/
11673#define GPIO_PUPDR_PUPD0_Pos (0U)
11674#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos)
11675#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
11676#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos)
11677#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos)
11679#define GPIO_PUPDR_PUPD1_Pos (2U)
11680#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos)
11681#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
11682#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos)
11683#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos)
11685#define GPIO_PUPDR_PUPD2_Pos (4U)
11686#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos)
11687#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
11688#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos)
11689#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos)
11691#define GPIO_PUPDR_PUPD3_Pos (6U)
11692#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos)
11693#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
11694#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos)
11695#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos)
11697#define GPIO_PUPDR_PUPD4_Pos (8U)
11698#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos)
11699#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
11700#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos)
11701#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos)
11703#define GPIO_PUPDR_PUPD5_Pos (10U)
11704#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos)
11705#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
11706#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos)
11707#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos)
11709#define GPIO_PUPDR_PUPD6_Pos (12U)
11710#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos)
11711#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
11712#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos)
11713#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos)
11715#define GPIO_PUPDR_PUPD7_Pos (14U)
11716#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos)
11717#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
11718#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos)
11719#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos)
11721#define GPIO_PUPDR_PUPD8_Pos (16U)
11722#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos)
11723#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
11724#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos)
11725#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos)
11727#define GPIO_PUPDR_PUPD9_Pos (18U)
11728#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos)
11729#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
11730#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos)
11731#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos)
11733#define GPIO_PUPDR_PUPD10_Pos (20U)
11734#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos)
11735#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
11736#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos)
11737#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos)
11739#define GPIO_PUPDR_PUPD11_Pos (22U)
11740#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos)
11741#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
11742#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos)
11743#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos)
11745#define GPIO_PUPDR_PUPD12_Pos (24U)
11746#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos)
11747#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
11748#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos)
11749#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos)
11751#define GPIO_PUPDR_PUPD13_Pos (26U)
11752#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos)
11753#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
11754#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos)
11755#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos)
11757#define GPIO_PUPDR_PUPD14_Pos (28U)
11758#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos)
11759#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
11760#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos)
11761#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos)
11763#define GPIO_PUPDR_PUPD15_Pos (30U)
11764#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos)
11765#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
11766#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos)
11767#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos)
11769/****************** Bits definition for GPIO_IDR register *******************/
11770#define GPIO_IDR_ID0_Pos (0U)
11771#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos)
11772#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
11773#define GPIO_IDR_ID1_Pos (1U)
11774#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos)
11775#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
11776#define GPIO_IDR_ID2_Pos (2U)
11777#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos)
11778#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
11779#define GPIO_IDR_ID3_Pos (3U)
11780#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos)
11781#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
11782#define GPIO_IDR_ID4_Pos (4U)
11783#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos)
11784#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
11785#define GPIO_IDR_ID5_Pos (5U)
11786#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos)
11787#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
11788#define GPIO_IDR_ID6_Pos (6U)
11789#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos)
11790#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
11791#define GPIO_IDR_ID7_Pos (7U)
11792#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos)
11793#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
11794#define GPIO_IDR_ID8_Pos (8U)
11795#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos)
11796#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
11797#define GPIO_IDR_ID9_Pos (9U)
11798#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos)
11799#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
11800#define GPIO_IDR_ID10_Pos (10U)
11801#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos)
11802#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
11803#define GPIO_IDR_ID11_Pos (11U)
11804#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos)
11805#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
11806#define GPIO_IDR_ID12_Pos (12U)
11807#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos)
11808#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
11809#define GPIO_IDR_ID13_Pos (13U)
11810#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos)
11811#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
11812#define GPIO_IDR_ID14_Pos (14U)
11813#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos)
11814#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
11815#define GPIO_IDR_ID15_Pos (15U)
11816#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos)
11817#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
11818
11819/****************** Bits definition for GPIO_ODR register *******************/
11820#define GPIO_ODR_OD0_Pos (0U)
11821#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos)
11822#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
11823#define GPIO_ODR_OD1_Pos (1U)
11824#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos)
11825#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
11826#define GPIO_ODR_OD2_Pos (2U)
11827#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos)
11828#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
11829#define GPIO_ODR_OD3_Pos (3U)
11830#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos)
11831#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
11832#define GPIO_ODR_OD4_Pos (4U)
11833#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos)
11834#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
11835#define GPIO_ODR_OD5_Pos (5U)
11836#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos)
11837#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
11838#define GPIO_ODR_OD6_Pos (6U)
11839#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos)
11840#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
11841#define GPIO_ODR_OD7_Pos (7U)
11842#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos)
11843#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
11844#define GPIO_ODR_OD8_Pos (8U)
11845#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos)
11846#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
11847#define GPIO_ODR_OD9_Pos (9U)
11848#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos)
11849#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
11850#define GPIO_ODR_OD10_Pos (10U)
11851#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos)
11852#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
11853#define GPIO_ODR_OD11_Pos (11U)
11854#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos)
11855#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
11856#define GPIO_ODR_OD12_Pos (12U)
11857#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos)
11858#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
11859#define GPIO_ODR_OD13_Pos (13U)
11860#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos)
11861#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
11862#define GPIO_ODR_OD14_Pos (14U)
11863#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos)
11864#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
11865#define GPIO_ODR_OD15_Pos (15U)
11866#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos)
11867#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
11868
11869/****************** Bits definition for GPIO_BSRR register ******************/
11870#define GPIO_BSRR_BS0_Pos (0U)
11871#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)
11872#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
11873#define GPIO_BSRR_BS1_Pos (1U)
11874#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)
11875#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
11876#define GPIO_BSRR_BS2_Pos (2U)
11877#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)
11878#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
11879#define GPIO_BSRR_BS3_Pos (3U)
11880#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)
11881#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
11882#define GPIO_BSRR_BS4_Pos (4U)
11883#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)
11884#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
11885#define GPIO_BSRR_BS5_Pos (5U)
11886#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)
11887#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
11888#define GPIO_BSRR_BS6_Pos (6U)
11889#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)
11890#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
11891#define GPIO_BSRR_BS7_Pos (7U)
11892#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)
11893#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
11894#define GPIO_BSRR_BS8_Pos (8U)
11895#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)
11896#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
11897#define GPIO_BSRR_BS9_Pos (9U)
11898#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)
11899#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
11900#define GPIO_BSRR_BS10_Pos (10U)
11901#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)
11902#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
11903#define GPIO_BSRR_BS11_Pos (11U)
11904#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)
11905#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
11906#define GPIO_BSRR_BS12_Pos (12U)
11907#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)
11908#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
11909#define GPIO_BSRR_BS13_Pos (13U)
11910#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)
11911#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
11912#define GPIO_BSRR_BS14_Pos (14U)
11913#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)
11914#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
11915#define GPIO_BSRR_BS15_Pos (15U)
11916#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)
11917#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
11918#define GPIO_BSRR_BR0_Pos (16U)
11919#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)
11920#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
11921#define GPIO_BSRR_BR1_Pos (17U)
11922#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)
11923#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
11924#define GPIO_BSRR_BR2_Pos (18U)
11925#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)
11926#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
11927#define GPIO_BSRR_BR3_Pos (19U)
11928#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)
11929#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
11930#define GPIO_BSRR_BR4_Pos (20U)
11931#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)
11932#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
11933#define GPIO_BSRR_BR5_Pos (21U)
11934#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)
11935#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
11936#define GPIO_BSRR_BR6_Pos (22U)
11937#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)
11938#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
11939#define GPIO_BSRR_BR7_Pos (23U)
11940#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)
11941#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
11942#define GPIO_BSRR_BR8_Pos (24U)
11943#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)
11944#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
11945#define GPIO_BSRR_BR9_Pos (25U)
11946#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)
11947#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
11948#define GPIO_BSRR_BR10_Pos (26U)
11949#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)
11950#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
11951#define GPIO_BSRR_BR11_Pos (27U)
11952#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)
11953#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
11954#define GPIO_BSRR_BR12_Pos (28U)
11955#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)
11956#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
11957#define GPIO_BSRR_BR13_Pos (29U)
11958#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)
11959#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
11960#define GPIO_BSRR_BR14_Pos (30U)
11961#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)
11962#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
11963#define GPIO_BSRR_BR15_Pos (31U)
11964#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)
11965#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
11966
11967/****************** Bit definition for GPIO_LCKR register *********************/
11968#define GPIO_LCKR_LCK0_Pos (0U)
11969#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)
11970#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
11971#define GPIO_LCKR_LCK1_Pos (1U)
11972#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)
11973#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
11974#define GPIO_LCKR_LCK2_Pos (2U)
11975#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)
11976#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
11977#define GPIO_LCKR_LCK3_Pos (3U)
11978#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)
11979#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
11980#define GPIO_LCKR_LCK4_Pos (4U)
11981#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)
11982#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
11983#define GPIO_LCKR_LCK5_Pos (5U)
11984#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)
11985#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
11986#define GPIO_LCKR_LCK6_Pos (6U)
11987#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)
11988#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
11989#define GPIO_LCKR_LCK7_Pos (7U)
11990#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)
11991#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
11992#define GPIO_LCKR_LCK8_Pos (8U)
11993#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)
11994#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
11995#define GPIO_LCKR_LCK9_Pos (9U)
11996#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)
11997#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
11998#define GPIO_LCKR_LCK10_Pos (10U)
11999#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)
12000#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
12001#define GPIO_LCKR_LCK11_Pos (11U)
12002#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)
12003#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
12004#define GPIO_LCKR_LCK12_Pos (12U)
12005#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)
12006#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
12007#define GPIO_LCKR_LCK13_Pos (13U)
12008#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)
12009#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
12010#define GPIO_LCKR_LCK14_Pos (14U)
12011#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)
12012#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
12013#define GPIO_LCKR_LCK15_Pos (15U)
12014#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)
12015#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
12016#define GPIO_LCKR_LCKK_Pos (16U)
12017#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)
12018#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
12019
12020/****************** Bit definition for GPIO_AFRL register ********************/
12021#define GPIO_AFRL_AFSEL0_Pos (0U)
12022#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos)
12023#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
12024#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos)
12025#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos)
12026#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos)
12027#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos)
12028#define GPIO_AFRL_AFSEL1_Pos (4U)
12029#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos)
12030#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
12031#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos)
12032#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos)
12033#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos)
12034#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos)
12035#define GPIO_AFRL_AFSEL2_Pos (8U)
12036#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos)
12037#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
12038#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos)
12039#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos)
12040#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos)
12041#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos)
12042#define GPIO_AFRL_AFSEL3_Pos (12U)
12043#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos)
12044#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
12045#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos)
12046#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos)
12047#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos)
12048#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos)
12049#define GPIO_AFRL_AFSEL4_Pos (16U)
12050#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos)
12051#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
12052#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos)
12053#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos)
12054#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos)
12055#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos)
12056#define GPIO_AFRL_AFSEL5_Pos (20U)
12057#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos)
12058#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
12059#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos)
12060#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos)
12061#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos)
12062#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos)
12063#define GPIO_AFRL_AFSEL6_Pos (24U)
12064#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos)
12065#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
12066#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos)
12067#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos)
12068#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos)
12069#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos)
12070#define GPIO_AFRL_AFSEL7_Pos (28U)
12071#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos)
12072#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
12073#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos)
12074#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos)
12075#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos)
12076#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos)
12078/* Legacy defines */
12079#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
12080#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
12081#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
12082#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
12083#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
12084#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
12085#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
12086#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
12087
12088/****************** Bit definition for GPIO_AFRH register ********************/
12089#define GPIO_AFRH_AFSEL8_Pos (0U)
12090#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos)
12091#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
12092#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos)
12093#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos)
12094#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos)
12095#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos)
12096#define GPIO_AFRH_AFSEL9_Pos (4U)
12097#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos)
12098#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
12099#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos)
12100#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos)
12101#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos)
12102#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos)
12103#define GPIO_AFRH_AFSEL10_Pos (8U)
12104#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos)
12105#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
12106#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos)
12107#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos)
12108#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos)
12109#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos)
12110#define GPIO_AFRH_AFSEL11_Pos (12U)
12111#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos)
12112#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
12113#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos)
12114#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos)
12115#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos)
12116#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos)
12117#define GPIO_AFRH_AFSEL12_Pos (16U)
12118#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos)
12119#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
12120#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos)
12121#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos)
12122#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos)
12123#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos)
12124#define GPIO_AFRH_AFSEL13_Pos (20U)
12125#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos)
12126#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
12127#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos)
12128#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos)
12129#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos)
12130#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos)
12131#define GPIO_AFRH_AFSEL14_Pos (24U)
12132#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos)
12133#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
12134#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos)
12135#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos)
12136#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos)
12137#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos)
12138#define GPIO_AFRH_AFSEL15_Pos (28U)
12139#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos)
12140#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
12141#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos)
12142#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos)
12143#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos)
12144#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos)
12146/* Legacy defines */
12147#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
12148#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
12149#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
12150#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
12151#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
12152#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
12153#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
12154#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
12155
12156/******************************************************************************/
12157/* */
12158/* HSEM HW Semaphore */
12159/* */
12160/******************************************************************************/
12161/******************** Bit definition for HSEM_R register ********************/
12162#define HSEM_R_PROCID_Pos (0U)
12163#define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos)
12164#define HSEM_R_PROCID HSEM_R_PROCID_Msk
12165#define HSEM_R_COREID_Pos (8U)
12166#define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos)
12167#define HSEM_R_COREID HSEM_R_COREID_Msk
12168#define HSEM_R_LOCK_Pos (31U)
12169#define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos)
12170#define HSEM_R_LOCK HSEM_R_LOCK_Msk
12172/******************** Bit definition for HSEM_RLR register ******************/
12173#define HSEM_RLR_PROCID_Pos (0U)
12174#define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos)
12175#define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk
12176#define HSEM_RLR_COREID_Pos (8U)
12177#define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos)
12178#define HSEM_RLR_COREID HSEM_RLR_COREID_Msk
12179#define HSEM_RLR_LOCK_Pos (31U)
12180#define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos)
12181#define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk
12183/******************** Bit definition for HSEM_C1IER register *****************/
12184#define HSEM_C1IER_ISE0_Pos (0U)
12185#define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos)
12186#define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk
12187#define HSEM_C1IER_ISE1_Pos (1U)
12188#define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos)
12189#define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk
12190#define HSEM_C1IER_ISE2_Pos (2U)
12191#define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos)
12192#define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk
12193#define HSEM_C1IER_ISE3_Pos (3U)
12194#define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos)
12195#define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk
12196#define HSEM_C1IER_ISE4_Pos (4U)
12197#define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos)
12198#define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk
12199#define HSEM_C1IER_ISE5_Pos (5U)
12200#define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos)
12201#define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk
12202#define HSEM_C1IER_ISE6_Pos (6U)
12203#define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos)
12204#define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk
12205#define HSEM_C1IER_ISE7_Pos (7U)
12206#define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos)
12207#define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk
12208#define HSEM_C1IER_ISE8_Pos (8U)
12209#define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos)
12210#define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk
12211#define HSEM_C1IER_ISE9_Pos (9U)
12212#define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos)
12213#define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk
12214#define HSEM_C1IER_ISE10_Pos (10U)
12215#define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos)
12216#define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk
12217#define HSEM_C1IER_ISE11_Pos (11U)
12218#define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos)
12219#define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk
12220#define HSEM_C1IER_ISE12_Pos (12U)
12221#define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos)
12222#define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk
12223#define HSEM_C1IER_ISE13_Pos (13U)
12224#define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos)
12225#define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk
12226#define HSEM_C1IER_ISE14_Pos (14U)
12227#define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos)
12228#define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk
12229#define HSEM_C1IER_ISE15_Pos (15U)
12230#define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos)
12231#define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk
12232#define HSEM_C1IER_ISE16_Pos (16U)
12233#define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos)
12234#define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk
12235#define HSEM_C1IER_ISE17_Pos (17U)
12236#define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos)
12237#define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk
12238#define HSEM_C1IER_ISE18_Pos (18U)
12239#define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos)
12240#define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk
12241#define HSEM_C1IER_ISE19_Pos (19U)
12242#define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos)
12243#define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk
12244#define HSEM_C1IER_ISE20_Pos (20U)
12245#define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos)
12246#define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk
12247#define HSEM_C1IER_ISE21_Pos (21U)
12248#define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos)
12249#define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk
12250#define HSEM_C1IER_ISE22_Pos (22U)
12251#define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos)
12252#define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk
12253#define HSEM_C1IER_ISE23_Pos (23U)
12254#define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos)
12255#define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk
12256#define HSEM_C1IER_ISE24_Pos (24U)
12257#define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos)
12258#define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk
12259#define HSEM_C1IER_ISE25_Pos (25U)
12260#define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos)
12261#define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk
12262#define HSEM_C1IER_ISE26_Pos (26U)
12263#define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos)
12264#define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk
12265#define HSEM_C1IER_ISE27_Pos (27U)
12266#define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos)
12267#define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk
12268#define HSEM_C1IER_ISE28_Pos (28U)
12269#define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos)
12270#define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk
12271#define HSEM_C1IER_ISE29_Pos (29U)
12272#define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos)
12273#define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk
12274#define HSEM_C1IER_ISE30_Pos (30U)
12275#define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos)
12276#define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk
12277#define HSEM_C1IER_ISE31_Pos (31U)
12278#define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos)
12279#define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk
12281/******************** Bit definition for HSEM_C1ICR register *****************/
12282#define HSEM_C1ICR_ISC0_Pos (0U)
12283#define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos)
12284#define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk
12285#define HSEM_C1ICR_ISC1_Pos (1U)
12286#define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos)
12287#define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk
12288#define HSEM_C1ICR_ISC2_Pos (2U)
12289#define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos)
12290#define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk
12291#define HSEM_C1ICR_ISC3_Pos (3U)
12292#define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos)
12293#define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk
12294#define HSEM_C1ICR_ISC4_Pos (4U)
12295#define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos)
12296#define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk
12297#define HSEM_C1ICR_ISC5_Pos (5U)
12298#define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos)
12299#define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk
12300#define HSEM_C1ICR_ISC6_Pos (6U)
12301#define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos)
12302#define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk
12303#define HSEM_C1ICR_ISC7_Pos (7U)
12304#define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos)
12305#define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk
12306#define HSEM_C1ICR_ISC8_Pos (8U)
12307#define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos)
12308#define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk
12309#define HSEM_C1ICR_ISC9_Pos (9U)
12310#define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos)
12311#define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk
12312#define HSEM_C1ICR_ISC10_Pos (10U)
12313#define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos)
12314#define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk
12315#define HSEM_C1ICR_ISC11_Pos (11U)
12316#define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos)
12317#define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk
12318#define HSEM_C1ICR_ISC12_Pos (12U)
12319#define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos)
12320#define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk
12321#define HSEM_C1ICR_ISC13_Pos (13U)
12322#define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos)
12323#define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk
12324#define HSEM_C1ICR_ISC14_Pos (14U)
12325#define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos)
12326#define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk
12327#define HSEM_C1ICR_ISC15_Pos (15U)
12328#define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos)
12329#define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk
12330#define HSEM_C1ICR_ISC16_Pos (16U)
12331#define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos)
12332#define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk
12333#define HSEM_C1ICR_ISC17_Pos (17U)
12334#define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos)
12335#define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk
12336#define HSEM_C1ICR_ISC18_Pos (18U)
12337#define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos)
12338#define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk
12339#define HSEM_C1ICR_ISC19_Pos (19U)
12340#define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos)
12341#define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk
12342#define HSEM_C1ICR_ISC20_Pos (20U)
12343#define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos)
12344#define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk
12345#define HSEM_C1ICR_ISC21_Pos (21U)
12346#define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos)
12347#define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk
12348#define HSEM_C1ICR_ISC22_Pos (22U)
12349#define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos)
12350#define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk
12351#define HSEM_C1ICR_ISC23_Pos (23U)
12352#define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos)
12353#define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk
12354#define HSEM_C1ICR_ISC24_Pos (24U)
12355#define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos)
12356#define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk
12357#define HSEM_C1ICR_ISC25_Pos (25U)
12358#define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos)
12359#define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk
12360#define HSEM_C1ICR_ISC26_Pos (26U)
12361#define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos)
12362#define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk
12363#define HSEM_C1ICR_ISC27_Pos (27U)
12364#define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos)
12365#define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk
12366#define HSEM_C1ICR_ISC28_Pos (28U)
12367#define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos)
12368#define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk
12369#define HSEM_C1ICR_ISC29_Pos (29U)
12370#define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos)
12371#define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk
12372#define HSEM_C1ICR_ISC30_Pos (30U)
12373#define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos)
12374#define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk
12375#define HSEM_C1ICR_ISC31_Pos (31U)
12376#define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos)
12377#define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk
12379/******************** Bit definition for HSEM_C1ISR register *****************/
12380#define HSEM_C1ISR_ISF0_Pos (0U)
12381#define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos)
12382#define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk
12383#define HSEM_C1ISR_ISF1_Pos (1U)
12384#define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos)
12385#define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk
12386#define HSEM_C1ISR_ISF2_Pos (2U)
12387#define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos)
12388#define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk
12389#define HSEM_C1ISR_ISF3_Pos (3U)
12390#define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos)
12391#define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk
12392#define HSEM_C1ISR_ISF4_Pos (4U)
12393#define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos)
12394#define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk
12395#define HSEM_C1ISR_ISF5_Pos (5U)
12396#define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos)
12397#define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk
12398#define HSEM_C1ISR_ISF6_Pos (6U)
12399#define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos)
12400#define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk
12401#define HSEM_C1ISR_ISF7_Pos (7U)
12402#define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos)
12403#define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk
12404#define HSEM_C1ISR_ISF8_Pos (8U)
12405#define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos)
12406#define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk
12407#define HSEM_C1ISR_ISF9_Pos (9U)
12408#define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos)
12409#define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk
12410#define HSEM_C1ISR_ISF10_Pos (10U)
12411#define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos)
12412#define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk
12413#define HSEM_C1ISR_ISF11_Pos (11U)
12414#define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos)
12415#define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk
12416#define HSEM_C1ISR_ISF12_Pos (12U)
12417#define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos)
12418#define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk
12419#define HSEM_C1ISR_ISF13_Pos (13U)
12420#define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos)
12421#define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk
12422#define HSEM_C1ISR_ISF14_Pos (14U)
12423#define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos)
12424#define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk
12425#define HSEM_C1ISR_ISF15_Pos (15U)
12426#define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos)
12427#define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk
12428#define HSEM_C1ISR_ISF16_Pos (16U)
12429#define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos)
12430#define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk
12431#define HSEM_C1ISR_ISF17_Pos (17U)
12432#define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos)
12433#define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk
12434#define HSEM_C1ISR_ISF18_Pos (18U)
12435#define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos)
12436#define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk
12437#define HSEM_C1ISR_ISF19_Pos (19U)
12438#define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos)
12439#define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk
12440#define HSEM_C1ISR_ISF20_Pos (20U)
12441#define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos)
12442#define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk
12443#define HSEM_C1ISR_ISF21_Pos (21U)
12444#define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos)
12445#define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk
12446#define HSEM_C1ISR_ISF22_Pos (22U)
12447#define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos)
12448#define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk
12449#define HSEM_C1ISR_ISF23_Pos (23U)
12450#define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos)
12451#define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk
12452#define HSEM_C1ISR_ISF24_Pos (24U)
12453#define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos)
12454#define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk
12455#define HSEM_C1ISR_ISF25_Pos (25U)
12456#define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos)
12457#define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk
12458#define HSEM_C1ISR_ISF26_Pos (26U)
12459#define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos)
12460#define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk
12461#define HSEM_C1ISR_ISF27_Pos (27U)
12462#define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos)
12463#define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk
12464#define HSEM_C1ISR_ISF28_Pos (28U)
12465#define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos)
12466#define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk
12467#define HSEM_C1ISR_ISF29_Pos (29U)
12468#define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos)
12469#define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk
12470#define HSEM_C1ISR_ISF30_Pos (30U)
12471#define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos)
12472#define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk
12473#define HSEM_C1ISR_ISF31_Pos (31U)
12474#define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos)
12475#define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk
12477/******************** Bit definition for HSEM_C1MISR register *****************/
12478#define HSEM_C1MISR_MISF0_Pos (0U)
12479#define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos)
12480#define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk
12481#define HSEM_C1MISR_MISF1_Pos (1U)
12482#define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos)
12483#define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk
12484#define HSEM_C1MISR_MISF2_Pos (2U)
12485#define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos)
12486#define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk
12487#define HSEM_C1MISR_MISF3_Pos (3U)
12488#define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos)
12489#define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk
12490#define HSEM_C1MISR_MISF4_Pos (4U)
12491#define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos)
12492#define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk
12493#define HSEM_C1MISR_MISF5_Pos (5U)
12494#define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos)
12495#define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk
12496#define HSEM_C1MISR_MISF6_Pos (6U)
12497#define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos)
12498#define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk
12499#define HSEM_C1MISR_MISF7_Pos (7U)
12500#define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos)
12501#define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk
12502#define HSEM_C1MISR_MISF8_Pos (8U)
12503#define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos)
12504#define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk
12505#define HSEM_C1MISR_MISF9_Pos (9U)
12506#define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos)
12507#define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk
12508#define HSEM_C1MISR_MISF10_Pos (10U)
12509#define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos)
12510#define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk
12511#define HSEM_C1MISR_MISF11_Pos (11U)
12512#define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos)
12513#define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk
12514#define HSEM_C1MISR_MISF12_Pos (12U)
12515#define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos)
12516#define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk
12517#define HSEM_C1MISR_MISF13_Pos (13U)
12518#define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos)
12519#define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk
12520#define HSEM_C1MISR_MISF14_Pos (14U)
12521#define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos)
12522#define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk
12523#define HSEM_C1MISR_MISF15_Pos (15U)
12524#define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos)
12525#define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk
12526#define HSEM_C1MISR_MISF16_Pos (16U)
12527#define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos)
12528#define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk
12529#define HSEM_C1MISR_MISF17_Pos (17U)
12530#define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos)
12531#define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk
12532#define HSEM_C1MISR_MISF18_Pos (18U)
12533#define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos)
12534#define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk
12535#define HSEM_C1MISR_MISF19_Pos (19U)
12536#define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos)
12537#define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk
12538#define HSEM_C1MISR_MISF20_Pos (20U)
12539#define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos)
12540#define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk
12541#define HSEM_C1MISR_MISF21_Pos (21U)
12542#define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos)
12543#define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk
12544#define HSEM_C1MISR_MISF22_Pos (22U)
12545#define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos)
12546#define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk
12547#define HSEM_C1MISR_MISF23_Pos (23U)
12548#define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos)
12549#define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk
12550#define HSEM_C1MISR_MISF24_Pos (24U)
12551#define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos)
12552#define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk
12553#define HSEM_C1MISR_MISF25_Pos (25U)
12554#define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos)
12555#define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk
12556#define HSEM_C1MISR_MISF26_Pos (26U)
12557#define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos)
12558#define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk
12559#define HSEM_C1MISR_MISF27_Pos (27U)
12560#define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos)
12561#define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk
12562#define HSEM_C1MISR_MISF28_Pos (28U)
12563#define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos)
12564#define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk
12565#define HSEM_C1MISR_MISF29_Pos (29U)
12566#define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos)
12567#define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk
12568#define HSEM_C1MISR_MISF30_Pos (30U)
12569#define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos)
12570#define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk
12571#define HSEM_C1MISR_MISF31_Pos (31U)
12572#define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos)
12573#define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk
12575/******************** Bit definition for HSEM_CR register *****************/
12576#define HSEM_CR_COREID_Pos (8U)
12577#define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos)
12578#define HSEM_CR_COREID HSEM_CR_COREID_Msk
12579#define HSEM_CR_KEY_Pos (16U)
12580#define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos)
12581#define HSEM_CR_KEY HSEM_CR_KEY_Msk
12583/******************** Bit definition for HSEM_KEYR register *****************/
12584#define HSEM_KEYR_KEY_Pos (16U)
12585#define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos)
12586#define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk
12588/******************************************************************************/
12589/* */
12590/* Inter-integrated Circuit Interface (I2C) */
12591/* */
12592/******************************************************************************/
12593/******************* Bit definition for I2C_CR1 register *******************/
12594#define I2C_CR1_PE_Pos (0U)
12595#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)
12596#define I2C_CR1_PE I2C_CR1_PE_Msk
12597#define I2C_CR1_TXIE_Pos (1U)
12598#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos)
12599#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk
12600#define I2C_CR1_RXIE_Pos (2U)
12601#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos)
12602#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk
12603#define I2C_CR1_ADDRIE_Pos (3U)
12604#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos)
12605#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk
12606#define I2C_CR1_NACKIE_Pos (4U)
12607#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos)
12608#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk
12609#define I2C_CR1_STOPIE_Pos (5U)
12610#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos)
12611#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk
12612#define I2C_CR1_TCIE_Pos (6U)
12613#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos)
12614#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk
12615#define I2C_CR1_ERRIE_Pos (7U)
12616#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos)
12617#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk
12618#define I2C_CR1_DNF_Pos (8U)
12619#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos)
12620#define I2C_CR1_DNF I2C_CR1_DNF_Msk
12621#define I2C_CR1_ANFOFF_Pos (12U)
12622#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos)
12623#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk
12624#define I2C_CR1_TXDMAEN_Pos (14U)
12625#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos)
12626#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk
12627#define I2C_CR1_RXDMAEN_Pos (15U)
12628#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos)
12629#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk
12630#define I2C_CR1_SBC_Pos (16U)
12631#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos)
12632#define I2C_CR1_SBC I2C_CR1_SBC_Msk
12633#define I2C_CR1_NOSTRETCH_Pos (17U)
12634#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)
12635#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk
12636#define I2C_CR1_WUPEN_Pos (18U)
12637#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos)
12638#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk
12639#define I2C_CR1_GCEN_Pos (19U)
12640#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos)
12641#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk
12642#define I2C_CR1_SMBHEN_Pos (20U)
12643#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos)
12644#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk
12645#define I2C_CR1_SMBDEN_Pos (21U)
12646#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos)
12647#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk
12648#define I2C_CR1_ALERTEN_Pos (22U)
12649#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos)
12650#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk
12651#define I2C_CR1_PECEN_Pos (23U)
12652#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos)
12653#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk
12655/****************** Bit definition for I2C_CR2 register ********************/
12656#define I2C_CR2_SADD_Pos (0U)
12657#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos)
12658#define I2C_CR2_SADD I2C_CR2_SADD_Msk
12659#define I2C_CR2_RD_WRN_Pos (10U)
12660#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos)
12661#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk
12662#define I2C_CR2_ADD10_Pos (11U)
12663#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos)
12664#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk
12665#define I2C_CR2_HEAD10R_Pos (12U)
12666#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos)
12667#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk
12668#define I2C_CR2_START_Pos (13U)
12669#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos)
12670#define I2C_CR2_START I2C_CR2_START_Msk
12671#define I2C_CR2_STOP_Pos (14U)
12672#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos)
12673#define I2C_CR2_STOP I2C_CR2_STOP_Msk
12674#define I2C_CR2_NACK_Pos (15U)
12675#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos)
12676#define I2C_CR2_NACK I2C_CR2_NACK_Msk
12677#define I2C_CR2_NBYTES_Pos (16U)
12678#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos)
12679#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk
12680#define I2C_CR2_RELOAD_Pos (24U)
12681#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos)
12682#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk
12683#define I2C_CR2_AUTOEND_Pos (25U)
12684#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos)
12685#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk
12686#define I2C_CR2_PECBYTE_Pos (26U)
12687#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos)
12688#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk
12690/******************* Bit definition for I2C_OAR1 register ******************/
12691#define I2C_OAR1_OA1_Pos (0U)
12692#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos)
12693#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk
12694#define I2C_OAR1_OA1MODE_Pos (10U)
12695#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos)
12696#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk
12697#define I2C_OAR1_OA1EN_Pos (15U)
12698#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos)
12699#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk
12701/******************* Bit definition for I2C_OAR2 register ******************/
12702#define I2C_OAR2_OA2_Pos (1U)
12703#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos)
12704#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk
12705#define I2C_OAR2_OA2MSK_Pos (8U)
12706#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos)
12707#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk
12708#define I2C_OAR2_OA2NOMASK 0x00000000UL
12709#define I2C_OAR2_OA2MASK01_Pos (8U)
12710#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos)
12711#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk
12712#define I2C_OAR2_OA2MASK02_Pos (9U)
12713#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos)
12714#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk
12715#define I2C_OAR2_OA2MASK03_Pos (8U)
12716#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos)
12717#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk
12718#define I2C_OAR2_OA2MASK04_Pos (10U)
12719#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos)
12720#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk
12721#define I2C_OAR2_OA2MASK05_Pos (8U)
12722#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos)
12723#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk
12724#define I2C_OAR2_OA2MASK06_Pos (9U)
12725#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos)
12726#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk
12727#define I2C_OAR2_OA2MASK07_Pos (8U)
12728#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos)
12729#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk
12730#define I2C_OAR2_OA2EN_Pos (15U)
12731#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos)
12732#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk
12734/******************* Bit definition for I2C_TIMINGR register *******************/
12735#define I2C_TIMINGR_SCLL_Pos (0U)
12736#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos)
12737#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk
12738#define I2C_TIMINGR_SCLH_Pos (8U)
12739#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos)
12740#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk
12741#define I2C_TIMINGR_SDADEL_Pos (16U)
12742#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos)
12743#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk
12744#define I2C_TIMINGR_SCLDEL_Pos (20U)
12745#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos)
12746#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk
12747#define I2C_TIMINGR_PRESC_Pos (28U)
12748#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos)
12749#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk
12751/******************* Bit definition for I2C_TIMEOUTR register *******************/
12752#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
12753#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)
12754#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk
12755#define I2C_TIMEOUTR_TIDLE_Pos (12U)
12756#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)
12757#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk
12758#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
12759#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)
12760#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk
12761#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
12762#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)
12763#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk
12764#define I2C_TIMEOUTR_TEXTEN_Pos (31U)
12765#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)
12766#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk
12768/****************** Bit definition for I2C_ISR register *********************/
12769#define I2C_ISR_TXE_Pos (0U)
12770#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos)
12771#define I2C_ISR_TXE I2C_ISR_TXE_Msk
12772#define I2C_ISR_TXIS_Pos (1U)
12773#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos)
12774#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk
12775#define I2C_ISR_RXNE_Pos (2U)
12776#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos)
12777#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk
12778#define I2C_ISR_ADDR_Pos (3U)
12779#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos)
12780#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk
12781#define I2C_ISR_NACKF_Pos (4U)
12782#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos)
12783#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk
12784#define I2C_ISR_STOPF_Pos (5U)
12785#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos)
12786#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk
12787#define I2C_ISR_TC_Pos (6U)
12788#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos)
12789#define I2C_ISR_TC I2C_ISR_TC_Msk
12790#define I2C_ISR_TCR_Pos (7U)
12791#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos)
12792#define I2C_ISR_TCR I2C_ISR_TCR_Msk
12793#define I2C_ISR_BERR_Pos (8U)
12794#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos)
12795#define I2C_ISR_BERR I2C_ISR_BERR_Msk
12796#define I2C_ISR_ARLO_Pos (9U)
12797#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos)
12798#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk
12799#define I2C_ISR_OVR_Pos (10U)
12800#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos)
12801#define I2C_ISR_OVR I2C_ISR_OVR_Msk
12802#define I2C_ISR_PECERR_Pos (11U)
12803#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos)
12804#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk
12805#define I2C_ISR_TIMEOUT_Pos (12U)
12806#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos)
12807#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk
12808#define I2C_ISR_ALERT_Pos (13U)
12809#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos)
12810#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk
12811#define I2C_ISR_BUSY_Pos (15U)
12812#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos)
12813#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk
12814#define I2C_ISR_DIR_Pos (16U)
12815#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos)
12816#define I2C_ISR_DIR I2C_ISR_DIR_Msk
12817#define I2C_ISR_ADDCODE_Pos (17U)
12818#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos)
12819#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk
12821/****************** Bit definition for I2C_ICR register *********************/
12822#define I2C_ICR_ADDRCF_Pos (3U)
12823#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos)
12824#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk
12825#define I2C_ICR_NACKCF_Pos (4U)
12826#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos)
12827#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk
12828#define I2C_ICR_STOPCF_Pos (5U)
12829#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos)
12830#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk
12831#define I2C_ICR_BERRCF_Pos (8U)
12832#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos)
12833#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk
12834#define I2C_ICR_ARLOCF_Pos (9U)
12835#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos)
12836#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk
12837#define I2C_ICR_OVRCF_Pos (10U)
12838#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos)
12839#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk
12840#define I2C_ICR_PECCF_Pos (11U)
12841#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos)
12842#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk
12843#define I2C_ICR_TIMOUTCF_Pos (12U)
12844#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos)
12845#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk
12846#define I2C_ICR_ALERTCF_Pos (13U)
12847#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos)
12848#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk
12850/****************** Bit definition for I2C_PECR register *********************/
12851#define I2C_PECR_PEC_Pos (0U)
12852#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos)
12853#define I2C_PECR_PEC I2C_PECR_PEC_Msk
12855/****************** Bit definition for I2C_RXDR register *********************/
12856#define I2C_RXDR_RXDATA_Pos (0U)
12857#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos)
12858#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk
12860/****************** Bit definition for I2C_TXDR register *********************/
12861#define I2C_TXDR_TXDATA_Pos (0U)
12862#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos)
12863#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk
12865/******************************************************************************/
12866/* */
12867/* Independent WATCHDOG */
12868/* */
12869/******************************************************************************/
12870/******************* Bit definition for IWDG_KR register ********************/
12871#define IWDG_KR_KEY_Pos (0U)
12872#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)
12873#define IWDG_KR_KEY IWDG_KR_KEY_Msk
12875/******************* Bit definition for IWDG_PR register ********************/
12876#define IWDG_PR_PR_Pos (0U)
12877#define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)
12878#define IWDG_PR_PR IWDG_PR_PR_Msk
12879#define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)
12880#define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)
12881#define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)
12883/******************* Bit definition for IWDG_RLR register *******************/
12884#define IWDG_RLR_RL_Pos (0U)
12885#define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)
12886#define IWDG_RLR_RL IWDG_RLR_RL_Msk
12888/******************* Bit definition for IWDG_SR register ********************/
12889#define IWDG_SR_PVU_Pos (0U)
12890#define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)
12891#define IWDG_SR_PVU IWDG_SR_PVU_Msk
12892#define IWDG_SR_RVU_Pos (1U)
12893#define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)
12894#define IWDG_SR_RVU IWDG_SR_RVU_Msk
12895#define IWDG_SR_WVU_Pos (2U)
12896#define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos)
12897#define IWDG_SR_WVU IWDG_SR_WVU_Msk
12899/******************* Bit definition for IWDG_KR register ********************/
12900#define IWDG_WINR_WIN_Pos (0U)
12901#define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos)
12902#define IWDG_WINR_WIN IWDG_WINR_WIN_Msk
12904/******************************************************************************/
12905/* */
12906/* MDMA */
12907/* */
12908/******************************************************************************/
12909/******************** Bit definition for MDMA_GISR0 register ****************/
12910#define MDMA_GISR0_GIF0_Pos (0U)
12911#define MDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos)
12912#define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk
12913#define MDMA_GISR0_GIF1_Pos (1U)
12914#define MDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos)
12915#define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk
12916#define MDMA_GISR0_GIF2_Pos (2U)
12917#define MDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos)
12918#define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk
12919#define MDMA_GISR0_GIF3_Pos (3U)
12920#define MDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos)
12921#define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk
12922#define MDMA_GISR0_GIF4_Pos (4U)
12923#define MDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos)
12924#define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk
12925#define MDMA_GISR0_GIF5_Pos (5U)
12926#define MDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos)
12927#define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk
12928#define MDMA_GISR0_GIF6_Pos (6U)
12929#define MDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos)
12930#define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk
12931#define MDMA_GISR0_GIF7_Pos (7U)
12932#define MDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos)
12933#define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk
12934#define MDMA_GISR0_GIF8_Pos (8U)
12935#define MDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos)
12936#define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk
12937#define MDMA_GISR0_GIF9_Pos (9U)
12938#define MDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos)
12939#define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk
12940#define MDMA_GISR0_GIF10_Pos (10U)
12941#define MDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos)
12942#define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk
12943#define MDMA_GISR0_GIF11_Pos (11U)
12944#define MDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos)
12945#define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk
12946#define MDMA_GISR0_GIF12_Pos (12U)
12947#define MDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos)
12948#define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk
12949#define MDMA_GISR0_GIF13_Pos (13U)
12950#define MDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos)
12951#define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk
12952#define MDMA_GISR0_GIF14_Pos (14U)
12953#define MDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos)
12954#define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk
12955#define MDMA_GISR0_GIF15_Pos (15U)
12956#define MDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos)
12957#define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk
12959/******************** Bit definition for MDMA_CxISR register ****************/
12960#define MDMA_CISR_TEIF_Pos (0U)
12961#define MDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos)
12962#define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk
12963#define MDMA_CISR_CTCIF_Pos (1U)
12964#define MDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos)
12965#define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk
12966#define MDMA_CISR_BRTIF_Pos (2U)
12967#define MDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos)
12968#define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk
12969#define MDMA_CISR_BTIF_Pos (3U)
12970#define MDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos)
12971#define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk
12972#define MDMA_CISR_TCIF_Pos (4U)
12973#define MDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos)
12974#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk
12975#define MDMA_CISR_CRQA_Pos (16U)
12976#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos)
12977#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk
12979/******************** Bit definition for MDMA_CxIFCR register ****************/
12980#define MDMA_CIFCR_CTEIF_Pos (0U)
12981#define MDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos)
12982#define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk
12983#define MDMA_CIFCR_CCTCIF_Pos (1U)
12984#define MDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos)
12985#define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk
12986#define MDMA_CIFCR_CBRTIF_Pos (2U)
12987#define MDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos)
12988#define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk
12989#define MDMA_CIFCR_CBTIF_Pos (3U)
12990#define MDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos)
12991#define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk
12992#define MDMA_CIFCR_CLTCIF_Pos (4U)
12993#define MDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos)
12994#define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk
12996/******************** Bit definition for MDMA_CxESR register ****************/
12997#define MDMA_CESR_TEA_Pos (0U)
12998#define MDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos)
12999#define MDMA_CESR_TEA MDMA_CESR_TEA_Msk
13000#define MDMA_CESR_TED_Pos (7U)
13001#define MDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos)
13002#define MDMA_CESR_TED MDMA_CESR_TED_Msk
13003#define MDMA_CESR_TELD_Pos (8U)
13004#define MDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos)
13005#define MDMA_CESR_TELD MDMA_CESR_TELD_Msk
13006#define MDMA_CESR_TEMD_Pos (9U)
13007#define MDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos)
13008#define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk
13009#define MDMA_CESR_ASE_Pos (10U)
13010#define MDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos)
13011#define MDMA_CESR_ASE MDMA_CESR_ASE_Msk
13012#define MDMA_CESR_BSE_Pos (11U)
13013#define MDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos)
13014#define MDMA_CESR_BSE MDMA_CESR_BSE_Msk
13016/******************** Bit definition for MDMA_CxCR register ****************/
13017#define MDMA_CCR_EN_Pos (0U)
13018#define MDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos)
13019#define MDMA_CCR_EN MDMA_CCR_EN_Msk
13020#define MDMA_CCR_TEIE_Pos (1U)
13021#define MDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos)
13022#define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk
13023#define MDMA_CCR_CTCIE_Pos (2U)
13024#define MDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos)
13025#define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk
13026#define MDMA_CCR_BRTIE_Pos (3U)
13027#define MDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos)
13028#define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk
13029#define MDMA_CCR_BTIE_Pos (4U)
13030#define MDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos)
13031#define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk
13032#define MDMA_CCR_TCIE_Pos (5U)
13033#define MDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos)
13034#define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk
13035#define MDMA_CCR_PL_Pos (6U)
13036#define MDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos)
13037#define MDMA_CCR_PL MDMA_CCR_PL_Msk
13038#define MDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos)
13039#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos)
13040#define MDMA_CCR_BEX_Pos (12U)
13041#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos)
13042#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk
13043#define MDMA_CCR_HEX_Pos (13U)
13044#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos)
13045#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk
13046#define MDMA_CCR_WEX_Pos (14U)
13047#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos)
13048#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk
13049#define MDMA_CCR_SWRQ_Pos (16U)
13050#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos)
13051#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk
13053/******************** Bit definition for MDMA_CxTCR register ****************/
13054#define MDMA_CTCR_SINC_Pos (0U)
13055#define MDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos)
13056#define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk
13057#define MDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos)
13058#define MDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos)
13059#define MDMA_CTCR_DINC_Pos (2U)
13060#define MDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos)
13061#define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk
13062#define MDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos)
13063#define MDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos)
13064#define MDMA_CTCR_SSIZE_Pos (4U)
13065#define MDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos)
13066#define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk
13067#define MDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos)
13068#define MDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos)
13069#define MDMA_CTCR_DSIZE_Pos (6U)
13070#define MDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos)
13071#define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk
13072#define MDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos)
13073#define MDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos)
13074#define MDMA_CTCR_SINCOS_Pos (8U)
13075#define MDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos)
13076#define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk
13077#define MDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos)
13078#define MDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos)
13079#define MDMA_CTCR_DINCOS_Pos (10U)
13080#define MDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos)
13081#define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk
13082#define MDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos)
13083#define MDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos)
13084#define MDMA_CTCR_SBURST_Pos (12U)
13085#define MDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos)
13086#define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk
13087#define MDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos)
13088#define MDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos)
13089#define MDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos)
13090#define MDMA_CTCR_DBURST_Pos (15U)
13091#define MDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos)
13092#define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk
13093#define MDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos)
13094#define MDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos)
13095#define MDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos)
13096#define MDMA_CTCR_TLEN_Pos (18U)
13097#define MDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos)
13098#define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk
13099#define MDMA_CTCR_PKE_Pos (25U)
13100#define MDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos)
13101#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk
13102#define MDMA_CTCR_PAM_Pos (26U)
13103#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos)
13104#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk
13105#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos)
13106#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos)
13107#define MDMA_CTCR_TRGM_Pos (28U)
13108#define MDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos)
13109#define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk
13110#define MDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos)
13111#define MDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos)
13112#define MDMA_CTCR_SWRM_Pos (30U)
13113#define MDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos)
13114#define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk
13115#define MDMA_CTCR_BWM_Pos (31U)
13116#define MDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos)
13117#define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk
13119/******************** Bit definition for MDMA_CxBNDTR register ****************/
13120#define MDMA_CBNDTR_BNDT_Pos (0U)
13121#define MDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)
13122#define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk
13123#define MDMA_CBNDTR_BRSUM_Pos (18U)
13124#define MDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos)
13125#define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk
13126#define MDMA_CBNDTR_BRDUM_Pos (19U)
13127#define MDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos)
13128#define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk
13129#define MDMA_CBNDTR_BRC_Pos (20U)
13130#define MDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos)
13131#define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk
13133/******************** Bit definition for MDMA_CxSAR register ****************/
13134#define MDMA_CSAR_SAR_Pos (0U)
13135#define MDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)
13136#define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk
13138/******************** Bit definition for MDMA_CxDAR register ****************/
13139#define MDMA_CDAR_DAR_Pos (0U)
13140#define MDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)
13141#define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk
13143/******************** Bit definition for MDMA_CxBRUR ************************/
13144#define MDMA_CBRUR_SUV_Pos (0U)
13145#define MDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos)
13146#define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk
13147#define MDMA_CBRUR_DUV_Pos (16U)
13148#define MDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos)
13149#define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk
13151/******************** Bit definition for MDMA_CxLAR *************************/
13152#define MDMA_CLAR_LAR_Pos (0U)
13153#define MDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)
13154#define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk
13156/******************** Bit definition for MDMA_CxTBR) ************************/
13157#define MDMA_CTBR_TSEL_Pos (0U)
13158#define MDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos)
13159#define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk
13160#define MDMA_CTBR_SBUS_Pos (16U)
13161#define MDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos)
13162#define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk
13163#define MDMA_CTBR_DBUS_Pos (17U)
13164#define MDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos)
13165#define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk
13167/******************** Bit definition for MDMA_CxMAR) ************************/
13168#define MDMA_CMAR_MAR_Pos (0U)
13169#define MDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)
13170#define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk
13172/******************** Bit definition for MDMA_CxMDR) ************************/
13173#define MDMA_CMDR_MDR_Pos (0U)
13174#define MDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)
13175#define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk
13177/******************************************************************************/
13178/* */
13179/* Operational Amplifier (OPAMP) */
13180/* */
13181/******************************************************************************/
13182/********************* Bit definition for OPAMPx_CSR register ***************/
13183#define OPAMP_CSR_OPAMPxEN_Pos (0U)
13184#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)
13185#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk
13186#define OPAMP_CSR_FORCEVP_Pos (1U)
13187#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos)
13188#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk
13190#define OPAMP_CSR_VPSEL_Pos (2U)
13191#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos)
13192#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk
13193#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos)
13194#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos)
13196#define OPAMP_CSR_VMSEL_Pos (5U)
13197#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos)
13198#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk
13199#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos)
13200#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos)
13202#define OPAMP_CSR_OPAHSM_Pos (8U)
13203#define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos)
13204#define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk
13205#define OPAMP_CSR_CALON_Pos (11U)
13206#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos)
13207#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk
13209#define OPAMP_CSR_CALSEL_Pos (12U)
13210#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos)
13211#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk
13212#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos)
13213#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos)
13215#define OPAMP_CSR_PGGAIN_Pos (14U)
13216#define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos)
13217#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk
13218#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos)
13219#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos)
13220#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos)
13221#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos)
13223#define OPAMP_CSR_USERTRIM_Pos (18U)
13224#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos)
13225#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk
13226#define OPAMP_CSR_TSTREF_Pos (29U)
13227#define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos)
13228#define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk
13229#define OPAMP_CSR_CALOUT_Pos (30U)
13230#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos)
13231#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk
13233/********************* Bit definition for OPAMP1_CSR register ***************/
13234#define OPAMP1_CSR_OPAEN_Pos (0U)
13235#define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos)
13236#define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk
13237#define OPAMP1_CSR_FORCEVP_Pos (1U)
13238#define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos)
13239#define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk
13241#define OPAMP1_CSR_VPSEL_Pos (2U)
13242#define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos)
13243#define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk
13244#define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos)
13245#define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos)
13247#define OPAMP1_CSR_VMSEL_Pos (5U)
13248#define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos)
13249#define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk
13250#define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos)
13251#define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos)
13253#define OPAMP1_CSR_OPAHSM_Pos (8U)
13254#define OPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos)
13255#define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk
13256#define OPAMP1_CSR_CALON_Pos (11U)
13257#define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos)
13258#define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk
13260#define OPAMP1_CSR_CALSEL_Pos (12U)
13261#define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos)
13262#define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk
13263#define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos)
13264#define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos)
13266#define OPAMP1_CSR_PGGAIN_Pos (14U)
13267#define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos)
13268#define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk
13269#define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos)
13270#define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos)
13271#define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos)
13272#define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos)
13274#define OPAMP1_CSR_USERTRIM_Pos (18U)
13275#define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos)
13276#define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk
13277#define OPAMP1_CSR_TSTREF_Pos (29U)
13278#define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos)
13279#define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk
13280#define OPAMP1_CSR_CALOUT_Pos (30U)
13281#define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos)
13282#define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk
13284/********************* Bit definition for OPAMP2_CSR register ***************/
13285#define OPAMP2_CSR_OPAEN_Pos (0U)
13286#define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos)
13287#define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk
13288#define OPAMP2_CSR_FORCEVP_Pos (1U)
13289#define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos)
13290#define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk
13292#define OPAMP2_CSR_VPSEL_Pos (2U)
13293#define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos)
13294#define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk
13295#define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos)
13296#define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos)
13298#define OPAMP2_CSR_VMSEL_Pos (5U)
13299#define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos)
13300#define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk
13301#define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos)
13302#define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos)
13304#define OPAMP2_CSR_OPAHSM_Pos (8U)
13305#define OPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos)
13306#define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk
13307#define OPAMP2_CSR_CALON_Pos (11U)
13308#define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos)
13309#define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk
13311#define OPAMP2_CSR_CALSEL_Pos (12U)
13312#define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos)
13313#define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk
13314#define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos)
13315#define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos)
13317#define OPAMP2_CSR_PGGAIN_Pos (14U)
13318#define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos)
13319#define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk
13320#define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos)
13321#define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos)
13322#define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos)
13323#define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos)
13325#define OPAMP2_CSR_USERTRIM_Pos (18U)
13326#define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos)
13327#define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk
13328#define OPAMP2_CSR_TSTREF_Pos (29U)
13329#define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos)
13330#define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk
13331#define OPAMP2_CSR_CALOUT_Pos (30U)
13332#define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos)
13333#define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk
13335/******************* Bit definition for OPAMP_OTR register ******************/
13336#define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
13337#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos)
13338#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk
13339#define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
13340#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos)
13341#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk
13343/******************* Bit definition for OPAMP1_OTR register ******************/
13344#define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
13345#define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos)
13346#define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk
13347#define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
13348#define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos)
13349#define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk
13351/******************* Bit definition for OPAMP2_OTR register ******************/
13352#define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
13353#define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos)
13354#define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk
13355#define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
13356#define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos)
13357#define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk
13359/******************* Bit definition for OPAMP_HSOTR register ****************/
13360#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
13361#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos)
13362#define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk
13363#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
13364#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos)
13365#define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk
13367/******************* Bit definition for OPAMP1_HSOTR register ****************/
13368#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
13369#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos)
13370#define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk
13371#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
13372#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos)
13373#define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk
13375/******************* Bit definition for OPAMP2_HSOTR register ****************/
13376#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
13377#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos)
13378#define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk
13379#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
13380#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos)
13381#define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk
13383/******************************************************************************/
13384/* */
13385/* Power Control */
13386/* */
13387/******************************************************************************/
13388/************************* NUMBER OF POWER DOMAINS **************************/
13389#define POWER_DOMAINS_NUMBER 3U
13391/******************** Bit definition for PWR_CR1 register *******************/
13392#define PWR_CR1_ALS_Pos (17U)
13393#define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos)
13394#define PWR_CR1_ALS PWR_CR1_ALS_Msk
13395#define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos)
13396#define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos)
13397#define PWR_CR1_AVDEN_Pos (16U)
13398#define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos)
13399#define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk
13400#define PWR_CR1_SVOS_Pos (14U)
13401#define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos)
13402#define PWR_CR1_SVOS PWR_CR1_SVOS_Msk
13403#define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos)
13404#define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos)
13405#define PWR_CR1_FLPS_Pos (9U)
13406#define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos)
13407#define PWR_CR1_FLPS PWR_CR1_FLPS_Msk
13408#define PWR_CR1_DBP_Pos (8U)
13409#define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos)
13410#define PWR_CR1_DBP PWR_CR1_DBP_Msk
13411#define PWR_CR1_PLS_Pos (5U)
13412#define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos)
13413#define PWR_CR1_PLS PWR_CR1_PLS_Msk
13414#define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos)
13415#define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos)
13416#define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos)
13417#define PWR_CR1_PVDEN_Pos (4U)
13418#define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos)
13419#define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk
13420#define PWR_CR1_LPDS_Pos (0U)
13421#define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos)
13422#define PWR_CR1_LPDS PWR_CR1_LPDS_Msk
13425#define PWR_CR1_PLS_LEV0 (0UL)
13426#define PWR_CR1_PLS_LEV1_Pos (5U)
13427#define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos)
13428#define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk
13429#define PWR_CR1_PLS_LEV2_Pos (6U)
13430#define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos)
13431#define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk
13432#define PWR_CR1_PLS_LEV3_Pos (5U)
13433#define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos)
13434#define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk
13435#define PWR_CR1_PLS_LEV4_Pos (7U)
13436#define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos)
13437#define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk
13438#define PWR_CR1_PLS_LEV5_Pos (5U)
13439#define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos)
13440#define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk
13441#define PWR_CR1_PLS_LEV6_Pos (6U)
13442#define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos)
13443#define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk
13444#define PWR_CR1_PLS_LEV7_Pos (5U)
13445#define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos)
13446#define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk
13449#define PWR_CR1_ALS_LEV0 (0UL)
13450#define PWR_CR1_ALS_LEV1_Pos (17U)
13451#define PWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos)
13452#define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk
13453#define PWR_CR1_ALS_LEV2_Pos (18U)
13454#define PWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos)
13455#define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk
13456#define PWR_CR1_ALS_LEV3_Pos (17U)
13457#define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos)
13458#define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk
13460/******************** Bit definition for PWR_CSR1 register ******************/
13461#define PWR_CSR1_AVDO_Pos (16U)
13462#define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos)
13463#define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk
13464#define PWR_CSR1_ACTVOS_Pos (14U)
13465#define PWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos)
13466#define PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk
13467#define PWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos)
13468#define PWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos)
13469#define PWR_CSR1_ACTVOSRDY_Pos (13U)
13470#define PWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)
13471#define PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk
13472#define PWR_CSR1_PVDO_Pos (4U)
13473#define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos)
13474#define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk
13476/******************** Bit definition for PWR_CR2 register *******************/
13477#define PWR_CR2_TEMPH_Pos (23U)
13478#define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos)
13479#define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk
13480#define PWR_CR2_TEMPL_Pos (22U)
13481#define PWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos)
13482#define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk
13483#define PWR_CR2_VBATH_Pos (21U)
13484#define PWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos)
13485#define PWR_CR2_VBATH PWR_CR2_VBATH_Msk
13486#define PWR_CR2_VBATL_Pos (20U)
13487#define PWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos)
13488#define PWR_CR2_VBATL PWR_CR2_VBATL_Msk
13489#define PWR_CR2_BRRDY_Pos (16U)
13490#define PWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos)
13491#define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk
13492#define PWR_CR2_MONEN_Pos (4U)
13493#define PWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos)
13494#define PWR_CR2_MONEN PWR_CR2_MONEN_Msk
13495#define PWR_CR2_BREN_Pos (0U)
13496#define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos)
13497#define PWR_CR2_BREN PWR_CR2_BREN_Msk
13499/******************** Bit definition for PWR_CR3 register *******************/
13500#define PWR_CR3_USB33RDY_Pos (26U)
13501#define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos)
13502#define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk
13503#define PWR_CR3_USBREGEN_Pos (25U)
13504#define PWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos)
13505#define PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk
13506#define PWR_CR3_USB33DEN_Pos (24U)
13507#define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos)
13508#define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk
13509#define PWR_CR3_VBRS_Pos (9U)
13510#define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos)
13511#define PWR_CR3_VBRS PWR_CR3_VBRS_Msk
13512#define PWR_CR3_VBE_Pos (8U)
13513#define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos)
13514#define PWR_CR3_VBE PWR_CR3_VBE_Msk
13515#define PWR_CR3_SCUEN_Pos (2U)
13516#define PWR_CR3_SCUEN_Msk (0x1UL << PWR_CR3_SCUEN_Pos)
13517#define PWR_CR3_SCUEN PWR_CR3_SCUEN_Msk
13518#define PWR_CR3_LDOEN_Pos (1U)
13519#define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos)
13520#define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk
13521#define PWR_CR3_BYPASS_Pos (0U)
13522#define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos)
13523#define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk
13525/******************** Bit definition for PWR_CPUCR register *****************/
13526#define PWR_CPUCR_RUN_D3_Pos (11U)
13527#define PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos)
13528#define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk
13529#define PWR_CPUCR_CSSF_Pos (9U)
13530#define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos)
13531#define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk
13532#define PWR_CPUCR_SBF_D2_Pos (8U)
13533#define PWR_CPUCR_SBF_D2_Msk (0x1UL << PWR_CPUCR_SBF_D2_Pos)
13534#define PWR_CPUCR_SBF_D2 PWR_CPUCR_SBF_D2_Msk
13535#define PWR_CPUCR_SBF_D1_Pos (7U)
13536#define PWR_CPUCR_SBF_D1_Msk (0x1UL << PWR_CPUCR_SBF_D1_Pos)
13537#define PWR_CPUCR_SBF_D1 PWR_CPUCR_SBF_D1_Msk
13538#define PWR_CPUCR_SBF_Pos (6U)
13539#define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos)
13540#define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk
13541#define PWR_CPUCR_STOPF_Pos (5U)
13542#define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos)
13543#define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk
13544#define PWR_CPUCR_PDDS_D3_Pos (2U)
13545#define PWR_CPUCR_PDDS_D3_Msk (0x1UL << PWR_CPUCR_PDDS_D3_Pos)
13546#define PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_D3_Msk
13547#define PWR_CPUCR_PDDS_D2_Pos (1U)
13548#define PWR_CPUCR_PDDS_D2_Msk (0x1UL << PWR_CPUCR_PDDS_D2_Pos)
13549#define PWR_CPUCR_PDDS_D2 PWR_CPUCR_PDDS_D2_Msk
13550#define PWR_CPUCR_PDDS_D1_Pos (0U)
13551#define PWR_CPUCR_PDDS_D1_Msk (0x1UL << PWR_CPUCR_PDDS_D1_Pos)
13552#define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk
13555/******************** Bit definition for PWR_D3CR register ******************/
13556#define PWR_D3CR_VOS_Pos (14U)
13557#define PWR_D3CR_VOS_Msk (0x3UL << PWR_D3CR_VOS_Pos)
13558#define PWR_D3CR_VOS PWR_D3CR_VOS_Msk
13559#define PWR_D3CR_VOS_0 (0x1UL << PWR_D3CR_VOS_Pos)
13560#define PWR_D3CR_VOS_1 (0x2UL << PWR_D3CR_VOS_Pos)
13561#define PWR_D3CR_VOSRDY_Pos (13U)
13562#define PWR_D3CR_VOSRDY_Msk (0x1UL << PWR_D3CR_VOSRDY_Pos)
13563#define PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk
13565/****************** Bit definition for PWR_WKUPCR register ******************/
13566#define PWR_WKUPCR_WKUPC6_Pos (5U)
13567#define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos)
13568#define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk
13569#define PWR_WKUPCR_WKUPC5_Pos (4U)
13570#define PWR_WKUPCR_WKUPC5_Msk (0x1UL << PWR_WKUPCR_WKUPC5_Pos)
13571#define PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk
13572#define PWR_WKUPCR_WKUPC4_Pos (3U)
13573#define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos)
13574#define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk
13575#define PWR_WKUPCR_WKUPC3_Pos (2U)
13576#define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos)
13577#define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk
13578#define PWR_WKUPCR_WKUPC2_Pos (1U)
13579#define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos)
13580#define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk
13581#define PWR_WKUPCR_WKUPC1_Pos (0U)
13582#define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos)
13583#define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk
13585/******************** Bit definition for PWR_WKUPFR register ****************/
13586#define PWR_WKUPFR_WKUPF6_Pos (5U)
13587#define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos)
13588#define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk
13589#define PWR_WKUPFR_WKUPF5_Pos (4U)
13590#define PWR_WKUPFR_WKUPF5_Msk (0x1UL << PWR_WKUPFR_WKUPF5_Pos)
13591#define PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk
13592#define PWR_WKUPFR_WKUPF4_Pos (3U)
13593#define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos)
13594#define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk
13595#define PWR_WKUPFR_WKUPF3_Pos (2U)
13596#define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos)
13597#define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk
13598#define PWR_WKUPFR_WKUPF2_Pos (1U)
13599#define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos)
13600#define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk
13601#define PWR_WKUPFR_WKUPF1_Pos (0U)
13602#define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos)
13603#define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk
13605/****************** Bit definition for PWR_WKUPEPR register *****************/
13606#define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
13607#define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
13608#define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk
13609#define PWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
13610#define PWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)
13611#define PWR_WKUPEPR_WKUPPUPD5_Pos (24U)
13612#define PWR_WKUPEPR_WKUPPUPD5_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)
13613#define PWR_WKUPEPR_WKUPPUPD5 PWR_WKUPEPR_WKUPPUPD5_Msk
13614#define PWR_WKUPEPR_WKUPPUPD5_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)
13615#define PWR_WKUPEPR_WKUPPUPD5_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)
13616#define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)
13617#define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
13618#define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk
13619#define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
13620#define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)
13621#define PWR_WKUPEPR_WKUPPUPD3_Pos (20U)
13622#define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)
13623#define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk
13624#define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)
13625#define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)
13626#define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)
13627#define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
13628#define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk
13629#define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
13630#define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)
13631#define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)
13632#define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
13633#define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk
13634#define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
13635#define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)
13636#define PWR_WKUPEPR_WKUPP6_Pos (13U)
13637#define PWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)
13638#define PWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk
13639#define PWR_WKUPEPR_WKUPP5_Pos (12U)
13640#define PWR_WKUPEPR_WKUPP5_Msk (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)
13641#define PWR_WKUPEPR_WKUPP5 PWR_WKUPEPR_WKUPP5_Msk
13642#define PWR_WKUPEPR_WKUPP4_Pos (11U)
13643#define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)
13644#define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk
13645#define PWR_WKUPEPR_WKUPP3_Pos (10U)
13646#define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)
13647#define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk
13648#define PWR_WKUPEPR_WKUPP2_Pos (9U)
13649#define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)
13650#define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk
13651#define PWR_WKUPEPR_WKUPP1_Pos (8U)
13652#define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)
13653#define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk
13654#define PWR_WKUPEPR_WKUPEN6_Pos (5U)
13655#define PWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)
13656#define PWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk
13657#define PWR_WKUPEPR_WKUPEN5_Pos (4U)
13658#define PWR_WKUPEPR_WKUPEN5_Msk (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)
13659#define PWR_WKUPEPR_WKUPEN5 PWR_WKUPEPR_WKUPEN5_Msk
13660#define PWR_WKUPEPR_WKUPEN4_Pos (3U)
13661#define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)
13662#define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk
13663#define PWR_WKUPEPR_WKUPEN3_Pos (2U)
13664#define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)
13665#define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk
13666#define PWR_WKUPEPR_WKUPEN2_Pos (1U)
13667#define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)
13668#define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk
13669#define PWR_WKUPEPR_WKUPEN1_Pos (0U)
13670#define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)
13671#define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk
13672#define PWR_WKUPEPR_WKUPEN_Pos (0U)
13673#define PWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)
13674#define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk
13676/******************************************************************************/
13677/* */
13678/* Reset and Clock Control */
13679/* */
13680/******************************************************************************/
13681/******************************* RCC VERSION ********************************/
13682#define RCC_VER_X
13683
13684/******************** Bit definition for RCC_CR register ********************/
13685#define RCC_CR_HSION_Pos (0U)
13686#define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)
13687#define RCC_CR_HSION RCC_CR_HSION_Msk
13688#define RCC_CR_HSIKERON_Pos (1U)
13689#define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos)
13690#define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk
13691#define RCC_CR_HSIRDY_Pos (2U)
13692#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)
13693#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk
13694#define RCC_CR_HSIDIV_Pos (3U)
13695#define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos)
13696#define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk
13697#define RCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos)
13698#define RCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos)
13699#define RCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos)
13700#define RCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos)
13702#define RCC_CR_HSIDIVF_Pos (5U)
13703#define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos)
13704#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk
13705#define RCC_CR_CSION_Pos (7U)
13706#define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos)
13707#define RCC_CR_CSION RCC_CR_CSION_Msk
13708#define RCC_CR_CSIRDY_Pos (8U)
13709#define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos)
13710#define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk
13711#define RCC_CR_CSIKERON_Pos (9U)
13712#define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos)
13713#define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk
13714#define RCC_CR_HSI48ON_Pos (12U)
13715#define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos)
13716#define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk
13717#define RCC_CR_HSI48RDY_Pos (13U)
13718#define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos)
13719#define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk
13721#define RCC_CR_D1CKRDY_Pos (14U)
13722#define RCC_CR_D1CKRDY_Msk (0x1UL << RCC_CR_D1CKRDY_Pos)
13723#define RCC_CR_D1CKRDY RCC_CR_D1CKRDY_Msk
13724#define RCC_CR_D2CKRDY_Pos (15U)
13725#define RCC_CR_D2CKRDY_Msk (0x1UL << RCC_CR_D2CKRDY_Pos)
13726#define RCC_CR_D2CKRDY RCC_CR_D2CKRDY_Msk
13728#define RCC_CR_HSEON_Pos (16U)
13729#define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)
13730#define RCC_CR_HSEON RCC_CR_HSEON_Msk
13731#define RCC_CR_HSERDY_Pos (17U)
13732#define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)
13733#define RCC_CR_HSERDY RCC_CR_HSERDY_Msk
13734#define RCC_CR_HSEBYP_Pos (18U)
13735#define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)
13736#define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk
13737#define RCC_CR_CSSHSEON_Pos (19U)
13738#define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos)
13739#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk
13742#define RCC_CR_PLL1ON_Pos (24U)
13743#define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos)
13744#define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk
13745#define RCC_CR_PLL1RDY_Pos (25U)
13746#define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos)
13747#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk
13748#define RCC_CR_PLL2ON_Pos (26U)
13749#define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos)
13750#define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk
13751#define RCC_CR_PLL2RDY_Pos (27U)
13752#define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos)
13753#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk
13754#define RCC_CR_PLL3ON_Pos (28U)
13755#define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos)
13756#define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk
13757#define RCC_CR_PLL3RDY_Pos (29U)
13758#define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos)
13759#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk
13761/*Legacy */
13762#define RCC_CR_PLLON_Pos (24U)
13763#define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)
13764#define RCC_CR_PLLON RCC_CR_PLLON_Msk
13765#define RCC_CR_PLLRDY_Pos (25U)
13766#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)
13767#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk
13769/******************** Bit definition for RCC_HSICFGR register ***************/
13771#define RCC_HSICFGR_HSICAL_Pos (0U)
13772#define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos)
13773#define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk
13774#define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos)
13775#define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos)
13776#define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos)
13777#define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos)
13778#define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos)
13779#define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos)
13780#define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos)
13781#define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos)
13782#define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos)
13783#define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos)
13784#define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos)
13785#define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos)
13788#define RCC_HSICFGR_HSITRIM_Pos (24U)
13789#define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos)
13790#define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk
13791#define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos)
13792#define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos)
13793#define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos)
13794#define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos)
13795#define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos)
13796#define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos)
13797#define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos)
13800/******************** Bit definition for RCC_CRRCR register *****************/
13801
13803#define RCC_CRRCR_HSI48CAL_Pos (0U)
13804#define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos)
13805#define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk
13806#define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos)
13807#define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos)
13808#define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos)
13809#define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos)
13810#define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos)
13811#define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos)
13812#define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos)
13813#define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos)
13814#define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos)
13815#define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos)
13818/******************** Bit definition for RCC_CSICFGR register *****************/
13820#define RCC_CSICFGR_CSICAL_Pos (0U)
13821#define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos)
13822#define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk
13823#define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos)
13824#define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos)
13825#define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos)
13826#define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos)
13827#define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos)
13828#define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos)
13829#define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos)
13830#define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos)
13833#define RCC_CSICFGR_CSITRIM_Pos (24U)
13834#define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos)
13835#define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk
13836#define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos)
13837#define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos)
13838#define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos)
13839#define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos)
13840#define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos)
13841#define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos)
13843/******************** Bit definition for RCC_CFGR register ******************/
13845#define RCC_CFGR_SW_Pos (0U)
13846#define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos)
13847#define RCC_CFGR_SW RCC_CFGR_SW_Msk
13848#define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)
13849#define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)
13850#define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos)
13852#define RCC_CFGR_SW_HSI (0x00000000UL)
13853#define RCC_CFGR_SW_CSI (0x00000001UL)
13854#define RCC_CFGR_SW_HSE (0x00000002UL)
13855#define RCC_CFGR_SW_PLL1 (0x00000003UL)
13858#define RCC_CFGR_SWS_Pos (3U)
13859#define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos)
13860#define RCC_CFGR_SWS RCC_CFGR_SWS_Msk
13861#define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)
13862#define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)
13863#define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos)
13865#define RCC_CFGR_SWS_HSI (0x00000000UL)
13866#define RCC_CFGR_SWS_CSI (0x00000008UL)
13867#define RCC_CFGR_SWS_HSE (0x00000010UL)
13868#define RCC_CFGR_SWS_PLL1 (0x00000018UL)
13870#define RCC_CFGR_STOPWUCK_Pos (6U)
13871#define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos)
13872#define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk
13874#define RCC_CFGR_STOPKERWUCK_Pos (7U)
13875#define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)
13876#define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk
13879#define RCC_CFGR_RTCPRE_Pos (8U)
13880#define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos)
13881#define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk
13882#define RCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos)
13883#define RCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos)
13884#define RCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos)
13885#define RCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos)
13886#define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos)
13887#define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos)
13890#define RCC_CFGR_HRTIMSEL_Pos (14U)
13891#define RCC_CFGR_HRTIMSEL_Msk (0x1UL << RCC_CFGR_HRTIMSEL_Pos)
13892#define RCC_CFGR_HRTIMSEL RCC_CFGR_HRTIMSEL_Msk
13895#define RCC_CFGR_TIMPRE_Pos (15U)
13896#define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos)
13897#define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk
13900#define RCC_CFGR_MCO1_Pos (22U)
13901#define RCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos)
13902#define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk
13903#define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos)
13904#define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos)
13905#define RCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos)
13907#define RCC_CFGR_MCO1PRE_Pos (18U)
13908#define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos)
13909#define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk
13910#define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos)
13911#define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos)
13912#define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos)
13913#define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos)
13915#define RCC_CFGR_MCO2PRE_Pos (25U)
13916#define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos)
13917#define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk
13918#define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos)
13919#define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos)
13920#define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos)
13921#define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos)
13923#define RCC_CFGR_MCO2_Pos (29U)
13924#define RCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos)
13925#define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk
13926#define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos)
13927#define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos)
13928#define RCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos)
13930/******************** Bit definition for RCC_D1CFGR register ******************/
13932#define RCC_D1CFGR_HPRE_Pos (0U)
13933#define RCC_D1CFGR_HPRE_Msk (0xFUL << RCC_D1CFGR_HPRE_Pos)
13934#define RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_Msk
13935#define RCC_D1CFGR_HPRE_0 (0x1UL << RCC_D1CFGR_HPRE_Pos)
13936#define RCC_D1CFGR_HPRE_1 (0x2UL << RCC_D1CFGR_HPRE_Pos)
13937#define RCC_D1CFGR_HPRE_2 (0x4UL << RCC_D1CFGR_HPRE_Pos)
13938#define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos)
13941#define RCC_D1CFGR_HPRE_DIV1 (0U)
13942#define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
13943#define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos)
13944#define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk
13945#define RCC_D1CFGR_HPRE_DIV4_Pos (0U)
13946#define RCC_D1CFGR_HPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos)
13947#define RCC_D1CFGR_HPRE_DIV4 RCC_D1CFGR_HPRE_DIV4_Msk
13948#define RCC_D1CFGR_HPRE_DIV8_Pos (1U)
13949#define RCC_D1CFGR_HPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos)
13950#define RCC_D1CFGR_HPRE_DIV8 RCC_D1CFGR_HPRE_DIV8_Msk
13951#define RCC_D1CFGR_HPRE_DIV16_Pos (0U)
13952#define RCC_D1CFGR_HPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos)
13953#define RCC_D1CFGR_HPRE_DIV16 RCC_D1CFGR_HPRE_DIV16_Msk
13954#define RCC_D1CFGR_HPRE_DIV64_Pos (2U)
13955#define RCC_D1CFGR_HPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos)
13956#define RCC_D1CFGR_HPRE_DIV64 RCC_D1CFGR_HPRE_DIV64_Msk
13957#define RCC_D1CFGR_HPRE_DIV128_Pos (0U)
13958#define RCC_D1CFGR_HPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos)
13959#define RCC_D1CFGR_HPRE_DIV128 RCC_D1CFGR_HPRE_DIV128_Msk
13960#define RCC_D1CFGR_HPRE_DIV256_Pos (1U)
13961#define RCC_D1CFGR_HPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos)
13962#define RCC_D1CFGR_HPRE_DIV256 RCC_D1CFGR_HPRE_DIV256_Msk
13963#define RCC_D1CFGR_HPRE_DIV512_Pos (0U)
13964#define RCC_D1CFGR_HPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos)
13965#define RCC_D1CFGR_HPRE_DIV512 RCC_D1CFGR_HPRE_DIV512_Msk
13968#define RCC_D1CFGR_D1PPRE_Pos (4U)
13969#define RCC_D1CFGR_D1PPRE_Msk (0x7UL << RCC_D1CFGR_D1PPRE_Pos)
13970#define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk
13971#define RCC_D1CFGR_D1PPRE_0 (0x1UL << RCC_D1CFGR_D1PPRE_Pos)
13972#define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos)
13973#define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos)
13975#define RCC_D1CFGR_D1PPRE_DIV1 (0U)
13976#define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
13977#define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos)
13978#define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk
13979#define RCC_D1CFGR_D1PPRE_DIV4_Pos (4U)
13980#define RCC_D1CFGR_D1PPRE_DIV4_Msk (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos)
13981#define RCC_D1CFGR_D1PPRE_DIV4 RCC_D1CFGR_D1PPRE_DIV4_Msk
13982#define RCC_D1CFGR_D1PPRE_DIV8_Pos (5U)
13983#define RCC_D1CFGR_D1PPRE_DIV8_Msk (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos)
13984#define RCC_D1CFGR_D1PPRE_DIV8 RCC_D1CFGR_D1PPRE_DIV8_Msk
13985#define RCC_D1CFGR_D1PPRE_DIV16_Pos (4U)
13986#define RCC_D1CFGR_D1PPRE_DIV16_Msk (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos)
13987#define RCC_D1CFGR_D1PPRE_DIV16 RCC_D1CFGR_D1PPRE_DIV16_Msk
13989#define RCC_D1CFGR_D1CPRE_Pos (8U)
13990#define RCC_D1CFGR_D1CPRE_Msk (0xFUL << RCC_D1CFGR_D1CPRE_Pos)
13991#define RCC_D1CFGR_D1CPRE RCC_D1CFGR_D1CPRE_Msk
13992#define RCC_D1CFGR_D1CPRE_0 (0x1UL << RCC_D1CFGR_D1CPRE_Pos)
13993#define RCC_D1CFGR_D1CPRE_1 (0x2UL << RCC_D1CFGR_D1CPRE_Pos)
13994#define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos)
13995#define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos)
13997#define RCC_D1CFGR_D1CPRE_DIV1 (0U)
13998#define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
13999#define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos)
14000#define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk
14001#define RCC_D1CFGR_D1CPRE_DIV4_Pos (8U)
14002#define RCC_D1CFGR_D1CPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos)
14003#define RCC_D1CFGR_D1CPRE_DIV4 RCC_D1CFGR_D1CPRE_DIV4_Msk
14004#define RCC_D1CFGR_D1CPRE_DIV8_Pos (9U)
14005#define RCC_D1CFGR_D1CPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos)
14006#define RCC_D1CFGR_D1CPRE_DIV8 RCC_D1CFGR_D1CPRE_DIV8_Msk
14007#define RCC_D1CFGR_D1CPRE_DIV16_Pos (8U)
14008#define RCC_D1CFGR_D1CPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos)
14009#define RCC_D1CFGR_D1CPRE_DIV16 RCC_D1CFGR_D1CPRE_DIV16_Msk
14010#define RCC_D1CFGR_D1CPRE_DIV64_Pos (10U)
14011#define RCC_D1CFGR_D1CPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos)
14012#define RCC_D1CFGR_D1CPRE_DIV64 RCC_D1CFGR_D1CPRE_DIV64_Msk
14013#define RCC_D1CFGR_D1CPRE_DIV128_Pos (8U)
14014#define RCC_D1CFGR_D1CPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos)
14015#define RCC_D1CFGR_D1CPRE_DIV128 RCC_D1CFGR_D1CPRE_DIV128_Msk
14016#define RCC_D1CFGR_D1CPRE_DIV256_Pos (9U)
14017#define RCC_D1CFGR_D1CPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos)
14018#define RCC_D1CFGR_D1CPRE_DIV256 RCC_D1CFGR_D1CPRE_DIV256_Msk
14019#define RCC_D1CFGR_D1CPRE_DIV512_Pos (8U)
14020#define RCC_D1CFGR_D1CPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos)
14021#define RCC_D1CFGR_D1CPRE_DIV512 RCC_D1CFGR_D1CPRE_DIV512_Msk
14023/******************** Bit definition for RCC_D2CFGR register ******************/
14025#define RCC_D2CFGR_D2PPRE1_Pos (4U)
14026#define RCC_D2CFGR_D2PPRE1_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_Pos)
14027#define RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_Msk
14028#define RCC_D2CFGR_D2PPRE1_0 (0x1UL << RCC_D2CFGR_D2PPRE1_Pos)
14029#define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos)
14030#define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos)
14032#define RCC_D2CFGR_D2PPRE1_DIV1 (0U)
14033#define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
14034#define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos)
14035#define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk
14036#define RCC_D2CFGR_D2PPRE1_DIV4_Pos (4U)
14037#define RCC_D2CFGR_D2PPRE1_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos)
14038#define RCC_D2CFGR_D2PPRE1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4_Msk
14039#define RCC_D2CFGR_D2PPRE1_DIV8_Pos (5U)
14040#define RCC_D2CFGR_D2PPRE1_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos)
14041#define RCC_D2CFGR_D2PPRE1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8_Msk
14042#define RCC_D2CFGR_D2PPRE1_DIV16_Pos (4U)
14043#define RCC_D2CFGR_D2PPRE1_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos)
14044#define RCC_D2CFGR_D2PPRE1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16_Msk
14047#define RCC_D2CFGR_D2PPRE2_Pos (8U)
14048#define RCC_D2CFGR_D2PPRE2_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_Pos)
14049#define RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_Msk
14050#define RCC_D2CFGR_D2PPRE2_0 (0x1UL << RCC_D2CFGR_D2PPRE2_Pos)
14051#define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos)
14052#define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos)
14054#define RCC_D2CFGR_D2PPRE2_DIV1 (0U)
14055#define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
14056#define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos)
14057#define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk
14058#define RCC_D2CFGR_D2PPRE2_DIV4_Pos (8U)
14059#define RCC_D2CFGR_D2PPRE2_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos)
14060#define RCC_D2CFGR_D2PPRE2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4_Msk
14061#define RCC_D2CFGR_D2PPRE2_DIV8_Pos (9U)
14062#define RCC_D2CFGR_D2PPRE2_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos)
14063#define RCC_D2CFGR_D2PPRE2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8_Msk
14064#define RCC_D2CFGR_D2PPRE2_DIV16_Pos (8U)
14065#define RCC_D2CFGR_D2PPRE2_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos)
14066#define RCC_D2CFGR_D2PPRE2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16_Msk
14068/******************** Bit definition for RCC_D3CFGR register ******************/
14070#define RCC_D3CFGR_D3PPRE_Pos (4U)
14071#define RCC_D3CFGR_D3PPRE_Msk (0x7UL << RCC_D3CFGR_D3PPRE_Pos)
14072#define RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_Msk
14073#define RCC_D3CFGR_D3PPRE_0 (0x1UL << RCC_D3CFGR_D3PPRE_Pos)
14074#define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos)
14075#define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos)
14077#define RCC_D3CFGR_D3PPRE_DIV1 (0U)
14078#define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
14079#define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos)
14080#define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk
14081#define RCC_D3CFGR_D3PPRE_DIV4_Pos (4U)
14082#define RCC_D3CFGR_D3PPRE_DIV4_Msk (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos)
14083#define RCC_D3CFGR_D3PPRE_DIV4 RCC_D3CFGR_D3PPRE_DIV4_Msk
14084#define RCC_D3CFGR_D3PPRE_DIV8_Pos (5U)
14085#define RCC_D3CFGR_D3PPRE_DIV8_Msk (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos)
14086#define RCC_D3CFGR_D3PPRE_DIV8 RCC_D3CFGR_D3PPRE_DIV8_Msk
14087#define RCC_D3CFGR_D3PPRE_DIV16_Pos (4U)
14088#define RCC_D3CFGR_D3PPRE_DIV16_Msk (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos)
14089#define RCC_D3CFGR_D3PPRE_DIV16 RCC_D3CFGR_D3PPRE_DIV16_Msk
14091/******************** Bit definition for RCC_PLLCKSELR register *************/
14092
14093#define RCC_PLLCKSELR_PLLSRC_Pos (0U)
14094#define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos)
14095#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
14096
14097#define RCC_PLLCKSELR_PLLSRC_HSI (0U)
14098#define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
14099#define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos)
14100#define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk
14101#define RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U)
14102#define RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos)
14103#define RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk
14104#define RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U)
14105#define RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos)
14106#define RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk
14108#define RCC_PLLCKSELR_DIVM1_Pos (4U)
14109#define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos)
14110#define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk
14111#define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos)
14112#define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos)
14113#define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos)
14114#define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos)
14115#define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos)
14116#define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos)
14118#define RCC_PLLCKSELR_DIVM2_Pos (12U)
14119#define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos)
14120#define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk
14121#define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos)
14122#define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos)
14123#define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos)
14124#define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos)
14125#define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos)
14126#define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos)
14128#define RCC_PLLCKSELR_DIVM3_Pos (20U)
14129#define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos)
14130#define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk
14131#define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos)
14132#define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos)
14133#define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos)
14134#define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos)
14135#define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos)
14136#define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos)
14138/******************** Bit definition for RCC_PLLCFGR register ***************/
14139
14140#define RCC_PLLCFGR_PLL1FRACEN_Pos (0U)
14141#define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos)
14142#define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk
14143#define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U)
14144#define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos)
14145#define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk
14146#define RCC_PLLCFGR_PLL1RGE_Pos (2U)
14147#define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos)
14148#define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk
14149#define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos)
14150#define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos)
14151#define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos)
14152#define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos)
14154#define RCC_PLLCFGR_PLL2FRACEN_Pos (4U)
14155#define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos)
14156#define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk
14157#define RCC_PLLCFGR_PLL2VCOSEL_Pos (5U)
14158#define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos)
14159#define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk
14160#define RCC_PLLCFGR_PLL2RGE_Pos (6U)
14161#define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos)
14162#define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk
14163#define RCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos)
14164#define RCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos)
14165#define RCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos)
14166#define RCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos)
14168#define RCC_PLLCFGR_PLL3FRACEN_Pos (8U)
14169#define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos)
14170#define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk
14171#define RCC_PLLCFGR_PLL3VCOSEL_Pos (9U)
14172#define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos)
14173#define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk
14174#define RCC_PLLCFGR_PLL3RGE_Pos (10U)
14175#define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos)
14176#define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk
14177#define RCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos)
14178#define RCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos)
14179#define RCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos)
14180#define RCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos)
14182#define RCC_PLLCFGR_DIVP1EN_Pos (16U)
14183#define RCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos)
14184#define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk
14185#define RCC_PLLCFGR_DIVQ1EN_Pos (17U)
14186#define RCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos)
14187#define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk
14188#define RCC_PLLCFGR_DIVR1EN_Pos (18U)
14189#define RCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos)
14190#define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk
14191
14192#define RCC_PLLCFGR_DIVP2EN_Pos (19U)
14193#define RCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos)
14194#define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk
14195#define RCC_PLLCFGR_DIVQ2EN_Pos (20U)
14196#define RCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos)
14197#define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk
14198#define RCC_PLLCFGR_DIVR2EN_Pos (21U)
14199#define RCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos)
14200#define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk
14201
14202#define RCC_PLLCFGR_DIVP3EN_Pos (22U)
14203#define RCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos)
14204#define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk
14205#define RCC_PLLCFGR_DIVQ3EN_Pos (23U)
14206#define RCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos)
14207#define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk
14208#define RCC_PLLCFGR_DIVR3EN_Pos (24U)
14209#define RCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos)
14210#define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk
14211
14212
14213/******************** Bit definition for RCC_PLL1DIVR register ***************/
14214#define RCC_PLL1DIVR_N1_Pos (0U)
14215#define RCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos)
14216#define RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk
14217#define RCC_PLL1DIVR_P1_Pos (9U)
14218#define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos)
14219#define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk
14220#define RCC_PLL1DIVR_Q1_Pos (16U)
14221#define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos)
14222#define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
14223#define RCC_PLL1DIVR_R1_Pos (24U)
14224#define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos)
14225#define RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk
14226
14227/******************** Bit definition for RCC_PLL1FRACR register ***************/
14228#define RCC_PLL1FRACR_FRACN1_Pos (3U)
14229#define RCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos)
14230#define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk
14231
14232/******************** Bit definition for RCC_PLL2DIVR register ***************/
14233#define RCC_PLL2DIVR_N2_Pos (0U)
14234#define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos)
14235#define RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk
14236#define RCC_PLL2DIVR_P2_Pos (9U)
14237#define RCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos)
14238#define RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk
14239#define RCC_PLL2DIVR_Q2_Pos (16U)
14240#define RCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos)
14241#define RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk
14242#define RCC_PLL2DIVR_R2_Pos (24U)
14243#define RCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos)
14244#define RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk
14245
14246/******************** Bit definition for RCC_PLL2FRACR register ***************/
14247#define RCC_PLL2FRACR_FRACN2_Pos (3U)
14248#define RCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos)
14249#define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk
14250
14251/******************** Bit definition for RCC_PLL3DIVR register ***************/
14252#define RCC_PLL3DIVR_N3_Pos (0U)
14253#define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos)
14254#define RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk
14255#define RCC_PLL3DIVR_P3_Pos (9U)
14256#define RCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos)
14257#define RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk
14258#define RCC_PLL3DIVR_Q3_Pos (16U)
14259#define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos)
14260#define RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk
14261#define RCC_PLL3DIVR_R3_Pos (24U)
14262#define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos)
14263#define RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk
14264
14265/******************** Bit definition for RCC_PLL3FRACR register ***************/
14266#define RCC_PLL3FRACR_FRACN3_Pos (3U)
14267#define RCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos)
14268#define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk
14269
14270/******************** Bit definition for RCC_D1CCIPR register ***************/
14271#define RCC_D1CCIPR_FMCSEL_Pos (0U)
14272#define RCC_D1CCIPR_FMCSEL_Msk (0x3UL << RCC_D1CCIPR_FMCSEL_Pos)
14273#define RCC_D1CCIPR_FMCSEL RCC_D1CCIPR_FMCSEL_Msk
14274#define RCC_D1CCIPR_FMCSEL_0 (0x1UL << RCC_D1CCIPR_FMCSEL_Pos)
14275#define RCC_D1CCIPR_FMCSEL_1 (0x2UL << RCC_D1CCIPR_FMCSEL_Pos)
14276#define RCC_D1CCIPR_QSPISEL_Pos (4U)
14277#define RCC_D1CCIPR_QSPISEL_Msk (0x3UL << RCC_D1CCIPR_QSPISEL_Pos)
14278#define RCC_D1CCIPR_QSPISEL RCC_D1CCIPR_QSPISEL_Msk
14279#define RCC_D1CCIPR_QSPISEL_0 (0x1UL << RCC_D1CCIPR_QSPISEL_Pos)
14280#define RCC_D1CCIPR_QSPISEL_1 (0x2UL << RCC_D1CCIPR_QSPISEL_Pos)
14281#define RCC_D1CCIPR_SDMMCSEL_Pos (16U)
14282#define RCC_D1CCIPR_SDMMCSEL_Msk (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos)
14283#define RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMCSEL_Msk
14284#define RCC_D1CCIPR_CKPERSEL_Pos (28U)
14285#define RCC_D1CCIPR_CKPERSEL_Msk (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos)
14286#define RCC_D1CCIPR_CKPERSEL RCC_D1CCIPR_CKPERSEL_Msk
14287#define RCC_D1CCIPR_CKPERSEL_0 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos)
14288#define RCC_D1CCIPR_CKPERSEL_1 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos)
14290/******************** Bit definition for RCC_D2CCIP1R register ***************/
14291#define RCC_D2CCIP1R_SAI1SEL_Pos (0U)
14292#define RCC_D2CCIP1R_SAI1SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos)
14293#define RCC_D2CCIP1R_SAI1SEL RCC_D2CCIP1R_SAI1SEL_Msk
14294#define RCC_D2CCIP1R_SAI1SEL_0 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos)
14295#define RCC_D2CCIP1R_SAI1SEL_1 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos)
14296#define RCC_D2CCIP1R_SAI1SEL_2 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos)
14298#define RCC_D2CCIP1R_SAI23SEL_Pos (6U)
14299#define RCC_D2CCIP1R_SAI23SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos)
14300#define RCC_D2CCIP1R_SAI23SEL RCC_D2CCIP1R_SAI23SEL_Msk
14301#define RCC_D2CCIP1R_SAI23SEL_0 (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos)
14302#define RCC_D2CCIP1R_SAI23SEL_1 (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos)
14303#define RCC_D2CCIP1R_SAI23SEL_2 (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos)
14305#define RCC_D2CCIP1R_SPI123SEL_Pos (12U)
14306#define RCC_D2CCIP1R_SPI123SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos)
14307#define RCC_D2CCIP1R_SPI123SEL RCC_D2CCIP1R_SPI123SEL_Msk
14308#define RCC_D2CCIP1R_SPI123SEL_0 (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos)
14309#define RCC_D2CCIP1R_SPI123SEL_1 (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos)
14310#define RCC_D2CCIP1R_SPI123SEL_2 (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos)
14312#define RCC_D2CCIP1R_SPI45SEL_Pos (16U)
14313#define RCC_D2CCIP1R_SPI45SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos)
14314#define RCC_D2CCIP1R_SPI45SEL RCC_D2CCIP1R_SPI45SEL_Msk
14315#define RCC_D2CCIP1R_SPI45SEL_0 (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos)
14316#define RCC_D2CCIP1R_SPI45SEL_1 (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos)
14317#define RCC_D2CCIP1R_SPI45SEL_2 (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos)
14319#define RCC_D2CCIP1R_SPDIFSEL_Pos (20U)
14320#define RCC_D2CCIP1R_SPDIFSEL_Msk (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
14321#define RCC_D2CCIP1R_SPDIFSEL RCC_D2CCIP1R_SPDIFSEL_Msk
14322#define RCC_D2CCIP1R_SPDIFSEL_0 (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
14323#define RCC_D2CCIP1R_SPDIFSEL_1 (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos)
14325#define RCC_D2CCIP1R_DFSDM1SEL_Pos (24U)
14326#define RCC_D2CCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos)
14327#define RCC_D2CCIP1R_DFSDM1SEL RCC_D2CCIP1R_DFSDM1SEL_Msk
14328
14329#define RCC_D2CCIP1R_FDCANSEL_Pos (28U)
14330#define RCC_D2CCIP1R_FDCANSEL_Msk (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos)
14331#define RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_Msk
14332#define RCC_D2CCIP1R_FDCANSEL_0 (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos)
14333#define RCC_D2CCIP1R_FDCANSEL_1 (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos)
14335#define RCC_D2CCIP1R_SWPSEL_Pos (31U)
14336#define RCC_D2CCIP1R_SWPSEL_Msk (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos)
14337#define RCC_D2CCIP1R_SWPSEL RCC_D2CCIP1R_SWPSEL_Msk
14338
14339/******************** Bit definition for RCC_D2CCIP2R register ***************/
14340#define RCC_D2CCIP2R_USART16SEL_Pos (3U)
14341#define RCC_D2CCIP2R_USART16SEL_Msk (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos)
14342#define RCC_D2CCIP2R_USART16SEL RCC_D2CCIP2R_USART16SEL_Msk
14343#define RCC_D2CCIP2R_USART16SEL_0 (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos)
14344#define RCC_D2CCIP2R_USART16SEL_1 (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos)
14345#define RCC_D2CCIP2R_USART16SEL_2 (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos)
14347#define RCC_D2CCIP2R_USART28SEL_Pos (0U)
14348#define RCC_D2CCIP2R_USART28SEL_Msk (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos)
14349#define RCC_D2CCIP2R_USART28SEL RCC_D2CCIP2R_USART28SEL_Msk
14350#define RCC_D2CCIP2R_USART28SEL_0 (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos)
14351#define RCC_D2CCIP2R_USART28SEL_1 (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos)
14352#define RCC_D2CCIP2R_USART28SEL_2 (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos)
14354#define RCC_D2CCIP2R_RNGSEL_Pos (8U)
14355#define RCC_D2CCIP2R_RNGSEL_Msk (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos)
14356#define RCC_D2CCIP2R_RNGSEL RCC_D2CCIP2R_RNGSEL_Msk
14357#define RCC_D2CCIP2R_RNGSEL_0 (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos)
14358#define RCC_D2CCIP2R_RNGSEL_1 (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos)
14360#define RCC_D2CCIP2R_I2C123SEL_Pos (12U)
14361#define RCC_D2CCIP2R_I2C123SEL_Msk (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos)
14362#define RCC_D2CCIP2R_I2C123SEL RCC_D2CCIP2R_I2C123SEL_Msk
14363#define RCC_D2CCIP2R_I2C123SEL_0 (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos)
14364#define RCC_D2CCIP2R_I2C123SEL_1 (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos)
14366#define RCC_D2CCIP2R_USBSEL_Pos (20U)
14367#define RCC_D2CCIP2R_USBSEL_Msk (0x3UL << RCC_D2CCIP2R_USBSEL_Pos)
14368#define RCC_D2CCIP2R_USBSEL RCC_D2CCIP2R_USBSEL_Msk
14369#define RCC_D2CCIP2R_USBSEL_0 (0x1UL << RCC_D2CCIP2R_USBSEL_Pos)
14370#define RCC_D2CCIP2R_USBSEL_1 (0x2UL << RCC_D2CCIP2R_USBSEL_Pos)
14372#define RCC_D2CCIP2R_CECSEL_Pos (22U)
14373#define RCC_D2CCIP2R_CECSEL_Msk (0x3UL << RCC_D2CCIP2R_CECSEL_Pos)
14374#define RCC_D2CCIP2R_CECSEL RCC_D2CCIP2R_CECSEL_Msk
14375#define RCC_D2CCIP2R_CECSEL_0 (0x1UL << RCC_D2CCIP2R_CECSEL_Pos)
14376#define RCC_D2CCIP2R_CECSEL_1 (0x2UL << RCC_D2CCIP2R_CECSEL_Pos)
14378#define RCC_D2CCIP2R_LPTIM1SEL_Pos (28U)
14379#define RCC_D2CCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
14380#define RCC_D2CCIP2R_LPTIM1SEL RCC_D2CCIP2R_LPTIM1SEL_Msk
14381#define RCC_D2CCIP2R_LPTIM1SEL_0 (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
14382#define RCC_D2CCIP2R_LPTIM1SEL_1 (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
14383#define RCC_D2CCIP2R_LPTIM1SEL_2 (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos)
14385/******************** Bit definition for RCC_D3CCIPR register ***************/
14386#define RCC_D3CCIPR_LPUART1SEL_Pos (0U)
14387#define RCC_D3CCIPR_LPUART1SEL_Msk (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos)
14388#define RCC_D3CCIPR_LPUART1SEL RCC_D3CCIPR_LPUART1SEL_Msk
14389#define RCC_D3CCIPR_LPUART1SEL_0 (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos)
14390#define RCC_D3CCIPR_LPUART1SEL_1 (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos)
14391#define RCC_D3CCIPR_LPUART1SEL_2 (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos)
14393#define RCC_D3CCIPR_I2C4SEL_Pos (8U)
14394#define RCC_D3CCIPR_I2C4SEL_Msk (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos)
14395#define RCC_D3CCIPR_I2C4SEL RCC_D3CCIPR_I2C4SEL_Msk
14396#define RCC_D3CCIPR_I2C4SEL_0 (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos)
14397#define RCC_D3CCIPR_I2C4SEL_1 (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos)
14399#define RCC_D3CCIPR_LPTIM2SEL_Pos (10U)
14400#define RCC_D3CCIPR_LPTIM2SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
14401#define RCC_D3CCIPR_LPTIM2SEL RCC_D3CCIPR_LPTIM2SEL_Msk
14402#define RCC_D3CCIPR_LPTIM2SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
14403#define RCC_D3CCIPR_LPTIM2SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
14404#define RCC_D3CCIPR_LPTIM2SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos)
14406#define RCC_D3CCIPR_LPTIM345SEL_Pos (13U)
14407#define RCC_D3CCIPR_LPTIM345SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
14408#define RCC_D3CCIPR_LPTIM345SEL RCC_D3CCIPR_LPTIM345SEL_Msk
14409#define RCC_D3CCIPR_LPTIM345SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
14410#define RCC_D3CCIPR_LPTIM345SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
14411#define RCC_D3CCIPR_LPTIM345SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos)
14413#define RCC_D3CCIPR_SAI4ASEL_Pos (21U)
14414#define RCC_D3CCIPR_SAI4ASEL_Msk (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos)
14415#define RCC_D3CCIPR_SAI4ASEL RCC_D3CCIPR_SAI4ASEL_Msk
14416#define RCC_D3CCIPR_SAI4ASEL_0 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos)
14417#define RCC_D3CCIPR_SAI4ASEL_1 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos)
14418#define RCC_D3CCIPR_SAI4ASEL_2 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos)
14420#define RCC_D3CCIPR_SAI4BSEL_Pos (24U)
14421#define RCC_D3CCIPR_SAI4BSEL_Msk (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos)
14422#define RCC_D3CCIPR_SAI4BSEL RCC_D3CCIPR_SAI4BSEL_Msk
14423#define RCC_D3CCIPR_SAI4BSEL_0 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos)
14424#define RCC_D3CCIPR_SAI4BSEL_1 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos)
14425#define RCC_D3CCIPR_SAI4BSEL_2 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos)
14427#define RCC_D3CCIPR_ADCSEL_Pos (16U)
14428#define RCC_D3CCIPR_ADCSEL_Msk (0x3UL << RCC_D3CCIPR_ADCSEL_Pos)
14429#define RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_Msk
14430#define RCC_D3CCIPR_ADCSEL_0 (0x1UL << RCC_D3CCIPR_ADCSEL_Pos)
14431#define RCC_D3CCIPR_ADCSEL_1 (0x2UL << RCC_D3CCIPR_ADCSEL_Pos)
14433#define RCC_D3CCIPR_SPI6SEL_Pos (28U)
14434#define RCC_D3CCIPR_SPI6SEL_Msk (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos)
14435#define RCC_D3CCIPR_SPI6SEL RCC_D3CCIPR_SPI6SEL_Msk
14436#define RCC_D3CCIPR_SPI6SEL_0 (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos)
14437#define RCC_D3CCIPR_SPI6SEL_1 (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos)
14438#define RCC_D3CCIPR_SPI6SEL_2 (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos)
14439/******************** Bit definition for RCC_CIER register ******************/
14440#define RCC_CIER_LSIRDYIE_Pos (0U)
14441#define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos)
14442#define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
14443#define RCC_CIER_LSERDYIE_Pos (1U)
14444#define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos)
14445#define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
14446#define RCC_CIER_HSIRDYIE_Pos (2U)
14447#define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos)
14448#define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
14449#define RCC_CIER_HSERDYIE_Pos (3U)
14450#define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos)
14451#define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
14452#define RCC_CIER_CSIRDYIE_Pos (4U)
14453#define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos)
14454#define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk
14455#define RCC_CIER_HSI48RDYIE_Pos (5U)
14456#define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos)
14457#define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
14458#define RCC_CIER_PLL1RDYIE_Pos (6U)
14459#define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos)
14460#define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk
14461#define RCC_CIER_PLL2RDYIE_Pos (7U)
14462#define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos)
14463#define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk
14464#define RCC_CIER_PLL3RDYIE_Pos (8U)
14465#define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos)
14466#define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk
14467#define RCC_CIER_LSECSSIE_Pos (9U)
14468#define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos)
14469#define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
14470
14471/******************** Bit definition for RCC_CIFR register ******************/
14472#define RCC_CIFR_LSIRDYF_Pos (0U)
14473#define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos)
14474#define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
14475#define RCC_CIFR_LSERDYF_Pos (1U)
14476#define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos)
14477#define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
14478#define RCC_CIFR_HSIRDYF_Pos (2U)
14479#define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos)
14480#define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
14481#define RCC_CIFR_HSERDYF_Pos (3U)
14482#define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos)
14483#define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
14484#define RCC_CIFR_CSIRDYF_Pos (4U)
14485#define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos)
14486#define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk
14487#define RCC_CIFR_HSI48RDYF_Pos (5U)
14488#define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos)
14489#define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
14490#define RCC_CIFR_PLLRDYF_Pos (6U)
14491#define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos)
14492#define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
14493#define RCC_CIFR_PLL2RDYF_Pos (7U)
14494#define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos)
14495#define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk
14496#define RCC_CIFR_PLL3RDYF_Pos (8U)
14497#define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos)
14498#define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk
14499#define RCC_CIFR_LSECSSF_Pos (9U)
14500#define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos)
14501#define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
14502#define RCC_CIFR_HSECSSF_Pos (10U)
14503#define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos)
14504#define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk
14505
14506/******************** Bit definition for RCC_CICR register ******************/
14507#define RCC_CICR_LSIRDYC_Pos (0U)
14508#define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos)
14509#define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
14510#define RCC_CICR_LSERDYC_Pos (1U)
14511#define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos)
14512#define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
14513#define RCC_CICR_HSIRDYC_Pos (2U)
14514#define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos)
14515#define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
14516#define RCC_CICR_HSERDYC_Pos (3U)
14517#define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos)
14518#define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
14519#define RCC_CICR_CSIRDYC_Pos (4U)
14520#define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos)
14521#define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk
14522#define RCC_CICR_HSI48RDYC_Pos (5U)
14523#define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos)
14524#define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
14525#define RCC_CICR_PLLRDYC_Pos (6U)
14526#define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos)
14527#define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
14528#define RCC_CICR_PLL2RDYC_Pos (7U)
14529#define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos)
14530#define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk
14531#define RCC_CICR_PLL3RDYC_Pos (8U)
14532#define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos)
14533#define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk
14534#define RCC_CICR_LSECSSC_Pos (9U)
14535#define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos)
14536#define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
14537#define RCC_CICR_HSECSSC_Pos (10U)
14538#define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos)
14539#define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk
14540
14541/******************** Bit definition for RCC_BDCR register ******************/
14542#define RCC_BDCR_LSEON_Pos (0U)
14543#define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)
14544#define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
14545#define RCC_BDCR_LSERDY_Pos (1U)
14546#define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)
14547#define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
14548#define RCC_BDCR_LSEBYP_Pos (2U)
14549#define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)
14550#define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
14551
14552#define RCC_BDCR_LSEDRV_Pos (3U)
14553#define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos)
14554#define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
14555#define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos)
14556#define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos)
14558#define RCC_BDCR_LSECSSON_Pos (5U)
14559#define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos)
14560#define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
14561#define RCC_BDCR_LSECSSD_Pos (6U)
14562#define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos)
14563#define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
14564
14565#define RCC_BDCR_RTCSEL_Pos (8U)
14566#define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)
14567#define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
14568#define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)
14569#define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)
14571#define RCC_BDCR_RTCEN_Pos (15U)
14572#define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)
14573#define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
14574#define RCC_BDCR_BDRST_Pos (16U)
14575#define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)
14576#define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
14577/******************** Bit definition for RCC_CSR register *******************/
14578#define RCC_CSR_LSION_Pos (0U)
14579#define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)
14580#define RCC_CSR_LSION RCC_CSR_LSION_Msk
14581#define RCC_CSR_LSIRDY_Pos (1U)
14582#define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)
14583#define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
14584
14585
14586/******************** Bit definition for RCC_AHB3ENR register **************/
14587#define RCC_AHB3ENR_MDMAEN_Pos (0U)
14588#define RCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)
14589#define RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk
14590#define RCC_AHB3ENR_DMA2DEN_Pos (4U)
14591#define RCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)
14592#define RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk
14593#define RCC_AHB3ENR_FMCEN_Pos (12U)
14594#define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos)
14595#define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
14596#define RCC_AHB3ENR_QSPIEN_Pos (14U)
14597#define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)
14598#define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
14599#define RCC_AHB3ENR_SDMMC1EN_Pos (16U)
14600#define RCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)
14601#define RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk
14602
14603/******************** Bit definition for RCC_AHB1ENR register ***************/
14604#define RCC_AHB1ENR_DMA1EN_Pos (0U)
14605#define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)
14606#define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
14607#define RCC_AHB1ENR_DMA2EN_Pos (1U)
14608#define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)
14609#define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
14610#define RCC_AHB1ENR_ADC12EN_Pos (5U)
14611#define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)
14612#define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk
14613#define RCC_AHB1ENR_ETH1MACEN_Pos (15U)
14614#define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)
14615#define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk
14616#define RCC_AHB1ENR_ETH1TXEN_Pos (16U)
14617#define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)
14618#define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk
14619#define RCC_AHB1ENR_ETH1RXEN_Pos (17U)
14620#define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)
14621#define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk
14622#define RCC_AHB1ENR_USB1OTGHSEN_Pos (25U)
14623#define RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)
14624#define RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk
14625#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U)
14626#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos)
14627#define RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
14628#define RCC_AHB1ENR_USB2OTGFSEN_Pos (27U)
14629#define RCC_AHB1ENR_USB2OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)
14630#define RCC_AHB1ENR_USB2OTGFSEN RCC_AHB1ENR_USB2OTGFSEN_Msk
14631#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos (28U)
14632#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos)
14633#define RCC_AHB1ENR_USB2OTGFSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
14634
14635/* Legacy define */
14636#define RCC_AHB1ENR_USB2OTGHSEN_Pos RCC_AHB1ENR_USB2OTGFSEN_Pos
14637#define RCC_AHB1ENR_USB2OTGHSEN_Msk RCC_AHB1ENR_USB2OTGFSEN_Msk
14638#define RCC_AHB1ENR_USB2OTGHSEN RCC_AHB1ENR_USB2OTGFSEN
14639#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos RCC_AHB1ENR_USB2OTGFSULPIEN_Pos
14640#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
14641#define RCC_AHB1ENR_USB2OTGHSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN
14642
14643
14644/******************** Bit definition for RCC_AHB2ENR register ***************/
14645#define RCC_AHB2ENR_DCMIEN_Pos (0U)
14646#define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)
14647#define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
14648#define RCC_AHB2ENR_RNGEN_Pos (6U)
14649#define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos)
14650#define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
14651#define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
14652#define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)
14653#define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
14654#define RCC_AHB2ENR_SRAM1EN_Pos (29U)
14655#define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)
14656#define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk
14657#define RCC_AHB2ENR_SRAM2EN_Pos (30U)
14658#define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)
14659#define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk
14660#define RCC_AHB2ENR_SRAM3EN_Pos (31U)
14661#define RCC_AHB2ENR_SRAM3EN_Msk (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)
14662#define RCC_AHB2ENR_SRAM3EN RCC_AHB2ENR_SRAM3EN_Msk
14663
14664/* Legacy define */
14665#define RCC_AHB2ENR_D2SRAM1EN_Pos RCC_AHB2ENR_SRAM1EN_Pos
14666#define RCC_AHB2ENR_D2SRAM1EN_Msk RCC_AHB2ENR_SRAM1EN_Msk
14667#define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_SRAM1EN
14668#define RCC_AHB2ENR_D2SRAM2EN_Pos RCC_AHB2ENR_SRAM2EN_Pos
14669#define RCC_AHB2ENR_D2SRAM2EN_Msk RCC_AHB2ENR_SRAM2EN_Msk
14670#define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_SRAM2EN
14671#define RCC_AHB2ENR_D2SRAM3EN_Pos RCC_AHB2ENR_SRAM3EN_Pos
14672#define RCC_AHB2ENR_D2SRAM3EN_Msk RCC_AHB2ENR_SRAM3EN_Msk
14673#define RCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_SRAM3EN
14674
14675/******************** Bit definition for RCC_AHB4ENR register ******************/
14676#define RCC_AHB4ENR_GPIOAEN_Pos (0U)
14677#define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)
14678#define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk
14679#define RCC_AHB4ENR_GPIOBEN_Pos (1U)
14680#define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)
14681#define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk
14682#define RCC_AHB4ENR_GPIOCEN_Pos (2U)
14683#define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)
14684#define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk
14685#define RCC_AHB4ENR_GPIODEN_Pos (3U)
14686#define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)
14687#define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk
14688#define RCC_AHB4ENR_GPIOEEN_Pos (4U)
14689#define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)
14690#define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk
14691#define RCC_AHB4ENR_GPIOFEN_Pos (5U)
14692#define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)
14693#define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk
14694#define RCC_AHB4ENR_GPIOGEN_Pos (6U)
14695#define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)
14696#define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk
14697#define RCC_AHB4ENR_GPIOHEN_Pos (7U)
14698#define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)
14699#define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk
14700#define RCC_AHB4ENR_GPIOIEN_Pos (8U)
14701#define RCC_AHB4ENR_GPIOIEN_Msk (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)
14702#define RCC_AHB4ENR_GPIOIEN RCC_AHB4ENR_GPIOIEN_Msk
14703#define RCC_AHB4ENR_GPIOJEN_Pos (9U)
14704#define RCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)
14705#define RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk
14706#define RCC_AHB4ENR_GPIOKEN_Pos (10U)
14707#define RCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)
14708#define RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk
14709#define RCC_AHB4ENR_CRCEN_Pos (19U)
14710#define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos)
14711#define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk
14712#define RCC_AHB4ENR_BDMAEN_Pos (21U)
14713#define RCC_AHB4ENR_BDMAEN_Msk (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)
14714#define RCC_AHB4ENR_BDMAEN RCC_AHB4ENR_BDMAEN_Msk
14715#define RCC_AHB4ENR_ADC3EN_Pos (24U)
14716#define RCC_AHB4ENR_ADC3EN_Msk (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)
14717#define RCC_AHB4ENR_ADC3EN RCC_AHB4ENR_ADC3EN_Msk
14718#define RCC_AHB4ENR_HSEMEN_Pos (25U)
14719#define RCC_AHB4ENR_HSEMEN_Msk (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)
14720#define RCC_AHB4ENR_HSEMEN RCC_AHB4ENR_HSEMEN_Msk
14721#define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
14722#define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)
14723#define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
14724
14725/******************** Bit definition for RCC_APB3ENR register ******************/
14726#define RCC_APB3ENR_WWDG1EN_Pos (6U)
14727#define RCC_APB3ENR_WWDG1EN_Msk (0x1UL << RCC_APB3ENR_WWDG1EN_Pos)
14728#define RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDG1EN_Msk
14729
14730/******************** Bit definition for RCC_APB1LENR register ******************/
14731
14732#define RCC_APB1LENR_TIM2EN_Pos (0U)
14733#define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos)
14734#define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk
14735#define RCC_APB1LENR_TIM3EN_Pos (1U)
14736#define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos)
14737#define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk
14738#define RCC_APB1LENR_TIM4EN_Pos (2U)
14739#define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos)
14740#define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk
14741#define RCC_APB1LENR_TIM5EN_Pos (3U)
14742#define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos)
14743#define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk
14744#define RCC_APB1LENR_TIM6EN_Pos (4U)
14745#define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos)
14746#define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk
14747#define RCC_APB1LENR_TIM7EN_Pos (5U)
14748#define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos)
14749#define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk
14750#define RCC_APB1LENR_TIM12EN_Pos (6U)
14751#define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos)
14752#define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk
14753#define RCC_APB1LENR_TIM13EN_Pos (7U)
14754#define RCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos)
14755#define RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk
14756#define RCC_APB1LENR_TIM14EN_Pos (8U)
14757#define RCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos)
14758#define RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk
14759#define RCC_APB1LENR_LPTIM1EN_Pos (9U)
14760#define RCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos)
14761#define RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk
14762
14763
14764#define RCC_APB1LENR_SPI2EN_Pos (14U)
14765#define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos)
14766#define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk
14767#define RCC_APB1LENR_SPI3EN_Pos (15U)
14768#define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos)
14769#define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk
14770#define RCC_APB1LENR_SPDIFRXEN_Pos (16U)
14771#define RCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos)
14772#define RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk
14773#define RCC_APB1LENR_USART2EN_Pos (17U)
14774#define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos)
14775#define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk
14776#define RCC_APB1LENR_USART3EN_Pos (18U)
14777#define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos)
14778#define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk
14779#define RCC_APB1LENR_UART4EN_Pos (19U)
14780#define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos)
14781#define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk
14782#define RCC_APB1LENR_UART5EN_Pos (20U)
14783#define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos)
14784#define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk
14785#define RCC_APB1LENR_I2C1EN_Pos (21U)
14786#define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos)
14787#define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk
14788#define RCC_APB1LENR_I2C2EN_Pos (22U)
14789#define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos)
14790#define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk
14791#define RCC_APB1LENR_I2C3EN_Pos (23U)
14792#define RCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos)
14793#define RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk
14794#define RCC_APB1LENR_CECEN_Pos (27U)
14795#define RCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos)
14796#define RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk
14797#define RCC_APB1LENR_DAC12EN_Pos (29U)
14798#define RCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos)
14799#define RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk
14800#define RCC_APB1LENR_UART7EN_Pos (30U)
14801#define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos)
14802#define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk
14803#define RCC_APB1LENR_UART8EN_Pos (31U)
14804#define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos)
14805#define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
14806
14807/* Legacy define */
14808#define RCC_APB1LENR_HDMICECEN_Pos RCC_APB1LENR_CECEN_Pos
14809#define RCC_APB1LENR_HDMICECEN_Msk RCC_APB1LENR_CECEN_Msk
14810#define RCC_APB1LENR_HDMICECEN RCC_APB1LENR_CECEN
14811/******************** Bit definition for RCC_APB1HENR register ******************/
14812#define RCC_APB1HENR_CRSEN_Pos (1U)
14813#define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos)
14814#define RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk
14815#define RCC_APB1HENR_SWPMIEN_Pos (2U)
14816#define RCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos)
14817#define RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk
14818#define RCC_APB1HENR_OPAMPEN_Pos (4U)
14819#define RCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos)
14820#define RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk
14821#define RCC_APB1HENR_MDIOSEN_Pos (5U)
14822#define RCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos)
14823#define RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk
14824#define RCC_APB1HENR_FDCANEN_Pos (8U)
14825#define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos)
14826#define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk
14827
14828/******************** Bit definition for RCC_APB2ENR register ******************/
14829#define RCC_APB2ENR_TIM1EN_Pos (0U)
14830#define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)
14831#define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
14832#define RCC_APB2ENR_TIM8EN_Pos (1U)
14833#define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos)
14834#define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
14835#define RCC_APB2ENR_USART1EN_Pos (4U)
14836#define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)
14837#define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
14838#define RCC_APB2ENR_USART6EN_Pos (5U)
14839#define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos)
14840#define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
14841#define RCC_APB2ENR_SPI1EN_Pos (12U)
14842#define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)
14843#define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
14844#define RCC_APB2ENR_SPI4EN_Pos (13U)
14845#define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos)
14846#define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
14847#define RCC_APB2ENR_TIM15EN_Pos (16U)
14848#define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos)
14849#define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
14850#define RCC_APB2ENR_TIM16EN_Pos (17U)
14851#define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos)
14852#define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
14853#define RCC_APB2ENR_TIM17EN_Pos (18U)
14854#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos)
14855#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
14856#define RCC_APB2ENR_SPI5EN_Pos (20U)
14857#define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos)
14858#define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
14859#define RCC_APB2ENR_SAI1EN_Pos (22U)
14860#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos)
14861#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
14862#define RCC_APB2ENR_SAI2EN_Pos (23U)
14863#define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos)
14864#define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
14865#define RCC_APB2ENR_SAI3EN_Pos (24U)
14866#define RCC_APB2ENR_SAI3EN_Msk (0x1UL << RCC_APB2ENR_SAI3EN_Pos)
14867#define RCC_APB2ENR_SAI3EN RCC_APB2ENR_SAI3EN_Msk
14868#define RCC_APB2ENR_DFSDM1EN_Pos (28U)
14869#define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos)
14870#define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
14871#define RCC_APB2ENR_HRTIMEN_Pos (29U)
14872#define RCC_APB2ENR_HRTIMEN_Msk (0x1UL << RCC_APB2ENR_HRTIMEN_Pos)
14873#define RCC_APB2ENR_HRTIMEN RCC_APB2ENR_HRTIMEN_Msk
14874
14875/******************** Bit definition for RCC_APB4ENR register ******************/
14876#define RCC_APB4ENR_SYSCFGEN_Pos (1U)
14877#define RCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos)
14878#define RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk
14879#define RCC_APB4ENR_LPUART1EN_Pos (3U)
14880#define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos)
14881#define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk
14882#define RCC_APB4ENR_SPI6EN_Pos (5U)
14883#define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos)
14884#define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk
14885#define RCC_APB4ENR_I2C4EN_Pos (7U)
14886#define RCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos)
14887#define RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk
14888#define RCC_APB4ENR_LPTIM2EN_Pos (9U)
14889#define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos)
14890#define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk
14891#define RCC_APB4ENR_LPTIM3EN_Pos (10U)
14892#define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos)
14893#define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk
14894#define RCC_APB4ENR_LPTIM4EN_Pos (11U)
14895#define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos)
14896#define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk
14897#define RCC_APB4ENR_LPTIM5EN_Pos (12U)
14898#define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos)
14899#define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk
14900#define RCC_APB4ENR_COMP12EN_Pos (14U)
14901#define RCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos)
14902#define RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk
14903#define RCC_APB4ENR_VREFEN_Pos (15U)
14904#define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos)
14905#define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk
14906#define RCC_APB4ENR_RTCAPBEN_Pos (16U)
14907#define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos)
14908#define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk
14909#define RCC_APB4ENR_SAI4EN_Pos (21U)
14910#define RCC_APB4ENR_SAI4EN_Msk (0x1UL << RCC_APB4ENR_SAI4EN_Pos)
14911#define RCC_APB4ENR_SAI4EN RCC_APB4ENR_SAI4EN_Msk
14912
14913
14914/******************** Bit definition for RCC_AHB3RSTR register ***************/
14915#define RCC_AHB3RSTR_MDMARST_Pos (0U)
14916#define RCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)
14917#define RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk
14918#define RCC_AHB3RSTR_DMA2DRST_Pos (4U)
14919#define RCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)
14920#define RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk
14921#define RCC_AHB3RSTR_FMCRST_Pos (12U)
14922#define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)
14923#define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
14924#define RCC_AHB3RSTR_QSPIRST_Pos (14U)
14925#define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)
14926#define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
14927#define RCC_AHB3RSTR_SDMMC1RST_Pos (16U)
14928#define RCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)
14929#define RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk
14930
14931
14932/******************** Bit definition for RCC_AHB1RSTR register ***************/
14933#define RCC_AHB1RSTR_DMA1RST_Pos (0U)
14934#define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)
14935#define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
14936#define RCC_AHB1RSTR_DMA2RST_Pos (1U)
14937#define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)
14938#define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
14939#define RCC_AHB1RSTR_ADC12RST_Pos (5U)
14940#define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)
14941#define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk
14942#define RCC_AHB1RSTR_ETH1MACRST_Pos (15U)
14943#define RCC_AHB1RSTR_ETH1MACRST_Msk (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)
14944#define RCC_AHB1RSTR_ETH1MACRST RCC_AHB1RSTR_ETH1MACRST_Msk
14945#define RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U)
14946#define RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos)
14947#define RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk
14948#define RCC_AHB1RSTR_USB2OTGFSRST_Pos (27U)
14949#define RCC_AHB1RSTR_USB2OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos)
14950#define RCC_AHB1RSTR_USB2OTGFSRST RCC_AHB1RSTR_USB2OTGFSRST_Msk
14951
14952/* Legacy define */
14953#define RCC_AHB1RSTR_USB2OTGHSRST_Pos RCC_AHB1RSTR_USB2OTGFSRST_Pos
14954#define RCC_AHB1RSTR_USB2OTGHSRST_Msk RCC_AHB1RSTR_USB2OTGFSRST_Msk
14955#define RCC_AHB1RSTR_USB2OTGHSRST RCC_AHB1RSTR_USB2OTGFSRST
14956
14957/******************** Bit definition for RCC_AHB2RSTR register ***************/
14958#define RCC_AHB2RSTR_DCMIRST_Pos (0U)
14959#define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)
14960#define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
14961#define RCC_AHB2RSTR_RNGRST_Pos (6U)
14962#define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)
14963#define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
14964#define RCC_AHB2RSTR_SDMMC2RST_Pos (9U)
14965#define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)
14966#define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk
14967
14968/******************** Bit definition for RCC_AHB4RSTR register ******************/
14969#define RCC_AHB4RSTR_GPIOARST_Pos (0U)
14970#define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)
14971#define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk
14972#define RCC_AHB4RSTR_GPIOBRST_Pos (1U)
14973#define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)
14974#define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk
14975#define RCC_AHB4RSTR_GPIOCRST_Pos (2U)
14976#define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)
14977#define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk
14978#define RCC_AHB4RSTR_GPIODRST_Pos (3U)
14979#define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)
14980#define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk
14981#define RCC_AHB4RSTR_GPIOERST_Pos (4U)
14982#define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)
14983#define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk
14984#define RCC_AHB4RSTR_GPIOFRST_Pos (5U)
14985#define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)
14986#define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk
14987#define RCC_AHB4RSTR_GPIOGRST_Pos (6U)
14988#define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)
14989#define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk
14990#define RCC_AHB4RSTR_GPIOHRST_Pos (7U)
14991#define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)
14992#define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk
14993#define RCC_AHB4RSTR_GPIOIRST_Pos (8U)
14994#define RCC_AHB4RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)
14995#define RCC_AHB4RSTR_GPIOIRST RCC_AHB4RSTR_GPIOIRST_Msk
14996#define RCC_AHB4RSTR_GPIOJRST_Pos (9U)
14997#define RCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)
14998#define RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk
14999#define RCC_AHB4RSTR_GPIOKRST_Pos (10U)
15000#define RCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)
15001#define RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk
15002#define RCC_AHB4RSTR_CRCRST_Pos (19U)
15003#define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)
15004#define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk
15005#define RCC_AHB4RSTR_BDMARST_Pos (21U)
15006#define RCC_AHB4RSTR_BDMARST_Msk (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)
15007#define RCC_AHB4RSTR_BDMARST RCC_AHB4RSTR_BDMARST_Msk
15008#define RCC_AHB4RSTR_ADC3RST_Pos (24U)
15009#define RCC_AHB4RSTR_ADC3RST_Msk (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)
15010#define RCC_AHB4RSTR_ADC3RST RCC_AHB4RSTR_ADC3RST_Msk
15011#define RCC_AHB4RSTR_HSEMRST_Pos (25U)
15012#define RCC_AHB4RSTR_HSEMRST_Msk (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)
15013#define RCC_AHB4RSTR_HSEMRST RCC_AHB4RSTR_HSEMRST_Msk
15014
15015
15016/******************** Bit definition for RCC_APB3RSTR register ******************/
15017
15018/******************** Bit definition for RCC_APB1LRSTR register ******************/
15019
15020#define RCC_APB1LRSTR_TIM2RST_Pos (0U)
15021#define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos)
15022#define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk
15023#define RCC_APB1LRSTR_TIM3RST_Pos (1U)
15024#define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos)
15025#define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk
15026#define RCC_APB1LRSTR_TIM4RST_Pos (2U)
15027#define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos)
15028#define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk
15029#define RCC_APB1LRSTR_TIM5RST_Pos (3U)
15030#define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos)
15031#define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk
15032#define RCC_APB1LRSTR_TIM6RST_Pos (4U)
15033#define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos)
15034#define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk
15035#define RCC_APB1LRSTR_TIM7RST_Pos (5U)
15036#define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos)
15037#define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk
15038#define RCC_APB1LRSTR_TIM12RST_Pos (6U)
15039#define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos)
15040#define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk
15041#define RCC_APB1LRSTR_TIM13RST_Pos (7U)
15042#define RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos)
15043#define RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk
15044#define RCC_APB1LRSTR_TIM14RST_Pos (8U)
15045#define RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos)
15046#define RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk
15047#define RCC_APB1LRSTR_LPTIM1RST_Pos (9U)
15048#define RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos)
15049#define RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk
15050#define RCC_APB1LRSTR_SPI2RST_Pos (14U)
15051#define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos)
15052#define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk
15053#define RCC_APB1LRSTR_SPI3RST_Pos (15U)
15054#define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos)
15055#define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk
15056#define RCC_APB1LRSTR_SPDIFRXRST_Pos (16U)
15057#define RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos)
15058#define RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk
15059#define RCC_APB1LRSTR_USART2RST_Pos (17U)
15060#define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos)
15061#define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk
15062#define RCC_APB1LRSTR_USART3RST_Pos (18U)
15063#define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos)
15064#define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk
15065#define RCC_APB1LRSTR_UART4RST_Pos (19U)
15066#define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos)
15067#define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk
15068#define RCC_APB1LRSTR_UART5RST_Pos (20U)
15069#define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos)
15070#define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk
15071#define RCC_APB1LRSTR_I2C1RST_Pos (21U)
15072#define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos)
15073#define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk
15074#define RCC_APB1LRSTR_I2C2RST_Pos (22U)
15075#define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos)
15076#define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk
15077#define RCC_APB1LRSTR_I2C3RST_Pos (23U)
15078#define RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos)
15079#define RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk
15080#define RCC_APB1LRSTR_CECRST_Pos (27U)
15081#define RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos)
15082#define RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk
15083#define RCC_APB1LRSTR_DAC12RST_Pos (29U)
15084#define RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos)
15085#define RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk
15086#define RCC_APB1LRSTR_UART7RST_Pos (30U)
15087#define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos)
15088#define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk
15089#define RCC_APB1LRSTR_UART8RST_Pos (31U)
15090#define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos)
15091#define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
15092
15093/* Legacy define */
15094#define RCC_APB1LRSTR_HDMICECRST_Pos RCC_APB1LRSTR_CECRST_Pos
15095#define RCC_APB1LRSTR_HDMICECRST_Msk RCC_APB1LRSTR_CECRST_Msk
15096#define RCC_APB1LRSTR_HDMICECRST RCC_APB1LRSTR_CECRST
15097/******************** Bit definition for RCC_APB1HRSTR register ******************/
15098#define RCC_APB1HRSTR_CRSRST_Pos (1U)
15099#define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos)
15100#define RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk
15101#define RCC_APB1HRSTR_SWPMIRST_Pos (2U)
15102#define RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos)
15103#define RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk
15104#define RCC_APB1HRSTR_OPAMPRST_Pos (4U)
15105#define RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos)
15106#define RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk
15107#define RCC_APB1HRSTR_MDIOSRST_Pos (5U)
15108#define RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos)
15109#define RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk
15110#define RCC_APB1HRSTR_FDCANRST_Pos (8U)
15111#define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos)
15112#define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk
15113
15114/******************** Bit definition for RCC_APB2RSTR register ******************/
15115#define RCC_APB2RSTR_TIM1RST_Pos (0U)
15116#define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)
15117#define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
15118#define RCC_APB2RSTR_TIM8RST_Pos (1U)
15119#define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos)
15120#define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
15121#define RCC_APB2RSTR_USART1RST_Pos (4U)
15122#define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)
15123#define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
15124#define RCC_APB2RSTR_USART6RST_Pos (5U)
15125#define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos)
15126#define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
15127#define RCC_APB2RSTR_SPI1RST_Pos (12U)
15128#define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)
15129#define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
15130#define RCC_APB2RSTR_SPI4RST_Pos (13U)
15131#define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos)
15132#define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
15133#define RCC_APB2RSTR_TIM15RST_Pos (16U)
15134#define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos)
15135#define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
15136#define RCC_APB2RSTR_TIM16RST_Pos (17U)
15137#define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos)
15138#define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
15139#define RCC_APB2RSTR_TIM17RST_Pos (18U)
15140#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos)
15141#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
15142#define RCC_APB2RSTR_SPI5RST_Pos (20U)
15143#define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos)
15144#define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
15145#define RCC_APB2RSTR_SAI1RST_Pos (22U)
15146#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos)
15147#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
15148#define RCC_APB2RSTR_SAI2RST_Pos (23U)
15149#define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos)
15150#define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
15151#define RCC_APB2RSTR_SAI3RST_Pos (24U)
15152#define RCC_APB2RSTR_SAI3RST_Msk (0x1UL << RCC_APB2RSTR_SAI3RST_Pos)
15153#define RCC_APB2RSTR_SAI3RST RCC_APB2RSTR_SAI3RST_Msk
15154#define RCC_APB2RSTR_DFSDM1RST_Pos (28U)
15155#define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos)
15156#define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
15157#define RCC_APB2RSTR_HRTIMRST_Pos (29U)
15158#define RCC_APB2RSTR_HRTIMRST_Msk (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos)
15159#define RCC_APB2RSTR_HRTIMRST RCC_APB2RSTR_HRTIMRST_Msk
15160
15161/******************** Bit definition for RCC_APB4RSTR register ******************/
15162#define RCC_APB4RSTR_SYSCFGRST_Pos (1U)
15163#define RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos)
15164#define RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk
15165#define RCC_APB4RSTR_LPUART1RST_Pos (3U)
15166#define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos)
15167#define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk
15168#define RCC_APB4RSTR_SPI6RST_Pos (5U)
15169#define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos)
15170#define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk
15171#define RCC_APB4RSTR_I2C4RST_Pos (7U)
15172#define RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos)
15173#define RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk
15174#define RCC_APB4RSTR_LPTIM2RST_Pos (9U)
15175#define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos)
15176#define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk
15177#define RCC_APB4RSTR_LPTIM3RST_Pos (10U)
15178#define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos)
15179#define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk
15180#define RCC_APB4RSTR_LPTIM4RST_Pos (11U)
15181#define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos)
15182#define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk
15183#define RCC_APB4RSTR_LPTIM5RST_Pos (12U)
15184#define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos)
15185#define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk
15186#define RCC_APB4RSTR_COMP12RST_Pos (14U)
15187#define RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos)
15188#define RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk
15189#define RCC_APB4RSTR_VREFRST_Pos (15U)
15190#define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos)
15191#define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk
15192#define RCC_APB4RSTR_SAI4RST_Pos (21U)
15193#define RCC_APB4RSTR_SAI4RST_Msk (0x1UL << RCC_APB4RSTR_SAI4RST_Pos)
15194#define RCC_APB4RSTR_SAI4RST RCC_APB4RSTR_SAI4RST_Msk
15195
15196
15197/******************** Bit definition for RCC_GCR register ********************/
15198#define RCC_GCR_WW1RSC_Pos (0U)
15199#define RCC_GCR_WW1RSC_Msk (0x1UL << RCC_GCR_WW1RSC_Pos)
15200#define RCC_GCR_WW1RSC RCC_GCR_WW1RSC_Msk
15201
15202/******************** Bit definition for RCC_D3AMR register ********************/
15203#define RCC_D3AMR_BDMAAMEN_Pos (0U)
15204#define RCC_D3AMR_BDMAAMEN_Msk (0x1UL << RCC_D3AMR_BDMAAMEN_Pos)
15205#define RCC_D3AMR_BDMAAMEN RCC_D3AMR_BDMAAMEN_Msk
15206#define RCC_D3AMR_LPUART1AMEN_Pos (3U)
15207#define RCC_D3AMR_LPUART1AMEN_Msk (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos)
15208#define RCC_D3AMR_LPUART1AMEN RCC_D3AMR_LPUART1AMEN_Msk
15209#define RCC_D3AMR_SPI6AMEN_Pos (5U)
15210#define RCC_D3AMR_SPI6AMEN_Msk (0x1UL << RCC_D3AMR_SPI6AMEN_Pos)
15211#define RCC_D3AMR_SPI6AMEN RCC_D3AMR_SPI6AMEN_Msk
15212#define RCC_D3AMR_I2C4AMEN_Pos (7U)
15213#define RCC_D3AMR_I2C4AMEN_Msk (0x1UL << RCC_D3AMR_I2C4AMEN_Pos)
15214#define RCC_D3AMR_I2C4AMEN RCC_D3AMR_I2C4AMEN_Msk
15215#define RCC_D3AMR_LPTIM2AMEN_Pos (9U)
15216#define RCC_D3AMR_LPTIM2AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos)
15217#define RCC_D3AMR_LPTIM2AMEN RCC_D3AMR_LPTIM2AMEN_Msk
15218#define RCC_D3AMR_LPTIM3AMEN_Pos (10U)
15219#define RCC_D3AMR_LPTIM3AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos)
15220#define RCC_D3AMR_LPTIM3AMEN RCC_D3AMR_LPTIM3AMEN_Msk
15221#define RCC_D3AMR_LPTIM4AMEN_Pos (11U)
15222#define RCC_D3AMR_LPTIM4AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos)
15223#define RCC_D3AMR_LPTIM4AMEN RCC_D3AMR_LPTIM4AMEN_Msk
15224#define RCC_D3AMR_LPTIM5AMEN_Pos (12U)
15225#define RCC_D3AMR_LPTIM5AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos)
15226#define RCC_D3AMR_LPTIM5AMEN RCC_D3AMR_LPTIM5AMEN_Msk
15227#define RCC_D3AMR_COMP12AMEN_Pos (14U)
15228#define RCC_D3AMR_COMP12AMEN_Msk (0x1UL << RCC_D3AMR_COMP12AMEN_Pos)
15229#define RCC_D3AMR_COMP12AMEN RCC_D3AMR_COMP12AMEN_Msk
15230#define RCC_D3AMR_VREFAMEN_Pos (15U)
15231#define RCC_D3AMR_VREFAMEN_Msk (0x1UL << RCC_D3AMR_VREFAMEN_Pos)
15232#define RCC_D3AMR_VREFAMEN RCC_D3AMR_VREFAMEN_Msk
15233#define RCC_D3AMR_RTCAMEN_Pos (16U)
15234#define RCC_D3AMR_RTCAMEN_Msk (0x1UL << RCC_D3AMR_RTCAMEN_Pos)
15235#define RCC_D3AMR_RTCAMEN RCC_D3AMR_RTCAMEN_Msk
15236#define RCC_D3AMR_CRCAMEN_Pos (19U)
15237#define RCC_D3AMR_CRCAMEN_Msk (0x1UL << RCC_D3AMR_CRCAMEN_Pos)
15238#define RCC_D3AMR_CRCAMEN RCC_D3AMR_CRCAMEN_Msk
15239#define RCC_D3AMR_SAI4AMEN_Pos (21U)
15240#define RCC_D3AMR_SAI4AMEN_Msk (0x1UL << RCC_D3AMR_SAI4AMEN_Pos)
15241#define RCC_D3AMR_SAI4AMEN RCC_D3AMR_SAI4AMEN_Msk
15242#define RCC_D3AMR_ADC3AMEN_Pos (24U)
15243#define RCC_D3AMR_ADC3AMEN_Msk (0x1UL << RCC_D3AMR_ADC3AMEN_Pos)
15244#define RCC_D3AMR_ADC3AMEN RCC_D3AMR_ADC3AMEN_Msk
15245
15246
15247#define RCC_D3AMR_BKPRAMAMEN_Pos (28U)
15248#define RCC_D3AMR_BKPRAMAMEN_Msk (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos)
15249#define RCC_D3AMR_BKPRAMAMEN RCC_D3AMR_BKPRAMAMEN_Msk
15250#define RCC_D3AMR_SRAM4AMEN_Pos (29U)
15251#define RCC_D3AMR_SRAM4AMEN_Msk (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos)
15252#define RCC_D3AMR_SRAM4AMEN RCC_D3AMR_SRAM4AMEN_Msk
15253/******************** Bit definition for RCC_AHB3LPENR register **************/
15254#define RCC_AHB3LPENR_MDMALPEN_Pos (0U)
15255#define RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)
15256#define RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk
15257#define RCC_AHB3LPENR_DMA2DLPEN_Pos (4U)
15258#define RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)
15259#define RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk
15260#define RCC_AHB3LPENR_FLASHLPEN_Pos (8U)
15261#define RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)
15262#define RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk
15263#define RCC_AHB3LPENR_FMCLPEN_Pos (12U)
15264#define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)
15265#define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
15266#define RCC_AHB3LPENR_QSPILPEN_Pos (14U)
15267#define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)
15268#define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
15269#define RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U)
15270#define RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)
15271#define RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk
15272#define RCC_AHB3LPENR_DTCM1LPEN_Pos (28U)
15273#define RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)
15274#define RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk
15275#define RCC_AHB3LPENR_DTCM2LPEN_Pos (29U)
15276#define RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)
15277#define RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk
15278#define RCC_AHB3LPENR_ITCMLPEN_Pos (30U)
15279#define RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)
15280#define RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk
15281#define RCC_AHB3LPENR_AXISRAMLPEN_Pos (31U)
15282#define RCC_AHB3LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)
15283#define RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAMLPEN_Msk
15284
15285
15286/******************** Bit definition for RCC_AHB1LPENR register ***************/
15287#define RCC_AHB1LPENR_DMA1LPEN_Pos (0U)
15288#define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos)
15289#define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
15290#define RCC_AHB1LPENR_DMA2LPEN_Pos (1U)
15291#define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos)
15292#define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
15293#define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)
15294#define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos)
15295#define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk
15296#define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U)
15297#define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos)
15298#define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk
15299#define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U)
15300#define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos)
15301#define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk
15302#define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U)
15303#define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos)
15304#define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk
15305#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U)
15306#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos)
15307#define RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
15308#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U)
15309#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos)
15310#define RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
15311#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos (27U)
15312#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos)
15313#define RCC_AHB1LPENR_USB2OTGFSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
15314#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos (28U)
15315#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos)
15316#define RCC_AHB1LPENR_USB2OTGFSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
15317
15318/* Legacy define */
15319#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos RCC_AHB1LPENR_USB2OTGFSLPEN_Pos
15320#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
15321#define RCC_AHB1LPENR_USB2OTGHSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN
15322#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos
15323#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
15324#define RCC_AHB1LPENR_USB2OTGHSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN
15325
15326/******************** Bit definition for RCC_AHB2LPENR register ***************/
15327#define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
15328#define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos)
15329#define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
15330#define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
15331#define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos)
15332#define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
15333#define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
15334#define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos)
15335#define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
15336#define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U)
15337#define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos)
15338#define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk
15339#define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U)
15340#define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos)
15341#define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk
15342#define RCC_AHB2LPENR_SRAM3LPEN_Pos (31U)
15343#define RCC_AHB2LPENR_SRAM3LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos)
15344#define RCC_AHB2LPENR_SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN_Msk
15345
15346/* Legacy define */
15347#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos RCC_AHB2LPENR_SRAM1LPEN_Pos
15348#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk RCC_AHB2LPENR_SRAM1LPEN_Msk
15349#define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN
15350#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos RCC_AHB2LPENR_SRAM2LPEN_Pos
15351#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk RCC_AHB2LPENR_SRAM2LPEN_Msk
15352#define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN
15353#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos RCC_AHB2LPENR_SRAM3LPEN_Pos
15354#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk RCC_AHB2LPENR_SRAM3LPEN_Msk
15355#define RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN
15356
15357/******************** Bit definition for RCC_AHB4LPENR register ******************/
15358#define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
15359#define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos)
15360#define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk
15361#define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)
15362#define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos)
15363#define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk
15364#define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)
15365#define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos)
15366#define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk
15367#define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)
15368#define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos)
15369#define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk
15370#define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)
15371#define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos)
15372#define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk
15373#define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)
15374#define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos)
15375#define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk
15376#define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)
15377#define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos)
15378#define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk
15379#define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)
15380#define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos)
15381#define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk
15382#define RCC_AHB4LPENR_GPIOILPEN_Pos (8U)
15383#define RCC_AHB4LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos)
15384#define RCC_AHB4LPENR_GPIOILPEN RCC_AHB4LPENR_GPIOILPEN_Msk
15385#define RCC_AHB4LPENR_GPIOJLPEN_Pos (9U)
15386#define RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos)
15387#define RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk
15388#define RCC_AHB4LPENR_GPIOKLPEN_Pos (10U)
15389#define RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos)
15390#define RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk
15391#define RCC_AHB4LPENR_CRCLPEN_Pos (19U)
15392#define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos)
15393#define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk
15394#define RCC_AHB4LPENR_BDMALPEN_Pos (21U)
15395#define RCC_AHB4LPENR_BDMALPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos)
15396#define RCC_AHB4LPENR_BDMALPEN RCC_AHB4LPENR_BDMALPEN_Msk
15397#define RCC_AHB4LPENR_ADC3LPEN_Pos (24U)
15398#define RCC_AHB4LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos)
15399#define RCC_AHB4LPENR_ADC3LPEN RCC_AHB4LPENR_ADC3LPEN_Msk
15400#define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
15401#define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos)
15402#define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
15403#define RCC_AHB4LPENR_SRAM4LPEN_Pos (29U)
15404#define RCC_AHB4LPENR_SRAM4LPEN_Msk (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos)
15405#define RCC_AHB4LPENR_SRAM4LPEN RCC_AHB4LPENR_SRAM4LPEN_Msk
15406
15407/* Legacy define */
15408#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos RCC_AHB4LPENR_SRAM4LPEN_Pos
15409#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk RCC_AHB4LPENR_SRAM4LPEN_Msk
15410#define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_SRAM4LPEN
15411/******************** Bit definition for RCC_APB3LPENR register ******************/
15412#define RCC_APB3LPENR_WWDG1LPEN_Pos (6U)
15413#define RCC_APB3LPENR_WWDG1LPEN_Msk (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos)
15414#define RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDG1LPEN_Msk
15415
15416/******************** Bit definition for RCC_APB1LLPENR register ******************/
15417
15418#define RCC_APB1LLPENR_TIM2LPEN_Pos (0U)
15419#define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos)
15420#define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk
15421#define RCC_APB1LLPENR_TIM3LPEN_Pos (1U)
15422#define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos)
15423#define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk
15424#define RCC_APB1LLPENR_TIM4LPEN_Pos (2U)
15425#define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos)
15426#define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk
15427#define RCC_APB1LLPENR_TIM5LPEN_Pos (3U)
15428#define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos)
15429#define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk
15430#define RCC_APB1LLPENR_TIM6LPEN_Pos (4U)
15431#define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos)
15432#define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk
15433#define RCC_APB1LLPENR_TIM7LPEN_Pos (5U)
15434#define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos)
15435#define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk
15436#define RCC_APB1LLPENR_TIM12LPEN_Pos (6U)
15437#define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos)
15438#define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk
15439#define RCC_APB1LLPENR_TIM13LPEN_Pos (7U)
15440#define RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos)
15441#define RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk
15442#define RCC_APB1LLPENR_TIM14LPEN_Pos (8U)
15443#define RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos)
15444#define RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk
15445#define RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U)
15446#define RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos)
15447#define RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk
15448
15449
15450#define RCC_APB1LLPENR_SPI2LPEN_Pos (14U)
15451#define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos)
15452#define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk
15453#define RCC_APB1LLPENR_SPI3LPEN_Pos (15U)
15454#define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos)
15455#define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk
15456#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U)
15457#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos)
15458#define RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk
15459#define RCC_APB1LLPENR_USART2LPEN_Pos (17U)
15460#define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos)
15461#define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk
15462#define RCC_APB1LLPENR_USART3LPEN_Pos (18U)
15463#define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos)
15464#define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk
15465#define RCC_APB1LLPENR_UART4LPEN_Pos (19U)
15466#define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos)
15467#define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk
15468#define RCC_APB1LLPENR_UART5LPEN_Pos (20U)
15469#define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos)
15470#define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk
15471#define RCC_APB1LLPENR_I2C1LPEN_Pos (21U)
15472#define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos)
15473#define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk
15474#define RCC_APB1LLPENR_I2C2LPEN_Pos (22U)
15475#define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos)
15476#define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk
15477#define RCC_APB1LLPENR_I2C3LPEN_Pos (23U)
15478#define RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos)
15479#define RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk
15480#define RCC_APB1LLPENR_CECLPEN_Pos (27U)
15481#define RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos)
15482#define RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk
15483#define RCC_APB1LLPENR_DAC12LPEN_Pos (29U)
15484#define RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos)
15485#define RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk
15486#define RCC_APB1LLPENR_UART7LPEN_Pos (30U)
15487#define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos)
15488#define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk
15489#define RCC_APB1LLPENR_UART8LPEN_Pos (31U)
15490#define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos)
15491#define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
15492
15493/* Legacy define */
15494#define RCC_APB1LLPENR_HDMICECEN_Pos RCC_APB1LLPENR_CECLPEN_Pos
15495#define RCC_APB1LLPENR_HDMICECEN_Msk RCC_APB1LLPENR_CECLPEN_Msk
15496#define RCC_APB1LLPENR_HDMICECEN RCC_APB1LLPENR_CECLPEN
15497/******************** Bit definition for RCC_APB1HLPENR register ******************/
15498#define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
15499#define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos)
15500#define RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk
15501#define RCC_APB1HLPENR_SWPMILPEN_Pos (2U)
15502#define RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos)
15503#define RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk
15504#define RCC_APB1HLPENR_OPAMPLPEN_Pos (4U)
15505#define RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos)
15506#define RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk
15507#define RCC_APB1HLPENR_MDIOSLPEN_Pos (5U)
15508#define RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos)
15509#define RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk
15510#define RCC_APB1HLPENR_FDCANLPEN_Pos (8U)
15511#define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos)
15512#define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk
15513
15514/******************** Bit definition for RCC_APB2LPENR register ******************/
15515#define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
15516#define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos)
15517#define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
15518#define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
15519#define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos)
15520#define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
15521#define RCC_APB2LPENR_USART1LPEN_Pos (4U)
15522#define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos)
15523#define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
15524#define RCC_APB2LPENR_USART6LPEN_Pos (5U)
15525#define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos)
15526#define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
15527#define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
15528#define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos)
15529#define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
15530#define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
15531#define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos)
15532#define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
15533#define RCC_APB2LPENR_TIM15LPEN_Pos (16U)
15534#define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos)
15535#define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk
15536#define RCC_APB2LPENR_TIM16LPEN_Pos (17U)
15537#define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos)
15538#define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk
15539#define RCC_APB2LPENR_TIM17LPEN_Pos (18U)
15540#define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos)
15541#define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk
15542#define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
15543#define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos)
15544#define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
15545#define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
15546#define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos)
15547#define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
15548#define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
15549#define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos)
15550#define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
15551#define RCC_APB2LPENR_SAI3LPEN_Pos (24U)
15552#define RCC_APB2LPENR_SAI3LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos)
15553#define RCC_APB2LPENR_SAI3LPEN RCC_APB2LPENR_SAI3LPEN_Msk
15554#define RCC_APB2LPENR_DFSDM1LPEN_Pos (28U)
15555#define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos)
15556#define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
15557#define RCC_APB2LPENR_HRTIMLPEN_Pos (29U)
15558#define RCC_APB2LPENR_HRTIMLPEN_Msk (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos)
15559#define RCC_APB2LPENR_HRTIMLPEN RCC_APB2LPENR_HRTIMLPEN_Msk
15560
15561/******************** Bit definition for RCC_APB4LPENR register ******************/
15562#define RCC_APB4LPENR_SYSCFGLPEN_Pos (1U)
15563#define RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos)
15564#define RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk
15565#define RCC_APB4LPENR_LPUART1LPEN_Pos (3U)
15566#define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos)
15567#define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk
15568#define RCC_APB4LPENR_SPI6LPEN_Pos (5U)
15569#define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos)
15570#define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk
15571#define RCC_APB4LPENR_I2C4LPEN_Pos (7U)
15572#define RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos)
15573#define RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk
15574#define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U)
15575#define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos)
15576#define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk
15577#define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U)
15578#define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos)
15579#define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk
15580#define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U)
15581#define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos)
15582#define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk
15583#define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U)
15584#define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos)
15585#define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk
15586#define RCC_APB4LPENR_COMP12LPEN_Pos (14U)
15587#define RCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos)
15588#define RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk
15589#define RCC_APB4LPENR_VREFLPEN_Pos (15U)
15590#define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos)
15591#define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk
15592#define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U)
15593#define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos)
15594#define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk
15595#define RCC_APB4LPENR_SAI4LPEN_Pos (21U)
15596#define RCC_APB4LPENR_SAI4LPEN_Msk (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos)
15597#define RCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk
15598
15599
15600/******************** Bit definition for RCC_RSR register *******************/
15601#define RCC_RSR_RMVF_Pos (16U)
15602#define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos)
15603#define RCC_RSR_RMVF RCC_RSR_RMVF_Msk
15604#define RCC_RSR_CPURSTF_Pos (17U)
15605#define RCC_RSR_CPURSTF_Msk (0x1UL << RCC_RSR_CPURSTF_Pos)
15606#define RCC_RSR_CPURSTF RCC_RSR_CPURSTF_Msk
15607#define RCC_RSR_D1RSTF_Pos (19U)
15608#define RCC_RSR_D1RSTF_Msk (0x1UL << RCC_RSR_D1RSTF_Pos)
15609#define RCC_RSR_D1RSTF RCC_RSR_D1RSTF_Msk
15610#define RCC_RSR_D2RSTF_Pos (20U)
15611#define RCC_RSR_D2RSTF_Msk (0x1UL << RCC_RSR_D2RSTF_Pos)
15612#define RCC_RSR_D2RSTF RCC_RSR_D2RSTF_Msk
15613#define RCC_RSR_BORRSTF_Pos (21U)
15614#define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos)
15615#define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk
15616#define RCC_RSR_PINRSTF_Pos (22U)
15617#define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos)
15618#define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk
15619#define RCC_RSR_PORRSTF_Pos (23U)
15620#define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos)
15621#define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk
15622#define RCC_RSR_SFTRSTF_Pos (24U)
15623#define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos)
15624#define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk
15625#define RCC_RSR_IWDG1RSTF_Pos (26U)
15626#define RCC_RSR_IWDG1RSTF_Msk (0x1UL << RCC_RSR_IWDG1RSTF_Pos)
15627#define RCC_RSR_IWDG1RSTF RCC_RSR_IWDG1RSTF_Msk
15628#define RCC_RSR_WWDG1RSTF_Pos (28U)
15629#define RCC_RSR_WWDG1RSTF_Msk (0x1UL << RCC_RSR_WWDG1RSTF_Pos)
15630#define RCC_RSR_WWDG1RSTF RCC_RSR_WWDG1RSTF_Msk
15631
15632#define RCC_RSR_LPWRRSTF_Pos (30U)
15633#define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos)
15634#define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk
15635
15636
15637/******************************************************************************/
15638/* */
15639/* RNG */
15640/* */
15641/******************************************************************************/
15642/******************** Bits definition for RNG_CR register *******************/
15643#define RNG_CR_RNGEN_Pos (2U)
15644#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos)
15645#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
15646#define RNG_CR_IE_Pos (3U)
15647#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos)
15648#define RNG_CR_IE RNG_CR_IE_Msk
15649#define RNG_CR_CED_Pos (5U)
15650#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos)
15651#define RNG_CR_CED RNG_CR_CED_Msk
15652
15653/******************** Bits definition for RNG_SR register *******************/
15654#define RNG_SR_DRDY_Pos (0U)
15655#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos)
15656#define RNG_SR_DRDY RNG_SR_DRDY_Msk
15657#define RNG_SR_CECS_Pos (1U)
15658#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos)
15659#define RNG_SR_CECS RNG_SR_CECS_Msk
15660#define RNG_SR_SECS_Pos (2U)
15661#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos)
15662#define RNG_SR_SECS RNG_SR_SECS_Msk
15663#define RNG_SR_CEIS_Pos (5U)
15664#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos)
15665#define RNG_SR_CEIS RNG_SR_CEIS_Msk
15666#define RNG_SR_SEIS_Pos (6U)
15667#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos)
15668#define RNG_SR_SEIS RNG_SR_SEIS_Msk
15669
15670/******************************************************************************/
15671/* */
15672/* Real-Time Clock (RTC) */
15673/* */
15674/******************************************************************************/
15675/******************** Bits definition for RTC_TR register *******************/
15676#define RTC_TR_PM_Pos (22U)
15677#define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos)
15678#define RTC_TR_PM RTC_TR_PM_Msk
15679#define RTC_TR_HT_Pos (20U)
15680#define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos)
15681#define RTC_TR_HT RTC_TR_HT_Msk
15682#define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos)
15683#define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos)
15684#define RTC_TR_HU_Pos (16U)
15685#define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos)
15686#define RTC_TR_HU RTC_TR_HU_Msk
15687#define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos)
15688#define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos)
15689#define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos)
15690#define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos)
15691#define RTC_TR_MNT_Pos (12U)
15692#define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos)
15693#define RTC_TR_MNT RTC_TR_MNT_Msk
15694#define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos)
15695#define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos)
15696#define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos)
15697#define RTC_TR_MNU_Pos (8U)
15698#define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos)
15699#define RTC_TR_MNU RTC_TR_MNU_Msk
15700#define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos)
15701#define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos)
15702#define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos)
15703#define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos)
15704#define RTC_TR_ST_Pos (4U)
15705#define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos)
15706#define RTC_TR_ST RTC_TR_ST_Msk
15707#define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos)
15708#define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos)
15709#define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos)
15710#define RTC_TR_SU_Pos (0U)
15711#define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos)
15712#define RTC_TR_SU RTC_TR_SU_Msk
15713#define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos)
15714#define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos)
15715#define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos)
15716#define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos)
15718/******************** Bits definition for RTC_DR register *******************/
15719#define RTC_DR_YT_Pos (20U)
15720#define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos)
15721#define RTC_DR_YT RTC_DR_YT_Msk
15722#define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos)
15723#define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos)
15724#define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos)
15725#define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos)
15726#define RTC_DR_YU_Pos (16U)
15727#define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos)
15728#define RTC_DR_YU RTC_DR_YU_Msk
15729#define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos)
15730#define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos)
15731#define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos)
15732#define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos)
15733#define RTC_DR_WDU_Pos (13U)
15734#define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos)
15735#define RTC_DR_WDU RTC_DR_WDU_Msk
15736#define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos)
15737#define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos)
15738#define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos)
15739#define RTC_DR_MT_Pos (12U)
15740#define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos)
15741#define RTC_DR_MT RTC_DR_MT_Msk
15742#define RTC_DR_MU_Pos (8U)
15743#define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos)
15744#define RTC_DR_MU RTC_DR_MU_Msk
15745#define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos)
15746#define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos)
15747#define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos)
15748#define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos)
15749#define RTC_DR_DT_Pos (4U)
15750#define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos)
15751#define RTC_DR_DT RTC_DR_DT_Msk
15752#define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos)
15753#define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos)
15754#define RTC_DR_DU_Pos (0U)
15755#define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos)
15756#define RTC_DR_DU RTC_DR_DU_Msk
15757#define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos)
15758#define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos)
15759#define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos)
15760#define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos)
15762/******************** Bits definition for RTC_CR register *******************/
15763#define RTC_CR_ITSE_Pos (24U)
15764#define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos)
15765#define RTC_CR_ITSE RTC_CR_ITSE_Msk
15766#define RTC_CR_COE_Pos (23U)
15767#define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos)
15768#define RTC_CR_COE RTC_CR_COE_Msk
15769#define RTC_CR_OSEL_Pos (21U)
15770#define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos)
15771#define RTC_CR_OSEL RTC_CR_OSEL_Msk
15772#define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos)
15773#define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos)
15774#define RTC_CR_POL_Pos (20U)
15775#define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos)
15776#define RTC_CR_POL RTC_CR_POL_Msk
15777#define RTC_CR_COSEL_Pos (19U)
15778#define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos)
15779#define RTC_CR_COSEL RTC_CR_COSEL_Msk
15780#define RTC_CR_BKP_Pos (18U)
15781#define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos)
15782#define RTC_CR_BKP RTC_CR_BKP_Msk
15783#define RTC_CR_SUB1H_Pos (17U)
15784#define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos)
15785#define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
15786#define RTC_CR_ADD1H_Pos (16U)
15787#define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos)
15788#define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
15789#define RTC_CR_TSIE_Pos (15U)
15790#define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos)
15791#define RTC_CR_TSIE RTC_CR_TSIE_Msk
15792#define RTC_CR_WUTIE_Pos (14U)
15793#define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos)
15794#define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
15795#define RTC_CR_ALRBIE_Pos (13U)
15796#define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos)
15797#define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
15798#define RTC_CR_ALRAIE_Pos (12U)
15799#define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos)
15800#define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
15801#define RTC_CR_TSE_Pos (11U)
15802#define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos)
15803#define RTC_CR_TSE RTC_CR_TSE_Msk
15804#define RTC_CR_WUTE_Pos (10U)
15805#define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos)
15806#define RTC_CR_WUTE RTC_CR_WUTE_Msk
15807#define RTC_CR_ALRBE_Pos (9U)
15808#define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos)
15809#define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
15810#define RTC_CR_ALRAE_Pos (8U)
15811#define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos)
15812#define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
15813#define RTC_CR_FMT_Pos (6U)
15814#define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos)
15815#define RTC_CR_FMT RTC_CR_FMT_Msk
15816#define RTC_CR_BYPSHAD_Pos (5U)
15817#define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos)
15818#define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
15819#define RTC_CR_REFCKON_Pos (4U)
15820#define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos)
15821#define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
15822#define RTC_CR_TSEDGE_Pos (3U)
15823#define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos)
15824#define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
15825#define RTC_CR_WUCKSEL_Pos (0U)
15826#define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos)
15827#define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
15828#define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos)
15829#define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos)
15830#define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos)
15832/******************** Bits definition for RTC_ISR register ******************/
15833#define RTC_ISR_ITSF_Pos (17U)
15834#define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos)
15835#define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
15836#define RTC_ISR_RECALPF_Pos (16U)
15837#define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos)
15838#define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
15839#define RTC_ISR_TAMP3F_Pos (15U)
15840#define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos)
15841#define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
15842#define RTC_ISR_TAMP2F_Pos (14U)
15843#define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos)
15844#define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
15845#define RTC_ISR_TAMP1F_Pos (13U)
15846#define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos)
15847#define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
15848#define RTC_ISR_TSOVF_Pos (12U)
15849#define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos)
15850#define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
15851#define RTC_ISR_TSF_Pos (11U)
15852#define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos)
15853#define RTC_ISR_TSF RTC_ISR_TSF_Msk
15854#define RTC_ISR_WUTF_Pos (10U)
15855#define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos)
15856#define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
15857#define RTC_ISR_ALRBF_Pos (9U)
15858#define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos)
15859#define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
15860#define RTC_ISR_ALRAF_Pos (8U)
15861#define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos)
15862#define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
15863#define RTC_ISR_INIT_Pos (7U)
15864#define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos)
15865#define RTC_ISR_INIT RTC_ISR_INIT_Msk
15866#define RTC_ISR_INITF_Pos (6U)
15867#define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos)
15868#define RTC_ISR_INITF RTC_ISR_INITF_Msk
15869#define RTC_ISR_RSF_Pos (5U)
15870#define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos)
15871#define RTC_ISR_RSF RTC_ISR_RSF_Msk
15872#define RTC_ISR_INITS_Pos (4U)
15873#define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos)
15874#define RTC_ISR_INITS RTC_ISR_INITS_Msk
15875#define RTC_ISR_SHPF_Pos (3U)
15876#define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos)
15877#define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
15878#define RTC_ISR_WUTWF_Pos (2U)
15879#define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos)
15880#define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
15881#define RTC_ISR_ALRBWF_Pos (1U)
15882#define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos)
15883#define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
15884#define RTC_ISR_ALRAWF_Pos (0U)
15885#define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos)
15886#define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
15887
15888/******************** Bits definition for RTC_PRER register *****************/
15889#define RTC_PRER_PREDIV_A_Pos (16U)
15890#define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos)
15891#define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
15892#define RTC_PRER_PREDIV_S_Pos (0U)
15893#define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)
15894#define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
15895
15896/******************** Bits definition for RTC_WUTR register *****************/
15897#define RTC_WUTR_WUT_Pos (0U)
15898#define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos)
15899#define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
15900
15901/******************** Bits definition for RTC_ALRMAR register ***************/
15902#define RTC_ALRMAR_MSK4_Pos (31U)
15903#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos)
15904#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
15905#define RTC_ALRMAR_WDSEL_Pos (30U)
15906#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos)
15907#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
15908#define RTC_ALRMAR_DT_Pos (28U)
15909#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos)
15910#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
15911#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos)
15912#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos)
15913#define RTC_ALRMAR_DU_Pos (24U)
15914#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos)
15915#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
15916#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos)
15917#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos)
15918#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos)
15919#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos)
15920#define RTC_ALRMAR_MSK3_Pos (23U)
15921#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos)
15922#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
15923#define RTC_ALRMAR_PM_Pos (22U)
15924#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos)
15925#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
15926#define RTC_ALRMAR_HT_Pos (20U)
15927#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos)
15928#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
15929#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos)
15930#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos)
15931#define RTC_ALRMAR_HU_Pos (16U)
15932#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos)
15933#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
15934#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos)
15935#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos)
15936#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos)
15937#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos)
15938#define RTC_ALRMAR_MSK2_Pos (15U)
15939#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos)
15940#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
15941#define RTC_ALRMAR_MNT_Pos (12U)
15942#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos)
15943#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
15944#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos)
15945#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos)
15946#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos)
15947#define RTC_ALRMAR_MNU_Pos (8U)
15948#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos)
15949#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
15950#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos)
15951#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos)
15952#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos)
15953#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos)
15954#define RTC_ALRMAR_MSK1_Pos (7U)
15955#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos)
15956#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
15957#define RTC_ALRMAR_ST_Pos (4U)
15958#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos)
15959#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
15960#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos)
15961#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos)
15962#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos)
15963#define RTC_ALRMAR_SU_Pos (0U)
15964#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos)
15965#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
15966#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos)
15967#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos)
15968#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos)
15969#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos)
15971/******************** Bits definition for RTC_ALRMBR register ***************/
15972#define RTC_ALRMBR_MSK4_Pos (31U)
15973#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos)
15974#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
15975#define RTC_ALRMBR_WDSEL_Pos (30U)
15976#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos)
15977#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
15978#define RTC_ALRMBR_DT_Pos (28U)
15979#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos)
15980#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
15981#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos)
15982#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos)
15983#define RTC_ALRMBR_DU_Pos (24U)
15984#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos)
15985#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
15986#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos)
15987#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos)
15988#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos)
15989#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos)
15990#define RTC_ALRMBR_MSK3_Pos (23U)
15991#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos)
15992#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
15993#define RTC_ALRMBR_PM_Pos (22U)
15994#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos)
15995#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
15996#define RTC_ALRMBR_HT_Pos (20U)
15997#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos)
15998#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
15999#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos)
16000#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos)
16001#define RTC_ALRMBR_HU_Pos (16U)
16002#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos)
16003#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
16004#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos)
16005#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos)
16006#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos)
16007#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos)
16008#define RTC_ALRMBR_MSK2_Pos (15U)
16009#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos)
16010#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
16011#define RTC_ALRMBR_MNT_Pos (12U)
16012#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos)
16013#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
16014#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos)
16015#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos)
16016#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos)
16017#define RTC_ALRMBR_MNU_Pos (8U)
16018#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos)
16019#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
16020#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos)
16021#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos)
16022#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos)
16023#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos)
16024#define RTC_ALRMBR_MSK1_Pos (7U)
16025#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos)
16026#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
16027#define RTC_ALRMBR_ST_Pos (4U)
16028#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos)
16029#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
16030#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos)
16031#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos)
16032#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos)
16033#define RTC_ALRMBR_SU_Pos (0U)
16034#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos)
16035#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
16036#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos)
16037#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos)
16038#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos)
16039#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos)
16041/******************** Bits definition for RTC_WPR register ******************/
16042#define RTC_WPR_KEY_Pos (0U)
16043#define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos)
16044#define RTC_WPR_KEY RTC_WPR_KEY_Msk
16045
16046/******************** Bits definition for RTC_SSR register ******************/
16047#define RTC_SSR_SS_Pos (0U)
16048#define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos)
16049#define RTC_SSR_SS RTC_SSR_SS_Msk
16050
16051/******************** Bits definition for RTC_SHIFTR register ***************/
16052#define RTC_SHIFTR_SUBFS_Pos (0U)
16053#define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)
16054#define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
16055#define RTC_SHIFTR_ADD1S_Pos (31U)
16056#define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos)
16057#define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
16058
16059/******************** Bits definition for RTC_TSTR register *****************/
16060#define RTC_TSTR_PM_Pos (22U)
16061#define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos)
16062#define RTC_TSTR_PM RTC_TSTR_PM_Msk
16063#define RTC_TSTR_HT_Pos (20U)
16064#define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos)
16065#define RTC_TSTR_HT RTC_TSTR_HT_Msk
16066#define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos)
16067#define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos)
16068#define RTC_TSTR_HU_Pos (16U)
16069#define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos)
16070#define RTC_TSTR_HU RTC_TSTR_HU_Msk
16071#define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos)
16072#define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos)
16073#define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos)
16074#define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos)
16075#define RTC_TSTR_MNT_Pos (12U)
16076#define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos)
16077#define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
16078#define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos)
16079#define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos)
16080#define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos)
16081#define RTC_TSTR_MNU_Pos (8U)
16082#define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos)
16083#define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
16084#define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos)
16085#define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos)
16086#define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos)
16087#define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos)
16088#define RTC_TSTR_ST_Pos (4U)
16089#define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos)
16090#define RTC_TSTR_ST RTC_TSTR_ST_Msk
16091#define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos)
16092#define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos)
16093#define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos)
16094#define RTC_TSTR_SU_Pos (0U)
16095#define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos)
16096#define RTC_TSTR_SU RTC_TSTR_SU_Msk
16097#define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos)
16098#define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos)
16099#define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos)
16100#define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos)
16102/******************** Bits definition for RTC_TSDR register *****************/
16103#define RTC_TSDR_WDU_Pos (13U)
16104#define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos)
16105#define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
16106#define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos)
16107#define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos)
16108#define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos)
16109#define RTC_TSDR_MT_Pos (12U)
16110#define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos)
16111#define RTC_TSDR_MT RTC_TSDR_MT_Msk
16112#define RTC_TSDR_MU_Pos (8U)
16113#define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos)
16114#define RTC_TSDR_MU RTC_TSDR_MU_Msk
16115#define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos)
16116#define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos)
16117#define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos)
16118#define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos)
16119#define RTC_TSDR_DT_Pos (4U)
16120#define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos)
16121#define RTC_TSDR_DT RTC_TSDR_DT_Msk
16122#define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos)
16123#define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos)
16124#define RTC_TSDR_DU_Pos (0U)
16125#define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos)
16126#define RTC_TSDR_DU RTC_TSDR_DU_Msk
16127#define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos)
16128#define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos)
16129#define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos)
16130#define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos)
16132/******************** Bits definition for RTC_TSSSR register ****************/
16133#define RTC_TSSSR_SS_Pos (0U)
16134#define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos)
16135#define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
16136
16137/******************** Bits definition for RTC_CALR register *****************/
16138#define RTC_CALR_CALP_Pos (15U)
16139#define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos)
16140#define RTC_CALR_CALP RTC_CALR_CALP_Msk
16141#define RTC_CALR_CALW8_Pos (14U)
16142#define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos)
16143#define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
16144#define RTC_CALR_CALW16_Pos (13U)
16145#define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos)
16146#define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
16147#define RTC_CALR_CALM_Pos (0U)
16148#define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos)
16149#define RTC_CALR_CALM RTC_CALR_CALM_Msk
16150#define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos)
16151#define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos)
16152#define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos)
16153#define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos)
16154#define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos)
16155#define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos)
16156#define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos)
16157#define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos)
16158#define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos)
16160/******************** Bits definition for RTC_TAMPCR register ***************/
16161#define RTC_TAMPCR_TAMP3MF_Pos (24U)
16162#define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)
16163#define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
16164#define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
16165#define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)
16166#define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
16167#define RTC_TAMPCR_TAMP3IE_Pos (22U)
16168#define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)
16169#define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
16170#define RTC_TAMPCR_TAMP2MF_Pos (21U)
16171#define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)
16172#define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
16173#define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
16174#define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)
16175#define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
16176#define RTC_TAMPCR_TAMP2IE_Pos (19U)
16177#define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)
16178#define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
16179#define RTC_TAMPCR_TAMP1MF_Pos (18U)
16180#define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)
16181#define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
16182#define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
16183#define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)
16184#define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
16185#define RTC_TAMPCR_TAMP1IE_Pos (16U)
16186#define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)
16187#define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
16188#define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
16189#define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)
16190#define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
16191#define RTC_TAMPCR_TAMPPRCH_Pos (13U)
16192#define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)
16193#define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
16194#define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)
16195#define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)
16196#define RTC_TAMPCR_TAMPFLT_Pos (11U)
16197#define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)
16198#define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
16199#define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)
16200#define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)
16201#define RTC_TAMPCR_TAMPFREQ_Pos (8U)
16202#define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)
16203#define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
16204#define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)
16205#define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)
16206#define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)
16207#define RTC_TAMPCR_TAMPTS_Pos (7U)
16208#define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos)
16209#define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
16210#define RTC_TAMPCR_TAMP3TRG_Pos (6U)
16211#define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)
16212#define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
16213#define RTC_TAMPCR_TAMP3E_Pos (5U)
16214#define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos)
16215#define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
16216#define RTC_TAMPCR_TAMP2TRG_Pos (4U)
16217#define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)
16218#define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
16219#define RTC_TAMPCR_TAMP2E_Pos (3U)
16220#define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos)
16221#define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
16222#define RTC_TAMPCR_TAMPIE_Pos (2U)
16223#define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos)
16224#define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
16225#define RTC_TAMPCR_TAMP1TRG_Pos (1U)
16226#define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)
16227#define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
16228#define RTC_TAMPCR_TAMP1E_Pos (0U)
16229#define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos)
16230#define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
16231
16232/******************** Bits definition for RTC_ALRMASSR register *************/
16233#define RTC_ALRMASSR_MASKSS_Pos (24U)
16234#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos)
16235#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
16236#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos)
16237#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos)
16238#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos)
16239#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos)
16240#define RTC_ALRMASSR_SS_Pos (0U)
16241#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos)
16242#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
16243
16244/******************** Bits definition for RTC_ALRMBSSR register *************/
16245#define RTC_ALRMBSSR_MASKSS_Pos (24U)
16246#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)
16247#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
16248#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)
16249#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)
16250#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)
16251#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)
16252#define RTC_ALRMBSSR_SS_Pos (0U)
16253#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)
16254#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
16255
16256/******************** Bits definition for RTC_OR register *******************/
16257#define RTC_OR_OUT_RMP_Pos (1U)
16258#define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos)
16259#define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
16260#define RTC_OR_ALARMOUTTYPE_Pos (0U)
16261#define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)
16262#define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
16263
16264/******************** Bits definition for RTC_BKP0R register ****************/
16265#define RTC_BKP0R_Pos (0U)
16266#define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos)
16267#define RTC_BKP0R RTC_BKP0R_Msk
16268
16269/******************** Bits definition for RTC_BKP1R register ****************/
16270#define RTC_BKP1R_Pos (0U)
16271#define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos)
16272#define RTC_BKP1R RTC_BKP1R_Msk
16273
16274/******************** Bits definition for RTC_BKP2R register ****************/
16275#define RTC_BKP2R_Pos (0U)
16276#define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos)
16277#define RTC_BKP2R RTC_BKP2R_Msk
16278
16279/******************** Bits definition for RTC_BKP3R register ****************/
16280#define RTC_BKP3R_Pos (0U)
16281#define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos)
16282#define RTC_BKP3R RTC_BKP3R_Msk
16283
16284/******************** Bits definition for RTC_BKP4R register ****************/
16285#define RTC_BKP4R_Pos (0U)
16286#define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos)
16287#define RTC_BKP4R RTC_BKP4R_Msk
16288
16289/******************** Bits definition for RTC_BKP5R register ****************/
16290#define RTC_BKP5R_Pos (0U)
16291#define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos)
16292#define RTC_BKP5R RTC_BKP5R_Msk
16293
16294/******************** Bits definition for RTC_BKP6R register ****************/
16295#define RTC_BKP6R_Pos (0U)
16296#define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos)
16297#define RTC_BKP6R RTC_BKP6R_Msk
16298
16299/******************** Bits definition for RTC_BKP7R register ****************/
16300#define RTC_BKP7R_Pos (0U)
16301#define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos)
16302#define RTC_BKP7R RTC_BKP7R_Msk
16303
16304/******************** Bits definition for RTC_BKP8R register ****************/
16305#define RTC_BKP8R_Pos (0U)
16306#define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos)
16307#define RTC_BKP8R RTC_BKP8R_Msk
16308
16309/******************** Bits definition for RTC_BKP9R register ****************/
16310#define RTC_BKP9R_Pos (0U)
16311#define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos)
16312#define RTC_BKP9R RTC_BKP9R_Msk
16313
16314/******************** Bits definition for RTC_BKP10R register ***************/
16315#define RTC_BKP10R_Pos (0U)
16316#define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos)
16317#define RTC_BKP10R RTC_BKP10R_Msk
16318
16319/******************** Bits definition for RTC_BKP11R register ***************/
16320#define RTC_BKP11R_Pos (0U)
16321#define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos)
16322#define RTC_BKP11R RTC_BKP11R_Msk
16323
16324/******************** Bits definition for RTC_BKP12R register ***************/
16325#define RTC_BKP12R_Pos (0U)
16326#define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos)
16327#define RTC_BKP12R RTC_BKP12R_Msk
16328
16329/******************** Bits definition for RTC_BKP13R register ***************/
16330#define RTC_BKP13R_Pos (0U)
16331#define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos)
16332#define RTC_BKP13R RTC_BKP13R_Msk
16333
16334/******************** Bits definition for RTC_BKP14R register ***************/
16335#define RTC_BKP14R_Pos (0U)
16336#define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos)
16337#define RTC_BKP14R RTC_BKP14R_Msk
16338
16339/******************** Bits definition for RTC_BKP15R register ***************/
16340#define RTC_BKP15R_Pos (0U)
16341#define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos)
16342#define RTC_BKP15R RTC_BKP15R_Msk
16343
16344/******************** Bits definition for RTC_BKP16R register ***************/
16345#define RTC_BKP16R_Pos (0U)
16346#define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos)
16347#define RTC_BKP16R RTC_BKP16R_Msk
16348
16349/******************** Bits definition for RTC_BKP17R register ***************/
16350#define RTC_BKP17R_Pos (0U)
16351#define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos)
16352#define RTC_BKP17R RTC_BKP17R_Msk
16353
16354/******************** Bits definition for RTC_BKP18R register ***************/
16355#define RTC_BKP18R_Pos (0U)
16356#define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos)
16357#define RTC_BKP18R RTC_BKP18R_Msk
16358
16359/******************** Bits definition for RTC_BKP19R register ***************/
16360#define RTC_BKP19R_Pos (0U)
16361#define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos)
16362#define RTC_BKP19R RTC_BKP19R_Msk
16363
16364/******************** Bits definition for RTC_BKP20R register ***************/
16365#define RTC_BKP20R_Pos (0U)
16366#define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos)
16367#define RTC_BKP20R RTC_BKP20R_Msk
16368
16369/******************** Bits definition for RTC_BKP21R register ***************/
16370#define RTC_BKP21R_Pos (0U)
16371#define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos)
16372#define RTC_BKP21R RTC_BKP21R_Msk
16373
16374/******************** Bits definition for RTC_BKP22R register ***************/
16375#define RTC_BKP22R_Pos (0U)
16376#define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos)
16377#define RTC_BKP22R RTC_BKP22R_Msk
16378
16379/******************** Bits definition for RTC_BKP23R register ***************/
16380#define RTC_BKP23R_Pos (0U)
16381#define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos)
16382#define RTC_BKP23R RTC_BKP23R_Msk
16383
16384/******************** Bits definition for RTC_BKP24R register ***************/
16385#define RTC_BKP24R_Pos (0U)
16386#define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos)
16387#define RTC_BKP24R RTC_BKP24R_Msk
16388
16389/******************** Bits definition for RTC_BKP25R register ***************/
16390#define RTC_BKP25R_Pos (0U)
16391#define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos)
16392#define RTC_BKP25R RTC_BKP25R_Msk
16393
16394/******************** Bits definition for RTC_BKP26R register ***************/
16395#define RTC_BKP26R_Pos (0U)
16396#define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos)
16397#define RTC_BKP26R RTC_BKP26R_Msk
16398
16399/******************** Bits definition for RTC_BKP27R register ***************/
16400#define RTC_BKP27R_Pos (0U)
16401#define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos)
16402#define RTC_BKP27R RTC_BKP27R_Msk
16403
16404/******************** Bits definition for RTC_BKP28R register ***************/
16405#define RTC_BKP28R_Pos (0U)
16406#define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos)
16407#define RTC_BKP28R RTC_BKP28R_Msk
16408
16409/******************** Bits definition for RTC_BKP29R register ***************/
16410#define RTC_BKP29R_Pos (0U)
16411#define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos)
16412#define RTC_BKP29R RTC_BKP29R_Msk
16413
16414/******************** Bits definition for RTC_BKP30R register ***************/
16415#define RTC_BKP30R_Pos (0U)
16416#define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos)
16417#define RTC_BKP30R RTC_BKP30R_Msk
16418
16419/******************** Bits definition for RTC_BKP31R register ***************/
16420#define RTC_BKP31R_Pos (0U)
16421#define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos)
16422#define RTC_BKP31R RTC_BKP31R_Msk
16423
16424/******************** Number of backup registers ******************************/
16425#define RTC_BKP_NUMBER_Pos (5U)
16426#define RTC_BKP_NUMBER_Msk (0x1UL << RTC_BKP_NUMBER_Pos)
16427#define RTC_BKP_NUMBER RTC_BKP_NUMBER_Msk
16428
16429/******************************************************************************/
16430/* */
16431/* SPDIF-RX Interface */
16432/* */
16433/******************************************************************************/
16434/******************** Bit definition for SPDIF_CR register ******************/
16435#define SPDIFRX_CR_SPDIFEN_Pos (0U)
16436#define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)
16437#define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk
16438#define SPDIFRX_CR_RXDMAEN_Pos (2U)
16439#define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)
16440#define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk
16441#define SPDIFRX_CR_RXSTEO_Pos (3U)
16442#define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos)
16443#define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk
16444#define SPDIFRX_CR_DRFMT_Pos (4U)
16445#define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos)
16446#define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk
16447#define SPDIFRX_CR_PMSK_Pos (6U)
16448#define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos)
16449#define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk
16450#define SPDIFRX_CR_VMSK_Pos (7U)
16451#define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos)
16452#define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk
16453#define SPDIFRX_CR_CUMSK_Pos (8U)
16454#define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos)
16455#define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk
16456#define SPDIFRX_CR_PTMSK_Pos (9U)
16457#define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos)
16458#define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk
16459#define SPDIFRX_CR_CBDMAEN_Pos (10U)
16460#define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)
16461#define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk
16462#define SPDIFRX_CR_CHSEL_Pos (11U)
16463#define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos)
16464#define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk
16465#define SPDIFRX_CR_NBTR_Pos (12U)
16466#define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos)
16467#define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk
16468#define SPDIFRX_CR_WFA_Pos (14U)
16469#define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos)
16470#define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk
16471#define SPDIFRX_CR_INSEL_Pos (16U)
16472#define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos)
16473#define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk
16474#define SPDIFRX_CR_CKSEN_Pos (20U)
16475#define SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos)
16476#define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk
16477#define SPDIFRX_CR_CKSBKPEN_Pos (21U)
16478#define SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)
16479#define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk
16481/******************* Bit definition for SPDIFRX_IMR register *******************/
16482#define SPDIFRX_IMR_RXNEIE_Pos (0U)
16483#define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)
16484#define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk
16485#define SPDIFRX_IMR_CSRNEIE_Pos (1U)
16486#define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)
16487#define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk
16488#define SPDIFRX_IMR_PERRIE_Pos (2U)
16489#define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos)
16490#define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk
16491#define SPDIFRX_IMR_OVRIE_Pos (3U)
16492#define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos)
16493#define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk
16494#define SPDIFRX_IMR_SBLKIE_Pos (4U)
16495#define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)
16496#define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk
16497#define SPDIFRX_IMR_SYNCDIE_Pos (5U)
16498#define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)
16499#define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk
16500#define SPDIFRX_IMR_IFEIE_Pos (6U)
16501#define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos)
16502#define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk
16504/******************* Bit definition for SPDIFRX_SR register *******************/
16505#define SPDIFRX_SR_RXNE_Pos (0U)
16506#define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos)
16507#define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk
16508#define SPDIFRX_SR_CSRNE_Pos (1U)
16509#define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos)
16510#define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk
16511#define SPDIFRX_SR_PERR_Pos (2U)
16512#define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos)
16513#define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk
16514#define SPDIFRX_SR_OVR_Pos (3U)
16515#define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos)
16516#define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk
16517#define SPDIFRX_SR_SBD_Pos (4U)
16518#define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos)
16519#define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk
16520#define SPDIFRX_SR_SYNCD_Pos (5U)
16521#define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos)
16522#define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk
16523#define SPDIFRX_SR_FERR_Pos (6U)
16524#define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos)
16525#define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk
16526#define SPDIFRX_SR_SERR_Pos (7U)
16527#define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos)
16528#define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk
16529#define SPDIFRX_SR_TERR_Pos (8U)
16530#define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos)
16531#define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk
16532#define SPDIFRX_SR_WIDTH5_Pos (16U)
16533#define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)
16534#define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk
16536/******************* Bit definition for SPDIFRX_IFCR register *******************/
16537#define SPDIFRX_IFCR_PERRCF_Pos (2U)
16538#define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)
16539#define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk
16540#define SPDIFRX_IFCR_OVRCF_Pos (3U)
16541#define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)
16542#define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk
16543#define SPDIFRX_IFCR_SBDCF_Pos (4U)
16544#define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)
16545#define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk
16546#define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
16547#define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)
16548#define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk
16550/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
16551#define SPDIFRX_DR0_DR_Pos (0U)
16552#define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)
16553#define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk
16554#define SPDIFRX_DR0_PE_Pos (24U)
16555#define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos)
16556#define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk
16557#define SPDIFRX_DR0_V_Pos (25U)
16558#define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos)
16559#define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk
16560#define SPDIFRX_DR0_U_Pos (26U)
16561#define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos)
16562#define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk
16563#define SPDIFRX_DR0_C_Pos (27U)
16564#define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos)
16565#define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk
16566#define SPDIFRX_DR0_PT_Pos (28U)
16567#define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos)
16568#define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk
16570/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
16571#define SPDIFRX_DR1_DR_Pos (8U)
16572#define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)
16573#define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk
16574#define SPDIFRX_DR1_PT_Pos (4U)
16575#define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos)
16576#define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk
16577#define SPDIFRX_DR1_C_Pos (3U)
16578#define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos)
16579#define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk
16580#define SPDIFRX_DR1_U_Pos (2U)
16581#define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos)
16582#define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk
16583#define SPDIFRX_DR1_V_Pos (1U)
16584#define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos)
16585#define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk
16586#define SPDIFRX_DR1_PE_Pos (0U)
16587#define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos)
16588#define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk
16590/******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
16591#define SPDIFRX_DR1_DRNL1_Pos (16U)
16592#define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)
16593#define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk
16594#define SPDIFRX_DR1_DRNL2_Pos (0U)
16595#define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)
16596#define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk
16598/******************* Bit definition for SPDIFRX_CSR register *******************/
16599#define SPDIFRX_CSR_USR_Pos (0U)
16600#define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos)
16601#define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk
16602#define SPDIFRX_CSR_CS_Pos (16U)
16603#define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos)
16604#define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk
16605#define SPDIFRX_CSR_SOB_Pos (24U)
16606#define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos)
16607#define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk
16609/******************* Bit definition for SPDIFRX_DIR register *******************/
16610#define SPDIFRX_DIR_THI_Pos (0U)
16611#define SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos)
16612#define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk
16613#define SPDIFRX_DIR_TLO_Pos (16U)
16614#define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)
16615#define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk
16617/******************* Bit definition for SPDIFRX_VERR register *******************/
16618#define SPDIFRX_VERR_MINREV_Pos (0U)
16619#define SPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos)
16620#define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk
16621#define SPDIFRX_VERR_MAJREV_Pos (4U)
16622#define SPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos)
16623#define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk
16625/******************* Bit definition for SPDIFRX_IDR register *******************/
16626#define SPDIFRX_IDR_ID_Pos (0U)
16627#define SPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)
16628#define SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk
16630/******************* Bit definition for SPDIFRX_SIDR register *******************/
16631#define SPDIFRX_SIDR_SID_Pos (0U)
16632#define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)
16633#define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk
16635/******************************************************************************/
16636/* */
16637/* Serial Audio Interface */
16638/* */
16639/******************************************************************************/
16640/******************************* SAI VERSION ********************************/
16641#define SAI_VER_V2_X
16642
16643/******************** Bit definition for SAI_GCR register *******************/
16644#define SAI_GCR_SYNCIN_Pos (0U)
16645#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos)
16646#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk
16647#define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos)
16648#define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos)
16650#define SAI_GCR_SYNCOUT_Pos (4U)
16651#define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos)
16652#define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk
16653#define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos)
16654#define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos)
16656/******************* Bit definition for SAI_xCR1 register *******************/
16657#define SAI_xCR1_MODE_Pos (0U)
16658#define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos)
16659#define SAI_xCR1_MODE SAI_xCR1_MODE_Msk
16660#define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos)
16661#define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos)
16663#define SAI_xCR1_PRTCFG_Pos (2U)
16664#define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos)
16665#define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk
16666#define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos)
16667#define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos)
16669#define SAI_xCR1_DS_Pos (5U)
16670#define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos)
16671#define SAI_xCR1_DS SAI_xCR1_DS_Msk
16672#define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos)
16673#define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos)
16674#define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos)
16676#define SAI_xCR1_LSBFIRST_Pos (8U)
16677#define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos)
16678#define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk
16679#define SAI_xCR1_CKSTR_Pos (9U)
16680#define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos)
16681#define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk
16683#define SAI_xCR1_SYNCEN_Pos (10U)
16684#define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos)
16685#define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk
16686#define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos)
16687#define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos)
16689#define SAI_xCR1_MONO_Pos (12U)
16690#define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos)
16691#define SAI_xCR1_MONO SAI_xCR1_MONO_Msk
16692#define SAI_xCR1_OUTDRIV_Pos (13U)
16693#define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos)
16694#define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk
16695#define SAI_xCR1_SAIEN_Pos (16U)
16696#define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos)
16697#define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk
16698#define SAI_xCR1_DMAEN_Pos (17U)
16699#define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos)
16700#define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk
16701#define SAI_xCR1_NODIV_Pos (19U)
16702#define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos)
16703#define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk
16705#define SAI_xCR1_MCKDIV_Pos (20U)
16706#define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos)
16707#define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk
16708#define SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos)
16709#define SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos)
16710#define SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos)
16711#define SAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos)
16712#define SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos)
16713#define SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos)
16715#define SAI_xCR1_MCKEN_Pos (27U)
16716#define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos)
16717#define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk
16719#define SAI_xCR1_OSR_Pos (26U)
16720#define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos)
16721#define SAI_xCR1_OSR SAI_xCR1_OSR_Msk
16723/* Legacy define */
16724#define SAI_xCR1_NOMCK SAI_xCR1_NODIV
16725
16726/******************* Bit definition for SAI_xCR2 register *******************/
16727#define SAI_xCR2_FTH_Pos (0U)
16728#define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos)
16729#define SAI_xCR2_FTH SAI_xCR2_FTH_Msk
16730#define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos)
16731#define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos)
16732#define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos)
16734#define SAI_xCR2_FFLUSH_Pos (3U)
16735#define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos)
16736#define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk
16737#define SAI_xCR2_TRIS_Pos (4U)
16738#define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos)
16739#define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk
16740#define SAI_xCR2_MUTE_Pos (5U)
16741#define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos)
16742#define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk
16743#define SAI_xCR2_MUTEVAL_Pos (6U)
16744#define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos)
16745#define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk
16747#define SAI_xCR2_MUTECNT_Pos (7U)
16748#define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos)
16749#define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk
16750#define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos)
16751#define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos)
16752#define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos)
16753#define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos)
16754#define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos)
16755#define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos)
16757#define SAI_xCR2_CPL_Pos (13U)
16758#define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos)
16759#define SAI_xCR2_CPL SAI_xCR2_CPL_Msk
16761#define SAI_xCR2_COMP_Pos (14U)
16762#define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos)
16763#define SAI_xCR2_COMP SAI_xCR2_COMP_Msk
16764#define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos)
16765#define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos)
16767/****************** Bit definition for SAI_xFRCR register *******************/
16768#define SAI_xFRCR_FRL_Pos (0U)
16769#define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos)
16770#define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk
16771#define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos)
16772#define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos)
16773#define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos)
16774#define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos)
16775#define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos)
16776#define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos)
16777#define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos)
16778#define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos)
16780#define SAI_xFRCR_FSALL_Pos (8U)
16781#define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos)
16782#define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk
16783#define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos)
16784#define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos)
16785#define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos)
16786#define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos)
16787#define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos)
16788#define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos)
16789#define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos)
16791#define SAI_xFRCR_FSDEF_Pos (16U)
16792#define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos)
16793#define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk
16794#define SAI_xFRCR_FSPOL_Pos (17U)
16795#define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos)
16796#define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk
16797#define SAI_xFRCR_FSOFF_Pos (18U)
16798#define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos)
16799#define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk
16801/* Legacy define */
16802#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
16803
16804/****************** Bit definition for SAI_xSLOTR register *******************/
16805#define SAI_xSLOTR_FBOFF_Pos (0U)
16806#define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos)
16807#define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk
16808#define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos)
16809#define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos)
16810#define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos)
16811#define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos)
16812#define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos)
16814#define SAI_xSLOTR_SLOTSZ_Pos (6U)
16815#define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)
16816#define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk
16817#define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)
16818#define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)
16820#define SAI_xSLOTR_NBSLOT_Pos (8U)
16821#define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos)
16822#define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk
16823#define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos)
16824#define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos)
16825#define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos)
16826#define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos)
16828#define SAI_xSLOTR_SLOTEN_Pos (16U)
16829#define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)
16830#define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk
16832/******************* Bit definition for SAI_xIMR register *******************/
16833#define SAI_xIMR_OVRUDRIE_Pos (0U)
16834#define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos)
16835#define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk
16836#define SAI_xIMR_MUTEDETIE_Pos (1U)
16837#define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos)
16838#define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk
16839#define SAI_xIMR_WCKCFGIE_Pos (2U)
16840#define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos)
16841#define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk
16842#define SAI_xIMR_FREQIE_Pos (3U)
16843#define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos)
16844#define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk
16845#define SAI_xIMR_CNRDYIE_Pos (4U)
16846#define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos)
16847#define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk
16848#define SAI_xIMR_AFSDETIE_Pos (5U)
16849#define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos)
16850#define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk
16851#define SAI_xIMR_LFSDETIE_Pos (6U)
16852#define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos)
16853#define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk
16855/******************** Bit definition for SAI_xSR register *******************/
16856#define SAI_xSR_OVRUDR_Pos (0U)
16857#define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos)
16858#define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk
16859#define SAI_xSR_MUTEDET_Pos (1U)
16860#define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos)
16861#define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk
16862#define SAI_xSR_WCKCFG_Pos (2U)
16863#define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos)
16864#define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk
16865#define SAI_xSR_FREQ_Pos (3U)
16866#define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos)
16867#define SAI_xSR_FREQ SAI_xSR_FREQ_Msk
16868#define SAI_xSR_CNRDY_Pos (4U)
16869#define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos)
16870#define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk
16871#define SAI_xSR_AFSDET_Pos (5U)
16872#define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos)
16873#define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk
16874#define SAI_xSR_LFSDET_Pos (6U)
16875#define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos)
16876#define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk
16878#define SAI_xSR_FLVL_Pos (16U)
16879#define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos)
16880#define SAI_xSR_FLVL SAI_xSR_FLVL_Msk
16881#define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos)
16882#define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos)
16883#define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos)
16885/****************** Bit definition for SAI_xCLRFR register ******************/
16886#define SAI_xCLRFR_COVRUDR_Pos (0U)
16887#define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos)
16888#define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk
16889#define SAI_xCLRFR_CMUTEDET_Pos (1U)
16890#define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)
16891#define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk
16892#define SAI_xCLRFR_CWCKCFG_Pos (2U)
16893#define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)
16894#define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk
16895#define SAI_xCLRFR_CFREQ_Pos (3U)
16896#define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos)
16897#define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk
16898#define SAI_xCLRFR_CCNRDY_Pos (4U)
16899#define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos)
16900#define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk
16901#define SAI_xCLRFR_CAFSDET_Pos (5U)
16902#define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos)
16903#define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk
16904#define SAI_xCLRFR_CLFSDET_Pos (6U)
16905#define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos)
16906#define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk
16908/****************** Bit definition for SAI_xDR register *********************/
16909#define SAI_xDR_DATA_Pos (0U)
16910#define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)
16911#define SAI_xDR_DATA SAI_xDR_DATA_Msk
16912
16913/******************* Bit definition for SAI_PDMCR register ******************/
16914#define SAI_PDMCR_PDMEN_Pos (0U)
16915#define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos)
16916#define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk
16918#define SAI_PDMCR_MICNBR_Pos (4U)
16919#define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos)
16920#define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk
16921#define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos)
16922#define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos)
16924#define SAI_PDMCR_CKEN1_Pos (8U)
16925#define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos)
16926#define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk
16927#define SAI_PDMCR_CKEN2_Pos (9U)
16928#define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos)
16929#define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk
16930#define SAI_PDMCR_CKEN3_Pos (10U)
16931#define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos)
16932#define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk
16933#define SAI_PDMCR_CKEN4_Pos (11U)
16934#define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos)
16935#define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk
16937/****************** Bit definition for SAI_PDMDLY register ******************/
16938#define SAI_PDMDLY_DLYM1L_Pos (0U)
16939#define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos)
16940#define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk
16941#define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos)
16942#define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos)
16943#define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos)
16945#define SAI_PDMDLY_DLYM1R_Pos (4U)
16946#define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos)
16947#define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk
16948#define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos)
16949#define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos)
16950#define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos)
16952#define SAI_PDMDLY_DLYM2L_Pos (8U)
16953#define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos)
16954#define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk
16955#define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos)
16956#define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos)
16957#define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos)
16959#define SAI_PDMDLY_DLYM2R_Pos (12U)
16960#define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos)
16961#define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk
16962#define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos)
16963#define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos)
16964#define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos)
16966#define SAI_PDMDLY_DLYM3L_Pos (16U)
16967#define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos)
16968#define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk
16969#define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos)
16970#define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos)
16971#define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos)
16973#define SAI_PDMDLY_DLYM3R_Pos (20U)
16974#define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos)
16975#define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk
16976#define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos)
16977#define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos)
16978#define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos)
16980#define SAI_PDMDLY_DLYM4L_Pos (24U)
16981#define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos)
16982#define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk
16983#define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos)
16984#define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos)
16985#define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos)
16987#define SAI_PDMDLY_DLYM4R_Pos (28U)
16988#define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos)
16989#define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk
16990#define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos)
16991#define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos)
16992#define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos)
16994/******************************************************************************/
16995/* */
16996/* SDMMC Interface */
16997/* */
16998/******************************************************************************/
16999/****************** Bit definition for SDMMC_POWER register ******************/
17000#define SDMMC_POWER_PWRCTRL_Pos (0U)
17001#define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos)
17002#define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk
17003#define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos)
17004#define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos)
17005#define SDMMC_POWER_VSWITCH_Pos (2U)
17006#define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos)
17007#define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk
17008#define SDMMC_POWER_VSWITCHEN_Pos (3U)
17009#define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)
17010#define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk
17011#define SDMMC_POWER_DIRPOL_Pos (4U)
17012#define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos)
17013#define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk
17015/****************** Bit definition for SDMMC_CLKCR register ******************/
17016#define SDMMC_CLKCR_CLKDIV_Pos (0U)
17017#define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)
17018#define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk
17019#define SDMMC_CLKCR_PWRSAV_Pos (12U)
17020#define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)
17021#define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk
17023#define SDMMC_CLKCR_WIDBUS_Pos (14U)
17024#define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)
17025#define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk
17026#define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)
17027#define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)
17029#define SDMMC_CLKCR_NEGEDGE_Pos (16U)
17030#define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)
17031#define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk
17032#define SDMMC_CLKCR_HWFC_EN_Pos (17U)
17033#define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)
17034#define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk
17035#define SDMMC_CLKCR_DDR_Pos (18U)
17036#define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos)
17037#define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk
17038#define SDMMC_CLKCR_BUSSPEED_Pos (19U)
17039#define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)
17040#define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk
17041#define SDMMC_CLKCR_SELCLKRX_Pos (20U)
17042#define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)
17043#define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk
17044#define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)
17045#define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)
17047/******************* Bit definition for SDMMC_ARG register *******************/
17048#define SDMMC_ARG_CMDARG_Pos (0U)
17049#define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos)
17050#define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk
17052/******************* Bit definition for SDMMC_CMD register *******************/
17053#define SDMMC_CMD_CMDINDEX_Pos (0U)
17054#define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)
17055#define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk
17056#define SDMMC_CMD_CMDTRANS_Pos (6U)
17057#define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos)
17058#define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk
17059#define SDMMC_CMD_CMDSTOP_Pos (7U)
17060#define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos)
17061#define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk
17063#define SDMMC_CMD_WAITRESP_Pos (8U)
17064#define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos)
17065#define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk
17066#define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos)
17067#define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos)
17069#define SDMMC_CMD_WAITINT_Pos (10U)
17070#define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos)
17071#define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk
17072#define SDMMC_CMD_WAITPEND_Pos (11U)
17073#define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos)
17074#define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk
17075#define SDMMC_CMD_CPSMEN_Pos (12U)
17076#define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos)
17077#define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk
17078#define SDMMC_CMD_DTHOLD_Pos (13U)
17079#define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos)
17080#define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk
17081#define SDMMC_CMD_BOOTMODE_Pos (14U)
17082#define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos)
17083#define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk
17084#define SDMMC_CMD_BOOTEN_Pos (15U)
17085#define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos)
17086#define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk
17087#define SDMMC_CMD_CMDSUSPEND_Pos (16U)
17088#define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)
17089#define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk
17091/***************** Bit definition for SDMMC_RESPCMD register *****************/
17092#define SDMMC_RESPCMD_RESPCMD_Pos (0U)
17093#define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos)
17094#define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk
17096/****************** Bit definition for SDMMC_RESP0 register ******************/
17097#define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
17098#define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos)
17099#define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk
17101/****************** Bit definition for SDMMC_RESP1 register ******************/
17102#define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
17103#define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos)
17104#define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk
17106/****************** Bit definition for SDMMC_RESP2 register ******************/
17107#define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
17108#define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos)
17109#define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk
17111/****************** Bit definition for SDMMC_RESP3 register ******************/
17112#define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
17113#define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos)
17114#define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk
17116/****************** Bit definition for SDMMC_RESP4 register ******************/
17117#define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
17118#define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos)
17119#define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk
17121/****************** Bit definition for SDMMC_DTIMER register *****************/
17122#define SDMMC_DTIMER_DATATIME_Pos (0U)
17123#define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos)
17124#define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk
17126/****************** Bit definition for SDMMC_DLEN register *******************/
17127#define SDMMC_DLEN_DATALENGTH_Pos (0U)
17128#define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos)
17129#define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk
17131/****************** Bit definition for SDMMC_DCTRL register ******************/
17132#define SDMMC_DCTRL_DTEN_Pos (0U)
17133#define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos)
17134#define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk
17135#define SDMMC_DCTRL_DTDIR_Pos (1U)
17136#define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos)
17137#define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk
17138#define SDMMC_DCTRL_DTMODE_Pos (2U)
17139#define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos)
17140#define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk
17141#define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos)
17142#define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos)
17144#define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
17145#define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
17146#define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk
17147#define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
17148#define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
17149#define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
17150#define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)
17152#define SDMMC_DCTRL_RWSTART_Pos (8U)
17153#define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos)
17154#define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk
17155#define SDMMC_DCTRL_RWSTOP_Pos (9U)
17156#define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)
17157#define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk
17158#define SDMMC_DCTRL_RWMOD_Pos (10U)
17159#define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos)
17160#define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk
17161#define SDMMC_DCTRL_SDIOEN_Pos (11U)
17162#define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)
17163#define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk
17164#define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
17165#define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)
17166#define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk
17167#define SDMMC_DCTRL_FIFORST_Pos (13U)
17168#define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos)
17169#define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk
17171/****************** Bit definition for SDMMC_DCOUNT register *****************/
17172#define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
17173#define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos)
17174#define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk
17176/****************** Bit definition for SDMMC_STA register ********************/
17177#define SDMMC_STA_CCRCFAIL_Pos (0U)
17178#define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos)
17179#define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk
17180#define SDMMC_STA_DCRCFAIL_Pos (1U)
17181#define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos)
17182#define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk
17183#define SDMMC_STA_CTIMEOUT_Pos (2U)
17184#define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos)
17185#define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk
17186#define SDMMC_STA_DTIMEOUT_Pos (3U)
17187#define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos)
17188#define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk
17189#define SDMMC_STA_TXUNDERR_Pos (4U)
17190#define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos)
17191#define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk
17192#define SDMMC_STA_RXOVERR_Pos (5U)
17193#define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos)
17194#define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk
17195#define SDMMC_STA_CMDREND_Pos (6U)
17196#define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos)
17197#define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk
17198#define SDMMC_STA_CMDSENT_Pos (7U)
17199#define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos)
17200#define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk
17201#define SDMMC_STA_DATAEND_Pos (8U)
17202#define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos)
17203#define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk
17204#define SDMMC_STA_DHOLD_Pos (9U)
17205#define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos)
17206#define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk
17207#define SDMMC_STA_DBCKEND_Pos (10U)
17208#define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos)
17209#define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk
17210#define SDMMC_STA_DABORT_Pos (11U)
17211#define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos)
17212#define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk
17213#define SDMMC_STA_DPSMACT_Pos (12U)
17214#define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos)
17215#define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk
17216#define SDMMC_STA_CPSMACT_Pos (13U)
17217#define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos)
17218#define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk
17219#define SDMMC_STA_TXFIFOHE_Pos (14U)
17220#define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos)
17221#define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk
17222#define SDMMC_STA_RXFIFOHF_Pos (15U)
17223#define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos)
17224#define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk
17225#define SDMMC_STA_TXFIFOF_Pos (16U)
17226#define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos)
17227#define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk
17228#define SDMMC_STA_RXFIFOF_Pos (17U)
17229#define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos)
17230#define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk
17231#define SDMMC_STA_TXFIFOE_Pos (18U)
17232#define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos)
17233#define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk
17234#define SDMMC_STA_RXFIFOE_Pos (19U)
17235#define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos)
17236#define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk
17237#define SDMMC_STA_BUSYD0_Pos (20U)
17238#define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos)
17239#define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk
17240#define SDMMC_STA_BUSYD0END_Pos (21U)
17241#define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos)
17242#define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk
17243#define SDMMC_STA_SDIOIT_Pos (22U)
17244#define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos)
17245#define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk
17246#define SDMMC_STA_ACKFAIL_Pos (23U)
17247#define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos)
17248#define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk
17249#define SDMMC_STA_ACKTIMEOUT_Pos (24U)
17250#define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)
17251#define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk
17252#define SDMMC_STA_VSWEND_Pos (25U)
17253#define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos)
17254#define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk
17255#define SDMMC_STA_CKSTOP_Pos (26U)
17256#define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos)
17257#define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk
17258#define SDMMC_STA_IDMATE_Pos (27U)
17259#define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos)
17260#define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk
17261#define SDMMC_STA_IDMABTC_Pos (28U)
17262#define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos)
17263#define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk
17265/******************* Bit definition for SDMMC_ICR register *******************/
17266#define SDMMC_ICR_CCRCFAILC_Pos (0U)
17267#define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)
17268#define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk
17269#define SDMMC_ICR_DCRCFAILC_Pos (1U)
17270#define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)
17271#define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk
17272#define SDMMC_ICR_CTIMEOUTC_Pos (2U)
17273#define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)
17274#define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk
17275#define SDMMC_ICR_DTIMEOUTC_Pos (3U)
17276#define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)
17277#define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk
17278#define SDMMC_ICR_TXUNDERRC_Pos (4U)
17279#define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)
17280#define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk
17281#define SDMMC_ICR_RXOVERRC_Pos (5U)
17282#define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos)
17283#define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk
17284#define SDMMC_ICR_CMDRENDC_Pos (6U)
17285#define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos)
17286#define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk
17287#define SDMMC_ICR_CMDSENTC_Pos (7U)
17288#define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos)
17289#define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk
17290#define SDMMC_ICR_DATAENDC_Pos (8U)
17291#define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos)
17292#define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk
17293#define SDMMC_ICR_DHOLDC_Pos (9U)
17294#define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos)
17295#define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk
17296#define SDMMC_ICR_DBCKENDC_Pos (10U)
17297#define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos)
17298#define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk
17299#define SDMMC_ICR_DABORTC_Pos (11U)
17300#define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos)
17301#define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk
17302#define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
17303#define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)
17304#define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk
17305#define SDMMC_ICR_SDIOITC_Pos (22U)
17306#define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos)
17307#define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk
17308#define SDMMC_ICR_ACKFAILC_Pos (23U)
17309#define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos)
17310#define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk
17311#define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
17312#define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)
17313#define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk
17314#define SDMMC_ICR_VSWENDC_Pos (25U)
17315#define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos)
17316#define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk
17317#define SDMMC_ICR_CKSTOPC_Pos (26U)
17318#define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos)
17319#define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk
17320#define SDMMC_ICR_IDMATEC_Pos (27U)
17321#define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos)
17322#define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk
17323#define SDMMC_ICR_IDMABTCC_Pos (28U)
17324#define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos)
17325#define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk
17327/****************** Bit definition for SDMMC_MASK register *******************/
17328#define SDMMC_MASK_CCRCFAILIE_Pos (0U)
17329#define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)
17330#define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk
17331#define SDMMC_MASK_DCRCFAILIE_Pos (1U)
17332#define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)
17333#define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk
17334#define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
17335#define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)
17336#define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk
17337#define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
17338#define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)
17339#define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk
17340#define SDMMC_MASK_TXUNDERRIE_Pos (4U)
17341#define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)
17342#define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk
17343#define SDMMC_MASK_RXOVERRIE_Pos (5U)
17344#define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)
17345#define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk
17346#define SDMMC_MASK_CMDRENDIE_Pos (6U)
17347#define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)
17348#define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk
17349#define SDMMC_MASK_CMDSENTIE_Pos (7U)
17350#define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)
17351#define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk
17352#define SDMMC_MASK_DATAENDIE_Pos (8U)
17353#define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos)
17354#define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk
17355#define SDMMC_MASK_DHOLDIE_Pos (9U)
17356#define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos)
17357#define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk
17358#define SDMMC_MASK_DBCKENDIE_Pos (10U)
17359#define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)
17360#define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk
17361#define SDMMC_MASK_DABORTIE_Pos (11U)
17362#define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos)
17363#define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk
17365#define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
17366#define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)
17367#define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk
17368#define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
17369#define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)
17370#define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk
17372#define SDMMC_MASK_RXFIFOFIE_Pos (17U)
17373#define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)
17374#define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk
17375#define SDMMC_MASK_TXFIFOEIE_Pos (18U)
17376#define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)
17377#define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk
17379#define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
17380#define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos)
17381#define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk
17382#define SDMMC_MASK_SDIOITIE_Pos (22U)
17383#define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos)
17384#define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk
17385#define SDMMC_MASK_ACKFAILIE_Pos (23U)
17386#define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)
17387#define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk
17388#define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
17389#define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos)
17390#define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk
17391#define SDMMC_MASK_VSWENDIE_Pos (25U)
17392#define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos)
17393#define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk
17394#define SDMMC_MASK_CKSTOPIE_Pos (26U)
17395#define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)
17396#define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk
17397#define SDMMC_MASK_IDMABTCIE_Pos (28U)
17398#define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)
17399#define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk
17401/***************** Bit definition for SDMMC_ACKTIME register *****************/
17402#define SDMMC_ACKTIME_ACKTIME_Pos (0U)
17403#define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos)
17404#define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk
17406/****************** Bit definition for SDMMC_FIFO register *******************/
17407#define SDMMC_FIFO_FIFODATA_Pos (0U)
17408#define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos)
17409#define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk
17411/****************** Bit definition for SDMMC_IDMACTRL register ****************/
17412#define SDMMC_IDMA_IDMAEN_Pos (0U)
17413#define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos)
17414#define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk
17415#define SDMMC_IDMA_IDMABMODE_Pos (1U)
17416#define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)
17417#define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk
17418#define SDMMC_IDMA_IDMABACT_Pos (2U)
17419#define SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos)
17420#define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk
17422/***************** Bit definition for SDMMC_IDMABSIZE register ***************/
17423#define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)
17424#define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos)
17425#define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk
17427/***************** Bit definition for SDMMC_IDMABASE0 register ***************/
17428#define SDMMC_IDMABASE0_IDMABASE0 (0xFFFFFFFFU)
17430/***************** Bit definition for SDMMC_IDMABASE1 register ***************/
17431#define SDMMC_IDMABASE1_IDMABASE1 (0xFFFFFFFFU)
17433/******************************************************************************/
17434/* */
17435/* Delay Block Interface (DLYB) */
17436/* */
17437/******************************************************************************/
17438/******************* Bit definition for DLYB_CR register ********************/
17439#define DLYB_CR_DEN_Pos (0U)
17440#define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos)
17441#define DLYB_CR_DEN DLYB_CR_DEN_Msk
17442#define DLYB_CR_SEN_Pos (1U)
17443#define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos)
17444#define DLYB_CR_SEN DLYB_CR_SEN_Msk
17447/******************* Bit definition for DLYB_CFGR register ********************/
17448#define DLYB_CFGR_SEL_Pos (0U)
17449#define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos)
17450#define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk
17451#define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos)
17452#define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos)
17453#define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos)
17454#define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos)
17456#define DLYB_CFGR_UNIT_Pos (8U)
17457#define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos)
17458#define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk
17459#define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos)
17460#define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos)
17461#define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos)
17462#define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos)
17463#define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos)
17464#define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos)
17465#define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos)
17467#define DLYB_CFGR_LNG_Pos (16U)
17468#define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos)
17469#define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk
17470#define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos)
17471#define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos)
17472#define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos)
17473#define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos)
17474#define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos)
17475#define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos)
17476#define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos)
17477#define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos)
17478#define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos)
17479#define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos)
17480#define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos)
17481#define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos)
17483#define DLYB_CFGR_LNGF_Pos (31U)
17484#define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos)
17485#define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk
17487/******************************************************************************/
17488/* */
17489/* Serial Peripheral Interface (SPI/I2S) */
17490/* */
17491/******************************************************************************/
17492/******************* Bit definition for SPI_CR1 register ********************/
17493#define SPI_CR1_SPE_Pos (0U)
17494#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)
17495#define SPI_CR1_SPE SPI_CR1_SPE_Msk
17496#define SPI_CR1_MASRX_Pos (8U)
17497#define SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos)
17498#define SPI_CR1_MASRX SPI_CR1_MASRX_Msk
17499#define SPI_CR1_CSTART_Pos (9U)
17500#define SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos)
17501#define SPI_CR1_CSTART SPI_CR1_CSTART_Msk
17502#define SPI_CR1_CSUSP_Pos (10U)
17503#define SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos)
17504#define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk
17505#define SPI_CR1_HDDIR_Pos (11U)
17506#define SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos)
17507#define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk
17508#define SPI_CR1_SSI_Pos (12U)
17509#define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)
17510#define SPI_CR1_SSI SPI_CR1_SSI_Msk
17511#define SPI_CR1_CRC33_17_Pos (13U)
17512#define SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos)
17513#define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk
17514#define SPI_CR1_RCRCINI_Pos (14U)
17515#define SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos)
17516#define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk
17517#define SPI_CR1_TCRCINI_Pos (15U)
17518#define SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos)
17519#define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk
17520#define SPI_CR1_IOLOCK_Pos (16U)
17521#define SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos)
17522#define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk
17524/******************* Bit definition for SPI_CR2 register ********************/
17525#define SPI_CR2_TSER_Pos (16U)
17526#define SPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos)
17527#define SPI_CR2_TSER SPI_CR2_TSER_Msk
17528#define SPI_CR2_TSIZE_Pos (0U)
17529#define SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos)
17530#define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk
17532/******************* Bit definition for SPI_CFG1 register ********************/
17533#define SPI_CFG1_DSIZE_Pos (0U)
17534#define SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos)
17535#define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk
17536#define SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos)
17537#define SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos)
17538#define SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos)
17539#define SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos)
17540#define SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos)
17542#define SPI_CFG1_FTHLV_Pos (5U)
17543#define SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos)
17544#define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk
17545#define SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos)
17546#define SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos)
17547#define SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos)
17548#define SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos)
17550#define SPI_CFG1_UDRCFG_Pos (9U)
17551#define SPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos)
17552#define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk
17553#define SPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos)
17554#define SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos)
17557#define SPI_CFG1_UDRDET_Pos (11U)
17558#define SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos)
17559#define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk
17560#define SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos)
17561#define SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos)
17563#define SPI_CFG1_RXDMAEN_Pos (14U)
17564#define SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos)
17565#define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk
17566#define SPI_CFG1_TXDMAEN_Pos (15U)
17567#define SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos)
17568#define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk
17570#define SPI_CFG1_CRCSIZE_Pos (16U)
17571#define SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos)
17572#define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk
17573#define SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos)
17574#define SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos)
17575#define SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos)
17576#define SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos)
17577#define SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos)
17579#define SPI_CFG1_CRCEN_Pos (22U)
17580#define SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos)
17581#define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk
17583#define SPI_CFG1_MBR_Pos (28U)
17584#define SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos)
17585#define SPI_CFG1_MBR SPI_CFG1_MBR_Msk
17586#define SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos)
17587#define SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos)
17588#define SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos)
17590/******************* Bit definition for SPI_CFG2 register ********************/
17591#define SPI_CFG2_MSSI_Pos (0U)
17592#define SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos)
17593#define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk
17594#define SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos)
17595#define SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos)
17596#define SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos)
17597#define SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos)
17599#define SPI_CFG2_MIDI_Pos (4U)
17600#define SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos)
17601#define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk
17602#define SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos)
17603#define SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos)
17604#define SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos)
17605#define SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos)
17607#define SPI_CFG2_IOSWP_Pos (15U)
17608#define SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos)
17609#define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk
17611#define SPI_CFG2_COMM_Pos (17U)
17612#define SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos)
17613#define SPI_CFG2_COMM SPI_CFG2_COMM_Msk
17614#define SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos)
17615#define SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos)
17617#define SPI_CFG2_SP_Pos (19U)
17618#define SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos)
17619#define SPI_CFG2_SP SPI_CFG2_SP_Msk
17620#define SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos)
17621#define SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos)
17622#define SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos)
17624#define SPI_CFG2_MASTER_Pos (22U)
17625#define SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos)
17626#define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk
17627#define SPI_CFG2_LSBFRST_Pos (23U)
17628#define SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos)
17629#define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk
17630#define SPI_CFG2_CPHA_Pos (24U)
17631#define SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos)
17632#define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk
17633#define SPI_CFG2_CPOL_Pos (25U)
17634#define SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos)
17635#define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk
17636#define SPI_CFG2_SSM_Pos (26U)
17637#define SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos)
17638#define SPI_CFG2_SSM SPI_CFG2_SSM_Msk
17640#define SPI_CFG2_SSIOP_Pos (28U)
17641#define SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos)
17642#define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk
17643#define SPI_CFG2_SSOE_Pos (29U)
17644#define SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos)
17645#define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk
17646#define SPI_CFG2_SSOM_Pos (30U)
17647#define SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos)
17648#define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk
17650#define SPI_CFG2_AFCNTR_Pos (31U)
17651#define SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos)
17652#define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk
17654/******************* Bit definition for SPI_IER register ********************/
17655#define SPI_IER_RXPIE_Pos (0U)
17656#define SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos)
17657#define SPI_IER_RXPIE SPI_IER_RXPIE_Msk
17658#define SPI_IER_TXPIE_Pos (1U)
17659#define SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos)
17660#define SPI_IER_TXPIE SPI_IER_TXPIE_Msk
17661#define SPI_IER_DXPIE_Pos (2U)
17662#define SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos)
17663#define SPI_IER_DXPIE SPI_IER_DXPIE_Msk
17664#define SPI_IER_EOTIE_Pos (3U)
17665#define SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos)
17666#define SPI_IER_EOTIE SPI_IER_EOTIE_Msk
17667#define SPI_IER_TXTFIE_Pos (4U)
17668#define SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos)
17669#define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk
17670#define SPI_IER_UDRIE_Pos (5U)
17671#define SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos)
17672#define SPI_IER_UDRIE SPI_IER_UDRIE_Msk
17673#define SPI_IER_OVRIE_Pos (6U)
17674#define SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos)
17675#define SPI_IER_OVRIE SPI_IER_OVRIE_Msk
17676#define SPI_IER_CRCEIE_Pos (7U)
17677#define SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos)
17678#define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk
17679#define SPI_IER_TIFREIE_Pos (8U)
17680#define SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos)
17681#define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk
17682#define SPI_IER_MODFIE_Pos (9U)
17683#define SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos)
17684#define SPI_IER_MODFIE SPI_IER_MODFIE_Msk
17685#define SPI_IER_TSERFIE_Pos (10U)
17686#define SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos)
17687#define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk
17689/******************* Bit definition for SPI_SR register ********************/
17690#define SPI_SR_RXP_Pos (0U)
17691#define SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos)
17692#define SPI_SR_RXP SPI_SR_RXP_Msk
17693#define SPI_SR_TXP_Pos (1U)
17694#define SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos)
17695#define SPI_SR_TXP SPI_SR_TXP_Msk
17696#define SPI_SR_DXP_Pos (2U)
17697#define SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos)
17698#define SPI_SR_DXP SPI_SR_DXP_Msk
17699#define SPI_SR_EOT_Pos (3U)
17700#define SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos)
17701#define SPI_SR_EOT SPI_SR_EOT_Msk
17702#define SPI_SR_TXTF_Pos (4U)
17703#define SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos)
17704#define SPI_SR_TXTF SPI_SR_TXTF_Msk
17705#define SPI_SR_UDR_Pos (5U)
17706#define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)
17707#define SPI_SR_UDR SPI_SR_UDR_Msk
17708#define SPI_SR_OVR_Pos (6U)
17709#define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)
17710#define SPI_SR_OVR SPI_SR_OVR_Msk
17711#define SPI_SR_CRCE_Pos (7U)
17712#define SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos)
17713#define SPI_SR_CRCE SPI_SR_CRCE_Msk
17714#define SPI_SR_TIFRE_Pos (8U)
17715#define SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos)
17716#define SPI_SR_TIFRE SPI_SR_TIFRE_Msk
17717#define SPI_SR_MODF_Pos (9U)
17718#define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)
17719#define SPI_SR_MODF SPI_SR_MODF_Msk
17720#define SPI_SR_TSERF_Pos (10U)
17721#define SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos)
17722#define SPI_SR_TSERF SPI_SR_TSERF_Msk
17723#define SPI_SR_SUSP_Pos (11U)
17724#define SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos)
17725#define SPI_SR_SUSP SPI_SR_SUSP_Msk
17726#define SPI_SR_TXC_Pos (12U)
17727#define SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos)
17728#define SPI_SR_TXC SPI_SR_TXC_Msk
17729#define SPI_SR_RXPLVL_Pos (13U)
17730#define SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos)
17731#define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk
17732#define SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos)
17733#define SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos)
17734#define SPI_SR_RXWNE_Pos (15U)
17735#define SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos)
17736#define SPI_SR_RXWNE SPI_SR_RXWNE_Msk
17737#define SPI_SR_CTSIZE_Pos (16U)
17738#define SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos)
17739#define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk
17741/******************* Bit definition for SPI_IFCR register ********************/
17742#define SPI_IFCR_EOTC_Pos (3U)
17743#define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos)
17744#define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk
17745#define SPI_IFCR_TXTFC_Pos (4U)
17746#define SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos)
17747#define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk
17748#define SPI_IFCR_UDRC_Pos (5U)
17749#define SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos)
17750#define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk
17751#define SPI_IFCR_OVRC_Pos (6U)
17752#define SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos)
17753#define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk
17754#define SPI_IFCR_CRCEC_Pos (7U)
17755#define SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos)
17756#define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk
17757#define SPI_IFCR_TIFREC_Pos (8U)
17758#define SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos)
17759#define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk
17760#define SPI_IFCR_MODFC_Pos (9U)
17761#define SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos)
17762#define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk
17763#define SPI_IFCR_TSERFC_Pos (10U)
17764#define SPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos)
17765#define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk
17766#define SPI_IFCR_SUSPC_Pos (11U)
17767#define SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos)
17768#define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk
17770/******************* Bit definition for SPI_TXDR register ********************/
17771#define SPI_TXDR_TXDR_Pos (0U)
17772#define SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)
17773#define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
17774
17775/******************* Bit definition for SPI_RXDR register ********************/
17776#define SPI_RXDR_RXDR_Pos (0U)
17777#define SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)
17778#define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
17779
17780/******************* Bit definition for SPI_CRCPOLY register ********************/
17781#define SPI_CRCPOLY_CRCPOLY_Pos (0U)
17782#define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)
17783#define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
17784
17785/******************* Bit definition for SPI_TXCRC register ********************/
17786#define SPI_TXCRC_TXCRC_Pos (0U)
17787#define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)
17788#define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
17789
17790/******************* Bit definition for SPI_RXCRC register ********************/
17791#define SPI_RXCRC_RXCRC_Pos (0U)
17792#define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)
17793#define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
17794
17795/******************* Bit definition for SPI_UDRDR register ********************/
17796#define SPI_UDRDR_UDRDR_Pos (0U)
17797#define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)
17798#define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
17799
17800/****************** Bit definition for SPI_I2SCFGR register *****************/
17801#define SPI_I2SCFGR_I2SMOD_Pos (0U)
17802#define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)
17803#define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk
17804#define SPI_I2SCFGR_I2SCFG_Pos (1U)
17805#define SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)
17806#define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk
17807#define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)
17808#define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)
17809#define SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)
17810#define SPI_I2SCFGR_I2SSTD_Pos (4U)
17811#define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)
17812#define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk
17813#define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)
17814#define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)
17815#define SPI_I2SCFGR_PCMSYNC_Pos (7U)
17816#define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)
17817#define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk
17818#define SPI_I2SCFGR_DATLEN_Pos (8U)
17819#define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)
17820#define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk
17821#define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)
17822#define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)
17823#define SPI_I2SCFGR_CHLEN_Pos (10U)
17824#define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)
17825#define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk
17826#define SPI_I2SCFGR_CKPOL_Pos (11U)
17827#define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)
17828#define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk
17829#define SPI_I2SCFGR_FIXCH_Pos (12U)
17830#define SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos)
17831#define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk
17832#define SPI_I2SCFGR_WSINV_Pos (13U)
17833#define SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos)
17834#define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk
17835#define SPI_I2SCFGR_DATFMT_Pos (14U)
17836#define SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos)
17837#define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk
17838#define SPI_I2SCFGR_I2SDIV_Pos (16U)
17839#define SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)
17840#define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk
17841#define SPI_I2SCFGR_ODD_Pos (24U)
17842#define SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos)
17843#define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk
17844#define SPI_I2SCFGR_MCKOE_Pos (25U)
17845#define SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos)
17846#define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk
17849/******************************************************************************/
17850/* */
17851/* QUADSPI */
17852/* */
17853/******************************************************************************/
17854/***************** Bit definition for QUADSPI_CR register *******************/
17855#define QUADSPI_CR_EN_Pos (0U)
17856#define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos)
17857#define QUADSPI_CR_EN QUADSPI_CR_EN_Msk
17858#define QUADSPI_CR_ABORT_Pos (1U)
17859#define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos)
17860#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk
17861#define QUADSPI_CR_DMAEN_Pos (2U)
17862#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos)
17863#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk
17864#define QUADSPI_CR_TCEN_Pos (3U)
17865#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos)
17866#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk
17867#define QUADSPI_CR_SSHIFT_Pos (4U)
17868#define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos)
17869#define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk
17870#define QUADSPI_CR_DFM_Pos (6U)
17871#define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos)
17872#define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk
17873#define QUADSPI_CR_FSEL_Pos (7U)
17874#define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos)
17875#define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk
17876#define QUADSPI_CR_FTHRES_Pos (8U)
17877#define QUADSPI_CR_FTHRES_Msk (0x1FUL << QUADSPI_CR_FTHRES_Pos)
17878#define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk
17879#define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos)
17880#define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos)
17881#define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos)
17882#define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos)
17883#define QUADSPI_CR_FTHRES_4 (0x10UL << QUADSPI_CR_FTHRES_Pos)
17884#define QUADSPI_CR_TEIE_Pos (16U)
17885#define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos)
17886#define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk
17887#define QUADSPI_CR_TCIE_Pos (17U)
17888#define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos)
17889#define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk
17890#define QUADSPI_CR_FTIE_Pos (18U)
17891#define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos)
17892#define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk
17893#define QUADSPI_CR_SMIE_Pos (19U)
17894#define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos)
17895#define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk
17896#define QUADSPI_CR_TOIE_Pos (20U)
17897#define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos)
17898#define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk
17899#define QUADSPI_CR_APMS_Pos (22U)
17900#define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos)
17901#define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk
17902#define QUADSPI_CR_PMM_Pos (23U)
17903#define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos)
17904#define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk
17905#define QUADSPI_CR_PRESCALER_Pos (24U)
17906#define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos)
17907#define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk
17908#define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos)
17909#define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos)
17910#define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos)
17911#define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos)
17912#define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos)
17913#define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos)
17914#define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos)
17915#define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos)
17917/***************** Bit definition for QUADSPI_DCR register ******************/
17918#define QUADSPI_DCR_CKMODE_Pos (0U)
17919#define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos)
17920#define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk
17921#define QUADSPI_DCR_CSHT_Pos (8U)
17922#define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos)
17923#define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk
17924#define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos)
17925#define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos)
17926#define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos)
17927#define QUADSPI_DCR_FSIZE_Pos (16U)
17928#define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos)
17929#define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk
17930#define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos)
17931#define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos)
17932#define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos)
17933#define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos)
17934#define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos)
17936/****************** Bit definition for QUADSPI_SR register *******************/
17937#define QUADSPI_SR_TEF_Pos (0U)
17938#define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos)
17939#define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk
17940#define QUADSPI_SR_TCF_Pos (1U)
17941#define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos)
17942#define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk
17943#define QUADSPI_SR_FTF_Pos (2U)
17944#define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos)
17945#define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk
17946#define QUADSPI_SR_SMF_Pos (3U)
17947#define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos)
17948#define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk
17949#define QUADSPI_SR_TOF_Pos (4U)
17950#define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos)
17951#define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk
17952#define QUADSPI_SR_BUSY_Pos (5U)
17953#define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos)
17954#define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk
17955#define QUADSPI_SR_FLEVEL_Pos (8U)
17956#define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos)
17957#define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk
17958#define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos)
17959#define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos)
17960#define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos)
17961#define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos)
17962#define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos)
17963#define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos)
17965/****************** Bit definition for QUADSPI_FCR register ******************/
17966#define QUADSPI_FCR_CTEF_Pos (0U)
17967#define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos)
17968#define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk
17969#define QUADSPI_FCR_CTCF_Pos (1U)
17970#define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos)
17971#define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk
17972#define QUADSPI_FCR_CSMF_Pos (3U)
17973#define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos)
17974#define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk
17975#define QUADSPI_FCR_CTOF_Pos (4U)
17976#define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos)
17977#define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk
17979/****************** Bit definition for QUADSPI_DLR register ******************/
17980#define QUADSPI_DLR_DL_Pos (0U)
17981#define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)
17982#define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk
17984/****************** Bit definition for QUADSPI_CCR register ******************/
17985#define QUADSPI_CCR_INSTRUCTION_Pos (0U)
17986#define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos)
17987#define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk
17988#define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos)
17989#define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos)
17990#define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos)
17991#define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos)
17992#define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos)
17993#define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos)
17994#define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos)
17995#define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos)
17996#define QUADSPI_CCR_IMODE_Pos (8U)
17997#define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos)
17998#define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk
17999#define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos)
18000#define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos)
18001#define QUADSPI_CCR_ADMODE_Pos (10U)
18002#define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos)
18003#define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk
18004#define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos)
18005#define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos)
18006#define QUADSPI_CCR_ADSIZE_Pos (12U)
18007#define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos)
18008#define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk
18009#define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos)
18010#define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos)
18011#define QUADSPI_CCR_ABMODE_Pos (14U)
18012#define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos)
18013#define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk
18014#define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos)
18015#define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos)
18016#define QUADSPI_CCR_ABSIZE_Pos (16U)
18017#define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos)
18018#define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk
18019#define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos)
18020#define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos)
18021#define QUADSPI_CCR_DCYC_Pos (18U)
18022#define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos)
18023#define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk
18024#define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos)
18025#define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos)
18026#define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos)
18027#define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos)
18028#define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos)
18029#define QUADSPI_CCR_DMODE_Pos (24U)
18030#define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos)
18031#define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk
18032#define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos)
18033#define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos)
18034#define QUADSPI_CCR_FMODE_Pos (26U)
18035#define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos)
18036#define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk
18037#define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos)
18038#define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos)
18039#define QUADSPI_CCR_SIOO_Pos (28U)
18040#define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos)
18041#define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk
18042#define QUADSPI_CCR_DHHC_Pos (30U)
18043#define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos)
18044#define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk
18045#define QUADSPI_CCR_DDRM_Pos (31U)
18046#define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos)
18047#define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk
18049/****************** Bit definition for QUADSPI_AR register *******************/
18050#define QUADSPI_AR_ADDRESS_Pos (0U)
18051#define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos)
18052#define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk
18054/****************** Bit definition for QUADSPI_ABR register ******************/
18055#define QUADSPI_ABR_ALTERNATE_Pos (0U)
18056#define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos)
18057#define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk
18059/****************** Bit definition for QUADSPI_DR register *******************/
18060#define QUADSPI_DR_DATA_Pos (0U)
18061#define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos)
18062#define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk
18064/****************** Bit definition for QUADSPI_PSMKR register ****************/
18065#define QUADSPI_PSMKR_MASK_Pos (0U)
18066#define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos)
18067#define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk
18069/****************** Bit definition for QUADSPI_PSMAR register ****************/
18070#define QUADSPI_PSMAR_MATCH_Pos (0U)
18071#define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos)
18072#define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk
18074/****************** Bit definition for QUADSPI_PIR register *****************/
18075#define QUADSPI_PIR_INTERVAL_Pos (0U)
18076#define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos)
18077#define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk
18079/****************** Bit definition for QUADSPI_LPTR register *****************/
18080#define QUADSPI_LPTR_TIMEOUT_Pos (0U)
18081#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos)
18082#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk
18084/******************************************************************************/
18085/* */
18086/* SYSCFG */
18087/* */
18088/******************************************************************************/
18089
18090/****************** Bit definition for SYSCFG_PMCR register ******************/
18091#define SYSCFG_PMCR_I2C1_FMP_Pos (0U)
18092#define SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)
18093#define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk
18094#define SYSCFG_PMCR_I2C2_FMP_Pos (1U)
18095#define SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)
18096#define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk
18097#define SYSCFG_PMCR_I2C3_FMP_Pos (2U)
18098#define SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)
18099#define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk
18100#define SYSCFG_PMCR_I2C4_FMP_Pos (3U)
18101#define SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)
18102#define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk
18103#define SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U)
18104#define SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos)
18105#define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk
18106#define SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U)
18107#define SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos)
18108#define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk
18109#define SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U)
18110#define SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos)
18111#define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk
18112#define SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U)
18113#define SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos)
18114#define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk
18115#define SYSCFG_PMCR_BOOSTEN_Pos (8U)
18116#define SYSCFG_PMCR_BOOSTEN_Msk (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)
18117#define SYSCFG_PMCR_BOOSTEN SYSCFG_PMCR_BOOSTEN_Msk
18119#define SYSCFG_PMCR_BOOSTVDDSEL_Pos (9U)
18120#define SYSCFG_PMCR_BOOSTVDDSEL_Msk (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos)
18121#define SYSCFG_PMCR_BOOSTVDDSEL SYSCFG_PMCR_BOOSTVDDSEL_Msk
18123#define SYSCFG_PMCR_EPIS_SEL_Pos (21U)
18124#define SYSCFG_PMCR_EPIS_SEL_Msk (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)
18125#define SYSCFG_PMCR_EPIS_SEL SYSCFG_PMCR_EPIS_SEL_Msk
18126#define SYSCFG_PMCR_EPIS_SEL_0 (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)
18127#define SYSCFG_PMCR_EPIS_SEL_1 (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)
18128#define SYSCFG_PMCR_EPIS_SEL_2 (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)
18129#define SYSCFG_PMCR_PA0SO_Pos (24U)
18130#define SYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos)
18131#define SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk
18132#define SYSCFG_PMCR_PA1SO_Pos (25U)
18133#define SYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos)
18134#define SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk
18135#define SYSCFG_PMCR_PC2SO_Pos (26U)
18136#define SYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos)
18137#define SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk
18138#define SYSCFG_PMCR_PC3SO_Pos (27U)
18139#define SYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos)
18140#define SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk
18142/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
18143#define SYSCFG_EXTICR1_EXTI0_Pos (0U)
18144#define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)
18145#define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk
18146#define SYSCFG_EXTICR1_EXTI1_Pos (4U)
18147#define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)
18148#define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk
18149#define SYSCFG_EXTICR1_EXTI2_Pos (8U)
18150#define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)
18151#define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk
18152#define SYSCFG_EXTICR1_EXTI3_Pos (12U)
18153#define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)
18154#define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk
18158#define SYSCFG_EXTICR1_EXTI0_PA (0U)
18159#define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U)
18160#define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U)
18161#define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U)
18162#define SYSCFG_EXTICR1_EXTI0_PE (0x00000004U)
18163#define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U)
18164#define SYSCFG_EXTICR1_EXTI0_PG (0x00000006U)
18165#define SYSCFG_EXTICR1_EXTI0_PH (0x00000007U)
18166#define SYSCFG_EXTICR1_EXTI0_PI (0x00000008U)
18167#define SYSCFG_EXTICR1_EXTI0_PJ (0x00000009U)
18168#define SYSCFG_EXTICR1_EXTI0_PK (0x0000000AU)
18173#define SYSCFG_EXTICR1_EXTI1_PA (0U)
18174#define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U)
18175#define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U)
18176#define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U)
18177#define SYSCFG_EXTICR1_EXTI1_PE (0x00000040U)
18178#define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U)
18179#define SYSCFG_EXTICR1_EXTI1_PG (0x00000060U)
18180#define SYSCFG_EXTICR1_EXTI1_PH (0x00000070U)
18181#define SYSCFG_EXTICR1_EXTI1_PI (0x00000080U)
18182#define SYSCFG_EXTICR1_EXTI1_PJ (0x00000090U)
18183#define SYSCFG_EXTICR1_EXTI1_PK (0x000000A0U)
18187#define SYSCFG_EXTICR1_EXTI2_PA (0U)
18188#define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U)
18189#define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U)
18190#define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U)
18191#define SYSCFG_EXTICR1_EXTI2_PE (0x00000400U)
18192#define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U)
18193#define SYSCFG_EXTICR1_EXTI2_PG (0x00000600U)
18194#define SYSCFG_EXTICR1_EXTI2_PH (0x00000700U)
18195#define SYSCFG_EXTICR1_EXTI2_PI (0x00000800U)
18196#define SYSCFG_EXTICR1_EXTI2_PJ (0x00000900U)
18197#define SYSCFG_EXTICR1_EXTI2_PK (0x00000A00U)
18202#define SYSCFG_EXTICR1_EXTI3_PA (0U)
18203#define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U)
18204#define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U)
18205#define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U)
18206#define SYSCFG_EXTICR1_EXTI3_PE (0x00004000U)
18207#define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U)
18208#define SYSCFG_EXTICR1_EXTI3_PG (0x00006000U)
18209#define SYSCFG_EXTICR1_EXTI3_PH (0x00007000U)
18210#define SYSCFG_EXTICR1_EXTI3_PI (0x00008000U)
18211#define SYSCFG_EXTICR1_EXTI3_PJ (0x00009000U)
18212#define SYSCFG_EXTICR1_EXTI3_PK (0x0000A000U)
18214/***************** Bit definition for SYSCFG_EXTICR2 register ***************/
18215#define SYSCFG_EXTICR2_EXTI4_Pos (0U)
18216#define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)
18217#define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk
18218#define SYSCFG_EXTICR2_EXTI5_Pos (4U)
18219#define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)
18220#define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk
18221#define SYSCFG_EXTICR2_EXTI6_Pos (8U)
18222#define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)
18223#define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk
18224#define SYSCFG_EXTICR2_EXTI7_Pos (12U)
18225#define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)
18226#define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk
18230#define SYSCFG_EXTICR2_EXTI4_PA (0U)
18231#define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U)
18232#define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U)
18233#define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U)
18234#define SYSCFG_EXTICR2_EXTI4_PE (0x00000004U)
18235#define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U)
18236#define SYSCFG_EXTICR2_EXTI4_PG (0x00000006U)
18237#define SYSCFG_EXTICR2_EXTI4_PH (0x00000007U)
18238#define SYSCFG_EXTICR2_EXTI4_PI (0x00000008U)
18239#define SYSCFG_EXTICR2_EXTI4_PJ (0x00000009U)
18240#define SYSCFG_EXTICR2_EXTI4_PK (0x0000000AU)
18244#define SYSCFG_EXTICR2_EXTI5_PA (0U)
18245#define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U)
18246#define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U)
18247#define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U)
18248#define SYSCFG_EXTICR2_EXTI5_PE (0x00000040U)
18249#define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U)
18250#define SYSCFG_EXTICR2_EXTI5_PG (0x00000060U)
18251#define SYSCFG_EXTICR2_EXTI5_PH (0x00000070U)
18252#define SYSCFG_EXTICR2_EXTI5_PI (0x00000080U)
18253#define SYSCFG_EXTICR2_EXTI5_PJ (0x00000090U)
18254#define SYSCFG_EXTICR2_EXTI5_PK (0x000000A0U)
18258#define SYSCFG_EXTICR2_EXTI6_PA (0U)
18259#define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U)
18260#define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U)
18261#define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U)
18262#define SYSCFG_EXTICR2_EXTI6_PE (0x00000400U)
18263#define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U)
18264#define SYSCFG_EXTICR2_EXTI6_PG (0x00000600U)
18265#define SYSCFG_EXTICR2_EXTI6_PH (0x00000700U)
18266#define SYSCFG_EXTICR2_EXTI6_PI (0x00000800U)
18267#define SYSCFG_EXTICR2_EXTI6_PJ (0x00000900U)
18268#define SYSCFG_EXTICR2_EXTI6_PK (0x00000A00U)
18273#define SYSCFG_EXTICR2_EXTI7_PA (0U)
18274#define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U)
18275#define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U)
18276#define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U)
18277#define SYSCFG_EXTICR2_EXTI7_PE (0x00004000U)
18278#define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U)
18279#define SYSCFG_EXTICR2_EXTI7_PG (0x00006000U)
18280#define SYSCFG_EXTICR2_EXTI7_PH (0x00007000U)
18281#define SYSCFG_EXTICR2_EXTI7_PI (0x00008000U)
18282#define SYSCFG_EXTICR2_EXTI7_PJ (0x00009000U)
18283#define SYSCFG_EXTICR2_EXTI7_PK (0x0000A000U)
18285/***************** Bit definition for SYSCFG_EXTICR3 register ***************/
18286#define SYSCFG_EXTICR3_EXTI8_Pos (0U)
18287#define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)
18288#define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk
18289#define SYSCFG_EXTICR3_EXTI9_Pos (4U)
18290#define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)
18291#define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk
18292#define SYSCFG_EXTICR3_EXTI10_Pos (8U)
18293#define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)
18294#define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk
18295#define SYSCFG_EXTICR3_EXTI11_Pos (12U)
18296#define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)
18297#define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk
18302#define SYSCFG_EXTICR3_EXTI8_PA (0U)
18303#define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U)
18304#define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U)
18305#define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U)
18306#define SYSCFG_EXTICR3_EXTI8_PE (0x00000004U)
18307#define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U)
18308#define SYSCFG_EXTICR3_EXTI8_PG (0x00000006U)
18309#define SYSCFG_EXTICR3_EXTI8_PH (0x00000007U)
18310#define SYSCFG_EXTICR3_EXTI8_PI (0x00000008U)
18311#define SYSCFG_EXTICR3_EXTI8_PJ (0x00000009U)
18312#define SYSCFG_EXTICR3_EXTI8_PK (0x0000000AU)
18317#define SYSCFG_EXTICR3_EXTI9_PA (0U)
18318#define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U)
18319#define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U)
18320#define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U)
18321#define SYSCFG_EXTICR3_EXTI9_PE (0x00000040U)
18322#define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U)
18323#define SYSCFG_EXTICR3_EXTI9_PG (0x00000060U)
18324#define SYSCFG_EXTICR3_EXTI9_PH (0x00000070U)
18325#define SYSCFG_EXTICR3_EXTI9_PI (0x00000080U)
18326#define SYSCFG_EXTICR3_EXTI9_PJ (0x00000090U)
18327#define SYSCFG_EXTICR3_EXTI9_PK (0x000000A0U)
18332#define SYSCFG_EXTICR3_EXTI10_PA (0U)
18333#define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U)
18334#define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U)
18335#define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U)
18336#define SYSCFG_EXTICR3_EXTI10_PE (0x00000400U)
18337#define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U)
18338#define SYSCFG_EXTICR3_EXTI10_PG (0x00000600U)
18339#define SYSCFG_EXTICR3_EXTI10_PH (0x00000700U)
18340#define SYSCFG_EXTICR3_EXTI10_PI (0x00000800U)
18341#define SYSCFG_EXTICR3_EXTI10_PJ (0x00000900U)
18342#define SYSCFG_EXTICR3_EXTI10_PK (0x00000A00U)
18347#define SYSCFG_EXTICR3_EXTI11_PA (0U)
18348#define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U)
18349#define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U)
18350#define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U)
18351#define SYSCFG_EXTICR3_EXTI11_PE (0x00004000U)
18352#define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U)
18353#define SYSCFG_EXTICR3_EXTI11_PG (0x00006000U)
18354#define SYSCFG_EXTICR3_EXTI11_PH (0x00007000U)
18355#define SYSCFG_EXTICR3_EXTI11_PI (0x00008000U)
18356#define SYSCFG_EXTICR3_EXTI11_PJ (0x00009000U)
18357#define SYSCFG_EXTICR3_EXTI11_PK (0x0000A000U)
18359/***************** Bit definition for SYSCFG_EXTICR4 register ***************/
18360#define SYSCFG_EXTICR4_EXTI12_Pos (0U)
18361#define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)
18362#define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk
18363#define SYSCFG_EXTICR4_EXTI13_Pos (4U)
18364#define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)
18365#define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk
18366#define SYSCFG_EXTICR4_EXTI14_Pos (8U)
18367#define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)
18368#define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk
18369#define SYSCFG_EXTICR4_EXTI15_Pos (12U)
18370#define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)
18371#define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk
18375#define SYSCFG_EXTICR4_EXTI12_PA (0U)
18376#define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U)
18377#define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U)
18378#define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U)
18379#define SYSCFG_EXTICR4_EXTI12_PE (0x00000004U)
18380#define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U)
18381#define SYSCFG_EXTICR4_EXTI12_PG (0x00000006U)
18382#define SYSCFG_EXTICR4_EXTI12_PH (0x00000007U)
18383#define SYSCFG_EXTICR4_EXTI12_PI (0x00000008U)
18384#define SYSCFG_EXTICR4_EXTI12_PJ (0x00000009U)
18385#define SYSCFG_EXTICR4_EXTI12_PK (0x0000000AU)
18389#define SYSCFG_EXTICR4_EXTI13_PA (0U)
18390#define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U)
18391#define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U)
18392#define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U)
18393#define SYSCFG_EXTICR4_EXTI13_PE (0x00000040U)
18394#define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U)
18395#define SYSCFG_EXTICR4_EXTI13_PG (0x00000060U)
18396#define SYSCFG_EXTICR4_EXTI13_PH (0x00000070U)
18397#define SYSCFG_EXTICR4_EXTI13_PI (0x00000080U)
18398#define SYSCFG_EXTICR4_EXTI13_PJ (0x00000090U)
18399#define SYSCFG_EXTICR4_EXTI13_PK (0x000000A0U)
18403#define SYSCFG_EXTICR4_EXTI14_PA (0U)
18404#define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U)
18405#define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U)
18406#define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U)
18407#define SYSCFG_EXTICR4_EXTI14_PE (0x00000400U)
18408#define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U)
18409#define SYSCFG_EXTICR4_EXTI14_PG (0x00000600U)
18410#define SYSCFG_EXTICR4_EXTI14_PH (0x00000700U)
18411#define SYSCFG_EXTICR4_EXTI14_PI (0x00000800U)
18412#define SYSCFG_EXTICR4_EXTI14_PJ (0x00000900U)
18413#define SYSCFG_EXTICR4_EXTI14_PK (0x00000A00U)
18417#define SYSCFG_EXTICR4_EXTI15_PA (0U)
18418#define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U)
18419#define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U)
18420#define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U)
18421#define SYSCFG_EXTICR4_EXTI15_PE (0x00004000U)
18422#define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U)
18423#define SYSCFG_EXTICR4_EXTI15_PG (0x00006000U)
18424#define SYSCFG_EXTICR4_EXTI15_PH (0x00007000U)
18425#define SYSCFG_EXTICR4_EXTI15_PI (0x00008000U)
18426#define SYSCFG_EXTICR4_EXTI15_PJ (0x00009000U)
18427#define SYSCFG_EXTICR4_EXTI15_PK (0x0000A000U)
18429/****************** Bit definition for SYSCFG_CFGR register ******************/
18430#define SYSCFG_CFGR_PVDL_Pos (2U)
18431#define SYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos)
18432#define SYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk
18433#define SYSCFG_CFGR_FLASHL_Pos (3U)
18434#define SYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos)
18435#define SYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk
18436#define SYSCFG_CFGR_CM7L_Pos (6U)
18437#define SYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos)
18438#define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk
18439#define SYSCFG_CFGR_BKRAML_Pos (7U)
18440#define SYSCFG_CFGR_BKRAML_Msk (0x1UL << SYSCFG_CFGR_BKRAML_Pos)
18441#define SYSCFG_CFGR_BKRAML SYSCFG_CFGR_BKRAML_Msk
18442#define SYSCFG_CFGR_SRAM4L_Pos (9U)
18443#define SYSCFG_CFGR_SRAM4L_Msk (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)
18444#define SYSCFG_CFGR_SRAM4L SYSCFG_CFGR_SRAM4L_Msk
18445#define SYSCFG_CFGR_SRAM3L_Pos (10U)
18446#define SYSCFG_CFGR_SRAM3L_Msk (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)
18447#define SYSCFG_CFGR_SRAM3L SYSCFG_CFGR_SRAM3L_Msk
18448#define SYSCFG_CFGR_SRAM2L_Pos (11U)
18449#define SYSCFG_CFGR_SRAM2L_Msk (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)
18450#define SYSCFG_CFGR_SRAM2L SYSCFG_CFGR_SRAM2L_Msk
18451#define SYSCFG_CFGR_SRAM1L_Pos (12U)
18452#define SYSCFG_CFGR_SRAM1L_Msk (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)
18453#define SYSCFG_CFGR_SRAM1L SYSCFG_CFGR_SRAM1L_Msk
18454#define SYSCFG_CFGR_DTCML_Pos (13U)
18455#define SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos)
18456#define SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk
18457#define SYSCFG_CFGR_ITCML_Pos (14U)
18458#define SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos)
18459#define SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk
18460#define SYSCFG_CFGR_AXISRAML_Pos (15U)
18461#define SYSCFG_CFGR_AXISRAML_Msk (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)
18462#define SYSCFG_CFGR_AXISRAML SYSCFG_CFGR_AXISRAML_Msk
18464/****************** Bit definition for SYSCFG_CCCSR register ******************/
18465#define SYSCFG_CCCSR_EN_Pos (0U)
18466#define SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos)
18467#define SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk
18468#define SYSCFG_CCCSR_CS_Pos (1U)
18469#define SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos)
18470#define SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk
18471#define SYSCFG_CCCSR_READY_Pos (8U)
18472#define SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos)
18473#define SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk
18474#define SYSCFG_CCCSR_HSLV_Pos (16U)
18475#define SYSCFG_CCCSR_HSLV_Msk (0x1UL << SYSCFG_CCCSR_HSLV_Pos)
18476#define SYSCFG_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk
18478/****************** Bit definition for SYSCFG_CCVR register *******************/
18479#define SYSCFG_CCVR_NCV_Pos (0U)
18480#define SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos)
18481#define SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk
18482#define SYSCFG_CCVR_PCV_Pos (4U)
18483#define SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos)
18484#define SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk
18486/****************** Bit definition for SYSCFG_CCCR register *******************/
18487#define SYSCFG_CCCR_NCC_Pos (0U)
18488#define SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos)
18489#define SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk
18490#define SYSCFG_CCCR_PCC_Pos (4U)
18491#define SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos)
18492#define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk
18493/****************** Bit definition for SYSCFG_PWRCR register *******************/
18494#define SYSCFG_PWRCR_ODEN_Pos (0U)
18495#define SYSCFG_PWRCR_ODEN_Msk (0x1UL << SYSCFG_PWRCR_ODEN_Pos)
18496#define SYSCFG_PWRCR_ODEN SYSCFG_PWRCR_ODEN_Msk
18498/****************** Bit definition for SYSCFG_PKGR register *******************/
18499#define SYSCFG_PKGR_PKG_Pos (0U)
18500#define SYSCFG_PKGR_PKG_Msk (0xFUL << SYSCFG_PKGR_PKG_Pos)
18501#define SYSCFG_PKGR_PKG SYSCFG_PKGR_PKG_Msk
18503/****************** Bit definition for SYSCFG_UR0 register *******************/
18504#define SYSCFG_UR0_BKS_Pos (0U)
18505#define SYSCFG_UR0_BKS_Msk (0x1UL << SYSCFG_UR0_BKS_Pos)
18506#define SYSCFG_UR0_BKS SYSCFG_UR0_BKS_Msk
18507#define SYSCFG_UR0_RDP_Pos (16U)
18508#define SYSCFG_UR0_RDP_Msk (0xFFUL << SYSCFG_UR0_RDP_Pos)
18509#define SYSCFG_UR0_RDP SYSCFG_UR0_RDP_Msk
18511/****************** Bit definition for SYSCFG_UR2 register *******************/
18512#define SYSCFG_UR2_BORH_Pos (0U)
18513#define SYSCFG_UR2_BORH_Msk (0x3UL << SYSCFG_UR2_BORH_Pos)
18514#define SYSCFG_UR2_BORH SYSCFG_UR2_BORH_Msk
18515#define SYSCFG_UR2_BORH_0 (0x1UL << SYSCFG_UR2_BORH_Pos)
18516#define SYSCFG_UR2_BORH_1 (0x2UL << SYSCFG_UR2_BORH_Pos)
18517#define SYSCFG_UR2_BOOT_ADD0_Pos (16U)
18518#define SYSCFG_UR2_BOOT_ADD0_Msk (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos)
18519#define SYSCFG_UR2_BOOT_ADD0 SYSCFG_UR2_BOOT_ADD0_Msk
18520/****************** Bit definition for SYSCFG_UR3 register *******************/
18521#define SYSCFG_UR3_BOOT_ADD1_Pos (0U)
18522#define SYSCFG_UR3_BOOT_ADD1_Msk (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos)
18523#define SYSCFG_UR3_BOOT_ADD1 SYSCFG_UR3_BOOT_ADD1_Msk
18525 /****************** Bit definition for SYSCFG_UR4 register *******************/
18526
18527#define SYSCFG_UR4_MEPAD_BANK1_Pos (16U)
18528#define SYSCFG_UR4_MEPAD_BANK1_Msk (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)
18529#define SYSCFG_UR4_MEPAD_BANK1 SYSCFG_UR4_MEPAD_BANK1_Msk
18531/****************** Bit definition for SYSCFG_UR5 register *******************/
18532#define SYSCFG_UR5_MESAD_BANK1_Pos (0U)
18533#define SYSCFG_UR5_MESAD_BANK1_Msk (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)
18534#define SYSCFG_UR5_MESAD_BANK1 SYSCFG_UR5_MESAD_BANK1_Msk
18535#define SYSCFG_UR5_WRPN_BANK1_Pos (16U)
18536#define SYSCFG_UR5_WRPN_BANK1_Msk (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)
18537#define SYSCFG_UR5_WRPN_BANK1 SYSCFG_UR5_WRPN_BANK1_Msk
18539/****************** Bit definition for SYSCFG_UR6 register *******************/
18540#define SYSCFG_UR6_PABEG_BANK1_Pos (0U)
18541#define SYSCFG_UR6_PABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos)
18542#define SYSCFG_UR6_PABEG_BANK1 SYSCFG_UR6_PABEG_BANK1_Msk
18543#define SYSCFG_UR6_PAEND_BANK1_Pos (16U)
18544#define SYSCFG_UR6_PAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos)
18545#define SYSCFG_UR6_PAEND_BANK1 SYSCFG_UR6_PAEND_BANK1_Msk
18547/****************** Bit definition for SYSCFG_UR7 register *******************/
18548#define SYSCFG_UR7_SABEG_BANK1_Pos (0U)
18549#define SYSCFG_UR7_SABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos)
18550#define SYSCFG_UR7_SABEG_BANK1 SYSCFG_UR7_SABEG_BANK1_Msk
18551#define SYSCFG_UR7_SAEND_BANK1_Pos (16U)
18552#define SYSCFG_UR7_SAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos)
18553#define SYSCFG_UR7_SAEND_BANK1 SYSCFG_UR7_SAEND_BANK1_Msk
18555/****************** Bit definition for SYSCFG_UR8 register *******************/
18556#define SYSCFG_UR8_MEPAD_BANK2_Pos (0U)
18557#define SYSCFG_UR8_MEPAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)
18558#define SYSCFG_UR8_MEPAD_BANK2 SYSCFG_UR8_MEPAD_BANK2_Msk
18559#define SYSCFG_UR8_MESAD_BANK2_Pos (16U)
18560#define SYSCFG_UR8_MESAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)
18561#define SYSCFG_UR8_MESAD_BANK2 SYSCFG_UR8_MESAD_BANK2_Msk
18563/****************** Bit definition for SYSCFG_UR9 register *******************/
18564#define SYSCFG_UR9_WRPN_BANK2_Pos (0U)
18565#define SYSCFG_UR9_WRPN_BANK2_Msk (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)
18566#define SYSCFG_UR9_WRPN_BANK2 SYSCFG_UR9_WRPN_BANK2_Msk
18567#define SYSCFG_UR9_PABEG_BANK2_Pos (16U)
18568#define SYSCFG_UR9_PABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos)
18569#define SYSCFG_UR9_PABEG_BANK2 SYSCFG_UR9_PABEG_BANK2_Msk
18571/****************** Bit definition for SYSCFG_UR10 register *******************/
18572#define SYSCFG_UR10_PAEND_BANK2_Pos (0U)
18573#define SYSCFG_UR10_PAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos)
18574#define SYSCFG_UR10_PAEND_BANK2 SYSCFG_UR10_PAEND_BANK2_Msk
18575#define SYSCFG_UR10_SABEG_BANK2_Pos (16U)
18576#define SYSCFG_UR10_SABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos)
18577#define SYSCFG_UR10_SABEG_BANK2 SYSCFG_UR10_SABEG_BANK2_Msk
18579/****************** Bit definition for SYSCFG_UR11 register *******************/
18580#define SYSCFG_UR11_SAEND_BANK2_Pos (0U)
18581#define SYSCFG_UR11_SAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos)
18582#define SYSCFG_UR11_SAEND_BANK2 SYSCFG_UR11_SAEND_BANK2_Msk
18583#define SYSCFG_UR11_IWDG1M_Pos (16U)
18584#define SYSCFG_UR11_IWDG1M_Msk (0x1UL << SYSCFG_UR11_IWDG1M_Pos)
18585#define SYSCFG_UR11_IWDG1M SYSCFG_UR11_IWDG1M_Msk
18587/****************** Bit definition for SYSCFG_UR12 register *******************/
18588
18589#define SYSCFG_UR12_SECURE_Pos (16U)
18590#define SYSCFG_UR12_SECURE_Msk (0x1UL << SYSCFG_UR12_SECURE_Pos)
18591#define SYSCFG_UR12_SECURE SYSCFG_UR12_SECURE_Msk
18593/****************** Bit definition for SYSCFG_UR13 register *******************/
18594#define SYSCFG_UR13_SDRS_Pos (0U)
18595#define SYSCFG_UR13_SDRS_Msk (0x3UL << SYSCFG_UR13_SDRS_Pos)
18596#define SYSCFG_UR13_SDRS SYSCFG_UR13_SDRS_Msk
18597#define SYSCFG_UR13_D1SBRST_Pos (16U)
18598#define SYSCFG_UR13_D1SBRST_Msk (0x1UL << SYSCFG_UR13_D1SBRST_Pos)
18599#define SYSCFG_UR13_D1SBRST SYSCFG_UR13_D1SBRST_Msk
18601/****************** Bit definition for SYSCFG_UR14 register *******************/
18602#define SYSCFG_UR14_D1STPRST_Pos (0U)
18603#define SYSCFG_UR14_D1STPRST_Msk (0x1UL << SYSCFG_UR14_D1STPRST_Pos)
18604#define SYSCFG_UR14_D1STPRST SYSCFG_UR14_D1STPRST_Msk
18606/****************** Bit definition for SYSCFG_UR15 register *******************/
18607#define SYSCFG_UR15_FZIWDGSTB_Pos (16U)
18608#define SYSCFG_UR15_FZIWDGSTB_Msk (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)
18609#define SYSCFG_UR15_FZIWDGSTB SYSCFG_UR15_FZIWDGSTB_Msk
18611/****************** Bit definition for SYSCFG_UR16 register *******************/
18612#define SYSCFG_UR16_FZIWDGSTP_Pos (0U)
18613#define SYSCFG_UR16_FZIWDGSTP_Msk (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)
18614#define SYSCFG_UR16_FZIWDGSTP SYSCFG_UR16_FZIWDGSTP_Msk
18615#define SYSCFG_UR16_PKP_Pos (16U)
18616#define SYSCFG_UR16_PKP_Msk (0x1UL << SYSCFG_UR16_PKP_Pos)
18617#define SYSCFG_UR16_PKP SYSCFG_UR16_PKP_Msk
18619/****************** Bit definition for SYSCFG_UR17 register *******************/
18620#define SYSCFG_UR17_IOHSLV_Pos (0U)
18621#define SYSCFG_UR17_IOHSLV_Msk (0x1UL << SYSCFG_UR17_IOHSLV_Pos)
18622#define SYSCFG_UR17_IOHSLV SYSCFG_UR17_IOHSLV_Msk
18625/******************************************************************************/
18626/* */
18627/* TIM */
18628/* */
18629/******************************************************************************/
18630#define TIM_BREAK_INPUT_SUPPORT
18632/******************* Bit definition for TIM_CR1 register ********************/
18633#define TIM_CR1_CEN_Pos (0U)
18634#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)
18635#define TIM_CR1_CEN TIM_CR1_CEN_Msk
18636#define TIM_CR1_UDIS_Pos (1U)
18637#define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)
18638#define TIM_CR1_UDIS TIM_CR1_UDIS_Msk
18639#define TIM_CR1_URS_Pos (2U)
18640#define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)
18641#define TIM_CR1_URS TIM_CR1_URS_Msk
18642#define TIM_CR1_OPM_Pos (3U)
18643#define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)
18644#define TIM_CR1_OPM TIM_CR1_OPM_Msk
18645#define TIM_CR1_DIR_Pos (4U)
18646#define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)
18647#define TIM_CR1_DIR TIM_CR1_DIR_Msk
18649#define TIM_CR1_CMS_Pos (5U)
18650#define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)
18651#define TIM_CR1_CMS TIM_CR1_CMS_Msk
18652#define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)
18653#define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)
18655#define TIM_CR1_ARPE_Pos (7U)
18656#define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)
18657#define TIM_CR1_ARPE TIM_CR1_ARPE_Msk
18659#define TIM_CR1_CKD_Pos (8U)
18660#define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)
18661#define TIM_CR1_CKD TIM_CR1_CKD_Msk
18662#define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)
18663#define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)
18665#define TIM_CR1_UIFREMAP_Pos (11U)
18666#define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos)
18667#define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk
18669/******************* Bit definition for TIM_CR2 register ********************/
18670#define TIM_CR2_CCPC_Pos (0U)
18671#define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)
18672#define TIM_CR2_CCPC TIM_CR2_CCPC_Msk
18673#define TIM_CR2_CCUS_Pos (2U)
18674#define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)
18675#define TIM_CR2_CCUS TIM_CR2_CCUS_Msk
18676#define TIM_CR2_CCDS_Pos (3U)
18677#define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)
18678#define TIM_CR2_CCDS TIM_CR2_CCDS_Msk
18680#define TIM_CR2_MMS_Pos (4U)
18681#define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)
18682#define TIM_CR2_MMS TIM_CR2_MMS_Msk
18683#define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)
18684#define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)
18685#define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)
18687#define TIM_CR2_TI1S_Pos (7U)
18688#define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)
18689#define TIM_CR2_TI1S TIM_CR2_TI1S_Msk
18690#define TIM_CR2_OIS1_Pos (8U)
18691#define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)
18692#define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk
18693#define TIM_CR2_OIS1N_Pos (9U)
18694#define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)
18695#define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk
18696#define TIM_CR2_OIS2_Pos (10U)
18697#define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)
18698#define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk
18699#define TIM_CR2_OIS2N_Pos (11U)
18700#define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)
18701#define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk
18702#define TIM_CR2_OIS3_Pos (12U)
18703#define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)
18704#define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk
18705#define TIM_CR2_OIS3N_Pos (13U)
18706#define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)
18707#define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk
18708#define TIM_CR2_OIS4_Pos (14U)
18709#define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)
18710#define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk
18711#define TIM_CR2_OIS5_Pos (16U)
18712#define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos)
18713#define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk
18714#define TIM_CR2_OIS6_Pos (18U)
18715#define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos)
18716#define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk
18718#define TIM_CR2_MMS2_Pos (20U)
18719#define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos)
18720#define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk
18721#define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos)
18722#define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos)
18723#define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos)
18724#define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos)
18726/******************* Bit definition for TIM_SMCR register *******************/
18727#define TIM_SMCR_SMS_Pos (0U)
18728#define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos)
18729#define TIM_SMCR_SMS TIM_SMCR_SMS_Msk
18730#define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos)
18731#define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos)
18732#define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos)
18733#define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos)
18735#define TIM_SMCR_TS_Pos (4U)
18736#define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos)
18737#define TIM_SMCR_TS TIM_SMCR_TS_Msk
18738#define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos)
18739#define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos)
18740#define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos)
18741#define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos)
18742#define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos)
18744#define TIM_SMCR_MSM_Pos (7U)
18745#define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)
18746#define TIM_SMCR_MSM TIM_SMCR_MSM_Msk
18748#define TIM_SMCR_ETF_Pos (8U)
18749#define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)
18750#define TIM_SMCR_ETF TIM_SMCR_ETF_Msk
18751#define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)
18752#define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)
18753#define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)
18754#define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)
18756#define TIM_SMCR_ETPS_Pos (12U)
18757#define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)
18758#define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk
18759#define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)
18760#define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)
18762#define TIM_SMCR_ECE_Pos (14U)
18763#define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)
18764#define TIM_SMCR_ECE TIM_SMCR_ECE_Msk
18765#define TIM_SMCR_ETP_Pos (15U)
18766#define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)
18767#define TIM_SMCR_ETP TIM_SMCR_ETP_Msk
18769/******************* Bit definition for TIM_DIER register *******************/
18770#define TIM_DIER_UIE_Pos (0U)
18771#define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)
18772#define TIM_DIER_UIE TIM_DIER_UIE_Msk
18773#define TIM_DIER_CC1IE_Pos (1U)
18774#define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)
18775#define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk
18776#define TIM_DIER_CC2IE_Pos (2U)
18777#define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)
18778#define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk
18779#define TIM_DIER_CC3IE_Pos (3U)
18780#define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)
18781#define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk
18782#define TIM_DIER_CC4IE_Pos (4U)
18783#define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)
18784#define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk
18785#define TIM_DIER_COMIE_Pos (5U)
18786#define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)
18787#define TIM_DIER_COMIE TIM_DIER_COMIE_Msk
18788#define TIM_DIER_TIE_Pos (6U)
18789#define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)
18790#define TIM_DIER_TIE TIM_DIER_TIE_Msk
18791#define TIM_DIER_BIE_Pos (7U)
18792#define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)
18793#define TIM_DIER_BIE TIM_DIER_BIE_Msk
18794#define TIM_DIER_UDE_Pos (8U)
18795#define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)
18796#define TIM_DIER_UDE TIM_DIER_UDE_Msk
18797#define TIM_DIER_CC1DE_Pos (9U)
18798#define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)
18799#define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk
18800#define TIM_DIER_CC2DE_Pos (10U)
18801#define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)
18802#define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk
18803#define TIM_DIER_CC3DE_Pos (11U)
18804#define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)
18805#define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk
18806#define TIM_DIER_CC4DE_Pos (12U)
18807#define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)
18808#define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk
18809#define TIM_DIER_COMDE_Pos (13U)
18810#define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)
18811#define TIM_DIER_COMDE TIM_DIER_COMDE_Msk
18812#define TIM_DIER_TDE_Pos (14U)
18813#define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)
18814#define TIM_DIER_TDE TIM_DIER_TDE_Msk
18816/******************** Bit definition for TIM_SR register ********************/
18817#define TIM_SR_UIF_Pos (0U)
18818#define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)
18819#define TIM_SR_UIF TIM_SR_UIF_Msk
18820#define TIM_SR_CC1IF_Pos (1U)
18821#define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)
18822#define TIM_SR_CC1IF TIM_SR_CC1IF_Msk
18823#define TIM_SR_CC2IF_Pos (2U)
18824#define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)
18825#define TIM_SR_CC2IF TIM_SR_CC2IF_Msk
18826#define TIM_SR_CC3IF_Pos (3U)
18827#define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)
18828#define TIM_SR_CC3IF TIM_SR_CC3IF_Msk
18829#define TIM_SR_CC4IF_Pos (4U)
18830#define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)
18831#define TIM_SR_CC4IF TIM_SR_CC4IF_Msk
18832#define TIM_SR_COMIF_Pos (5U)
18833#define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)
18834#define TIM_SR_COMIF TIM_SR_COMIF_Msk
18835#define TIM_SR_TIF_Pos (6U)
18836#define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)
18837#define TIM_SR_TIF TIM_SR_TIF_Msk
18838#define TIM_SR_BIF_Pos (7U)
18839#define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)
18840#define TIM_SR_BIF TIM_SR_BIF_Msk
18841#define TIM_SR_B2IF_Pos (8U)
18842#define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos)
18843#define TIM_SR_B2IF TIM_SR_B2IF_Msk
18844#define TIM_SR_CC1OF_Pos (9U)
18845#define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)
18846#define TIM_SR_CC1OF TIM_SR_CC1OF_Msk
18847#define TIM_SR_CC2OF_Pos (10U)
18848#define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)
18849#define TIM_SR_CC2OF TIM_SR_CC2OF_Msk
18850#define TIM_SR_CC3OF_Pos (11U)
18851#define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)
18852#define TIM_SR_CC3OF TIM_SR_CC3OF_Msk
18853#define TIM_SR_CC4OF_Pos (12U)
18854#define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)
18855#define TIM_SR_CC4OF TIM_SR_CC4OF_Msk
18856#define TIM_SR_CC5IF_Pos (16U)
18857#define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos)
18858#define TIM_SR_CC5IF TIM_SR_CC5IF_Msk
18859#define TIM_SR_CC6IF_Pos (17U)
18860#define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos)
18861#define TIM_SR_CC6IF TIM_SR_CC6IF_Msk
18862#define TIM_SR_SBIF_Pos (13U)
18863#define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos)
18864#define TIM_SR_SBIF TIM_SR_SBIF_Msk
18866/******************* Bit definition for TIM_EGR register ********************/
18867#define TIM_EGR_UG_Pos (0U)
18868#define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)
18869#define TIM_EGR_UG TIM_EGR_UG_Msk
18870#define TIM_EGR_CC1G_Pos (1U)
18871#define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)
18872#define TIM_EGR_CC1G TIM_EGR_CC1G_Msk
18873#define TIM_EGR_CC2G_Pos (2U)
18874#define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)
18875#define TIM_EGR_CC2G TIM_EGR_CC2G_Msk
18876#define TIM_EGR_CC3G_Pos (3U)
18877#define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)
18878#define TIM_EGR_CC3G TIM_EGR_CC3G_Msk
18879#define TIM_EGR_CC4G_Pos (4U)
18880#define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)
18881#define TIM_EGR_CC4G TIM_EGR_CC4G_Msk
18882#define TIM_EGR_COMG_Pos (5U)
18883#define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)
18884#define TIM_EGR_COMG TIM_EGR_COMG_Msk
18885#define TIM_EGR_TG_Pos (6U)
18886#define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)
18887#define TIM_EGR_TG TIM_EGR_TG_Msk
18888#define TIM_EGR_BG_Pos (7U)
18889#define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)
18890#define TIM_EGR_BG TIM_EGR_BG_Msk
18891#define TIM_EGR_B2G_Pos (8U)
18892#define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos)
18893#define TIM_EGR_B2G TIM_EGR_B2G_Msk
18896/****************** Bit definition for TIM_CCMR1 register *******************/
18897#define TIM_CCMR1_CC1S_Pos (0U)
18898#define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)
18899#define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk
18900#define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)
18901#define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)
18903#define TIM_CCMR1_OC1FE_Pos (2U)
18904#define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)
18905#define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk
18906#define TIM_CCMR1_OC1PE_Pos (3U)
18907#define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)
18908#define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk
18910#define TIM_CCMR1_OC1M_Pos (4U)
18911#define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos)
18912#define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk
18913#define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos)
18914#define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos)
18915#define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos)
18916#define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos)
18918#define TIM_CCMR1_OC1CE_Pos (7U)
18919#define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)
18920#define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk
18922#define TIM_CCMR1_CC2S_Pos (8U)
18923#define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)
18924#define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk
18925#define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)
18926#define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)
18928#define TIM_CCMR1_OC2FE_Pos (10U)
18929#define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)
18930#define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk
18931#define TIM_CCMR1_OC2PE_Pos (11U)
18932#define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)
18933#define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk
18935#define TIM_CCMR1_OC2M_Pos (12U)
18936#define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos)
18937#define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk
18938#define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos)
18939#define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos)
18940#define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos)
18941#define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos)
18943#define TIM_CCMR1_OC2CE_Pos (15U)
18944#define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)
18945#define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk
18947/*----------------------------------------------------------------------------*/
18948
18949#define TIM_CCMR1_IC1PSC_Pos (2U)
18950#define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)
18951#define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk
18952#define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)
18953#define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)
18955#define TIM_CCMR1_IC1F_Pos (4U)
18956#define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)
18957#define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk
18958#define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)
18959#define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)
18960#define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)
18961#define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)
18963#define TIM_CCMR1_IC2PSC_Pos (10U)
18964#define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)
18965#define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk
18966#define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)
18967#define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)
18969#define TIM_CCMR1_IC2F_Pos (12U)
18970#define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)
18971#define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk
18972#define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)
18973#define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)
18974#define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)
18975#define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)
18977/****************** Bit definition for TIM_CCMR2 register *******************/
18978#define TIM_CCMR2_CC3S_Pos (0U)
18979#define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)
18980#define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk
18981#define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)
18982#define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)
18984#define TIM_CCMR2_OC3FE_Pos (2U)
18985#define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)
18986#define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk
18987#define TIM_CCMR2_OC3PE_Pos (3U)
18988#define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)
18989#define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk
18991#define TIM_CCMR2_OC3M_Pos (4U)
18992#define TIM_CCMR2_OC3M_Msk (0x1007UL << TIM_CCMR2_OC3M_Pos)
18993#define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk
18994#define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)
18995#define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)
18996#define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)
18997#define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos)
18999#define TIM_CCMR2_OC3CE_Pos (7U)
19000#define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)
19001#define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk
19003#define TIM_CCMR2_CC4S_Pos (8U)
19004#define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)
19005#define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk
19006#define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)
19007#define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)
19009#define TIM_CCMR2_OC4FE_Pos (10U)
19010#define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)
19011#define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk
19012#define TIM_CCMR2_OC4PE_Pos (11U)
19013#define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)
19014#define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk
19016#define TIM_CCMR2_OC4M_Pos (12U)
19017#define TIM_CCMR2_OC4M_Msk (0x1007UL << TIM_CCMR2_OC4M_Pos)
19018#define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk
19019#define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)
19020#define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)
19021#define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)
19022#define TIM_CCMR2_OC4M_3 (0x1000UL << TIM_CCMR2_OC4M_Pos)
19024#define TIM_CCMR2_OC4CE_Pos (15U)
19025#define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)
19026#define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk
19028/*----------------------------------------------------------------------------*/
19029
19030#define TIM_CCMR2_IC3PSC_Pos (2U)
19031#define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)
19032#define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk
19033#define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)
19034#define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)
19036#define TIM_CCMR2_IC3F_Pos (4U)
19037#define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)
19038#define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk
19039#define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)
19040#define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)
19041#define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)
19042#define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)
19044#define TIM_CCMR2_IC4PSC_Pos (10U)
19045#define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)
19046#define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk
19047#define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)
19048#define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)
19050#define TIM_CCMR2_IC4F_Pos (12U)
19051#define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)
19052#define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk
19053#define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)
19054#define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)
19055#define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)
19056#define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)
19058/******************* Bit definition for TIM_CCER register *******************/
19059#define TIM_CCER_CC1E_Pos (0U)
19060#define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)
19061#define TIM_CCER_CC1E TIM_CCER_CC1E_Msk
19062#define TIM_CCER_CC1P_Pos (1U)
19063#define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)
19064#define TIM_CCER_CC1P TIM_CCER_CC1P_Msk
19065#define TIM_CCER_CC1NE_Pos (2U)
19066#define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)
19067#define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk
19068#define TIM_CCER_CC1NP_Pos (3U)
19069#define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)
19070#define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk
19071#define TIM_CCER_CC2E_Pos (4U)
19072#define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)
19073#define TIM_CCER_CC2E TIM_CCER_CC2E_Msk
19074#define TIM_CCER_CC2P_Pos (5U)
19075#define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)
19076#define TIM_CCER_CC2P TIM_CCER_CC2P_Msk
19077#define TIM_CCER_CC2NE_Pos (6U)
19078#define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)
19079#define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk
19080#define TIM_CCER_CC2NP_Pos (7U)
19081#define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)
19082#define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk
19083#define TIM_CCER_CC3E_Pos (8U)
19084#define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)
19085#define TIM_CCER_CC3E TIM_CCER_CC3E_Msk
19086#define TIM_CCER_CC3P_Pos (9U)
19087#define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)
19088#define TIM_CCER_CC3P TIM_CCER_CC3P_Msk
19089#define TIM_CCER_CC3NE_Pos (10U)
19090#define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)
19091#define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk
19092#define TIM_CCER_CC3NP_Pos (11U)
19093#define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)
19094#define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk
19095#define TIM_CCER_CC4E_Pos (12U)
19096#define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)
19097#define TIM_CCER_CC4E TIM_CCER_CC4E_Msk
19098#define TIM_CCER_CC4P_Pos (13U)
19099#define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)
19100#define TIM_CCER_CC4P TIM_CCER_CC4P_Msk
19101#define TIM_CCER_CC4NP_Pos (15U)
19102#define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos)
19103#define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk
19104#define TIM_CCER_CC5E_Pos (16U)
19105#define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos)
19106#define TIM_CCER_CC5E TIM_CCER_CC5E_Msk
19107#define TIM_CCER_CC5P_Pos (17U)
19108#define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos)
19109#define TIM_CCER_CC5P TIM_CCER_CC5P_Msk
19110#define TIM_CCER_CC6E_Pos (20U)
19111#define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos)
19112#define TIM_CCER_CC6E TIM_CCER_CC6E_Msk
19113#define TIM_CCER_CC6P_Pos (21U)
19114#define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos)
19115#define TIM_CCER_CC6P TIM_CCER_CC6P_Msk
19116/******************* Bit definition for TIM_CNT register ********************/
19117#define TIM_CNT_CNT_Pos (0U)
19118#define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)
19119#define TIM_CNT_CNT TIM_CNT_CNT_Msk
19120#define TIM_CNT_UIFCPY_Pos (31U)
19121#define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos)
19122#define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk
19123/******************* Bit definition for TIM_PSC register ********************/
19124#define TIM_PSC_PSC_Pos (0U)
19125#define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)
19126#define TIM_PSC_PSC TIM_PSC_PSC_Msk
19128/******************* Bit definition for TIM_ARR register ********************/
19129#define TIM_ARR_ARR_Pos (0U)
19130#define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)
19131#define TIM_ARR_ARR TIM_ARR_ARR_Msk
19133/******************* Bit definition for TIM_RCR register ********************/
19134#define TIM_RCR_REP_Pos (0U)
19135#define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)
19136#define TIM_RCR_REP TIM_RCR_REP_Msk
19138/******************* Bit definition for TIM_CCR1 register *******************/
19139#define TIM_CCR1_CCR1_Pos (0U)
19140#define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)
19141#define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk
19143/******************* Bit definition for TIM_CCR2 register *******************/
19144#define TIM_CCR2_CCR2_Pos (0U)
19145#define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)
19146#define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk
19148/******************* Bit definition for TIM_CCR3 register *******************/
19149#define TIM_CCR3_CCR3_Pos (0U)
19150#define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)
19151#define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk
19153/******************* Bit definition for TIM_CCR4 register *******************/
19154#define TIM_CCR4_CCR4_Pos (0U)
19155#define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)
19156#define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk
19158/******************* Bit definition for TIM_CCR5 register *******************/
19159#define TIM_CCR5_CCR5_Pos (0U)
19160#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)
19161#define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk
19162#define TIM_CCR5_GC5C1_Pos (29U)
19163#define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos)
19164#define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk
19165#define TIM_CCR5_GC5C2_Pos (30U)
19166#define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos)
19167#define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk
19168#define TIM_CCR5_GC5C3_Pos (31U)
19169#define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos)
19170#define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk
19172/******************* Bit definition for TIM_CCR6 register *******************/
19173#define TIM_CCR6_CCR6_Pos (0U)
19174#define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos)
19175#define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk
19177/******************* Bit definition for TIM_BDTR register *******************/
19178#define TIM_BDTR_DTG_Pos (0U)
19179#define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)
19180#define TIM_BDTR_DTG TIM_BDTR_DTG_Msk
19181#define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)
19182#define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)
19183#define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)
19184#define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)
19185#define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)
19186#define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)
19187#define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)
19188#define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)
19190#define TIM_BDTR_LOCK_Pos (8U)
19191#define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)
19192#define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk
19193#define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)
19194#define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)
19196#define TIM_BDTR_OSSI_Pos (10U)
19197#define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)
19198#define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk
19199#define TIM_BDTR_OSSR_Pos (11U)
19200#define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)
19201#define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk
19202#define TIM_BDTR_BKE_Pos (12U)
19203#define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)
19204#define TIM_BDTR_BKE TIM_BDTR_BKE_Msk
19205#define TIM_BDTR_BKP_Pos (13U)
19206#define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)
19207#define TIM_BDTR_BKP TIM_BDTR_BKP_Msk
19208#define TIM_BDTR_AOE_Pos (14U)
19209#define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)
19210#define TIM_BDTR_AOE TIM_BDTR_AOE_Msk
19211#define TIM_BDTR_MOE_Pos (15U)
19212#define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)
19213#define TIM_BDTR_MOE TIM_BDTR_MOE_Msk
19215#define TIM_BDTR_BKF_Pos (16U)
19216#define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos)
19217#define TIM_BDTR_BKF TIM_BDTR_BKF_Msk
19218#define TIM_BDTR_BK2F_Pos (20U)
19219#define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos)
19220#define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk
19222#define TIM_BDTR_BK2E_Pos (24U)
19223#define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos)
19224#define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk
19225#define TIM_BDTR_BK2P_Pos (25U)
19226#define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos)
19227#define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk
19229/******************* Bit definition for TIM_DCR register ********************/
19230#define TIM_DCR_DBA_Pos (0U)
19231#define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)
19232#define TIM_DCR_DBA TIM_DCR_DBA_Msk
19233#define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)
19234#define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)
19235#define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)
19236#define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)
19237#define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)
19239#define TIM_DCR_DBL_Pos (8U)
19240#define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)
19241#define TIM_DCR_DBL TIM_DCR_DBL_Msk
19242#define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)
19243#define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)
19244#define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)
19245#define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)
19246#define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)
19248/******************* Bit definition for TIM_DMAR register *******************/
19249#define TIM_DMAR_DMAB_Pos (0U)
19250#define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)
19251#define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk
19253/****************** Bit definition for TIM_CCMR3 register *******************/
19254#define TIM_CCMR3_OC5FE_Pos (2U)
19255#define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos)
19256#define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk
19257#define TIM_CCMR3_OC5PE_Pos (3U)
19258#define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos)
19259#define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk
19261#define TIM_CCMR3_OC5M_Pos (4U)
19262#define TIM_CCMR3_OC5M_Msk (0x1007UL << TIM_CCMR3_OC5M_Pos)
19263#define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk
19264#define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos)
19265#define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos)
19266#define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos)
19267#define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos)
19269#define TIM_CCMR3_OC5CE_Pos (7U)
19270#define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos)
19271#define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk
19273#define TIM_CCMR3_OC6FE_Pos (10U)
19274#define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos)
19275#define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk
19276#define TIM_CCMR3_OC6PE_Pos (11U)
19277#define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos)
19278#define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk
19280#define TIM_CCMR3_OC6M_Pos (12U)
19281#define TIM_CCMR3_OC6M_Msk (0x1007UL << TIM_CCMR3_OC6M_Pos)
19282#define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk
19283#define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos)
19284#define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos)
19285#define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos)
19286#define TIM_CCMR3_OC6M_3 (0x1000UL << TIM_CCMR3_OC6M_Pos)
19288#define TIM_CCMR3_OC6CE_Pos (15U)
19289#define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos)
19290#define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk
19291/******************* Bit definition for TIM1_AF1 register *********************/
19292#define TIM1_AF1_BKINE_Pos (0U)
19293#define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos)
19294#define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk
19295#define TIM1_AF1_BKCMP1E_Pos (1U)
19296#define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos)
19297#define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk
19298#define TIM1_AF1_BKCMP2E_Pos (2U)
19299#define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos)
19300#define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk
19301#define TIM1_AF1_BKDF1BK0E_Pos (8U)
19302#define TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)
19303#define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk
19304#define TIM1_AF1_BKINP_Pos (9U)
19305#define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos)
19306#define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk
19307#define TIM1_AF1_BKCMP1P_Pos (10U)
19308#define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos)
19309#define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk
19310#define TIM1_AF1_BKCMP2P_Pos (11U)
19311#define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos)
19312#define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk
19314#define TIM1_AF1_ETRSEL_Pos (14U)
19315#define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos)
19316#define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk
19317#define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos)
19318#define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos)
19319#define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos)
19320#define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos)
19322/******************* Bit definition for TIM1_AF2 register *********************/
19323#define TIM1_AF2_BK2INE_Pos (0U)
19324#define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos)
19325#define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk
19326#define TIM1_AF2_BK2CMP1E_Pos (1U)
19327#define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos)
19328#define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk
19329#define TIM1_AF2_BK2CMP2E_Pos (2U)
19330#define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos)
19331#define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk
19332#define TIM1_AF2_BK2DFBK1E_Pos (8U)
19333#define TIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)
19334#define TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk
19335#define TIM1_AF2_BK2INP_Pos (9U)
19336#define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos)
19337#define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk
19338#define TIM1_AF2_BK2CMP1P_Pos (10U)
19339#define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos)
19340#define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk
19341#define TIM1_AF2_BK2CMP2P_Pos (11U)
19342#define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos)
19343#define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk
19345/******************* Bit definition for TIM_TISEL register *********************/
19346#define TIM_TISEL_TI1SEL_Pos (0U)
19347#define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos)
19348#define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk
19349#define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos)
19350#define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos)
19351#define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos)
19352#define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos)
19354#define TIM_TISEL_TI2SEL_Pos (8U)
19355#define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos)
19356#define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk
19357#define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos)
19358#define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos)
19359#define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos)
19360#define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos)
19362#define TIM_TISEL_TI3SEL_Pos (16U)
19363#define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos)
19364#define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk
19365#define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos)
19366#define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos)
19367#define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos)
19368#define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos)
19370#define TIM_TISEL_TI4SEL_Pos (24U)
19371#define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos)
19372#define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk
19373#define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos)
19374#define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos)
19375#define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos)
19376#define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos)
19378/******************* Bit definition for TIM8_AF1 register *********************/
19379#define TIM8_AF1_BKINE_Pos (0U)
19380#define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos)
19381#define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk
19382#define TIM8_AF1_BKCMP1E_Pos (1U)
19383#define TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos)
19384#define TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk
19385#define TIM8_AF1_BKCMP2E_Pos (2U)
19386#define TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos)
19387#define TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk
19388#define TIM8_AF1_BKDFBK2E_Pos (8U)
19389#define TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos)
19390#define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk
19391#define TIM8_AF1_BKINP_Pos (9U)
19392#define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos)
19393#define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk
19394#define TIM8_AF1_BKCMP1P_Pos (10U)
19395#define TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos)
19396#define TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk
19397#define TIM8_AF1_BKCMP2P_Pos (11U)
19398#define TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos)
19399#define TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk
19401#define TIM8_AF1_ETRSEL_Pos (14U)
19402#define TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos)
19403#define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk
19404#define TIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos)
19405#define TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos)
19406#define TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos)
19407#define TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos)
19408/******************* Bit definition for TIM8_AF2 register *********************/
19409#define TIM8_AF2_BK2INE_Pos (0U)
19410#define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos)
19411#define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk
19412#define TIM8_AF2_BK2CMP1E_Pos (1U)
19413#define TIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos)
19414#define TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk
19415#define TIM8_AF2_BK2CMP2E_Pos (2U)
19416#define TIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos)
19417#define TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk
19418#define TIM8_AF2_BK2DFBK3E_Pos (8U)
19419#define TIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)
19420#define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk
19421#define TIM8_AF2_BK2INP_Pos (9U)
19422#define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos)
19423#define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk
19424#define TIM8_AF2_BK2CMP1P_Pos (10U)
19425#define TIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos)
19426#define TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk
19427#define TIM8_AF2_BK2CMP2P_Pos (11U)
19428#define TIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos)
19429#define TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk
19431/******************* Bit definition for TIM2_AF1 register *********************/
19432#define TIM2_AF1_ETRSEL_Pos (14U)
19433#define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos)
19434#define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk
19435#define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos)
19436#define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos)
19437#define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos)
19438#define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos)
19440/******************* Bit definition for TIM3_AF1 register *********************/
19441#define TIM3_AF1_ETRSEL_Pos (14U)
19442#define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos)
19443#define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk
19444#define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos)
19445#define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos)
19446#define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos)
19447#define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos)
19449/******************* Bit definition for TIM5_AF1 register *********************/
19450#define TIM5_AF1_ETRSEL_Pos (14U)
19451#define TIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos)
19452#define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk
19453#define TIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos)
19454#define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos)
19455#define TIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos)
19456#define TIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos)
19458/******************* Bit definition for TIM15_AF1 register *********************/
19459#define TIM15_AF1_BKINE_Pos (0U)
19460#define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos)
19461#define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk
19462#define TIM15_AF1_BKCMP1E_Pos (1U)
19463#define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos)
19464#define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk
19465#define TIM15_AF1_BKCMP2E_Pos (2U)
19466#define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos)
19467#define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk
19468#define TIM15_AF1_BKDF1BK2E_Pos (8U)
19469#define TIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)
19470#define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk
19471#define TIM15_AF1_BKINP_Pos (9U)
19472#define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos)
19473#define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk
19474#define TIM15_AF1_BKCMP1P_Pos (10U)
19475#define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos)
19476#define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk
19477#define TIM15_AF1_BKCMP2P_Pos (11U)
19478#define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos)
19479#define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk
19481/******************* Bit definition for TIM16_ register *********************/
19482#define TIM16_AF1_BKINE_Pos (0U)
19483#define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos)
19484#define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk
19485#define TIM16_AF1_BKCMP1E_Pos (1U)
19486#define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos)
19487#define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk
19488#define TIM16_AF1_BKCMP2E_Pos (2U)
19489#define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos)
19490#define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk
19491#define TIM16_AF1_BKDF1BK2E_Pos (8U)
19492#define TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)
19493#define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk
19494#define TIM16_AF1_BKINP_Pos (9U)
19495#define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos)
19496#define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk
19497#define TIM16_AF1_BKCMP1P_Pos (10U)
19498#define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos)
19499#define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk
19500#define TIM16_AF1_BKCMP2P_Pos (11U)
19501#define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos)
19502#define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk
19504/******************* Bit definition for TIM17_AF1 register *********************/
19505#define TIM17_AF1_BKINE_Pos (0U)
19506#define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos)
19507#define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk
19508#define TIM17_AF1_BKCMP1E_Pos (1U)
19509#define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos)
19510#define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk
19511#define TIM17_AF1_BKCMP2E_Pos (2U)
19512#define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos)
19513#define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk
19514#define TIM17_AF1_BKDF1BK2E_Pos (8U)
19515#define TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)
19516#define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk
19517#define TIM17_AF1_BKINP_Pos (9U)
19518#define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos)
19519#define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk
19520#define TIM17_AF1_BKCMP1P_Pos (10U)
19521#define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos)
19522#define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk
19523#define TIM17_AF1_BKCMP2P_Pos (11U)
19524#define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos)
19525#define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk
19527/******************************************************************************/
19528/* */
19529/* Low Power Timer (LPTTIM) */
19530/* */
19531/******************************************************************************/
19532/****************** Bit definition for LPTIM_ISR register *******************/
19533#define LPTIM_ISR_CMPM_Pos (0U)
19534#define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos)
19535#define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk
19536#define LPTIM_ISR_ARRM_Pos (1U)
19537#define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos)
19538#define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk
19539#define LPTIM_ISR_EXTTRIG_Pos (2U)
19540#define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos)
19541#define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk
19542#define LPTIM_ISR_CMPOK_Pos (3U)
19543#define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos)
19544#define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk
19545#define LPTIM_ISR_ARROK_Pos (4U)
19546#define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos)
19547#define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk
19548#define LPTIM_ISR_UP_Pos (5U)
19549#define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos)
19550#define LPTIM_ISR_UP LPTIM_ISR_UP_Msk
19551#define LPTIM_ISR_DOWN_Pos (6U)
19552#define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos)
19553#define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk
19555/****************** Bit definition for LPTIM_ICR register *******************/
19556#define LPTIM_ICR_CMPMCF_Pos (0U)
19557#define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos)
19558#define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk
19559#define LPTIM_ICR_ARRMCF_Pos (1U)
19560#define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos)
19561#define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk
19562#define LPTIM_ICR_EXTTRIGCF_Pos (2U)
19563#define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)
19564#define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk
19565#define LPTIM_ICR_CMPOKCF_Pos (3U)
19566#define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos)
19567#define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk
19568#define LPTIM_ICR_ARROKCF_Pos (4U)
19569#define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos)
19570#define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk
19571#define LPTIM_ICR_UPCF_Pos (5U)
19572#define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos)
19573#define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk
19574#define LPTIM_ICR_DOWNCF_Pos (6U)
19575#define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos)
19576#define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk
19578/****************** Bit definition for LPTIM_IER register ********************/
19579#define LPTIM_IER_CMPMIE_Pos (0U)
19580#define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos)
19581#define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk
19582#define LPTIM_IER_ARRMIE_Pos (1U)
19583#define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos)
19584#define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk
19585#define LPTIM_IER_EXTTRIGIE_Pos (2U)
19586#define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)
19587#define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk
19588#define LPTIM_IER_CMPOKIE_Pos (3U)
19589#define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos)
19590#define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk
19591#define LPTIM_IER_ARROKIE_Pos (4U)
19592#define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos)
19593#define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk
19594#define LPTIM_IER_UPIE_Pos (5U)
19595#define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos)
19596#define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk
19597#define LPTIM_IER_DOWNIE_Pos (6U)
19598#define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos)
19599#define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk
19601/****************** Bit definition for LPTIM_CFGR register *******************/
19602#define LPTIM_CFGR_CKSEL_Pos (0U)
19603#define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos)
19604#define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk
19606#define LPTIM_CFGR_CKPOL_Pos (1U)
19607#define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos)
19608#define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk
19609#define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos)
19610#define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos)
19612#define LPTIM_CFGR_CKFLT_Pos (3U)
19613#define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos)
19614#define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk
19615#define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos)
19616#define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos)
19618#define LPTIM_CFGR_TRGFLT_Pos (6U)
19619#define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos)
19620#define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk
19621#define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos)
19622#define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos)
19624#define LPTIM_CFGR_PRESC_Pos (9U)
19625#define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos)
19626#define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk
19627#define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos)
19628#define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos)
19629#define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos)
19631#define LPTIM_CFGR_TRIGSEL_Pos (13U)
19632#define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)
19633#define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk
19634#define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)
19635#define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)
19636#define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)
19638#define LPTIM_CFGR_TRIGEN_Pos (17U)
19639#define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos)
19640#define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk
19641#define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos)
19642#define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos)
19644#define LPTIM_CFGR_TIMOUT_Pos (19U)
19645#define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos)
19646#define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk
19647#define LPTIM_CFGR_WAVE_Pos (20U)
19648#define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos)
19649#define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk
19650#define LPTIM_CFGR_WAVPOL_Pos (21U)
19651#define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos)
19652#define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk
19653#define LPTIM_CFGR_PRELOAD_Pos (22U)
19654#define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos)
19655#define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk
19656#define LPTIM_CFGR_COUNTMODE_Pos (23U)
19657#define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)
19658#define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk
19659#define LPTIM_CFGR_ENC_Pos (24U)
19660#define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos)
19661#define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk
19663/****************** Bit definition for LPTIM_CR register ********************/
19664#define LPTIM_CR_ENABLE_Pos (0U)
19665#define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos)
19666#define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk
19667#define LPTIM_CR_SNGSTRT_Pos (1U)
19668#define LPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos)
19669#define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk
19670#define LPTIM_CR_CNTSTRT_Pos (2U)
19671#define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos)
19672#define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk
19673#define LPTIM_CR_COUNTRST_Pos (3U)
19674#define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos)
19675#define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk
19676#define LPTIM_CR_RSTARE_Pos (4U)
19677#define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos)
19678#define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk
19681/****************** Bit definition for LPTIM_CMP register *******************/
19682#define LPTIM_CMP_CMP_Pos (0U)
19683#define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos)
19684#define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk
19686/****************** Bit definition for LPTIM_ARR register *******************/
19687#define LPTIM_ARR_ARR_Pos (0U)
19688#define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos)
19689#define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk
19691/****************** Bit definition for LPTIM_CNT register *******************/
19692#define LPTIM_CNT_CNT_Pos (0U)
19693#define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos)
19694#define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk
19696/****************** Bit definition for LPTIM_CFGR2 register *****************/
19697#define LPTIM_CFGR2_IN1SEL_Pos (0U)
19698#define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)
19699#define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk
19700#define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)
19701#define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)
19702#define LPTIM_CFGR2_IN2SEL_Pos (4U)
19703#define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)
19704#define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk
19705#define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)
19706#define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)
19708/******************************************************************************/
19709/* */
19710/* Analog Comparators (COMP) */
19711/* */
19712/******************************************************************************/
19713
19714/******************* Bit definition for COMP_SR register ********************/
19715#define COMP_SR_C1VAL_Pos (0U)
19716#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos)
19717#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
19718#define COMP_SR_C2VAL_Pos (1U)
19719#define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos)
19720#define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
19721#define COMP_SR_C1IF_Pos (16U)
19722#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos)
19723#define COMP_SR_C1IF COMP_SR_C1IF_Msk
19724#define COMP_SR_C2IF_Pos (17U)
19725#define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos)
19726#define COMP_SR_C2IF COMP_SR_C2IF_Msk
19727/******************* Bit definition for COMP_ICFR register ********************/
19728#define COMP_ICFR_C1IF_Pos (16U)
19729#define COMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos)
19730#define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
19731#define COMP_ICFR_C2IF_Pos (17U)
19732#define COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos)
19733#define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
19734/******************* Bit definition for COMP_OR register ********************/
19735#define COMP_OR_AFOPA6_Pos (0U)
19736#define COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos)
19737#define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
19738#define COMP_OR_AFOPA8_Pos (1U)
19739#define COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos)
19740#define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
19741#define COMP_OR_AFOPB12_Pos (2U)
19742#define COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos)
19743#define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
19744#define COMP_OR_AFOPE6_Pos (3U)
19745#define COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos)
19746#define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
19747#define COMP_OR_AFOPE15_Pos (4U)
19748#define COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos)
19749#define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
19750#define COMP_OR_AFOPG2_Pos (5U)
19751#define COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos)
19752#define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
19753#define COMP_OR_AFOPG3_Pos (6U)
19754#define COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos)
19755#define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
19756#define COMP_OR_AFOPG4_Pos (7U)
19757#define COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos)
19758#define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
19759#define COMP_OR_AFOPI1_Pos (8U)
19760#define COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos)
19761#define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
19762#define COMP_OR_AFOPI4_Pos (9U)
19763#define COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos)
19764#define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
19765#define COMP_OR_AFOPK2_Pos (10U)
19766#define COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos)
19767#define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
19768
19770#define COMP_CFGRx_EN_Pos (0U)
19771#define COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos)
19772#define COMP_CFGRx_EN COMP_CFGRx_EN_Msk
19773#define COMP_CFGRx_BRGEN_Pos (1U)
19774#define COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos)
19775#define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk
19776#define COMP_CFGRx_SCALEN_Pos (2U)
19777#define COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos)
19778#define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk
19779#define COMP_CFGRx_POLARITY_Pos (3U)
19780#define COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos)
19781#define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk
19782#define COMP_CFGRx_WINMODE_Pos (4U)
19783#define COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos)
19784#define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk
19785#define COMP_CFGRx_ITEN_Pos (6U)
19786#define COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos)
19787#define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk
19788#define COMP_CFGRx_HYST_Pos (8U)
19789#define COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos)
19790#define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk
19791#define COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos)
19792#define COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos)
19793#define COMP_CFGRx_PWRMODE_Pos (12U)
19794#define COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos)
19795#define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk
19796#define COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos)
19797#define COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos)
19798#define COMP_CFGRx_INMSEL_Pos (16U)
19799#define COMP_CFGRx_INMSEL_Msk (0x7UL << COMP_CFGRx_INMSEL_Pos)
19800#define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk
19801#define COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos)
19802#define COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos)
19803#define COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos)
19804#define COMP_CFGRx_INPSEL_Pos (20U)
19805#define COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos)
19806#define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk
19807#define COMP_CFGRx_BLANKING_Pos (24U)
19808#define COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos)
19809#define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk
19810#define COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos)
19811#define COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos)
19812#define COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos)
19813#define COMP_CFGRx_LOCK_Pos (31U)
19814#define COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos)
19815#define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk
19818/******************************************************************************/
19819/* */
19820/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
19821/* */
19822/******************************************************************************/
19823/****************** Bit definition for USART_CR1 register *******************/
19824#define USART_CR1_UE_Pos (0U)
19825#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)
19826#define USART_CR1_UE USART_CR1_UE_Msk
19827#define USART_CR1_UESM_Pos (1U)
19828#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos)
19829#define USART_CR1_UESM USART_CR1_UESM_Msk
19830#define USART_CR1_RE_Pos (2U)
19831#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)
19832#define USART_CR1_RE USART_CR1_RE_Msk
19833#define USART_CR1_TE_Pos (3U)
19834#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)
19835#define USART_CR1_TE USART_CR1_TE_Msk
19836#define USART_CR1_IDLEIE_Pos (4U)
19837#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)
19838#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk
19839#define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
19840#define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos)
19841#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk
19842#define USART_CR1_TCIE_Pos (6U)
19843#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)
19844#define USART_CR1_TCIE USART_CR1_TCIE_Msk
19845#define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
19846#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos)
19847#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk
19848#define USART_CR1_PEIE_Pos (8U)
19849#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)
19850#define USART_CR1_PEIE USART_CR1_PEIE_Msk
19851#define USART_CR1_PS_Pos (9U)
19852#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)
19853#define USART_CR1_PS USART_CR1_PS_Msk
19854#define USART_CR1_PCE_Pos (10U)
19855#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)
19856#define USART_CR1_PCE USART_CR1_PCE_Msk
19857#define USART_CR1_WAKE_Pos (11U)
19858#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)
19859#define USART_CR1_WAKE USART_CR1_WAKE_Msk
19860#define USART_CR1_M_Pos (12U)
19861#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos)
19862#define USART_CR1_M USART_CR1_M_Msk
19863#define USART_CR1_M0_Pos (12U)
19864#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos)
19865#define USART_CR1_M0 USART_CR1_M0_Msk
19866#define USART_CR1_MME_Pos (13U)
19867#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos)
19868#define USART_CR1_MME USART_CR1_MME_Msk
19869#define USART_CR1_CMIE_Pos (14U)
19870#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos)
19871#define USART_CR1_CMIE USART_CR1_CMIE_Msk
19872#define USART_CR1_OVER8_Pos (15U)
19873#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos)
19874#define USART_CR1_OVER8 USART_CR1_OVER8_Msk
19875#define USART_CR1_DEDT_Pos (16U)
19876#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos)
19877#define USART_CR1_DEDT USART_CR1_DEDT_Msk
19878#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos)
19879#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos)
19880#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos)
19881#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos)
19882#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos)
19883#define USART_CR1_DEAT_Pos (21U)
19884#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos)
19885#define USART_CR1_DEAT USART_CR1_DEAT_Msk
19886#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos)
19887#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos)
19888#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos)
19889#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos)
19890#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos)
19891#define USART_CR1_RTOIE_Pos (26U)
19892#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos)
19893#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk
19894#define USART_CR1_EOBIE_Pos (27U)
19895#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos)
19896#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk
19897#define USART_CR1_M1_Pos (28U)
19898#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos)
19899#define USART_CR1_M1 USART_CR1_M1_Msk
19900#define USART_CR1_FIFOEN_Pos (29U)
19901#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos)
19902#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk
19903#define USART_CR1_TXFEIE_Pos (30U)
19904#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos)
19905#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk
19906#define USART_CR1_RXFFIE_Pos (31U)
19907#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos)
19908#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk
19910/* Legacy define */
19911#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
19912#define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
19913
19914/****************** Bit definition for USART_CR2 register *******************/
19915#define USART_CR2_SLVEN_Pos (0U)
19916#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos)
19917#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk
19918#define USART_CR2_DIS_NSS_Pos (3U)
19919#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos)
19920#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk
19921#define USART_CR2_ADDM7_Pos (4U)
19922#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos)
19923#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk
19924#define USART_CR2_LBDL_Pos (5U)
19925#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)
19926#define USART_CR2_LBDL USART_CR2_LBDL_Msk
19927#define USART_CR2_LBDIE_Pos (6U)
19928#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)
19929#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk
19930#define USART_CR2_LBCL_Pos (8U)
19931#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)
19932#define USART_CR2_LBCL USART_CR2_LBCL_Msk
19933#define USART_CR2_CPHA_Pos (9U)
19934#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)
19935#define USART_CR2_CPHA USART_CR2_CPHA_Msk
19936#define USART_CR2_CPOL_Pos (10U)
19937#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)
19938#define USART_CR2_CPOL USART_CR2_CPOL_Msk
19939#define USART_CR2_CLKEN_Pos (11U)
19940#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)
19941#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk
19942#define USART_CR2_STOP_Pos (12U)
19943#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)
19944#define USART_CR2_STOP USART_CR2_STOP_Msk
19945#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)
19946#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)
19947#define USART_CR2_LINEN_Pos (14U)
19948#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)
19949#define USART_CR2_LINEN USART_CR2_LINEN_Msk
19950#define USART_CR2_SWAP_Pos (15U)
19951#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos)
19952#define USART_CR2_SWAP USART_CR2_SWAP_Msk
19953#define USART_CR2_RXINV_Pos (16U)
19954#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos)
19955#define USART_CR2_RXINV USART_CR2_RXINV_Msk
19956#define USART_CR2_TXINV_Pos (17U)
19957#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos)
19958#define USART_CR2_TXINV USART_CR2_TXINV_Msk
19959#define USART_CR2_DATAINV_Pos (18U)
19960#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos)
19961#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk
19962#define USART_CR2_MSBFIRST_Pos (19U)
19963#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos)
19964#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk
19965#define USART_CR2_ABREN_Pos (20U)
19966#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos)
19967#define USART_CR2_ABREN USART_CR2_ABREN_Msk
19968#define USART_CR2_ABRMODE_Pos (21U)
19969#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos)
19970#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk
19971#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos)
19972#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos)
19973#define USART_CR2_RTOEN_Pos (23U)
19974#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos)
19975#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk
19976#define USART_CR2_ADD_Pos (24U)
19977#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos)
19978#define USART_CR2_ADD USART_CR2_ADD_Msk
19980/****************** Bit definition for USART_CR3 register *******************/
19981#define USART_CR3_EIE_Pos (0U)
19982#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)
19983#define USART_CR3_EIE USART_CR3_EIE_Msk
19984#define USART_CR3_IREN_Pos (1U)
19985#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)
19986#define USART_CR3_IREN USART_CR3_IREN_Msk
19987#define USART_CR3_IRLP_Pos (2U)
19988#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)
19989#define USART_CR3_IRLP USART_CR3_IRLP_Msk
19990#define USART_CR3_HDSEL_Pos (3U)
19991#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)
19992#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk
19993#define USART_CR3_NACK_Pos (4U)
19994#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)
19995#define USART_CR3_NACK USART_CR3_NACK_Msk
19996#define USART_CR3_SCEN_Pos (5U)
19997#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)
19998#define USART_CR3_SCEN USART_CR3_SCEN_Msk
19999#define USART_CR3_DMAR_Pos (6U)
20000#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)
20001#define USART_CR3_DMAR USART_CR3_DMAR_Msk
20002#define USART_CR3_DMAT_Pos (7U)
20003#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)
20004#define USART_CR3_DMAT USART_CR3_DMAT_Msk
20005#define USART_CR3_RTSE_Pos (8U)
20006#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)
20007#define USART_CR3_RTSE USART_CR3_RTSE_Msk
20008#define USART_CR3_CTSE_Pos (9U)
20009#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)
20010#define USART_CR3_CTSE USART_CR3_CTSE_Msk
20011#define USART_CR3_CTSIE_Pos (10U)
20012#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)
20013#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk
20014#define USART_CR3_ONEBIT_Pos (11U)
20015#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos)
20016#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk
20017#define USART_CR3_OVRDIS_Pos (12U)
20018#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos)
20019#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk
20020#define USART_CR3_DDRE_Pos (13U)
20021#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos)
20022#define USART_CR3_DDRE USART_CR3_DDRE_Msk
20023#define USART_CR3_DEM_Pos (14U)
20024#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos)
20025#define USART_CR3_DEM USART_CR3_DEM_Msk
20026#define USART_CR3_DEP_Pos (15U)
20027#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos)
20028#define USART_CR3_DEP USART_CR3_DEP_Msk
20029#define USART_CR3_SCARCNT_Pos (17U)
20030#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos)
20031#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk
20032#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos)
20033#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos)
20034#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos)
20035#define USART_CR3_WUS_Pos (20U)
20036#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos)
20037#define USART_CR3_WUS USART_CR3_WUS_Msk
20038#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos)
20039#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos)
20040#define USART_CR3_WUFIE_Pos (22U)
20041#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos)
20042#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk
20043#define USART_CR3_TXFTIE_Pos (23U)
20044#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos)
20045#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk
20046#define USART_CR3_TCBGTIE_Pos (24U)
20047#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos)
20048#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk
20049#define USART_CR3_RXFTCFG_Pos (25U)
20050#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos)
20051#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk
20052#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos)
20053#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos)
20054#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos)
20055#define USART_CR3_RXFTIE_Pos (28U)
20056#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos)
20057#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk
20058#define USART_CR3_TXFTCFG_Pos (29U)
20059#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos)
20060#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk
20061#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos)
20062#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos)
20063#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos)
20065/****************** Bit definition for USART_BRR register *******************/
20066#define USART_BRR_DIV_FRACTION_Pos (0U)
20067#define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos)
20068#define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk
20069#define USART_BRR_DIV_MANTISSA_Pos (4U)
20070#define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos)
20071#define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk
20073/****************** Bit definition for USART_GTPR register ******************/
20074#define USART_GTPR_PSC_Pos (0U)
20075#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)
20076#define USART_GTPR_PSC USART_GTPR_PSC_Msk
20077#define USART_GTPR_GT_Pos (8U)
20078#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)
20079#define USART_GTPR_GT USART_GTPR_GT_Msk
20081/******************* Bit definition for USART_RTOR register *****************/
20082#define USART_RTOR_RTO_Pos (0U)
20083#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos)
20084#define USART_RTOR_RTO USART_RTOR_RTO_Msk
20085#define USART_RTOR_BLEN_Pos (24U)
20086#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos)
20087#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk
20089/******************* Bit definition for USART_RQR register ******************/
20090#define USART_RQR_ABRRQ_Pos (0U)
20091#define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos)
20092#define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk
20093#define USART_RQR_SBKRQ_Pos (1U)
20094#define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos)
20095#define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk
20096#define USART_RQR_MMRQ_Pos (2U)
20097#define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos)
20098#define USART_RQR_MMRQ USART_RQR_MMRQ_Msk
20099#define USART_RQR_RXFRQ_Pos (3U)
20100#define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos)
20101#define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk
20102#define USART_RQR_TXFRQ_Pos (4U)
20103#define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos)
20104#define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk
20106/******************* Bit definition for USART_ISR register ******************/
20107#define USART_ISR_PE_Pos (0U)
20108#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos)
20109#define USART_ISR_PE USART_ISR_PE_Msk
20110#define USART_ISR_FE_Pos (1U)
20111#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos)
20112#define USART_ISR_FE USART_ISR_FE_Msk
20113#define USART_ISR_NE_Pos (2U)
20114#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos)
20115#define USART_ISR_NE USART_ISR_NE_Msk
20116#define USART_ISR_ORE_Pos (3U)
20117#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos)
20118#define USART_ISR_ORE USART_ISR_ORE_Msk
20119#define USART_ISR_IDLE_Pos (4U)
20120#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos)
20121#define USART_ISR_IDLE USART_ISR_IDLE_Msk
20122#define USART_ISR_RXNE_RXFNE_Pos (5U)
20123#define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos)
20124#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk
20125#define USART_ISR_TC_Pos (6U)
20126#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos)
20127#define USART_ISR_TC USART_ISR_TC_Msk
20128#define USART_ISR_TXE_TXFNF_Pos (7U)
20129#define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos)
20130#define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk
20131#define USART_ISR_LBDF_Pos (8U)
20132#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos)
20133#define USART_ISR_LBDF USART_ISR_LBDF_Msk
20134#define USART_ISR_CTSIF_Pos (9U)
20135#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos)
20136#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk
20137#define USART_ISR_CTS_Pos (10U)
20138#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos)
20139#define USART_ISR_CTS USART_ISR_CTS_Msk
20140#define USART_ISR_RTOF_Pos (11U)
20141#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos)
20142#define USART_ISR_RTOF USART_ISR_RTOF_Msk
20143#define USART_ISR_EOBF_Pos (12U)
20144#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos)
20145#define USART_ISR_EOBF USART_ISR_EOBF_Msk
20146#define USART_ISR_UDR_Pos (13U)
20147#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos)
20148#define USART_ISR_UDR USART_ISR_UDR_Msk
20149#define USART_ISR_ABRE_Pos (14U)
20150#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos)
20151#define USART_ISR_ABRE USART_ISR_ABRE_Msk
20152#define USART_ISR_ABRF_Pos (15U)
20153#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos)
20154#define USART_ISR_ABRF USART_ISR_ABRF_Msk
20155#define USART_ISR_BUSY_Pos (16U)
20156#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos)
20157#define USART_ISR_BUSY USART_ISR_BUSY_Msk
20158#define USART_ISR_CMF_Pos (17U)
20159#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos)
20160#define USART_ISR_CMF USART_ISR_CMF_Msk
20161#define USART_ISR_SBKF_Pos (18U)
20162#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos)
20163#define USART_ISR_SBKF USART_ISR_SBKF_Msk
20164#define USART_ISR_RWU_Pos (19U)
20165#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos)
20166#define USART_ISR_RWU USART_ISR_RWU_Msk
20167#define USART_ISR_WUF_Pos (20U)
20168#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos)
20169#define USART_ISR_WUF USART_ISR_WUF_Msk
20170#define USART_ISR_TEACK_Pos (21U)
20171#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos)
20172#define USART_ISR_TEACK USART_ISR_TEACK_Msk
20173#define USART_ISR_REACK_Pos (22U)
20174#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos)
20175#define USART_ISR_REACK USART_ISR_REACK_Msk
20176#define USART_ISR_TXFE_Pos (23U)
20177#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos)
20178#define USART_ISR_TXFE USART_ISR_TXFE_Msk
20179#define USART_ISR_RXFF_Pos (24U)
20180#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos)
20181#define USART_ISR_RXFF USART_ISR_RXFF_Msk
20182#define USART_ISR_TCBGT_Pos (25U)
20183#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos)
20184#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk
20185#define USART_ISR_RXFT_Pos (26U)
20186#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos)
20187#define USART_ISR_RXFT USART_ISR_RXFT_Msk
20188#define USART_ISR_TXFT_Pos (27U)
20189#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos)
20190#define USART_ISR_TXFT USART_ISR_TXFT_Msk
20192/******************* Bit definition for USART_ICR register ******************/
20193#define USART_ICR_PECF_Pos (0U)
20194#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos)
20195#define USART_ICR_PECF USART_ICR_PECF_Msk
20196#define USART_ICR_FECF_Pos (1U)
20197#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos)
20198#define USART_ICR_FECF USART_ICR_FECF_Msk
20199#define USART_ICR_NECF_Pos (2U)
20200#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos)
20201#define USART_ICR_NECF USART_ICR_NECF_Msk
20202#define USART_ICR_ORECF_Pos (3U)
20203#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos)
20204#define USART_ICR_ORECF USART_ICR_ORECF_Msk
20205#define USART_ICR_IDLECF_Pos (4U)
20206#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos)
20207#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk
20208#define USART_ICR_TXFECF_Pos (5U)
20209#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos)
20210#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk
20211#define USART_ICR_TCCF_Pos (6U)
20212#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos)
20213#define USART_ICR_TCCF USART_ICR_TCCF_Msk
20214#define USART_ICR_TCBGTCF_Pos (7U)
20215#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos)
20216#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk
20217#define USART_ICR_LBDCF_Pos (8U)
20218#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos)
20219#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk
20220#define USART_ICR_CTSCF_Pos (9U)
20221#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos)
20222#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk
20223#define USART_ICR_RTOCF_Pos (11U)
20224#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos)
20225#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk
20226#define USART_ICR_EOBCF_Pos (12U)
20227#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos)
20228#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk
20229#define USART_ICR_UDRCF_Pos (13U)
20230#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos)
20231#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk
20232#define USART_ICR_CMCF_Pos (17U)
20233#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos)
20234#define USART_ICR_CMCF USART_ICR_CMCF_Msk
20235#define USART_ICR_WUCF_Pos (20U)
20236#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos)
20237#define USART_ICR_WUCF USART_ICR_WUCF_Msk
20239/******************* Bit definition for USART_RDR register ******************/
20240#define USART_RDR_RDR_Pos (0U)
20241#define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos)
20242#define USART_RDR_RDR USART_RDR_RDR_Msk
20244/******************* Bit definition for USART_TDR register ******************/
20245#define USART_TDR_TDR_Pos (0U)
20246#define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos)
20247#define USART_TDR_TDR USART_TDR_TDR_Msk
20249/******************* Bit definition for USART_PRESC register ******************/
20250#define USART_PRESC_PRESCALER_Pos (0U)
20251#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos)
20252#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk
20253#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos)
20254#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos)
20255#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos)
20256#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos)
20258/******************************************************************************/
20259/* */
20260/* Single Wire Protocol Master Interface (SWPMI) */
20261/* */
20262/******************************************************************************/
20263
20264/******************* Bit definition for SWPMI_CR register ********************/
20265#define SWPMI_CR_RXDMA_Pos (0U)
20266#define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos)
20267#define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk
20268#define SWPMI_CR_TXDMA_Pos (1U)
20269#define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos)
20270#define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk
20271#define SWPMI_CR_RXMODE_Pos (2U)
20272#define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos)
20273#define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk
20274#define SWPMI_CR_TXMODE_Pos (3U)
20275#define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos)
20276#define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk
20277#define SWPMI_CR_LPBK_Pos (4U)
20278#define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos)
20279#define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk
20280#define SWPMI_CR_SWPACT_Pos (5U)
20281#define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos)
20282#define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk
20283#define SWPMI_CR_DEACT_Pos (10U)
20284#define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos)
20285#define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk
20286#define SWPMI_CR_SWPEN_Pos (11U)
20287#define SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos)
20288#define SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk
20290/******************* Bit definition for SWPMI_BRR register ********************/
20291#define SWPMI_BRR_BR_Pos (0U)
20292#define SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos)
20293#define SWPMI_BRR_BR SWPMI_BRR_BR_Msk
20295/******************* Bit definition for SWPMI_ISR register ********************/
20296#define SWPMI_ISR_RXBFF_Pos (0U)
20297#define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos)
20298#define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk
20299#define SWPMI_ISR_TXBEF_Pos (1U)
20300#define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos)
20301#define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk
20302#define SWPMI_ISR_RXBERF_Pos (2U)
20303#define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos)
20304#define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk
20305#define SWPMI_ISR_RXOVRF_Pos (3U)
20306#define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos)
20307#define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk
20308#define SWPMI_ISR_TXUNRF_Pos (4U)
20309#define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos)
20310#define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk
20311#define SWPMI_ISR_RXNE_Pos (5U)
20312#define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos)
20313#define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk
20314#define SWPMI_ISR_TXE_Pos (6U)
20315#define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos)
20316#define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk
20317#define SWPMI_ISR_TCF_Pos (7U)
20318#define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos)
20319#define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk
20320#define SWPMI_ISR_SRF_Pos (8U)
20321#define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos)
20322#define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk
20323#define SWPMI_ISR_SUSP_Pos (9U)
20324#define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos)
20325#define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk
20326#define SWPMI_ISR_DEACTF_Pos (10U)
20327#define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos)
20328#define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk
20329#define SWPMI_ISR_RDYF_Pos (11U)
20330#define SWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos)
20331#define SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk
20333/******************* Bit definition for SWPMI_ICR register ********************/
20334#define SWPMI_ICR_CRXBFF_Pos (0U)
20335#define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos)
20336#define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk
20337#define SWPMI_ICR_CTXBEF_Pos (1U)
20338#define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos)
20339#define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk
20340#define SWPMI_ICR_CRXBERF_Pos (2U)
20341#define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos)
20342#define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk
20343#define SWPMI_ICR_CRXOVRF_Pos (3U)
20344#define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos)
20345#define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk
20346#define SWPMI_ICR_CTXUNRF_Pos (4U)
20347#define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos)
20348#define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk
20349#define SWPMI_ICR_CTCF_Pos (7U)
20350#define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos)
20351#define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk
20352#define SWPMI_ICR_CSRF_Pos (8U)
20353#define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos)
20354#define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk
20355#define SWPMI_ICR_CRDYF_Pos (11U)
20356#define SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos)
20357#define SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk
20359/******************* Bit definition for SWPMI_IER register ********************/
20360#define SWPMI_IER_RXBFIE_Pos (0U)
20361#define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos)
20362#define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk
20363#define SWPMI_IER_TXBEIE_Pos (1U)
20364#define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos)
20365#define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk
20366#define SWPMI_IER_RXBERIE_Pos (2U)
20367#define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos)
20368#define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk
20369#define SWPMI_IER_RXOVRIE_Pos (3U)
20370#define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos)
20371#define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk
20372#define SWPMI_IER_TXUNRIE_Pos (4U)
20373#define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos)
20374#define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk
20375#define SWPMI_IER_RIE_Pos (5U)
20376#define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos)
20377#define SWPMI_IER_RIE SWPMI_IER_RIE_Msk
20378#define SWPMI_IER_TIE_Pos (6U)
20379#define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos)
20380#define SWPMI_IER_TIE SWPMI_IER_TIE_Msk
20381#define SWPMI_IER_TCIE_Pos (7U)
20382#define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos)
20383#define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk
20384#define SWPMI_IER_SRIE_Pos (8U)
20385#define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos)
20386#define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk
20387#define SWPMI_IER_RDYIE_Pos (11U)
20388#define SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos)
20389#define SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk
20391/******************* Bit definition for SWPMI_RFL register ********************/
20392#define SWPMI_RFL_RFL_Pos (0U)
20393#define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos)
20394#define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk
20395#define SWPMI_RFL_RFL_0_1 (0x00000003U)
20397/******************* Bit definition for SWPMI_TDR register ********************/
20398#define SWPMI_TDR_TD_Pos (0U)
20399#define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)
20400#define SWPMI_TDR_TD SWPMI_TDR_TD_Msk
20402/******************* Bit definition for SWPMI_RDR register ********************/
20403#define SWPMI_RDR_RD_Pos (0U)
20404#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)
20405#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk
20408/******************* Bit definition for SWPMI_OR register ********************/
20409#define SWPMI_OR_TBYP_Pos (0U)
20410#define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos)
20411#define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk
20412#define SWPMI_OR_CLASS_Pos (1U)
20413#define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos)
20414#define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk
20416/******************************************************************************/
20417/* */
20418/* Window WATCHDOG */
20419/* */
20420/******************************************************************************/
20421/******************* Bit definition for WWDG_CR register ********************/
20422#define WWDG_CR_T_Pos (0U)
20423#define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)
20424#define WWDG_CR_T WWDG_CR_T_Msk
20425#define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)
20426#define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)
20427#define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)
20428#define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)
20429#define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)
20430#define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)
20431#define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)
20433#define WWDG_CR_WDGA_Pos (7U)
20434#define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)
20435#define WWDG_CR_WDGA WWDG_CR_WDGA_Msk
20437/******************* Bit definition for WWDG_CFR register *******************/
20438#define WWDG_CFR_W_Pos (0U)
20439#define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)
20440#define WWDG_CFR_W WWDG_CFR_W_Msk
20441#define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)
20442#define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)
20443#define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)
20444#define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)
20445#define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)
20446#define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)
20447#define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)
20449#define WWDG_CFR_EWI_Pos (9U)
20450#define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)
20451#define WWDG_CFR_EWI WWDG_CFR_EWI_Msk
20453#define WWDG_CFR_WDGTB_Pos (11U)
20454#define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos)
20455#define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk
20456#define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)
20457#define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)
20458#define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos)
20460/******************* Bit definition for WWDG_SR register ********************/
20461#define WWDG_SR_EWIF_Pos (0U)
20462#define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)
20463#define WWDG_SR_EWIF WWDG_SR_EWIF_Msk
20466/******************************************************************************/
20467/* */
20468/* DBG */
20469/* */
20470/******************************************************************************/
20471/********************************* DEVICE ID ********************************/
20472#define STM32H7_DEV_ID 0x450UL
20473
20474/******************** Bit definition for DBGMCU_IDCODE register *************/
20475#define DBGMCU_IDCODE_DEV_ID_Pos (0U)
20476#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)
20477#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
20478#define DBGMCU_IDCODE_REV_ID_Pos (16U)
20479#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)
20480#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
20481
20482/******************** Bit definition for DBGMCU_CR register *****************/
20483#define DBGMCU_CR_DBG_SLEEPD1_Pos (0U)
20484#define DBGMCU_CR_DBG_SLEEPD1_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos)
20485#define DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPD1_Msk
20486#define DBGMCU_CR_DBG_STOPD1_Pos (1U)
20487#define DBGMCU_CR_DBG_STOPD1_Msk (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)
20488#define DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPD1_Msk
20489#define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)
20490#define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos)
20491#define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk
20492#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
20493#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos)
20494#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
20495#define DBGMCU_CR_DBG_CKD1EN_Pos (21U)
20496#define DBGMCU_CR_DBG_CKD1EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)
20497#define DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKD1EN_Msk
20498#define DBGMCU_CR_DBG_CKD3EN_Pos (22U)
20499#define DBGMCU_CR_DBG_CKD3EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)
20500#define DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKD3EN_Msk
20501#define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
20502#define DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)
20503#define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
20504
20505/******************** Bit definition for APB3FZ1 register ************/
20506#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U)
20507#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos)
20508#define DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk
20509/******************** Bit definition for APB1LFZ1 register ************/
20510#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U)
20511#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos)
20512#define DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk
20513#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U)
20514#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos)
20515#define DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk
20516#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U)
20517#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos)
20518#define DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk
20519#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U)
20520#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos)
20521#define DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk
20522#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U)
20523#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos)
20524#define DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk
20525#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U)
20526#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos)
20527#define DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk
20528#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U)
20529#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos)
20530#define DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk
20531#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U)
20532#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos)
20533#define DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk
20534#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U)
20535#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos)
20536#define DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk
20537#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U)
20538#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos)
20539#define DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
20540#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U)
20541#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos)
20542#define DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk
20543#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U)
20544#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos)
20545#define DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk
20546#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U)
20547#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos)
20548#define DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk
20549
20550/******************** Bit definition for APB1HFZ1 register ************/
20551#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos (8U)
20552#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos)
20553#define DBGMCU_APB1HFZ1_DBG_FDCAN DBGMCU_APB1HFZ1_DBG_FDCAN_Msk
20554/******************** Bit definition for APB2FZ1 register ************/
20555#define DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U)
20556#define DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos)
20557#define DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk
20558#define DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U)
20559#define DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos)
20560#define DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk
20561#define DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U)
20562#define DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos)
20563#define DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk
20564#define DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U)
20565#define DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos)
20566#define DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk
20567#define DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U)
20568#define DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos)
20569#define DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk
20570#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos (29U)
20571#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos)
20572#define DBGMCU_APB2FZ1_DBG_HRTIM DBGMCU_APB2FZ1_DBG_HRTIM_Msk
20573
20574/******************** Bit definition for APB4FZ1 register ************/
20575#define DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U)
20576#define DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos)
20577#define DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk
20578#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U)
20579#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos)
20580#define DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
20581#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U)
20582#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos)
20583#define DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
20584#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos (11U)
20585#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos)
20586#define DBGMCU_APB4FZ1_DBG_LPTIM4 DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
20587#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos (12U)
20588#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos)
20589#define DBGMCU_APB4FZ1_DBG_LPTIM5 DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
20590#define DBGMCU_APB4FZ1_DBG_RTC_Pos (16U)
20591#define DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos)
20592#define DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk
20593#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U)
20594#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos)
20595#define DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk
20596/******************************************************************************/
20597/* */
20598/* High Resolution Timer (HRTIM) */
20599/* */
20600/******************************************************************************/
20601/******************** Master Timer control register ***************************/
20602#define HRTIM_MCR_CK_PSC_Pos (0U)
20603#define HRTIM_MCR_CK_PSC_Msk (0x7UL << HRTIM_MCR_CK_PSC_Pos)
20604#define HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk
20605#define HRTIM_MCR_CK_PSC_0 (0x1UL << HRTIM_MCR_CK_PSC_Pos)
20606#define HRTIM_MCR_CK_PSC_1 (0x2UL << HRTIM_MCR_CK_PSC_Pos)
20607#define HRTIM_MCR_CK_PSC_2 (0x4UL << HRTIM_MCR_CK_PSC_Pos)
20609#define HRTIM_MCR_CONT_Pos (3U)
20610#define HRTIM_MCR_CONT_Msk (0x1UL << HRTIM_MCR_CONT_Pos)
20611#define HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk
20612#define HRTIM_MCR_RETRIG_Pos (4U)
20613#define HRTIM_MCR_RETRIG_Msk (0x1UL << HRTIM_MCR_RETRIG_Pos)
20614#define HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk
20615#define HRTIM_MCR_HALF_Pos (5U)
20616#define HRTIM_MCR_HALF_Msk (0x1UL << HRTIM_MCR_HALF_Pos)
20617#define HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk
20619#define HRTIM_MCR_SYNC_IN_Pos (8U)
20620#define HRTIM_MCR_SYNC_IN_Msk (0x3UL << HRTIM_MCR_SYNC_IN_Pos)
20621#define HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk
20622#define HRTIM_MCR_SYNC_IN_0 (0x1UL << HRTIM_MCR_SYNC_IN_Pos)
20623#define HRTIM_MCR_SYNC_IN_1 (0x2UL << HRTIM_MCR_SYNC_IN_Pos)
20624#define HRTIM_MCR_SYNCRSTM_Pos (10U)
20625#define HRTIM_MCR_SYNCRSTM_Msk (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)
20626#define HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk
20627#define HRTIM_MCR_SYNCSTRTM_Pos (11U)
20628#define HRTIM_MCR_SYNCSTRTM_Msk (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)
20629#define HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk
20630#define HRTIM_MCR_SYNC_OUT_Pos (12U)
20631#define HRTIM_MCR_SYNC_OUT_Msk (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)
20632#define HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk
20633#define HRTIM_MCR_SYNC_OUT_0 (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)
20634#define HRTIM_MCR_SYNC_OUT_1 (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)
20635#define HRTIM_MCR_SYNC_SRC_Pos (14U)
20636#define HRTIM_MCR_SYNC_SRC_Msk (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)
20637#define HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk
20638#define HRTIM_MCR_SYNC_SRC_0 (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)
20639#define HRTIM_MCR_SYNC_SRC_1 (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)
20641#define HRTIM_MCR_MCEN_Pos (16U)
20642#define HRTIM_MCR_MCEN_Msk (0x1UL << HRTIM_MCR_MCEN_Pos)
20643#define HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk
20644#define HRTIM_MCR_TACEN_Pos (17U)
20645#define HRTIM_MCR_TACEN_Msk (0x1UL << HRTIM_MCR_TACEN_Pos)
20646#define HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk
20647#define HRTIM_MCR_TBCEN_Pos (18U)
20648#define HRTIM_MCR_TBCEN_Msk (0x1UL << HRTIM_MCR_TBCEN_Pos)
20649#define HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk
20650#define HRTIM_MCR_TCCEN_Pos (19U)
20651#define HRTIM_MCR_TCCEN_Msk (0x1UL << HRTIM_MCR_TCCEN_Pos)
20652#define HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk
20653#define HRTIM_MCR_TDCEN_Pos (20U)
20654#define HRTIM_MCR_TDCEN_Msk (0x1UL << HRTIM_MCR_TDCEN_Pos)
20655#define HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk
20656#define HRTIM_MCR_TECEN_Pos (21U)
20657#define HRTIM_MCR_TECEN_Msk (0x1UL << HRTIM_MCR_TECEN_Pos)
20658#define HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk
20660#define HRTIM_MCR_DACSYNC_Pos (25U)
20661#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos)
20662#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk
20663#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos)
20664#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos)
20666#define HRTIM_MCR_PREEN_Pos (27U)
20667#define HRTIM_MCR_PREEN_Msk (0x1UL << HRTIM_MCR_PREEN_Pos)
20668#define HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk
20669#define HRTIM_MCR_MREPU_Pos (29U)
20670#define HRTIM_MCR_MREPU_Msk (0x1UL << HRTIM_MCR_MREPU_Pos)
20671#define HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk
20673#define HRTIM_MCR_BRSTDMA_Pos (30U)
20674#define HRTIM_MCR_BRSTDMA_Msk (0x3UL << HRTIM_MCR_BRSTDMA_Pos)
20675#define HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk
20676#define HRTIM_MCR_BRSTDMA_0 (0x1UL << HRTIM_MCR_BRSTDMA_Pos)
20677#define HRTIM_MCR_BRSTDMA_1 (0x2UL << HRTIM_MCR_BRSTDMA_Pos)
20679/******************** Master Timer Interrupt status register ******************/
20680#define HRTIM_MISR_MCMP1_Pos (0U)
20681#define HRTIM_MISR_MCMP1_Msk (0x1UL << HRTIM_MISR_MCMP1_Pos)
20682#define HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk
20683#define HRTIM_MISR_MCMP2_Pos (1U)
20684#define HRTIM_MISR_MCMP2_Msk (0x1UL << HRTIM_MISR_MCMP2_Pos)
20685#define HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk
20686#define HRTIM_MISR_MCMP3_Pos (2U)
20687#define HRTIM_MISR_MCMP3_Msk (0x1UL << HRTIM_MISR_MCMP3_Pos)
20688#define HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk
20689#define HRTIM_MISR_MCMP4_Pos (3U)
20690#define HRTIM_MISR_MCMP4_Msk (0x1UL << HRTIM_MISR_MCMP4_Pos)
20691#define HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk
20692#define HRTIM_MISR_MREP_Pos (4U)
20693#define HRTIM_MISR_MREP_Msk (0x1UL << HRTIM_MISR_MREP_Pos)
20694#define HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk
20695#define HRTIM_MISR_SYNC_Pos (5U)
20696#define HRTIM_MISR_SYNC_Msk (0x1UL << HRTIM_MISR_SYNC_Pos)
20697#define HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk
20698#define HRTIM_MISR_MUPD_Pos (6U)
20699#define HRTIM_MISR_MUPD_Msk (0x1UL << HRTIM_MISR_MUPD_Pos)
20700#define HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk
20702/******************** Master Timer Interrupt clear register *******************/
20703#define HRTIM_MICR_MCMP1_Pos (0U)
20704#define HRTIM_MICR_MCMP1_Msk (0x1UL << HRTIM_MICR_MCMP1_Pos)
20705#define HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk
20706#define HRTIM_MICR_MCMP2_Pos (1U)
20707#define HRTIM_MICR_MCMP2_Msk (0x1UL << HRTIM_MICR_MCMP2_Pos)
20708#define HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk
20709#define HRTIM_MICR_MCMP3_Pos (2U)
20710#define HRTIM_MICR_MCMP3_Msk (0x1UL << HRTIM_MICR_MCMP3_Pos)
20711#define HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk
20712#define HRTIM_MICR_MCMP4_Pos (3U)
20713#define HRTIM_MICR_MCMP4_Msk (0x1UL << HRTIM_MICR_MCMP4_Pos)
20714#define HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk
20715#define HRTIM_MICR_MREP_Pos (4U)
20716#define HRTIM_MICR_MREP_Msk (0x1UL << HRTIM_MICR_MREP_Pos)
20717#define HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk
20718#define HRTIM_MICR_SYNC_Pos (5U)
20719#define HRTIM_MICR_SYNC_Msk (0x1UL << HRTIM_MICR_SYNC_Pos)
20720#define HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk
20721#define HRTIM_MICR_MUPD_Pos (6U)
20722#define HRTIM_MICR_MUPD_Msk (0x1UL << HRTIM_MICR_MUPD_Pos)
20723#define HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk
20725/******************** Master Timer DMA/Interrupt enable register **************/
20726#define HRTIM_MDIER_MCMP1IE_Pos (0U)
20727#define HRTIM_MDIER_MCMP1IE_Msk (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)
20728#define HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk
20729#define HRTIM_MDIER_MCMP2IE_Pos (1U)
20730#define HRTIM_MDIER_MCMP2IE_Msk (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)
20731#define HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk
20732#define HRTIM_MDIER_MCMP3IE_Pos (2U)
20733#define HRTIM_MDIER_MCMP3IE_Msk (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)
20734#define HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk
20735#define HRTIM_MDIER_MCMP4IE_Pos (3U)
20736#define HRTIM_MDIER_MCMP4IE_Msk (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)
20737#define HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk
20738#define HRTIM_MDIER_MREPIE_Pos (4U)
20739#define HRTIM_MDIER_MREPIE_Msk (0x1UL << HRTIM_MDIER_MREPIE_Pos)
20740#define HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk
20741#define HRTIM_MDIER_SYNCIE_Pos (5U)
20742#define HRTIM_MDIER_SYNCIE_Msk (0x1UL << HRTIM_MDIER_SYNCIE_Pos)
20743#define HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk
20744#define HRTIM_MDIER_MUPDIE_Pos (6U)
20745#define HRTIM_MDIER_MUPDIE_Msk (0x1UL << HRTIM_MDIER_MUPDIE_Pos)
20746#define HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk
20748#define HRTIM_MDIER_MCMP1DE_Pos (16U)
20749#define HRTIM_MDIER_MCMP1DE_Msk (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)
20750#define HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk
20751#define HRTIM_MDIER_MCMP2DE_Pos (17U)
20752#define HRTIM_MDIER_MCMP2DE_Msk (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)
20753#define HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk
20754#define HRTIM_MDIER_MCMP3DE_Pos (18U)
20755#define HRTIM_MDIER_MCMP3DE_Msk (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)
20756#define HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk
20757#define HRTIM_MDIER_MCMP4DE_Pos (19U)
20758#define HRTIM_MDIER_MCMP4DE_Msk (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)
20759#define HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk
20760#define HRTIM_MDIER_MREPDE_Pos (20U)
20761#define HRTIM_MDIER_MREPDE_Msk (0x1UL << HRTIM_MDIER_MREPDE_Pos)
20762#define HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk
20763#define HRTIM_MDIER_SYNCDE_Pos (21U)
20764#define HRTIM_MDIER_SYNCDE_Msk (0x1UL << HRTIM_MDIER_SYNCDE_Pos)
20765#define HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk
20766#define HRTIM_MDIER_MUPDDE_Pos (22U)
20767#define HRTIM_MDIER_MUPDDE_Msk (0x1UL << HRTIM_MDIER_MUPDDE_Pos)
20768#define HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk
20770/******************* Bit definition for HRTIM_MCNTR register ****************/
20771#define HRTIM_MCNTR_MCNTR_Pos (0U)
20772#define HRTIM_MCNTR_MCNTR_Msk (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)
20773#define HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk
20775/******************* Bit definition for HRTIM_MPER register *****************/
20776#define HRTIM_MPER_MPER_Pos (0U)
20777#define HRTIM_MPER_MPER_Msk (0xFFFFUL << HRTIM_MPER_MPER_Pos)
20778#define HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk
20780/******************* Bit definition for HRTIM_MREP register *****************/
20781#define HRTIM_MREP_MREP_Pos (0U)
20782#define HRTIM_MREP_MREP_Msk (0xFFUL << HRTIM_MREP_MREP_Pos)
20783#define HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk
20785/******************* Bit definition for HRTIM_MCMP1R register *****************/
20786#define HRTIM_MCMP1R_MCMP1R_Pos (0U)
20787#define HRTIM_MCMP1R_MCMP1R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)
20788#define HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk
20790/******************* Bit definition for HRTIM_MCMP2R register *****************/
20791#define HRTIM_MCMP1R_MCMP2R_Pos (0U)
20792#define HRTIM_MCMP1R_MCMP2R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)
20793#define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP1R_MCMP2R_Msk
20795/******************* Bit definition for HRTIM_MCMP3R register *****************/
20796#define HRTIM_MCMP1R_MCMP3R_Pos (0U)
20797#define HRTIM_MCMP1R_MCMP3R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)
20798#define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP1R_MCMP3R_Msk
20800/******************* Bit definition for HRTIM_MCMP4R register *****************/
20801#define HRTIM_MCMP1R_MCMP4R_Pos (0U)
20802#define HRTIM_MCMP1R_MCMP4R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)
20803#define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP1R_MCMP4R_Msk
20805/******************** Slave control register **********************************/
20806#define HRTIM_TIMCR_CK_PSC_Pos (0U)
20807#define HRTIM_TIMCR_CK_PSC_Msk (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)
20808#define HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk
20809#define HRTIM_TIMCR_CK_PSC_0 (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)
20810#define HRTIM_TIMCR_CK_PSC_1 (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)
20811#define HRTIM_TIMCR_CK_PSC_2 (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)
20813#define HRTIM_TIMCR_CONT_Pos (3U)
20814#define HRTIM_TIMCR_CONT_Msk (0x1UL << HRTIM_TIMCR_CONT_Pos)
20815#define HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk
20816#define HRTIM_TIMCR_RETRIG_Pos (4U)
20817#define HRTIM_TIMCR_RETRIG_Msk (0x1UL << HRTIM_TIMCR_RETRIG_Pos)
20818#define HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk
20819#define HRTIM_TIMCR_HALF_Pos (5U)
20820#define HRTIM_TIMCR_HALF_Msk (0x1UL << HRTIM_TIMCR_HALF_Pos)
20821#define HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk
20822#define HRTIM_TIMCR_PSHPLL_Pos (6U)
20823#define HRTIM_TIMCR_PSHPLL_Msk (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)
20824#define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk
20826#define HRTIM_TIMCR_SYNCRST_Pos (10U)
20827#define HRTIM_TIMCR_SYNCRST_Msk (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)
20828#define HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk
20829#define HRTIM_TIMCR_SYNCSTRT_Pos (11U)
20830#define HRTIM_TIMCR_SYNCSTRT_Msk (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)
20831#define HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk
20833#define HRTIM_TIMCR_DELCMP2_Pos (12U)
20834#define HRTIM_TIMCR_DELCMP2_Msk (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)
20835#define HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk
20836#define HRTIM_TIMCR_DELCMP2_0 (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)
20837#define HRTIM_TIMCR_DELCMP2_1 (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)
20838#define HRTIM_TIMCR_DELCMP4_Pos (14U)
20839#define HRTIM_TIMCR_DELCMP4_Msk (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)
20840#define HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk
20841#define HRTIM_TIMCR_DELCMP4_0 (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)
20842#define HRTIM_TIMCR_DELCMP4_1 (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)
20844#define HRTIM_TIMCR_TREPU_Pos (17U)
20845#define HRTIM_TIMCR_TREPU_Msk (0x1UL << HRTIM_TIMCR_TREPU_Pos)
20846#define HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk
20847#define HRTIM_TIMCR_TRSTU_Pos (18U)
20848#define HRTIM_TIMCR_TRSTU_Msk (0x1UL << HRTIM_TIMCR_TRSTU_Pos)
20849#define HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk
20850#define HRTIM_TIMCR_TAU_Pos (19U)
20851#define HRTIM_TIMCR_TAU_Msk (0x1UL << HRTIM_TIMCR_TAU_Pos)
20852#define HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk
20853#define HRTIM_TIMCR_TBU_Pos (20U)
20854#define HRTIM_TIMCR_TBU_Msk (0x1UL << HRTIM_TIMCR_TBU_Pos)
20855#define HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk
20856#define HRTIM_TIMCR_TCU_Pos (21U)
20857#define HRTIM_TIMCR_TCU_Msk (0x1UL << HRTIM_TIMCR_TCU_Pos)
20858#define HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk
20859#define HRTIM_TIMCR_TDU_Pos (22U)
20860#define HRTIM_TIMCR_TDU_Msk (0x1UL << HRTIM_TIMCR_TDU_Pos)
20861#define HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk
20862#define HRTIM_TIMCR_TEU_Pos (23U)
20863#define HRTIM_TIMCR_TEU_Msk (0x1UL << HRTIM_TIMCR_TEU_Pos)
20864#define HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk
20865#define HRTIM_TIMCR_MSTU_Pos (24U)
20866#define HRTIM_TIMCR_MSTU_Msk (0x1UL << HRTIM_TIMCR_MSTU_Pos)
20867#define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk
20869#define HRTIM_TIMCR_DACSYNC_Pos (25U)
20870#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)
20871#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk
20872#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)
20873#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)
20874#define HRTIM_TIMCR_PREEN_Pos (27U)
20875#define HRTIM_TIMCR_PREEN_Msk (0x1UL << HRTIM_TIMCR_PREEN_Pos)
20876#define HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk
20878#define HRTIM_TIMCR_UPDGAT_Pos (28U)
20879#define HRTIM_TIMCR_UPDGAT_Msk (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)
20880#define HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk
20881#define HRTIM_TIMCR_UPDGAT_0 (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)
20882#define HRTIM_TIMCR_UPDGAT_1 (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)
20883#define HRTIM_TIMCR_UPDGAT_2 (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)
20884#define HRTIM_TIMCR_UPDGAT_3 (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)
20886/******************** Slave Interrupt status register **************************/
20887#define HRTIM_TIMISR_CMP1_Pos (0U)
20888#define HRTIM_TIMISR_CMP1_Msk (0x1UL << HRTIM_TIMISR_CMP1_Pos)
20889#define HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk
20890#define HRTIM_TIMISR_CMP2_Pos (1U)
20891#define HRTIM_TIMISR_CMP2_Msk (0x1UL << HRTIM_TIMISR_CMP2_Pos)
20892#define HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk
20893#define HRTIM_TIMISR_CMP3_Pos (2U)
20894#define HRTIM_TIMISR_CMP3_Msk (0x1UL << HRTIM_TIMISR_CMP3_Pos)
20895#define HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk
20896#define HRTIM_TIMISR_CMP4_Pos (3U)
20897#define HRTIM_TIMISR_CMP4_Msk (0x1UL << HRTIM_TIMISR_CMP4_Pos)
20898#define HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk
20899#define HRTIM_TIMISR_REP_Pos (4U)
20900#define HRTIM_TIMISR_REP_Msk (0x1UL << HRTIM_TIMISR_REP_Pos)
20901#define HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk
20902#define HRTIM_TIMISR_UPD_Pos (6U)
20903#define HRTIM_TIMISR_UPD_Msk (0x1UL << HRTIM_TIMISR_UPD_Pos)
20904#define HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk
20905#define HRTIM_TIMISR_CPT1_Pos (7U)
20906#define HRTIM_TIMISR_CPT1_Msk (0x1UL << HRTIM_TIMISR_CPT1_Pos)
20907#define HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk
20908#define HRTIM_TIMISR_CPT2_Pos (8U)
20909#define HRTIM_TIMISR_CPT2_Msk (0x1UL << HRTIM_TIMISR_CPT2_Pos)
20910#define HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk
20911#define HRTIM_TIMISR_SET1_Pos (9U)
20912#define HRTIM_TIMISR_SET1_Msk (0x1UL << HRTIM_TIMISR_SET1_Pos)
20913#define HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk
20914#define HRTIM_TIMISR_RST1_Pos (10U)
20915#define HRTIM_TIMISR_RST1_Msk (0x1UL << HRTIM_TIMISR_RST1_Pos)
20916#define HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk
20917#define HRTIM_TIMISR_SET2_Pos (11U)
20918#define HRTIM_TIMISR_SET2_Msk (0x1UL << HRTIM_TIMISR_SET2_Pos)
20919#define HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk
20920#define HRTIM_TIMISR_RST2_Pos (12U)
20921#define HRTIM_TIMISR_RST2_Msk (0x1UL << HRTIM_TIMISR_RST2_Pos)
20922#define HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk
20923#define HRTIM_TIMISR_RST_Pos (13U)
20924#define HRTIM_TIMISR_RST_Msk (0x1UL << HRTIM_TIMISR_RST_Pos)
20925#define HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk
20926#define HRTIM_TIMISR_DLYPRT_Pos (14U)
20927#define HRTIM_TIMISR_DLYPRT_Msk (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)
20928#define HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk
20929#define HRTIM_TIMISR_CPPSTAT_Pos (16U)
20930#define HRTIM_TIMISR_CPPSTAT_Msk (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)
20931#define HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk
20932#define HRTIM_TIMISR_IPPSTAT_Pos (17U)
20933#define HRTIM_TIMISR_IPPSTAT_Msk (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)
20934#define HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk
20935#define HRTIM_TIMISR_O1STAT_Pos (18U)
20936#define HRTIM_TIMISR_O1STAT_Msk (0x1UL << HRTIM_TIMISR_O1STAT_Pos)
20937#define HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk
20938#define HRTIM_TIMISR_O2STAT_Pos (19U)
20939#define HRTIM_TIMISR_O2STAT_Msk (0x1UL << HRTIM_TIMISR_O2STAT_Pos)
20940#define HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk
20941#define HRTIM_TIMISR_O1CPY_Pos (20U)
20942#define HRTIM_TIMISR_O1CPY_Msk (0x1UL << HRTIM_TIMISR_O1CPY_Pos)
20943#define HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk
20944#define HRTIM_TIMISR_O2CPY_Pos (21U)
20945#define HRTIM_TIMISR_O2CPY_Msk (0x1UL << HRTIM_TIMISR_O2CPY_Pos)
20946#define HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk
20948/******************** Slave Interrupt clear register **************************/
20949#define HRTIM_TIMICR_CMP1C_Pos (0U)
20950#define HRTIM_TIMICR_CMP1C_Msk (0x1UL << HRTIM_TIMICR_CMP1C_Pos)
20951#define HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk
20952#define HRTIM_TIMICR_CMP2C_Pos (1U)
20953#define HRTIM_TIMICR_CMP2C_Msk (0x1UL << HRTIM_TIMICR_CMP2C_Pos)
20954#define HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk
20955#define HRTIM_TIMICR_CMP3C_Pos (2U)
20956#define HRTIM_TIMICR_CMP3C_Msk (0x1UL << HRTIM_TIMICR_CMP3C_Pos)
20957#define HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk
20958#define HRTIM_TIMICR_CMP4C_Pos (3U)
20959#define HRTIM_TIMICR_CMP4C_Msk (0x1UL << HRTIM_TIMICR_CMP4C_Pos)
20960#define HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk
20961#define HRTIM_TIMICR_REPC_Pos (4U)
20962#define HRTIM_TIMICR_REPC_Msk (0x1UL << HRTIM_TIMICR_REPC_Pos)
20963#define HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk
20964#define HRTIM_TIMICR_UPDC_Pos (6U)
20965#define HRTIM_TIMICR_UPDC_Msk (0x1UL << HRTIM_TIMICR_UPDC_Pos)
20966#define HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk
20967#define HRTIM_TIMICR_CPT1C_Pos (7U)
20968#define HRTIM_TIMICR_CPT1C_Msk (0x1UL << HRTIM_TIMICR_CPT1C_Pos)
20969#define HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk
20970#define HRTIM_TIMICR_CPT2C_Pos (8U)
20971#define HRTIM_TIMICR_CPT2C_Msk (0x1UL << HRTIM_TIMICR_CPT2C_Pos)
20972#define HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk
20973#define HRTIM_TIMICR_SET1C_Pos (9U)
20974#define HRTIM_TIMICR_SET1C_Msk (0x1UL << HRTIM_TIMICR_SET1C_Pos)
20975#define HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk
20976#define HRTIM_TIMICR_RST1C_Pos (10U)
20977#define HRTIM_TIMICR_RST1C_Msk (0x1UL << HRTIM_TIMICR_RST1C_Pos)
20978#define HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk
20979#define HRTIM_TIMICR_SET2C_Pos (11U)
20980#define HRTIM_TIMICR_SET2C_Msk (0x1UL << HRTIM_TIMICR_SET2C_Pos)
20981#define HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk
20982#define HRTIM_TIMICR_RST2C_Pos (12U)
20983#define HRTIM_TIMICR_RST2C_Msk (0x1UL << HRTIM_TIMICR_RST2C_Pos)
20984#define HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk
20985#define HRTIM_TIMICR_RSTC_Pos (13U)
20986#define HRTIM_TIMICR_RSTC_Msk (0x1UL << HRTIM_TIMICR_RSTC_Pos)
20987#define HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk
20988#define HRTIM_TIMICR_DLYPRTC_Pos (14U)
20989#define HRTIM_TIMICR_DLYPRTC_Msk (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)
20990#define HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk
20992/******************** Slave DMA/Interrupt enable register *********************/
20993#define HRTIM_TIMDIER_CMP1IE_Pos (0U)
20994#define HRTIM_TIMDIER_CMP1IE_Msk (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)
20995#define HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk
20996#define HRTIM_TIMDIER_CMP2IE_Pos (1U)
20997#define HRTIM_TIMDIER_CMP2IE_Msk (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)
20998#define HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk
20999#define HRTIM_TIMDIER_CMP3IE_Pos (2U)
21000#define HRTIM_TIMDIER_CMP3IE_Msk (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)
21001#define HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk
21002#define HRTIM_TIMDIER_CMP4IE_Pos (3U)
21003#define HRTIM_TIMDIER_CMP4IE_Msk (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)
21004#define HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk
21005#define HRTIM_TIMDIER_REPIE_Pos (4U)
21006#define HRTIM_TIMDIER_REPIE_Msk (0x1UL << HRTIM_TIMDIER_REPIE_Pos)
21007#define HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk
21008#define HRTIM_TIMDIER_UPDIE_Pos (6U)
21009#define HRTIM_TIMDIER_UPDIE_Msk (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)
21010#define HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk
21011#define HRTIM_TIMDIER_CPT1IE_Pos (7U)
21012#define HRTIM_TIMDIER_CPT1IE_Msk (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)
21013#define HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk
21014#define HRTIM_TIMDIER_CPT2IE_Pos (8U)
21015#define HRTIM_TIMDIER_CPT2IE_Msk (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)
21016#define HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk
21017#define HRTIM_TIMDIER_SET1IE_Pos (9U)
21018#define HRTIM_TIMDIER_SET1IE_Msk (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)
21019#define HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk
21020#define HRTIM_TIMDIER_RST1IE_Pos (10U)
21021#define HRTIM_TIMDIER_RST1IE_Msk (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)
21022#define HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk
21023#define HRTIM_TIMDIER_SET2IE_Pos (11U)
21024#define HRTIM_TIMDIER_SET2IE_Msk (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)
21025#define HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk
21026#define HRTIM_TIMDIER_RST2IE_Pos (12U)
21027#define HRTIM_TIMDIER_RST2IE_Msk (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)
21028#define HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk
21029#define HRTIM_TIMDIER_RSTIE_Pos (13U)
21030#define HRTIM_TIMDIER_RSTIE_Msk (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)
21031#define HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk
21032#define HRTIM_TIMDIER_DLYPRTIE_Pos (14U)
21033#define HRTIM_TIMDIER_DLYPRTIE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)
21034#define HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk
21036#define HRTIM_TIMDIER_CMP1DE_Pos (16U)
21037#define HRTIM_TIMDIER_CMP1DE_Msk (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)
21038#define HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk
21039#define HRTIM_TIMDIER_CMP2DE_Pos (17U)
21040#define HRTIM_TIMDIER_CMP2DE_Msk (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)
21041#define HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk
21042#define HRTIM_TIMDIER_CMP3DE_Pos (18U)
21043#define HRTIM_TIMDIER_CMP3DE_Msk (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)
21044#define HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk
21045#define HRTIM_TIMDIER_CMP4DE_Pos (19U)
21046#define HRTIM_TIMDIER_CMP4DE_Msk (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)
21047#define HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk
21048#define HRTIM_TIMDIER_REPDE_Pos (20U)
21049#define HRTIM_TIMDIER_REPDE_Msk (0x1UL << HRTIM_TIMDIER_REPDE_Pos)
21050#define HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk
21051#define HRTIM_TIMDIER_UPDDE_Pos (22U)
21052#define HRTIM_TIMDIER_UPDDE_Msk (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)
21053#define HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk
21054#define HRTIM_TIMDIER_CPT1DE_Pos (23U)
21055#define HRTIM_TIMDIER_CPT1DE_Msk (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)
21056#define HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk
21057#define HRTIM_TIMDIER_CPT2DE_Pos (24U)
21058#define HRTIM_TIMDIER_CPT2DE_Msk (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)
21059#define HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk
21060#define HRTIM_TIMDIER_SET1DE_Pos (25U)
21061#define HRTIM_TIMDIER_SET1DE_Msk (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)
21062#define HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk
21063#define HRTIM_TIMDIER_RST1DE_Pos (26U)
21064#define HRTIM_TIMDIER_RST1DE_Msk (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)
21065#define HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk
21066#define HRTIM_TIMDIER_SET2DE_Pos (27U)
21067#define HRTIM_TIMDIER_SET2DE_Msk (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)
21068#define HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk
21069#define HRTIM_TIMDIER_RST2DE_Pos (28U)
21070#define HRTIM_TIMDIER_RST2DE_Msk (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)
21071#define HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk
21072#define HRTIM_TIMDIER_RSTDE_Pos (29U)
21073#define HRTIM_TIMDIER_RSTDE_Msk (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)
21074#define HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk
21075#define HRTIM_TIMDIER_DLYPRTDE_Pos (30U)
21076#define HRTIM_TIMDIER_DLYPRTDE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)
21077#define HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk
21079/****************** Bit definition for HRTIM_CNTR register ****************/
21080#define HRTIM_CNTR_CNTR_Pos (0U)
21081#define HRTIM_CNTR_CNTR_Msk (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)
21082#define HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk
21084/******************* Bit definition for HRTIM_PER register *****************/
21085#define HRTIM_PER_PER_Pos (0U)
21086#define HRTIM_PER_PER_Msk (0xFFFFUL << HRTIM_PER_PER_Pos)
21087#define HRTIM_PER_PER HRTIM_PER_PER_Msk
21089/******************* Bit definition for HRTIM_REP register *****************/
21090#define HRTIM_REP_REP_Pos (0U)
21091#define HRTIM_REP_REP_Msk (0xFFUL << HRTIM_REP_REP_Pos)
21092#define HRTIM_REP_REP HRTIM_REP_REP_Msk
21094/******************* Bit definition for HRTIM_CMP1R register *****************/
21095#define HRTIM_CMP1R_CMP1R_Pos (0U)
21096#define HRTIM_CMP1R_CMP1R_Msk (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)
21097#define HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk
21099/******************* Bit definition for HRTIM_CMP1CR register *****************/
21100#define HRTIM_CMP1CR_CMP1CR_Pos (0U)
21101#define HRTIM_CMP1CR_CMP1CR_Msk (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos)
21102#define HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk
21104/******************* Bit definition for HRTIM_CMP2R register *****************/
21105#define HRTIM_CMP2R_CMP2R_Pos (0U)
21106#define HRTIM_CMP2R_CMP2R_Msk (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)
21107#define HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk
21109/******************* Bit definition for HRTIM_CMP3R register *****************/
21110#define HRTIM_CMP3R_CMP3R_Pos (0U)
21111#define HRTIM_CMP3R_CMP3R_Msk (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)
21112#define HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk
21114/******************* Bit definition for HRTIM_CMP4R register *****************/
21115#define HRTIM_CMP4R_CMP4R_Pos (0U)
21116#define HRTIM_CMP4R_CMP4R_Msk (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)
21117#define HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk
21119/******************* Bit definition for HRTIM_CPT1R register ****************/
21120#define HRTIM_CPT1R_CPT1R_Pos (0U)
21121#define HRTIM_CPT1R_CPT1R_Msk (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)
21122#define HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk
21124/******************* Bit definition for HRTIM_CPT2R register ****************/
21125#define HRTIM_CPT2R_CPT2R_Pos (0U)
21126#define HRTIM_CPT2R_CPT2R_Msk (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)
21127#define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk
21129/******************** Bit definition for Slave Deadtime register **************/
21130#define HRTIM_DTR_DTR_Pos (0U)
21131#define HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos)
21132#define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk
21133#define HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos)
21134#define HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos)
21135#define HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos)
21136#define HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos)
21137#define HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos)
21138#define HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos)
21139#define HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos)
21140#define HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos)
21141#define HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos)
21142#define HRTIM_DTR_SDTR_Pos (9U)
21143#define HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos)
21144#define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk
21145#define HRTIM_DTR_DTPRSC_Pos (10U)
21146#define HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos)
21147#define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk
21148#define HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos)
21149#define HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos)
21150#define HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos)
21151#define HRTIM_DTR_DTRSLK_Pos (14U)
21152#define HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos)
21153#define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk
21154#define HRTIM_DTR_DTRLK_Pos (15U)
21155#define HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos)
21156#define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk
21157#define HRTIM_DTR_DTF_Pos (16U)
21158#define HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos)
21159#define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk
21160#define HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos)
21161#define HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos)
21162#define HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos)
21163#define HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos)
21164#define HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos)
21165#define HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos)
21166#define HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos)
21167#define HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos)
21168#define HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos)
21169#define HRTIM_DTR_SDTF_Pos (25U)
21170#define HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos)
21171#define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk
21172#define HRTIM_DTR_DTFSLK_Pos (30U)
21173#define HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos)
21174#define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk
21175#define HRTIM_DTR_DTFLK_Pos (31U)
21176#define HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos)
21177#define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk
21179/**** Bit definition for Slave Output 1 set register **************************/
21180#define HRTIM_SET1R_SST_Pos (0U)
21181#define HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos)
21182#define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk
21183#define HRTIM_SET1R_RESYNC_Pos (1U)
21184#define HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos)
21185#define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk
21186#define HRTIM_SET1R_PER_Pos (2U)
21187#define HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos)
21188#define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk
21189#define HRTIM_SET1R_CMP1_Pos (3U)
21190#define HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos)
21191#define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk
21192#define HRTIM_SET1R_CMP2_Pos (4U)
21193#define HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos)
21194#define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk
21195#define HRTIM_SET1R_CMP3_Pos (5U)
21196#define HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos)
21197#define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk
21198#define HRTIM_SET1R_CMP4_Pos (6U)
21199#define HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos)
21200#define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk
21202#define HRTIM_SET1R_MSTPER_Pos (7U)
21203#define HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos)
21204#define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk
21205#define HRTIM_SET1R_MSTCMP1_Pos (8U)
21206#define HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)
21207#define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk
21208#define HRTIM_SET1R_MSTCMP2_Pos (9U)
21209#define HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)
21210#define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk
21211#define HRTIM_SET1R_MSTCMP3_Pos (10U)
21212#define HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)
21213#define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk
21214#define HRTIM_SET1R_MSTCMP4_Pos (11U)
21215#define HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)
21216#define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk
21218#define HRTIM_SET1R_TIMEVNT1_Pos (12U)
21219#define HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)
21220#define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk
21221#define HRTIM_SET1R_TIMEVNT2_Pos (13U)
21222#define HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)
21223#define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk
21224#define HRTIM_SET1R_TIMEVNT3_Pos (14U)
21225#define HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)
21226#define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk
21227#define HRTIM_SET1R_TIMEVNT4_Pos (15U)
21228#define HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)
21229#define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk
21230#define HRTIM_SET1R_TIMEVNT5_Pos (16U)
21231#define HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)
21232#define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk
21233#define HRTIM_SET1R_TIMEVNT6_Pos (17U)
21234#define HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)
21235#define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk
21236#define HRTIM_SET1R_TIMEVNT7_Pos (18U)
21237#define HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)
21238#define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk
21239#define HRTIM_SET1R_TIMEVNT8_Pos (19U)
21240#define HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)
21241#define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk
21242#define HRTIM_SET1R_TIMEVNT9_Pos (20U)
21243#define HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)
21244#define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk
21246#define HRTIM_SET1R_EXTVNT1_Pos (21U)
21247#define HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)
21248#define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk
21249#define HRTIM_SET1R_EXTVNT2_Pos (22U)
21250#define HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)
21251#define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk
21252#define HRTIM_SET1R_EXTVNT3_Pos (23U)
21253#define HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)
21254#define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk
21255#define HRTIM_SET1R_EXTVNT4_Pos (24U)
21256#define HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)
21257#define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk
21258#define HRTIM_SET1R_EXTVNT5_Pos (25U)
21259#define HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)
21260#define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk
21261#define HRTIM_SET1R_EXTVNT6_Pos (26U)
21262#define HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)
21263#define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk
21264#define HRTIM_SET1R_EXTVNT7_Pos (27U)
21265#define HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)
21266#define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk
21267#define HRTIM_SET1R_EXTVNT8_Pos (28U)
21268#define HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)
21269#define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk
21270#define HRTIM_SET1R_EXTVNT9_Pos (29U)
21271#define HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)
21272#define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk
21273#define HRTIM_SET1R_EXTVNT10_Pos (30U)
21274#define HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)
21275#define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk
21277#define HRTIM_SET1R_UPDATE_Pos (31U)
21278#define HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos)
21279#define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk
21281/**** Bit definition for Slave Output 1 reset register ************************/
21282#define HRTIM_RST1R_SRT_Pos (0U)
21283#define HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos)
21284#define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk
21285#define HRTIM_RST1R_RESYNC_Pos (1U)
21286#define HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos)
21287#define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk
21288#define HRTIM_RST1R_PER_Pos (2U)
21289#define HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos)
21290#define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk
21291#define HRTIM_RST1R_CMP1_Pos (3U)
21292#define HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos)
21293#define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk
21294#define HRTIM_RST1R_CMP2_Pos (4U)
21295#define HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos)
21296#define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk
21297#define HRTIM_RST1R_CMP3_Pos (5U)
21298#define HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos)
21299#define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk
21300#define HRTIM_RST1R_CMP4_Pos (6U)
21301#define HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos)
21302#define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk
21304#define HRTIM_RST1R_MSTPER_Pos (7U)
21305#define HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos)
21306#define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk
21307#define HRTIM_RST1R_MSTCMP1_Pos (8U)
21308#define HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)
21309#define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk
21310#define HRTIM_RST1R_MSTCMP2_Pos (9U)
21311#define HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)
21312#define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk
21313#define HRTIM_RST1R_MSTCMP3_Pos (10U)
21314#define HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)
21315#define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk
21316#define HRTIM_RST1R_MSTCMP4_Pos (11U)
21317#define HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)
21318#define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk
21320#define HRTIM_RST1R_TIMEVNT1_Pos (12U)
21321#define HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)
21322#define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk
21323#define HRTIM_RST1R_TIMEVNT2_Pos (13U)
21324#define HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)
21325#define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk
21326#define HRTIM_RST1R_TIMEVNT3_Pos (14U)
21327#define HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)
21328#define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk
21329#define HRTIM_RST1R_TIMEVNT4_Pos (15U)
21330#define HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)
21331#define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk
21332#define HRTIM_RST1R_TIMEVNT5_Pos (16U)
21333#define HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)
21334#define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk
21335#define HRTIM_RST1R_TIMEVNT6_Pos (17U)
21336#define HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)
21337#define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk
21338#define HRTIM_RST1R_TIMEVNT7_Pos (18U)
21339#define HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)
21340#define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk
21341#define HRTIM_RST1R_TIMEVNT8_Pos (19U)
21342#define HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)
21343#define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk
21344#define HRTIM_RST1R_TIMEVNT9_Pos (20U)
21345#define HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)
21346#define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk
21348#define HRTIM_RST1R_EXTVNT1_Pos (21U)
21349#define HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)
21350#define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk
21351#define HRTIM_RST1R_EXTVNT2_Pos (22U)
21352#define HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)
21353#define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk
21354#define HRTIM_RST1R_EXTVNT3_Pos (23U)
21355#define HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)
21356#define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk
21357#define HRTIM_RST1R_EXTVNT4_Pos (24U)
21358#define HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)
21359#define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk
21360#define HRTIM_RST1R_EXTVNT5_Pos (25U)
21361#define HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)
21362#define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk
21363#define HRTIM_RST1R_EXTVNT6_Pos (26U)
21364#define HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)
21365#define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk
21366#define HRTIM_RST1R_EXTVNT7_Pos (27U)
21367#define HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)
21368#define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk
21369#define HRTIM_RST1R_EXTVNT8_Pos (28U)
21370#define HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)
21371#define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk
21372#define HRTIM_RST1R_EXTVNT9_Pos (29U)
21373#define HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)
21374#define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk
21375#define HRTIM_RST1R_EXTVNT10_Pos (30U)
21376#define HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)
21377#define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk
21379#define HRTIM_RST1R_UPDATE_Pos (31U)
21380#define HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos)
21381#define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk
21384/**** Bit definition for Slave Output 2 set register **************************/
21385#define HRTIM_SET2R_SST_Pos (0U)
21386#define HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos)
21387#define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk
21388#define HRTIM_SET2R_RESYNC_Pos (1U)
21389#define HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos)
21390#define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk
21391#define HRTIM_SET2R_PER_Pos (2U)
21392#define HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos)
21393#define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk
21394#define HRTIM_SET2R_CMP1_Pos (3U)
21395#define HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos)
21396#define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk
21397#define HRTIM_SET2R_CMP2_Pos (4U)
21398#define HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos)
21399#define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk
21400#define HRTIM_SET2R_CMP3_Pos (5U)
21401#define HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos)
21402#define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk
21403#define HRTIM_SET2R_CMP4_Pos (6U)
21404#define HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos)
21405#define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk
21407#define HRTIM_SET2R_MSTPER_Pos (7U)
21408#define HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos)
21409#define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk
21410#define HRTIM_SET2R_MSTCMP1_Pos (8U)
21411#define HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)
21412#define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk
21413#define HRTIM_SET2R_MSTCMP2_Pos (9U)
21414#define HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)
21415#define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk
21416#define HRTIM_SET2R_MSTCMP3_Pos (10U)
21417#define HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)
21418#define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk
21419#define HRTIM_SET2R_MSTCMP4_Pos (11U)
21420#define HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)
21421#define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk
21423#define HRTIM_SET2R_TIMEVNT1_Pos (12U)
21424#define HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)
21425#define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk
21426#define HRTIM_SET2R_TIMEVNT2_Pos (13U)
21427#define HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)
21428#define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk
21429#define HRTIM_SET2R_TIMEVNT3_Pos (14U)
21430#define HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)
21431#define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk
21432#define HRTIM_SET2R_TIMEVNT4_Pos (15U)
21433#define HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)
21434#define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk
21435#define HRTIM_SET2R_TIMEVNT5_Pos (16U)
21436#define HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)
21437#define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk
21438#define HRTIM_SET2R_TIMEVNT6_Pos (17U)
21439#define HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)
21440#define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk
21441#define HRTIM_SET2R_TIMEVNT7_Pos (18U)
21442#define HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)
21443#define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk
21444#define HRTIM_SET2R_TIMEVNT8_Pos (19U)
21445#define HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)
21446#define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk
21447#define HRTIM_SET2R_TIMEVNT9_Pos (20U)
21448#define HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)
21449#define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk
21451#define HRTIM_SET2R_EXTVNT1_Pos (21U)
21452#define HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)
21453#define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk
21454#define HRTIM_SET2R_EXTVNT2_Pos (22U)
21455#define HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)
21456#define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk
21457#define HRTIM_SET2R_EXTVNT3_Pos (23U)
21458#define HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)
21459#define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk
21460#define HRTIM_SET2R_EXTVNT4_Pos (24U)
21461#define HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)
21462#define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk
21463#define HRTIM_SET2R_EXTVNT5_Pos (25U)
21464#define HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)
21465#define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk
21466#define HRTIM_SET2R_EXTVNT6_Pos (26U)
21467#define HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)
21468#define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk
21469#define HRTIM_SET2R_EXTVNT7_Pos (27U)
21470#define HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)
21471#define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk
21472#define HRTIM_SET2R_EXTVNT8_Pos (28U)
21473#define HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)
21474#define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk
21475#define HRTIM_SET2R_EXTVNT9_Pos (29U)
21476#define HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)
21477#define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk
21478#define HRTIM_SET2R_EXTVNT10_Pos (30U)
21479#define HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)
21480#define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk
21482#define HRTIM_SET2R_UPDATE_Pos (31U)
21483#define HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos)
21484#define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk
21486/**** Bit definition for Slave Output 2 reset register ************************/
21487#define HRTIM_RST2R_SRT_Pos (0U)
21488#define HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos)
21489#define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk
21490#define HRTIM_RST2R_RESYNC_Pos (1U)
21491#define HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos)
21492#define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk
21493#define HRTIM_RST2R_PER_Pos (2U)
21494#define HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos)
21495#define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk
21496#define HRTIM_RST2R_CMP1_Pos (3U)
21497#define HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos)
21498#define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk
21499#define HRTIM_RST2R_CMP2_Pos (4U)
21500#define HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos)
21501#define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk
21502#define HRTIM_RST2R_CMP3_Pos (5U)
21503#define HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos)
21504#define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk
21505#define HRTIM_RST2R_CMP4_Pos (6U)
21506#define HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos)
21507#define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk
21509#define HRTIM_RST2R_MSTPER_Pos (7U)
21510#define HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos)
21511#define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk
21512#define HRTIM_RST2R_MSTCMP1_Pos (8U)
21513#define HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)
21514#define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk
21515#define HRTIM_RST2R_MSTCMP2_Pos (9U)
21516#define HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)
21517#define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk
21518#define HRTIM_RST2R_MSTCMP3_Pos (10U)
21519#define HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)
21520#define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk
21521#define HRTIM_RST2R_MSTCMP4_Pos (11U)
21522#define HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)
21523#define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk
21525#define HRTIM_RST2R_TIMEVNT1_Pos (12U)
21526#define HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)
21527#define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk
21528#define HRTIM_RST2R_TIMEVNT2_Pos (13U)
21529#define HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)
21530#define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk
21531#define HRTIM_RST2R_TIMEVNT3_Pos (14U)
21532#define HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)
21533#define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk
21534#define HRTIM_RST2R_TIMEVNT4_Pos (15U)
21535#define HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)
21536#define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk
21537#define HRTIM_RST2R_TIMEVNT5_Pos (16U)
21538#define HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)
21539#define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk
21540#define HRTIM_RST2R_TIMEVNT6_Pos (17U)
21541#define HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)
21542#define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk
21543#define HRTIM_RST2R_TIMEVNT7_Pos (18U)
21544#define HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)
21545#define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk
21546#define HRTIM_RST2R_TIMEVNT8_Pos (19U)
21547#define HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)
21548#define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk
21549#define HRTIM_RST2R_TIMEVNT9_Pos (20U)
21550#define HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)
21551#define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk
21553#define HRTIM_RST2R_EXTVNT1_Pos (21U)
21554#define HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)
21555#define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk
21556#define HRTIM_RST2R_EXTVNT2_Pos (22U)
21557#define HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)
21558#define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk
21559#define HRTIM_RST2R_EXTVNT3_Pos (23U)
21560#define HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)
21561#define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk
21562#define HRTIM_RST2R_EXTVNT4_Pos (24U)
21563#define HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)
21564#define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk
21565#define HRTIM_RST2R_EXTVNT5_Pos (25U)
21566#define HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)
21567#define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk
21568#define HRTIM_RST2R_EXTVNT6_Pos (26U)
21569#define HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)
21570#define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk
21571#define HRTIM_RST2R_EXTVNT7_Pos (27U)
21572#define HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)
21573#define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk
21574#define HRTIM_RST2R_EXTVNT8_Pos (28U)
21575#define HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)
21576#define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk
21577#define HRTIM_RST2R_EXTVNT9_Pos (29U)
21578#define HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)
21579#define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk
21580#define HRTIM_RST2R_EXTVNT10_Pos (30U)
21581#define HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)
21582#define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk
21584#define HRTIM_RST2R_UPDATE_Pos (31U)
21585#define HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos)
21586#define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk
21588/**** Bit definition for Slave external event filtering register 1 ***********/
21589#define HRTIM_EEFR1_EE1LTCH_Pos (0U)
21590#define HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)
21591#define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk
21592#define HRTIM_EEFR1_EE1FLTR_Pos (1U)
21593#define HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)
21594#define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk
21595#define HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)
21596#define HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)
21597#define HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)
21598#define HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)
21600#define HRTIM_EEFR1_EE2LTCH_Pos (6U)
21601#define HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)
21602#define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk
21603#define HRTIM_EEFR1_EE2FLTR_Pos (7U)
21604#define HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)
21605#define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk
21606#define HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)
21607#define HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)
21608#define HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)
21609#define HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)
21611#define HRTIM_EEFR1_EE3LTCH_Pos (12U)
21612#define HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)
21613#define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk
21614#define HRTIM_EEFR1_EE3FLTR_Pos (13U)
21615#define HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)
21616#define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk
21617#define HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)
21618#define HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)
21619#define HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)
21620#define HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)
21622#define HRTIM_EEFR1_EE4LTCH_Pos (18U)
21623#define HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)
21624#define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk
21625#define HRTIM_EEFR1_EE4FLTR_Pos (19U)
21626#define HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)
21627#define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk
21628#define HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)
21629#define HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)
21630#define HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)
21631#define HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)
21633#define HRTIM_EEFR1_EE5LTCH_Pos (24U)
21634#define HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)
21635#define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk
21636#define HRTIM_EEFR1_EE5FLTR_Pos (25U)
21637#define HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)
21638#define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk
21639#define HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)
21640#define HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)
21641#define HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)
21642#define HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)
21644/**** Bit definition for Slave external event filtering register 2 ***********/
21645#define HRTIM_EEFR2_EE6LTCH_Pos (0U)
21646#define HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)
21647#define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk
21648#define HRTIM_EEFR2_EE6FLTR_Pos (1U)
21649#define HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)
21650#define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk
21651#define HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)
21652#define HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)
21653#define HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)
21654#define HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)
21656#define HRTIM_EEFR2_EE7LTCH_Pos (6U)
21657#define HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)
21658#define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk
21659#define HRTIM_EEFR2_EE7FLTR_Pos (7U)
21660#define HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)
21661#define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk
21662#define HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)
21663#define HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)
21664#define HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)
21665#define HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)
21667#define HRTIM_EEFR2_EE8LTCH_Pos (12U)
21668#define HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)
21669#define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk
21670#define HRTIM_EEFR2_EE8FLTR_Pos (13U)
21671#define HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)
21672#define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk
21673#define HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)
21674#define HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)
21675#define HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)
21676#define HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)
21678#define HRTIM_EEFR2_EE9LTCH_Pos (18U)
21679#define HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)
21680#define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk
21681#define HRTIM_EEFR2_EE9FLTR_Pos (19U)
21682#define HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)
21683#define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk
21684#define HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)
21685#define HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)
21686#define HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)
21687#define HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)
21689#define HRTIM_EEFR2_EE10LTCH_Pos (24U)
21690#define HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)
21691#define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk
21692#define HRTIM_EEFR2_EE10FLTR_Pos (25U)
21693#define HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)
21694#define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk
21695#define HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)
21696#define HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)
21697#define HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)
21698#define HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)
21700/**** Bit definition for Slave Timer reset register ***************************/
21701#define HRTIM_RSTR_UPDATE_Pos (1U)
21702#define HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos)
21703#define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk
21704#define HRTIM_RSTR_CMP2_Pos (2U)
21705#define HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos)
21706#define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk
21707#define HRTIM_RSTR_CMP4_Pos (3U)
21708#define HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos)
21709#define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk
21711#define HRTIM_RSTR_MSTPER_Pos (4U)
21712#define HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos)
21713#define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk
21714#define HRTIM_RSTR_MSTCMP1_Pos (5U)
21715#define HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)
21716#define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk
21717#define HRTIM_RSTR_MSTCMP2_Pos (6U)
21718#define HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)
21719#define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk
21720#define HRTIM_RSTR_MSTCMP3_Pos (7U)
21721#define HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)
21722#define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk
21723#define HRTIM_RSTR_MSTCMP4_Pos (8U)
21724#define HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)
21725#define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk
21727#define HRTIM_RSTR_EXTEVNT1_Pos (9U)
21728#define HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)
21729#define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk
21730#define HRTIM_RSTR_EXTEVNT2_Pos (10U)
21731#define HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)
21732#define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk
21733#define HRTIM_RSTR_EXTEVNT3_Pos (11U)
21734#define HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)
21735#define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk
21736#define HRTIM_RSTR_EXTEVNT4_Pos (12U)
21737#define HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)
21738#define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk
21739#define HRTIM_RSTR_EXTEVNT5_Pos (13U)
21740#define HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)
21741#define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk
21742#define HRTIM_RSTR_EXTEVNT6_Pos (14U)
21743#define HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)
21744#define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk
21745#define HRTIM_RSTR_EXTEVNT7_Pos (15U)
21746#define HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)
21747#define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk
21748#define HRTIM_RSTR_EXTEVNT8_Pos (16U)
21749#define HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)
21750#define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk
21751#define HRTIM_RSTR_EXTEVNT9_Pos (17U)
21752#define HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)
21753#define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk
21754#define HRTIM_RSTR_EXTEVNT10_Pos (18U)
21755#define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)
21756#define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk
21758/* Slave Timer A reset enable bits upon other slave timers events */
21759#define HRTIM_RSTR_TIMBCMP1_Pos (19U)
21760#define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)
21761#define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk
21762#define HRTIM_RSTR_TIMBCMP2_Pos (20U)
21763#define HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)
21764#define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk
21765#define HRTIM_RSTR_TIMBCMP4_Pos (21U)
21766#define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)
21767#define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk
21769#define HRTIM_RSTR_TIMCCMP1_Pos (22U)
21770#define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)
21771#define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk
21772#define HRTIM_RSTR_TIMCCMP2_Pos (23U)
21773#define HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)
21774#define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk
21775#define HRTIM_RSTR_TIMCCMP4_Pos (24U)
21776#define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)
21777#define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk
21779#define HRTIM_RSTR_TIMDCMP1_Pos (25U)
21780#define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)
21781#define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk
21782#define HRTIM_RSTR_TIMDCMP2_Pos (26U)
21783#define HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)
21784#define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk
21785#define HRTIM_RSTR_TIMDCMP4_Pos (27U)
21786#define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)
21787#define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk
21789#define HRTIM_RSTR_TIMECMP1_Pos (28U)
21790#define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)
21791#define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk
21792#define HRTIM_RSTR_TIMECMP2_Pos (29U)
21793#define HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)
21794#define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk
21795#define HRTIM_RSTR_TIMECMP4_Pos (30U)
21796#define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)
21797#define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk
21799/* Slave Timer B reset enable bits upon other slave timers events */
21800#define HRTIM_RSTBR_TIMACMP1_Pos (19U)
21801#define HRTIM_RSTBR_TIMACMP1_Msk (0x1UL << HRTIM_RSTBR_TIMACMP1_Pos)
21802#define HRTIM_RSTBR_TIMACMP1 HRTIM_RSTBR_TIMACMP1_Msk
21803#define HRTIM_RSTBR_TIMACMP2_Pos (20U)
21804#define HRTIM_RSTBR_TIMACMP2_Msk (0x1UL << HRTIM_RSTBR_TIMACMP2_Pos)
21805#define HRTIM_RSTBR_TIMACMP2 HRTIM_RSTBR_TIMACMP2_Msk
21806#define HRTIM_RSTBR_TIMACMP4_Pos (21U)
21807#define HRTIM_RSTBR_TIMACMP4_Msk (0x1UL << HRTIM_RSTBR_TIMACMP4_Pos)
21808#define HRTIM_RSTBR_TIMACMP4 HRTIM_RSTBR_TIMACMP4_Msk
21810#define HRTIM_RSTBR_TIMCCMP1_Pos (22U)
21811#define HRTIM_RSTBR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP1_Pos)
21812#define HRTIM_RSTBR_TIMCCMP1 HRTIM_RSTBR_TIMCCMP1_Msk
21813#define HRTIM_RSTBR_TIMCCMP2_Pos (23U)
21814#define HRTIM_RSTBR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP2_Pos)
21815#define HRTIM_RSTBR_TIMCCMP2 HRTIM_RSTBR_TIMCCMP2_Msk
21816#define HRTIM_RSTBR_TIMCCMP4_Pos (24U)
21817#define HRTIM_RSTBR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMCCMP4_Pos)
21818#define HRTIM_RSTBR_TIMCCMP4 HRTIM_RSTBR_TIMCCMP4_Msk
21820#define HRTIM_RSTBR_TIMDCMP1_Pos (25U)
21821#define HRTIM_RSTBR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP1_Pos)
21822#define HRTIM_RSTBR_TIMDCMP1 HRTIM_RSTBR_TIMDCMP1_Msk
21823#define HRTIM_RSTBR_TIMDCMP2_Pos (26U)
21824#define HRTIM_RSTBR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP2_Pos)
21825#define HRTIM_RSTBR_TIMDCMP2 HRTIM_RSTBR_TIMDCMP2_Msk
21826#define HRTIM_RSTBR_TIMDCMP4_Pos (27U)
21827#define HRTIM_RSTBR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTBR_TIMDCMP4_Pos)
21828#define HRTIM_RSTBR_TIMDCMP4 HRTIM_RSTBR_TIMDCMP4_Msk
21830#define HRTIM_RSTBR_TIMECMP1_Pos (28U)
21831#define HRTIM_RSTBR_TIMECMP1_Msk (0x1UL << HRTIM_RSTBR_TIMECMP1_Pos)
21832#define HRTIM_RSTBR_TIMECMP1 HRTIM_RSTBR_TIMECMP1_Msk
21833#define HRTIM_RSTBR_TIMECMP2_Pos (29U)
21834#define HRTIM_RSTBR_TIMECMP2_Msk (0x1UL << HRTIM_RSTBR_TIMECMP2_Pos)
21835#define HRTIM_RSTBR_TIMECMP2 HRTIM_RSTBR_TIMECMP2_Msk
21836#define HRTIM_RSTBR_TIMECMP4_Pos (30U)
21837#define HRTIM_RSTBR_TIMECMP4_Msk (0x1UL << HRTIM_RSTBR_TIMECMP4_Pos)
21838#define HRTIM_RSTBR_TIMECMP4 HRTIM_RSTBR_TIMECMP4_Msk
21840/* Slave Timer C reset enable bits upon other slave timers events */
21841#define HRTIM_RSTCR_TIMACMP1_Pos (19U)
21842#define HRTIM_RSTCR_TIMACMP1_Msk (0x1UL << HRTIM_RSTCR_TIMACMP1_Pos)
21843#define HRTIM_RSTCR_TIMACMP1 HRTIM_RSTCR_TIMACMP1_Msk
21844#define HRTIM_RSTCR_TIMACMP2_Pos (20U)
21845#define HRTIM_RSTCR_TIMACMP2_Msk (0x1UL << HRTIM_RSTCR_TIMACMP2_Pos)
21846#define HRTIM_RSTCR_TIMACMP2 HRTIM_RSTCR_TIMACMP2_Msk
21847#define HRTIM_RSTCR_TIMACMP4_Pos (21U)
21848#define HRTIM_RSTCR_TIMACMP4_Msk (0x1UL << HRTIM_RSTCR_TIMACMP4_Pos)
21849#define HRTIM_RSTCR_TIMACMP4 HRTIM_RSTCR_TIMACMP4_Msk
21851#define HRTIM_RSTCR_TIMBCMP1_Pos (22U)
21852#define HRTIM_RSTCR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP1_Pos)
21853#define HRTIM_RSTCR_TIMBCMP1 HRTIM_RSTCR_TIMBCMP1_Msk
21854#define HRTIM_RSTCR_TIMBCMP2_Pos (23U)
21855#define HRTIM_RSTCR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP2_Pos)
21856#define HRTIM_RSTCR_TIMBCMP2 HRTIM_RSTCR_TIMBCMP2_Msk
21857#define HRTIM_RSTCR_TIMBCMP4_Pos (24U)
21858#define HRTIM_RSTCR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMBCMP4_Pos)
21859#define HRTIM_RSTCR_TIMBCMP4 HRTIM_RSTCR_TIMBCMP4_Msk
21861#define HRTIM_RSTCR_TIMDCMP1_Pos (25U)
21862#define HRTIM_RSTCR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP1_Pos)
21863#define HRTIM_RSTCR_TIMDCMP1 HRTIM_RSTCR_TIMDCMP1_Msk
21864#define HRTIM_RSTCR_TIMDCMP2_Pos (26U)
21865#define HRTIM_RSTCR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP2_Pos)
21866#define HRTIM_RSTCR_TIMDCMP2 HRTIM_RSTCR_TIMDCMP2_Msk
21867#define HRTIM_RSTCR_TIMDCMP4_Pos (27U)
21868#define HRTIM_RSTCR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTCR_TIMDCMP4_Pos)
21869#define HRTIM_RSTCR_TIMDCMP4 HRTIM_RSTCR_TIMDCMP4_Msk
21871#define HRTIM_RSTCR_TIMECMP1_Pos (28U)
21872#define HRTIM_RSTCR_TIMECMP1_Msk (0x1UL << HRTIM_RSTCR_TIMECMP1_Pos)
21873#define HRTIM_RSTCR_TIMECMP1 HRTIM_RSTCR_TIMECMP1_Msk
21874#define HRTIM_RSTCR_TIMECMP2_Pos (29U)
21875#define HRTIM_RSTCR_TIMECMP2_Msk (0x1UL << HRTIM_RSTCR_TIMECMP2_Pos)
21876#define HRTIM_RSTCR_TIMECMP2 HRTIM_RSTCR_TIMECMP2_Msk
21877#define HRTIM_RSTCR_TIMECMP4_Pos (30U)
21878#define HRTIM_RSTCR_TIMECMP4_Msk (0x1UL << HRTIM_RSTCR_TIMECMP4_Pos)
21879#define HRTIM_RSTCR_TIMECMP4 HRTIM_RSTCR_TIMECMP4_Msk
21881/* Slave Timer D reset enable bits upon other slave timers events */
21882#define HRTIM_RSTDR_TIMACMP1_Pos (19U)
21883#define HRTIM_RSTDR_TIMACMP1_Msk (0x1UL << HRTIM_RSTDR_TIMACMP1_Pos)
21884#define HRTIM_RSTDR_TIMACMP1 HRTIM_RSTDR_TIMACMP1_Msk
21885#define HRTIM_RSTDR_TIMACMP2_Pos (20U)
21886#define HRTIM_RSTDR_TIMACMP2_Msk (0x1UL << HRTIM_RSTDR_TIMACMP2_Pos)
21887#define HRTIM_RSTDR_TIMACMP2 HRTIM_RSTDR_TIMACMP2_Msk
21888#define HRTIM_RSTDR_TIMACMP4_Pos (21U)
21889#define HRTIM_RSTDR_TIMACMP4_Msk (0x1UL << HRTIM_RSTDR_TIMACMP4_Pos)
21890#define HRTIM_RSTDR_TIMACMP4 HRTIM_RSTDR_TIMACMP4_Msk
21892#define HRTIM_RSTDR_TIMBCMP1_Pos (22U)
21893#define HRTIM_RSTDR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP1_Pos)
21894#define HRTIM_RSTDR_TIMBCMP1 HRTIM_RSTDR_TIMBCMP1_Msk
21895#define HRTIM_RSTDR_TIMBCMP2_Pos (23U)
21896#define HRTIM_RSTDR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP2_Pos)
21897#define HRTIM_RSTDR_TIMBCMP2 HRTIM_RSTDR_TIMBCMP2_Msk
21898#define HRTIM_RSTDR_TIMBCMP4_Pos (24U)
21899#define HRTIM_RSTDR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMBCMP4_Pos)
21900#define HRTIM_RSTDR_TIMBCMP4 HRTIM_RSTDR_TIMBCMP4_Msk
21902#define HRTIM_RSTDR_TIMCCMP1_Pos (25U)
21903#define HRTIM_RSTDR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP1_Pos)
21904#define HRTIM_RSTDR_TIMCCMP1 HRTIM_RSTDR_TIMCCMP1_Msk
21905#define HRTIM_RSTDR_TIMCCMP2_Pos (26U)
21906#define HRTIM_RSTDR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP2_Pos)
21907#define HRTIM_RSTDR_TIMCCMP2 HRTIM_RSTDR_TIMCCMP2_Msk
21908#define HRTIM_RSTDR_TIMCCMP4_Pos (27U)
21909#define HRTIM_RSTDR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTDR_TIMCCMP4_Pos)
21910#define HRTIM_RSTDR_TIMCCMP4 HRTIM_RSTDR_TIMCCMP4_Msk
21912#define HRTIM_RSTDR_TIMECMP1_Pos (28U)
21913#define HRTIM_RSTDR_TIMECMP1_Msk (0x1UL << HRTIM_RSTDR_TIMECMP1_Pos)
21914#define HRTIM_RSTDR_TIMECMP1 HRTIM_RSTDR_TIMECMP1_Msk
21915#define HRTIM_RSTDR_TIMECMP2_Pos (29U)
21916#define HRTIM_RSTDR_TIMECMP2_Msk (0x1UL << HRTIM_RSTDR_TIMECMP2_Pos)
21917#define HRTIM_RSTDR_TIMECMP2 HRTIM_RSTDR_TIMECMP2_Msk
21918#define HRTIM_RSTDR_TIMECMP4_Pos (30U)
21919#define HRTIM_RSTDR_TIMECMP4_Msk (0x1UL << HRTIM_RSTDR_TIMECMP4_Pos)
21920#define HRTIM_RSTDR_TIMECMP4 HRTIM_RSTDR_TIMECMP4_Msk
21922/* Slave Timer E reset enable bits upon other slave timers events */
21923#define HRTIM_RSTER_TIMACMP1_Pos (19U)
21924#define HRTIM_RSTER_TIMACMP1_Msk (0x1UL << HRTIM_RSTER_TIMACMP1_Pos)
21925#define HRTIM_RSTER_TIMACMP1 HRTIM_RSTER_TIMACMP1_Msk
21926#define HRTIM_RSTER_TIMACMP2_Pos (20U)
21927#define HRTIM_RSTER_TIMACMP2_Msk (0x1UL << HRTIM_RSTER_TIMACMP2_Pos)
21928#define HRTIM_RSTER_TIMACMP2 HRTIM_RSTER_TIMACMP2_Msk
21929#define HRTIM_RSTER_TIMACMP4_Pos (21U)
21930#define HRTIM_RSTER_TIMACMP4_Msk (0x1UL << HRTIM_RSTER_TIMACMP4_Pos)
21931#define HRTIM_RSTER_TIMACMP4 HRTIM_RSTER_TIMACMP4_Msk
21933#define HRTIM_RSTER_TIMBCMP1_Pos (22U)
21934#define HRTIM_RSTER_TIMBCMP1_Msk (0x1UL << HRTIM_RSTER_TIMBCMP1_Pos)
21935#define HRTIM_RSTER_TIMBCMP1 HRTIM_RSTER_TIMBCMP1_Msk
21936#define HRTIM_RSTER_TIMBCMP2_Pos (23U)
21937#define HRTIM_RSTER_TIMBCMP2_Msk (0x1UL << HRTIM_RSTER_TIMBCMP2_Pos)
21938#define HRTIM_RSTER_TIMBCMP2 HRTIM_RSTER_TIMBCMP2_Msk
21939#define HRTIM_RSTER_TIMBCMP4_Pos (24U)
21940#define HRTIM_RSTER_TIMBCMP4_Msk (0x1UL << HRTIM_RSTER_TIMBCMP4_Pos)
21941#define HRTIM_RSTER_TIMBCMP4 HRTIM_RSTER_TIMBCMP4_Msk
21943#define HRTIM_RSTER_TIMCCMP1_Pos (25U)
21944#define HRTIM_RSTER_TIMCCMP1_Msk (0x1UL << HRTIM_RSTER_TIMCCMP1_Pos)
21945#define HRTIM_RSTER_TIMCCMP1 HRTIM_RSTER_TIMCCMP1_Msk
21946#define HRTIM_RSTER_TIMCCMP2_Pos (26U)
21947#define HRTIM_RSTER_TIMCCMP2_Msk (0x1UL << HRTIM_RSTER_TIMCCMP2_Pos)
21948#define HRTIM_RSTER_TIMCCMP2 HRTIM_RSTER_TIMCCMP2_Msk
21949#define HRTIM_RSTER_TIMCCMP4_Pos (27U)
21950#define HRTIM_RSTER_TIMCCMP4_Msk (0x1UL << HRTIM_RSTER_TIMCCMP4_Pos)
21951#define HRTIM_RSTER_TIMCCMP4 HRTIM_RSTER_TIMCCMP4_Msk
21953#define HRTIM_RSTER_TIMDCMP1_Pos (28U)
21954#define HRTIM_RSTER_TIMDCMP1_Msk (0x1UL << HRTIM_RSTER_TIMDCMP1_Pos)
21955#define HRTIM_RSTER_TIMDCMP1 HRTIM_RSTER_TIMDCMP1_Msk
21956#define HRTIM_RSTER_TIMDCMP2_Pos (29U)
21957#define HRTIM_RSTER_TIMDCMP2_Msk (0x1UL << HRTIM_RSTER_TIMDCMP2_Pos)
21958#define HRTIM_RSTER_TIMDCMP2 HRTIM_RSTER_TIMDCMP2_Msk
21959#define HRTIM_RSTER_TIMDCMP4_Pos (30U)
21960#define HRTIM_RSTER_TIMDCMP4_Msk (0x1UL << HRTIM_RSTER_TIMDCMP4_Pos)
21961#define HRTIM_RSTER_TIMDCMP4 HRTIM_RSTER_TIMDCMP4_Msk
21963/**** Bit definition for Slave Timer Chopper register *************************/
21964#define HRTIM_CHPR_CARFRQ_Pos (0U)
21965#define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos)
21966#define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk
21967#define HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos)
21968#define HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos)
21969#define HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos)
21970#define HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos)
21972#define HRTIM_CHPR_CARDTY_Pos (4U)
21973#define HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos)
21974#define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk
21975#define HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos)
21976#define HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos)
21977#define HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos)
21979#define HRTIM_CHPR_STRPW_Pos (7U)
21980#define HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos)
21981#define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk
21982#define HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos)
21983#define HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos)
21984#define HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos)
21985#define HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos)
21987/**** Bit definition for Slave Timer Capture 1 control register ***************/
21988#define HRTIM_CPT1CR_SWCPT_Pos (0U)
21989#define HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)
21990#define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk
21991#define HRTIM_CPT1CR_UPDCPT_Pos (1U)
21992#define HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)
21993#define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk
21994#define HRTIM_CPT1CR_EXEV1CPT_Pos (2U)
21995#define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)
21996#define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk
21997#define HRTIM_CPT1CR_EXEV2CPT_Pos (3U)
21998#define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)
21999#define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk
22000#define HRTIM_CPT1CR_EXEV3CPT_Pos (4U)
22001#define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)
22002#define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk
22003#define HRTIM_CPT1CR_EXEV4CPT_Pos (5U)
22004#define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)
22005#define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk
22006#define HRTIM_CPT1CR_EXEV5CPT_Pos (6U)
22007#define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)
22008#define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk
22009#define HRTIM_CPT1CR_EXEV6CPT_Pos (7U)
22010#define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)
22011#define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk
22012#define HRTIM_CPT1CR_EXEV7CPT_Pos (8U)
22013#define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)
22014#define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk
22015#define HRTIM_CPT1CR_EXEV8CPT_Pos (9U)
22016#define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)
22017#define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk
22018#define HRTIM_CPT1CR_EXEV9CPT_Pos (10U)
22019#define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)
22020#define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk
22021#define HRTIM_CPT1CR_EXEV10CPT_Pos (11U)
22022#define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)
22023#define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk
22025#define HRTIM_CPT1CR_TA1SET_Pos (12U)
22026#define HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)
22027#define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk
22028#define HRTIM_CPT1CR_TA1RST_Pos (13U)
22029#define HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)
22030#define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk
22031#define HRTIM_CPT1CR_TIMACMP1_Pos (14U)
22032#define HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)
22033#define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk
22034#define HRTIM_CPT1CR_TIMACMP2_Pos (15U)
22035#define HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)
22036#define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk
22038#define HRTIM_CPT1CR_TB1SET_Pos (16U)
22039#define HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)
22040#define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk
22041#define HRTIM_CPT1CR_TB1RST_Pos (17U)
22042#define HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)
22043#define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk
22044#define HRTIM_CPT1CR_TIMBCMP1_Pos (18U)
22045#define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)
22046#define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk
22047#define HRTIM_CPT1CR_TIMBCMP2_Pos (19U)
22048#define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)
22049#define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk
22051#define HRTIM_CPT1CR_TC1SET_Pos (20U)
22052#define HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)
22053#define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk
22054#define HRTIM_CPT1CR_TC1RST_Pos (21U)
22055#define HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)
22056#define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk
22057#define HRTIM_CPT1CR_TIMCCMP1_Pos (22U)
22058#define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)
22059#define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk
22060#define HRTIM_CPT1CR_TIMCCMP2_Pos (23U)
22061#define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)
22062#define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk
22064#define HRTIM_CPT1CR_TD1SET_Pos (24U)
22065#define HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)
22066#define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk
22067#define HRTIM_CPT1CR_TD1RST_Pos (25U)
22068#define HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)
22069#define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk
22070#define HRTIM_CPT1CR_TIMDCMP1_Pos (26U)
22071#define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)
22072#define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk
22073#define HRTIM_CPT1CR_TIMDCMP2_Pos (27U)
22074#define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)
22075#define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk
22077#define HRTIM_CPT1CR_TE1SET_Pos (28U)
22078#define HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)
22079#define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk
22080#define HRTIM_CPT1CR_TE1RST_Pos (29U)
22081#define HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)
22082#define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk
22083#define HRTIM_CPT1CR_TIMECMP1_Pos (30U)
22084#define HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)
22085#define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk
22086#define HRTIM_CPT1CR_TIMECMP2_Pos (31U)
22087#define HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)
22088#define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk
22090/**** Bit definition for Slave Timer Capture 2 control register ***************/
22091#define HRTIM_CPT2CR_SWCPT_Pos (0U)
22092#define HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)
22093#define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk
22094#define HRTIM_CPT2CR_UPDCPT_Pos (1U)
22095#define HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)
22096#define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk
22097#define HRTIM_CPT2CR_EXEV1CPT_Pos (2U)
22098#define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)
22099#define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk
22100#define HRTIM_CPT2CR_EXEV2CPT_Pos (3U)
22101#define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)
22102#define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk
22103#define HRTIM_CPT2CR_EXEV3CPT_Pos (4U)
22104#define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)
22105#define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk
22106#define HRTIM_CPT2CR_EXEV4CPT_Pos (5U)
22107#define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)
22108#define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk
22109#define HRTIM_CPT2CR_EXEV5CPT_Pos (6U)
22110#define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)
22111#define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk
22112#define HRTIM_CPT2CR_EXEV6CPT_Pos (7U)
22113#define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)
22114#define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk
22115#define HRTIM_CPT2CR_EXEV7CPT_Pos (8U)
22116#define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)
22117#define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk
22118#define HRTIM_CPT2CR_EXEV8CPT_Pos (9U)
22119#define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)
22120#define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk
22121#define HRTIM_CPT2CR_EXEV9CPT_Pos (10U)
22122#define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)
22123#define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk
22124#define HRTIM_CPT2CR_EXEV10CPT_Pos (11U)
22125#define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)
22126#define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk
22128#define HRTIM_CPT2CR_TA1SET_Pos (12U)
22129#define HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)
22130#define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk
22131#define HRTIM_CPT2CR_TA1RST_Pos (13U)
22132#define HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)
22133#define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk
22134#define HRTIM_CPT2CR_TIMACMP1_Pos (14U)
22135#define HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)
22136#define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk
22137#define HRTIM_CPT2CR_TIMACMP2_Pos (15U)
22138#define HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)
22139#define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk
22141#define HRTIM_CPT2CR_TB1SET_Pos (16U)
22142#define HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)
22143#define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk
22144#define HRTIM_CPT2CR_TB1RST_Pos (17U)
22145#define HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)
22146#define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk
22147#define HRTIM_CPT2CR_TIMBCMP1_Pos (18U)
22148#define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)
22149#define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk
22150#define HRTIM_CPT2CR_TIMBCMP2_Pos (19U)
22151#define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)
22152#define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk
22154#define HRTIM_CPT2CR_TC1SET_Pos (20U)
22155#define HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)
22156#define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk
22157#define HRTIM_CPT2CR_TC1RST_Pos (21U)
22158#define HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)
22159#define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk
22160#define HRTIM_CPT2CR_TIMCCMP1_Pos (22U)
22161#define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)
22162#define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk
22163#define HRTIM_CPT2CR_TIMCCMP2_Pos (23U)
22164#define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)
22165#define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk
22167#define HRTIM_CPT2CR_TD1SET_Pos (24U)
22168#define HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)
22169#define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk
22170#define HRTIM_CPT2CR_TD1RST_Pos (25U)
22171#define HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)
22172#define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk
22173#define HRTIM_CPT2CR_TIMDCMP1_Pos (26U)
22174#define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)
22175#define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk
22176#define HRTIM_CPT2CR_TIMDCMP2_Pos (27U)
22177#define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)
22178#define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk
22180#define HRTIM_CPT2CR_TE1SET_Pos (28U)
22181#define HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)
22182#define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk
22183#define HRTIM_CPT2CR_TE1RST_Pos (29U)
22184#define HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)
22185#define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk
22186#define HRTIM_CPT2CR_TIMECMP1_Pos (30U)
22187#define HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)
22188#define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk
22189#define HRTIM_CPT2CR_TIMECMP2_Pos (31U)
22190#define HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)
22191#define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk
22193/**** Bit definition for Slave Timer Output register **************************/
22194#define HRTIM_OUTR_POL1_Pos (1U)
22195#define HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos)
22196#define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk
22197#define HRTIM_OUTR_IDLM1_Pos (2U)
22198#define HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos)
22199#define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk
22200#define HRTIM_OUTR_IDLES1_Pos (3U)
22201#define HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos)
22202#define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk
22203#define HRTIM_OUTR_FAULT1_Pos (4U)
22204#define HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos)
22205#define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk
22206#define HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos)
22207#define HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos)
22208#define HRTIM_OUTR_CHP1_Pos (6U)
22209#define HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos)
22210#define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk
22211#define HRTIM_OUTR_DIDL1_Pos (7U)
22212#define HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos)
22213#define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk
22215#define HRTIM_OUTR_DTEN_Pos (8U)
22216#define HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos)
22217#define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk
22218#define HRTIM_OUTR_DLYPRTEN_Pos (9U)
22219#define HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)
22220#define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk
22221#define HRTIM_OUTR_DLYPRT_Pos (10U)
22222#define HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos)
22223#define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk
22224#define HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos)
22225#define HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos)
22226#define HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos)
22228#define HRTIM_OUTR_POL2_Pos (17U)
22229#define HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos)
22230#define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk
22231#define HRTIM_OUTR_IDLM2_Pos (18U)
22232#define HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos)
22233#define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk
22234#define HRTIM_OUTR_IDLES2_Pos (19U)
22235#define HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos)
22236#define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk
22237#define HRTIM_OUTR_FAULT2_Pos (20U)
22238#define HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos)
22239#define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk
22240#define HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos)
22241#define HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos)
22242#define HRTIM_OUTR_CHP2_Pos (22U)
22243#define HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos)
22244#define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk
22245#define HRTIM_OUTR_DIDL2_Pos (23U)
22246#define HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos)
22247#define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk
22249/**** Bit definition for Slave Timer Fault register ***************************/
22250#define HRTIM_FLTR_FLT1EN_Pos (0U)
22251#define HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos)
22252#define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk
22253#define HRTIM_FLTR_FLT2EN_Pos (1U)
22254#define HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos)
22255#define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk
22256#define HRTIM_FLTR_FLT3EN_Pos (2U)
22257#define HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos)
22258#define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk
22259#define HRTIM_FLTR_FLT4EN_Pos (3U)
22260#define HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos)
22261#define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk
22262#define HRTIM_FLTR_FLT5EN_Pos (4U)
22263#define HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos)
22264#define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk
22265#define HRTIM_FLTR_FLTLCK_Pos (31U)
22266#define HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos)
22267#define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk
22269/**** Bit definition for Common HRTIM Timer control register 1 ****************/
22270#define HRTIM_CR1_MUDIS_Pos (0U)
22271#define HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos)
22272#define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk
22273#define HRTIM_CR1_TAUDIS_Pos (1U)
22274#define HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos)
22275#define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk
22276#define HRTIM_CR1_TBUDIS_Pos (2U)
22277#define HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos)
22278#define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk
22279#define HRTIM_CR1_TCUDIS_Pos (3U)
22280#define HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos)
22281#define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk
22282#define HRTIM_CR1_TDUDIS_Pos (4U)
22283#define HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos)
22284#define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk
22285#define HRTIM_CR1_TEUDIS_Pos (5U)
22286#define HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos)
22287#define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk
22288#define HRTIM_CR1_ADC1USRC_Pos (16U)
22289#define HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos)
22290#define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk
22291#define HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos)
22292#define HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos)
22293#define HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos)
22294#define HRTIM_CR1_ADC2USRC_Pos (19U)
22295#define HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos)
22296#define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk
22297#define HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos)
22298#define HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos)
22299#define HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos)
22300#define HRTIM_CR1_ADC3USRC_Pos (22U)
22301#define HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos)
22302#define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk
22303#define HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos)
22304#define HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos)
22305#define HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos)
22306#define HRTIM_CR1_ADC4USRC_Pos (25U)
22307#define HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos)
22308#define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk
22309#define HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos)
22310#define HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos)
22311#define HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos)
22313/**** Bit definition for Common HRTIM Timer control register 2 ****************/
22314#define HRTIM_CR2_MSWU_Pos (0U)
22315#define HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos)
22316#define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk
22317#define HRTIM_CR2_TASWU_Pos (1U)
22318#define HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos)
22319#define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk
22320#define HRTIM_CR2_TBSWU_Pos (2U)
22321#define HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos)
22322#define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk
22323#define HRTIM_CR2_TCSWU_Pos (3U)
22324#define HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos)
22325#define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk
22326#define HRTIM_CR2_TDSWU_Pos (4U)
22327#define HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos)
22328#define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk
22329#define HRTIM_CR2_TESWU_Pos (5U)
22330#define HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos)
22331#define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk
22332#define HRTIM_CR2_MRST_Pos (8U)
22333#define HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos)
22334#define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk
22335#define HRTIM_CR2_TARST_Pos (9U)
22336#define HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos)
22337#define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk
22338#define HRTIM_CR2_TBRST_Pos (10U)
22339#define HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos)
22340#define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk
22341#define HRTIM_CR2_TCRST_Pos (11U)
22342#define HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos)
22343#define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk
22344#define HRTIM_CR2_TDRST_Pos (12U)
22345#define HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos)
22346#define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk
22347#define HRTIM_CR2_TERST_Pos (13U)
22348#define HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos)
22349#define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk
22351/**** Bit definition for Common HRTIM Timer interrupt status register *********/
22352#define HRTIM_ISR_FLT1_Pos (0U)
22353#define HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos)
22354#define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk
22355#define HRTIM_ISR_FLT2_Pos (1U)
22356#define HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos)
22357#define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk
22358#define HRTIM_ISR_FLT3_Pos (2U)
22359#define HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos)
22360#define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk
22361#define HRTIM_ISR_FLT4_Pos (3U)
22362#define HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos)
22363#define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk
22364#define HRTIM_ISR_FLT5_Pos (4U)
22365#define HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos)
22366#define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk
22367#define HRTIM_ISR_SYSFLT_Pos (5U)
22368#define HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos)
22369#define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk
22370#define HRTIM_ISR_BMPER_Pos (17U)
22371#define HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos)
22372#define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk
22374/**** Bit definition for Common HRTIM Timer interrupt clear register **********/
22375#define HRTIM_ICR_FLT1C_Pos (0U)
22376#define HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos)
22377#define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk
22378#define HRTIM_ICR_FLT2C_Pos (1U)
22379#define HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos)
22380#define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk
22381#define HRTIM_ICR_FLT3C_Pos (2U)
22382#define HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos)
22383#define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk
22384#define HRTIM_ICR_FLT4C_Pos (3U)
22385#define HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos)
22386#define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk
22387#define HRTIM_ICR_FLT5C_Pos (4U)
22388#define HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos)
22389#define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk
22390#define HRTIM_ICR_SYSFLTC_Pos (5U)
22391#define HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos)
22392#define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk
22393#define HRTIM_ICR_BMPERC_Pos (17U)
22394#define HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos)
22395#define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk
22397/**** Bit definition for Common HRTIM Timer interrupt enable register *********/
22398#define HRTIM_IER_FLT1_Pos (0U)
22399#define HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos)
22400#define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk
22401#define HRTIM_IER_FLT2_Pos (1U)
22402#define HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos)
22403#define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk
22404#define HRTIM_IER_FLT3_Pos (2U)
22405#define HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos)
22406#define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk
22407#define HRTIM_IER_FLT4_Pos (3U)
22408#define HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos)
22409#define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk
22410#define HRTIM_IER_FLT5_Pos (4U)
22411#define HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos)
22412#define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk
22413#define HRTIM_IER_SYSFLT_Pos (5U)
22414#define HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos)
22415#define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk
22416#define HRTIM_IER_BMPER_Pos (17U)
22417#define HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos)
22418#define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk
22420/**** Bit definition for Common HRTIM Timer output enable register ************/
22421#define HRTIM_OENR_TA1OEN_Pos (0U)
22422#define HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos)
22423#define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk
22424#define HRTIM_OENR_TA2OEN_Pos (1U)
22425#define HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos)
22426#define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk
22427#define HRTIM_OENR_TB1OEN_Pos (2U)
22428#define HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos)
22429#define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk
22430#define HRTIM_OENR_TB2OEN_Pos (3U)
22431#define HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos)
22432#define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk
22433#define HRTIM_OENR_TC1OEN_Pos (4U)
22434#define HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos)
22435#define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk
22436#define HRTIM_OENR_TC2OEN_Pos (5U)
22437#define HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos)
22438#define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk
22439#define HRTIM_OENR_TD1OEN_Pos (6U)
22440#define HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos)
22441#define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk
22442#define HRTIM_OENR_TD2OEN_Pos (7U)
22443#define HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos)
22444#define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk
22445#define HRTIM_OENR_TE1OEN_Pos (8U)
22446#define HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos)
22447#define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk
22448#define HRTIM_OENR_TE2OEN_Pos (9U)
22449#define HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos)
22450#define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk
22452/**** Bit definition for Common HRTIM Timer output disable register ***********/
22453#define HRTIM_ODISR_TA1ODIS_Pos (0U)
22454#define HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)
22455#define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk
22456#define HRTIM_ODISR_TA2ODIS_Pos (1U)
22457#define HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)
22458#define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk
22459#define HRTIM_ODISR_TB1ODIS_Pos (2U)
22460#define HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)
22461#define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk
22462#define HRTIM_ODISR_TB2ODIS_Pos (3U)
22463#define HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)
22464#define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk
22465#define HRTIM_ODISR_TC1ODIS_Pos (4U)
22466#define HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)
22467#define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk
22468#define HRTIM_ODISR_TC2ODIS_Pos (5U)
22469#define HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)
22470#define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk
22471#define HRTIM_ODISR_TD1ODIS_Pos (6U)
22472#define HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)
22473#define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk
22474#define HRTIM_ODISR_TD2ODIS_Pos (7U)
22475#define HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)
22476#define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk
22477#define HRTIM_ODISR_TE1ODIS_Pos (8U)
22478#define HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)
22479#define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk
22480#define HRTIM_ODISR_TE2ODIS_Pos (9U)
22481#define HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)
22482#define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk
22484/**** Bit definition for Common HRTIM Timer output disable status register *****/
22485#define HRTIM_ODSR_TA1ODS_Pos (0U)
22486#define HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos)
22487#define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk
22488#define HRTIM_ODSR_TA2ODS_Pos (1U)
22489#define HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos)
22490#define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk
22491#define HRTIM_ODSR_TB1ODS_Pos (2U)
22492#define HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos)
22493#define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk
22494#define HRTIM_ODSR_TB2ODS_Pos (3U)
22495#define HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos)
22496#define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk
22497#define HRTIM_ODSR_TC1ODS_Pos (4U)
22498#define HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos)
22499#define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk
22500#define HRTIM_ODSR_TC2ODS_Pos (5U)
22501#define HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos)
22502#define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk
22503#define HRTIM_ODSR_TD1ODS_Pos (6U)
22504#define HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos)
22505#define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk
22506#define HRTIM_ODSR_TD2ODS_Pos (7U)
22507#define HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos)
22508#define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk
22509#define HRTIM_ODSR_TE1ODS_Pos (8U)
22510#define HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos)
22511#define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk
22512#define HRTIM_ODSR_TE2ODS_Pos (9U)
22513#define HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos)
22514#define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk
22516/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
22517#define HRTIM_BMCR_BME_Pos (0U)
22518#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos)
22519#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk
22520#define HRTIM_BMCR_BMOM_Pos (1U)
22521#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos)
22522#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk
22523#define HRTIM_BMCR_BMCLK_Pos (2U)
22524#define HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos)
22525#define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk
22526#define HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos)
22527#define HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos)
22528#define HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos)
22529#define HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos)
22530#define HRTIM_BMCR_BMPRSC_Pos (6U)
22531#define HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos)
22532#define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk
22533#define HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos)
22534#define HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos)
22535#define HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos)
22536#define HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos)
22537#define HRTIM_BMCR_BMPREN_Pos (10U)
22538#define HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos)
22539#define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk
22540#define HRTIM_BMCR_MTBM_Pos (16U)
22541#define HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos)
22542#define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk
22543#define HRTIM_BMCR_TABM_Pos (17U)
22544#define HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos)
22545#define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk
22546#define HRTIM_BMCR_TBBM_Pos (18U)
22547#define HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos)
22548#define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk
22549#define HRTIM_BMCR_TCBM_Pos (19U)
22550#define HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos)
22551#define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk
22552#define HRTIM_BMCR_TDBM_Pos (20U)
22553#define HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos)
22554#define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk
22555#define HRTIM_BMCR_TEBM_Pos (21U)
22556#define HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos)
22557#define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk
22558#define HRTIM_BMCR_BMSTAT_Pos (31U)
22559#define HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos)
22560#define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk
22562/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
22563#define HRTIM_BMTRGR_SW_Pos (0U)
22564#define HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos)
22565#define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk
22566#define HRTIM_BMTRGR_MSTRST_Pos (1U)
22567#define HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)
22568#define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk
22569#define HRTIM_BMTRGR_MSTREP_Pos (2U)
22570#define HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)
22571#define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk
22572#define HRTIM_BMTRGR_MSTCMP1_Pos (3U)
22573#define HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)
22574#define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk
22575#define HRTIM_BMTRGR_MSTCMP2_Pos (4U)
22576#define HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)
22577#define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk
22578#define HRTIM_BMTRGR_MSTCMP3_Pos (5U)
22579#define HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)
22580#define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk
22581#define HRTIM_BMTRGR_MSTCMP4_Pos (6U)
22582#define HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)
22583#define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk
22584#define HRTIM_BMTRGR_TARST_Pos (7U)
22585#define HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos)
22586#define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk
22587#define HRTIM_BMTRGR_TAREP_Pos (8U)
22588#define HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos)
22589#define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk
22590#define HRTIM_BMTRGR_TACMP1_Pos (9U)
22591#define HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)
22592#define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk
22593#define HRTIM_BMTRGR_TACMP2_Pos (10U)
22594#define HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)
22595#define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk
22596#define HRTIM_BMTRGR_TBRST_Pos (11U)
22597#define HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos)
22598#define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk
22599#define HRTIM_BMTRGR_TBREP_Pos (12U)
22600#define HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos)
22601#define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk
22602#define HRTIM_BMTRGR_TBCMP1_Pos (13U)
22603#define HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)
22604#define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk
22605#define HRTIM_BMTRGR_TBCMP2_Pos (14U)
22606#define HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)
22607#define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk
22608#define HRTIM_BMTRGR_TCRST_Pos (15U)
22609#define HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos)
22610#define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk
22611#define HRTIM_BMTRGR_TCREP_Pos (16U)
22612#define HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos)
22613#define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk
22614#define HRTIM_BMTRGR_TCCMP1_Pos (17U)
22615#define HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)
22616#define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk
22617#define HRTIM_BMTRGR_TCCMP2_Pos (18U)
22618#define HRTIM_BMTRGR_TCCMP2_Msk (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)
22619#define HRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk
22620#define HRTIM_BMTRGR_TDRST_Pos (19U)
22621#define HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos)
22622#define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk
22623#define HRTIM_BMTRGR_TDREP_Pos (20U)
22624#define HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos)
22625#define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk
22626#define HRTIM_BMTRGR_TDCMP1_Pos (21U)
22627#define HRTIM_BMTRGR_TDCMP1_Msk (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)
22628#define HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk
22629#define HRTIM_BMTRGR_TDCMP2_Pos (22U)
22630#define HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)
22631#define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk
22632#define HRTIM_BMTRGR_TERST_Pos (23U)
22633#define HRTIM_BMTRGR_TERST_Msk (0x1UL << HRTIM_BMTRGR_TERST_Pos)
22634#define HRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk
22635#define HRTIM_BMTRGR_TEREP_Pos (24U)
22636#define HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos)
22637#define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk
22638#define HRTIM_BMTRGR_TECMP1_Pos (25U)
22639#define HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)
22640#define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk
22641#define HRTIM_BMTRGR_TECMP2_Pos (26U)
22642#define HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)
22643#define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk
22644#define HRTIM_BMTRGR_TAEEV7_Pos (27U)
22645#define HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)
22646#define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk
22647#define HRTIM_BMTRGR_TDEEV8_Pos (28U)
22648#define HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)
22649#define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk
22650#define HRTIM_BMTRGR_EEV7_Pos (29U)
22651#define HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos)
22652#define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk
22653#define HRTIM_BMTRGR_EEV8_Pos (30U)
22654#define HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos)
22655#define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk
22656#define HRTIM_BMTRGR_OCHPEV_Pos (31U)
22657#define HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)
22658#define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk
22660/******************* Bit definition for HRTIM_BMCMPR register ***************/
22661#define HRTIM_BMCMPR_BMCMPR_Pos (0U)
22662#define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)
22663#define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk
22665/******************* Bit definition for HRTIM_BMPER register ****************/
22666#define HRTIM_BMPER_BMPER_Pos (0U)
22667#define HRTIM_BMPER_BMPER_Msk (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)
22668#define HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk
22670/******************* Bit definition for HRTIM_EECR1 register ****************/
22671#define HRTIM_EECR1_EE1SRC_Pos (0U)
22672#define HRTIM_EECR1_EE1SRC_Msk (0x3UL << HRTIM_EECR1_EE1SRC_Pos)
22673#define HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk
22674#define HRTIM_EECR1_EE1SRC_0 (0x1UL << HRTIM_EECR1_EE1SRC_Pos)
22675#define HRTIM_EECR1_EE1SRC_1 (0x2UL << HRTIM_EECR1_EE1SRC_Pos)
22676#define HRTIM_EECR1_EE1POL_Pos (2U)
22677#define HRTIM_EECR1_EE1POL_Msk (0x1UL << HRTIM_EECR1_EE1POL_Pos)
22678#define HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk
22679#define HRTIM_EECR1_EE1SNS_Pos (3U)
22680#define HRTIM_EECR1_EE1SNS_Msk (0x3UL << HRTIM_EECR1_EE1SNS_Pos)
22681#define HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk
22682#define HRTIM_EECR1_EE1SNS_0 (0x1UL << HRTIM_EECR1_EE1SNS_Pos)
22683#define HRTIM_EECR1_EE1SNS_1 (0x2UL << HRTIM_EECR1_EE1SNS_Pos)
22684#define HRTIM_EECR1_EE1FAST_Pos (5U)
22685#define HRTIM_EECR1_EE1FAST_Msk (0x1UL << HRTIM_EECR1_EE1FAST_Pos)
22686#define HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk
22688#define HRTIM_EECR1_EE2SRC_Pos (6U)
22689#define HRTIM_EECR1_EE2SRC_Msk (0x3UL << HRTIM_EECR1_EE2SRC_Pos)
22690#define HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk
22691#define HRTIM_EECR1_EE2SRC_0 (0x1UL << HRTIM_EECR1_EE2SRC_Pos)
22692#define HRTIM_EECR1_EE2SRC_1 (0x2UL << HRTIM_EECR1_EE2SRC_Pos)
22693#define HRTIM_EECR1_EE2POL_Pos (8U)
22694#define HRTIM_EECR1_EE2POL_Msk (0x1UL << HRTIM_EECR1_EE2POL_Pos)
22695#define HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk
22696#define HRTIM_EECR1_EE2SNS_Pos (9U)
22697#define HRTIM_EECR1_EE2SNS_Msk (0x3UL << HRTIM_EECR1_EE2SNS_Pos)
22698#define HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk
22699#define HRTIM_EECR1_EE2SNS_0 (0x1UL << HRTIM_EECR1_EE2SNS_Pos)
22700#define HRTIM_EECR1_EE2SNS_1 (0x2UL << HRTIM_EECR1_EE2SNS_Pos)
22701#define HRTIM_EECR1_EE2FAST_Pos (11U)
22702#define HRTIM_EECR1_EE2FAST_Msk (0x1UL << HRTIM_EECR1_EE2FAST_Pos)
22703#define HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk
22705#define HRTIM_EECR1_EE3SRC_Pos (12U)
22706#define HRTIM_EECR1_EE3SRC_Msk (0x3UL << HRTIM_EECR1_EE3SRC_Pos)
22707#define HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk
22708#define HRTIM_EECR1_EE3SRC_0 (0x1UL << HRTIM_EECR1_EE3SRC_Pos)
22709#define HRTIM_EECR1_EE3SRC_1 (0x2UL << HRTIM_EECR1_EE3SRC_Pos)
22710#define HRTIM_EECR1_EE3POL_Pos (14U)
22711#define HRTIM_EECR1_EE3POL_Msk (0x1UL << HRTIM_EECR1_EE3POL_Pos)
22712#define HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk
22713#define HRTIM_EECR1_EE3SNS_Pos (15U)
22714#define HRTIM_EECR1_EE3SNS_Msk (0x3UL << HRTIM_EECR1_EE3SNS_Pos)
22715#define HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk
22716#define HRTIM_EECR1_EE3SNS_0 (0x1UL << HRTIM_EECR1_EE3SNS_Pos)
22717#define HRTIM_EECR1_EE3SNS_1 (0x2UL << HRTIM_EECR1_EE3SNS_Pos)
22718#define HRTIM_EECR1_EE3FAST_Pos (17U)
22719#define HRTIM_EECR1_EE3FAST_Msk (0x1UL << HRTIM_EECR1_EE3FAST_Pos)
22720#define HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk
22722#define HRTIM_EECR1_EE4SRC_Pos (18U)
22723#define HRTIM_EECR1_EE4SRC_Msk (0x3UL << HRTIM_EECR1_EE4SRC_Pos)
22724#define HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk
22725#define HRTIM_EECR1_EE4SRC_0 (0x1UL << HRTIM_EECR1_EE4SRC_Pos)
22726#define HRTIM_EECR1_EE4SRC_1 (0x2UL << HRTIM_EECR1_EE4SRC_Pos)
22727#define HRTIM_EECR1_EE4POL_Pos (20U)
22728#define HRTIM_EECR1_EE4POL_Msk (0x1UL << HRTIM_EECR1_EE4POL_Pos)
22729#define HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk
22730#define HRTIM_EECR1_EE4SNS_Pos (21U)
22731#define HRTIM_EECR1_EE4SNS_Msk (0x3UL << HRTIM_EECR1_EE4SNS_Pos)
22732#define HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk
22733#define HRTIM_EECR1_EE4SNS_0 (0x1UL << HRTIM_EECR1_EE4SNS_Pos)
22734#define HRTIM_EECR1_EE4SNS_1 (0x2UL << HRTIM_EECR1_EE4SNS_Pos)
22735#define HRTIM_EECR1_EE4FAST_Pos (23U)
22736#define HRTIM_EECR1_EE4FAST_Msk (0x1UL << HRTIM_EECR1_EE4FAST_Pos)
22737#define HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk
22739#define HRTIM_EECR1_EE5SRC_Pos (24U)
22740#define HRTIM_EECR1_EE5SRC_Msk (0x3UL << HRTIM_EECR1_EE5SRC_Pos)
22741#define HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk
22742#define HRTIM_EECR1_EE5SRC_0 (0x1UL << HRTIM_EECR1_EE5SRC_Pos)
22743#define HRTIM_EECR1_EE5SRC_1 (0x2UL << HRTIM_EECR1_EE5SRC_Pos)
22744#define HRTIM_EECR1_EE5POL_Pos (26U)
22745#define HRTIM_EECR1_EE5POL_Msk (0x1UL << HRTIM_EECR1_EE5POL_Pos)
22746#define HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk
22747#define HRTIM_EECR1_EE5SNS_Pos (27U)
22748#define HRTIM_EECR1_EE5SNS_Msk (0x3UL << HRTIM_EECR1_EE5SNS_Pos)
22749#define HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk
22750#define HRTIM_EECR1_EE5SNS_0 (0x1UL << HRTIM_EECR1_EE5SNS_Pos)
22751#define HRTIM_EECR1_EE5SNS_1 (0x2UL << HRTIM_EECR1_EE5SNS_Pos)
22752#define HRTIM_EECR1_EE5FAST_Pos (29U)
22753#define HRTIM_EECR1_EE5FAST_Msk (0x1UL << HRTIM_EECR1_EE5FAST_Pos)
22754#define HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk
22756/******************* Bit definition for HRTIM_EECR2 register ****************/
22757#define HRTIM_EECR2_EE6SRC_Pos (0U)
22758#define HRTIM_EECR2_EE6SRC_Msk (0x3UL << HRTIM_EECR2_EE6SRC_Pos)
22759#define HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk
22760#define HRTIM_EECR2_EE6SRC_0 (0x1UL << HRTIM_EECR2_EE6SRC_Pos)
22761#define HRTIM_EECR2_EE6SRC_1 (0x2UL << HRTIM_EECR2_EE6SRC_Pos)
22762#define HRTIM_EECR2_EE6POL_Pos (2U)
22763#define HRTIM_EECR2_EE6POL_Msk (0x1UL << HRTIM_EECR2_EE6POL_Pos)
22764#define HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk
22765#define HRTIM_EECR2_EE6SNS_Pos (3U)
22766#define HRTIM_EECR2_EE6SNS_Msk (0x3UL << HRTIM_EECR2_EE6SNS_Pos)
22767#define HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk
22768#define HRTIM_EECR2_EE6SNS_0 (0x1UL << HRTIM_EECR2_EE6SNS_Pos)
22769#define HRTIM_EECR2_EE6SNS_1 (0x2UL << HRTIM_EECR2_EE6SNS_Pos)
22771#define HRTIM_EECR2_EE7SRC_Pos (6U)
22772#define HRTIM_EECR2_EE7SRC_Msk (0x3UL << HRTIM_EECR2_EE7SRC_Pos)
22773#define HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk
22774#define HRTIM_EECR2_EE7SRC_0 (0x1UL << HRTIM_EECR2_EE7SRC_Pos)
22775#define HRTIM_EECR2_EE7SRC_1 (0x2UL << HRTIM_EECR2_EE7SRC_Pos)
22776#define HRTIM_EECR2_EE7POL_Pos (8U)
22777#define HRTIM_EECR2_EE7POL_Msk (0x1UL << HRTIM_EECR2_EE7POL_Pos)
22778#define HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk
22779#define HRTIM_EECR2_EE7SNS_Pos (9U)
22780#define HRTIM_EECR2_EE7SNS_Msk (0x3UL << HRTIM_EECR2_EE7SNS_Pos)
22781#define HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk
22782#define HRTIM_EECR2_EE7SNS_0 (0x1UL << HRTIM_EECR2_EE7SNS_Pos)
22783#define HRTIM_EECR2_EE7SNS_1 (0x2UL << HRTIM_EECR2_EE7SNS_Pos)
22785#define HRTIM_EECR2_EE8SRC_Pos (12U)
22786#define HRTIM_EECR2_EE8SRC_Msk (0x3UL << HRTIM_EECR2_EE8SRC_Pos)
22787#define HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk
22788#define HRTIM_EECR2_EE8SRC_0 (0x1UL << HRTIM_EECR2_EE8SRC_Pos)
22789#define HRTIM_EECR2_EE8SRC_1 (0x2UL << HRTIM_EECR2_EE8SRC_Pos)
22790#define HRTIM_EECR2_EE8POL_Pos (14U)
22791#define HRTIM_EECR2_EE8POL_Msk (0x1UL << HRTIM_EECR2_EE8POL_Pos)
22792#define HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk
22793#define HRTIM_EECR2_EE8SNS_Pos (15U)
22794#define HRTIM_EECR2_EE8SNS_Msk (0x3UL << HRTIM_EECR2_EE8SNS_Pos)
22795#define HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk
22796#define HRTIM_EECR2_EE8SNS_0 (0x1UL << HRTIM_EECR2_EE8SNS_Pos)
22797#define HRTIM_EECR2_EE8SNS_1 (0x2UL << HRTIM_EECR2_EE8SNS_Pos)
22799#define HRTIM_EECR2_EE9SRC_Pos (18U)
22800#define HRTIM_EECR2_EE9SRC_Msk (0x3UL << HRTIM_EECR2_EE9SRC_Pos)
22801#define HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk
22802#define HRTIM_EECR2_EE9SRC_0 (0x1UL << HRTIM_EECR2_EE9SRC_Pos)
22803#define HRTIM_EECR2_EE9SRC_1 (0x2UL << HRTIM_EECR2_EE9SRC_Pos)
22804#define HRTIM_EECR2_EE9POL_Pos (20U)
22805#define HRTIM_EECR2_EE9POL_Msk (0x1UL << HRTIM_EECR2_EE9POL_Pos)
22806#define HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk
22807#define HRTIM_EECR2_EE9SNS_Pos (21U)
22808#define HRTIM_EECR2_EE9SNS_Msk (0x3UL << HRTIM_EECR2_EE9SNS_Pos)
22809#define HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk
22810#define HRTIM_EECR2_EE9SNS_0 (0x1UL << HRTIM_EECR2_EE9SNS_Pos)
22811#define HRTIM_EECR2_EE9SNS_1 (0x2UL << HRTIM_EECR2_EE9SNS_Pos)
22813#define HRTIM_EECR2_EE10SRC_Pos (24U)
22814#define HRTIM_EECR2_EE10SRC_Msk (0x3UL << HRTIM_EECR2_EE10SRC_Pos)
22815#define HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk
22816#define HRTIM_EECR2_EE10SRC_0 (0x1UL << HRTIM_EECR2_EE10SRC_Pos)
22817#define HRTIM_EECR2_EE10SRC_1 (0x2UL << HRTIM_EECR2_EE10SRC_Pos)
22818#define HRTIM_EECR2_EE10POL_Pos (26U)
22819#define HRTIM_EECR2_EE10POL_Msk (0x1UL << HRTIM_EECR2_EE10POL_Pos)
22820#define HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk
22821#define HRTIM_EECR2_EE10SNS_Pos (27U)
22822#define HRTIM_EECR2_EE10SNS_Msk (0x3UL << HRTIM_EECR2_EE10SNS_Pos)
22823#define HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk
22824#define HRTIM_EECR2_EE10SNS_0 (0x1UL << HRTIM_EECR2_EE10SNS_Pos)
22825#define HRTIM_EECR2_EE10SNS_1 (0x2UL << HRTIM_EECR2_EE10SNS_Pos)
22827/******************* Bit definition for HRTIM_EECR3 register ****************/
22828#define HRTIM_EECR3_EE6F_Pos (0U)
22829#define HRTIM_EECR3_EE6F_Msk (0xFUL << HRTIM_EECR3_EE6F_Pos)
22830#define HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk
22831#define HRTIM_EECR3_EE6F_0 (0x1UL << HRTIM_EECR3_EE6F_Pos)
22832#define HRTIM_EECR3_EE6F_1 (0x2UL << HRTIM_EECR3_EE6F_Pos)
22833#define HRTIM_EECR3_EE6F_2 (0x4UL << HRTIM_EECR3_EE6F_Pos)
22834#define HRTIM_EECR3_EE6F_3 (0x8UL << HRTIM_EECR3_EE6F_Pos)
22835#define HRTIM_EECR3_EE7F_Pos (6U)
22836#define HRTIM_EECR3_EE7F_Msk (0xFUL << HRTIM_EECR3_EE7F_Pos)
22837#define HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk
22838#define HRTIM_EECR3_EE7F_0 (0x1UL << HRTIM_EECR3_EE7F_Pos)
22839#define HRTIM_EECR3_EE7F_1 (0x2UL << HRTIM_EECR3_EE7F_Pos)
22840#define HRTIM_EECR3_EE7F_2 (0x4UL << HRTIM_EECR3_EE7F_Pos)
22841#define HRTIM_EECR3_EE7F_3 (0x8UL << HRTIM_EECR3_EE7F_Pos)
22842#define HRTIM_EECR3_EE8F_Pos (12U)
22843#define HRTIM_EECR3_EE8F_Msk (0xFUL << HRTIM_EECR3_EE8F_Pos)
22844#define HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk
22845#define HRTIM_EECR3_EE8F_0 (0x1UL << HRTIM_EECR3_EE8F_Pos)
22846#define HRTIM_EECR3_EE8F_1 (0x2UL << HRTIM_EECR3_EE8F_Pos)
22847#define HRTIM_EECR3_EE8F_2 (0x4UL << HRTIM_EECR3_EE8F_Pos)
22848#define HRTIM_EECR3_EE8F_3 (0x8UL << HRTIM_EECR3_EE8F_Pos)
22849#define HRTIM_EECR3_EE9F_Pos (18U)
22850#define HRTIM_EECR3_EE9F_Msk (0xFUL << HRTIM_EECR3_EE9F_Pos)
22851#define HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk
22852#define HRTIM_EECR3_EE9F_0 (0x1UL << HRTIM_EECR3_EE9F_Pos)
22853#define HRTIM_EECR3_EE9F_1 (0x2UL << HRTIM_EECR3_EE9F_Pos)
22854#define HRTIM_EECR3_EE9F_2 (0x4UL << HRTIM_EECR3_EE9F_Pos)
22855#define HRTIM_EECR3_EE9F_3 (0x8UL << HRTIM_EECR3_EE9F_Pos)
22856#define HRTIM_EECR3_EE10F_Pos (24U)
22857#define HRTIM_EECR3_EE10F_Msk (0xFUL << HRTIM_EECR3_EE10F_Pos)
22858#define HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk
22859#define HRTIM_EECR3_EE10F_0 (0x1UL << HRTIM_EECR3_EE10F_Pos)
22860#define HRTIM_EECR3_EE10F_1 (0x2UL << HRTIM_EECR3_EE10F_Pos)
22861#define HRTIM_EECR3_EE10F_2 (0x4UL << HRTIM_EECR3_EE10F_Pos)
22862#define HRTIM_EECR3_EE10F_3 (0x8UL << HRTIM_EECR3_EE10F_Pos)
22863#define HRTIM_EECR3_EEVSD_Pos (30U)
22864#define HRTIM_EECR3_EEVSD_Msk (0x3UL << HRTIM_EECR3_EEVSD_Pos)
22865#define HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk
22866#define HRTIM_EECR3_EEVSD_0 (0x1UL << HRTIM_EECR3_EEVSD_Pos)
22867#define HRTIM_EECR3_EEVSD_1 (0x2UL << HRTIM_EECR3_EEVSD_Pos)
22869/******************* Bit definition for HRTIM_ADC1R register ****************/
22870#define HRTIM_ADC1R_AD1MC1_Pos (0U)
22871#define HRTIM_ADC1R_AD1MC1_Msk (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)
22872#define HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk
22873#define HRTIM_ADC1R_AD1MC2_Pos (1U)
22874#define HRTIM_ADC1R_AD1MC2_Msk (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)
22875#define HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk
22876#define HRTIM_ADC1R_AD1MC3_Pos (2U)
22877#define HRTIM_ADC1R_AD1MC3_Msk (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)
22878#define HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk
22879#define HRTIM_ADC1R_AD1MC4_Pos (3U)
22880#define HRTIM_ADC1R_AD1MC4_Msk (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)
22881#define HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk
22882#define HRTIM_ADC1R_AD1MPER_Pos (4U)
22883#define HRTIM_ADC1R_AD1MPER_Msk (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)
22884#define HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk
22885#define HRTIM_ADC1R_AD1EEV1_Pos (5U)
22886#define HRTIM_ADC1R_AD1EEV1_Msk (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)
22887#define HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk
22888#define HRTIM_ADC1R_AD1EEV2_Pos (6U)
22889#define HRTIM_ADC1R_AD1EEV2_Msk (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)
22890#define HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk
22891#define HRTIM_ADC1R_AD1EEV3_Pos (7U)
22892#define HRTIM_ADC1R_AD1EEV3_Msk (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)
22893#define HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk
22894#define HRTIM_ADC1R_AD1EEV4_Pos (8U)
22895#define HRTIM_ADC1R_AD1EEV4_Msk (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)
22896#define HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk
22897#define HRTIM_ADC1R_AD1EEV5_Pos (9U)
22898#define HRTIM_ADC1R_AD1EEV5_Msk (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)
22899#define HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk
22900#define HRTIM_ADC1R_AD1TAC2_Pos (10U)
22901#define HRTIM_ADC1R_AD1TAC2_Msk (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)
22902#define HRTIM_ADC1R_AD1TAC2 HRTIM_ADC1R_AD1TAC2_Msk
22903#define HRTIM_ADC1R_AD1TAC3_Pos (11U)
22904#define HRTIM_ADC1R_AD1TAC3_Msk (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)
22905#define HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk
22906#define HRTIM_ADC1R_AD1TAC4_Pos (12U)
22907#define HRTIM_ADC1R_AD1TAC4_Msk (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)
22908#define HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk
22909#define HRTIM_ADC1R_AD1TAPER_Pos (13U)
22910#define HRTIM_ADC1R_AD1TAPER_Msk (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)
22911#define HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk
22912#define HRTIM_ADC1R_AD1TARST_Pos (14U)
22913#define HRTIM_ADC1R_AD1TARST_Msk (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)
22914#define HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk
22915#define HRTIM_ADC1R_AD1TBC2_Pos (15U)
22916#define HRTIM_ADC1R_AD1TBC2_Msk (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)
22917#define HRTIM_ADC1R_AD1TBC2 HRTIM_ADC1R_AD1TBC2_Msk
22918#define HRTIM_ADC1R_AD1TBC3_Pos (16U)
22919#define HRTIM_ADC1R_AD1TBC3_Msk (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)
22920#define HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk
22921#define HRTIM_ADC1R_AD1TBC4_Pos (17U)
22922#define HRTIM_ADC1R_AD1TBC4_Msk (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)
22923#define HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk
22924#define HRTIM_ADC1R_AD1TBPER_Pos (18U)
22925#define HRTIM_ADC1R_AD1TBPER_Msk (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)
22926#define HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk
22927#define HRTIM_ADC1R_AD1TBRST_Pos (19U)
22928#define HRTIM_ADC1R_AD1TBRST_Msk (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)
22929#define HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk
22930#define HRTIM_ADC1R_AD1TCC2_Pos (20U)
22931#define HRTIM_ADC1R_AD1TCC2_Msk (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)
22932#define HRTIM_ADC1R_AD1TCC2 HRTIM_ADC1R_AD1TCC2_Msk
22933#define HRTIM_ADC1R_AD1TCC3_Pos (21U)
22934#define HRTIM_ADC1R_AD1TCC3_Msk (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)
22935#define HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk
22936#define HRTIM_ADC1R_AD1TCC4_Pos (22U)
22937#define HRTIM_ADC1R_AD1TCC4_Msk (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)
22938#define HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk
22939#define HRTIM_ADC1R_AD1TCPER_Pos (23U)
22940#define HRTIM_ADC1R_AD1TCPER_Msk (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)
22941#define HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk
22942#define HRTIM_ADC1R_AD1TDC2_Pos (24U)
22943#define HRTIM_ADC1R_AD1TDC2_Msk (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)
22944#define HRTIM_ADC1R_AD1TDC2 HRTIM_ADC1R_AD1TDC2_Msk
22945#define HRTIM_ADC1R_AD1TDC3_Pos (25U)
22946#define HRTIM_ADC1R_AD1TDC3_Msk (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)
22947#define HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk
22948#define HRTIM_ADC1R_AD1TDC4_Pos (26U)
22949#define HRTIM_ADC1R_AD1TDC4_Msk (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)
22950#define HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk
22951#define HRTIM_ADC1R_AD1TDPER_Pos (27U)
22952#define HRTIM_ADC1R_AD1TDPER_Msk (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)
22953#define HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk
22954#define HRTIM_ADC1R_AD1TEC2_Pos (28U)
22955#define HRTIM_ADC1R_AD1TEC2_Msk (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)
22956#define HRTIM_ADC1R_AD1TEC2 HRTIM_ADC1R_AD1TEC2_Msk
22957#define HRTIM_ADC1R_AD1TEC3_Pos (29U)
22958#define HRTIM_ADC1R_AD1TEC3_Msk (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)
22959#define HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk
22960#define HRTIM_ADC1R_AD1TEC4_Pos (30U)
22961#define HRTIM_ADC1R_AD1TEC4_Msk (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)
22962#define HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk
22963#define HRTIM_ADC1R_AD1TEPER_Pos (31U)
22964#define HRTIM_ADC1R_AD1TEPER_Msk (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)
22965#define HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk
22967/******************* Bit definition for HRTIM_ADC2R register ****************/
22968#define HRTIM_ADC2R_AD2MC1_Pos (0U)
22969#define HRTIM_ADC2R_AD2MC1_Msk (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)
22970#define HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk
22971#define HRTIM_ADC2R_AD2MC2_Pos (1U)
22972#define HRTIM_ADC2R_AD2MC2_Msk (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)
22973#define HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk
22974#define HRTIM_ADC2R_AD2MC3_Pos (2U)
22975#define HRTIM_ADC2R_AD2MC3_Msk (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)
22976#define HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk
22977#define HRTIM_ADC2R_AD2MC4_Pos (3U)
22978#define HRTIM_ADC2R_AD2MC4_Msk (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)
22979#define HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk
22980#define HRTIM_ADC2R_AD2MPER_Pos (4U)
22981#define HRTIM_ADC2R_AD2MPER_Msk (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)
22982#define HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk
22983#define HRTIM_ADC2R_AD2EEV6_Pos (5U)
22984#define HRTIM_ADC2R_AD2EEV6_Msk (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)
22985#define HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk
22986#define HRTIM_ADC2R_AD2EEV7_Pos (6U)
22987#define HRTIM_ADC2R_AD2EEV7_Msk (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)
22988#define HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk
22989#define HRTIM_ADC2R_AD2EEV8_Pos (7U)
22990#define HRTIM_ADC2R_AD2EEV8_Msk (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)
22991#define HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk
22992#define HRTIM_ADC2R_AD2EEV9_Pos (8U)
22993#define HRTIM_ADC2R_AD2EEV9_Msk (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)
22994#define HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk
22995#define HRTIM_ADC2R_AD2EEV10_Pos (9U)
22996#define HRTIM_ADC2R_AD2EEV10_Msk (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)
22997#define HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk
22998#define HRTIM_ADC2R_AD2TAC2_Pos (10U)
22999#define HRTIM_ADC2R_AD2TAC2_Msk (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)
23000#define HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk
23001#define HRTIM_ADC2R_AD2TAC3_Pos (11U)
23002#define HRTIM_ADC2R_AD2TAC3_Msk (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)
23003#define HRTIM_ADC2R_AD2TAC3 HRTIM_ADC2R_AD2TAC3_Msk
23004#define HRTIM_ADC2R_AD2TAC4_Pos (12U)
23005#define HRTIM_ADC2R_AD2TAC4_Msk (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)
23006#define HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk
23007#define HRTIM_ADC2R_AD2TAPER_Pos (13U)
23008#define HRTIM_ADC2R_AD2TAPER_Msk (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)
23009#define HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk
23010#define HRTIM_ADC2R_AD2TBC2_Pos (14U)
23011#define HRTIM_ADC2R_AD2TBC2_Msk (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)
23012#define HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk
23013#define HRTIM_ADC2R_AD2TBC3_Pos (15U)
23014#define HRTIM_ADC2R_AD2TBC3_Msk (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)
23015#define HRTIM_ADC2R_AD2TBC3 HRTIM_ADC2R_AD2TBC3_Msk
23016#define HRTIM_ADC2R_AD2TBC4_Pos (16U)
23017#define HRTIM_ADC2R_AD2TBC4_Msk (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)
23018#define HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk
23019#define HRTIM_ADC2R_AD2TBPER_Pos (17U)
23020#define HRTIM_ADC2R_AD2TBPER_Msk (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)
23021#define HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk
23022#define HRTIM_ADC2R_AD2TCC2_Pos (18U)
23023#define HRTIM_ADC2R_AD2TCC2_Msk (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)
23024#define HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk
23025#define HRTIM_ADC2R_AD2TCC3_Pos (19U)
23026#define HRTIM_ADC2R_AD2TCC3_Msk (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)
23027#define HRTIM_ADC2R_AD2TCC3 HRTIM_ADC2R_AD2TCC3_Msk
23028#define HRTIM_ADC2R_AD2TCC4_Pos (20U)
23029#define HRTIM_ADC2R_AD2TCC4_Msk (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)
23030#define HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk
23031#define HRTIM_ADC2R_AD2TCPER_Pos (21U)
23032#define HRTIM_ADC2R_AD2TCPER_Msk (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)
23033#define HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk
23034#define HRTIM_ADC2R_AD2TCRST_Pos (22U)
23035#define HRTIM_ADC2R_AD2TCRST_Msk (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)
23036#define HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk
23037#define HRTIM_ADC2R_AD2TDC2_Pos (23U)
23038#define HRTIM_ADC2R_AD2TDC2_Msk (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)
23039#define HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk
23040#define HRTIM_ADC2R_AD2TDC3_Pos (24U)
23041#define HRTIM_ADC2R_AD2TDC3_Msk (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)
23042#define HRTIM_ADC2R_AD2TDC3 HRTIM_ADC2R_AD2TDC3_Msk
23043#define HRTIM_ADC2R_AD2TDC4_Pos (25U)
23044#define HRTIM_ADC2R_AD2TDC4_Msk (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)
23045#define HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk
23046#define HRTIM_ADC2R_AD2TDPER_Pos (26U)
23047#define HRTIM_ADC2R_AD2TDPER_Msk (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)
23048#define HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk
23049#define HRTIM_ADC2R_AD2TDRST_Pos (27U)
23050#define HRTIM_ADC2R_AD2TDRST_Msk (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)
23051#define HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk
23052#define HRTIM_ADC2R_AD2TEC2_Pos (28U)
23053#define HRTIM_ADC2R_AD2TEC2_Msk (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)
23054#define HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk
23055#define HRTIM_ADC2R_AD2TEC3_Pos (29U)
23056#define HRTIM_ADC2R_AD2TEC3_Msk (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)
23057#define HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk
23058#define HRTIM_ADC2R_AD2TEC4_Pos (30U)
23059#define HRTIM_ADC2R_AD2TEC4_Msk (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)
23060#define HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk
23061#define HRTIM_ADC2R_AD2TERST_Pos (31U)
23062#define HRTIM_ADC2R_AD2TERST_Msk (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)
23063#define HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk
23065/******************* Bit definition for HRTIM_ADC3R register ****************/
23066#define HRTIM_ADC3R_AD3MC1_Pos (0U)
23067#define HRTIM_ADC3R_AD3MC1_Msk (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)
23068#define HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk
23069#define HRTIM_ADC3R_AD3MC2_Pos (1U)
23070#define HRTIM_ADC3R_AD3MC2_Msk (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)
23071#define HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk
23072#define HRTIM_ADC3R_AD3MC3_Pos (2U)
23073#define HRTIM_ADC3R_AD3MC3_Msk (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)
23074#define HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk
23075#define HRTIM_ADC3R_AD3MC4_Pos (3U)
23076#define HRTIM_ADC3R_AD3MC4_Msk (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)
23077#define HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk
23078#define HRTIM_ADC3R_AD3MPER_Pos (4U)
23079#define HRTIM_ADC3R_AD3MPER_Msk (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)
23080#define HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk
23081#define HRTIM_ADC3R_AD3EEV1_Pos (5U)
23082#define HRTIM_ADC3R_AD3EEV1_Msk (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)
23083#define HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk
23084#define HRTIM_ADC3R_AD3EEV2_Pos (6U)
23085#define HRTIM_ADC3R_AD3EEV2_Msk (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)
23086#define HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk
23087#define HRTIM_ADC3R_AD3EEV3_Pos (7U)
23088#define HRTIM_ADC3R_AD3EEV3_Msk (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)
23089#define HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk
23090#define HRTIM_ADC3R_AD3EEV4_Pos (8U)
23091#define HRTIM_ADC3R_AD3EEV4_Msk (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)
23092#define HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk
23093#define HRTIM_ADC3R_AD3EEV5_Pos (9U)
23094#define HRTIM_ADC3R_AD3EEV5_Msk (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)
23095#define HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk
23096#define HRTIM_ADC3R_AD3TAC2_Pos (10U)
23097#define HRTIM_ADC3R_AD3TAC2_Msk (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)
23098#define HRTIM_ADC3R_AD3TAC2 HRTIM_ADC3R_AD3TAC2_Msk
23099#define HRTIM_ADC3R_AD3TAC3_Pos (11U)
23100#define HRTIM_ADC3R_AD3TAC3_Msk (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)
23101#define HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk
23102#define HRTIM_ADC3R_AD3TAC4_Pos (12U)
23103#define HRTIM_ADC3R_AD3TAC4_Msk (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)
23104#define HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk
23105#define HRTIM_ADC3R_AD3TAPER_Pos (13U)
23106#define HRTIM_ADC3R_AD3TAPER_Msk (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)
23107#define HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk
23108#define HRTIM_ADC3R_AD3TARST_Pos (14U)
23109#define HRTIM_ADC3R_AD3TARST_Msk (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)
23110#define HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk
23111#define HRTIM_ADC3R_AD3TBC2_Pos (15U)
23112#define HRTIM_ADC3R_AD3TBC2_Msk (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)
23113#define HRTIM_ADC3R_AD3TBC2 HRTIM_ADC3R_AD3TBC2_Msk
23114#define HRTIM_ADC3R_AD3TBC3_Pos (16U)
23115#define HRTIM_ADC3R_AD3TBC3_Msk (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)
23116#define HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk
23117#define HRTIM_ADC3R_AD3TBC4_Pos (17U)
23118#define HRTIM_ADC3R_AD3TBC4_Msk (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)
23119#define HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk
23120#define HRTIM_ADC3R_AD3TBPER_Pos (18U)
23121#define HRTIM_ADC3R_AD3TBPER_Msk (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)
23122#define HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk
23123#define HRTIM_ADC3R_AD3TBRST_Pos (19U)
23124#define HRTIM_ADC3R_AD3TBRST_Msk (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)
23125#define HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk
23126#define HRTIM_ADC3R_AD3TCC2_Pos (20U)
23127#define HRTIM_ADC3R_AD3TCC2_Msk (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)
23128#define HRTIM_ADC3R_AD3TCC2 HRTIM_ADC3R_AD3TCC2_Msk
23129#define HRTIM_ADC3R_AD3TCC3_Pos (21U)
23130#define HRTIM_ADC3R_AD3TCC3_Msk (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)
23131#define HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk
23132#define HRTIM_ADC3R_AD3TCC4_Pos (22U)
23133#define HRTIM_ADC3R_AD3TCC4_Msk (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)
23134#define HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk
23135#define HRTIM_ADC3R_AD3TCPER_Pos (23U)
23136#define HRTIM_ADC3R_AD3TCPER_Msk (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)
23137#define HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk
23138#define HRTIM_ADC3R_AD3TDC2_Pos (24U)
23139#define HRTIM_ADC3R_AD3TDC2_Msk (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)
23140#define HRTIM_ADC3R_AD3TDC2 HRTIM_ADC3R_AD3TDC2_Msk
23141#define HRTIM_ADC3R_AD3TDC3_Pos (25U)
23142#define HRTIM_ADC3R_AD3TDC3_Msk (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)
23143#define HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk
23144#define HRTIM_ADC3R_AD3TDC4_Pos (26U)
23145#define HRTIM_ADC3R_AD3TDC4_Msk (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)
23146#define HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk
23147#define HRTIM_ADC3R_AD3TDPER_Pos (27U)
23148#define HRTIM_ADC3R_AD3TDPER_Msk (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)
23149#define HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk
23150#define HRTIM_ADC3R_AD3TEC2_Pos (28U)
23151#define HRTIM_ADC3R_AD3TEC2_Msk (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)
23152#define HRTIM_ADC3R_AD3TEC2 HRTIM_ADC3R_AD3TEC2_Msk
23153#define HRTIM_ADC3R_AD3TEC3_Pos (29U)
23154#define HRTIM_ADC3R_AD3TEC3_Msk (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)
23155#define HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk
23156#define HRTIM_ADC3R_AD3TEC4_Pos (30U)
23157#define HRTIM_ADC3R_AD3TEC4_Msk (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)
23158#define HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk
23159#define HRTIM_ADC3R_AD3TEPER_Pos (31U)
23160#define HRTIM_ADC3R_AD3TEPER_Msk (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)
23161#define HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk
23163/******************* Bit definition for HRTIM_ADC4R register ****************/
23164#define HRTIM_ADC4R_AD4MC1_Pos (0U)
23165#define HRTIM_ADC4R_AD4MC1_Msk (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)
23166#define HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk
23167#define HRTIM_ADC4R_AD4MC2_Pos (1U)
23168#define HRTIM_ADC4R_AD4MC2_Msk (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)
23169#define HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk
23170#define HRTIM_ADC4R_AD4MC3_Pos (2U)
23171#define HRTIM_ADC4R_AD4MC3_Msk (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)
23172#define HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk
23173#define HRTIM_ADC4R_AD4MC4_Pos (3U)
23174#define HRTIM_ADC4R_AD4MC4_Msk (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)
23175#define HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk
23176#define HRTIM_ADC4R_AD4MPER_Pos (4U)
23177#define HRTIM_ADC4R_AD4MPER_Msk (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)
23178#define HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk
23179#define HRTIM_ADC4R_AD4EEV6_Pos (5U)
23180#define HRTIM_ADC4R_AD4EEV6_Msk (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)
23181#define HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk
23182#define HRTIM_ADC4R_AD4EEV7_Pos (6U)
23183#define HRTIM_ADC4R_AD4EEV7_Msk (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)
23184#define HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk
23185#define HRTIM_ADC4R_AD4EEV8_Pos (7U)
23186#define HRTIM_ADC4R_AD4EEV8_Msk (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)
23187#define HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk
23188#define HRTIM_ADC4R_AD4EEV9_Pos (8U)
23189#define HRTIM_ADC4R_AD4EEV9_Msk (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)
23190#define HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk
23191#define HRTIM_ADC4R_AD4EEV10_Pos (9U)
23192#define HRTIM_ADC4R_AD4EEV10_Msk (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)
23193#define HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk
23194#define HRTIM_ADC4R_AD4TAC2_Pos (10U)
23195#define HRTIM_ADC4R_AD4TAC2_Msk (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)
23196#define HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk
23197#define HRTIM_ADC4R_AD4TAC3_Pos (11U)
23198#define HRTIM_ADC4R_AD4TAC3_Msk (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)
23199#define HRTIM_ADC4R_AD4TAC3 HRTIM_ADC4R_AD4TAC3_Msk
23200#define HRTIM_ADC4R_AD4TAC4_Pos (12U)
23201#define HRTIM_ADC4R_AD4TAC4_Msk (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)
23202#define HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk
23203#define HRTIM_ADC4R_AD4TAPER_Pos (13U)
23204#define HRTIM_ADC4R_AD4TAPER_Msk (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)
23205#define HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk
23206#define HRTIM_ADC4R_AD4TBC2_Pos (14U)
23207#define HRTIM_ADC4R_AD4TBC2_Msk (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)
23208#define HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk
23209#define HRTIM_ADC4R_AD4TBC3_Pos (15U)
23210#define HRTIM_ADC4R_AD4TBC3_Msk (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)
23211#define HRTIM_ADC4R_AD4TBC3 HRTIM_ADC4R_AD4TBC3_Msk
23212#define HRTIM_ADC4R_AD4TBC4_Pos (16U)
23213#define HRTIM_ADC4R_AD4TBC4_Msk (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)
23214#define HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk
23215#define HRTIM_ADC4R_AD4TBPER_Pos (17U)
23216#define HRTIM_ADC4R_AD4TBPER_Msk (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)
23217#define HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk
23218#define HRTIM_ADC4R_AD4TCC2_Pos (18U)
23219#define HRTIM_ADC4R_AD4TCC2_Msk (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)
23220#define HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk
23221#define HRTIM_ADC4R_AD4TCC3_Pos (19U)
23222#define HRTIM_ADC4R_AD4TCC3_Msk (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)
23223#define HRTIM_ADC4R_AD4TCC3 HRTIM_ADC4R_AD4TCC3_Msk
23224#define HRTIM_ADC4R_AD4TCC4_Pos (20U)
23225#define HRTIM_ADC4R_AD4TCC4_Msk (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)
23226#define HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk
23227#define HRTIM_ADC4R_AD4TCPER_Pos (21U)
23228#define HRTIM_ADC4R_AD4TCPER_Msk (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)
23229#define HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk
23230#define HRTIM_ADC4R_AD4TCRST_Pos (22U)
23231#define HRTIM_ADC4R_AD4TCRST_Msk (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)
23232#define HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk
23233#define HRTIM_ADC4R_AD4TDC2_Pos (23U)
23234#define HRTIM_ADC4R_AD4TDC2_Msk (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)
23235#define HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk
23236#define HRTIM_ADC4R_AD4TDC3_Pos (24U)
23237#define HRTIM_ADC4R_AD4TDC3_Msk (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)
23238#define HRTIM_ADC4R_AD4TDC3 HRTIM_ADC4R_AD4TDC3_Msk
23239#define HRTIM_ADC4R_AD4TDC4_Pos (25U)
23240#define HRTIM_ADC4R_AD4TDC4_Msk (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)
23241#define HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk
23242#define HRTIM_ADC4R_AD4TDPER_Pos (26U)
23243#define HRTIM_ADC4R_AD4TDPER_Msk (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)
23244#define HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk
23245#define HRTIM_ADC4R_AD4TDRST_Pos (27U)
23246#define HRTIM_ADC4R_AD4TDRST_Msk (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)
23247#define HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk
23248#define HRTIM_ADC4R_AD4TEC2_Pos (28U)
23249#define HRTIM_ADC4R_AD4TEC2_Msk (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)
23250#define HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk
23251#define HRTIM_ADC4R_AD4TEC3_Pos (29U)
23252#define HRTIM_ADC4R_AD4TEC3_Msk (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)
23253#define HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk
23254#define HRTIM_ADC4R_AD4TEC4_Pos (30U)
23255#define HRTIM_ADC4R_AD4TEC4_Msk (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)
23256#define HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk
23257#define HRTIM_ADC4R_AD4TERST_Pos (31U)
23258#define HRTIM_ADC4R_AD4TERST_Msk (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)
23259#define HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk
23261/******************* Bit definition for HRTIM_FLTINR1 register ***************/
23262#define HRTIM_FLTINR1_FLT1E_Pos (0U)
23263#define HRTIM_FLTINR1_FLT1E_Msk (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)
23264#define HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk
23265#define HRTIM_FLTINR1_FLT1P_Pos (1U)
23266#define HRTIM_FLTINR1_FLT1P_Msk (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)
23267#define HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk
23268#define HRTIM_FLTINR1_FLT1SRC_Pos (2U)
23269#define HRTIM_FLTINR1_FLT1SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)
23270#define HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_Msk
23271#define HRTIM_FLTINR1_FLT1F_Pos (3U)
23272#define HRTIM_FLTINR1_FLT1F_Msk (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)
23273#define HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk
23274#define HRTIM_FLTINR1_FLT1F_0 (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)
23275#define HRTIM_FLTINR1_FLT1F_1 (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)
23276#define HRTIM_FLTINR1_FLT1F_2 (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)
23277#define HRTIM_FLTINR1_FLT1F_3 (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)
23278#define HRTIM_FLTINR1_FLT1LCK_Pos (7U)
23279#define HRTIM_FLTINR1_FLT1LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)
23280#define HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk
23282#define HRTIM_FLTINR1_FLT2E_Pos (8U)
23283#define HRTIM_FLTINR1_FLT2E_Msk (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)
23284#define HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk
23285#define HRTIM_FLTINR1_FLT2P_Pos (9U)
23286#define HRTIM_FLTINR1_FLT2P_Msk (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)
23287#define HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk
23288#define HRTIM_FLTINR1_FLT2SRC_Pos (10U)
23289#define HRTIM_FLTINR1_FLT2SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)
23290#define HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_Msk
23291#define HRTIM_FLTINR1_FLT2F_Pos (11U)
23292#define HRTIM_FLTINR1_FLT2F_Msk (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)
23293#define HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk
23294#define HRTIM_FLTINR1_FLT2F_0 (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)
23295#define HRTIM_FLTINR1_FLT2F_1 (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)
23296#define HRTIM_FLTINR1_FLT2F_2 (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)
23297#define HRTIM_FLTINR1_FLT2F_3 (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)
23298#define HRTIM_FLTINR1_FLT2LCK_Pos (15U)
23299#define HRTIM_FLTINR1_FLT2LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)
23300#define HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk
23302#define HRTIM_FLTINR1_FLT3E_Pos (16U)
23303#define HRTIM_FLTINR1_FLT3E_Msk (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)
23304#define HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk
23305#define HRTIM_FLTINR1_FLT3P_Pos (17U)
23306#define HRTIM_FLTINR1_FLT3P_Msk (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)
23307#define HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk
23308#define HRTIM_FLTINR1_FLT3SRC_Pos (18U)
23309#define HRTIM_FLTINR1_FLT3SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)
23310#define HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_Msk
23311#define HRTIM_FLTINR1_FLT3F_Pos (19U)
23312#define HRTIM_FLTINR1_FLT3F_Msk (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)
23313#define HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk
23314#define HRTIM_FLTINR1_FLT3F_0 (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)
23315#define HRTIM_FLTINR1_FLT3F_1 (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)
23316#define HRTIM_FLTINR1_FLT3F_2 (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)
23317#define HRTIM_FLTINR1_FLT3F_3 (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)
23318#define HRTIM_FLTINR1_FLT3LCK_Pos (23U)
23319#define HRTIM_FLTINR1_FLT3LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)
23320#define HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk
23322#define HRTIM_FLTINR1_FLT4E_Pos (24U)
23323#define HRTIM_FLTINR1_FLT4E_Msk (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)
23324#define HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk
23325#define HRTIM_FLTINR1_FLT4P_Pos (25U)
23326#define HRTIM_FLTINR1_FLT4P_Msk (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)
23327#define HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk
23328#define HRTIM_FLTINR1_FLT4SRC_Pos (26U)
23329#define HRTIM_FLTINR1_FLT4SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)
23330#define HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_Msk
23331#define HRTIM_FLTINR1_FLT4F_Pos (27U)
23332#define HRTIM_FLTINR1_FLT4F_Msk (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)
23333#define HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk
23334#define HRTIM_FLTINR1_FLT4F_0 (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)
23335#define HRTIM_FLTINR1_FLT4F_1 (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)
23336#define HRTIM_FLTINR1_FLT4F_2 (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)
23337#define HRTIM_FLTINR1_FLT4F_3 (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)
23338#define HRTIM_FLTINR1_FLT4LCK_Pos (31U)
23339#define HRTIM_FLTINR1_FLT4LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)
23340#define HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk
23342/******************* Bit definition for HRTIM_FLTINR2 register ***************/
23343#define HRTIM_FLTINR2_FLT5E_Pos (0U)
23344#define HRTIM_FLTINR2_FLT5E_Msk (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)
23345#define HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk
23346#define HRTIM_FLTINR2_FLT5P_Pos (1U)
23347#define HRTIM_FLTINR2_FLT5P_Msk (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)
23348#define HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk
23349#define HRTIM_FLTINR2_FLT5SRC_Pos (2U)
23350#define HRTIM_FLTINR2_FLT5SRC_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)
23351#define HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_Msk
23352#define HRTIM_FLTINR2_FLT5F_Pos (3U)
23353#define HRTIM_FLTINR2_FLT5F_Msk (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)
23354#define HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk
23355#define HRTIM_FLTINR2_FLT5F_0 (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)
23356#define HRTIM_FLTINR2_FLT5F_1 (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)
23357#define HRTIM_FLTINR2_FLT5F_2 (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)
23358#define HRTIM_FLTINR2_FLT5F_3 (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)
23359#define HRTIM_FLTINR2_FLT5LCK_Pos (7U)
23360#define HRTIM_FLTINR2_FLT5LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)
23361#define HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk
23362#define HRTIM_FLTINR2_FLTSD_Pos (24U)
23363#define HRTIM_FLTINR2_FLTSD_Msk (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)
23364#define HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk
23365#define HRTIM_FLTINR2_FLTSD_0 (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)
23366#define HRTIM_FLTINR2_FLTSD_1 (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)
23368/******************* Bit definition for HRTIM_BDMUPR register ***************/
23369#define HRTIM_BDMUPR_MCR_Pos (0U)
23370#define HRTIM_BDMUPR_MCR_Msk (0x1UL << HRTIM_BDMUPR_MCR_Pos)
23371#define HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk
23372#define HRTIM_BDMUPR_MICR_Pos (1U)
23373#define HRTIM_BDMUPR_MICR_Msk (0x1UL << HRTIM_BDMUPR_MICR_Pos)
23374#define HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk
23375#define HRTIM_BDMUPR_MDIER_Pos (2U)
23376#define HRTIM_BDMUPR_MDIER_Msk (0x1UL << HRTIM_BDMUPR_MDIER_Pos)
23377#define HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk
23378#define HRTIM_BDMUPR_MCNT_Pos (3U)
23379#define HRTIM_BDMUPR_MCNT_Msk (0x1UL << HRTIM_BDMUPR_MCNT_Pos)
23380#define HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk
23381#define HRTIM_BDMUPR_MPER_Pos (4U)
23382#define HRTIM_BDMUPR_MPER_Msk (0x1UL << HRTIM_BDMUPR_MPER_Pos)
23383#define HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk
23384#define HRTIM_BDMUPR_MREP_Pos (5U)
23385#define HRTIM_BDMUPR_MREP_Msk (0x1UL << HRTIM_BDMUPR_MREP_Pos)
23386#define HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk
23387#define HRTIM_BDMUPR_MCMP1_Pos (6U)
23388#define HRTIM_BDMUPR_MCMP1_Msk (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)
23389#define HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk
23390#define HRTIM_BDMUPR_MCMP2_Pos (7U)
23391#define HRTIM_BDMUPR_MCMP2_Msk (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)
23392#define HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk
23393#define HRTIM_BDMUPR_MCMP3_Pos (8U)
23394#define HRTIM_BDMUPR_MCMP3_Msk (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)
23395#define HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk
23396#define HRTIM_BDMUPR_MCMP4_Pos (9U)
23397#define HRTIM_BDMUPR_MCMP4_Msk (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)
23398#define HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk
23400/******************* Bit definition for HRTIM_BDTUPR register ***************/
23401#define HRTIM_BDTUPR_TIMCR_Pos (0U)
23402#define HRTIM_BDTUPR_TIMCR_Msk (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)
23403#define HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk
23404#define HRTIM_BDTUPR_TIMICR_Pos (1U)
23405#define HRTIM_BDTUPR_TIMICR_Msk (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)
23406#define HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk
23407#define HRTIM_BDTUPR_TIMDIER_Pos (2U)
23408#define HRTIM_BDTUPR_TIMDIER_Msk (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)
23409#define HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk
23410#define HRTIM_BDTUPR_TIMCNT_Pos (3U)
23411#define HRTIM_BDTUPR_TIMCNT_Msk (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)
23412#define HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk
23413#define HRTIM_BDTUPR_TIMPER_Pos (4U)
23414#define HRTIM_BDTUPR_TIMPER_Msk (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)
23415#define HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk
23416#define HRTIM_BDTUPR_TIMREP_Pos (5U)
23417#define HRTIM_BDTUPR_TIMREP_Msk (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)
23418#define HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk
23419#define HRTIM_BDTUPR_TIMCMP1_Pos (6U)
23420#define HRTIM_BDTUPR_TIMCMP1_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)
23421#define HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk
23422#define HRTIM_BDTUPR_TIMCMP2_Pos (7U)
23423#define HRTIM_BDTUPR_TIMCMP2_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)
23424#define HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk
23425#define HRTIM_BDTUPR_TIMCMP3_Pos (8U)
23426#define HRTIM_BDTUPR_TIMCMP3_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)
23427#define HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk
23428#define HRTIM_BDTUPR_TIMCMP4_Pos (9U)
23429#define HRTIM_BDTUPR_TIMCMP4_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)
23430#define HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk
23431#define HRTIM_BDTUPR_TIMDTR_Pos (10U)
23432#define HRTIM_BDTUPR_TIMDTR_Msk (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)
23433#define HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk
23434#define HRTIM_BDTUPR_TIMSET1R_Pos (11U)
23435#define HRTIM_BDTUPR_TIMSET1R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)
23436#define HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk
23437#define HRTIM_BDTUPR_TIMRST1R_Pos (12U)
23438#define HRTIM_BDTUPR_TIMRST1R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)
23439#define HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk
23440#define HRTIM_BDTUPR_TIMSET2R_Pos (13U)
23441#define HRTIM_BDTUPR_TIMSET2R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)
23442#define HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk
23443#define HRTIM_BDTUPR_TIMRST2R_Pos (14U)
23444#define HRTIM_BDTUPR_TIMRST2R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)
23445#define HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk
23446#define HRTIM_BDTUPR_TIMEEFR1_Pos (15U)
23447#define HRTIM_BDTUPR_TIMEEFR1_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)
23448#define HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk
23449#define HRTIM_BDTUPR_TIMEEFR2_Pos (16U)
23450#define HRTIM_BDTUPR_TIMEEFR2_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)
23451#define HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk
23452#define HRTIM_BDTUPR_TIMRSTR_Pos (17U)
23453#define HRTIM_BDTUPR_TIMRSTR_Msk (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)
23454#define HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk
23455#define HRTIM_BDTUPR_TIMCHPR_Pos (18U)
23456#define HRTIM_BDTUPR_TIMCHPR_Msk (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)
23457#define HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk
23458#define HRTIM_BDTUPR_TIMOUTR_Pos (19U)
23459#define HRTIM_BDTUPR_TIMOUTR_Msk (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)
23460#define HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk
23461#define HRTIM_BDTUPR_TIMFLTR_Pos (20U)
23462#define HRTIM_BDTUPR_TIMFLTR_Msk (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)
23463#define HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk
23465/******************* Bit definition for HRTIM_BDMADR register ***************/
23466#define HRTIM_BDMADR_BDMADR_Pos (0U)
23467#define HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos)
23468#define HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk
23470/******************************************************************************/
23471/* */
23472/* RAM ECC monitoring */
23473/* */
23474/******************************************************************************/
23475/****************** Bit definition for RAMECC_IER register ******************/
23476#define RAMECC_IER_GECCDEBWIE_Pos (3U)
23477#define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)
23478#define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk
23479#define RAMECC_IER_GECCDEIE_Pos (2U)
23480#define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos)
23481#define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk
23482#define RAMECC_IER_GECCSEIE_Pos (1U)
23483#define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos)
23484#define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk
23485#define RAMECC_IER_GIE_Pos (0U)
23486#define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos)
23487#define RAMECC_IER_GIE RAMECC_IER_GIE_Msk
23489/******************* Bit definition for RAMECC_CR register ******************/
23490#define RAMECC_CR_ECCELEN_Pos (5U)
23491#define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos)
23492#define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk
23493#define RAMECC_CR_ECCDEBWIE_Pos (4U)
23494#define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)
23495#define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk
23496#define RAMECC_CR_ECCDEIE_Pos (3U)
23497#define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos)
23498#define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk
23499#define RAMECC_CR_ECCSEIE_Pos (2U)
23500#define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos)
23501#define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk
23503/******************* Bit definition for RAMECC_SR register ******************/
23504#define RAMECC_SR_DEBWDF_Pos (2U)
23505#define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos)
23506#define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk
23507#define RAMECC_SR_DEDF_Pos (1U)
23508#define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos)
23509#define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk
23510#define RAMECC_SR_SEDCF_Pos (0U)
23511#define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos)
23512#define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk
23514/****************** Bit definition for RAMECC_FAR register ******************/
23515#define RAMECC_FAR_FADD_Pos (0U)
23516#define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)
23517#define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk
23519/****************** Bit definition for RAMECC_FDRL register *****************/
23520#define RAMECC_FAR_FDATAL_Pos (0U)
23521#define RAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)
23522#define RAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk
23524/****************** Bit definition for RAMECC_FDRH register *****************/
23525#define RAMECC_FAR_FDATAH_Pos (0U)
23526#define RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)
23527#define RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
23528
23529/***************** Bit definition for RAMECC_FECR register ******************/
23530#define RAMECC_FECR_FEC_Pos (0U)
23531#define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)
23532#define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk
23534/******************************************************************************/
23535/* */
23536/* MDIOS */
23537/* */
23538/******************************************************************************/
23539/******************** Bit definition for MDIOS_CR register *******************/
23540#define MDIOS_CR_EN_Pos (0U)
23541#define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos)
23542#define MDIOS_CR_EN MDIOS_CR_EN_Msk
23543#define MDIOS_CR_WRIE_Pos (1U)
23544#define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos)
23545#define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk
23546#define MDIOS_CR_RDIE_Pos (2U)
23547#define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos)
23548#define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk
23549#define MDIOS_CR_EIE_Pos (3U)
23550#define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos)
23551#define MDIOS_CR_EIE MDIOS_CR_EIE_Msk
23552#define MDIOS_CR_DPC_Pos (7U)
23553#define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos)
23554#define MDIOS_CR_DPC MDIOS_CR_DPC_Msk
23555#define MDIOS_CR_PORT_ADDRESS_Pos (8U)
23556#define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)
23557#define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk
23558#define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)
23559#define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)
23560#define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)
23561#define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)
23562#define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)
23564/******************** Bit definition for MDIOS_SR register *******************/
23565#define MDIOS_SR_PERF_Pos (0U)
23566#define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos)
23567#define MDIOS_SR_PERF MDIOS_SR_PERF_Msk
23568#define MDIOS_SR_SERF_Pos (1U)
23569#define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos)
23570#define MDIOS_SR_SERF MDIOS_SR_SERF_Msk
23571#define MDIOS_SR_TERF_Pos (2U)
23572#define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos)
23573#define MDIOS_SR_TERF MDIOS_SR_TERF_Msk
23575/******************** Bit definition for MDIOS_CLRFR register *******************/
23576#define MDIOS_SR_CPERF_Pos (0U)
23577#define MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos)
23578#define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk
23579#define MDIOS_SR_CSERF_Pos (1U)
23580#define MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos)
23581#define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk
23582#define MDIOS_SR_CTERF_Pos (2U)
23583#define MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos)
23584#define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk
23586/******************************************************************************/
23587/* */
23588/* USB_OTG */
23589/* */
23590/******************************************************************************/
23591/******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
23592#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
23593#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)
23594#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk
23595#define USB_OTG_GOTGCTL_SRQ_Pos (1U)
23596#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)
23597#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk
23598#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
23599#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos)
23600#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk
23601#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
23602#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos)
23603#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk
23604#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
23605#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos)
23606#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk
23607#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
23608#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos)
23609#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk
23610#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
23611#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos)
23612#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk
23613#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
23614#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos)
23615#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk
23616#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
23617#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)
23618#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk
23619#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
23620#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)
23621#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk
23622#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
23623#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)
23624#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk
23625#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
23626#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)
23627#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk
23628#define USB_OTG_GOTGCTL_EHEN_Pos (12U)
23629#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos)
23630#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk
23631#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
23632#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)
23633#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk
23634#define USB_OTG_GOTGCTL_DBCT_Pos (17U)
23635#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)
23636#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk
23637#define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
23638#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)
23639#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk
23640#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
23641#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos)
23642#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk
23643#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
23644#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos)
23645#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk
23646#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
23647#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos)
23648#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk
23650/******************** Bit definition forUSB_OTG_HCFG register ********************/
23651
23652#define USB_OTG_HCFG_FSLSPCS_Pos (0U)
23653#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)
23654#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk
23655#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)
23656#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)
23657#define USB_OTG_HCFG_FSLSS_Pos (2U)
23658#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)
23659#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk
23661/******************** Bit definition forUSB_OTG_DCFG register ********************/
23662
23663#define USB_OTG_DCFG_DSPD_Pos (0U)
23664#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)
23665#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk
23666#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)
23667#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)
23668#define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
23669#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)
23670#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk
23672#define USB_OTG_DCFG_DAD_Pos (4U)
23673#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)
23674#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk
23675#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)
23676#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)
23677#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)
23678#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)
23679#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)
23680#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)
23681#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)
23683#define USB_OTG_DCFG_PFIVL_Pos (11U)
23684#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)
23685#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk
23686#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)
23687#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)
23689#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
23690#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)
23691#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk
23693#define USB_OTG_DCFG_ERRATIM_Pos (15U)
23694#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos)
23695#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk
23697#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
23698#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)
23699#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk
23700#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)
23701#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)
23703/******************** Bit definition forUSB_OTG_PCGCR register ********************/
23704#define USB_OTG_PCGCR_STPPCLK_Pos (0U)
23705#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)
23706#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk
23707#define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
23708#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)
23709#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk
23710#define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
23711#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)
23712#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk
23714/******************** Bit definition forUSB_OTG_GOTGINT register ********************/
23715#define USB_OTG_GOTGINT_SEDET_Pos (2U)
23716#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)
23717#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk
23718#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
23719#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)
23720#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk
23721#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
23722#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)
23723#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk
23724#define USB_OTG_GOTGINT_HNGDET_Pos (17U)
23725#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)
23726#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk
23727#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
23728#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)
23729#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk
23730#define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
23731#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)
23732#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk
23734/******************** Bit definition forUSB_OTG_DCTL register ********************/
23735#define USB_OTG_DCTL_RWUSIG_Pos (0U)
23736#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)
23737#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk
23738#define USB_OTG_DCTL_SDIS_Pos (1U)
23739#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)
23740#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk
23741#define USB_OTG_DCTL_GINSTS_Pos (2U)
23742#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)
23743#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk
23744#define USB_OTG_DCTL_GONSTS_Pos (3U)
23745#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)
23746#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk
23748#define USB_OTG_DCTL_TCTL_Pos (4U)
23749#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)
23750#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk
23751#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)
23752#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)
23753#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)
23754#define USB_OTG_DCTL_SGINAK_Pos (7U)
23755#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)
23756#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk
23757#define USB_OTG_DCTL_CGINAK_Pos (8U)
23758#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)
23759#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk
23760#define USB_OTG_DCTL_SGONAK_Pos (9U)
23761#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)
23762#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk
23763#define USB_OTG_DCTL_CGONAK_Pos (10U)
23764#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)
23765#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk
23766#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
23767#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)
23768#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk
23769#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
23770#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos)
23771#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk
23772#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
23773#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos)
23774#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk
23776/******************** Bit definition forUSB_OTG_HFIR register ********************/
23777#define USB_OTG_HFIR_FRIVL_Pos (0U)
23778#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)
23779#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk
23781/******************** Bit definition forUSB_OTG_HFNUM register ********************/
23782#define USB_OTG_HFNUM_FRNUM_Pos (0U)
23783#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)
23784#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk
23785#define USB_OTG_HFNUM_FTREM_Pos (16U)
23786#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)
23787#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk
23789/******************** Bit definition forUSB_OTG_DSTS register ********************/
23790#define USB_OTG_DSTS_SUSPSTS_Pos (0U)
23791#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)
23792#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk
23794#define USB_OTG_DSTS_ENUMSPD_Pos (1U)
23795#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)
23796#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk
23797#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)
23798#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)
23799#define USB_OTG_DSTS_EERR_Pos (3U)
23800#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)
23801#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk
23802#define USB_OTG_DSTS_FNSOF_Pos (8U)
23803#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)
23804#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk
23806/******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
23807#define USB_OTG_GAHBCFG_GINT_Pos (0U)
23808#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)
23809#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk
23811#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
23812#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
23813#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk
23814#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
23815#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
23816#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
23817#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
23818#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)
23819#define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
23820#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)
23821#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk
23822#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
23823#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)
23824#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk
23825#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
23826#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)
23827#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk
23829/******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
23830
23831#define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
23832#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)
23833#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk
23834#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)
23835#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)
23836#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)
23837#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
23838#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)
23839#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk
23840#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
23841#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)
23842#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk
23843#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
23844#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)
23845#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk
23847#define USB_OTG_GUSBCFG_TRDT_Pos (10U)
23848#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)
23849#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk
23850#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)
23851#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)
23852#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)
23853#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)
23854#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
23855#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)
23856#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk
23857#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
23858#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)
23859#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk
23860#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
23861#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)
23862#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk
23863#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
23864#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)
23865#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk
23866#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
23867#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)
23868#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk
23869#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
23870#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)
23871#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk
23872#define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
23873#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)
23874#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk
23875#define USB_OTG_GUSBCFG_PCCI_Pos (23U)
23876#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)
23877#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk
23878#define USB_OTG_GUSBCFG_PTCI_Pos (24U)
23879#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)
23880#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk
23881#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
23882#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)
23883#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk
23884#define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
23885#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)
23886#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk
23887#define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
23888#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)
23889#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk
23890#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
23891#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)
23892#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk
23894/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
23895#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
23896#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)
23897#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk
23898#define USB_OTG_GRSTCTL_HSRST_Pos (1U)
23899#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)
23900#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk
23901#define USB_OTG_GRSTCTL_FCRST_Pos (2U)
23902#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)
23903#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk
23904#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
23905#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)
23906#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk
23907#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
23908#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)
23909#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk
23911#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
23912#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)
23913#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk
23914#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
23915#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
23916#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
23917#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
23918#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)
23919#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
23920#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)
23921#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk
23922#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
23923#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)
23924#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk
23926/******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
23927#define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
23928#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)
23929#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk
23930#define USB_OTG_DIEPMSK_EPDM_Pos (1U)
23931#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)
23932#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk
23933#define USB_OTG_DIEPMSK_TOM_Pos (3U)
23934#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)
23935#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk
23936#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
23937#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)
23938#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk
23939#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
23940#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)
23941#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk
23942#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
23943#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)
23944#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk
23945#define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
23946#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)
23947#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk
23948#define USB_OTG_DIEPMSK_BIM_Pos (9U)
23949#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)
23950#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk
23952/******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
23953#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
23954#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)
23955#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk
23957#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
23958#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
23959#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk
23960#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
23961#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
23962#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
23963#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
23964#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
23965#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
23966#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
23967#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)
23969#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
23970#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
23971#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk
23972#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
23973#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
23974#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
23975#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
23976#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
23977#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
23978#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
23979#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)
23981/******************** Bit definition forUSB_OTG_HAINT register ********************/
23982#define USB_OTG_HAINT_HAINT_Pos (0U)
23983#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)
23984#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk
23986/******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
23987#define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
23988#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)
23989#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk
23990#define USB_OTG_DOEPMSK_EPDM_Pos (1U)
23991#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)
23992#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk
23993#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
23994#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)
23995#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk
23996#define USB_OTG_DOEPMSK_STUPM_Pos (3U)
23997#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)
23998#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk
23999#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
24000#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)
24001#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk
24002#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
24003#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)
24004#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk
24005#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
24006#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)
24007#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk
24008#define USB_OTG_DOEPMSK_OPEM_Pos (8U)
24009#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)
24010#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk
24011#define USB_OTG_DOEPMSK_BOIM_Pos (9U)
24012#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)
24013#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk
24014#define USB_OTG_DOEPMSK_BERRM_Pos (12U)
24015#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)
24016#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk
24017#define USB_OTG_DOEPMSK_NAKM_Pos (13U)
24018#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)
24019#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk
24020#define USB_OTG_DOEPMSK_NYETM_Pos (14U)
24021#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)
24022#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk
24024/******************** Bit definition forUSB_OTG_GINTSTS register ********************/
24025#define USB_OTG_GINTSTS_CMOD_Pos (0U)
24026#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)
24027#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk
24028#define USB_OTG_GINTSTS_MMIS_Pos (1U)
24029#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)
24030#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk
24031#define USB_OTG_GINTSTS_OTGINT_Pos (2U)
24032#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)
24033#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk
24034#define USB_OTG_GINTSTS_SOF_Pos (3U)
24035#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)
24036#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk
24037#define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
24038#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)
24039#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk
24040#define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
24041#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)
24042#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk
24043#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
24044#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)
24045#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk
24046#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
24047#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)
24048#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk
24049#define USB_OTG_GINTSTS_ESUSP_Pos (10U)
24050#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)
24051#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk
24052#define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
24053#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)
24054#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk
24055#define USB_OTG_GINTSTS_USBRST_Pos (12U)
24056#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)
24057#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk
24058#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
24059#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)
24060#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk
24061#define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
24062#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)
24063#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk
24064#define USB_OTG_GINTSTS_EOPF_Pos (15U)
24065#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)
24066#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk
24067#define USB_OTG_GINTSTS_IEPINT_Pos (18U)
24068#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)
24069#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk
24070#define USB_OTG_GINTSTS_OEPINT_Pos (19U)
24071#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)
24072#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk
24073#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
24074#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)
24075#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk
24076#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
24077#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)
24078#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk
24079#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
24080#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)
24081#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk
24082#define USB_OTG_GINTSTS_RSTDET_Pos (23U)
24083#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos)
24084#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk
24085#define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
24086#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)
24087#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk
24088#define USB_OTG_GINTSTS_HCINT_Pos (25U)
24089#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)
24090#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk
24091#define USB_OTG_GINTSTS_PTXFE_Pos (26U)
24092#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)
24093#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk
24094#define USB_OTG_GINTSTS_LPMINT_Pos (27U)
24095#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos)
24096#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk
24097#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
24098#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)
24099#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk
24100#define USB_OTG_GINTSTS_DISCINT_Pos (29U)
24101#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)
24102#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk
24103#define USB_OTG_GINTSTS_SRQINT_Pos (30U)
24104#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)
24105#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk
24106#define USB_OTG_GINTSTS_WKUINT_Pos (31U)
24107#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)
24108#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk
24110/******************** Bit definition forUSB_OTG_GINTMSK register ********************/
24111#define USB_OTG_GINTMSK_MMISM_Pos (1U)
24112#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)
24113#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk
24114#define USB_OTG_GINTMSK_OTGINT_Pos (2U)
24115#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)
24116#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk
24117#define USB_OTG_GINTMSK_SOFM_Pos (3U)
24118#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)
24119#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk
24120#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
24121#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)
24122#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk
24123#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
24124#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)
24125#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk
24126#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
24127#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)
24128#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk
24129#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
24130#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)
24131#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk
24132#define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
24133#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)
24134#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk
24135#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
24136#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)
24137#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk
24138#define USB_OTG_GINTMSK_USBRST_Pos (12U)
24139#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)
24140#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk
24141#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
24142#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)
24143#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk
24144#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
24145#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)
24146#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk
24147#define USB_OTG_GINTMSK_EOPFM_Pos (15U)
24148#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)
24149#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk
24150#define USB_OTG_GINTMSK_EPMISM_Pos (17U)
24151#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)
24152#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk
24153#define USB_OTG_GINTMSK_IEPINT_Pos (18U)
24154#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)
24155#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk
24156#define USB_OTG_GINTMSK_OEPINT_Pos (19U)
24157#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)
24158#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk
24159#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
24160#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)
24161#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk
24162#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
24163#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)
24164#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk
24165#define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
24166#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)
24167#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk
24168#define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
24169#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos)
24170#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk
24171#define USB_OTG_GINTMSK_PRTIM_Pos (24U)
24172#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)
24173#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk
24174#define USB_OTG_GINTMSK_HCIM_Pos (25U)
24175#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)
24176#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk
24177#define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
24178#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)
24179#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk
24180#define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
24181#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos)
24182#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk
24183#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
24184#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)
24185#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk
24186#define USB_OTG_GINTMSK_DISCINT_Pos (29U)
24187#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)
24188#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk
24189#define USB_OTG_GINTMSK_SRQIM_Pos (30U)
24190#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)
24191#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk
24192#define USB_OTG_GINTMSK_WUIM_Pos (31U)
24193#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)
24194#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk
24196/******************** Bit definition forUSB_OTG_DAINT register ********************/
24197#define USB_OTG_DAINT_IEPINT_Pos (0U)
24198#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)
24199#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk
24200#define USB_OTG_DAINT_OEPINT_Pos (16U)
24201#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)
24202#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk
24204/******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
24205#define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
24206#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)
24207#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk
24209/******************** Bit definition for USB_OTG_GRXSTSP register ********************/
24210#define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
24211#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)
24212#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk
24213#define USB_OTG_GRXSTSP_BCNT_Pos (4U)
24214#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)
24215#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk
24216#define USB_OTG_GRXSTSP_DPID_Pos (15U)
24217#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)
24218#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk
24219#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
24220#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)
24221#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk
24223/******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
24224#define USB_OTG_DAINTMSK_IEPM_Pos (0U)
24225#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)
24226#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk
24227#define USB_OTG_DAINTMSK_OEPM_Pos (16U)
24228#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)
24229#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk
24231/******************** Bit definition for OTG register ********************/
24232
24233#define USB_OTG_CHNUM_Pos (0U)
24234#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)
24235#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk
24236#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)
24237#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)
24238#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)
24239#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)
24240#define USB_OTG_BCNT_Pos (4U)
24241#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)
24242#define USB_OTG_BCNT USB_OTG_BCNT_Msk
24244#define USB_OTG_DPID_Pos (15U)
24245#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)
24246#define USB_OTG_DPID USB_OTG_DPID_Msk
24247#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)
24248#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)
24250#define USB_OTG_PKTSTS_Pos (17U)
24251#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)
24252#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk
24253#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)
24254#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)
24255#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)
24256#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)
24258#define USB_OTG_EPNUM_Pos (0U)
24259#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)
24260#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk
24261#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)
24262#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)
24263#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)
24264#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)
24266#define USB_OTG_FRMNUM_Pos (21U)
24267#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)
24268#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk
24269#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)
24270#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)
24271#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)
24272#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)
24274/******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
24275#define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
24276#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)
24277#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk
24279/******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
24280#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
24281#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)
24282#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk
24284/******************** Bit definition for OTG register ********************/
24285#define USB_OTG_NPTXFSA_Pos (0U)
24286#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)
24287#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk
24288#define USB_OTG_NPTXFD_Pos (16U)
24289#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)
24290#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk
24291#define USB_OTG_TX0FSA_Pos (0U)
24292#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)
24293#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk
24294#define USB_OTG_TX0FD_Pos (16U)
24295#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)
24296#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk
24298/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
24299#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
24300#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)
24301#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk
24303/******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
24304#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
24305#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)
24306#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk
24308#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
24309#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
24310#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk
24311#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
24312#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
24313#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
24314#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
24315#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
24316#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
24317#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
24318#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)
24320#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
24321#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
24322#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk
24323#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
24324#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
24325#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
24326#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
24327#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
24328#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
24329#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)
24331/******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
24332#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
24333#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)
24334#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk
24335#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
24336#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)
24337#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk
24339#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
24340#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
24341#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk
24342#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
24343#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
24344#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
24345#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
24346#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
24347#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
24348#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
24349#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
24350#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)
24351#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
24352#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)
24353#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk
24355#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
24356#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
24357#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk
24358#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
24359#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
24360#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
24361#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
24362#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
24363#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
24364#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
24365#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
24366#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)
24367#define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
24368#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)
24369#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk
24371/******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
24372#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
24373#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)
24374#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk
24376/******************** Bit definition forUSB_OTG_DEACHINT register ********************/
24377#define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
24378#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)
24379#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk
24380#define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
24381#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)
24382#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk
24384/******************** Bit definition forUSB_OTG_GCCFG register ********************/
24385#define USB_OTG_GCCFG_DCDET_Pos (0U)
24386#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos)
24387#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk
24388#define USB_OTG_GCCFG_PDET_Pos (1U)
24389#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos)
24390#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk
24391#define USB_OTG_GCCFG_SDET_Pos (2U)
24392#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos)
24393#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk
24394#define USB_OTG_GCCFG_PS2DET_Pos (3U)
24395#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos)
24396#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk
24397#define USB_OTG_GCCFG_PWRDWN_Pos (16U)
24398#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)
24399#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk
24400#define USB_OTG_GCCFG_BCDEN_Pos (17U)
24401#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos)
24402#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk
24403#define USB_OTG_GCCFG_DCDEN_Pos (18U)
24404#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos)
24405#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk
24406#define USB_OTG_GCCFG_PDEN_Pos (19U)
24407#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos)
24408#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk
24409#define USB_OTG_GCCFG_SDEN_Pos (20U)
24410#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos)
24411#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk
24412#define USB_OTG_GCCFG_VBDEN_Pos (21U)
24413#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos)
24414#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk
24416/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
24417#define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
24418#define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos)
24419#define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk
24420#define USB_OTG_GPWRDN_ADPIF_Pos (23U)
24421#define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos)
24422#define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk
24424/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
24425#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
24426#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)
24427#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk
24428#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
24429#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)
24430#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk
24432/******************** Bit definition forUSB_OTG_CID register ********************/
24433#define USB_OTG_CID_PRODUCT_ID_Pos (0U)
24434#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)
24435#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk
24437/******************** Bit definition for USB_OTG_GLPMCFG register ********************/
24438#define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
24439#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos)
24440#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk
24441#define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
24442#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos)
24443#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk
24444#define USB_OTG_GLPMCFG_BESL_Pos (2U)
24445#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos)
24446#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk
24447#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
24448#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos)
24449#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk
24450#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
24451#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos)
24452#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk
24453#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
24454#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos)
24455#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk
24456#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
24457#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos)
24458#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk
24459#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
24460#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos)
24461#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk
24462#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
24463#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos)
24464#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk
24465#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
24466#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos)
24467#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk
24468#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
24469#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos)
24470#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk
24471#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
24472#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos)
24473#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk
24474#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
24475#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos)
24476#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk
24477#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
24478#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos)
24479#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk
24480#define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
24481#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos)
24482#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk
24484/******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
24485#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
24486#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)
24487#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk
24488#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
24489#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)
24490#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk
24491#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
24492#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)
24493#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk
24494#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
24495#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)
24496#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk
24497#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
24498#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)
24499#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk
24500#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
24501#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)
24502#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk
24503#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
24504#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)
24505#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk
24506#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
24507#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)
24508#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk
24509#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
24510#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)
24511#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk
24513/******************** Bit definition forUSB_OTG_HPRT register ********************/
24514#define USB_OTG_HPRT_PCSTS_Pos (0U)
24515#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)
24516#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk
24517#define USB_OTG_HPRT_PCDET_Pos (1U)
24518#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)
24519#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk
24520#define USB_OTG_HPRT_PENA_Pos (2U)
24521#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)
24522#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk
24523#define USB_OTG_HPRT_PENCHNG_Pos (3U)
24524#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)
24525#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk
24526#define USB_OTG_HPRT_POCA_Pos (4U)
24527#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)
24528#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk
24529#define USB_OTG_HPRT_POCCHNG_Pos (5U)
24530#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)
24531#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk
24532#define USB_OTG_HPRT_PRES_Pos (6U)
24533#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)
24534#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk
24535#define USB_OTG_HPRT_PSUSP_Pos (7U)
24536#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)
24537#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk
24538#define USB_OTG_HPRT_PRST_Pos (8U)
24539#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)
24540#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk
24542#define USB_OTG_HPRT_PLSTS_Pos (10U)
24543#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)
24544#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk
24545#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)
24546#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)
24547#define USB_OTG_HPRT_PPWR_Pos (12U)
24548#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)
24549#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk
24551#define USB_OTG_HPRT_PTCTL_Pos (13U)
24552#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)
24553#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk
24554#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)
24555#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)
24556#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)
24557#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)
24559#define USB_OTG_HPRT_PSPD_Pos (17U)
24560#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)
24561#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk
24562#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)
24563#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)
24565/******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
24566#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
24567#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)
24568#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk
24569#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
24570#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)
24571#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk
24572#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
24573#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)
24574#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk
24575#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
24576#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)
24577#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk
24578#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
24579#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)
24580#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk
24581#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
24582#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)
24583#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk
24584#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
24585#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)
24586#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk
24587#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
24588#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)
24589#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk
24590#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
24591#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)
24592#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk
24593#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
24594#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)
24595#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk
24596#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
24597#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)
24598#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk
24600/******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
24601#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
24602#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)
24603#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk
24604#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
24605#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)
24606#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk
24608/******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
24609#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
24610#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)
24611#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk
24612#define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
24613#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)
24614#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk
24615#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
24616#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)
24617#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk
24618#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
24619#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)
24620#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk
24622#define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
24623#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)
24624#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk
24625#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)
24626#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)
24627#define USB_OTG_DIEPCTL_STALL_Pos (21U)
24628#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)
24629#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk
24631#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
24632#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)
24633#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk
24634#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
24635#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
24636#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
24637#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)
24638#define USB_OTG_DIEPCTL_CNAK_Pos (26U)
24639#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)
24640#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk
24641#define USB_OTG_DIEPCTL_SNAK_Pos (27U)
24642#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)
24643#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk
24644#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
24645#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)
24646#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk
24647#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
24648#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)
24649#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk
24650#define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
24651#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)
24652#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk
24653#define USB_OTG_DIEPCTL_EPENA_Pos (31U)
24654#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)
24655#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk
24657/******************** Bit definition forUSB_OTG_HCCHAR register ********************/
24658#define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
24659#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)
24660#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk
24662#define USB_OTG_HCCHAR_EPNUM_Pos (11U)
24663#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)
24664#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk
24665#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)
24666#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)
24667#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)
24668#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)
24669#define USB_OTG_HCCHAR_EPDIR_Pos (15U)
24670#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)
24671#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk
24672#define USB_OTG_HCCHAR_LSDEV_Pos (17U)
24673#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)
24674#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk
24676#define USB_OTG_HCCHAR_EPTYP_Pos (18U)
24677#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)
24678#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk
24679#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)
24680#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)
24682#define USB_OTG_HCCHAR_MC_Pos (20U)
24683#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)
24684#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk
24685#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)
24686#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)
24688#define USB_OTG_HCCHAR_DAD_Pos (22U)
24689#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)
24690#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk
24691#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)
24692#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)
24693#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)
24694#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)
24695#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)
24696#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)
24697#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)
24698#define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
24699#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)
24700#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk
24701#define USB_OTG_HCCHAR_CHDIS_Pos (30U)
24702#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)
24703#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk
24704#define USB_OTG_HCCHAR_CHENA_Pos (31U)
24705#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)
24706#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk
24708/******************** Bit definition forUSB_OTG_HCSPLT register ********************/
24709
24710#define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
24711#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)
24712#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk
24713#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)
24714#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)
24715#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)
24716#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)
24717#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)
24718#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)
24719#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)
24721#define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
24722#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)
24723#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk
24724#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)
24725#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)
24726#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)
24727#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)
24728#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)
24729#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)
24730#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)
24732#define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
24733#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)
24734#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk
24735#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)
24736#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)
24737#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
24738#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)
24739#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk
24740#define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
24741#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)
24742#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk
24744/******************** Bit definition forUSB_OTG_HCINT register ********************/
24745#define USB_OTG_HCINT_XFRC_Pos (0U)
24746#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)
24747#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk
24748#define USB_OTG_HCINT_CHH_Pos (1U)
24749#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)
24750#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk
24751#define USB_OTG_HCINT_AHBERR_Pos (2U)
24752#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)
24753#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk
24754#define USB_OTG_HCINT_STALL_Pos (3U)
24755#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)
24756#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk
24757#define USB_OTG_HCINT_NAK_Pos (4U)
24758#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)
24759#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk
24760#define USB_OTG_HCINT_ACK_Pos (5U)
24761#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)
24762#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk
24763#define USB_OTG_HCINT_NYET_Pos (6U)
24764#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)
24765#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk
24766#define USB_OTG_HCINT_TXERR_Pos (7U)
24767#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)
24768#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk
24769#define USB_OTG_HCINT_BBERR_Pos (8U)
24770#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)
24771#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk
24772#define USB_OTG_HCINT_FRMOR_Pos (9U)
24773#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)
24774#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk
24775#define USB_OTG_HCINT_DTERR_Pos (10U)
24776#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)
24777#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk
24779/******************** Bit definition forUSB_OTG_DIEPINT register ********************/
24780#define USB_OTG_DIEPINT_XFRC_Pos (0U)
24781#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)
24782#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk
24783#define USB_OTG_DIEPINT_EPDISD_Pos (1U)
24784#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)
24785#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk
24786#define USB_OTG_DIEPINT_AHBERR_Pos (2U)
24787#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)
24788#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk
24789#define USB_OTG_DIEPINT_TOC_Pos (3U)
24790#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)
24791#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk
24792#define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
24793#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)
24794#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk
24795#define USB_OTG_DIEPINT_INEPNM_Pos (5U)
24796#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)
24797#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk
24798#define USB_OTG_DIEPINT_INEPNE_Pos (6U)
24799#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)
24800#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk
24801#define USB_OTG_DIEPINT_TXFE_Pos (7U)
24802#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)
24803#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk
24804#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
24805#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)
24806#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk
24807#define USB_OTG_DIEPINT_BNA_Pos (9U)
24808#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)
24809#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk
24810#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
24811#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)
24812#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk
24813#define USB_OTG_DIEPINT_BERR_Pos (12U)
24814#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)
24815#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk
24816#define USB_OTG_DIEPINT_NAK_Pos (13U)
24817#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)
24818#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk
24820/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
24821#define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
24822#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)
24823#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk
24824#define USB_OTG_HCINTMSK_CHHM_Pos (1U)
24825#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)
24826#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk
24827#define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
24828#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)
24829#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk
24830#define USB_OTG_HCINTMSK_STALLM_Pos (3U)
24831#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)
24832#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk
24833#define USB_OTG_HCINTMSK_NAKM_Pos (4U)
24834#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)
24835#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk
24836#define USB_OTG_HCINTMSK_ACKM_Pos (5U)
24837#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)
24838#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk
24839#define USB_OTG_HCINTMSK_NYET_Pos (6U)
24840#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)
24841#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk
24842#define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
24843#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)
24844#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk
24845#define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
24846#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)
24847#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk
24848#define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
24849#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)
24850#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk
24851#define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
24852#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)
24853#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk
24855/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
24856
24857#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
24858#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)
24859#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk
24860#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
24861#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)
24862#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk
24863#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
24864#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)
24865#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk
24866/******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
24867#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
24868#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)
24869#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk
24870#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
24871#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)
24872#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk
24873#define USB_OTG_HCTSIZ_DOPING_Pos (31U)
24874#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)
24875#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk
24876#define USB_OTG_HCTSIZ_DPID_Pos (29U)
24877#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)
24878#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk
24879#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)
24880#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)
24882/******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
24883#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
24884#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)
24885#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk
24887/******************** Bit definition forUSB_OTG_HCDMA register ********************/
24888#define USB_OTG_HCDMA_DMAADDR_Pos (0U)
24889#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)
24890#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk
24892/******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
24893#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
24894#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)
24895#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk
24897/******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
24898#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
24899#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)
24900#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk
24901#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
24902#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)
24903#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk
24905/******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
24906
24907#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
24908#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)
24909#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk
24910#define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
24911#define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)
24912#define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk
24913#define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
24914#define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)
24915#define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk
24916#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
24917#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)
24918#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk
24919#define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
24920#define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)
24921#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk
24922#define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
24923#define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)
24924#define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk
24925#define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)
24926#define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)
24927#define USB_OTG_DOEPCTL_SNPM_Pos (20U)
24928#define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)
24929#define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk
24930#define USB_OTG_DOEPCTL_STALL_Pos (21U)
24931#define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)
24932#define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk
24933#define USB_OTG_DOEPCTL_CNAK_Pos (26U)
24934#define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)
24935#define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk
24936#define USB_OTG_DOEPCTL_SNAK_Pos (27U)
24937#define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)
24938#define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk
24939#define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
24940#define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)
24941#define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk
24942#define USB_OTG_DOEPCTL_EPENA_Pos (31U)
24943#define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)
24944#define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk
24946/******************** Bit definition forUSB_OTG_DOEPINT register ********************/
24947#define USB_OTG_DOEPINT_XFRC_Pos (0U)
24948#define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)
24949#define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk
24950#define USB_OTG_DOEPINT_EPDISD_Pos (1U)
24951#define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)
24952#define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk
24953#define USB_OTG_DOEPINT_AHBERR_Pos (2U)
24954#define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)
24955#define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk
24956#define USB_OTG_DOEPINT_STUP_Pos (3U)
24957#define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)
24958#define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk
24959#define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
24960#define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)
24961#define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk
24962#define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
24963#define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)
24964#define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk
24965#define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
24966#define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)
24967#define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk
24968#define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
24969#define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)
24970#define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk
24971#define USB_OTG_DOEPINT_BERR_Pos (12U)
24972#define USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos)
24973#define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk
24974#define USB_OTG_DOEPINT_NAK_Pos (13U)
24975#define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)
24976#define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk
24977#define USB_OTG_DOEPINT_NYET_Pos (14U)
24978#define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)
24979#define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk
24980#define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
24981#define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)
24982#define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk
24984/******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
24985
24986#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
24987#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)
24988#define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk
24989#define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
24990#define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)
24991#define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk
24993#define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
24994#define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
24995#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk
24996#define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
24997#define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)
24999/******************** Bit definition for PCGCCTL register ********************/
25000#define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
25001#define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)
25002#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk
25003#define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
25004#define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)
25005#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk
25006#define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
25007#define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)
25008#define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk
25022/******************************* ADC Instances ********************************/
25023#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
25024 ((INSTANCE) == ADC2) || \
25025 ((INSTANCE) == ADC3))
25026
25027#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
25028
25029#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
25030 ((INSTANCE) == ADC3_COMMON))
25031
25032/******************************** COMP Instances ******************************/
25033#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
25034 ((INSTANCE) == COMP2))
25035
25036#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
25037/******************** COMP Instances with window mode capability **************/
25038#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
25039
25040
25041/******************************* CRC Instances ********************************/
25042#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
25043
25044/******************************* DAC Instances ********************************/
25045#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
25046/******************************* DCMI Instances *******************************/
25047#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
25048
25049/******************************* DELAYBLOCK Instances *******************************/
25050#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \
25051 ((INSTANCE) == DLYB_SDMMC2) || \
25052 ((INSTANCE) == DLYB_QUADSPI))
25053/****************************** DFSDM Instances *******************************/
25054#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
25055 ((INSTANCE) == DFSDM1_Filter1) || \
25056 ((INSTANCE) == DFSDM1_Filter2) || \
25057 ((INSTANCE) == DFSDM1_Filter3))
25058
25059#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
25060 ((INSTANCE) == DFSDM1_Channel1) || \
25061 ((INSTANCE) == DFSDM1_Channel2) || \
25062 ((INSTANCE) == DFSDM1_Channel3) || \
25063 ((INSTANCE) == DFSDM1_Channel4) || \
25064 ((INSTANCE) == DFSDM1_Channel5) || \
25065 ((INSTANCE) == DFSDM1_Channel6) || \
25066 ((INSTANCE) == DFSDM1_Channel7))
25067/****************************** RAMECC Instances ******************************/
25068#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1) || \
25069 ((INSTANCE) == RAMECC1_Monitor2) || \
25070 ((INSTANCE) == RAMECC1_Monitor3) || \
25071 ((INSTANCE) == RAMECC1_Monitor4) || \
25072 ((INSTANCE) == RAMECC1_Monitor5) || \
25073 ((INSTANCE) == RAMECC2_Monitor1) || \
25074 ((INSTANCE) == RAMECC2_Monitor2) || \
25075 ((INSTANCE) == RAMECC2_Monitor3) || \
25076 ((INSTANCE) == RAMECC2_Monitor4) || \
25077 ((INSTANCE) == RAMECC2_Monitor5) || \
25078 ((INSTANCE) == RAMECC3_Monitor1) || \
25079 ((INSTANCE) == RAMECC3_Monitor2))
25080
25081/******************************** DMA Instances *******************************/
25082#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
25083 ((INSTANCE) == DMA1_Stream1) || \
25084 ((INSTANCE) == DMA1_Stream2) || \
25085 ((INSTANCE) == DMA1_Stream3) || \
25086 ((INSTANCE) == DMA1_Stream4) || \
25087 ((INSTANCE) == DMA1_Stream5) || \
25088 ((INSTANCE) == DMA1_Stream6) || \
25089 ((INSTANCE) == DMA1_Stream7) || \
25090 ((INSTANCE) == DMA2_Stream0) || \
25091 ((INSTANCE) == DMA2_Stream1) || \
25092 ((INSTANCE) == DMA2_Stream2) || \
25093 ((INSTANCE) == DMA2_Stream3) || \
25094 ((INSTANCE) == DMA2_Stream4) || \
25095 ((INSTANCE) == DMA2_Stream5) || \
25096 ((INSTANCE) == DMA2_Stream6) || \
25097 ((INSTANCE) == DMA2_Stream7) || \
25098 ((INSTANCE) == BDMA_Channel0) || \
25099 ((INSTANCE) == BDMA_Channel1) || \
25100 ((INSTANCE) == BDMA_Channel2) || \
25101 ((INSTANCE) == BDMA_Channel3) || \
25102 ((INSTANCE) == BDMA_Channel4) || \
25103 ((INSTANCE) == BDMA_Channel5) || \
25104 ((INSTANCE) == BDMA_Channel6) || \
25105 ((INSTANCE) == BDMA_Channel7))
25106
25107/****************************** BDMA CHANNEL Instances ***************************/
25108#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
25109 ((INSTANCE) == BDMA_Channel1) || \
25110 ((INSTANCE) == BDMA_Channel2) || \
25111 ((INSTANCE) == BDMA_Channel3) || \
25112 ((INSTANCE) == BDMA_Channel4) || \
25113 ((INSTANCE) == BDMA_Channel5) || \
25114 ((INSTANCE) == BDMA_Channel6) || \
25115 ((INSTANCE) == BDMA_Channel7))
25116
25117/****************************** DMA DMAMUX ALL Instances ***************************/
25118#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
25119 ((INSTANCE) == DMA1_Stream1) || \
25120 ((INSTANCE) == DMA1_Stream2) || \
25121 ((INSTANCE) == DMA1_Stream3) || \
25122 ((INSTANCE) == DMA1_Stream4) || \
25123 ((INSTANCE) == DMA1_Stream5) || \
25124 ((INSTANCE) == DMA1_Stream6) || \
25125 ((INSTANCE) == DMA1_Stream7) || \
25126 ((INSTANCE) == DMA2_Stream0) || \
25127 ((INSTANCE) == DMA2_Stream1) || \
25128 ((INSTANCE) == DMA2_Stream2) || \
25129 ((INSTANCE) == DMA2_Stream3) || \
25130 ((INSTANCE) == DMA2_Stream4) || \
25131 ((INSTANCE) == DMA2_Stream5) || \
25132 ((INSTANCE) == DMA2_Stream6) || \
25133 ((INSTANCE) == DMA2_Stream7) || \
25134 ((INSTANCE) == BDMA_Channel0) || \
25135 ((INSTANCE) == BDMA_Channel1) || \
25136 ((INSTANCE) == BDMA_Channel2) || \
25137 ((INSTANCE) == BDMA_Channel3) || \
25138 ((INSTANCE) == BDMA_Channel4) || \
25139 ((INSTANCE) == BDMA_Channel5) || \
25140 ((INSTANCE) == BDMA_Channel6) || \
25141 ((INSTANCE) == BDMA_Channel7))
25142
25143/****************************** BDMA DMAMUX Instances ***************************/
25144#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
25145 ((INSTANCE) == BDMA_Channel1) || \
25146 ((INSTANCE) == BDMA_Channel2) || \
25147 ((INSTANCE) == BDMA_Channel3) || \
25148 ((INSTANCE) == BDMA_Channel4) || \
25149 ((INSTANCE) == BDMA_Channel5) || \
25150 ((INSTANCE) == BDMA_Channel6) || \
25151 ((INSTANCE) == BDMA_Channel7))
25152
25153/****************************** DMA STREAM Instances ***************************/
25154#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
25155 ((INSTANCE) == DMA1_Stream1) || \
25156 ((INSTANCE) == DMA1_Stream2) || \
25157 ((INSTANCE) == DMA1_Stream3) || \
25158 ((INSTANCE) == DMA1_Stream4) || \
25159 ((INSTANCE) == DMA1_Stream5) || \
25160 ((INSTANCE) == DMA1_Stream6) || \
25161 ((INSTANCE) == DMA1_Stream7) || \
25162 ((INSTANCE) == DMA2_Stream0) || \
25163 ((INSTANCE) == DMA2_Stream1) || \
25164 ((INSTANCE) == DMA2_Stream2) || \
25165 ((INSTANCE) == DMA2_Stream3) || \
25166 ((INSTANCE) == DMA2_Stream4) || \
25167 ((INSTANCE) == DMA2_Stream5) || \
25168 ((INSTANCE) == DMA2_Stream6) || \
25169 ((INSTANCE) == DMA2_Stream7))
25170
25171/****************************** DMA DMAMUX Instances ***************************/
25172#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
25173 ((INSTANCE) == DMA1_Stream1) || \
25174 ((INSTANCE) == DMA1_Stream2) || \
25175 ((INSTANCE) == DMA1_Stream3) || \
25176 ((INSTANCE) == DMA1_Stream4) || \
25177 ((INSTANCE) == DMA1_Stream5) || \
25178 ((INSTANCE) == DMA1_Stream6) || \
25179 ((INSTANCE) == DMA1_Stream7) || \
25180 ((INSTANCE) == DMA2_Stream0) || \
25181 ((INSTANCE) == DMA2_Stream1) || \
25182 ((INSTANCE) == DMA2_Stream2) || \
25183 ((INSTANCE) == DMA2_Stream3) || \
25184 ((INSTANCE) == DMA2_Stream4) || \
25185 ((INSTANCE) == DMA2_Stream5) || \
25186 ((INSTANCE) == DMA2_Stream6) || \
25187 ((INSTANCE) == DMA2_Stream7))
25188
25189/******************************** DMA Request Generator Instances **************/
25190#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
25191 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
25192 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
25193 ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
25194 ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
25195 ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
25196 ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
25197 ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
25198 ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
25199 ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
25200 ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
25201 ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
25202 ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
25203 ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
25204 ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
25205 ((INSTANCE) == DMAMUX2_RequestGenerator7))
25206
25207/******************************* DMA2D Instances *******************************/
25208#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
25209
25210/******************************** MDMA Request Generator Instances **************/
25211#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
25212 ((INSTANCE) == MDMA_Channel1) || \
25213 ((INSTANCE) == MDMA_Channel2) || \
25214 ((INSTANCE) == MDMA_Channel3) || \
25215 ((INSTANCE) == MDMA_Channel4) || \
25216 ((INSTANCE) == MDMA_Channel5) || \
25217 ((INSTANCE) == MDMA_Channel6) || \
25218 ((INSTANCE) == MDMA_Channel7) || \
25219 ((INSTANCE) == MDMA_Channel8) || \
25220 ((INSTANCE) == MDMA_Channel9) || \
25221 ((INSTANCE) == MDMA_Channel10) || \
25222 ((INSTANCE) == MDMA_Channel11) || \
25223 ((INSTANCE) == MDMA_Channel12) || \
25224 ((INSTANCE) == MDMA_Channel13) || \
25225 ((INSTANCE) == MDMA_Channel14) || \
25226 ((INSTANCE) == MDMA_Channel15))
25227
25228/******************************* QUADSPI Instances *******************************/
25229#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
25230
25231/******************************* FDCAN Instances ******************************/
25232#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
25233 ((__INSTANCE__) == FDCAN2))
25234
25235#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
25236
25237/******************************* GPIO Instances *******************************/
25238#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
25239 ((INSTANCE) == GPIOB) || \
25240 ((INSTANCE) == GPIOC) || \
25241 ((INSTANCE) == GPIOD) || \
25242 ((INSTANCE) == GPIOE) || \
25243 ((INSTANCE) == GPIOF) || \
25244 ((INSTANCE) == GPIOG) || \
25245 ((INSTANCE) == GPIOH) || \
25246 ((INSTANCE) == GPIOI) || \
25247 ((INSTANCE) == GPIOJ) || \
25248 ((INSTANCE) == GPIOK))
25249
25250/******************************* GPIO AF Instances ****************************/
25251#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
25252
25253/**************************** GPIO Lock Instances *****************************/
25254/* On H7, all GPIO Bank support the Lock mechanism */
25255#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
25256
25257/******************************** HSEM Instances *******************************/
25258#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
25259#define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
25260#define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
25261#define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
25262
25263#define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
25264#define HSEM_SEMID_MAX (31U) /* HSEM ID Max */
25265
25266#define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
25267#define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
25268
25269#define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
25270#define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
25271
25272/******************************** I2C Instances *******************************/
25273#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
25274 ((INSTANCE) == I2C2) || \
25275 ((INSTANCE) == I2C3) || \
25276 ((INSTANCE) == I2C4))
25277
25278/****************************** SMBUS Instances *******************************/
25279#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
25280 ((INSTANCE) == I2C2) || \
25281 ((INSTANCE) == I2C3) || \
25282 ((INSTANCE) == I2C4))
25283
25284/************** I2C Instances : wakeup capability from stop modes *************/
25285#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
25286
25287/******************************** I2S Instances *******************************/
25288#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
25289 ((INSTANCE) == SPI2) || \
25290 ((INSTANCE) == SPI3))
25291
25292
25293/******************************* RNG Instances ********************************/
25294#define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
25295
25296/****************************** RTC Instances *********************************/
25297#define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
25298
25299/****************************** SDMMC Instances *********************************/
25300#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
25301 ((_INSTANCE_) == SDMMC2))
25302
25303/******************************** SPI Instances *******************************/
25304#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
25305 ((INSTANCE) == SPI2) || \
25306 ((INSTANCE) == SPI3) || \
25307 ((INSTANCE) == SPI4) || \
25308 ((INSTANCE) == SPI5) || \
25309 ((INSTANCE) == SPI6))
25310
25311#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
25312 ((INSTANCE) == SPI2) || \
25313 ((INSTANCE) == SPI3))
25314
25315/******************************** SWPMI Instances *****************************/
25316#define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
25317
25318/****************** LPTIM Instances : All supported instances *****************/
25319#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
25320 ((INSTANCE) == LPTIM2) || \
25321 ((INSTANCE) == LPTIM3) || \
25322 ((INSTANCE) == LPTIM4) || \
25323 ((INSTANCE) == LPTIM5))
25324
25325/****************** LPTIM Instances : supporting encoder interface **************/
25326#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
25327 ((INSTANCE) == LPTIM2))
25328
25329/****************** TIM Instances : All supported instances *******************/
25330#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25331 ((INSTANCE) == TIM2) || \
25332 ((INSTANCE) == TIM3) || \
25333 ((INSTANCE) == TIM4) || \
25334 ((INSTANCE) == TIM5) || \
25335 ((INSTANCE) == TIM6) || \
25336 ((INSTANCE) == TIM7) || \
25337 ((INSTANCE) == TIM8) || \
25338 ((INSTANCE) == TIM12) || \
25339 ((INSTANCE) == TIM13) || \
25340 ((INSTANCE) == TIM14) || \
25341 ((INSTANCE) == TIM15) || \
25342 ((INSTANCE) == TIM16) || \
25343 ((INSTANCE) == TIM17))
25344
25345/************* TIM Instances : at least 1 capture/compare channel *************/
25346#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25347 ((INSTANCE) == TIM2) || \
25348 ((INSTANCE) == TIM3) || \
25349 ((INSTANCE) == TIM4) || \
25350 ((INSTANCE) == TIM5) || \
25351 ((INSTANCE) == TIM8) || \
25352 ((INSTANCE) == TIM12) || \
25353 ((INSTANCE) == TIM13) || \
25354 ((INSTANCE) == TIM14) || \
25355 ((INSTANCE) == TIM15) || \
25356 ((INSTANCE) == TIM16) || \
25357 ((INSTANCE) == TIM17))
25358
25359/************ TIM Instances : at least 2 capture/compare channels *************/
25360#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25361 ((INSTANCE) == TIM2) || \
25362 ((INSTANCE) == TIM3) || \
25363 ((INSTANCE) == TIM4) || \
25364 ((INSTANCE) == TIM5) || \
25365 ((INSTANCE) == TIM8) || \
25366 ((INSTANCE) == TIM12) || \
25367 ((INSTANCE) == TIM15))
25368
25369/************ TIM Instances : at least 3 capture/compare channels *************/
25370#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25371 ((INSTANCE) == TIM2) || \
25372 ((INSTANCE) == TIM3) || \
25373 ((INSTANCE) == TIM4) || \
25374 ((INSTANCE) == TIM5) || \
25375 ((INSTANCE) == TIM8))
25376
25377/************ TIM Instances : at least 4 capture/compare channels *************/
25378#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25379 ((INSTANCE) == TIM2) || \
25380 ((INSTANCE) == TIM3) || \
25381 ((INSTANCE) == TIM4) || \
25382 ((INSTANCE) == TIM5) || \
25383 ((INSTANCE) == TIM8))
25384
25385/************ TIM Instances : at least 5 capture/compare channels *************/
25386#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25387 ((INSTANCE) == TIM8))
25388/************ TIM Instances : at least 6 capture/compare channels *************/
25389#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25390 ((INSTANCE) == TIM8))
25391
25392/******************** TIM Instances : Advanced-control timers *****************/
25393#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
25394 ((__INSTANCE__) == TIM8))
25395
25396/******************** TIM Instances : Advanced-control timers *****************/
25397
25398/******************* TIM Instances : Timer input XOR function *****************/
25399#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25400 ((INSTANCE) == TIM2) || \
25401 ((INSTANCE) == TIM3) || \
25402 ((INSTANCE) == TIM4) || \
25403 ((INSTANCE) == TIM5) || \
25404 ((INSTANCE) == TIM8) || \
25405 ((INSTANCE) == TIM15))
25406
25407/****************** TIM Instances : DMA requests generation (UDE) *************/
25408#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25409 ((INSTANCE) == TIM2) || \
25410 ((INSTANCE) == TIM3) || \
25411 ((INSTANCE) == TIM4) || \
25412 ((INSTANCE) == TIM5) || \
25413 ((INSTANCE) == TIM6) || \
25414 ((INSTANCE) == TIM7) || \
25415 ((INSTANCE) == TIM8) || \
25416 ((INSTANCE) == TIM15) || \
25417 ((INSTANCE) == TIM16) || \
25418 ((INSTANCE) == TIM17))
25419
25420/************ TIM Instances : DMA requests generation (CCxDE) *****************/
25421#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25422 ((INSTANCE) == TIM2) || \
25423 ((INSTANCE) == TIM3) || \
25424 ((INSTANCE) == TIM4) || \
25425 ((INSTANCE) == TIM5) || \
25426 ((INSTANCE) == TIM8) || \
25427 ((INSTANCE) == TIM15) || \
25428 ((INSTANCE) == TIM16) || \
25429 ((INSTANCE) == TIM17))
25430
25431/************ TIM Instances : DMA requests generation (COMDE) *****************/
25432#define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25433 ((INSTANCE) == TIM2) || \
25434 ((INSTANCE) == TIM3) || \
25435 ((INSTANCE) == TIM4) || \
25436 ((INSTANCE) == TIM5) || \
25437 ((INSTANCE) == TIM8) || \
25438 ((INSTANCE) == TIM15))
25439
25440/******************** TIM Instances : DMA burst feature ***********************/
25441#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25442 ((INSTANCE) == TIM2) || \
25443 ((INSTANCE) == TIM3) || \
25444 ((INSTANCE) == TIM4) || \
25445 ((INSTANCE) == TIM5) || \
25446 ((INSTANCE) == TIM8))
25447
25448/*************** TIM Instances : external trigger reamp input available *******/
25449#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25450 ((INSTANCE) == TIM2) || \
25451 ((INSTANCE) == TIM3) || \
25452 ((INSTANCE) == TIM4) || \
25453 ((INSTANCE) == TIM5) || \
25454 ((INSTANCE) == TIM8))
25455
25456/****************** TIM Instances : remapping capability **********************/
25457#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25458 ((INSTANCE) == TIM2) || \
25459 ((INSTANCE) == TIM3) || \
25460 ((INSTANCE) == TIM5) || \
25461 ((INSTANCE) == TIM8) || \
25462 ((INSTANCE) == TIM16) || \
25463 ((INSTANCE) == TIM17))
25464
25465/*************** TIM Instances : external trigger reamp input available *******/
25466#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25467 ((INSTANCE) == TIM2) || \
25468 ((INSTANCE) == TIM3) || \
25469 ((INSTANCE) == TIM5) || \
25470 ((INSTANCE) == TIM8))
25471
25472/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
25473#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25474 ((INSTANCE) == TIM2) || \
25475 ((INSTANCE) == TIM3) || \
25476 ((INSTANCE) == TIM4) || \
25477 ((INSTANCE) == TIM5) || \
25478 ((INSTANCE) == TIM6) || \
25479 ((INSTANCE) == TIM7) || \
25480 ((INSTANCE) == TIM8) || \
25481 ((INSTANCE) == TIM12) || \
25482 ((INSTANCE) == TIM15))
25483
25484/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
25485#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25486 ((INSTANCE) == TIM2) || \
25487 ((INSTANCE) == TIM3) || \
25488 ((INSTANCE) == TIM4) || \
25489 ((INSTANCE) == TIM5) || \
25490 ((INSTANCE) == TIM8) || \
25491 ((INSTANCE) == TIM12) || \
25492 ((INSTANCE) == TIM15))
25493
25494/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
25495#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25496 ((INSTANCE) == TIM8))
25497
25498/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
25499#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25500 ((INSTANCE) == TIM2) || \
25501 ((INSTANCE) == TIM3) || \
25502 ((INSTANCE) == TIM4) || \
25503 ((INSTANCE) == TIM5) || \
25504 ((INSTANCE) == TIM8) || \
25505 ((INSTANCE) == TIM15) || \
25506 ((INSTANCE) == TIM16) || \
25507 ((INSTANCE) == TIM17))
25508
25509/****************** TIM Instances : supporting commutation event *************/
25510#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25511 ((INSTANCE) == TIM8) || \
25512 ((INSTANCE) == TIM15) || \
25513 ((INSTANCE) == TIM16) || \
25514 ((INSTANCE) == TIM17))
25515
25516/****************** TIM Instances : supporting encoder interface **************/
25517#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
25518 ((__INSTANCE__) == TIM2) || \
25519 ((__INSTANCE__) == TIM3) || \
25520 ((__INSTANCE__) == TIM4) || \
25521 ((__INSTANCE__) == TIM5) || \
25522 ((__INSTANCE__) == TIM8))
25523
25524/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
25525#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25526 ((INSTANCE) == TIM8))
25527/******************* TIM Instances : output(s) available **********************/
25528#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
25529 ((((INSTANCE) == TIM1) && \
25530 (((CHANNEL) == TIM_CHANNEL_1) || \
25531 ((CHANNEL) == TIM_CHANNEL_2) || \
25532 ((CHANNEL) == TIM_CHANNEL_3) || \
25533 ((CHANNEL) == TIM_CHANNEL_4) || \
25534 ((CHANNEL) == TIM_CHANNEL_5) || \
25535 ((CHANNEL) == TIM_CHANNEL_6))) \
25536 || \
25537 (((INSTANCE) == TIM2) && \
25538 (((CHANNEL) == TIM_CHANNEL_1) || \
25539 ((CHANNEL) == TIM_CHANNEL_2) || \
25540 ((CHANNEL) == TIM_CHANNEL_3) || \
25541 ((CHANNEL) == TIM_CHANNEL_4))) \
25542 || \
25543 (((INSTANCE) == TIM3) && \
25544 (((CHANNEL) == TIM_CHANNEL_1)|| \
25545 ((CHANNEL) == TIM_CHANNEL_2) || \
25546 ((CHANNEL) == TIM_CHANNEL_3) || \
25547 ((CHANNEL) == TIM_CHANNEL_4))) \
25548 || \
25549 (((INSTANCE) == TIM4) && \
25550 (((CHANNEL) == TIM_CHANNEL_1) || \
25551 ((CHANNEL) == TIM_CHANNEL_2) || \
25552 ((CHANNEL) == TIM_CHANNEL_3) || \
25553 ((CHANNEL) == TIM_CHANNEL_4))) \
25554 || \
25555 (((INSTANCE) == TIM5) && \
25556 (((CHANNEL) == TIM_CHANNEL_1) || \
25557 ((CHANNEL) == TIM_CHANNEL_2) || \
25558 ((CHANNEL) == TIM_CHANNEL_3) || \
25559 ((CHANNEL) == TIM_CHANNEL_4))) \
25560 || \
25561 (((INSTANCE) == TIM8) && \
25562 (((CHANNEL) == TIM_CHANNEL_1) || \
25563 ((CHANNEL) == TIM_CHANNEL_2) || \
25564 ((CHANNEL) == TIM_CHANNEL_3) || \
25565 ((CHANNEL) == TIM_CHANNEL_4) || \
25566 ((CHANNEL) == TIM_CHANNEL_5) || \
25567 ((CHANNEL) == TIM_CHANNEL_6))) \
25568 || \
25569 (((INSTANCE) == TIM12) && \
25570 (((CHANNEL) == TIM_CHANNEL_1) || \
25571 ((CHANNEL) == TIM_CHANNEL_2))) \
25572 || \
25573 (((INSTANCE) == TIM13) && \
25574 (((CHANNEL) == TIM_CHANNEL_1))) \
25575 || \
25576 (((INSTANCE) == TIM14) && \
25577 (((CHANNEL) == TIM_CHANNEL_1))) \
25578 || \
25579 (((INSTANCE) == TIM15) && \
25580 (((CHANNEL) == TIM_CHANNEL_1) || \
25581 ((CHANNEL) == TIM_CHANNEL_2))) \
25582 || \
25583 (((INSTANCE) == TIM16) && \
25584 (((CHANNEL) == TIM_CHANNEL_1))) \
25585 || \
25586 (((INSTANCE) == TIM17) && \
25587 (((CHANNEL) == TIM_CHANNEL_1))))
25588
25589/****************** TIM Instances : supporting the break function *************/
25590#define IS_TIM_BREAK_INSTANCE(INSTANCE)\
25591 (((INSTANCE) == TIM1) || \
25592 ((INSTANCE) == TIM8) || \
25593 ((INSTANCE) == TIM15) || \
25594 ((INSTANCE) == TIM16) || \
25595 ((INSTANCE) == TIM17))
25596
25597/************** TIM Instances : supporting Break source selection *************/
25598#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25599 ((INSTANCE) == TIM8))
25600
25601/****************** TIM Instances : supporting complementary output(s) ********/
25602#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
25603 ((((INSTANCE) == TIM1) && \
25604 (((CHANNEL) == TIM_CHANNEL_1) || \
25605 ((CHANNEL) == TIM_CHANNEL_2) || \
25606 ((CHANNEL) == TIM_CHANNEL_3))) \
25607 || \
25608 (((INSTANCE) == TIM8) && \
25609 (((CHANNEL) == TIM_CHANNEL_1) || \
25610 ((CHANNEL) == TIM_CHANNEL_2) || \
25611 ((CHANNEL) == TIM_CHANNEL_3))) \
25612 || \
25613 (((INSTANCE) == TIM15) && \
25614 ((CHANNEL) == TIM_CHANNEL_1)) \
25615 || \
25616 (((INSTANCE) == TIM16) && \
25617 ((CHANNEL) == TIM_CHANNEL_1)) \
25618 || \
25619 (((INSTANCE) == TIM17) && \
25620 ((CHANNEL) == TIM_CHANNEL_1)))
25621
25622/****************** TIM Instances : supporting counting mode selection ********/
25623#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
25624 (((INSTANCE) == TIM1) || \
25625 ((INSTANCE) == TIM2) || \
25626 ((INSTANCE) == TIM3) || \
25627 ((INSTANCE) == TIM4) || \
25628 ((INSTANCE) == TIM5) || \
25629 ((INSTANCE) == TIM8))
25630
25631/****************** TIM Instances : supporting repetition counter *************/
25632#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
25633 (((INSTANCE) == TIM1) || \
25634 ((INSTANCE) == TIM8) || \
25635 ((INSTANCE) == TIM15) || \
25636 ((INSTANCE) == TIM16) || \
25637 ((INSTANCE) == TIM17))
25638
25639/****************** TIM Instances : supporting synchronization ****************/
25640#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
25641 (((__INSTANCE__) == TIM1) || \
25642 ((__INSTANCE__) == TIM2) || \
25643 ((__INSTANCE__) == TIM3) || \
25644 ((__INSTANCE__) == TIM4) || \
25645 ((__INSTANCE__) == TIM5) || \
25646 ((__INSTANCE__) == TIM6) || \
25647 ((__INSTANCE__) == TIM8) || \
25648 ((__INSTANCE__) == TIM12) || \
25649 ((__INSTANCE__) == TIM15))
25650
25651/****************** TIM Instances : supporting clock division *****************/
25652#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
25653 (((INSTANCE) == TIM1) || \
25654 ((INSTANCE) == TIM2) || \
25655 ((INSTANCE) == TIM3) || \
25656 ((INSTANCE) == TIM4) || \
25657 ((INSTANCE) == TIM5) || \
25658 ((INSTANCE) == TIM8) || \
25659 ((INSTANCE) == TIM15) || \
25660 ((INSTANCE) == TIM16) || \
25661 ((INSTANCE) == TIM17))
25662
25663/****************** TIM Instances : supporting external clock mode 1 for ETRF input */
25664#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
25665 (((INSTANCE) == TIM1) || \
25666 ((INSTANCE) == TIM2) || \
25667 ((INSTANCE) == TIM3) || \
25668 ((INSTANCE) == TIM4) || \
25669 ((INSTANCE) == TIM5) || \
25670 ((INSTANCE) == TIM8))
25671
25672/****************** TIM Instances : supporting external clock mode 2 **********/
25673#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
25674 (((INSTANCE) == TIM1) || \
25675 ((INSTANCE) == TIM2) || \
25676 ((INSTANCE) == TIM3) || \
25677 ((INSTANCE) == TIM4) || \
25678 ((INSTANCE) == TIM5) || \
25679 ((INSTANCE) == TIM8))
25680
25681/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
25682#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
25683 (((INSTANCE) == TIM1) || \
25684 ((INSTANCE) == TIM2) || \
25685 ((INSTANCE) == TIM3) || \
25686 ((INSTANCE) == TIM4) || \
25687 ((INSTANCE) == TIM5) || \
25688 ((INSTANCE) == TIM8) || \
25689 ((INSTANCE) == TIM12) || \
25690 ((INSTANCE) == TIM15))
25691
25692/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
25693#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
25694 (((INSTANCE) == TIM1) || \
25695 ((INSTANCE) == TIM2) || \
25696 ((INSTANCE) == TIM3) || \
25697 ((INSTANCE) == TIM4) || \
25698 ((INSTANCE) == TIM5) || \
25699 ((INSTANCE) == TIM8) || \
25700 ((INSTANCE) == TIM12) || \
25701 ((INSTANCE) == TIM15))
25702
25703/****************** TIM Instances : supporting OCxREF clear *******************/
25704#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
25705 (((INSTANCE) == TIM1) || \
25706 ((INSTANCE) == TIM2) || \
25707 ((INSTANCE) == TIM3))
25708
25709/****************** TIM Instances : TIM_32B_COUNTER ***************************/
25710#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
25711 (((INSTANCE) == TIM2) || \
25712 ((INSTANCE) == TIM5))
25713
25714/****************** TIM Instances : TIM_BKIN2 ***************************/
25715#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
25716 (((INSTANCE) == TIM1) || \
25717 ((INSTANCE) == TIM8))
25718
25719/****************** TIM Instances : supporting Hall sensor interface **********/
25720#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
25721 ((__INSTANCE__) == TIM2) || \
25722 ((__INSTANCE__) == TIM3) || \
25723 ((__INSTANCE__) == TIM4) || \
25724 ((__INSTANCE__) == TIM5) || \
25725 ((__INSTANCE__) == TIM15) || \
25726 ((__INSTANCE__) == TIM8))
25727
25728/****************************** HRTIM Instances *******************************/
25729#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
25730
25731/******************** USART Instances : Synchronous mode **********************/
25732#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25733 ((INSTANCE) == USART2) || \
25734 ((INSTANCE) == USART3) || \
25735 ((INSTANCE) == USART6))
25736
25737/******************** USART Instances : SPI slave mode ************************/
25738#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25739 ((INSTANCE) == USART2) || \
25740 ((INSTANCE) == USART3) || \
25741 ((INSTANCE) == USART6))
25742
25743/******************** UART Instances : Asynchronous mode **********************/
25744#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25745 ((INSTANCE) == USART2) || \
25746 ((INSTANCE) == USART3) || \
25747 ((INSTANCE) == UART4) || \
25748 ((INSTANCE) == UART5) || \
25749 ((INSTANCE) == USART6) || \
25750 ((INSTANCE) == UART7) || \
25751 ((INSTANCE) == UART8))
25752
25753/******************** UART Instances : FIFO mode.******************************/
25754#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25755 ((INSTANCE) == USART2) || \
25756 ((INSTANCE) == USART3) || \
25757 ((INSTANCE) == UART4) || \
25758 ((INSTANCE) == UART5) || \
25759 ((INSTANCE) == USART6) || \
25760 ((INSTANCE) == UART7) || \
25761 ((INSTANCE) == UART8))
25762
25763/****************** UART Instances : Auto Baud Rate detection *****************/
25764#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25765 ((INSTANCE) == USART2) || \
25766 ((INSTANCE) == USART3) || \
25767 ((INSTANCE) == UART4) || \
25768 ((INSTANCE) == UART5) || \
25769 ((INSTANCE) == USART6) || \
25770 ((INSTANCE) == UART7) || \
25771 ((INSTANCE) == UART8))
25772
25773/*********************** UART Instances : Driver Enable ***********************/
25774#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25775 ((INSTANCE) == USART2) || \
25776 ((INSTANCE) == USART3) || \
25777 ((INSTANCE) == UART4) || \
25778 ((INSTANCE) == UART5) || \
25779 ((INSTANCE) == USART6) || \
25780 ((INSTANCE) == UART7) || \
25781 ((INSTANCE) == UART8) || \
25782 ((INSTANCE) == LPUART1))
25783
25784/********************* UART Instances : Half-Duplex mode **********************/
25785#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25786 ((INSTANCE) == USART2) || \
25787 ((INSTANCE) == USART3) || \
25788 ((INSTANCE) == UART4) || \
25789 ((INSTANCE) == UART5) || \
25790 ((INSTANCE) == USART6) || \
25791 ((INSTANCE) == UART7) || \
25792 ((INSTANCE) == UART8) || \
25793 ((INSTANCE) == LPUART1))
25794
25795/******************* UART Instances : Hardware Flow control *******************/
25796#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25797 ((INSTANCE) == USART2) || \
25798 ((INSTANCE) == USART3) || \
25799 ((INSTANCE) == UART4) || \
25800 ((INSTANCE) == UART5) || \
25801 ((INSTANCE) == USART6) || \
25802 ((INSTANCE) == UART7) || \
25803 ((INSTANCE) == UART8) || \
25804 ((INSTANCE) == LPUART1))
25805
25806/************************* UART Instances : LIN mode **************************/
25807#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25808 ((INSTANCE) == USART2) || \
25809 ((INSTANCE) == USART3) || \
25810 ((INSTANCE) == UART4) || \
25811 ((INSTANCE) == UART5) || \
25812 ((INSTANCE) == USART6) || \
25813 ((INSTANCE) == UART7) || \
25814 ((INSTANCE) == UART8))
25815
25816/****************** UART Instances : Wake-up from Stop mode *******************/
25817#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25818 ((INSTANCE) == USART2) || \
25819 ((INSTANCE) == USART3) || \
25820 ((INSTANCE) == UART4) || \
25821 ((INSTANCE) == UART5) || \
25822 ((INSTANCE) == USART6) || \
25823 ((INSTANCE) == UART7) || \
25824 ((INSTANCE) == UART8) || \
25825 ((INSTANCE) == LPUART1))
25826
25827/************************* UART Instances : IRDA mode *************************/
25828#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25829 ((INSTANCE) == USART2) || \
25830 ((INSTANCE) == USART3) || \
25831 ((INSTANCE) == UART4) || \
25832 ((INSTANCE) == UART5) || \
25833 ((INSTANCE) == USART6) || \
25834 ((INSTANCE) == UART7) || \
25835 ((INSTANCE) == UART8))
25836
25837/********************* USART Instances : Smard card mode **********************/
25838#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25839 ((INSTANCE) == USART2) || \
25840 ((INSTANCE) == USART3) || \
25841 ((INSTANCE) == USART6))
25842
25843/****************************** LPUART Instance *******************************/
25844#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
25845
25846/****************************** IWDG Instances ********************************/
25847#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1)
25848/****************************** USB Instances ********************************/
25849#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
25850
25851/****************************** WWDG Instances ********************************/
25852#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1)
25853/****************************** MDIOS Instances ********************************/
25854#define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
25855
25856/****************************** CEC Instances *********************************/
25857#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
25858
25859/****************************** SAI Instances ********************************/
25860#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
25861 ((INSTANCE) == SAI1_Block_B) || \
25862 ((INSTANCE) == SAI2_Block_A) || \
25863 ((INSTANCE) == SAI2_Block_B) || \
25864 ((INSTANCE) == SAI3_Block_A) || \
25865 ((INSTANCE) == SAI3_Block_B) || \
25866 ((INSTANCE) == SAI4_Block_A) || \
25867 ((INSTANCE) == SAI4_Block_B))
25868
25869/****************************** SPDIFRX Instances ********************************/
25870#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
25871
25872/****************************** OPAMP Instances *******************************/
25873#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
25874 ((INSTANCE) == OPAMP2))
25875
25876#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
25877
25878/*********************** USB OTG PCD Instances ********************************/
25879#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
25880 ((INSTANCE) == USB_OTG_HS))
25881
25882/*********************** USB OTG HCD Instances ********************************/
25883#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
25884 ((INSTANCE) == USB_OTG_HS))
25885
25886/******************************************************************************/
25887/* For a painless codes migration between the STM32H7xx device product */
25888/* lines, or with STM32F7xx devices the aliases defined below are put */
25889/* in place to overcome the differences in the interrupt handlers and IRQn */
25890/* definitions. No need to update developed interrupt code when moving */
25891/* across product lines within the same STM32H7 Family */
25892/******************************************************************************/
25893
25894/* Aliases for __IRQn */
25895#define HASH_RNG_IRQn RNG_IRQn
25896#define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
25897#define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
25898#define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
25899#define PVD_IRQn PVD_AVD_IRQn
25900
25901
25902
25903/* Aliases for __IRQHandler */
25904#define HASH_RNG_IRQHandler RNG_IRQHandler
25905#define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
25906#define TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler
25907#define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
25908#define PVD_IRQHandler PVD_AVD_IRQHandler
25909
25910/* Aliases for COMP __IRQHandler */
25911#define COMP_IRQHandler COMP1_IRQHandler
25912
25925#ifdef __cplusplus
25926}
25927#endif /* __cplusplus */
25928
25929#endif /* STM32H742xx_H */
25930
__IO
#define __IO
Definition: core_cm4.h:239
__I
#define __I
Definition: core_cm4.h:236
core_cm7.h
CMSIS Cortex-M7 Core Peripheral Access Layer Header File.
IRQn_Type
IRQn_Type
STM32H7XX Interrupt Number Definition, according to the selected device in Library_configuration_sect...
Definition: stm32h742xx.h:49
CRS_IRQn
@ CRS_IRQn
Definition: stm32h742xx.h:193
PendSV_IRQn
@ PendSV_IRQn
Definition: stm32h742xx.h:58
ETH_WKUP_IRQn
@ ETH_WKUP_IRQn
Definition: stm32h742xx.h:122
EXTI2_IRQn
@ EXTI2_IRQn
Definition: stm32h742xx.h:69
MDIOS_IRQn
@ MDIOS_IRQn
Definition: stm32h742xx.h:173
DMA1_Stream2_IRQn
@ DMA1_Stream2_IRQn
Definition: stm32h742xx.h:74
HRTIM1_TIMB_IRQn
@ HRTIM1_TIMB_IRQn
Definition: stm32h742xx.h:158
BDMA_Channel7_IRQn
@ BDMA_Channel7_IRQn
Definition: stm32h742xx.h:186
RTC_WKUP_IRQn
@ RTC_WKUP_IRQn
Definition: stm32h742xx.h:64
SPDIF_RX_IRQn
@ SPDIF_RX_IRQn
Definition: stm32h742xx.h:150
OTG_HS_EP1_IN_IRQn
@ OTG_HS_EP1_IN_IRQn
Definition: stm32h742xx.h:131
HRTIM1_Master_IRQn
@ HRTIM1_Master_IRQn
Definition: stm32h742xx.h:156
DMA2_Stream0_IRQn
@ DMA2_Stream0_IRQn
Definition: stm32h742xx.h:116
BDMA_Channel3_IRQn
@ BDMA_Channel3_IRQn
Definition: stm32h742xx.h:182
DMA2_Stream6_IRQn
@ DMA2_Stream6_IRQn
Definition: stm32h742xx.h:125
LPTIM3_IRQn
@ LPTIM3_IRQn
Definition: stm32h742xx.h:189
LPTIM4_IRQn
@ LPTIM4_IRQn
Definition: stm32h742xx.h:190
TIM15_IRQn
@ TIM15_IRQn
Definition: stm32h742xx.h:169
BDMA_Channel1_IRQn
@ BDMA_Channel1_IRQn
Definition: stm32h742xx.h:180
OTG_FS_EP1_IN_IRQn
@ OTG_FS_EP1_IN_IRQn
Definition: stm32h742xx.h:152
UART7_IRQn
@ UART7_IRQn
Definition: stm32h742xx.h:137
I2C1_ER_IRQn
@ I2C1_ER_IRQn
Definition: stm32h742xx.h:93
I2C2_EV_IRQn
@ I2C2_EV_IRQn
Definition: stm32h742xx.h:94
MemoryManagement_IRQn
@ MemoryManagement_IRQn
Definition: stm32h742xx.h:53
TIM17_IRQn
@ TIM17_IRQn
Definition: stm32h742xx.h:171
SAI1_IRQn
@ SAI1_IRQn
Definition: stm32h742xx.h:142
TIM4_IRQn
@ TIM4_IRQn
Definition: stm32h742xx.h:91
TIM2_IRQn
@ TIM2_IRQn
Definition: stm32h742xx.h:89
DMA2_Stream7_IRQn
@ DMA2_Stream7_IRQn
Definition: stm32h742xx.h:126
TIM8_BRK_TIM12_IRQn
@ TIM8_BRK_TIM12_IRQn
Definition: stm32h742xx.h:103
FDCAN1_IT0_IRQn
@ FDCAN1_IT0_IRQn
Definition: stm32h742xx.h:80
USART2_IRQn
@ USART2_IRQn
Definition: stm32h742xx.h:99
DMA2_Stream3_IRQn
@ DMA2_Stream3_IRQn
Definition: stm32h742xx.h:119
HRTIM1_FLT_IRQn
@ HRTIM1_FLT_IRQn
Definition: stm32h742xx.h:162
BDMA_Channel4_IRQn
@ BDMA_Channel4_IRQn
Definition: stm32h742xx.h:183
SVCall_IRQn
@ SVCall_IRQn
Definition: stm32h742xx.h:56
ADC_IRQn
@ ADC_IRQn
Definition: stm32h742xx.h:79
SPI3_IRQn
@ SPI3_IRQn
Definition: stm32h742xx.h:111
SPI2_IRQn
@ SPI2_IRQn
Definition: stm32h742xx.h:97
TIM1_BRK_IRQn
@ TIM1_BRK_IRQn
Definition: stm32h742xx.h:85
TIM7_IRQn
@ TIM7_IRQn
Definition: stm32h742xx.h:115
UART8_IRQn
@ UART8_IRQn
Definition: stm32h742xx.h:138
FDCAN2_IT0_IRQn
@ FDCAN2_IT0_IRQn
Definition: stm32h742xx.h:81
RCC_IRQn
@ RCC_IRQn
Definition: stm32h742xx.h:66
ADC3_IRQn
@ ADC3_IRQn
Definition: stm32h742xx.h:177
LPTIM2_IRQn
@ LPTIM2_IRQn
Definition: stm32h742xx.h:188
TIM6_DAC_IRQn
@ TIM6_DAC_IRQn
Definition: stm32h742xx.h:114
OTG_HS_EP1_OUT_IRQn
@ OTG_HS_EP1_OUT_IRQn
Definition: stm32h742xx.h:130
I2C2_ER_IRQn
@ I2C2_ER_IRQn
Definition: stm32h742xx.h:95
QUADSPI_IRQn
@ QUADSPI_IRQn
Definition: stm32h742xx.h:145
DFSDM1_FLT0_IRQn
@ DFSDM1_FLT0_IRQn
Definition: stm32h742xx.h:163
TIM8_CC_IRQn
@ TIM8_CC_IRQn
Definition: stm32h742xx.h:106
UsageFault_IRQn
@ UsageFault_IRQn
Definition: stm32h742xx.h:55
DMAMUX2_OVR_IRQn
@ DMAMUX2_OVR_IRQn
Definition: stm32h742xx.h:178
I2C4_ER_IRQn
@ I2C4_ER_IRQn
Definition: stm32h742xx.h:149
SysTick_IRQn
@ SysTick_IRQn
Definition: stm32h742xx.h:59
I2C3_ER_IRQn
@ I2C3_ER_IRQn
Definition: stm32h742xx.h:129
SAI4_IRQn
@ SAI4_IRQn
Definition: stm32h742xx.h:195
DFSDM1_FLT3_IRQn
@ DFSDM1_FLT3_IRQn
Definition: stm32h742xx.h:166
TIM1_UP_IRQn
@ TIM1_UP_IRQn
Definition: stm32h742xx.h:86
I2C3_EV_IRQn
@ I2C3_EV_IRQn
Definition: stm32h742xx.h:128
BusFault_IRQn
@ BusFault_IRQn
Definition: stm32h742xx.h:54
DMAMUX1_OVR_IRQn
@ DMAMUX1_OVR_IRQn
Definition: stm32h742xx.h:155
CEC_IRQn
@ CEC_IRQn
Definition: stm32h742xx.h:147
LPTIM5_IRQn
@ LPTIM5_IRQn
Definition: stm32h742xx.h:191
SPI5_IRQn
@ SPI5_IRQn
Definition: stm32h742xx.h:140
DebugMonitor_IRQn
@ DebugMonitor_IRQn
Definition: stm32h742xx.h:57
RNG_IRQn
@ RNG_IRQn
Definition: stm32h742xx.h:135
FLASH_IRQn
@ FLASH_IRQn
Definition: stm32h742xx.h:65
SWPMI1_IRQn
@ SWPMI1_IRQn
Definition: stm32h742xx.h:168
DMA2_Stream5_IRQn
@ DMA2_Stream5_IRQn
Definition: stm32h742xx.h:124
WWDG_IRQn
@ WWDG_IRQn
Definition: stm32h742xx.h:61
HRTIM1_TIMA_IRQn
@ HRTIM1_TIMA_IRQn
Definition: stm32h742xx.h:157
I2C1_EV_IRQn
@ I2C1_EV_IRQn
Definition: stm32h742xx.h:92
TIM3_IRQn
@ TIM3_IRQn
Definition: stm32h742xx.h:90
DMA2_Stream1_IRQn
@ DMA2_Stream1_IRQn
Definition: stm32h742xx.h:117
OTG_HS_WKUP_IRQn
@ OTG_HS_WKUP_IRQn
Definition: stm32h742xx.h:132
SDMMC1_IRQn
@ SDMMC1_IRQn
Definition: stm32h742xx.h:109
DMA1_Stream0_IRQn
@ DMA1_Stream0_IRQn
Definition: stm32h742xx.h:72
EXTI15_10_IRQn
@ EXTI15_10_IRQn
Definition: stm32h742xx.h:101
SPI4_IRQn
@ SPI4_IRQn
Definition: stm32h742xx.h:139
EXTI9_5_IRQn
@ EXTI9_5_IRQn
Definition: stm32h742xx.h:84
DMA1_Stream1_IRQn
@ DMA1_Stream1_IRQn
Definition: stm32h742xx.h:73
LPTIM1_IRQn
@ LPTIM1_IRQn
Definition: stm32h742xx.h:146
SPI6_IRQn
@ SPI6_IRQn
Definition: stm32h742xx.h:141
OTG_FS_IRQn
@ OTG_FS_IRQn
Definition: stm32h742xx.h:154
OTG_FS_WKUP_IRQn
@ OTG_FS_WKUP_IRQn
Definition: stm32h742xx.h:153
FPU_IRQn
@ FPU_IRQn
Definition: stm32h742xx.h:136
TIM8_UP_TIM13_IRQn
@ TIM8_UP_TIM13_IRQn
Definition: stm32h742xx.h:104
USART6_IRQn
@ USART6_IRQn
Definition: stm32h742xx.h:127
SPI1_IRQn
@ SPI1_IRQn
Definition: stm32h742xx.h:96
OTG_HS_IRQn
@ OTG_HS_IRQn
Definition: stm32h742xx.h:133
HSEM1_IRQn
@ HSEM1_IRQn
Definition: stm32h742xx.h:176
OTG_FS_EP1_OUT_IRQn
@ OTG_FS_EP1_OUT_IRQn
Definition: stm32h742xx.h:151
DFSDM1_FLT2_IRQn
@ DFSDM1_FLT2_IRQn
Definition: stm32h742xx.h:165
HardFault_IRQn
@ HardFault_IRQn
Definition: stm32h742xx.h:52
BDMA_Channel6_IRQn
@ BDMA_Channel6_IRQn
Definition: stm32h742xx.h:185
FMC_IRQn
@ FMC_IRQn
Definition: stm32h742xx.h:108
EXTI0_IRQn
@ EXTI0_IRQn
Definition: stm32h742xx.h:67
EXTI4_IRQn
@ EXTI4_IRQn
Definition: stm32h742xx.h:71
HRTIM1_TIMD_IRQn
@ HRTIM1_TIMD_IRQn
Definition: stm32h742xx.h:160
SAI2_IRQn
@ SAI2_IRQn
Definition: stm32h742xx.h:144
HRTIM1_TIMC_IRQn
@ HRTIM1_TIMC_IRQn
Definition: stm32h742xx.h:159
FDCAN_CAL_IRQn
@ FDCAN_CAL_IRQn
Definition: stm32h742xx.h:123
DMA2_Stream2_IRQn
@ DMA2_Stream2_IRQn
Definition: stm32h742xx.h:118
TAMP_STAMP_IRQn
@ TAMP_STAMP_IRQn
Definition: stm32h742xx.h:63
TIM1_TRG_COM_IRQn
@ TIM1_TRG_COM_IRQn
Definition: stm32h742xx.h:87
UART5_IRQn
@ UART5_IRQn
Definition: stm32h742xx.h:113
DMA1_Stream5_IRQn
@ DMA1_Stream5_IRQn
Definition: stm32h742xx.h:77
DMA2D_IRQn
@ DMA2D_IRQn
Definition: stm32h742xx.h:143
DCMI_IRQn
@ DCMI_IRQn
Definition: stm32h742xx.h:134
WAKEUP_PIN_IRQn
@ WAKEUP_PIN_IRQn
Definition: stm32h742xx.h:196
I2C4_EV_IRQn
@ I2C4_EV_IRQn
Definition: stm32h742xx.h:148
ECC_IRQn
@ ECC_IRQn
Definition: stm32h742xx.h:194
BDMA_Channel5_IRQn
@ BDMA_Channel5_IRQn
Definition: stm32h742xx.h:184
ETH_IRQn
@ ETH_IRQn
Definition: stm32h742xx.h:121
MDIOS_WKUP_IRQn
@ MDIOS_WKUP_IRQn
Definition: stm32h742xx.h:172
USART1_IRQn
@ USART1_IRQn
Definition: stm32h742xx.h:98
PVD_AVD_IRQn
@ PVD_AVD_IRQn
Definition: stm32h742xx.h:62
COMP_IRQn
@ COMP_IRQn
Definition: stm32h742xx.h:187
MDMA_IRQn
@ MDMA_IRQn
Definition: stm32h742xx.h:174
EXTI3_IRQn
@ EXTI3_IRQn
Definition: stm32h742xx.h:70
BDMA_Channel0_IRQn
@ BDMA_Channel0_IRQn
Definition: stm32h742xx.h:179
NonMaskableInt_IRQn
@ NonMaskableInt_IRQn
Definition: stm32h742xx.h:51
UART4_IRQn
@ UART4_IRQn
Definition: stm32h742xx.h:112
TIM8_TRG_COM_TIM14_IRQn
@ TIM8_TRG_COM_TIM14_IRQn
Definition: stm32h742xx.h:105
EXTI1_IRQn
@ EXTI1_IRQn
Definition: stm32h742xx.h:68
DMA2_Stream4_IRQn
@ DMA2_Stream4_IRQn
Definition: stm32h742xx.h:120
TIM5_IRQn
@ TIM5_IRQn
Definition: stm32h742xx.h:110
DMA1_Stream7_IRQn
@ DMA1_Stream7_IRQn
Definition: stm32h742xx.h:107
DMA1_Stream4_IRQn
@ DMA1_Stream4_IRQn
Definition: stm32h742xx.h:76
HRTIM1_TIME_IRQn
@ HRTIM1_TIME_IRQn
Definition: stm32h742xx.h:161
DMA1_Stream6_IRQn
@ DMA1_Stream6_IRQn
Definition: stm32h742xx.h:78
TIM1_CC_IRQn
@ TIM1_CC_IRQn
Definition: stm32h742xx.h:88
SAI3_IRQn
@ SAI3_IRQn
Definition: stm32h742xx.h:167
FDCAN1_IT1_IRQn
@ FDCAN1_IT1_IRQn
Definition: stm32h742xx.h:82
LPUART1_IRQn
@ LPUART1_IRQn
Definition: stm32h742xx.h:192
DMA1_Stream3_IRQn
@ DMA1_Stream3_IRQn
Definition: stm32h742xx.h:75
SDMMC2_IRQn
@ SDMMC2_IRQn
Definition: stm32h742xx.h:175
BDMA_Channel2_IRQn
@ BDMA_Channel2_IRQn
Definition: stm32h742xx.h:181
USART3_IRQn
@ USART3_IRQn
Definition: stm32h742xx.h:100
RTC_Alarm_IRQn
@ RTC_Alarm_IRQn
Definition: stm32h742xx.h:102
DFSDM1_FLT1_IRQn
@ DFSDM1_FLT1_IRQn
Definition: stm32h742xx.h:164
FDCAN2_IT1_IRQn
@ FDCAN2_IT1_IRQn
Definition: stm32h742xx.h:83
TIM16_IRQn
@ TIM16_IRQn
Definition: stm32h742xx.h:170
MCR
#define MCR
Modem Control Register.
Definition: uart.h:91
AFR
#define AFR
Alternate Function register.
Definition: uart.h:99
ADC_Common_TypeDef
Definition: stm32h723xx.h:289
ADC_TypeDef
Analog to Digital Converter.
Definition: stm32h723xx.h:242
ADC_TypeDef::RESERVED1
uint32_t RESERVED1
Definition: stm32h742xx.h:251
ADC_TypeDef::LTR1
__IO uint32_t LTR1
Definition: stm32h742xx.h:249
ADC_TypeDef::CALFACT
__IO uint32_t CALFACT
Definition: stm32h742xx.h:281
ADC_TypeDef::DIFSEL
__IO uint32_t DIFSEL
Definition: stm32h742xx.h:280
ADC_TypeDef::CALFACT2
__IO uint32_t CALFACT2
Definition: stm32h742xx.h:282
ADC_TypeDef::HTR3
__IO uint32_t HTR3
Definition: stm32h742xx.h:279
ADC_TypeDef::HTR1
__IO uint32_t HTR1
Definition: stm32h742xx.h:250
ADC_TypeDef::LTR2
__IO uint32_t LTR2
Definition: stm32h742xx.h:276
ADC_TypeDef::LTR3
__IO uint32_t LTR3
Definition: stm32h742xx.h:278
ADC_TypeDef::PCSEL
__IO uint32_t PCSEL
Definition: stm32h742xx.h:248
ADC_TypeDef::HTR2
__IO uint32_t HTR2
Definition: stm32h742xx.h:277
BDMA_Channel_TypeDef
Definition: stm32h723xx.h:619
BDMA_TypeDef
Definition: stm32h723xx.h:628
CEC_TypeDef
Consumer Electronics Control.
Definition: stm32h723xx.h:418
COMPOPT_TypeDef
Comparator.
Definition: stm32h723xx.h:1576
COMP_Common_TypeDef
Definition: stm32h723xx.h:1588
COMP_TypeDef
Definition: stm32h723xx.h:1583
CRC_TypeDef
CRC calculation unit.
Definition: stm32h723xx.h:442
CRS_TypeDef
Clock Recovery System.
Definition: stm32h723xx.h:456
DAC_TypeDef
Digital to Analog Converter.
Definition: stm32h723xx.h:469
DBGMCU_TypeDef
Debug MCU.
Definition: stm32h723xx.h:531
DCMI_TypeDef
DCMI.
Definition: stm32h723xx.h:561
DFSDM_Channel_TypeDef
DFSDM channel configuration registers.
Definition: stm32h723xx.h:518
DFSDM_Filter_TypeDef
DFSDM module registers.
Definition: stm32h723xx.h:496
DLYB_TypeDef
Delay Block DLYB.
Definition: stm32h723xx.h:1443
DMA2D_TypeDef
DMA2D Controller.
Definition: stm32h723xx.h:686
DMAMUX_ChannelStatus_TypeDef
Definition: stm32h723xx.h:639
DMAMUX_Channel_TypeDef
Definition: stm32h723xx.h:634
DMAMUX_RequestGenStatus_TypeDef
Definition: stm32h723xx.h:650
DMAMUX_RequestGen_TypeDef
Definition: stm32h723xx.h:645
DMA_Stream_TypeDef
DMA Controller.
Definition: stm32h723xx.h:601
DMA_TypeDef
Definition: stm32h723xx.h:611
ETH_TypeDef
Ethernet MAC.
Definition: stm32h723xx.h:717
EXTI_Core_TypeDef
This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx,...
Definition: stm32h723xx.h:936
EXTI_TypeDef
External Interrupt/Event Controller.
Definition: stm32h723xx.h:891
FDCAN_ClockCalibrationUnit_TypeDef
FD Controller Area Network.
Definition: stm32h723xx.h:403
FDCAN_GlobalTypeDef
FD Controller Area Network.
Definition: stm32h723xx.h:315
FLASH_TypeDef
FLASH Registers.
Definition: stm32h723xx.h:956
FLASH_TypeDef::CRCDATA2
__IO uint32_t CRCDATA2
Definition: stm32h742xx.h:954
FLASH_TypeDef::PRAR_PRG2
__IO uint32_t PRAR_PRG2
Definition: stm32h742xx.h:945
FLASH_TypeDef::RESERVED2
uint32_t RESERVED2
Definition: stm32h742xx.h:939
FLASH_TypeDef::ECC_FA2
__IO uint32_t ECC_FA2
Definition: stm32h742xx.h:955
FLASH_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32h742xx.h:940
FLASH_TypeDef::PRAR_CUR2
__IO uint32_t PRAR_CUR2
Definition: stm32h742xx.h:944
FLASH_TypeDef::KEYR2
__IO uint32_t KEYR2
Definition: stm32h742xx.h:938
FLASH_TypeDef::CRCCR2
__IO uint32_t CRCCR2
Definition: stm32h742xx.h:951
FLASH_TypeDef::CCR2
__IO uint32_t CCR2
Definition: stm32h742xx.h:942
FLASH_TypeDef::SCAR_CUR2
__IO uint32_t SCAR_CUR2
Definition: stm32h742xx.h:946
FLASH_TypeDef::WPSN_CUR2
__IO uint32_t WPSN_CUR2
Definition: stm32h742xx.h:948
FLASH_TypeDef::WPSN_PRG2
__IO uint32_t WPSN_PRG2
Definition: stm32h742xx.h:949
FLASH_TypeDef::SCAR_PRG2
__IO uint32_t SCAR_PRG2
Definition: stm32h742xx.h:947
FLASH_TypeDef::CRCSADD2
__IO uint32_t CRCSADD2
Definition: stm32h742xx.h:952
FLASH_TypeDef::SR2
__IO uint32_t SR2
Definition: stm32h742xx.h:941
FLASH_TypeDef::CRCEADD2
__IO uint32_t CRCEADD2
Definition: stm32h742xx.h:953
FMC_Bank1E_TypeDef
Flexible Memory Controller Bank1E.
Definition: stm32h723xx.h:1015
FMC_Bank1_TypeDef
Flexible Memory Controller.
Definition: stm32h723xx.h:1006
FMC_Bank2_TypeDef
Flexible Memory Controller Bank2.
Definition: stm32h723xx.h:1024
FMC_Bank3_TypeDef
Flexible Memory Controller Bank3.
Definition: stm32h723xx.h:1038
FMC_Bank5_6_TypeDef
Flexible Memory Controller Bank5 and 6.
Definition: stm32h723xx.h:1053
GPIO_TypeDef
General Purpose I/O.
Definition: stm32h723xx.h:1066
GPV_TypeDef
Global Programmer View.
Definition: stm32h723xx.h:1966
HRTIM_Common_TypeDef
Definition: stm32h742xx.h:1629
HRTIM_Common_TypeDef::RESERVED0
__IO uint32_t RESERVED0
Definition: stm32h742xx.h:1649
HRTIM_Common_TypeDef::BDTEUPR
__IO uint32_t BDTEUPR
Definition: stm32h742xx.h:1657
HRTIM_Common_TypeDef::ADC4R
__IO uint32_t ADC4R
Definition: stm32h742xx.h:1648
HRTIM_Common_TypeDef::CR2
__IO uint32_t CR2
Definition: stm32h742xx.h:1631
HRTIM_Common_TypeDef::BDMADR
__IO uint32_t BDMADR
Definition: stm32h742xx.h:1658
HRTIM_Common_TypeDef::FLTINR2
__IO uint32_t FLTINR2
Definition: stm32h742xx.h:1651
HRTIM_Common_TypeDef::EECR3
__IO uint32_t EECR3
Definition: stm32h742xx.h:1644
HRTIM_Common_TypeDef::FLTINR1
__IO uint32_t FLTINR1
Definition: stm32h742xx.h:1650
HRTIM_Common_TypeDef::EECR1
__IO uint32_t EECR1
Definition: stm32h742xx.h:1642
HRTIM_Common_TypeDef::ISR
__IO uint32_t ISR
Definition: stm32h742xx.h:1632
HRTIM_Common_TypeDef::BDMUPR
__IO uint32_t BDMUPR
Definition: stm32h742xx.h:1652
HRTIM_Common_TypeDef::BDTAUPR
__IO uint32_t BDTAUPR
Definition: stm32h742xx.h:1653
HRTIM_Common_TypeDef::BDTCUPR
__IO uint32_t BDTCUPR
Definition: stm32h742xx.h:1655
HRTIM_Common_TypeDef::EECR2
__IO uint32_t EECR2
Definition: stm32h742xx.h:1643
HRTIM_Common_TypeDef::BMCR
__IO uint32_t BMCR
Definition: stm32h742xx.h:1638
HRTIM_Common_TypeDef::CR1
__IO uint32_t CR1
Definition: stm32h742xx.h:1630
HRTIM_Common_TypeDef::OENR
__IO uint32_t OENR
Definition: stm32h742xx.h:1635
HRTIM_Common_TypeDef::BMPER
__IO uint32_t BMPER
Definition: stm32h742xx.h:1641
HRTIM_Common_TypeDef::IER
__IO uint32_t IER
Definition: stm32h742xx.h:1634
HRTIM_Common_TypeDef::ADC3R
__IO uint32_t ADC3R
Definition: stm32h742xx.h:1647
HRTIM_Common_TypeDef::BDTBUPR
__IO uint32_t BDTBUPR
Definition: stm32h742xx.h:1654
HRTIM_Common_TypeDef::ODSR
__IO uint32_t ODSR
Definition: stm32h742xx.h:1637
HRTIM_Common_TypeDef::ADC2R
__IO uint32_t ADC2R
Definition: stm32h742xx.h:1646
HRTIM_Common_TypeDef::ICR
__IO uint32_t ICR
Definition: stm32h742xx.h:1633
HRTIM_Common_TypeDef::BDTDUPR
__IO uint32_t BDTDUPR
Definition: stm32h742xx.h:1656
HRTIM_Common_TypeDef::BMTRGR
__IO uint32_t BMTRGR
Definition: stm32h742xx.h:1639
HRTIM_Common_TypeDef::BMCMPR
__IO uint32_t BMCMPR
Definition: stm32h742xx.h:1640
HRTIM_Common_TypeDef::ADC1R
__IO uint32_t ADC1R
Definition: stm32h742xx.h:1645
HRTIM_Common_TypeDef::ODISR
__IO uint32_t ODISR
Definition: stm32h742xx.h:1636
HRTIM_Master_TypeDef
High resolution Timer (HRTIM)
Definition: stm32h742xx.h:1578
HRTIM_Master_TypeDef::MCMP1R
__IO uint32_t MCMP1R
Definition: stm32h742xx.h:1586
HRTIM_Master_TypeDef::MCMP3R
__IO uint32_t MCMP3R
Definition: stm32h742xx.h:1589
HRTIM_Master_TypeDef::MPER
__IO uint32_t MPER
Definition: stm32h742xx.h:1584
HRTIM_Master_TypeDef::MCNTR
__IO uint32_t MCNTR
Definition: stm32h742xx.h:1583
HRTIM_Master_TypeDef::MCR
__IO uint32_t MCR
Definition: stm32h742xx.h:1579
HRTIM_Master_TypeDef::MISR
__IO uint32_t MISR
Definition: stm32h742xx.h:1580
HRTIM_Master_TypeDef::MCMP4R
__IO uint32_t MCMP4R
Definition: stm32h742xx.h:1590
HRTIM_Master_TypeDef::RESERVED0
uint32_t RESERVED0
Definition: stm32h742xx.h:1587
HRTIM_Master_TypeDef::MCMP2R
__IO uint32_t MCMP2R
Definition: stm32h742xx.h:1588
HRTIM_Master_TypeDef::MICR
__IO uint32_t MICR
Definition: stm32h742xx.h:1581
HRTIM_Master_TypeDef::MDIER
__IO uint32_t MDIER
Definition: stm32h742xx.h:1582
HRTIM_Master_TypeDef::MREP
__IO uint32_t MREP
Definition: stm32h742xx.h:1585
HRTIM_Timerx_TypeDef
Definition: stm32h742xx.h:1596
HRTIM_Timerx_TypeDef::CMP2xR
__IO uint32_t CMP2xR
Definition: stm32h742xx.h:1606
HRTIM_Timerx_TypeDef::EEFxR1
__IO uint32_t EEFxR1
Definition: stm32h742xx.h:1616
HRTIM_Timerx_TypeDef::CHPxR
__IO uint32_t CHPxR
Definition: stm32h742xx.h:1619
HRTIM_Timerx_TypeDef::RSTx2R
__IO uint32_t RSTx2R
Definition: stm32h742xx.h:1615
HRTIM_Timerx_TypeDef::TIMxISR
__IO uint32_t TIMxISR
Definition: stm32h742xx.h:1598
HRTIM_Timerx_TypeDef::CMP1CxR
__IO uint32_t CMP1CxR
Definition: stm32h742xx.h:1605
HRTIM_Timerx_TypeDef::SETx2R
__IO uint32_t SETx2R
Definition: stm32h742xx.h:1614
HRTIM_Timerx_TypeDef::CMP4xR
__IO uint32_t CMP4xR
Definition: stm32h742xx.h:1608
HRTIM_Timerx_TypeDef::CPT2xR
__IO uint32_t CPT2xR
Definition: stm32h742xx.h:1610
HRTIM_Timerx_TypeDef::RSTx1R
__IO uint32_t RSTx1R
Definition: stm32h742xx.h:1613
HRTIM_Timerx_TypeDef::EEFxR2
__IO uint32_t EEFxR2
Definition: stm32h742xx.h:1617
HRTIM_Timerx_TypeDef::CPT2xCR
__IO uint32_t CPT2xCR
Definition: stm32h742xx.h:1621
HRTIM_Timerx_TypeDef::DTxR
__IO uint32_t DTxR
Definition: stm32h742xx.h:1611
HRTIM_Timerx_TypeDef::CNTxR
__IO uint32_t CNTxR
Definition: stm32h742xx.h:1601
HRTIM_Timerx_TypeDef::CPT1xR
__IO uint32_t CPT1xR
Definition: stm32h742xx.h:1609
HRTIM_Timerx_TypeDef::RSTxR
__IO uint32_t RSTxR
Definition: stm32h742xx.h:1618
HRTIM_Timerx_TypeDef::TIMxCR
__IO uint32_t TIMxCR
Definition: stm32h742xx.h:1597
HRTIM_Timerx_TypeDef::CMP1xR
__IO uint32_t CMP1xR
Definition: stm32h742xx.h:1604
HRTIM_Timerx_TypeDef::OUTxR
__IO uint32_t OUTxR
Definition: stm32h742xx.h:1622
HRTIM_Timerx_TypeDef::REPxR
__IO uint32_t REPxR
Definition: stm32h742xx.h:1603
HRTIM_Timerx_TypeDef::CPT1xCR
__IO uint32_t CPT1xCR
Definition: stm32h742xx.h:1620
HRTIM_Timerx_TypeDef::TIMxICR
__IO uint32_t TIMxICR
Definition: stm32h742xx.h:1599
HRTIM_Timerx_TypeDef::TIMxDIER
__IO uint32_t TIMxDIER
Definition: stm32h742xx.h:1600
HRTIM_Timerx_TypeDef::CMP3xR
__IO uint32_t CMP3xR
Definition: stm32h742xx.h:1607
HRTIM_Timerx_TypeDef::PERxR
__IO uint32_t PERxR
Definition: stm32h742xx.h:1602
HRTIM_Timerx_TypeDef::SETx1R
__IO uint32_t SETx1R
Definition: stm32h742xx.h:1612
HRTIM_Timerx_TypeDef::FLTxR
__IO uint32_t FLTxR
Definition: stm32h742xx.h:1623
HRTIM_TypeDef
Definition: stm32h742xx.h:1662
HSEM_Common_TypeDef
Definition: stm32h723xx.h:1467
HSEM_TypeDef
HW Semaphore HSEM.
Definition: stm32h723xx.h:1453
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32h723xx.h:1133
IWDG_TypeDef
Independent WATCHDOG.
Definition: stm32h723xx.h:1152
LPTIM_TypeDef
LPTIMIMER.
Definition: stm32h723xx.h:1559
MDIOS_TypeDef
MDIOS.
Definition: stm32h723xx.h:1681
MDMA_Channel_TypeDef
Definition: stm32h723xx.h:664
MDMA_TypeDef
MDMA Controller.
Definition: stm32h723xx.h:659
OPAMP_TypeDef
Operational Amplifier (OPAMP)
Definition: stm32h723xx.h:1083
PWR_TypeDef
Power Control.
Definition: stm32h723xx.h:1214
QUADSPI_TypeDef
QUAD Serial Peripheral Interface.
Definition: stm32h742xx.h:1414
QUADSPI_TypeDef::PSMAR
__IO uint32_t PSMAR
Definition: stm32h742xx.h:1425
QUADSPI_TypeDef::DLR
__IO uint32_t DLR
Definition: stm32h742xx.h:1419
QUADSPI_TypeDef::PIR
__IO uint32_t PIR
Definition: stm32h742xx.h:1426
QUADSPI_TypeDef::PSMKR
__IO uint32_t PSMKR
Definition: stm32h742xx.h:1424
QUADSPI_TypeDef::DCR
__IO uint32_t DCR
Definition: stm32h742xx.h:1416
QUADSPI_TypeDef::CCR
__IO uint32_t CCR
Definition: stm32h742xx.h:1420
QUADSPI_TypeDef::LPTR
__IO uint32_t LPTR
Definition: stm32h742xx.h:1427
QUADSPI_TypeDef::AR
__IO uint32_t AR
Definition: stm32h742xx.h:1421
QUADSPI_TypeDef::SR
__IO uint32_t SR
Definition: stm32h742xx.h:1417
QUADSPI_TypeDef::FCR
__IO uint32_t FCR
Definition: stm32h742xx.h:1418
QUADSPI_TypeDef::CR
__IO uint32_t CR
Definition: stm32h742xx.h:1415
QUADSPI_TypeDef::DR
__IO uint32_t DR
Definition: stm32h742xx.h:1423
QUADSPI_TypeDef::ABR
__IO uint32_t ABR
Definition: stm32h742xx.h:1422
RAMECC_MonitorTypeDef
RAM_ECC_Specific_Registers.
Definition: stm32h723xx.h:1644
RAMECC_TypeDef
Definition: stm32h723xx.h:1654
RCC_TypeDef
Reset and Clock Control.
Definition: stm32h723xx.h:1233
RNG_TypeDef
RNG.
Definition: stm32h723xx.h:1668
RTC_TypeDef
Real-Time Clock.
Definition: stm32h723xx.h:1307
SAI_Block_TypeDef
Definition: stm32h723xx.h:1375
SAI_TypeDef
Serial Audio Interface.
Definition: stm32h723xx.h:1367
SDMMC_TypeDef
Secure digital input/output Interface.
Definition: stm32h723xx.h:1408
SPDIFRX_TypeDef
SPDIF-RX Interface.
Definition: stm32h723xx.h:1391
SPI_TypeDef
Serial Peripheral Interface.
Definition: stm32h723xx.h:1479
SWPMI_TypeDef
Single Wire Protocol Master Interface SPWMI.
Definition: stm32h723xx.h:1615
SYSCFG_TypeDef
System configuration controller.
Definition: stm32h723xx.h:1094
SYSCFG_TypeDef::UR10
__IO uint32_t UR10
Definition: stm32h742xx.h:1074
SYSCFG_TypeDef::PWRCR
__IO uint32_t PWRCR
Definition: stm32h742xx.h:1060
SYSCFG_TypeDef::UR8
__IO uint32_t UR8
Definition: stm32h742xx.h:1072
SYSCFG_TypeDef::UR9
__IO uint32_t UR9
Definition: stm32h742xx.h:1073
TIM_TypeDef
TIM.
Definition: stm32h723xx.h:1525
TTCAN_TypeDef
TTFD Controller Area Network.
Definition: stm32h723xx.h:376
USART_TypeDef
Universal Synchronous Asynchronous Receiver Transmitter.
Definition: stm32h723xx.h:1596
USB_OTG_DeviceTypeDef
USB_OTG_device_Registers.
Definition: stm32h723xx.h:1796
USB_OTG_GlobalTypeDef
USB_OTG_Core_Registers.
Definition: stm32h723xx.h:1761
USB_OTG_HostChannelTypeDef
USB_OTG_Host_Channel_Specific_Registers.
Definition: stm32h723xx.h:1869
USB_OTG_HostTypeDef
USB_OTG_Host_Mode_Register_Structures.
Definition: stm32h723xx.h:1855
USB_OTG_INEndpointTypeDef
USB_OTG_IN_Endpoint-Specific_Register.
Definition: stm32h723xx.h:1824
USB_OTG_OUTEndpointTypeDef
USB_OTG_OUT_Endpoint-Specific_Registers.
Definition: stm32h723xx.h:1840
VREFBUF_TypeDef
VREFBUF.
Definition: stm32h723xx.h:304
WWDG_TypeDef
Window WATCHDOG.
Definition: stm32h723xx.h:1633
_pr
Definition: hexdump.h:39
system_stm32h7xx.h
CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.
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