RTEMS 6.1-rc5
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MCR0 - Module Control Register 0 | |
#define | FLEXSPI_MCR0_SWRESET_MASK (0x1U) |
#define | FLEXSPI_MCR0_SWRESET_SHIFT (0U) |
#define | FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) |
#define | FLEXSPI_MCR0_MDIS_MASK (0x2U) |
#define | FLEXSPI_MCR0_MDIS_SHIFT (1U) |
#define | FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) |
#define | FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) |
#define | FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) |
#define | FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) |
#define | FLEXSPI_MCR0_ARDFEN_MASK (0x40U) |
#define | FLEXSPI_MCR0_ARDFEN_SHIFT (6U) |
#define | FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) |
#define | FLEXSPI_MCR0_ATDFEN_MASK (0x80U) |
#define | FLEXSPI_MCR0_ATDFEN_SHIFT (7U) |
#define | FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) |
#define | FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) |
#define | FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) |
#define | FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) |
#define | FLEXSPI_MCR0_HSEN_MASK (0x800U) |
#define | FLEXSPI_MCR0_HSEN_SHIFT (11U) |
#define | FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) |
#define | FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) |
#define | FLEXSPI_MCR0_DOZEEN_SHIFT (12U) |
#define | FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) |
#define | FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) |
#define | FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) |
#define | FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) |
#define | FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) |
#define | FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) |
#define | FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) |
#define | FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) |
#define | FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) |
#define | FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) |
#define | FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) |
#define | FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) |
#define | FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) |
MCR2 - Module Control Register 2 | |
#define | FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) |
#define | FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) |
#define | FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) |
#define | FLEXSPI_MCR2_CLRLEARNPHASE_MASK (0x4000U) |
#define | FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT (14U) |
#define | FLEXSPI_MCR2_CLRLEARNPHASE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) |
#define | FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) |
#define | FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) |
#define | FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) |
#define | FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) |
#define | FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) |
#define | FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) |
#define | FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) |
#define | FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) |
#define | FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) |
AHBCR - AHB Bus Control Register | |
#define | FLEXSPI_AHBCR_APAREN_MASK (0x1U) |
#define | FLEXSPI_AHBCR_APAREN_SHIFT (0U) |
#define | FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) |
#define | FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) |
#define | FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) |
#define | FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) |
#define | FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) |
#define | FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) |
#define | FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) |
#define | FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) |
#define | FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) |
#define | FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) |
#define | FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) |
#define | FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) |
#define | FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) |
INTEN - Interrupt Enable Register | |
#define | FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) |
#define | FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) |
#define | FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) |
#define | FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) |
#define | FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) |
#define | FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) |
#define | FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) |
#define | FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) |
#define | FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) |
#define | FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) |
#define | FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) |
#define | FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) |
#define | FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) |
#define | FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) |
#define | FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) |
#define | FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) |
#define | FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) |
#define | FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) |
#define | FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) |
#define | FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) |
#define | FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) |
#define | FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) |
#define | FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) |
#define | FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) |
#define | FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) |
#define | FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) |
#define | FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) |
#define | FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK (0x400U) |
#define | FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT (10U) |
#define | FLEXSPI_INTEN_AHBBUSTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) |
#define | FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) |
#define | FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) |
#define | FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) |
#define | PWM_INTEN_CMPIE_MASK (0x3FU) |
#define | PWM_INTEN_CMPIE_SHIFT (0U) |
#define | PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) |
#define | PWM_INTEN_CX0IE_MASK (0x40U) |
#define | PWM_INTEN_CX0IE_SHIFT (6U) |
#define | PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) |
#define | PWM_INTEN_CX1IE_MASK (0x80U) |
#define | PWM_INTEN_CX1IE_SHIFT (7U) |
#define | PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) |
#define | PWM_INTEN_CB0IE_MASK (0x100U) |
#define | PWM_INTEN_CB0IE_SHIFT (8U) |
#define | PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) |
#define | PWM_INTEN_CB1IE_MASK (0x200U) |
#define | PWM_INTEN_CB1IE_SHIFT (9U) |
#define | PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) |
#define | PWM_INTEN_CA0IE_MASK (0x400U) |
#define | PWM_INTEN_CA0IE_SHIFT (10U) |
#define | PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) |
#define | PWM_INTEN_CA1IE_MASK (0x800U) |
#define | PWM_INTEN_CA1IE_SHIFT (11U) |
#define | PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) |
#define | PWM_INTEN_RIE_MASK (0x1000U) |
#define | PWM_INTEN_RIE_SHIFT (12U) |
#define | PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) |
#define | PWM_INTEN_REIE_MASK (0x2000U) |
#define | PWM_INTEN_REIE_SHIFT (13U) |
#define | PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) |
#define | SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) |
#define | SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) |
#define | SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) |
#define | SEMC_INTEN_IPCMDERREN_MASK (0x2U) |
#define | SEMC_INTEN_IPCMDERREN_SHIFT (1U) |
#define | SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) |
#define | SEMC_INTEN_AXICMDERREN_MASK (0x4U) |
#define | SEMC_INTEN_AXICMDERREN_SHIFT (2U) |
#define | SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) |
#define | SEMC_INTEN_AXIBUSERREN_MASK (0x8U) |
#define | SEMC_INTEN_AXIBUSERREN_SHIFT (3U) |
#define | SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) |
#define | SEMC_INTEN_NDPAGEENDEN_MASK (0x10U) |
#define | SEMC_INTEN_NDPAGEENDEN_SHIFT (4U) |
#define | SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) |
#define | SEMC_INTEN_NDNOPENDEN_MASK (0x20U) |
#define | SEMC_INTEN_NDNOPENDEN_SHIFT (5U) |
#define | SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) |
INTR - Interrupt Register | |
#define | FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) |
#define | FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) |
#define | FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) |
#define | FLEXSPI_INTR_IPCMDGE_MASK (0x2U) |
#define | FLEXSPI_INTR_IPCMDGE_SHIFT (1U) |
#define | FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) |
#define | FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) |
#define | FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) |
#define | FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) |
#define | FLEXSPI_INTR_IPCMDERR_MASK (0x8U) |
#define | FLEXSPI_INTR_IPCMDERR_SHIFT (3U) |
#define | FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) |
#define | FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) |
#define | FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) |
#define | FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) |
#define | FLEXSPI_INTR_IPRXWA_MASK (0x20U) |
#define | FLEXSPI_INTR_IPRXWA_SHIFT (5U) |
#define | FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) |
#define | FLEXSPI_INTR_IPTXWE_MASK (0x40U) |
#define | FLEXSPI_INTR_IPTXWE_SHIFT (6U) |
#define | FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) |
#define | FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) |
#define | FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) |
#define | FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) |
#define | FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) |
#define | FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) |
#define | FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) |
#define | FLEXSPI_INTR_AHBBUSTIMEOUT_MASK (0x400U) |
#define | FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT (10U) |
#define | FLEXSPI_INTR_AHBBUSTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) |
#define | FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) |
#define | FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) |
#define | FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) |
LUTKEY - LUT Key Register | |
#define | FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_LUTKEY_KEY_SHIFT (0U) |
#define | FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) |
LUTCR - LUT Control Register | |
#define | FLEXSPI_LUTCR_LOCK_MASK (0x1U) |
#define | FLEXSPI_LUTCR_LOCK_SHIFT (0U) |
#define | FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) |
#define | FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) |
#define | FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) |
#define | FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) |
AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 3 Control Register 0 | |
#define | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0xFFU) |
#define | FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) |
#define | FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) |
#define | FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) |
#define | FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) |
#define | FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) |
#define | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x3000000U) |
#define | FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) |
#define | FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) |
#define | FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) |
#define | FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) |
#define | FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) |
FLSHCR0 - Flash Control Register 0 | |
#define | FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) |
#define | FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) |
#define | FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) |
FLSHCR1 - Flash Control Register 1 | |
#define | FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) |
#define | FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) |
#define | FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) |
#define | FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) |
#define | FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) |
#define | FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) |
#define | FLEXSPI_FLSHCR1_WA_MASK (0x400U) |
#define | FLEXSPI_FLSHCR1_WA_SHIFT (10U) |
#define | FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) |
#define | FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) |
#define | FLEXSPI_FLSHCR1_CAS_SHIFT (11U) |
#define | FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) |
#define | FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) |
#define | FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) |
#define | FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) |
#define | FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) |
#define | FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) |
#define | FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) |
FLSHCR2 - Flash Control Register 2 | |
#define | FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) |
#define | FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) |
#define | FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) |
#define | FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) |
#define | FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) |
#define | FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) |
#define | FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U) |
#define | FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) |
#define | FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) |
#define | FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) |
#define | FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) |
#define | FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) |
#define | FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) |
#define | FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) |
#define | FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) |
#define | FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) |
#define | FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) |
#define | FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) |
#define | FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) |
#define | FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) |
#define | FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) |
FLSHCR4 - Flash Control Register 4 | |
#define | FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) |
#define | FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) |
#define | FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) |
#define | FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) |
#define | FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) |
#define | FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) |
#define | FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) |
#define | FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) |
#define | FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) |
IPCR0 - IP Control Register 0 | |
#define | FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_IPCR0_SFAR_SHIFT (0U) |
#define | FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) |
IPCR1 - IP Control Register 1 | |
#define | FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) |
#define | FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) |
#define | FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) |
#define | FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U) |
#define | FLEXSPI_IPCR1_ISEQID_SHIFT (16U) |
#define | FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) |
#define | FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) |
#define | FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) |
#define | FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) |
#define | FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) |
#define | FLEXSPI_IPCR1_IPAREN_SHIFT (31U) |
#define | FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) |
IPCMD - IP Command Register | |
#define | FLEXSPI_IPCMD_TRG_MASK (0x1U) |
#define | FLEXSPI_IPCMD_TRG_SHIFT (0U) |
#define | FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) |
#define | SEMC_IPCMD_CMD_MASK (0xFFFFU) |
#define | SEMC_IPCMD_CMD_SHIFT (0U) |
#define | SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK) |
#define | SEMC_IPCMD_KEY_MASK (0xFFFF0000U) |
#define | SEMC_IPCMD_KEY_SHIFT (16U) |
#define | SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) |
IPRXFCR - IP RX FIFO Control Register | |
#define | FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) |
#define | FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) |
#define | FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) |
#define | FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) |
#define | FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) |
#define | FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) |
#define | FLEXSPI_IPRXFCR_RXWMRK_MASK (0x3CU) |
#define | FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) |
#define | FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) |
IPTXFCR - IP TX FIFO Control Register | |
#define | FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) |
#define | FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) |
#define | FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) |
#define | FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) |
#define | FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) |
#define | FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) |
#define | FLEXSPI_IPTXFCR_TXWMRK_MASK (0x3CU) |
#define | FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) |
#define | FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) |
DLLCR - DLL Control Register 0 | |
#define | FLEXSPI_DLLCR_DLLEN_MASK (0x1U) |
#define | FLEXSPI_DLLCR_DLLEN_SHIFT (0U) |
#define | FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) |
#define | FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) |
#define | FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) |
#define | FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) |
#define | FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) |
#define | FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) |
#define | FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) |
#define | FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) |
#define | FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) |
#define | FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) |
#define | FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) |
#define | FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) |
#define | FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) |
STS0 - Status Register 0 | |
#define | FLEXSPI_STS0_SEQIDLE_MASK (0x1U) |
#define | FLEXSPI_STS0_SEQIDLE_SHIFT (0U) |
#define | FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) |
#define | FLEXSPI_STS0_ARBIDLE_MASK (0x2U) |
#define | FLEXSPI_STS0_ARBIDLE_SHIFT (1U) |
#define | FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) |
#define | FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) |
#define | FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) |
#define | FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) |
#define | SEMC_STS0_IDLE_MASK (0x1U) |
#define | SEMC_STS0_IDLE_SHIFT (0U) |
#define | SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) |
#define | SEMC_STS0_NARDY_MASK (0x2U) |
#define | SEMC_STS0_NARDY_SHIFT (1U) |
#define | SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) |
STS1 - Status Register 1 | |
#define | FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) |
#define | FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) |
#define | FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) |
#define | FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) |
#define | FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) |
#define | FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) |
#define | FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) |
#define | FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) |
#define | FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) |
#define | FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) |
#define | FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) |
#define | FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) |
STS2 - Status Register 2 | |
#define | FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) |
#define | FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) |
#define | FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) |
#define | FLEXSPI_STS2_AREFLOCK_MASK (0x2U) |
#define | FLEXSPI_STS2_AREFLOCK_SHIFT (1U) |
#define | FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) |
#define | FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) |
#define | FLEXSPI_STS2_ASLVSEL_SHIFT (2U) |
#define | FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) |
#define | FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) |
#define | FLEXSPI_STS2_AREFSEL_SHIFT (8U) |
#define | FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) |
#define | FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) |
#define | FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) |
#define | FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) |
#define | FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) |
#define | FLEXSPI_STS2_BREFLOCK_SHIFT (17U) |
#define | FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) |
#define | FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) |
#define | FLEXSPI_STS2_BSLVSEL_SHIFT (18U) |
#define | FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) |
#define | FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) |
#define | FLEXSPI_STS2_BREFSEL_SHIFT (24U) |
#define | FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) |
#define | SEMC_STS2_NDWRPEND_MASK (0x8U) |
#define | SEMC_STS2_NDWRPEND_SHIFT (3U) |
#define | SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) |
AHBSPNDSTS - AHB Suspend Status Register | |
#define | FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) |
#define | FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) |
#define | FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) |
#define | FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) |
#define | FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) |
#define | FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) |
#define | FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) |
#define | FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) |
#define | FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) |
IPRXFSTS - IP RX FIFO Status Register | |
#define | FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) |
#define | FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) |
#define | FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) |
#define | FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) |
#define | FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) |
#define | FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) |
IPTXFSTS - IP TX FIFO Status Register | |
#define | FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) |
#define | FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) |
#define | FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) |
#define | FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) |
#define | FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) |
#define | FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) |
RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 | |
#define | FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_RFDR_RXDATA_SHIFT (0U) |
#define | FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) |
TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 | |
#define | FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_TFDR_TXDATA_SHIFT (0U) |
#define | FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) |
LUT - LUT 0..LUT 63 | |
#define | FLEXSPI_LUT_OPERAND0_MASK (0xFFU) |
#define | FLEXSPI_LUT_OPERAND0_SHIFT (0U) |
#define | FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) |
#define | FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) |
#define | FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) |
#define | FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) |
#define | FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) |
#define | FLEXSPI_LUT_OPCODE0_SHIFT (10U) |
#define | FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) |
#define | FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) |
#define | FLEXSPI_LUT_OPERAND1_SHIFT (16U) |
#define | FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) |
#define | FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) |
#define | FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) |
#define | FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) |
#define | FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) |
#define | FLEXSPI_LUT_OPCODE1_SHIFT (26U) |
#define | FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) |
MCR0 - Module Control Register 0 | |
#define | FLEXSPI_MCR0_SWRESET_MASK (0x1U) |
#define | FLEXSPI_MCR0_SWRESET_SHIFT (0U) |
#define | FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) |
#define | FLEXSPI_MCR0_MDIS_MASK (0x2U) |
#define | FLEXSPI_MCR0_MDIS_SHIFT (1U) |
#define | FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) |
#define | FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) |
#define | FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) |
#define | FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) |
#define | FLEXSPI_MCR0_ARDFEN_MASK (0x40U) |
#define | FLEXSPI_MCR0_ARDFEN_SHIFT (6U) |
#define | FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) |
#define | FLEXSPI_MCR0_ATDFEN_MASK (0x80U) |
#define | FLEXSPI_MCR0_ATDFEN_SHIFT (7U) |
#define | FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) |
#define | FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) |
#define | FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) |
#define | FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) |
#define | FLEXSPI_MCR0_HSEN_MASK (0x800U) |
#define | FLEXSPI_MCR0_HSEN_SHIFT (11U) |
#define | FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) |
#define | FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) |
#define | FLEXSPI_MCR0_DOZEEN_SHIFT (12U) |
#define | FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) |
#define | FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) |
#define | FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) |
#define | FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) |
#define | FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) |
#define | FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) |
#define | FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) |
#define | FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) |
#define | FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) |
#define | FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) |
#define | FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) |
#define | FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) |
#define | FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) |
MCR2 - Module Control Register 2 | |
#define | FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) |
#define | FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) |
#define | FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) |
#define | FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) |
#define | FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) |
#define | FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) |
#define | FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) |
#define | FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) |
#define | FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) |
#define | FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) |
#define | FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) |
#define | FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) |
AHBCR - AHB Bus Control Register | |
#define | FLEXSPI_AHBCR_APAREN_MASK (0x1U) |
#define | FLEXSPI_AHBCR_APAREN_SHIFT (0U) |
#define | FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) |
#define | FLEXSPI_AHBCR_CLRAHBRXBUF_MASK (0x2U) |
#define | FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT (1U) |
#define | FLEXSPI_AHBCR_CLRAHBRXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK) |
#define | FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) |
#define | FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) |
#define | FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) |
#define | FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) |
#define | FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) |
#define | FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) |
#define | FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) |
#define | FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) |
#define | FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) |
#define | FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) |
#define | FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) |
#define | FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) |
#define | FLEXSPI_AHBCR_READSZALIGN_MASK (0x400U) |
#define | FLEXSPI_AHBCR_READSZALIGN_SHIFT (10U) |
#define | FLEXSPI_AHBCR_READSZALIGN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK) |
#define | FLEXSPI_AHBCR_ECCEN_MASK (0x800U) |
#define | FLEXSPI_AHBCR_ECCEN_SHIFT (11U) |
#define | FLEXSPI_AHBCR_ECCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCEN_SHIFT)) & FLEXSPI_AHBCR_ECCEN_MASK) |
#define | FLEXSPI_AHBCR_SPLITEN_MASK (0x1000U) |
#define | FLEXSPI_AHBCR_SPLITEN_SHIFT (12U) |
#define | FLEXSPI_AHBCR_SPLITEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLITEN_SHIFT)) & FLEXSPI_AHBCR_SPLITEN_MASK) |
#define | FLEXSPI_AHBCR_SPLIT_LIMIT_MASK (0x6000U) |
#define | FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT (13U) |
#define | FLEXSPI_AHBCR_SPLIT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT)) & FLEXSPI_AHBCR_SPLIT_LIMIT_MASK) |
#define | FLEXSPI_AHBCR_KEYECCEN_MASK (0x8000U) |
#define | FLEXSPI_AHBCR_KEYECCEN_SHIFT (15U) |
#define | FLEXSPI_AHBCR_KEYECCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_KEYECCEN_SHIFT)) & FLEXSPI_AHBCR_KEYECCEN_MASK) |
#define | FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK (0x10000U) |
#define | FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT (16U) |
#define | FLEXSPI_AHBCR_ECCSINGLEERRCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK) |
#define | FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK (0x20000U) |
#define | FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT (17U) |
#define | FLEXSPI_AHBCR_ECCMULTIERRCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK) |
#define | FLEXSPI_AHBCR_HMSTRIDREMAP_MASK (0x40000U) |
#define | FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT (18U) |
#define | FLEXSPI_AHBCR_HMSTRIDREMAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT)) & FLEXSPI_AHBCR_HMSTRIDREMAP_MASK) |
#define | FLEXSPI_AHBCR_ECCSWAPEN_MASK (0x80000U) |
#define | FLEXSPI_AHBCR_ECCSWAPEN_SHIFT (19U) |
#define | FLEXSPI_AHBCR_ECCSWAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSWAPEN_SHIFT)) & FLEXSPI_AHBCR_ECCSWAPEN_MASK) |
#define | FLEXSPI_AHBCR_ALIGNMENT_MASK (0x300000U) |
#define | FLEXSPI_AHBCR_ALIGNMENT_SHIFT (20U) |
#define | FLEXSPI_AHBCR_ALIGNMENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK) |
INTEN - Interrupt Enable Register | |
#define | FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) |
#define | FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) |
#define | FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) |
#define | FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) |
#define | FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) |
#define | FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) |
#define | FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) |
#define | FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) |
#define | FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) |
#define | FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) |
#define | FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) |
#define | FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) |
#define | FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) |
#define | FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) |
#define | FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) |
#define | FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) |
#define | FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) |
#define | FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) |
#define | FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) |
#define | FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) |
#define | FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) |
#define | FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) |
#define | FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) |
#define | FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) |
#define | FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) |
#define | FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) |
#define | FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) |
#define | FLEXSPI_INTEN_AHBBUSERROREN_MASK (0x400U) |
#define | FLEXSPI_INTEN_AHBBUSERROREN_SHIFT (10U) |
#define | FLEXSPI_INTEN_AHBBUSERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK) |
#define | FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) |
#define | FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) |
#define | FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) |
#define | FLEXSPI_INTEN_KEYDONEEN_MASK (0x1000U) |
#define | FLEXSPI_INTEN_KEYDONEEN_SHIFT (12U) |
#define | FLEXSPI_INTEN_KEYDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK) |
#define | FLEXSPI_INTEN_KEYERROREN_MASK (0x2000U) |
#define | FLEXSPI_INTEN_KEYERROREN_SHIFT (13U) |
#define | FLEXSPI_INTEN_KEYERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK) |
#define | FLEXSPI_INTEN_ECCMULTIERREN_MASK (0x4000U) |
#define | FLEXSPI_INTEN_ECCMULTIERREN_SHIFT (14U) |
#define | FLEXSPI_INTEN_ECCMULTIERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCMULTIERREN_SHIFT)) & FLEXSPI_INTEN_ECCMULTIERREN_MASK) |
#define | FLEXSPI_INTEN_ECCSINGLEERREN_MASK (0x8000U) |
#define | FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT (15U) |
#define | FLEXSPI_INTEN_ECCSINGLEERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT)) & FLEXSPI_INTEN_ECCSINGLEERREN_MASK) |
#define | FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK (0x10000U) |
#define | FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT (16U) |
#define | FLEXSPI_INTEN_IPCMDSECUREVIOEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK) |
#define | PWM_INTEN_CMPIE_MASK (0x3FU) |
#define | PWM_INTEN_CMPIE_SHIFT (0U) |
#define | PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) |
#define | PWM_INTEN_CX0IE_MASK (0x40U) |
#define | PWM_INTEN_CX0IE_SHIFT (6U) |
#define | PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) |
#define | PWM_INTEN_CX1IE_MASK (0x80U) |
#define | PWM_INTEN_CX1IE_SHIFT (7U) |
#define | PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) |
#define | PWM_INTEN_CB0IE_MASK (0x100U) |
#define | PWM_INTEN_CB0IE_SHIFT (8U) |
#define | PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) |
#define | PWM_INTEN_CB1IE_MASK (0x200U) |
#define | PWM_INTEN_CB1IE_SHIFT (9U) |
#define | PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) |
#define | PWM_INTEN_CA0IE_MASK (0x400U) |
#define | PWM_INTEN_CA0IE_SHIFT (10U) |
#define | PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) |
#define | PWM_INTEN_CA1IE_MASK (0x800U) |
#define | PWM_INTEN_CA1IE_SHIFT (11U) |
#define | PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) |
#define | PWM_INTEN_RIE_MASK (0x1000U) |
#define | PWM_INTEN_RIE_SHIFT (12U) |
#define | PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) |
#define | PWM_INTEN_REIE_MASK (0x2000U) |
#define | PWM_INTEN_REIE_SHIFT (13U) |
#define | PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) |
#define | SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) |
#define | SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) |
#define | SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) |
#define | SEMC_INTEN_IPCMDERREN_MASK (0x2U) |
#define | SEMC_INTEN_IPCMDERREN_SHIFT (1U) |
#define | SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) |
#define | SEMC_INTEN_AXICMDERREN_MASK (0x4U) |
#define | SEMC_INTEN_AXICMDERREN_SHIFT (2U) |
#define | SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) |
#define | SEMC_INTEN_AXIBUSERREN_MASK (0x8U) |
#define | SEMC_INTEN_AXIBUSERREN_SHIFT (3U) |
#define | SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) |
#define | SEMC_INTEN_NDPAGEENDEN_MASK (0x10U) |
#define | SEMC_INTEN_NDPAGEENDEN_SHIFT (4U) |
#define | SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) |
#define | SEMC_INTEN_NDNOPENDEN_MASK (0x20U) |
#define | SEMC_INTEN_NDNOPENDEN_SHIFT (5U) |
#define | SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) |
INTR - Interrupt Register | |
#define | FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) |
#define | FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) |
#define | FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) |
#define | FLEXSPI_INTR_IPCMDGE_MASK (0x2U) |
#define | FLEXSPI_INTR_IPCMDGE_SHIFT (1U) |
#define | FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) |
#define | FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) |
#define | FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) |
#define | FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) |
#define | FLEXSPI_INTR_IPCMDERR_MASK (0x8U) |
#define | FLEXSPI_INTR_IPCMDERR_SHIFT (3U) |
#define | FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) |
#define | FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) |
#define | FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) |
#define | FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) |
#define | FLEXSPI_INTR_IPRXWA_MASK (0x20U) |
#define | FLEXSPI_INTR_IPRXWA_SHIFT (5U) |
#define | FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) |
#define | FLEXSPI_INTR_IPTXWE_MASK (0x40U) |
#define | FLEXSPI_INTR_IPTXWE_SHIFT (6U) |
#define | FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) |
#define | FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) |
#define | FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) |
#define | FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) |
#define | FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) |
#define | FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) |
#define | FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) |
#define | FLEXSPI_INTR_AHBBUSERROR_MASK (0x400U) |
#define | FLEXSPI_INTR_AHBBUSERROR_SHIFT (10U) |
#define | FLEXSPI_INTR_AHBBUSERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK) |
#define | FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) |
#define | FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) |
#define | FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) |
#define | FLEXSPI_INTR_KEYDONE_MASK (0x1000U) |
#define | FLEXSPI_INTR_KEYDONE_SHIFT (12U) |
#define | FLEXSPI_INTR_KEYDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK) |
#define | FLEXSPI_INTR_KEYERROR_MASK (0x2000U) |
#define | FLEXSPI_INTR_KEYERROR_SHIFT (13U) |
#define | FLEXSPI_INTR_KEYERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK) |
#define | FLEXSPI_INTR_ECCMULTIERR_MASK (0x4000U) |
#define | FLEXSPI_INTR_ECCMULTIERR_SHIFT (14U) |
#define | FLEXSPI_INTR_ECCMULTIERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCMULTIERR_SHIFT)) & FLEXSPI_INTR_ECCMULTIERR_MASK) |
#define | FLEXSPI_INTR_ECCSINGLEERR_MASK (0x8000U) |
#define | FLEXSPI_INTR_ECCSINGLEERR_SHIFT (15U) |
#define | FLEXSPI_INTR_ECCSINGLEERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCSINGLEERR_SHIFT)) & FLEXSPI_INTR_ECCSINGLEERR_MASK) |
#define | FLEXSPI_INTR_IPCMDSECUREVIO_MASK (0x10000U) |
#define | FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT (16U) |
#define | FLEXSPI_INTR_IPCMDSECUREVIO(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK) |
#define | SEMC_INTR_IPCMDDONE_MASK (0x1U) |
#define | SEMC_INTR_IPCMDDONE_SHIFT (0U) |
#define | SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) |
#define | SEMC_INTR_IPCMDERR_MASK (0x2U) |
#define | SEMC_INTR_IPCMDERR_SHIFT (1U) |
#define | SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) |
#define | SEMC_INTR_AXICMDERR_MASK (0x4U) |
#define | SEMC_INTR_AXICMDERR_SHIFT (2U) |
#define | SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) |
#define | SEMC_INTR_AXIBUSERR_MASK (0x8U) |
#define | SEMC_INTR_AXIBUSERR_SHIFT (3U) |
#define | SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) |
#define | SEMC_INTR_NDPAGEEND_MASK (0x10U) |
#define | SEMC_INTR_NDPAGEEND_SHIFT (4U) |
#define | SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) |
#define | SEMC_INTR_NDNOPEND_MASK (0x20U) |
#define | SEMC_INTR_NDNOPEND_SHIFT (5U) |
#define | SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) |
LUTKEY - LUT Key Register | |
#define | FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_LUTKEY_KEY_SHIFT (0U) |
#define | FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) |
LUTCR - LUT Control Register | |
#define | FLEXSPI_LUTCR_LOCK_MASK (0x1U) |
#define | FLEXSPI_LUTCR_LOCK_SHIFT (0U) |
#define | FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) |
#define | FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) |
#define | FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) |
#define | FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) |
#define | FLEXSPI_LUTCR_PROTECT_MASK (0x4U) |
#define | FLEXSPI_LUTCR_PROTECT_SHIFT (2U) |
#define | FLEXSPI_LUTCR_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK) |
AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 | |
#define | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x3FFU) |
#define | FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) |
#define | FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) |
#define | FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) |
#define | FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) |
#define | FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) |
#define | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) |
#define | FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) |
#define | FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) |
#define | FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK (0x40000000U) |
#define | FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT (30U) |
#define | FLEXSPI_AHBRXBUFCR0_REGIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK) |
#define | FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) |
#define | FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) |
#define | FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) |
FLSHCR0 - Flash Control Register 0 | |
#define | FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) |
#define | FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) |
#define | FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) |
#define | FLEXSPI_FLSHCR0_SPLITWREN_MASK (0x40000000U) |
#define | FLEXSPI_FLSHCR0_SPLITWREN_SHIFT (30U) |
#define | FLEXSPI_FLSHCR0_SPLITWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK) |
#define | FLEXSPI_FLSHCR0_SPLITRDEN_MASK (0x80000000U) |
#define | FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT (31U) |
#define | FLEXSPI_FLSHCR0_SPLITRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK) |
FLSHCR1 - Flash Control Register 1 | |
#define | FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) |
#define | FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) |
#define | FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) |
#define | FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) |
#define | FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) |
#define | FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) |
#define | FLEXSPI_FLSHCR1_WA_MASK (0x400U) |
#define | FLEXSPI_FLSHCR1_WA_SHIFT (10U) |
#define | FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) |
#define | FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) |
#define | FLEXSPI_FLSHCR1_CAS_SHIFT (11U) |
#define | FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) |
#define | FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) |
#define | FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) |
#define | FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) |
#define | FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) |
#define | FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) |
#define | FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) |
FLSHCR2 - Flash Control Register 2 | |
#define | FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) |
#define | FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) |
#define | FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) |
#define | FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) |
#define | FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) |
#define | FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) |
#define | FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U) |
#define | FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) |
#define | FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) |
#define | FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) |
#define | FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) |
#define | FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) |
#define | FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) |
#define | FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) |
#define | FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) |
#define | FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) |
#define | FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) |
#define | FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) |
#define | FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) |
#define | FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) |
#define | FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) |
FLSHCR4 - Flash Control Register 4 | |
#define | FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) |
#define | FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) |
#define | FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) |
#define | FLEXSPI_FLSHCR4_WMOPT2_MASK (0x2U) |
#define | FLEXSPI_FLSHCR4_WMOPT2_SHIFT (1U) |
#define | FLEXSPI_FLSHCR4_WMOPT2(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK) |
#define | FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) |
#define | FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) |
#define | FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) |
#define | FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) |
#define | FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) |
#define | FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) |
#define | FLEXSPI_FLSHCR4_PAR_WM_MASK (0x600U) |
#define | FLEXSPI_FLSHCR4_PAR_WM_SHIFT (9U) |
#define | FLEXSPI_FLSHCR4_PAR_WM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_WM_SHIFT)) & FLEXSPI_FLSHCR4_PAR_WM_MASK) |
#define | FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK (0x800U) |
#define | FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT (11U) |
#define | FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT)) & FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK) |
IPCR0 - IP Control Register 0 | |
#define | FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_IPCR0_SFAR_SHIFT (0U) |
#define | FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) |
IPCR1 - IP Control Register 1 | |
#define | FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) |
#define | FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) |
#define | FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) |
#define | FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U) |
#define | FLEXSPI_IPCR1_ISEQID_SHIFT (16U) |
#define | FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) |
#define | FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) |
#define | FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) |
#define | FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) |
#define | FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) |
#define | FLEXSPI_IPCR1_IPAREN_SHIFT (31U) |
#define | FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) |
IPCMD - IP Command Register | |
#define | FLEXSPI_IPCMD_TRG_MASK (0x1U) |
#define | FLEXSPI_IPCMD_TRG_SHIFT (0U) |
#define | FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) |
#define | SEMC_IPCMD_CMD_MASK (0xFFFFU) |
#define | SEMC_IPCMD_CMD_SHIFT (0U) |
#define | SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK) |
#define | SEMC_IPCMD_KEY_MASK (0xFFFF0000U) |
#define | SEMC_IPCMD_KEY_SHIFT (16U) |
#define | SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) |
IPRXFCR - IP RX FIFO Control Register | |
#define | FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) |
#define | FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) |
#define | FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) |
#define | FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) |
#define | FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) |
#define | FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) |
#define | FLEXSPI_IPRXFCR_RXWMRK_MASK (0x7CU) |
#define | FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) |
#define | FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) |
IPTXFCR - IP TX FIFO Control Register | |
#define | FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) |
#define | FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) |
#define | FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) |
#define | FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) |
#define | FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) |
#define | FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) |
#define | FLEXSPI_IPTXFCR_TXWMRK_MASK (0x7CU) |
#define | FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) |
#define | FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) |
DLLCR - DLL Control Register 0 | |
#define | FLEXSPI_DLLCR_DLLEN_MASK (0x1U) |
#define | FLEXSPI_DLLCR_DLLEN_SHIFT (0U) |
#define | FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) |
#define | FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) |
#define | FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) |
#define | FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) |
#define | FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) |
#define | FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) |
#define | FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) |
#define | FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) |
#define | FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) |
#define | FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) |
#define | FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) |
#define | FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) |
#define | FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) |
MISCCR4 - Misc Control Register 4 | |
#define | FLEXSPI_MISCCR4_AHBADDRESS_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_MISCCR4_AHBADDRESS_SHIFT (0U) |
#define | FLEXSPI_MISCCR4_AHBADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR4_AHBADDRESS_SHIFT)) & FLEXSPI_MISCCR4_AHBADDRESS_MASK) |
MISCCR5 - Misc Control Register 5 | |
#define | FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT (0U) |
#define | FLEXSPI_MISCCR5_ECCSINGLEERRORCORR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT)) & FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK) |
MISCCR6 - Misc Control Register 6 | |
#define | FLEXSPI_MISCCR6_VALID_MASK (0x1U) |
#define | FLEXSPI_MISCCR6_VALID_SHIFT (0U) |
#define | FLEXSPI_MISCCR6_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_VALID_SHIFT)) & FLEXSPI_MISCCR6_VALID_MASK) |
#define | FLEXSPI_MISCCR6_HIT_MASK (0x2U) |
#define | FLEXSPI_MISCCR6_HIT_SHIFT (1U) |
#define | FLEXSPI_MISCCR6_HIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_HIT_SHIFT)) & FLEXSPI_MISCCR6_HIT_MASK) |
#define | FLEXSPI_MISCCR6_ADDRESS_MASK (0xFFFFFFFCU) |
#define | FLEXSPI_MISCCR6_ADDRESS_SHIFT (2U) |
#define | FLEXSPI_MISCCR6_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_ADDRESS_SHIFT)) & FLEXSPI_MISCCR6_ADDRESS_MASK) |
MISCCR7 - Misc Control Register 7 | |
#define | FLEXSPI_MISCCR7_VALID_MASK (0x1U) |
#define | FLEXSPI_MISCCR7_VALID_SHIFT (0U) |
#define | FLEXSPI_MISCCR7_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_VALID_SHIFT)) & FLEXSPI_MISCCR7_VALID_MASK) |
#define | FLEXSPI_MISCCR7_HIT_MASK (0x2U) |
#define | FLEXSPI_MISCCR7_HIT_SHIFT (1U) |
#define | FLEXSPI_MISCCR7_HIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_HIT_SHIFT)) & FLEXSPI_MISCCR7_HIT_MASK) |
#define | FLEXSPI_MISCCR7_ADDRESS_MASK (0xFFFFFFFCU) |
#define | FLEXSPI_MISCCR7_ADDRESS_SHIFT (2U) |
#define | FLEXSPI_MISCCR7_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_ADDRESS_SHIFT)) & FLEXSPI_MISCCR7_ADDRESS_MASK) |
STS0 - Status Register 0 | |
#define | FLEXSPI_STS0_SEQIDLE_MASK (0x1U) |
#define | FLEXSPI_STS0_SEQIDLE_SHIFT (0U) |
#define | FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) |
#define | FLEXSPI_STS0_ARBIDLE_MASK (0x2U) |
#define | FLEXSPI_STS0_ARBIDLE_SHIFT (1U) |
#define | FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) |
#define | FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) |
#define | FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) |
#define | FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) |
#define | SEMC_STS0_IDLE_MASK (0x1U) |
#define | SEMC_STS0_IDLE_SHIFT (0U) |
#define | SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) |
#define | SEMC_STS0_NARDY_MASK (0x2U) |
#define | SEMC_STS0_NARDY_SHIFT (1U) |
#define | SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) |
STS1 - Status Register 1 | |
#define | FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) |
#define | FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) |
#define | FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) |
#define | FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) |
#define | FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) |
#define | FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) |
#define | FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) |
#define | FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) |
#define | FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) |
#define | FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) |
#define | FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) |
#define | FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) |
STS2 - Status Register 2 | |
#define | FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) |
#define | FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) |
#define | FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) |
#define | FLEXSPI_STS2_AREFLOCK_MASK (0x2U) |
#define | FLEXSPI_STS2_AREFLOCK_SHIFT (1U) |
#define | FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) |
#define | FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) |
#define | FLEXSPI_STS2_ASLVSEL_SHIFT (2U) |
#define | FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) |
#define | FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) |
#define | FLEXSPI_STS2_AREFSEL_SHIFT (8U) |
#define | FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) |
#define | FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) |
#define | FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) |
#define | FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) |
#define | FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) |
#define | FLEXSPI_STS2_BREFLOCK_SHIFT (17U) |
#define | FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) |
#define | FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) |
#define | FLEXSPI_STS2_BSLVSEL_SHIFT (18U) |
#define | FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) |
#define | FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) |
#define | FLEXSPI_STS2_BREFSEL_SHIFT (24U) |
#define | FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) |
#define | SEMC_STS2_NDWRPEND_MASK (0x8U) |
#define | SEMC_STS2_NDWRPEND_SHIFT (3U) |
#define | SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) |
AHBSPNDSTS - AHB Suspend Status Register | |
#define | FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) |
#define | FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) |
#define | FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) |
#define | FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) |
#define | FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) |
#define | FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) |
#define | FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) |
#define | FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) |
#define | FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) |
IPRXFSTS - IP RX FIFO Status Register | |
#define | FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) |
#define | FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) |
#define | FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) |
#define | FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) |
#define | FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) |
#define | FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) |
IPTXFSTS - IP TX FIFO Status Register | |
#define | FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) |
#define | FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) |
#define | FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) |
#define | FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) |
#define | FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) |
#define | FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) |
RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 | |
#define | FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_RFDR_RXDATA_SHIFT (0U) |
#define | FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) |
TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 | |
#define | FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_TFDR_TXDATA_SHIFT (0U) |
#define | FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) |
LUT - LUT 0..LUT 63 | |
#define | FLEXSPI_LUT_OPERAND0_MASK (0xFFU) |
#define | FLEXSPI_LUT_OPERAND0_SHIFT (0U) |
#define | FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) |
#define | FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) |
#define | FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) |
#define | FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) |
#define | FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) |
#define | FLEXSPI_LUT_OPCODE0_SHIFT (10U) |
#define | FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) |
#define | FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) |
#define | FLEXSPI_LUT_OPERAND1_SHIFT (16U) |
#define | FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) |
#define | FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) |
#define | FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) |
#define | FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) |
#define | FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) |
#define | FLEXSPI_LUT_OPCODE1_SHIFT (26U) |
#define | FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) |
HMSTRCR - AHB Master ID 0 Control Register..AHB Master ID 7 Control Register | |
#define | FLEXSPI_HMSTRCR_MASK_MASK (0xFFFFU) |
#define | FLEXSPI_HMSTRCR_MASK_SHIFT (0U) |
#define | FLEXSPI_HMSTRCR_MASK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MASK_SHIFT)) & FLEXSPI_HMSTRCR_MASK_MASK) |
#define | FLEXSPI_HMSTRCR_MSTRID_MASK (0xFFFF0000U) |
#define | FLEXSPI_HMSTRCR_MSTRID_SHIFT (16U) |
#define | FLEXSPI_HMSTRCR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MSTRID_SHIFT)) & FLEXSPI_HMSTRCR_MSTRID_MASK) |
HADDRSTART - HADDR REMAP START ADDR | |
#define | FLEXSPI_HADDRSTART_REMAPEN_MASK (0x1U) |
#define | FLEXSPI_HADDRSTART_REMAPEN_SHIFT (0U) |
#define | FLEXSPI_HADDRSTART_REMAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK) |
#define | FLEXSPI_HADDRSTART_KBINECC_MASK (0x2U) |
#define | FLEXSPI_HADDRSTART_KBINECC_SHIFT (1U) |
#define | FLEXSPI_HADDRSTART_KBINECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_KBINECC_SHIFT)) & FLEXSPI_HADDRSTART_KBINECC_MASK) |
#define | FLEXSPI_HADDRSTART_ADDRSTART_MASK (0xFFFFF000U) |
#define | FLEXSPI_HADDRSTART_ADDRSTART_SHIFT (12U) |
#define | FLEXSPI_HADDRSTART_ADDRSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_ADDRSTART_SHIFT)) & FLEXSPI_HADDRSTART_ADDRSTART_MASK) |
IPSNSZSTART0 - IPS nonsecure region Start address of region 0 | |
#define | FLEXSPI_IPSNSZSTART0_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_IPSNSZSTART0_start_address_SHIFT (12U) |
#define | FLEXSPI_IPSNSZSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART0_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART0_start_address_MASK) |
IPSNSZEND0 - IPS nonsecure region End address of region 0 | |
#define | FLEXSPI_IPSNSZEND0_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_IPSNSZEND0_end_address_SHIFT (12U) |
#define | FLEXSPI_IPSNSZEND0_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND0_end_address_SHIFT)) & FLEXSPI_IPSNSZEND0_end_address_MASK) |
IPSNSZSTART1 - IPS nonsecure region Start address of region 1 | |
#define | FLEXSPI_IPSNSZSTART1_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_IPSNSZSTART1_start_address_SHIFT (12U) |
#define | FLEXSPI_IPSNSZSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART1_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART1_start_address_MASK) |
IPSNSZEND1 - IPS nonsecure region End address of region 1 | |
#define | FLEXSPI_IPSNSZEND1_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_IPSNSZEND1_end_address_SHIFT (12U) |
#define | FLEXSPI_IPSNSZEND1_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND1_end_address_SHIFT)) & FLEXSPI_IPSNSZEND1_end_address_MASK) |
AHBBUFREGIONSTART0 - RX BUF Start address of region 0 | |
#define | FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK) |
AHBBUFREGIONEND0 - RX BUF region End address of region 0 | |
#define | FLEXSPI_AHBBUFREGIONEND0_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONEND0_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_end_address_MASK) |
AHBBUFREGIONSTART1 - RX BUF Start address of region 1 | |
#define | FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK) |
AHBBUFREGIONEND1 - RX BUF region End address of region 1 | |
#define | FLEXSPI_AHBBUFREGIONEND1_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONEND1_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_end_address_MASK) |
AHBBUFREGIONSTART2 - RX BUF Start address of region 2 | |
#define | FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONSTART2_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK) |
AHBBUFREGIONEND2 - RX BUF region End address of region 2 | |
#define | FLEXSPI_AHBBUFREGIONEND2_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONEND2_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_end_address_MASK) |
AHBBUFREGIONSTART3 - RX BUF Start address of region 3 | |
#define | FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONSTART3_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK) |
AHBBUFREGIONEND3 - RX BUF region End address of region 3 | |
#define | FLEXSPI_AHBBUFREGIONEND3_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONEND3_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_end_address_MASK) |
MCR0 - Module Control Register 0 | |
#define | FLEXSPI_MCR0_SWRESET_MASK (0x1U) |
#define | FLEXSPI_MCR0_SWRESET_SHIFT (0U) |
#define | FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) |
#define | FLEXSPI_MCR0_MDIS_MASK (0x2U) |
#define | FLEXSPI_MCR0_MDIS_SHIFT (1U) |
#define | FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) |
#define | FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U) |
#define | FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U) |
#define | FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) |
#define | FLEXSPI_MCR0_ARDFEN_MASK (0x40U) |
#define | FLEXSPI_MCR0_ARDFEN_SHIFT (6U) |
#define | FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) |
#define | FLEXSPI_MCR0_ATDFEN_MASK (0x80U) |
#define | FLEXSPI_MCR0_ATDFEN_SHIFT (7U) |
#define | FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) |
#define | FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U) |
#define | FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U) |
#define | FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) |
#define | FLEXSPI_MCR0_HSEN_MASK (0x800U) |
#define | FLEXSPI_MCR0_HSEN_SHIFT (11U) |
#define | FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) |
#define | FLEXSPI_MCR0_DOZEEN_MASK (0x1000U) |
#define | FLEXSPI_MCR0_DOZEEN_SHIFT (12U) |
#define | FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) |
#define | FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U) |
#define | FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U) |
#define | FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) |
#define | FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U) |
#define | FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U) |
#define | FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) |
#define | FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U) |
#define | FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U) |
#define | FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) |
#define | FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U) |
#define | FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U) |
#define | FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) |
MCR2 - Module Control Register 2 | |
#define | FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U) |
#define | FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U) |
#define | FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) |
#define | FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U) |
#define | FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U) |
#define | FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) |
#define | FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U) |
#define | FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U) |
#define | FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) |
#define | FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U) |
#define | FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U) |
#define | FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) |
AHBCR - AHB Bus Control Register | |
#define | FLEXSPI_AHBCR_APAREN_MASK (0x1U) |
#define | FLEXSPI_AHBCR_APAREN_SHIFT (0U) |
#define | FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) |
#define | FLEXSPI_AHBCR_CLRAHBRXBUF_MASK (0x2U) |
#define | FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT (1U) |
#define | FLEXSPI_AHBCR_CLRAHBRXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK) |
#define | FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U) |
#define | FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U) |
#define | FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) |
#define | FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U) |
#define | FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U) |
#define | FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) |
#define | FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U) |
#define | FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U) |
#define | FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) |
#define | FLEXSPI_AHBCR_READADDROPT_MASK (0x40U) |
#define | FLEXSPI_AHBCR_READADDROPT_SHIFT (6U) |
#define | FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) |
#define | FLEXSPI_AHBCR_READSZALIGN_MASK (0x400U) |
#define | FLEXSPI_AHBCR_READSZALIGN_SHIFT (10U) |
#define | FLEXSPI_AHBCR_READSZALIGN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK) |
#define | FLEXSPI_AHBCR_ECCEN_MASK (0x800U) |
#define | FLEXSPI_AHBCR_ECCEN_SHIFT (11U) |
#define | FLEXSPI_AHBCR_ECCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCEN_SHIFT)) & FLEXSPI_AHBCR_ECCEN_MASK) |
#define | FLEXSPI_AHBCR_SPLITEN_MASK (0x1000U) |
#define | FLEXSPI_AHBCR_SPLITEN_SHIFT (12U) |
#define | FLEXSPI_AHBCR_SPLITEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLITEN_SHIFT)) & FLEXSPI_AHBCR_SPLITEN_MASK) |
#define | FLEXSPI_AHBCR_SPLIT_LIMIT_MASK (0x6000U) |
#define | FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT (13U) |
#define | FLEXSPI_AHBCR_SPLIT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT)) & FLEXSPI_AHBCR_SPLIT_LIMIT_MASK) |
#define | FLEXSPI_AHBCR_KEYECCEN_MASK (0x8000U) |
#define | FLEXSPI_AHBCR_KEYECCEN_SHIFT (15U) |
#define | FLEXSPI_AHBCR_KEYECCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_KEYECCEN_SHIFT)) & FLEXSPI_AHBCR_KEYECCEN_MASK) |
#define | FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK (0x10000U) |
#define | FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT (16U) |
#define | FLEXSPI_AHBCR_ECCSINGLEERRCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK) |
#define | FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK (0x20000U) |
#define | FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT (17U) |
#define | FLEXSPI_AHBCR_ECCMULTIERRCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK) |
#define | FLEXSPI_AHBCR_HMSTRIDREMAP_MASK (0x40000U) |
#define | FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT (18U) |
#define | FLEXSPI_AHBCR_HMSTRIDREMAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT)) & FLEXSPI_AHBCR_HMSTRIDREMAP_MASK) |
#define | FLEXSPI_AHBCR_ECCSWAPEN_MASK (0x80000U) |
#define | FLEXSPI_AHBCR_ECCSWAPEN_SHIFT (19U) |
#define | FLEXSPI_AHBCR_ECCSWAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSWAPEN_SHIFT)) & FLEXSPI_AHBCR_ECCSWAPEN_MASK) |
#define | FLEXSPI_AHBCR_ALIGNMENT_MASK (0x300000U) |
#define | FLEXSPI_AHBCR_ALIGNMENT_SHIFT (20U) |
#define | FLEXSPI_AHBCR_ALIGNMENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK) |
INTEN - Interrupt Enable Register | |
#define | FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U) |
#define | FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U) |
#define | FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) |
#define | FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U) |
#define | FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U) |
#define | FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) |
#define | FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U) |
#define | FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U) |
#define | FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) |
#define | FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U) |
#define | FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U) |
#define | FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) |
#define | FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U) |
#define | FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U) |
#define | FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) |
#define | FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U) |
#define | FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U) |
#define | FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) |
#define | FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U) |
#define | FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U) |
#define | FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) |
#define | FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U) |
#define | FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U) |
#define | FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) |
#define | FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U) |
#define | FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U) |
#define | FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) |
#define | FLEXSPI_INTEN_AHBBUSERROREN_MASK (0x400U) |
#define | FLEXSPI_INTEN_AHBBUSERROREN_SHIFT (10U) |
#define | FLEXSPI_INTEN_AHBBUSERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK) |
#define | FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U) |
#define | FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U) |
#define | FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) |
#define | FLEXSPI_INTEN_KEYDONEEN_MASK (0x1000U) |
#define | FLEXSPI_INTEN_KEYDONEEN_SHIFT (12U) |
#define | FLEXSPI_INTEN_KEYDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK) |
#define | FLEXSPI_INTEN_KEYERROREN_MASK (0x2000U) |
#define | FLEXSPI_INTEN_KEYERROREN_SHIFT (13U) |
#define | FLEXSPI_INTEN_KEYERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK) |
#define | FLEXSPI_INTEN_ECCMULTIERREN_MASK (0x4000U) |
#define | FLEXSPI_INTEN_ECCMULTIERREN_SHIFT (14U) |
#define | FLEXSPI_INTEN_ECCMULTIERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCMULTIERREN_SHIFT)) & FLEXSPI_INTEN_ECCMULTIERREN_MASK) |
#define | FLEXSPI_INTEN_ECCSINGLEERREN_MASK (0x8000U) |
#define | FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT (15U) |
#define | FLEXSPI_INTEN_ECCSINGLEERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT)) & FLEXSPI_INTEN_ECCSINGLEERREN_MASK) |
#define | FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK (0x10000U) |
#define | FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT (16U) |
#define | FLEXSPI_INTEN_IPCMDSECUREVIOEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK) |
#define | PWM_INTEN_CMPIE_MASK (0x3FU) |
#define | PWM_INTEN_CMPIE_SHIFT (0U) |
#define | PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) |
#define | PWM_INTEN_CX0IE_MASK (0x40U) |
#define | PWM_INTEN_CX0IE_SHIFT (6U) |
#define | PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) |
#define | PWM_INTEN_CX1IE_MASK (0x80U) |
#define | PWM_INTEN_CX1IE_SHIFT (7U) |
#define | PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) |
#define | PWM_INTEN_CB0IE_MASK (0x100U) |
#define | PWM_INTEN_CB0IE_SHIFT (8U) |
#define | PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) |
#define | PWM_INTEN_CB1IE_MASK (0x200U) |
#define | PWM_INTEN_CB1IE_SHIFT (9U) |
#define | PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) |
#define | PWM_INTEN_CA0IE_MASK (0x400U) |
#define | PWM_INTEN_CA0IE_SHIFT (10U) |
#define | PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) |
#define | PWM_INTEN_CA1IE_MASK (0x800U) |
#define | PWM_INTEN_CA1IE_SHIFT (11U) |
#define | PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) |
#define | PWM_INTEN_RIE_MASK (0x1000U) |
#define | PWM_INTEN_RIE_SHIFT (12U) |
#define | PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) |
#define | PWM_INTEN_REIE_MASK (0x2000U) |
#define | PWM_INTEN_REIE_SHIFT (13U) |
#define | PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) |
#define | SEMC_INTEN_IPCMDDONEEN_MASK (0x1U) |
#define | SEMC_INTEN_IPCMDDONEEN_SHIFT (0U) |
#define | SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) |
#define | SEMC_INTEN_IPCMDERREN_MASK (0x2U) |
#define | SEMC_INTEN_IPCMDERREN_SHIFT (1U) |
#define | SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) |
#define | SEMC_INTEN_AXICMDERREN_MASK (0x4U) |
#define | SEMC_INTEN_AXICMDERREN_SHIFT (2U) |
#define | SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) |
#define | SEMC_INTEN_AXIBUSERREN_MASK (0x8U) |
#define | SEMC_INTEN_AXIBUSERREN_SHIFT (3U) |
#define | SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) |
#define | SEMC_INTEN_NDPAGEENDEN_MASK (0x10U) |
#define | SEMC_INTEN_NDPAGEENDEN_SHIFT (4U) |
#define | SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) |
#define | SEMC_INTEN_NDNOPENDEN_MASK (0x20U) |
#define | SEMC_INTEN_NDNOPENDEN_SHIFT (5U) |
#define | SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) |
INTR - Interrupt Register | |
#define | FLEXSPI_INTR_IPCMDDONE_MASK (0x1U) |
#define | FLEXSPI_INTR_IPCMDDONE_SHIFT (0U) |
#define | FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) |
#define | FLEXSPI_INTR_IPCMDGE_MASK (0x2U) |
#define | FLEXSPI_INTR_IPCMDGE_SHIFT (1U) |
#define | FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) |
#define | FLEXSPI_INTR_AHBCMDGE_MASK (0x4U) |
#define | FLEXSPI_INTR_AHBCMDGE_SHIFT (2U) |
#define | FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) |
#define | FLEXSPI_INTR_IPCMDERR_MASK (0x8U) |
#define | FLEXSPI_INTR_IPCMDERR_SHIFT (3U) |
#define | FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) |
#define | FLEXSPI_INTR_AHBCMDERR_MASK (0x10U) |
#define | FLEXSPI_INTR_AHBCMDERR_SHIFT (4U) |
#define | FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) |
#define | FLEXSPI_INTR_IPRXWA_MASK (0x20U) |
#define | FLEXSPI_INTR_IPRXWA_SHIFT (5U) |
#define | FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) |
#define | FLEXSPI_INTR_IPTXWE_MASK (0x40U) |
#define | FLEXSPI_INTR_IPTXWE_SHIFT (6U) |
#define | FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) |
#define | FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U) |
#define | FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U) |
#define | FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) |
#define | FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U) |
#define | FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U) |
#define | FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) |
#define | FLEXSPI_INTR_AHBBUSERROR_MASK (0x400U) |
#define | FLEXSPI_INTR_AHBBUSERROR_SHIFT (10U) |
#define | FLEXSPI_INTR_AHBBUSERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK) |
#define | FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U) |
#define | FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U) |
#define | FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) |
#define | FLEXSPI_INTR_KEYDONE_MASK (0x1000U) |
#define | FLEXSPI_INTR_KEYDONE_SHIFT (12U) |
#define | FLEXSPI_INTR_KEYDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK) |
#define | FLEXSPI_INTR_KEYERROR_MASK (0x2000U) |
#define | FLEXSPI_INTR_KEYERROR_SHIFT (13U) |
#define | FLEXSPI_INTR_KEYERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK) |
#define | FLEXSPI_INTR_ECCMULTIERR_MASK (0x4000U) |
#define | FLEXSPI_INTR_ECCMULTIERR_SHIFT (14U) |
#define | FLEXSPI_INTR_ECCMULTIERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCMULTIERR_SHIFT)) & FLEXSPI_INTR_ECCMULTIERR_MASK) |
#define | FLEXSPI_INTR_ECCSINGLEERR_MASK (0x8000U) |
#define | FLEXSPI_INTR_ECCSINGLEERR_SHIFT (15U) |
#define | FLEXSPI_INTR_ECCSINGLEERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCSINGLEERR_SHIFT)) & FLEXSPI_INTR_ECCSINGLEERR_MASK) |
#define | FLEXSPI_INTR_IPCMDSECUREVIO_MASK (0x10000U) |
#define | FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT (16U) |
#define | FLEXSPI_INTR_IPCMDSECUREVIO(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK) |
#define | SEMC_INTR_IPCMDDONE_MASK (0x1U) |
#define | SEMC_INTR_IPCMDDONE_SHIFT (0U) |
#define | SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) |
#define | SEMC_INTR_IPCMDERR_MASK (0x2U) |
#define | SEMC_INTR_IPCMDERR_SHIFT (1U) |
#define | SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) |
#define | SEMC_INTR_AXICMDERR_MASK (0x4U) |
#define | SEMC_INTR_AXICMDERR_SHIFT (2U) |
#define | SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) |
#define | SEMC_INTR_AXIBUSERR_MASK (0x8U) |
#define | SEMC_INTR_AXIBUSERR_SHIFT (3U) |
#define | SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) |
#define | SEMC_INTR_NDPAGEEND_MASK (0x10U) |
#define | SEMC_INTR_NDPAGEEND_SHIFT (4U) |
#define | SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) |
#define | SEMC_INTR_NDNOPEND_MASK (0x20U) |
#define | SEMC_INTR_NDNOPEND_SHIFT (5U) |
#define | SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) |
LUTKEY - LUT Key Register | |
#define | FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_LUTKEY_KEY_SHIFT (0U) |
#define | FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) |
LUTCR - LUT Control Register | |
#define | FLEXSPI_LUTCR_LOCK_MASK (0x1U) |
#define | FLEXSPI_LUTCR_LOCK_SHIFT (0U) |
#define | FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) |
#define | FLEXSPI_LUTCR_UNLOCK_MASK (0x2U) |
#define | FLEXSPI_LUTCR_UNLOCK_SHIFT (1U) |
#define | FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) |
#define | FLEXSPI_LUTCR_PROTECT_MASK (0x4U) |
#define | FLEXSPI_LUTCR_PROTECT_SHIFT (2U) |
#define | FLEXSPI_LUTCR_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK) |
AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 | |
#define | FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x3FFU) |
#define | FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U) |
#define | FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) |
#define | FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U) |
#define | FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U) |
#define | FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) |
#define | FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U) |
#define | FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U) |
#define | FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) |
#define | FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK (0x40000000U) |
#define | FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT (30U) |
#define | FLEXSPI_AHBRXBUFCR0_REGIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK) |
#define | FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U) |
#define | FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U) |
#define | FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) |
FLSHCR0 - Flash Control Register 0 | |
#define | FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU) |
#define | FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U) |
#define | FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) |
#define | FLEXSPI_FLSHCR0_SPLITWREN_MASK (0x40000000U) |
#define | FLEXSPI_FLSHCR0_SPLITWREN_SHIFT (30U) |
#define | FLEXSPI_FLSHCR0_SPLITWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK) |
#define | FLEXSPI_FLSHCR0_SPLITRDEN_MASK (0x80000000U) |
#define | FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT (31U) |
#define | FLEXSPI_FLSHCR0_SPLITRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK) |
FLSHCR1 - Flash Control Register 1 | |
#define | FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU) |
#define | FLEXSPI_FLSHCR1_TCSS_SHIFT (0U) |
#define | FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) |
#define | FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U) |
#define | FLEXSPI_FLSHCR1_TCSH_SHIFT (5U) |
#define | FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) |
#define | FLEXSPI_FLSHCR1_WA_MASK (0x400U) |
#define | FLEXSPI_FLSHCR1_WA_SHIFT (10U) |
#define | FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) |
#define | FLEXSPI_FLSHCR1_CAS_MASK (0x7800U) |
#define | FLEXSPI_FLSHCR1_CAS_SHIFT (11U) |
#define | FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) |
#define | FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U) |
#define | FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U) |
#define | FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) |
#define | FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U) |
#define | FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U) |
#define | FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) |
FLSHCR2 - Flash Control Register 2 | |
#define | FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU) |
#define | FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U) |
#define | FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) |
#define | FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U) |
#define | FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U) |
#define | FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) |
#define | FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U) |
#define | FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U) |
#define | FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) |
#define | FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U) |
#define | FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U) |
#define | FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) |
#define | FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U) |
#define | FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U) |
#define | FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK) |
#define | FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U) |
#define | FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U) |
#define | FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) |
#define | FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U) |
#define | FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U) |
#define | FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) |
FLSHCR4 - Flash Control Register 4 | |
#define | FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U) |
#define | FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U) |
#define | FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) |
#define | FLEXSPI_FLSHCR4_WMOPT2_MASK (0x2U) |
#define | FLEXSPI_FLSHCR4_WMOPT2_SHIFT (1U) |
#define | FLEXSPI_FLSHCR4_WMOPT2(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK) |
#define | FLEXSPI_FLSHCR4_WMENA_MASK (0x4U) |
#define | FLEXSPI_FLSHCR4_WMENA_SHIFT (2U) |
#define | FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) |
#define | FLEXSPI_FLSHCR4_WMENB_MASK (0x8U) |
#define | FLEXSPI_FLSHCR4_WMENB_SHIFT (3U) |
#define | FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) |
#define | FLEXSPI_FLSHCR4_PAR_WM_MASK (0x600U) |
#define | FLEXSPI_FLSHCR4_PAR_WM_SHIFT (9U) |
#define | FLEXSPI_FLSHCR4_PAR_WM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_WM_SHIFT)) & FLEXSPI_FLSHCR4_PAR_WM_MASK) |
#define | FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK (0x800U) |
#define | FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT (11U) |
#define | FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT)) & FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK) |
IPCR0 - IP Control Register 0 | |
#define | FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_IPCR0_SFAR_SHIFT (0U) |
#define | FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) |
IPCR1 - IP Control Register 1 | |
#define | FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU) |
#define | FLEXSPI_IPCR1_IDATSZ_SHIFT (0U) |
#define | FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) |
#define | FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U) |
#define | FLEXSPI_IPCR1_ISEQID_SHIFT (16U) |
#define | FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) |
#define | FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U) |
#define | FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U) |
#define | FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) |
#define | FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U) |
#define | FLEXSPI_IPCR1_IPAREN_SHIFT (31U) |
#define | FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) |
IPCMD - IP Command Register | |
#define | FLEXSPI_IPCMD_TRG_MASK (0x1U) |
#define | FLEXSPI_IPCMD_TRG_SHIFT (0U) |
#define | FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) |
#define | SEMC_IPCMD_CMD_MASK (0xFFFFU) |
#define | SEMC_IPCMD_CMD_SHIFT (0U) |
#define | SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK) |
#define | SEMC_IPCMD_KEY_MASK (0xFFFF0000U) |
#define | SEMC_IPCMD_KEY_SHIFT (16U) |
#define | SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) |
IPRXFCR - IP RX FIFO Control Register | |
#define | FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U) |
#define | FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U) |
#define | FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) |
#define | FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U) |
#define | FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U) |
#define | FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) |
#define | FLEXSPI_IPRXFCR_RXWMRK_MASK (0x7CU) |
#define | FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U) |
#define | FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) |
IPTXFCR - IP TX FIFO Control Register | |
#define | FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U) |
#define | FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U) |
#define | FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) |
#define | FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U) |
#define | FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U) |
#define | FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) |
#define | FLEXSPI_IPTXFCR_TXWMRK_MASK (0x7CU) |
#define | FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U) |
#define | FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) |
DLLCR - DLL Control Register 0 | |
#define | FLEXSPI_DLLCR_DLLEN_MASK (0x1U) |
#define | FLEXSPI_DLLCR_DLLEN_SHIFT (0U) |
#define | FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) |
#define | FLEXSPI_DLLCR_DLLRESET_MASK (0x2U) |
#define | FLEXSPI_DLLCR_DLLRESET_SHIFT (1U) |
#define | FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) |
#define | FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U) |
#define | FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U) |
#define | FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) |
#define | FLEXSPI_DLLCR_OVRDEN_MASK (0x100U) |
#define | FLEXSPI_DLLCR_OVRDEN_SHIFT (8U) |
#define | FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) |
#define | FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U) |
#define | FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U) |
#define | FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) |
MISCCR4 - Misc Control Register 4 | |
#define | FLEXSPI_MISCCR4_AHBADDRESS_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_MISCCR4_AHBADDRESS_SHIFT (0U) |
#define | FLEXSPI_MISCCR4_AHBADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR4_AHBADDRESS_SHIFT)) & FLEXSPI_MISCCR4_AHBADDRESS_MASK) |
MISCCR5 - Misc Control Register 5 | |
#define | FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT (0U) |
#define | FLEXSPI_MISCCR5_ECCSINGLEERRORCORR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT)) & FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK) |
MISCCR6 - Misc Control Register 6 | |
#define | FLEXSPI_MISCCR6_VALID_MASK (0x1U) |
#define | FLEXSPI_MISCCR6_VALID_SHIFT (0U) |
#define | FLEXSPI_MISCCR6_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_VALID_SHIFT)) & FLEXSPI_MISCCR6_VALID_MASK) |
#define | FLEXSPI_MISCCR6_HIT_MASK (0x2U) |
#define | FLEXSPI_MISCCR6_HIT_SHIFT (1U) |
#define | FLEXSPI_MISCCR6_HIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_HIT_SHIFT)) & FLEXSPI_MISCCR6_HIT_MASK) |
#define | FLEXSPI_MISCCR6_ADDRESS_MASK (0xFFFFFFFCU) |
#define | FLEXSPI_MISCCR6_ADDRESS_SHIFT (2U) |
#define | FLEXSPI_MISCCR6_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_ADDRESS_SHIFT)) & FLEXSPI_MISCCR6_ADDRESS_MASK) |
MISCCR7 - Misc Control Register 7 | |
#define | FLEXSPI_MISCCR7_VALID_MASK (0x1U) |
#define | FLEXSPI_MISCCR7_VALID_SHIFT (0U) |
#define | FLEXSPI_MISCCR7_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_VALID_SHIFT)) & FLEXSPI_MISCCR7_VALID_MASK) |
#define | FLEXSPI_MISCCR7_HIT_MASK (0x2U) |
#define | FLEXSPI_MISCCR7_HIT_SHIFT (1U) |
#define | FLEXSPI_MISCCR7_HIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_HIT_SHIFT)) & FLEXSPI_MISCCR7_HIT_MASK) |
#define | FLEXSPI_MISCCR7_ADDRESS_MASK (0xFFFFFFFCU) |
#define | FLEXSPI_MISCCR7_ADDRESS_SHIFT (2U) |
#define | FLEXSPI_MISCCR7_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_ADDRESS_SHIFT)) & FLEXSPI_MISCCR7_ADDRESS_MASK) |
STS0 - Status Register 0 | |
#define | FLEXSPI_STS0_SEQIDLE_MASK (0x1U) |
#define | FLEXSPI_STS0_SEQIDLE_SHIFT (0U) |
#define | FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) |
#define | FLEXSPI_STS0_ARBIDLE_MASK (0x2U) |
#define | FLEXSPI_STS0_ARBIDLE_SHIFT (1U) |
#define | FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) |
#define | FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU) |
#define | FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U) |
#define | FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) |
#define | SEMC_STS0_IDLE_MASK (0x1U) |
#define | SEMC_STS0_IDLE_SHIFT (0U) |
#define | SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) |
#define | SEMC_STS0_NARDY_MASK (0x2U) |
#define | SEMC_STS0_NARDY_SHIFT (1U) |
#define | SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) |
STS1 - Status Register 1 | |
#define | FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU) |
#define | FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U) |
#define | FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) |
#define | FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U) |
#define | FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U) |
#define | FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) |
#define | FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U) |
#define | FLEXSPI_STS1_IPCMDERRID_SHIFT (16U) |
#define | FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) |
#define | FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U) |
#define | FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U) |
#define | FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) |
STS2 - Status Register 2 | |
#define | FLEXSPI_STS2_ASLVLOCK_MASK (0x1U) |
#define | FLEXSPI_STS2_ASLVLOCK_SHIFT (0U) |
#define | FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) |
#define | FLEXSPI_STS2_AREFLOCK_MASK (0x2U) |
#define | FLEXSPI_STS2_AREFLOCK_SHIFT (1U) |
#define | FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) |
#define | FLEXSPI_STS2_ASLVSEL_MASK (0xFCU) |
#define | FLEXSPI_STS2_ASLVSEL_SHIFT (2U) |
#define | FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) |
#define | FLEXSPI_STS2_AREFSEL_MASK (0x3F00U) |
#define | FLEXSPI_STS2_AREFSEL_SHIFT (8U) |
#define | FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) |
#define | FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U) |
#define | FLEXSPI_STS2_BSLVLOCK_SHIFT (16U) |
#define | FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) |
#define | FLEXSPI_STS2_BREFLOCK_MASK (0x20000U) |
#define | FLEXSPI_STS2_BREFLOCK_SHIFT (17U) |
#define | FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) |
#define | FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U) |
#define | FLEXSPI_STS2_BSLVSEL_SHIFT (18U) |
#define | FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) |
#define | FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U) |
#define | FLEXSPI_STS2_BREFSEL_SHIFT (24U) |
#define | FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) |
#define | SEMC_STS2_NDWRPEND_MASK (0x8U) |
#define | SEMC_STS2_NDWRPEND_SHIFT (3U) |
#define | SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) |
AHBSPNDSTS - AHB Suspend Status Register | |
#define | FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U) |
#define | FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U) |
#define | FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) |
#define | FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU) |
#define | FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U) |
#define | FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) |
#define | FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U) |
#define | FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U) |
#define | FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) |
IPRXFSTS - IP RX FIFO Status Register | |
#define | FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU) |
#define | FLEXSPI_IPRXFSTS_FILL_SHIFT (0U) |
#define | FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) |
#define | FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U) |
#define | FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U) |
#define | FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) |
IPTXFSTS - IP TX FIFO Status Register | |
#define | FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU) |
#define | FLEXSPI_IPTXFSTS_FILL_SHIFT (0U) |
#define | FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) |
#define | FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U) |
#define | FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U) |
#define | FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) |
RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 | |
#define | FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_RFDR_RXDATA_SHIFT (0U) |
#define | FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) |
TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 | |
#define | FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU) |
#define | FLEXSPI_TFDR_TXDATA_SHIFT (0U) |
#define | FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) |
LUT - LUT 0..LUT 63 | |
#define | FLEXSPI_LUT_OPERAND0_MASK (0xFFU) |
#define | FLEXSPI_LUT_OPERAND0_SHIFT (0U) |
#define | FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) |
#define | FLEXSPI_LUT_NUM_PADS0_MASK (0x300U) |
#define | FLEXSPI_LUT_NUM_PADS0_SHIFT (8U) |
#define | FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) |
#define | FLEXSPI_LUT_OPCODE0_MASK (0xFC00U) |
#define | FLEXSPI_LUT_OPCODE0_SHIFT (10U) |
#define | FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) |
#define | FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U) |
#define | FLEXSPI_LUT_OPERAND1_SHIFT (16U) |
#define | FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) |
#define | FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U) |
#define | FLEXSPI_LUT_NUM_PADS1_SHIFT (24U) |
#define | FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) |
#define | FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U) |
#define | FLEXSPI_LUT_OPCODE1_SHIFT (26U) |
#define | FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) |
HMSTRCR - AHB Master ID 0 Control Register..AHB Master ID 7 Control Register | |
#define | FLEXSPI_HMSTRCR_MASK_MASK (0xFFFFU) |
#define | FLEXSPI_HMSTRCR_MASK_SHIFT (0U) |
#define | FLEXSPI_HMSTRCR_MASK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MASK_SHIFT)) & FLEXSPI_HMSTRCR_MASK_MASK) |
#define | FLEXSPI_HMSTRCR_MSTRID_MASK (0xFFFF0000U) |
#define | FLEXSPI_HMSTRCR_MSTRID_SHIFT (16U) |
#define | FLEXSPI_HMSTRCR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MSTRID_SHIFT)) & FLEXSPI_HMSTRCR_MSTRID_MASK) |
HADDRSTART - HADDR REMAP START ADDR | |
#define | FLEXSPI_HADDRSTART_REMAPEN_MASK (0x1U) |
#define | FLEXSPI_HADDRSTART_REMAPEN_SHIFT (0U) |
#define | FLEXSPI_HADDRSTART_REMAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK) |
#define | FLEXSPI_HADDRSTART_KBINECC_MASK (0x2U) |
#define | FLEXSPI_HADDRSTART_KBINECC_SHIFT (1U) |
#define | FLEXSPI_HADDRSTART_KBINECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_KBINECC_SHIFT)) & FLEXSPI_HADDRSTART_KBINECC_MASK) |
#define | FLEXSPI_HADDRSTART_ADDRSTART_MASK (0xFFFFF000U) |
#define | FLEXSPI_HADDRSTART_ADDRSTART_SHIFT (12U) |
#define | FLEXSPI_HADDRSTART_ADDRSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_ADDRSTART_SHIFT)) & FLEXSPI_HADDRSTART_ADDRSTART_MASK) |
IPSNSZSTART0 - IPS nonsecure region Start address of region 0 | |
#define | FLEXSPI_IPSNSZSTART0_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_IPSNSZSTART0_start_address_SHIFT (12U) |
#define | FLEXSPI_IPSNSZSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART0_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART0_start_address_MASK) |
IPSNSZEND0 - IPS nonsecure region End address of region 0 | |
#define | FLEXSPI_IPSNSZEND0_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_IPSNSZEND0_end_address_SHIFT (12U) |
#define | FLEXSPI_IPSNSZEND0_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND0_end_address_SHIFT)) & FLEXSPI_IPSNSZEND0_end_address_MASK) |
IPSNSZSTART1 - IPS nonsecure region Start address of region 1 | |
#define | FLEXSPI_IPSNSZSTART1_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_IPSNSZSTART1_start_address_SHIFT (12U) |
#define | FLEXSPI_IPSNSZSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART1_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART1_start_address_MASK) |
IPSNSZEND1 - IPS nonsecure region End address of region 1 | |
#define | FLEXSPI_IPSNSZEND1_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_IPSNSZEND1_end_address_SHIFT (12U) |
#define | FLEXSPI_IPSNSZEND1_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND1_end_address_SHIFT)) & FLEXSPI_IPSNSZEND1_end_address_MASK) |
AHBBUFREGIONSTART0 - RX BUF Start address of region 0 | |
#define | FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK) |
AHBBUFREGIONEND0 - RX BUF region End address of region 0 | |
#define | FLEXSPI_AHBBUFREGIONEND0_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONEND0_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_end_address_MASK) |
AHBBUFREGIONSTART1 - RX BUF Start address of region 1 | |
#define | FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK) |
AHBBUFREGIONEND1 - RX BUF region End address of region 1 | |
#define | FLEXSPI_AHBBUFREGIONEND1_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONEND1_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_end_address_MASK) |
AHBBUFREGIONSTART2 - RX BUF Start address of region 2 | |
#define | FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONSTART2_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK) |
AHBBUFREGIONEND2 - RX BUF region End address of region 2 | |
#define | FLEXSPI_AHBBUFREGIONEND2_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONEND2_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_end_address_MASK) |
AHBBUFREGIONSTART3 - RX BUF Start address of region 3 | |
#define | FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONSTART3_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK) |
AHBBUFREGIONEND3 - RX BUF region End address of region 3 | |
#define | FLEXSPI_AHBBUFREGIONEND3_end_address_MASK (0xFFFFF000U) |
#define | FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT (12U) |
#define | FLEXSPI_AHBBUFREGIONEND3_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_end_address_MASK) |
#define FLEXSPI_AHBBUFREGIONEND0_end_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_end_address_MASK) |
end_address - End address of region 0. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBBUFREGIONEND0_end_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_end_address_MASK) |
end_address - End address of region 0. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBBUFREGIONEND1_end_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_end_address_MASK) |
end_address - End address of region 1. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBBUFREGIONEND1_end_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_end_address_MASK) |
end_address - End address of region 1. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBBUFREGIONEND2_end_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_end_address_MASK) |
end_address - End address of region 2. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBBUFREGIONEND2_end_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_end_address_MASK) |
end_address - End address of region 2. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBBUFREGIONEND3_end_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_end_address_MASK) |
end_address - End address of region 3. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBBUFREGIONEND3_end_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_end_address_MASK) |
end_address - End address of region 3. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBBUFREGIONSTART0_start_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK) |
start_address - Start address of region 0. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBBUFREGIONSTART0_start_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK) |
start_address - Start address of region 0. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBBUFREGIONSTART1_start_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK) |
start_address - Start address of region 1. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBBUFREGIONSTART1_start_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK) |
start_address - Start address of region 1. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBBUFREGIONSTART2_start_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK) |
start_address - Start address of region 2. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBBUFREGIONSTART2_start_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK) |
start_address - Start address of region 2. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBBUFREGIONSTART3_start_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK) |
start_address - Start address of region 3. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBBUFREGIONSTART3_start_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK) |
start_address - Start address of region 3. Minimal 4K Bytes aligned. It is system address.
#define FLEXSPI_AHBCR_ALIGNMENT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK) |
ALIGNMENT - Decides all AHB read/write boundary. All access cross the boundary will be divided into smaller sub accesses. 0b00..No limit 0b01..1 KBytes 0b10..512 Bytes 0b11..256 Bytes
#define FLEXSPI_AHBCR_ALIGNMENT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK) |
ALIGNMENT - Decides all AHB read/write boundary. All access cross the boundary will be divided into smaller sub accesses. 0b00..No limit 0b01..1 KBytes 0b10..512 Bytes 0b11..256 Bytes
#define FLEXSPI_AHBCR_APAREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) |
APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . 0b0..Flash will be accessed in Individual mode. 0b1..Flash will be accessed in Parallel mode.
#define FLEXSPI_AHBCR_APAREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) |
APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . 0b0..Flash will be accessed in Individual mode. 0b1..Flash will be accessed in Parallel mode.
#define FLEXSPI_AHBCR_APAREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK) |
APAREN - Parallel mode enabled for AHB triggered Command (both read and write) . 0b0..Flash will be accessed in Individual mode. 0b1..Flash will be accessed in Parallel mode.
#define FLEXSPI_AHBCR_BUFFERABLEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) |
BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished.
#define FLEXSPI_AHBCR_BUFFERABLEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) |
BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished.
#define FLEXSPI_AHBCR_BUFFERABLEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK) |
BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat of AHB write access, refer for more details about AHB bufferable write. 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus ready after all data is transmitted to External device and AHB command finished. 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is granted by arbitrator and will not wait for AHB command finished.
#define FLEXSPI_AHBCR_CACHABLEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) |
CACHABLEEN - Enable AHB bus cachable read access support. 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
#define FLEXSPI_AHBCR_CACHABLEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) |
CACHABLEEN - Enable AHB bus cachable read access support. 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
#define FLEXSPI_AHBCR_CACHABLEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK) |
CACHABLEEN - Enable AHB bus cachable read access support. 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer. 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
#define FLEXSPI_AHBCR_CLRAHBRXBUF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK) |
CLRAHBRXBUF - Clear the status/pointers of AHB RX Buffer. Auto-cleared.
#define FLEXSPI_AHBCR_CLRAHBRXBUF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK) |
CLRAHBRXBUF - Clear the status/pointers of AHB RX Buffer. Auto-cleared.
#define FLEXSPI_AHBCR_ECCEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCEN_SHIFT)) & FLEXSPI_AHBCR_ECCEN_MASK) |
ECCEN - AHB Read ECC Enable 0b0..AHB read ECC check disabled 0b1..AHB read ECC check enabled
#define FLEXSPI_AHBCR_ECCEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCEN_SHIFT)) & FLEXSPI_AHBCR_ECCEN_MASK) |
ECCEN - AHB Read ECC Enable 0b0..AHB read ECC check disabled 0b1..AHB read ECC check enabled
#define FLEXSPI_AHBCR_ECCMULTIERRCLR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK) |
ECCMULTIERRCLR - AHB ECC Multi bits ERR CLR
#define FLEXSPI_AHBCR_ECCMULTIERRCLR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK) |
ECCMULTIERRCLR - AHB ECC Multi bits ERR CLR
#define FLEXSPI_AHBCR_ECCSINGLEERRCLR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK) |
ECCSINGLEERRCLR - AHB ECC Single bit ERR CLR
#define FLEXSPI_AHBCR_ECCSINGLEERRCLR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK) |
ECCSINGLEERRCLR - AHB ECC Single bit ERR CLR
#define FLEXSPI_AHBCR_ECCSWAPEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSWAPEN_SHIFT)) & FLEXSPI_AHBCR_ECCSWAPEN_MASK) |
ECCSWAPEN - ECC Read data swap function 0b0..rdata send to ecc check without swap. 0b1..rdata send to ecc ehck with swap.
#define FLEXSPI_AHBCR_ECCSWAPEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSWAPEN_SHIFT)) & FLEXSPI_AHBCR_ECCSWAPEN_MASK) |
ECCSWAPEN - ECC Read data swap function 0b0..rdata send to ecc check without swap. 0b1..rdata send to ecc ehck with swap.
#define FLEXSPI_AHBCR_HMSTRIDREMAP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT)) & FLEXSPI_AHBCR_HMSTRIDREMAP_MASK) |
HMSTRIDREMAP - AHB Master ID Remapping enable
#define FLEXSPI_AHBCR_HMSTRIDREMAP | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT)) & FLEXSPI_AHBCR_HMSTRIDREMAP_MASK) |
HMSTRIDREMAP - AHB Master ID Remapping enable
#define FLEXSPI_AHBCR_KEYECCEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_KEYECCEN_SHIFT)) & FLEXSPI_AHBCR_KEYECCEN_MASK) |
KEYECCEN - OTFAD KEY BLOC ECC Enable 0b0..AHB KEY ECC check disabled 0b1..AHB KEY ECC check enabled
#define FLEXSPI_AHBCR_KEYECCEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_KEYECCEN_SHIFT)) & FLEXSPI_AHBCR_KEYECCEN_MASK) |
KEYECCEN - OTFAD KEY BLOC ECC Enable 0b0..AHB KEY ECC check disabled 0b1..AHB KEY ECC check enabled
#define FLEXSPI_AHBCR_PREFETCHEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) |
PREFETCHEN - AHB Read Prefetch Enable.
#define FLEXSPI_AHBCR_PREFETCHEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) |
PREFETCHEN - AHB Read Prefetch Enable.
#define FLEXSPI_AHBCR_PREFETCHEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK) |
PREFETCHEN - AHB Read Prefetch Enable.
#define FLEXSPI_AHBCR_READADDROPT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) |
READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is wordaddressable. 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB burst required to meet the alignment requirement.
#define FLEXSPI_AHBCR_READADDROPT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) |
READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is word-addressable. 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB burst required to meet the alignment requirement.
#define FLEXSPI_AHBCR_READADDROPT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK) |
READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation. 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is word-addressable. 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB burst required to meet the alignment requirement.
#define FLEXSPI_AHBCR_READSZALIGN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK) |
READSZALIGN - AHB Read Size Alignment 0b0..AHB read size will be decided by other register setting like PREFETCH_EN,OTFAD_EN... 0b1..AHB read size to up size to 8 bytes aligned, no prefetching
#define FLEXSPI_AHBCR_READSZALIGN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK) |
READSZALIGN - AHB Read Size Alignment 0b0..AHB read size will be decided by other register setting like PREFETCH_EN,OTFAD_EN... 0b1..AHB read size to up size to 8 bytes aligned, no prefetching
#define FLEXSPI_AHBCR_SPLIT_LIMIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT)) & FLEXSPI_AHBCR_SPLIT_LIMIT_MASK) |
SPLIT_LIMIT - AHB SPLIT SIZE 0b00..AHB Split Size=8bytes 0b01..AHB Split Size=16bytes 0b10..AHB Split Size=32bytes 0b11..AHB Split Size=64bytes
#define FLEXSPI_AHBCR_SPLIT_LIMIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT)) & FLEXSPI_AHBCR_SPLIT_LIMIT_MASK) |
SPLIT_LIMIT - AHB SPLIT SIZE 0b00..AHB Split Size=8bytes 0b01..AHB Split Size=16bytes 0b10..AHB Split Size=32bytes 0b11..AHB Split Size=64bytes
#define FLEXSPI_AHBCR_SPLITEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLITEN_SHIFT)) & FLEXSPI_AHBCR_SPLITEN_MASK) |
SPLITEN - AHB transaction SPLIT 0b0..AHB Split disabled 0b1..AHB Split enabled
#define FLEXSPI_AHBCR_SPLITEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLITEN_SHIFT)) & FLEXSPI_AHBCR_SPLITEN_MASK) |
SPLITEN - AHB transaction SPLIT 0b0..AHB Split disabled 0b1..AHB Split enabled
#define FLEXSPI_AHBRXBUFCR0_BUFSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) |
BUFSZ - AHB RX Buffer Size in 64 bits.
#define FLEXSPI_AHBRXBUFCR0_BUFSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) |
BUFSZ - AHB RX Buffer Size in 64 bits.
#define FLEXSPI_AHBRXBUFCR0_BUFSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK) |
BUFSZ - AHB RX Buffer Size in 64 bits.
#define FLEXSPI_AHBRXBUFCR0_MSTRID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) |
MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).
#define FLEXSPI_AHBRXBUFCR0_MSTRID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) |
MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).
#define FLEXSPI_AHBRXBUFCR0_MSTRID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK) |
MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) |
PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) |
PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK) |
PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
#define FLEXSPI_AHBRXBUFCR0_PRIORITY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) |
PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned.
#define FLEXSPI_AHBRXBUFCR0_PRIORITY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) |
PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest.
#define FLEXSPI_AHBRXBUFCR0_PRIORITY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK) |
PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest.
#define FLEXSPI_AHBRXBUFCR0_REGIONEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK) |
REGIONEN - AHB RX Buffer address region funciton enable
#define FLEXSPI_AHBRXBUFCR0_REGIONEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK) |
REGIONEN - AHB RX Buffer address region funciton enable
#define FLEXSPI_AHBSPNDSTS_ACTIVE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) |
ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended.
#define FLEXSPI_AHBSPNDSTS_ACTIVE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) |
ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended.
#define FLEXSPI_AHBSPNDSTS_ACTIVE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK) |
ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended.
#define FLEXSPI_AHBSPNDSTS_BUFID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) |
BUFID - AHB RX BUF ID for suspended command sequence.
#define FLEXSPI_AHBSPNDSTS_BUFID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) |
BUFID - AHB RX BUF ID for suspended command sequence.
#define FLEXSPI_AHBSPNDSTS_BUFID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK) |
BUFID - AHB RX BUF ID for suspended command sequence.
#define FLEXSPI_AHBSPNDSTS_DATLFT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) |
DATLFT - Left Data size for suspended command sequence (in byte).
#define FLEXSPI_AHBSPNDSTS_DATLFT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) |
DATLFT - Left Data size for suspended command sequence (in byte).
#define FLEXSPI_AHBSPNDSTS_DATLFT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK) |
DATLFT - Left Data size for suspended command sequence (in byte).
#define FLEXSPI_DLLCR_DLLEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) |
DLLEN - DLL calibration enable.
#define FLEXSPI_DLLCR_DLLEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) |
DLLEN - DLL calibration enable.
#define FLEXSPI_DLLCR_DLLEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK) |
DLLEN - DLL calibration enable.
#define FLEXSPI_DLLCR_DLLRESET | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) |
DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation).
#define FLEXSPI_DLLCR_DLLRESET | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) |
DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation).
#define FLEXSPI_DLLCR_DLLRESET | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK) |
DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset action is edge triggered, so software need to clear this bit after set this bit (no delay limitation).
#define FLEXSPI_DLLCR_OVRDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) |
OVRDEN - Slave clock delay line delay cell number selection override enable.
#define FLEXSPI_DLLCR_OVRDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) |
OVRDEN - Slave clock delay line delay cell number selection override enable.
#define FLEXSPI_DLLCR_OVRDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK) |
OVRDEN - Slave clock delay line delay cell number selection override enable.
#define FLEXSPI_DLLCR_OVRDVAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) |
OVRDVAL - Slave clock delay line delay cell number selection override value.
#define FLEXSPI_DLLCR_OVRDVAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) |
OVRDVAL - Slave clock delay line delay cell number selection override value.
#define FLEXSPI_DLLCR_OVRDVAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK) |
OVRDVAL - Slave clock delay line delay cell number selection override value.
#define FLEXSPI_DLLCR_SLVDLYTARGET | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) |
SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock).
#define FLEXSPI_DLLCR_SLVDLYTARGET | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) |
SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1, OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended.
#define FLEXSPI_DLLCR_SLVDLYTARGET | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK) |
SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1, OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended.
#define FLEXSPI_FLSHCR0_FLSHSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) |
FLSHSZ - Flash Size in KByte.
#define FLEXSPI_FLSHCR0_FLSHSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) |
FLSHSZ - Flash Size in KByte.
#define FLEXSPI_FLSHCR0_FLSHSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK) |
FLSHSZ - Flash Size in KByte.
#define FLEXSPI_FLSHCR0_SPLITRDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK) |
SPLITRDEN - AHB read access split function control.
#define FLEXSPI_FLSHCR0_SPLITRDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK) |
SPLITRDEN - AHB read access split function control.
#define FLEXSPI_FLSHCR0_SPLITWREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK) |
SPLITWREN - AHB write access split function control.
#define FLEXSPI_FLSHCR0_SPLITWREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK) |
SPLITWREN - AHB write access split function control.
#define FLEXSPI_FLSHCR1_CAS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) |
CAS - Column Address Size.
#define FLEXSPI_FLSHCR1_CAS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) |
CAS - Column Address Size.
#define FLEXSPI_FLSHCR1_CAS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK) |
CAS - Column Address Size.
#define FLEXSPI_FLSHCR1_CSINTERVAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) |
CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0.
#define FLEXSPI_FLSHCR1_CSINTERVAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) |
CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0.
#define FLEXSPI_FLSHCR1_CSINTERVAL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK) |
CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection deassertion and flash device Chip selection assertion. If external flash has a limitation on the interval between command sequences, this field should be set accordingly. If there is no limitation, set this field with value 0x0.
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) |
CSINTERVALUNIT - CS interval unit 0b0..The CS interval unit is 1 serial clock cycle 0b1..The CS interval unit is 256 serial clock cycle
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) |
CSINTERVALUNIT - CS interval unit 0b0..The CS interval unit is 1 serial clock cycle 0b1..The CS interval unit is 256 serial clock cycle
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK) |
CSINTERVALUNIT - CS interval unit 0b0..The CS interval unit is 1 serial clock cycle 0b1..The CS interval unit is 256 serial clock cycle
#define FLEXSPI_FLSHCR1_TCSH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) |
TCSH - Serial Flash CS Hold time.
#define FLEXSPI_FLSHCR1_TCSH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) |
TCSH - Serial Flash CS Hold time.
#define FLEXSPI_FLSHCR1_TCSH | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK) |
TCSH - Serial Flash CS Hold time.
#define FLEXSPI_FLSHCR1_TCSS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) |
TCSS - Serial Flash CS setup time.
#define FLEXSPI_FLSHCR1_TCSS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) |
TCSS - Serial Flash CS setup time.
#define FLEXSPI_FLSHCR1_TCSS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK) |
TCSS - Serial Flash CS setup time.
#define FLEXSPI_FLSHCR1_WA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) |
WA - Word Addressable.
#define FLEXSPI_FLSHCR1_WA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) |
WA - Word Addressable.
#define FLEXSPI_FLSHCR1_WA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK) |
WA - Word Addressable.
#define FLEXSPI_FLSHCR2_ARDSEQID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) |
ARDSEQID - Sequence Index for AHB Read triggered Command in LUT.
#define FLEXSPI_FLSHCR2_ARDSEQID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) |
ARDSEQID - Sequence Index for AHB Read triggered Command in LUT.
#define FLEXSPI_FLSHCR2_ARDSEQID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK) |
ARDSEQID - Sequence Index for AHB Read triggered Command in LUT.
#define FLEXSPI_FLSHCR2_ARDSEQNUM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) |
ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT.
#define FLEXSPI_FLSHCR2_ARDSEQNUM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) |
ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT.
#define FLEXSPI_FLSHCR2_ARDSEQNUM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK) |
ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT.
#define FLEXSPI_FLSHCR2_AWRSEQID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) |
AWRSEQID - Sequence Index for AHB Write triggered Command.
#define FLEXSPI_FLSHCR2_AWRSEQID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) |
AWRSEQID - Sequence Index for AHB Write triggered Command.
#define FLEXSPI_FLSHCR2_AWRSEQID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK) |
AWRSEQID - Sequence Index for AHB Write triggered Command.
#define FLEXSPI_FLSHCR2_AWRSEQNUM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) |
AWRSEQNUM - Sequence Number for AHB Write triggered Command.
#define FLEXSPI_FLSHCR2_AWRSEQNUM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) |
AWRSEQNUM - Sequence Number for AHB Write triggered Command.
#define FLEXSPI_FLSHCR2_AWRSEQNUM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK) |
AWRSEQNUM - Sequence Number for AHB Write triggered Command.
#define FLEXSPI_FLSHCR2_AWRWAITUNIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) |
AWRWAITUNIT - AWRWAIT unit 0b000..The AWRWAIT unit is 2 ahb clock cycle 0b001..The AWRWAIT unit is 8 ahb clock cycle 0b010..The AWRWAIT unit is 32 ahb clock cycle 0b011..The AWRWAIT unit is 128 ahb clock cycle 0b100..The AWRWAIT unit is 512 ahb clock cycle 0b101..The AWRWAIT unit is 2048 ahb clock cycle 0b110..The AWRWAIT unit is 8192 ahb clock cycle 0b111..The AWRWAIT unit is 32768 ahb clock cycle
#define FLEXSPI_FLSHCR2_AWRWAITUNIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) |
AWRWAITUNIT - AWRWAIT unit 0b000..The AWRWAIT unit is 2 ahb clock cycle 0b001..The AWRWAIT unit is 8 ahb clock cycle 0b010..The AWRWAIT unit is 32 ahb clock cycle 0b011..The AWRWAIT unit is 128 ahb clock cycle 0b100..The AWRWAIT unit is 512 ahb clock cycle 0b101..The AWRWAIT unit is 2048 ahb clock cycle 0b110..The AWRWAIT unit is 8192 ahb clock cycle 0b111..The AWRWAIT unit is 32768 ahb clock cycle
#define FLEXSPI_FLSHCR2_AWRWAITUNIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK) |
AWRWAITUNIT - AWRWAIT unit 0b000..The AWRWAIT unit is 2 ahb clock cycle 0b001..The AWRWAIT unit is 8 ahb clock cycle 0b010..The AWRWAIT unit is 32 ahb clock cycle 0b011..The AWRWAIT unit is 128 ahb clock cycle 0b100..The AWRWAIT unit is 512 ahb clock cycle 0b101..The AWRWAIT unit is 2048 ahb clock cycle 0b110..The AWRWAIT unit is 8192 ahb clock cycle 0b111..The AWRWAIT unit is 32768 ahb clock cycle
#define FLEXSPI_FLSHCR2_CLRINSTRPTR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) |
CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details.
#define FLEXSPI_FLSHCR2_CLRINSTRPTR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) |
CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details.
#define FLEXSPI_FLSHCR2_CLRINSTRPTR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK) |
CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS. Refer Programmable Sequence Engine for details.
#define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT)) & FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK) |
PAR_ADDR_ADJ_DIS - Disable the address shift logic for lower density of 16 bit PSRAM.
#define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT)) & FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK) |
PAR_ADDR_ADJ_DIS - Disable the address shift logic for lower density of 16 bit PSRAM.
#define FLEXSPI_FLSHCR4_PAR_WM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_WM_SHIFT)) & FLEXSPI_FLSHCR4_PAR_WM_MASK) |
PAR_WM - Enable APMEM 16 bit write mask function, bit 9 for A1-B1 pair, bit 10 for A2-B2 pair.
#define FLEXSPI_FLSHCR4_PAR_WM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_WM_SHIFT)) & FLEXSPI_FLSHCR4_PAR_WM_MASK) |
PAR_WM - Enable APMEM 16 bit write mask function, bit 9 for A1-B1 pair, bit 10 for A2-B2 pair.
#define FLEXSPI_FLSHCR4_WMENA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) |
WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set. 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
#define FLEXSPI_FLSHCR4_WMENA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) |
WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set. 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
#define FLEXSPI_FLSHCR4_WMENA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK) |
WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for memory device on port A, this bit must be set. 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
#define FLEXSPI_FLSHCR4_WMENB | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) |
WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set. 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
#define FLEXSPI_FLSHCR4_WMENB | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) |
WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set. 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
#define FLEXSPI_FLSHCR4_WMENB | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK) |
WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for memory device on port B, this bit must be set. 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device. 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
#define FLEXSPI_FLSHCR4_WMOPT1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) |
WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode. 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode.
#define FLEXSPI_FLSHCR4_WMOPT1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) |
WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode. 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode.
#define FLEXSPI_FLSHCR4_WMOPT1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK) |
WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation. 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst start address alignment when flash is accessed in individual mode. 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst start address alignment when flash is accessed in individual mode.
#define FLEXSPI_FLSHCR4_WMOPT2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK) |
WMOPT2 - Write mask option bit 2. When using AP memory, This option bit could be used to remove AHB write burst minimal length limitation. When using this bit, WMOPT1 should also be set. 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst length when flash is accessed in individual mode. 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst length when flash is accessed in individual mode, the minimal write burst length should be 4.
#define FLEXSPI_FLSHCR4_WMOPT2 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK) |
WMOPT2 - Write mask option bit 2. When using AP memory, This option bit could be used to remove AHB write burst minimal length limitation. When using this bit, WMOPT1 should also be set. 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write burst length when flash is accessed in individual mode. 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write burst length when flash is accessed in individual mode, the minimal write burst length should be 4.
#define FLEXSPI_HADDRSTART_KBINECC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_KBINECC_SHIFT)) & FLEXSPI_HADDRSTART_KBINECC_MASK) |
KBINECC 0b0..If key blob is in remap region, FlexSPI will fetch keyblob at base address + offset 0b1..If key blob is in remap region, FlexSPI will fetch keyblob at base address + offset*2
#define FLEXSPI_HADDRSTART_KBINECC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_KBINECC_SHIFT)) & FLEXSPI_HADDRSTART_KBINECC_MASK) |
KBINECC 0b0..If key blob is in remap region, FlexSPI will fetch keyblob at base address + offset 0b1..If key blob is in remap region, FlexSPI will fetch keyblob at base address + offset*2
#define FLEXSPI_HADDRSTART_REMAPEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK) |
REMAPEN 0b0..HADDR REMAP Disabled 0b1..HADDR REMAP Enabled
#define FLEXSPI_HADDRSTART_REMAPEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK) |
REMAPEN 0b0..HADDR REMAP Disabled 0b1..HADDR REMAP Enabled
#define FLEXSPI_HMSTRCR_MASK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MASK_SHIFT)) & FLEXSPI_HMSTRCR_MASK_MASK) |
MASK - Mask bits for AHB master ID. 0b0000000000000000..Mask 0b0000000000000001..Unmask
#define FLEXSPI_HMSTRCR_MASK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MASK_SHIFT)) & FLEXSPI_HMSTRCR_MASK_MASK) |
MASK - Mask bits for AHB master ID. 0b0000000000000000..Mask 0b0000000000000001..Unmask
#define FLEXSPI_HMSTRCR_MSTRID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MSTRID_SHIFT)) & FLEXSPI_HMSTRCR_MSTRID_MASK) |
MSTRID - This is expected Master ID.
#define FLEXSPI_HMSTRCR_MSTRID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MSTRID_SHIFT)) & FLEXSPI_HMSTRCR_MSTRID_MASK) |
MSTRID - This is expected Master ID.
#define FLEXSPI_INTEN_AHBBUSERROREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK) |
AHBBUSERROREN - AHB Bus error interrupt enable.Refer Interrupts chapter for more details.
#define FLEXSPI_INTEN_AHBBUSERROREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK) |
AHBBUSERROREN - AHB Bus error interrupt enable.Refer Interrupts chapter for more details.
#define FLEXSPI_INTEN_AHBBUSTIMEOUTEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_AHBBUSTIMEOUTEN_MASK) |
AHBBUSTIMEOUTEN - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
#define FLEXSPI_INTEN_AHBCMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) |
AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable.
#define FLEXSPI_INTEN_AHBCMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) |
AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable.
#define FLEXSPI_INTEN_AHBCMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK) |
AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable.
#define FLEXSPI_INTEN_AHBCMDGEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) |
AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable.
#define FLEXSPI_INTEN_AHBCMDGEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) |
AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable.
#define FLEXSPI_INTEN_AHBCMDGEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK) |
AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable.
#define FLEXSPI_INTEN_ECCMULTIERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCMULTIERREN_SHIFT)) & FLEXSPI_INTEN_ECCMULTIERREN_MASK) |
ECCMULTIERREN - ECC multi bits error interrupt enable.Refer Interrupts chapter for more details.
#define FLEXSPI_INTEN_ECCMULTIERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCMULTIERREN_SHIFT)) & FLEXSPI_INTEN_ECCMULTIERREN_MASK) |
ECCMULTIERREN - ECC multi bits error interrupt enable.Refer Interrupts chapter for more details.
#define FLEXSPI_INTEN_ECCSINGLEERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT)) & FLEXSPI_INTEN_ECCSINGLEERREN_MASK) |
ECCSINGLEERREN - ECC single bit error interrupt enable.Refer Interrupts chapter for more details.
#define FLEXSPI_INTEN_ECCSINGLEERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT)) & FLEXSPI_INTEN_ECCSINGLEERREN_MASK) |
ECCSINGLEERREN - ECC single bit error interrupt enable.Refer Interrupts chapter for more details.
#define FLEXSPI_INTEN_IPCMDDONEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) |
IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable.
#define FLEXSPI_INTEN_IPCMDDONEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) |
IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable.
#define FLEXSPI_INTEN_IPCMDDONEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK) |
IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable.
#define FLEXSPI_INTEN_IPCMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) |
IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable.
#define FLEXSPI_INTEN_IPCMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) |
IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable.
#define FLEXSPI_INTEN_IPCMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK) |
IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable.
#define FLEXSPI_INTEN_IPCMDGEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) |
IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable.
#define FLEXSPI_INTEN_IPCMDGEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) |
IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable.
#define FLEXSPI_INTEN_IPCMDGEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK) |
IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable.
#define FLEXSPI_INTEN_IPCMDSECUREVIOEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK) |
IPCMDSECUREVIOEN - IP command security violation interrupt enable.
#define FLEXSPI_INTEN_IPCMDSECUREVIOEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK) |
IPCMDSECUREVIOEN - IP command security violation interrupt enable.
#define FLEXSPI_INTEN_IPRXWAEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) |
IPRXWAEN - IP RX FIFO WaterMark available interrupt enable.
#define FLEXSPI_INTEN_IPRXWAEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) |
IPRXWAEN - IP RX FIFO WaterMark available interrupt enable.
#define FLEXSPI_INTEN_IPRXWAEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK) |
IPRXWAEN - IP RX FIFO WaterMark available interrupt enable.
#define FLEXSPI_INTEN_IPTXWEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) |
IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable.
#define FLEXSPI_INTEN_IPTXWEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) |
IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable.
#define FLEXSPI_INTEN_IPTXWEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK) |
IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable.
#define FLEXSPI_INTEN_KEYDONEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK) |
KEYDONEEN - OTFAD key blob processing done interrupt enable.Refer Interrupts chapter for more details.
#define FLEXSPI_INTEN_KEYDONEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK) |
KEYDONEEN - OTFAD key blob processing done interrupt enable.Refer Interrupts chapter for more details.
#define FLEXSPI_INTEN_KEYERROREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK) |
KEYERROREN - OTFAD key blob processing error interrupt enable.Refer Interrupts chapter for more details.
#define FLEXSPI_INTEN_KEYERROREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK) |
KEYERROREN - OTFAD key blob processing error interrupt enable.Refer Interrupts chapter for more details.
#define FLEXSPI_INTEN_SCKSTOPBYRDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) |
SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable.
#define FLEXSPI_INTEN_SCKSTOPBYRDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) |
SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable.
#define FLEXSPI_INTEN_SCKSTOPBYRDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK) |
SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable.
#define FLEXSPI_INTEN_SCKSTOPBYWREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) |
SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable.
#define FLEXSPI_INTEN_SCKSTOPBYWREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) |
SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable.
#define FLEXSPI_INTEN_SCKSTOPBYWREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK) |
SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable.
#define FLEXSPI_INTEN_SEQTIMEOUTEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) |
SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.
#define FLEXSPI_INTEN_SEQTIMEOUTEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) |
SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.
#define FLEXSPI_INTEN_SEQTIMEOUTEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK) |
SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.
#define FLEXSPI_INTR_AHBBUSERROR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK) |
AHBBUSERROR - AHB Bus timeout or AHB bus illegal access Flash during OTFAD key blob processing interrupt.
#define FLEXSPI_INTR_AHBBUSERROR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK) |
AHBBUSERROR - AHB Bus timeout or AHB bus illegal access Flash during OTFAD key blob processing interrupt.
#define FLEXSPI_INTR_AHBBUSTIMEOUT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSTIMEOUT_SHIFT)) & FLEXSPI_INTR_AHBBUSTIMEOUT_MASK) |
AHBBUSTIMEOUT - AHB Bus timeout interrupt.Refer Interrupts chapter for more details.
#define FLEXSPI_INTR_AHBCMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) |
AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all.
#define FLEXSPI_INTR_AHBCMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) |
AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all.
#define FLEXSPI_INTR_AHBCMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK) |
AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for AHB command, this command will be ignored and not executed at all.
#define FLEXSPI_INTR_AHBCMDGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) |
AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt.
#define FLEXSPI_INTR_AHBCMDGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) |
AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt.
#define FLEXSPI_INTR_AHBCMDGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK) |
AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt.
#define FLEXSPI_INTR_ECCMULTIERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCMULTIERR_SHIFT)) & FLEXSPI_INTR_ECCMULTIERR_MASK) |
ECCMULTIERR - ECC multi bits error interrupt.
#define FLEXSPI_INTR_ECCMULTIERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCMULTIERR_SHIFT)) & FLEXSPI_INTR_ECCMULTIERR_MASK) |
ECCMULTIERR - ECC multi bits error interrupt.
#define FLEXSPI_INTR_ECCSINGLEERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCSINGLEERR_SHIFT)) & FLEXSPI_INTR_ECCSINGLEERR_MASK) |
ECCSINGLEERR - ECC single bit error interrupt.
#define FLEXSPI_INTR_ECCSINGLEERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCSINGLEERR_SHIFT)) & FLEXSPI_INTR_ECCSINGLEERR_MASK) |
ECCSINGLEERR - ECC single bit error interrupt.
#define FLEXSPI_INTR_IPCMDDONE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) |
IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated.
#define FLEXSPI_INTR_IPCMDDONE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) |
IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated.
#define FLEXSPI_INTR_IPCMDDONE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK) |
IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also generated when there is IPCMDGE or IPCMDERR interrupt generated.
#define FLEXSPI_INTR_IPCMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) |
IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all.
#define FLEXSPI_INTR_IPCMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) |
IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all.
#define FLEXSPI_INTR_IPCMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK) |
IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for IP command, this command will be ignored and not executed at all.
#define FLEXSPI_INTR_IPCMDGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) |
IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt.
#define FLEXSPI_INTR_IPCMDGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) |
IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt.
#define FLEXSPI_INTR_IPCMDGE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK) |
IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt.
#define FLEXSPI_INTR_IPCMDSECUREVIO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK) |
IPCMDSECUREVIO - IP command security violation interrupt.
#define FLEXSPI_INTR_IPCMDSECUREVIO | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK) |
IPCMDSECUREVIO - IP command security violation interrupt.
#define FLEXSPI_INTR_IPRXWA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) |
IPRXWA - IP RX FIFO watermark available interrupt.
#define FLEXSPI_INTR_IPRXWA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) |
IPRXWA - IP RX FIFO watermark available interrupt.
#define FLEXSPI_INTR_IPRXWA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK) |
IPRXWA - IP RX FIFO watermark available interrupt.
#define FLEXSPI_INTR_IPTXWE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) |
IPTXWE - IP TX FIFO watermark empty interrupt.
#define FLEXSPI_INTR_IPTXWE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) |
IPTXWE - IP TX FIFO watermark empty interrupt.
#define FLEXSPI_INTR_IPTXWE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK) |
IPTXWE - IP TX FIFO watermark empty interrupt.
#define FLEXSPI_INTR_KEYDONE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK) |
KEYDONE - OTFAD key blob processing done interrupt.
#define FLEXSPI_INTR_KEYDONE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK) |
KEYDONE - OTFAD key blob processing done interrupt.
#define FLEXSPI_INTR_KEYERROR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK) |
KEYERROR - OTFAD key blob processing error interrupt.
#define FLEXSPI_INTR_KEYERROR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK) |
KEYERROR - OTFAD key blob processing error interrupt.
#define FLEXSPI_INTR_SCKSTOPBYRD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) |
SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt.
#define FLEXSPI_INTR_SCKSTOPBYRD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) |
SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt.
#define FLEXSPI_INTR_SCKSTOPBYRD | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK) |
SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt.
#define FLEXSPI_INTR_SCKSTOPBYWR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) |
SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt.
#define FLEXSPI_INTR_SCKSTOPBYWR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) |
SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt.
#define FLEXSPI_INTR_SCKSTOPBYWR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK) |
SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt.
#define FLEXSPI_INTR_SEQTIMEOUT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) |
SEQTIMEOUT - Sequence execution timeout interrupt.
#define FLEXSPI_INTR_SEQTIMEOUT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) |
SEQTIMEOUT - Sequence execution timeout interrupt.
#define FLEXSPI_INTR_SEQTIMEOUT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK) |
SEQTIMEOUT - Sequence execution timeout interrupt.
#define FLEXSPI_IPCMD_TRG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) |
TRG - Setting this bit will trigger an IP Command.
#define FLEXSPI_IPCMD_TRG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) |
TRG - Setting this bit will trigger an IP Command.
#define FLEXSPI_IPCMD_TRG | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK) |
TRG - Setting this bit will trigger an IP Command.
#define FLEXSPI_IPCR0_SFAR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) |
SFAR - Serial Flash Address for IP command.
#define FLEXSPI_IPCR0_SFAR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) |
SFAR - Serial Flash Address for IP command.
#define FLEXSPI_IPCR0_SFAR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK) |
SFAR - Serial Flash Address for IP command.
#define FLEXSPI_IPCR1_IDATSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) |
IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command.
#define FLEXSPI_IPCR1_IDATSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) |
IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command.
#define FLEXSPI_IPCR1_IDATSZ | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK) |
IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command.
#define FLEXSPI_IPCR1_IPAREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) |
IPAREN - Parallel mode Enabled for IP command. 0b0..Flash will be accessed in Individual mode. 0b1..Flash will be accessed in Parallel mode.
#define FLEXSPI_IPCR1_IPAREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) |
IPAREN - Parallel mode Enabled for IP command. 0b0..Flash will be accessed in Individual mode. 0b1..Flash will be accessed in Parallel mode.
#define FLEXSPI_IPCR1_IPAREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK) |
IPAREN - Parallel mode Enabled for IP command. 0b0..Flash will be accessed in Individual mode. 0b1..Flash will be accessed in Parallel mode.
#define FLEXSPI_IPCR1_ISEQID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) |
ISEQID - Sequence Index in LUT for IP command.
#define FLEXSPI_IPCR1_ISEQID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) |
ISEQID - Sequence Index in LUT for IP command.
#define FLEXSPI_IPCR1_ISEQID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK) |
ISEQID - Sequence Index in LUT for IP command.
#define FLEXSPI_IPCR1_ISEQNUM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) |
ISEQNUM - Sequence Number for IP command: ISEQNUM+1.
#define FLEXSPI_IPCR1_ISEQNUM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) |
ISEQNUM - Sequence Number for IP command: ISEQNUM+1.
#define FLEXSPI_IPCR1_ISEQNUM | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK) |
ISEQNUM - Sequence Number for IP command: ISEQNUM+1.
#define FLEXSPI_IPRXFCR_CLRIPRXF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) |
CLRIPRXF - Clear all valid data entries in IP RX FIFO.
#define FLEXSPI_IPRXFCR_CLRIPRXF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) |
CLRIPRXF - Clear all valid data entries in IP RX FIFO.
#define FLEXSPI_IPRXFCR_CLRIPRXF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK) |
CLRIPRXF - Clear all valid data entries in IP RX FIFO.
#define FLEXSPI_IPRXFCR_RXDMAEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) |
RXDMAEN - IP RX FIFO reading by DMA enabled. 0b0..IP RX FIFO would be read by processor. 0b1..IP RX FIFO would be read by DMA.
#define FLEXSPI_IPRXFCR_RXDMAEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) |
RXDMAEN - IP RX FIFO reading by DMA enabled. 0b0..IP RX FIFO would be read by processor. 0b1..IP RX FIFO would be read by DMA.
#define FLEXSPI_IPRXFCR_RXDMAEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK) |
RXDMAEN - IP RX FIFO reading by DMA enabled. 0b0..IP RX FIFO would be read by processor. 0b1..IP RX FIFO would be read by DMA.
#define FLEXSPI_IPRXFCR_RXWMRK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) |
RXWMRK - Watermark level is (RXWMRK+1)*64 Bits.
#define FLEXSPI_IPRXFCR_RXWMRK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) |
RXWMRK - Watermark level is (RXWMRK+1)*64 Bits.
#define FLEXSPI_IPRXFCR_RXWMRK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK) |
RXWMRK - Watermark level is (RXWMRK+1)*64 Bits.
#define FLEXSPI_IPRXFSTS_FILL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) |
FILL - Fill level of IP RX FIFO.
#define FLEXSPI_IPRXFSTS_FILL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) |
FILL - Fill level of IP RX FIFO.
#define FLEXSPI_IPRXFSTS_FILL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK) |
FILL - Fill level of IP RX FIFO.
#define FLEXSPI_IPRXFSTS_RDCNTR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) |
RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits.
#define FLEXSPI_IPRXFSTS_RDCNTR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) |
RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits.
#define FLEXSPI_IPRXFSTS_RDCNTR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK) |
RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits.
#define FLEXSPI_IPSNSZEND0_end_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND0_end_address_SHIFT)) & FLEXSPI_IPSNSZEND0_end_address_MASK) |
end_address - End address of region 0. Minimal 4K Bytes aligned. It is flash address.
#define FLEXSPI_IPSNSZEND0_end_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND0_end_address_SHIFT)) & FLEXSPI_IPSNSZEND0_end_address_MASK) |
end_address - End address of region 0. Minimal 4K Bytes aligned. It is flash address.
#define FLEXSPI_IPSNSZEND1_end_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND1_end_address_SHIFT)) & FLEXSPI_IPSNSZEND1_end_address_MASK) |
end_address - End address of region 1. Minimal 4K Bytes aligned. It is flash address.
#define FLEXSPI_IPSNSZEND1_end_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND1_end_address_SHIFT)) & FLEXSPI_IPSNSZEND1_end_address_MASK) |
end_address - End address of region 1. Minimal 4K Bytes aligned. It is flash address.
#define FLEXSPI_IPSNSZSTART0_start_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART0_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART0_start_address_MASK) |
start_address - Start address of region 0. Minimal 4K Bytes aligned. It is flash address.
#define FLEXSPI_IPSNSZSTART0_start_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART0_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART0_start_address_MASK) |
start_address - Start address of region 0. Minimal 4K Bytes aligned. It is flash address.
#define FLEXSPI_IPSNSZSTART1_start_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART1_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART1_start_address_MASK) |
start_address - Start address of region 1. Minimal 4K Bytes aligned. It is flash address.
#define FLEXSPI_IPSNSZSTART1_start_address | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART1_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART1_start_address_MASK) |
start_address - Start address of region 1. Minimal 4K Bytes aligned. It is flash address.
#define FLEXSPI_IPTXFCR_CLRIPTXF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) |
CLRIPTXF - Clear all valid data entries in IP TX FIFO.
#define FLEXSPI_IPTXFCR_CLRIPTXF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) |
CLRIPTXF - Clear all valid data entries in IP TX FIFO.
#define FLEXSPI_IPTXFCR_CLRIPTXF | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK) |
CLRIPTXF - Clear all valid data entries in IP TX FIFO.
#define FLEXSPI_IPTXFCR_TXDMAEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) |
TXDMAEN - IP TX FIFO filling by DMA enabled. 0b0..IP TX FIFO would be filled by processor. 0b1..IP TX FIFO would be filled by DMA.
#define FLEXSPI_IPTXFCR_TXDMAEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) |
TXDMAEN - IP TX FIFO filling by DMA enabled. 0b0..IP TX FIFO would be filled by processor. 0b1..IP TX FIFO would be filled by DMA.
#define FLEXSPI_IPTXFCR_TXDMAEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK) |
TXDMAEN - IP TX FIFO filling by DMA enabled. 0b0..IP TX FIFO would be filled by processor. 0b1..IP TX FIFO would be filled by DMA.
#define FLEXSPI_IPTXFCR_TXWMRK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) |
TXWMRK - Watermark level is (TXWMRK+1)*64 Bits.
#define FLEXSPI_IPTXFCR_TXWMRK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) |
TXWMRK - Watermark level is (TXWMRK+1)*64 Bits.
#define FLEXSPI_IPTXFCR_TXWMRK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK) |
TXWMRK - Watermark level is (TXWMRK+1)*64 Bits.
#define FLEXSPI_IPTXFSTS_FILL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) |
FILL - Fill level of IP TX FIFO.
#define FLEXSPI_IPTXFSTS_FILL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) |
FILL - Fill level of IP TX FIFO.
#define FLEXSPI_IPTXFSTS_FILL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK) |
FILL - Fill level of IP TX FIFO.
#define FLEXSPI_IPTXFSTS_WRCNTR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) |
WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits.
#define FLEXSPI_IPTXFSTS_WRCNTR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) |
WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits.
#define FLEXSPI_IPTXFSTS_WRCNTR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK) |
WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits.
#define FLEXSPI_LUT_NUM_PADS0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) |
NUM_PADS0 - NUM_PADS0
#define FLEXSPI_LUT_NUM_PADS0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) |
NUM_PADS0 - NUM_PADS0
#define FLEXSPI_LUT_NUM_PADS0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK) |
NUM_PADS0 - NUM_PADS0
#define FLEXSPI_LUT_NUM_PADS1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) |
NUM_PADS1 - NUM_PADS1
#define FLEXSPI_LUT_NUM_PADS1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) |
NUM_PADS1 - NUM_PADS1
#define FLEXSPI_LUT_NUM_PADS1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK) |
NUM_PADS1 - NUM_PADS1
#define FLEXSPI_LUT_OPCODE0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) |
OPCODE0 - OPCODE
#define FLEXSPI_LUT_OPCODE0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) |
OPCODE0 - OPCODE
#define FLEXSPI_LUT_OPCODE0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK) |
OPCODE0 - OPCODE
#define FLEXSPI_LUT_OPCODE1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) |
OPCODE1 - OPCODE1
#define FLEXSPI_LUT_OPCODE1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) |
OPCODE1 - OPCODE1
#define FLEXSPI_LUT_OPCODE1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK) |
OPCODE1 - OPCODE1
#define FLEXSPI_LUT_OPERAND0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) |
OPERAND0 - OPERAND0
#define FLEXSPI_LUT_OPERAND0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) |
OPERAND0 - OPERAND0
#define FLEXSPI_LUT_OPERAND0 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK) |
OPERAND0 - OPERAND0
#define FLEXSPI_LUT_OPERAND1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) |
OPERAND1 - OPERAND1
#define FLEXSPI_LUT_OPERAND1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) |
OPERAND1 - OPERAND1
#define FLEXSPI_LUT_OPERAND1 | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK) |
OPERAND1 - OPERAND1
#define FLEXSPI_LUTCR_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) |
LOCK - Lock LUT
#define FLEXSPI_LUTCR_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) |
LOCK - Lock LUT
#define FLEXSPI_LUTCR_LOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK) |
LOCK - Lock LUT
#define FLEXSPI_LUTCR_PROTECT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK) |
PROTECT - LUT protection
#define FLEXSPI_LUTCR_PROTECT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK) |
PROTECT - LUT protection
#define FLEXSPI_LUTCR_UNLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) |
UNLOCK - Unlock LUT
#define FLEXSPI_LUTCR_UNLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) |
UNLOCK - Unlock LUT
#define FLEXSPI_LUTCR_UNLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK) |
UNLOCK - Unlock LUT
#define FLEXSPI_LUTKEY_KEY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) |
KEY - The Key to lock or unlock LUT.
#define FLEXSPI_LUTKEY_KEY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) |
KEY - The Key to lock or unlock LUT.
#define FLEXSPI_LUTKEY_KEY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK) |
KEY - The Key to lock or unlock LUT.
#define FLEXSPI_MCR0_AHBGRANTWAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) |
AHBGRANTWAIT - Timeout wait cycle for AHB command grant.
#define FLEXSPI_MCR0_AHBGRANTWAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) |
AHBGRANTWAIT - Timeout wait cycle for AHB command grant.
#define FLEXSPI_MCR0_AHBGRANTWAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK) |
AHBGRANTWAIT - Timeout wait cycle for AHB command grant.
#define FLEXSPI_MCR0_ARDFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) |
ARDFEN - Enable AHB bus Read Access to IP RX FIFO. 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
#define FLEXSPI_MCR0_ARDFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) |
ARDFEN - Enable AHB bus Read Access to IP RX FIFO. 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
#define FLEXSPI_MCR0_ARDFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK) |
ARDFEN - Enable AHB bus Read Access to IP RX FIFO. 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response. 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
#define FLEXSPI_MCR0_ATDFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) |
ATDFEN - Enable AHB bus Write Access to IP TX FIFO. 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
#define FLEXSPI_MCR0_ATDFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) |
ATDFEN - Enable AHB bus Write Access to IP TX FIFO. 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
#define FLEXSPI_MCR0_ATDFEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK) |
ATDFEN - Enable AHB bus Write Access to IP TX FIFO. 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response. 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
#define FLEXSPI_MCR0_COMBINATIONEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) |
COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]). 0b0..Disable. 0b1..Enable.
#define FLEXSPI_MCR0_COMBINATIONEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) |
COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]), when Port A and Port B are of 4 bit data width. 0b0..Disable. 0b1..Enable.
#define FLEXSPI_MCR0_COMBINATIONEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK) |
COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data pins (A_DATA[3:0] and B_DATA[3:0]), when Port A and Port B are of 4 bit data width. 0b0..Disable. 0b1..Enable.
#define FLEXSPI_MCR0_DOZEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) |
DOZEEN - Doze mode enable bit 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
#define FLEXSPI_MCR0_DOZEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) |
DOZEEN - Doze mode enable bit 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
#define FLEXSPI_MCR0_DOZEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK) |
DOZEEN - Doze mode enable bit 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system. 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
#define FLEXSPI_MCR0_HSEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) |
HSEN - Half Speed Serial Flash access Enable. 0b0..Disable divide by 2 of serial flash clock for half speed commands. 0b1..Enable divide by 2 of serial flash clock for half speed commands.
#define FLEXSPI_MCR0_HSEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) |
HSEN - Half Speed Serial Flash access Enable. 0b0..Disable divide by 2 of serial flash clock for half speed commands. 0b1..Enable divide by 2 of serial flash clock for half speed commands.
#define FLEXSPI_MCR0_HSEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK) |
HSEN - Half Speed Serial Flash access Enable. 0b0..Disable divide by 2 of serial flash clock for half speed commands. 0b1..Enable divide by 2 of serial flash clock for half speed commands.
#define FLEXSPI_MCR0_IPGRANTWAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) |
IPGRANTWAIT - Time out wait cycle for IP command grant.
#define FLEXSPI_MCR0_IPGRANTWAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) |
IPGRANTWAIT - Time out wait cycle for IP command grant.
#define FLEXSPI_MCR0_IPGRANTWAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK) |
IPGRANTWAIT - Time out wait cycle for IP command grant.
#define FLEXSPI_MCR0_MDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) |
MDIS - Module Disable
#define FLEXSPI_MCR0_MDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) |
MDIS - Module Disable
#define FLEXSPI_MCR0_MDIS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK) |
MDIS - Module Disable
#define FLEXSPI_MCR0_RXCLKSRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) |
RXCLKSRC - Sample Clock source selection for Flash Reading 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. 0b10..Reserved 0b11..Flash provided Read strobe and input from DQS pad
#define FLEXSPI_MCR0_RXCLKSRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) |
RXCLKSRC - Sample Clock source selection for Flash Reading 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. 0b10..Reserved 0b11..Flash provided Read strobe and input from DQS pad
#define FLEXSPI_MCR0_RXCLKSRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK) |
RXCLKSRC - Sample Clock source selection for Flash Reading 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally. 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad. 0b10..Reserved 0b11..Flash provided Read strobe and input from DQS pad
#define FLEXSPI_MCR0_SCKFREERUNEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) |
SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications, external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2). 0b0..Disable. 0b1..Enable.
#define FLEXSPI_MCR0_SCKFREERUNEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) |
SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications, external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2). 0b0..Disable. 0b1..Enable.
#define FLEXSPI_MCR0_SCKFREERUNEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK) |
SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications, external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2). 0b0..Disable. 0b1..Enable.
#define FLEXSPI_MCR0_SERCLKDIV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) |
SERCLKDIV - The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking. 0b000..Divided by 1 0b001..Divided by 2 0b010..Divided by 3 0b011..Divided by 4 0b100..Divided by 5 0b101..Divided by 6 0b110..Divided by 7 0b111..Divided by 8
#define FLEXSPI_MCR0_SERCLKDIV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) |
SERCLKDIV - The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking. 0b000..Divided by 1 0b001..Divided by 2 0b010..Divided by 3 0b011..Divided by 4 0b100..Divided by 5 0b101..Divided by 6 0b110..Divided by 7 0b111..Divided by 8
#define FLEXSPI_MCR0_SERCLKDIV | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK) |
SERCLKDIV - The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking. 0b000..Divided by 1 0b001..Divided by 2 0b010..Divided by 3 0b011..Divided by 4 0b100..Divided by 5 0b101..Divided by 6 0b110..Divided by 7 0b111..Divided by 8
#define FLEXSPI_MCR0_SWRESET | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) |
SWRESET - Software Reset
#define FLEXSPI_MCR0_SWRESET | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) |
SWRESET - Software Reset
#define FLEXSPI_MCR0_SWRESET | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK) |
SWRESET - Software Reset
#define FLEXSPI_MCR2_CLRAHBBUFOPT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) |
CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
#define FLEXSPI_MCR2_CLRAHBBUFOPT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) |
CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
#define FLEXSPI_MCR2_CLRAHBBUFOPT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK) |
CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid. 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK. 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
#define FLEXSPI_MCR2_CLRLEARNPHASE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRLEARNPHASE_SHIFT)) & FLEXSPI_MCR2_CLRLEARNPHASE_MASK) |
CLRLEARNPHASE - The sampling clock phase selection will be reset to phase 0 when this bit is written with 0x1. This bit will be auto-cleared immediately.
#define FLEXSPI_MCR2_RESUMEWAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) |
RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.
#define FLEXSPI_MCR2_RESUMEWAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) |
RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.
#define FLEXSPI_MCR2_RESUMEWAIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK) |
RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.
#define FLEXSPI_MCR2_SAMEDEVICEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) |
SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored. 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
#define FLEXSPI_MCR2_SAMEDEVICEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) |
SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored. 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
#define FLEXSPI_MCR2_SAMEDEVICEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK) |
SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2. 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1, FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be ignored. 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
#define FLEXSPI_MCR2_SCKBDIFFOPT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) |
SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case, port B flash access is not available. After changing the value of this field, MCR0[SWRESET] should be set. 0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available. 0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
#define FLEXSPI_MCR2_SCKBDIFFOPT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) |
SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case, port B flash access is not available. After changing the value of this field, MCR0[SWRESET] should be set. 0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available. 0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
#define FLEXSPI_MCR2_SCKBDIFFOPT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK) |
SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to A_SCLK). In this case, port B flash access is not available. After changing the value of this field, MCR0[SWRESET] should be set. 0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available. 0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
#define FLEXSPI_MISCCR4_AHBADDRESS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR4_AHBADDRESS_SHIFT)) & FLEXSPI_MISCCR4_AHBADDRESS_MASK) |
AHBADDRESS - AHB bus address that trigger the current ECC multi bits error interrupt.
#define FLEXSPI_MISCCR4_AHBADDRESS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR4_AHBADDRESS_SHIFT)) & FLEXSPI_MISCCR4_AHBADDRESS_MASK) |
AHBADDRESS - AHB bus address that trigger the current ECC multi bits error interrupt.
#define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT)) & FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK) |
ECCSINGLEERRORCORR - ECC single bit error correction indication.
#define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT)) & FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK) |
ECCSINGLEERRORCORR - ECC single bit error correction indication.
#define FLEXSPI_MISCCR6_ADDRESS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_ADDRESS_SHIFT)) & FLEXSPI_MISCCR6_ADDRESS_MASK) |
ADDRESS - ECC single error address
#define FLEXSPI_MISCCR6_ADDRESS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_ADDRESS_SHIFT)) & FLEXSPI_MISCCR6_ADDRESS_MASK) |
ADDRESS - ECC single error address
#define FLEXSPI_MISCCR6_HIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_HIT_SHIFT)) & FLEXSPI_MISCCR6_HIT_MASK) |
HIT - ECC single error information Hit
#define FLEXSPI_MISCCR6_HIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_HIT_SHIFT)) & FLEXSPI_MISCCR6_HIT_MASK) |
HIT - ECC single error information Hit
#define FLEXSPI_MISCCR6_VALID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_VALID_SHIFT)) & FLEXSPI_MISCCR6_VALID_MASK) |
VALID - ECC single error information Valid
#define FLEXSPI_MISCCR6_VALID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_VALID_SHIFT)) & FLEXSPI_MISCCR6_VALID_MASK) |
VALID - ECC single error information Valid
#define FLEXSPI_MISCCR7_ADDRESS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_ADDRESS_SHIFT)) & FLEXSPI_MISCCR7_ADDRESS_MASK) |
ADDRESS - ECC multi error address
#define FLEXSPI_MISCCR7_ADDRESS | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_ADDRESS_SHIFT)) & FLEXSPI_MISCCR7_ADDRESS_MASK) |
ADDRESS - ECC multi error address
#define FLEXSPI_MISCCR7_HIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_HIT_SHIFT)) & FLEXSPI_MISCCR7_HIT_MASK) |
HIT - ECC multi error information Hit
#define FLEXSPI_MISCCR7_HIT | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_HIT_SHIFT)) & FLEXSPI_MISCCR7_HIT_MASK) |
HIT - ECC multi error information Hit
#define FLEXSPI_MISCCR7_VALID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_VALID_SHIFT)) & FLEXSPI_MISCCR7_VALID_MASK) |
VALID - ECC multi error information Valid
#define FLEXSPI_MISCCR7_VALID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_VALID_SHIFT)) & FLEXSPI_MISCCR7_VALID_MASK) |
VALID - ECC multi error information Valid
#define FLEXSPI_RFDR_RXDATA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) |
RXDATA - RX Data
#define FLEXSPI_RFDR_RXDATA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) |
RXDATA - RX Data
#define FLEXSPI_RFDR_RXDATA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK) |
RXDATA - RX Data
#define FLEXSPI_STS0_ARBCMDSRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) |
ARBCMDSRC - This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). 0b00..Triggered by AHB read command (triggered by AHB read). 0b01..Triggered by AHB write command (triggered by AHB Write). 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). 0b11..Triggered by suspended command (resumed).
#define FLEXSPI_STS0_ARBCMDSRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) |
ARBCMDSRC - This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). 0b00..Triggered by AHB read command (triggered by AHB read). 0b01..Triggered by AHB write command (triggered by AHB Write). 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). 0b11..Triggered by suspended command (resumed).
#define FLEXSPI_STS0_ARBCMDSRC | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK) |
ARBCMDSRC - This status field indicates the trigger source of current command sequence granted by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1). 0b00..Triggered by AHB read command (triggered by AHB read). 0b01..Triggered by AHB write command (triggered by AHB Write). 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG). 0b11..Triggered by suspended command (resumed).
#define FLEXSPI_STS0_ARBIDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) |
ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
#define FLEXSPI_STS0_ARBIDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) |
ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
#define FLEXSPI_STS0_ARBIDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK) |
ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
#define FLEXSPI_STS0_SEQIDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) |
SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface.
#define FLEXSPI_STS0_SEQIDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) |
SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface.
#define FLEXSPI_STS0_SEQIDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK) |
SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command sequence executing on FlexSPI interface.
#define FLEXSPI_STS1_AHBCMDERRCODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) |
AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). 0b0000..No error. 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. 0b0011..There is unknown instruction opcode in the sequence. 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. 0b1110..Sequence execution timeout.
#define FLEXSPI_STS1_AHBCMDERRCODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) |
AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). 0b0000..No error. 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. 0b0011..There is unknown instruction opcode in the sequence. 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. 0b1110..Sequence execution timeout.
#define FLEXSPI_STS1_AHBCMDERRCODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK) |
AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c). 0b0000..No error. 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence. 0b0011..There is unknown instruction opcode in the sequence. 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. 0b1110..Sequence execution timeout.
#define FLEXSPI_STS1_AHBCMDERRID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) |
AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
#define FLEXSPI_STS1_AHBCMDERRID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) |
AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
#define FLEXSPI_STS1_AHBCMDERRID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK) |
AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
#define FLEXSPI_STS1_IPCMDERRCODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) |
IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). 0b0000..No error. 0b0010..IP command with JMP_ON_CS instruction used in the sequence. 0b0011..There is unknown instruction opcode in the sequence. 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2). 0b1110..Sequence execution timeout. 0b1111..Flash boundary crossed.
#define FLEXSPI_STS1_IPCMDERRCODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) |
IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). 0b0000..No error. 0b0010..IP command with JMP_ON_CS instruction used in the sequence. 0b0011..There is unknown instruction opcode in the sequence. 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2). 0b1110..Sequence execution timeout. 0b1111..Flash boundary crossed.
#define FLEXSPI_STS1_IPCMDERRCODE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK) |
IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c). 0b0000..No error. 0b0010..IP command with JMP_ON_CS instruction used in the sequence. 0b0011..There is unknown instruction opcode in the sequence. 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence. 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence. 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2). 0b1110..Sequence execution timeout. 0b1111..Flash boundary crossed.
#define FLEXSPI_STS1_IPCMDERRID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) |
IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c).
#define FLEXSPI_STS1_IPCMDERRID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) |
IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c).
#define FLEXSPI_STS1_IPCMDERRID | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK) |
IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be cleared when INTR[IPCMDERR] is write-1-clear(w1c).
#define FLEXSPI_STS2_AREFLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) |
AREFLOCK - Flash A sample clock reference delay line locked.
#define FLEXSPI_STS2_AREFLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) |
AREFLOCK - Flash A sample clock reference delay line locked.
#define FLEXSPI_STS2_AREFLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK) |
AREFLOCK - Flash A sample clock reference delay line locked.
#define FLEXSPI_STS2_AREFSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) |
AREFSEL - Flash A sample clock reference delay line delay cell number selection.
#define FLEXSPI_STS2_AREFSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) |
AREFSEL - Flash A sample clock reference delay line delay cell number selection.
#define FLEXSPI_STS2_AREFSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK) |
AREFSEL - Flash A sample clock reference delay line delay cell number selection.
#define FLEXSPI_STS2_ASLVLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) |
ASLVLOCK - Flash A sample clock slave delay line locked.
#define FLEXSPI_STS2_ASLVLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) |
ASLVLOCK - Flash A sample clock slave delay line locked.
#define FLEXSPI_STS2_ASLVLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK) |
ASLVLOCK - Flash A sample clock slave delay line locked.
#define FLEXSPI_STS2_ASLVSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) |
ASLVSEL - Flash A sample clock slave delay line delay cell number selection .
#define FLEXSPI_STS2_ASLVSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) |
ASLVSEL - Flash A sample clock slave delay line delay cell number selection .
#define FLEXSPI_STS2_ASLVSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK) |
ASLVSEL - Flash A sample clock slave delay line delay cell number selection .
#define FLEXSPI_STS2_BREFLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) |
BREFLOCK - Flash B sample clock reference delay line locked.
#define FLEXSPI_STS2_BREFLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) |
BREFLOCK - Flash B sample clock reference delay line locked.
#define FLEXSPI_STS2_BREFLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK) |
BREFLOCK - Flash B sample clock reference delay line locked.
#define FLEXSPI_STS2_BREFSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) |
BREFSEL - Flash B sample clock reference delay line delay cell number selection.
#define FLEXSPI_STS2_BREFSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) |
BREFSEL - Flash B sample clock reference delay line delay cell number selection.
#define FLEXSPI_STS2_BREFSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK) |
BREFSEL - Flash B sample clock reference delay line delay cell number selection.
#define FLEXSPI_STS2_BSLVLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) |
BSLVLOCK - Flash B sample clock slave delay line locked.
#define FLEXSPI_STS2_BSLVLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) |
BSLVLOCK - Flash B sample clock slave delay line locked.
#define FLEXSPI_STS2_BSLVLOCK | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK) |
BSLVLOCK - Flash B sample clock slave delay line locked.
#define FLEXSPI_STS2_BSLVSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) |
BSLVSEL - Flash B sample clock slave delay line delay cell number selection.
#define FLEXSPI_STS2_BSLVSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) |
BSLVSEL - Flash B sample clock slave delay line delay cell number selection.
#define FLEXSPI_STS2_BSLVSEL | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK) |
BSLVSEL - Flash B sample clock slave delay line delay cell number selection.
#define FLEXSPI_TFDR_TXDATA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) |
TXDATA - TX Data
#define FLEXSPI_TFDR_TXDATA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) |
TXDATA - TX Data
#define FLEXSPI_TFDR_TXDATA | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK) |
TXDATA - TX Data
#define PWM_INTEN_CA0IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) |
CA0IE - Capture A 0 Interrupt Enable 0b0..Interrupt request disabled for STS[CFA0]. 0b1..Interrupt request enabled for STS[CFA0].
#define PWM_INTEN_CA0IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) |
CA0IE - Capture A 0 Interrupt Enable 0b0..Interrupt request disabled for STS[CFA0]. 0b1..Interrupt request enabled for STS[CFA0].
#define PWM_INTEN_CA0IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK) |
CA0IE - Capture A 0 Interrupt Enable 0b0..Interrupt request disabled for STS[CFA0]. 0b1..Interrupt request enabled for STS[CFA0].
#define PWM_INTEN_CA1IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) |
CA1IE - Capture A 1 Interrupt Enable 0b0..Interrupt request disabled for STS[CFA1]. 0b1..Interrupt request enabled for STS[CFA1].
#define PWM_INTEN_CA1IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) |
CA1IE - Capture A 1 Interrupt Enable 0b0..Interrupt request disabled for STS[CFA1]. 0b1..Interrupt request enabled for STS[CFA1].
#define PWM_INTEN_CA1IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK) |
CA1IE - Capture A 1 Interrupt Enable 0b0..Interrupt request disabled for STS[CFA1]. 0b1..Interrupt request enabled for STS[CFA1].
#define PWM_INTEN_CB0IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) |
CB0IE - Capture B 0 Interrupt Enable 0b0..Interrupt request disabled for STS[CFB0]. 0b1..Interrupt request enabled for STS[CFB0].
#define PWM_INTEN_CB0IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) |
CB0IE - Capture B 0 Interrupt Enable 0b0..Interrupt request disabled for STS[CFB0]. 0b1..Interrupt request enabled for STS[CFB0].
#define PWM_INTEN_CB0IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK) |
CB0IE - Capture B 0 Interrupt Enable 0b0..Interrupt request disabled for STS[CFB0]. 0b1..Interrupt request enabled for STS[CFB0].
#define PWM_INTEN_CB1IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) |
CB1IE - Capture B 1 Interrupt Enable 0b0..Interrupt request disabled for STS[CFB1]. 0b1..Interrupt request enabled for STS[CFB1].
#define PWM_INTEN_CB1IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) |
CB1IE - Capture B 1 Interrupt Enable 0b0..Interrupt request disabled for STS[CFB1]. 0b1..Interrupt request enabled for STS[CFB1].
#define PWM_INTEN_CB1IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK) |
CB1IE - Capture B 1 Interrupt Enable 0b0..Interrupt request disabled for STS[CFB1]. 0b1..Interrupt request enabled for STS[CFB1].
#define PWM_INTEN_CMPIE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) |
CMPIE - Compare Interrupt Enables 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
#define PWM_INTEN_CMPIE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) |
CMPIE - Compare Interrupt Enables 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
#define PWM_INTEN_CMPIE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK) |
CMPIE - Compare Interrupt Enables 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request. 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
#define PWM_INTEN_CX0IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) |
CX0IE - Capture X 0 Interrupt Enable 0b0..Interrupt request disabled for STS[CFX0]. 0b1..Interrupt request enabled for STS[CFX0].
#define PWM_INTEN_CX0IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) |
CX0IE - Capture X 0 Interrupt Enable 0b0..Interrupt request disabled for STS[CFX0]. 0b1..Interrupt request enabled for STS[CFX0].
#define PWM_INTEN_CX0IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK) |
CX0IE - Capture X 0 Interrupt Enable 0b0..Interrupt request disabled for STS[CFX0]. 0b1..Interrupt request enabled for STS[CFX0].
#define PWM_INTEN_CX1IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) |
CX1IE - Capture X 1 Interrupt Enable 0b0..Interrupt request disabled for STS[CFX1]. 0b1..Interrupt request enabled for STS[CFX1].
#define PWM_INTEN_CX1IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) |
CX1IE - Capture X 1 Interrupt Enable 0b0..Interrupt request disabled for STS[CFX1]. 0b1..Interrupt request enabled for STS[CFX1].
#define PWM_INTEN_CX1IE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK) |
CX1IE - Capture X 1 Interrupt Enable 0b0..Interrupt request disabled for STS[CFX1]. 0b1..Interrupt request enabled for STS[CFX1].
#define PWM_INTEN_REIE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) |
REIE - Reload Error Interrupt Enable 0b0..STS[REF] CPU interrupt requests disabled 0b1..STS[REF] CPU interrupt requests enabled
#define PWM_INTEN_REIE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) |
REIE - Reload Error Interrupt Enable 0b0..STS[REF] CPU interrupt requests disabled 0b1..STS[REF] CPU interrupt requests enabled
#define PWM_INTEN_REIE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK) |
REIE - Reload Error Interrupt Enable 0b0..STS[REF] CPU interrupt requests disabled 0b1..STS[REF] CPU interrupt requests enabled
#define PWM_INTEN_RIE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) |
RIE - Reload Interrupt Enable 0b0..STS[RF] CPU interrupt requests disabled 0b1..STS[RF] CPU interrupt requests enabled
#define PWM_INTEN_RIE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) |
RIE - Reload Interrupt Enable 0b0..STS[RF] CPU interrupt requests disabled 0b1..STS[RF] CPU interrupt requests enabled
#define PWM_INTEN_RIE | ( | x | ) | (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK) |
RIE - Reload Interrupt Enable 0b0..STS[RF] CPU interrupt requests disabled 0b1..STS[RF] CPU interrupt requests enabled
#define SEMC_INTEN_AXIBUSERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) |
AXIBUSERREN - AXI bus error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_AXIBUSERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) |
AXIBUSERREN - AXI bus error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_AXIBUSERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK) |
AXIBUSERREN - AXI bus error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_AXICMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) |
AXICMDERREN - AXI command error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_AXICMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) |
AXICMDERREN - AXI command error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_AXICMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK) |
AXICMDERREN - AXI command error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_IPCMDDONEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) |
IPCMDDONEEN - IP command done interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_IPCMDDONEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) |
IPCMDDONEEN - IP command done interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_IPCMDDONEEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK) |
IPCMDDONEEN - IP command done interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_IPCMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) |
IPCMDERREN - IP command error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_IPCMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) |
IPCMDERREN - IP command error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_IPCMDERREN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK) |
IPCMDERREN - IP command error interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_NDNOPENDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) |
NDNOPENDEN - NAND no pending AXI access interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_NDNOPENDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) |
NDNOPENDEN - NAND no pending AXI access interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_NDNOPENDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK) |
NDNOPENDEN - NAND no pending AXI access interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_NDPAGEENDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) |
NDPAGEENDEN - NAND page end interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_NDPAGEENDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) |
NDPAGEENDEN - NAND page end interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTEN_NDPAGEENDEN | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK) |
NDPAGEENDEN - NAND page end interrupt enable 0b0..Interrupt is disabled 0b1..Interrupt is enabled
#define SEMC_INTR_AXIBUSERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) |
AXIBUSERR - AXI bus error interrupt 0b0..No AXI bus error. 0b1..AXI bus error occurs.
#define SEMC_INTR_AXIBUSERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK) |
AXIBUSERR - AXI bus error interrupt 0b0..No AXI bus error. 0b1..AXI bus error occurs.
#define SEMC_INTR_AXICMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) |
AXICMDERR - AXI command error interrupt 0b0..No AXI command error. 0b1..AXI command error occurs.
#define SEMC_INTR_AXICMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK) |
AXICMDERR - AXI command error interrupt 0b0..No AXI command error. 0b1..AXI command error occurs.
#define SEMC_INTR_IPCMDDONE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) |
IPCMDDONE - IP command normal done interrupt 0b0..IP command is not done. 0b1..IP command is done.
#define SEMC_INTR_IPCMDDONE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK) |
IPCMDDONE - IP command normal done interrupt 0b0..IP command is not done. 0b1..IP command is done.
#define SEMC_INTR_IPCMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) |
IPCMDERR - IP command error done interrupt 0b0..No IP command error. 0b1..IP command error occurs.
#define SEMC_INTR_IPCMDERR | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK) |
IPCMDERR - IP command error done interrupt 0b0..No IP command error. 0b1..IP command error occurs.
#define SEMC_INTR_NDNOPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) |
NDNOPEND - NAND no pending AXI write transaction interrupt 0b0..At least one NAND AXI write transaction is pending or no NAND write transaction is sent to the queue. 0b1..All NAND AXI write pending transactions are finished.
#define SEMC_INTR_NDNOPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK) |
NDNOPEND - NAND no pending AXI write transaction interrupt 0b0..At least one NAND AXI write transaction is pending or no NAND write transaction is sent to the queue. 0b1..All NAND AXI write pending transactions are finished.
#define SEMC_INTR_NDPAGEEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) |
NDPAGEEND - NAND page end interrupt 0b0..The last address of main space in the NAND is not written by AXI command. 0b1..The last address of main space in the NAND is written by AXI command.
#define SEMC_INTR_NDPAGEEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK) |
NDPAGEEND - NAND page end interrupt 0b0..The last address of main space in the NAND is not written by AXI command. 0b1..The last address of main space in the NAND is written by AXI command.
#define SEMC_IPCMD_KEY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK) |
KEY - This field should be written with 0xA55A when trigging an IP command.
#define SEMC_STS0_IDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) |
IDLE - Indicating whether SEMC is in IDLE state.
#define SEMC_STS0_IDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) |
IDLE - Indicating whether the SEMC is in idle state.
#define SEMC_STS0_IDLE | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK) |
IDLE - Indicating whether the SEMC is in idle state.
#define SEMC_STS0_NARDY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) |
NARDY - Indicating NAND device Ready/WAIT# pin level. 0b0..NAND device is not ready 0b1..NAND device is ready
#define SEMC_STS0_NARDY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) |
NARDY - Indicating NAND device Ready/WAIT# pin level. 0b0..NAND device is not ready 0b1..NAND device is ready
#define SEMC_STS0_NARDY | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK) |
NARDY - Indicating NAND device Ready/WAIT# pin level. 0b0..NAND device is not ready 0b1..NAND device is ready
#define SEMC_STS2_NDWRPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) |
NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device. 0b0..No pending 0b1..Pending
#define SEMC_STS2_NDWRPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) |
NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device. 0b0..No pending 0b1..Pending
#define SEMC_STS2_NDWRPEND | ( | x | ) | (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK) |
NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device. 0b0..No pending 0b1..Pending