RTEMS 6.1-rc5
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Modules | |
FLEXSPI Register Masks | |
Data Structures | |
struct | FLEXSPI_Type |
Macros | |
#define | FLEXSPI_BASE (0x402A8000u) |
#define | FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) |
#define | FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } |
#define | FLEXSPI_BASE_PTRS { FLEXSPI } |
#define | FLEXSPI_IRQS { FLEXSPI_IRQn } |
#define | FlexSPI_AMBA_BASE (0x60000000U) |
#define | FlexSPI_ASFM_BASE (0x00000000U) |
#define | FlexSPI_ARDF_BASE (0x7FC00000U) |
#define | FlexSPI_ATDF_BASE (0x7F800000U) |
#define | FLEXSPI1_BASE (0x400CC000u) |
#define | FLEXSPI1 ((FLEXSPI_Type *)FLEXSPI1_BASE) |
#define | FLEXSPI2_BASE (0x400D0000u) |
#define | FLEXSPI2 ((FLEXSPI_Type *)FLEXSPI2_BASE) |
#define | FLEXSPI_BASE_ADDRS { 0u, FLEXSPI1_BASE, FLEXSPI2_BASE } |
#define | FLEXSPI_BASE_PTRS { (FLEXSPI_Type *)0u, FLEXSPI1, FLEXSPI2 } |
#define | FLEXSPI_IRQS { NotAvail_IRQn, FLEXSPI1_IRQn, FLEXSPI2_IRQn } |
#define | FlexSPI1_AMBA_BASE (0x30000000U) |
#define | FlexSPI1_ASFM_BASE (0x30000000U) |
#define | FlexSPI1_ARDF_BASE (0x2FC00000U) |
#define | FlexSPI1_ATDF_BASE (0x2F800000U) |
#define | FlexSPI1_ALIAS_BASE (0x8000000U) |
#define | FlexSPI2_AMBA_BASE (0x60000000U) |
#define | FlexSPI2_ASFM_BASE (0x60000000U) |
#define | FlexSPI2_ARDF_BASE (0x7FC00000U) |
#define | FlexSPI2_ATDF_BASE (0x7F800000U) |
#define | FLEXSPI1_BASE (0x400CC000u) |
#define | FLEXSPI1 ((FLEXSPI_Type *)FLEXSPI1_BASE) |
#define | FLEXSPI2_BASE (0x400D0000u) |
#define | FLEXSPI2 ((FLEXSPI_Type *)FLEXSPI2_BASE) |
#define | FLEXSPI_BASE_ADDRS { 0u, FLEXSPI1_BASE, FLEXSPI2_BASE } |
#define | FLEXSPI_BASE_PTRS { (FLEXSPI_Type *)0u, FLEXSPI1, FLEXSPI2 } |
#define | FLEXSPI_IRQS { NotAvail_IRQn, FLEXSPI1_IRQn, FLEXSPI2_IRQn } |
#define | FlexSPI1_AMBA_BASE (0x30000000U) |
#define | FlexSPI1_ASFM_BASE (0x30000000U) |
#define | FlexSPI1_ARDF_BASE (0x2FC00000U) |
#define | FlexSPI1_ATDF_BASE (0x2F800000U) |
#define | FlexSPI1_ALIAS_BASE (0x8000000U) |
#define | FlexSPI2_AMBA_BASE (0x60000000U) |
#define | FlexSPI2_ASFM_BASE (0x60000000U) |
#define | FlexSPI2_ARDF_BASE (0x7FC00000U) |
#define | FlexSPI2_ATDF_BASE (0x7F800000U) |
#define FLEXSPI ((FLEXSPI_Type *)FLEXSPI_BASE) |
Peripheral FLEXSPI base pointer
#define FLEXSPI1 ((FLEXSPI_Type *)FLEXSPI1_BASE) |
Peripheral FLEXSPI1 base pointer
#define FLEXSPI1 ((FLEXSPI_Type *)FLEXSPI1_BASE) |
Peripheral FLEXSPI1 base pointer
#define FLEXSPI1_BASE (0x400CC000u) |
Peripheral FLEXSPI1 base address
#define FLEXSPI1_BASE (0x400CC000u) |
Peripheral FLEXSPI1 base address
#define FLEXSPI2 ((FLEXSPI_Type *)FLEXSPI2_BASE) |
Peripheral FLEXSPI2 base pointer
#define FLEXSPI2 ((FLEXSPI_Type *)FLEXSPI2_BASE) |
Peripheral FLEXSPI2 base pointer
#define FLEXSPI2_BASE (0x400D0000u) |
Peripheral FLEXSPI2 base address
#define FLEXSPI2_BASE (0x400D0000u) |
Peripheral FLEXSPI2 base address
#define FLEXSPI_BASE (0x402A8000u) |
Peripheral FLEXSPI base address
#define FLEXSPI_BASE_ADDRS { FLEXSPI_BASE } |
Array initializer of FLEXSPI peripheral base addresses
#define FLEXSPI_BASE_ADDRS { 0u, FLEXSPI1_BASE, FLEXSPI2_BASE } |
Array initializer of FLEXSPI peripheral base addresses
#define FLEXSPI_BASE_ADDRS { 0u, FLEXSPI1_BASE, FLEXSPI2_BASE } |
Array initializer of FLEXSPI peripheral base addresses
#define FLEXSPI_BASE_PTRS { FLEXSPI } |
Array initializer of FLEXSPI peripheral base pointers
#define FLEXSPI_BASE_PTRS { (FLEXSPI_Type *)0u, FLEXSPI1, FLEXSPI2 } |
Array initializer of FLEXSPI peripheral base pointers
#define FLEXSPI_BASE_PTRS { (FLEXSPI_Type *)0u, FLEXSPI1, FLEXSPI2 } |
Array initializer of FLEXSPI peripheral base pointers
#define FLEXSPI_IRQS { FLEXSPI_IRQn } |
Interrupt vectors for the FLEXSPI peripheral type
#define FLEXSPI_IRQS { NotAvail_IRQn, FLEXSPI1_IRQn, FLEXSPI2_IRQn } |
Interrupt vectors for the FLEXSPI peripheral type
#define FLEXSPI_IRQS { NotAvail_IRQn, FLEXSPI1_IRQn, FLEXSPI2_IRQn } |
Interrupt vectors for the FLEXSPI peripheral type