|
#define | TMS570_SCI_GCR0_Reserved(val) BSP_FLD32(val,1, 31) |
|
#define | TMS570_SCI_GCR0_Reserved_GET(reg) BSP_FLD32GET(reg,1, 31) |
|
#define | TMS570_SCI_GCR0_Reserved_SET(reg, val) BSP_FLD32SET(reg, val,1, 31) |
|
#define | TMS570_SCI_GCR0_RESET BSP_BIT32(0) |
|
#define | TMS570_SCI_GCR1_TXENA BSP_BIT32(25) |
|
#define | TMS570_SCI_GCR1_RXENA BSP_BIT32(24) |
|
#define | TMS570_SCI_GCR1_CONT BSP_BIT32(17) |
|
#define | TMS570_SCI_GCR1_LOOP_BACK BSP_BIT32(16) |
|
#define | TMS570_SCI_GCR1_POWERDOWN BSP_BIT32(9) |
|
#define | TMS570_SCI_GCR1_SLEEP BSP_BIT32(8) |
|
#define | TMS570_SCI_GCR1_SWnRST BSP_BIT32(7) |
|
#define | TMS570_SCI_GCR1_CLOCK BSP_BIT32(5) |
|
#define | TMS570_SCI_GCR1_STOP BSP_BIT32(4) |
|
#define | TMS570_SCI_GCR1_PARITY BSP_BIT32(3) |
|
#define | TMS570_SCI_GCR1_PARITY_ENA BSP_BIT32(2) |
|
#define | TMS570_SCI_GCR1_TIMING_MODE BSP_BIT32(1) |
|
#define | TMS570_SCI_GCR1_COMM_MODE BSP_BIT32(0) |
|
#define | TMS570_SCI_GCR2_CC BSP_BIT32(17) |
|
#define | TMS570_SCI_GCR2_SC BSP_BIT32(16) |
|
#define | TMS570_SCI_GCR2_GEN_WU BSP_BIT32(8) |
|
#define | TMS570_SCI_GCR2_POWERDOWN BSP_BIT32(0) |
|
#define | TMS570_SCI_SETINT_SET_FE_INT BSP_BIT32(26) |
|
#define | TMS570_SCI_SETINT_SET_OE_INT BSP_BIT32(25) |
|
#define | TMS570_SCI_SETINT_SET_PE_INT BSP_BIT32(24) |
|
#define | TMS570_SCI_SETINT_SET_RX_DMA_ALL BSP_BIT32(18) |
|
#define | TMS570_SCI_SETINT_SET_RX_DMA BSP_BIT32(17) |
|
#define | TMS570_SCI_SETINT_SET_TX_DMA BSP_BIT32(16) |
|
#define | TMS570_SCI_SETINT_SET_RX_INT BSP_BIT32(9) |
|
#define | TMS570_SCI_SETINT_SET_TX_INT BSP_BIT32(8) |
|
#define | TMS570_SCI_SETINT_SET_WAKEUP_INT BSP_BIT32(1) |
|
#define | TMS570_SCI_SETINT_SET_BRKDT_INT BSP_BIT32(0) |
|
#define | TMS570_SCI_CLEARINT_CLR_FE_INT BSP_BIT32(26) |
|
#define | TMS570_SCI_CLEARINT_CLR_CE_INT BSP_BIT32(25) |
|
#define | TMS570_SCI_CLEARINT_CLR_PE_INT BSP_BIT32(24) |
|
#define | TMS570_SCI_CLEARINT_CLR_RX_DMA_ALL BSP_BIT32(18) |
|
#define | TMS570_SCI_CLEARINT_CLR_RX_DMA BSP_BIT32(17) |
|
#define | TMS570_SCI_CLEARINT_CLR_TX_DMA BSP_BIT32(16) |
|
#define | TMS570_SCI_CLEARINT_CLR_RX_INT BSP_BIT32(9) |
|
#define | TMS570_SCI_CLEARINT_CLR_TX_INT BSP_BIT32(8) |
|
#define | TMS570_SCI_CLEARINT_CLR_WAKEUP_INT BSP_BIT32(1) |
|
#define | TMS570_SCI_CLEARINT_CLR_BRKDT_INT BSP_BIT32(0) |
|
#define | TMS570_SCI_SETINTLVL_SET_FE_INT_LVL BSP_BIT32(26) |
|
#define | TMS570_SCI_SETINTLVL_SET_CE_INT_LVL BSP_BIT32(25) |
|
#define | TMS570_SCI_SETINTLVL_SET_PE_INT_LVL BSP_BIT32(24) |
|
#define | TMS570_SCI_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_BIT32(18) |
|
#define | TMS570_SCI_SETINTLVL_SET_RX_INT_LVL BSP_BIT32(9) |
|
#define | TMS570_SCI_SETINTLVL_SET_TX_INT_LVL BSP_BIT32(8) |
|
#define | TMS570_SCI_SETINTLVL_SET_WAKEUP_INT_LVL BSP_BIT32(1) |
|
#define | TMS570_SCI_SETINTLVL_SET_BRKDT_INT_LVL BSP_BIT32(0) |
|
#define | TMS570_SCI_CLEARINTLVL_CLR_FE_INT_LVL BSP_BIT32(26) |
|
#define | TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25) |
|
#define | TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25) |
|
#define | TMS570_SCI_CLEARINTLVL_CLR_PE_INT_LVL BSP_BIT32(24) |
|
#define | TMS570_SCI_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_BIT32(18) |
|
#define | TMS570_SCI_CLEARINTLVL_CLR_RX_INT_LVL BSP_BIT32(9) |
|
#define | TMS570_SCI_CLEARINTLVL_8 BSP_BIT32(8) |
|
#define | TMS570_SCI_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_BIT32(1) |
|
#define | TMS570_SCI_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_BIT32(0) |
|
#define | TMS570_SCI_FLR_FE BSP_BIT32(26) |
|
#define | TMS570_SCI_FLR_OE BSP_BIT32(25) |
|
#define | TMS570_SCI_FLR_PE BSP_BIT32(24) |
|
#define | TMS570_SCI_FLR_RXWAKE BSP_BIT32(12) |
|
#define | TMS570_SCI_FLR_TX_EMPTY BSP_BIT32(11) |
|
#define | TMS570_SCI_FLR_TXWAKE BSP_BIT32(10) |
|
#define | TMS570_SCI_FLR_RXRDY BSP_BIT32(9) |
|
#define | TMS570_SCI_FLR_TXRDY BSP_BIT32(8) |
|
#define | TMS570_SCI_FLR_BUSY BSP_BIT32(3) |
|
#define | TMS570_SCI_FLR_IDLE BSP_BIT32(2) |
|
#define | TMS570_SCI_FLR_WAKEUP BSP_BIT32(1) |
|
#define | TMS570_SCI_FLR_BRKDT BSP_BIT32(0) |
|
#define | TMS570_SCI_INTVECT0_INVECT0(val) BSP_FLD32(val,0, 3) |
|
#define | TMS570_SCI_INTVECT0_INVECT0_GET(reg) BSP_FLD32GET(reg,0, 3) |
|
#define | TMS570_SCI_INTVECT0_INVECT0_SET(reg, val) BSP_FLD32SET(reg, val,0, 3) |
|
#define | TMS570_SCI_INTVECT1_INVECT1(val) BSP_FLD32(val,0, 3) |
|
#define | TMS570_SCI_INTVECT1_INVECT1_GET(reg) BSP_FLD32GET(reg,0, 3) |
|
#define | TMS570_SCI_INTVECT1_INVECT1_SET(reg, val) BSP_FLD32SET(reg, val,0, 3) |
|
#define | TMS570_SCI_FORMAT_CHAR(val) BSP_FLD32(val,0, 2) |
|
#define | TMS570_SCI_FORMAT_CHAR_GET(reg) BSP_FLD32GET(reg,0, 2) |
|
#define | TMS570_SCI_FORMAT_CHAR_SET(reg, val) BSP_FLD32SET(reg, val,0, 2) |
|
#define | TMS570_SCI_BRS_BAUD(val) BSP_FLD32(val,0, 23) |
|
#define | TMS570_SCI_BRS_BAUD_GET(reg) BSP_FLD32GET(reg,0, 23) |
|
#define | TMS570_SCI_BRS_BAUD_SET(reg, val) BSP_FLD32SET(reg, val,0, 23) |
|
#define | TMS570_SCI_ED_ED(val) BSP_FLD32(val,0, 7) |
|
#define | TMS570_SCI_ED_ED_GET(reg) BSP_FLD32GET(reg,0, 7) |
|
#define | TMS570_SCI_ED_ED_SET(reg, val) BSP_FLD32SET(reg, val,0, 7) |
|
#define | TMS570_SCI_RD_RD(val) BSP_FLD32(val,0, 7) |
|
#define | TMS570_SCI_RD_RD_GET(reg) BSP_FLD32GET(reg,0, 7) |
|
#define | TMS570_SCI_RD_RD_SET(reg, val) BSP_FLD32SET(reg, val,0, 7) |
|
#define | TMS570_SCI_TD_TD(val) BSP_FLD32(val,0, 7) |
|
#define | TMS570_SCI_TD_TD_GET(reg) BSP_FLD32GET(reg,0, 7) |
|
#define | TMS570_SCI_TD_TD_SET(reg, val) BSP_FLD32SET(reg, val,0, 7) |
|
#define | TMS570_SCI_PIO0_TX_FUNC BSP_BIT32(2) |
|
#define | TMS570_SCI_PIO0_RX_FUNC BSP_BIT32(1) |
|
#define | TMS570_SCI_PIO1_TX_DIR BSP_BIT32(2) |
|
#define | TMS570_SCI_PIO1_RX_DIR BSP_BIT32(1) |
|
#define | TMS570_SCI_PIO2_TX_IN BSP_BIT32(2) |
|
#define | TMS570_SCI_PIO2_RX_IN BSP_BIT32(1) |
|
#define | TMS570_SCI_PIO3_TX_OUT BSP_BIT32(2) |
|
#define | TMS570_SCI_PIO3_RX_OUT BSP_BIT32(1) |
|
#define | TMS570_SCI_PIO4_TX_SET BSP_BIT32(2) |
|
#define | TMS570_SCI_PIO4_RX_SET BSP_BIT32(1) |
|
#define | TMS570_SCI_PIO5_TX_CLR BSP_BIT32(2) |
|
#define | TMS570_SCI_PIO5_RX_CLR BSP_BIT32(1) |
|
#define | TMS570_SCI_PIO6_TX_PDR BSP_BIT32(2) |
|
#define | TMS570_SCI_PIO6_RX_PDR BSP_BIT32(1) |
|
#define | TMS570_SCI_PIO7_TX_PD BSP_BIT32(2) |
|
#define | TMS570_SCI_PIO7_RX_PD BSP_BIT32(1) |
|
#define | TMS570_SCI_PIO8_TX_PSL BSP_BIT32(2) |
|
#define | TMS570_SCI_PIO8_RX_PSL BSP_BIT32(1) |
|
#define | TMS570_SCI_IODFTCTRL_FEN BSP_BIT32(26) |
|
#define | TMS570_SCI_IODFTCTRL_PEN BSP_BIT32(25) |
|
#define | TMS570_SCI_IODFTCTRL_BRKD_TENA BSP_BIT32(24) |
|
#define | TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK(val) BSP_FLD32(val,19, 20) |
|
#define | TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_GET(reg) BSP_FLD32GET(reg,19, 20) |
|
#define | TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_SET(reg, val) BSP_FLD32SET(reg, val,19, 20) |
|
#define | TMS570_SCI_IODFTCTRL_TX_SHIFT(val) BSP_FLD32(val,16, 18) |
|
#define | TMS570_SCI_IODFTCTRL_TX_SHIFT_GET(reg) BSP_FLD32GET(reg,16, 18) |
|
#define | TMS570_SCI_IODFTCTRL_TX_SHIFT_SET(reg, val) BSP_FLD32SET(reg, val,16, 18) |
|
#define | TMS570_SCI_IODFTCTRL_IODFTENA(val) BSP_FLD32(val,8, 11) |
|
#define | TMS570_SCI_IODFTCTRL_IODFTENA_GET(reg) BSP_FLD32GET(reg,8, 11) |
|
#define | TMS570_SCI_IODFTCTRL_IODFTENA_SET(reg, val) BSP_FLD32SET(reg, val,8, 11) |
|
#define | TMS570_SCI_IODFTCTRL_LPBENA BSP_BIT32(1) |
|
#define | TMS570_SCI_IODFTCTRL_RXPENA BSP_BIT32(0) |
|