RTEMS
6.1-rc4
Loading...
Searching...
No Matches
bsps
arm
tms570
include
bsp
ti_herc
reg_sci.h
Go to the documentation of this file.
1
/* SPDX-License-Identifier: BSD-2-Clause */
2
11
/* The header file is generated by make_header.py from SCI.json */
12
/* Current script's version can be found at: */
13
/* https://github.com/AoLaD/rtems-tms570-utils/tree/headers/headers/python */
14
15
/*
16
* Copyright (c) 2014-2015, Premysl Houdek <kom541000@gmail.com>
17
*
18
* Czech Technical University in Prague
19
* Zikova 1903/4
20
* 166 36 Praha 6
21
* Czech Republic
22
*
23
* All rights reserved.
24
*
25
* Redistribution and use in source and binary forms, with or without
26
* modification, are permitted provided that the following conditions are met:
27
*
28
* 1. Redistributions of source code must retain the above copyright notice, this
29
* list of conditions and the following disclaimer.
30
* 2. Redistributions in binary form must reproduce the above copyright notice,
31
* this list of conditions and the following disclaimer in the documentation
32
* and/or other materials provided with the distribution.
33
*
34
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
35
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
36
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
37
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
38
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
39
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
40
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
41
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
42
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
43
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
44
*
45
* The views and conclusions contained in the software and documentation are those
46
* of the authors and should not be interpreted as representing official policies,
47
* either expressed or implied, of the FreeBSD Project.
48
*/
49
#ifndef LIBBSP_ARM_TMS570_SCI
50
#define LIBBSP_ARM_TMS570_SCI
51
52
#include <
bsp/utility.h
>
53
54
typedef
struct
{
55
uint32_t GCR0;
/*SCI Global Control Register 0*/
56
uint32_t GCR1;
/*SCI Global Control Register 1*/
57
uint32_t GCR2;
/*SCI Global Control Register 2*/
58
uint32_t SETINT;
/*SCI Set Interrupt Register*/
59
uint32_t CLEARINT;
/*SCI Clear Interrupt Register*/
60
uint32_t SETINTLVL;
/*SCI Set Interrupt Level Register*/
61
uint32_t CLEARINTLVL;
/*SCI Clear Interrupt Level Register*/
62
uint32_t FLR;
/*SCI Flags Register*/
63
uint32_t INTVECT0;
/*SCI Interrupt Vector Offset 0*/
64
uint32_t INTVECT1;
/*SCI Interrupt Vector Offset 1*/
65
uint32_t FORMAT;
/*SCI Format Control Register*/
66
uint32_t BRS;
/*Baud Rate Selection Register*/
67
uint32_t ED;
/*Receiver Emulation Data Buffer*/
68
uint32_t RD;
/*Receiver Data Buffer*/
69
uint32_t TD;
/*Transmit Data Buffer*/
70
uint32_t PIO0;
/*SCI Pin I/O Control Register 0*/
71
uint32_t PIO1;
/*SCI Pin I/O Control Register 1*/
72
uint32_t PIO2;
/*SCI Pin I/O Control Register 2*/
73
uint32_t PIO3;
/*SCI Pin I/O Control Register 3*/
74
uint32_t PIO4;
/*SCI Pin I/O Control Register 4*/
75
uint32_t PIO5;
/*SCI Pin I/O Control Register 5*/
76
uint32_t PIO6;
/*SCI Pin I/O Control Register 6*/
77
uint32_t PIO7;
/*SCI Pin I/O Control Register 7*/
78
uint32_t PIO8;
/*SCI Pin I/O Control Register 8*/
79
uint8_t reserved1 [48];
80
uint32_t IODFTCTRL;
/*Input/Output Error Enable Register*/
81
}
tms570_sci_t
;
82
83
84
/*----------------------TMS570_SCI_GCR0----------------------*/
85
/* field: Reserved - Read returns 0. Writes have no effect. */
86
#define TMS570_SCI_GCR0_Reserved(val) BSP_FLD32(val,1, 31)
87
#define TMS570_SCI_GCR0_Reserved_GET(reg) BSP_FLD32GET(reg,1, 31)
88
#define TMS570_SCI_GCR0_Reserved_SET(reg,val) BSP_FLD32SET(reg, val,1, 31)
89
90
/* field: RESET - This bit resets the SCI module. */
91
#define TMS570_SCI_GCR0_RESET BSP_BIT32(0)
92
93
94
/*----------------------TMS570_SCI_GCR1----------------------*/
95
/* field: TXENA - Transmit enable. */
96
#define TMS570_SCI_GCR1_TXENA BSP_BIT32(25)
97
98
/* field: RXENA - Receive enable. RXENA allows or prevents the transfer of data from SCIRXSHF to SCIRD. */
99
#define TMS570_SCI_GCR1_RXENA BSP_BIT32(24)
100
101
/* field: CONT - Continue on suspend. */
102
#define TMS570_SCI_GCR1_CONT BSP_BIT32(17)
103
104
/* field: LOOP_BACK - Loopback bit. The self-checking option for the SCI can be selected with this bit. */
105
#define TMS570_SCI_GCR1_LOOP_BACK BSP_BIT32(16)
106
107
/* field: POWERDOWN - If the POWERDOWN bit is set while the receiver is actively receiving data and the wake-up */
108
#define TMS570_SCI_GCR1_POWERDOWN BSP_BIT32(9)
109
110
/* field: SLEEP - SCI sleep. In a multiprocessor configuration, this bit controls the receive sleep function. */
111
#define TMS570_SCI_GCR1_SLEEP BSP_BIT32(8)
112
113
/* field: SWnRST - Software reset (active low). This bit is effective in LIN and SCI modes. */
114
#define TMS570_SCI_GCR1_SWnRST BSP_BIT32(7)
115
116
/* field: CLOCK - CLOCK */
117
#define TMS570_SCI_GCR1_CLOCK BSP_BIT32(5)
118
119
/* field: STOP - SCI number of stop bits per frame. */
120
#define TMS570_SCI_GCR1_STOP BSP_BIT32(4)
121
122
/* field: PARITY - SCI parity odd/even selection. If the PARITY ENA bit is set, PARITY designates odd or even parity. */
123
#define TMS570_SCI_GCR1_PARITY BSP_BIT32(3)
124
125
/* field: PARITY_ENA - Parity enable. This bit enables or disables the parity function. */
126
#define TMS570_SCI_GCR1_PARITY_ENA BSP_BIT32(2)
127
128
/* field: TIMING_MODE - SCI timing mode bit. */
129
#define TMS570_SCI_GCR1_TIMING_MODE BSP_BIT32(1)
130
131
/* field: COMM_MODE - SCI communication mode bit. */
132
#define TMS570_SCI_GCR1_COMM_MODE BSP_BIT32(0)
133
134
135
/*----------------------TMS570_SCI_GCR2----------------------*/
136
/* field: CC - Compare checksum. LIN mode only. */
137
#define TMS570_SCI_GCR2_CC BSP_BIT32(17)
138
139
/* field: SC - Send checksum byte. This bit is effective in LIN mode only. */
140
#define TMS570_SCI_GCR2_SC BSP_BIT32(16)
141
142
/* field: GEN_WU - Generate wakeup signal. This bit is effective in LIN mode only. */
143
#define TMS570_SCI_GCR2_GEN_WU BSP_BIT32(8)
144
145
/* field: POWERDOWN - Power down. This bit is effective in LIN or SCI mode. */
146
#define TMS570_SCI_GCR2_POWERDOWN BSP_BIT32(0)
147
148
149
/*---------------------TMS570_SCI_SETINT---------------------*/
150
/* field: SET_FE_INT - */
151
#define TMS570_SCI_SETINT_SET_FE_INT BSP_BIT32(26)
152
153
/* field: SET_OE_INT - SET OE INT */
154
#define TMS570_SCI_SETINT_SET_OE_INT BSP_BIT32(25)
155
156
/* field: SET_PE_INT - Set parity interrupt. */
157
#define TMS570_SCI_SETINT_SET_PE_INT BSP_BIT32(24)
158
159
/* field: SET_RX_DMA_ALL - SET RX DMA ALL */
160
#define TMS570_SCI_SETINT_SET_RX_DMA_ALL BSP_BIT32(18)
161
162
/* field: SET_RX_DMA - SET RX DMA */
163
#define TMS570_SCI_SETINT_SET_RX_DMA BSP_BIT32(17)
164
165
/* field: SET_TX_DMA - Set transmit DMA. To enable DMA requests for the transmitter, this bit must be set. */
166
#define TMS570_SCI_SETINT_SET_TX_DMA BSP_BIT32(16)
167
168
/* field: SET_RX_INT - SET RX INT */
169
#define TMS570_SCI_SETINT_SET_RX_INT BSP_BIT32(9)
170
171
/* field: SET_TX_INT - Set transmitter interrupt. */
172
#define TMS570_SCI_SETINT_SET_TX_INT BSP_BIT32(8)
173
174
/* field: SET_WAKEUP_INT - Set wakeup interrupt. */
175
#define TMS570_SCI_SETINT_SET_WAKEUP_INT BSP_BIT32(1)
176
177
/* field: SET_BRKDT_INT - Set breakdetect interrupt. */
178
#define TMS570_SCI_SETINT_SET_BRKDT_INT BSP_BIT32(0)
179
180
181
/*--------------------TMS570_SCI_CLEARINT--------------------*/
182
/* field: CLR_FE_INT - Clear framing-error interrupt. This bit disables the framing-error interrupt when set. */
183
#define TMS570_SCI_CLEARINT_CLR_FE_INT BSP_BIT32(26)
184
185
/* field: CLR_CE_INT - Clear overrun-error interrupt. This bit disables the SCI overrun error interrupt when set. */
186
#define TMS570_SCI_CLEARINT_CLR_CE_INT BSP_BIT32(25)
187
188
/* field: CLR_PE_INT - Clear parity interrupt. This bit disables the parity error interrupt when set. */
189
#define TMS570_SCI_CLEARINT_CLR_PE_INT BSP_BIT32(24)
190
191
/* field: CLR_RX_DMA_ALL - Clear receive DMA all. This bit clears the receive DMA request for address frames when set. */
192
#define TMS570_SCI_CLEARINT_CLR_RX_DMA_ALL BSP_BIT32(18)
193
194
/* field: CLR_RX_DMA - Clear receive DMA request. This bit disables the receive DMA request when set. */
195
#define TMS570_SCI_CLEARINT_CLR_RX_DMA BSP_BIT32(17)
196
197
/* field: CLR_TX_DMA - CLR TX DMA */
198
#define TMS570_SCI_CLEARINT_CLR_TX_DMA BSP_BIT32(16)
199
200
/* field: CLR_RX_INT - Clear receiver interrupt. This bit disables the receiver interrupt when set. */
201
#define TMS570_SCI_CLEARINT_CLR_RX_INT BSP_BIT32(9)
202
203
/* field: CLR_TX_INT - Clear transmitter interrupt. This bit disables the transmitter interrupt when set. */
204
#define TMS570_SCI_CLEARINT_CLR_TX_INT BSP_BIT32(8)
205
206
/* field: CLR_WAKEUP_INT - Clear wakeup interrupt. This bit disables the wakeup interrupt when set. */
207
#define TMS570_SCI_CLEARINT_CLR_WAKEUP_INT BSP_BIT32(1)
208
209
/* field: CLR_BRKDT_INT - Clear breakdetect interrupt. This bit disables the break-detect interrupt when set. */
210
#define TMS570_SCI_CLEARINT_CLR_BRKDT_INT BSP_BIT32(0)
211
212
213
/*--------------------TMS570_SCI_SETINTLVL--------------------*/
214
/* field: SET_FE_INT_LVL - Set framing-error interrupt level. */
215
#define TMS570_SCI_SETINTLVL_SET_FE_INT_LVL BSP_BIT32(26)
216
217
/* field: SET_CE_INT_LVL - Set overrun-error interrupt level. */
218
#define TMS570_SCI_SETINTLVL_SET_CE_INT_LVL BSP_BIT32(25)
219
220
/* field: SET_PE_INT_LVL - Set parity error interrupt level. */
221
#define TMS570_SCI_SETINTLVL_SET_PE_INT_LVL BSP_BIT32(24)
222
223
/* field: SET_RX_DMA_ALL_LVL - Set receive DMA all interrupt levels. */
224
#define TMS570_SCI_SETINTLVL_SET_RX_DMA_ALL_LVL BSP_BIT32(18)
225
226
/* field: SET_RX_INT_LVL - Set receiver interrupt level. */
227
#define TMS570_SCI_SETINTLVL_SET_RX_INT_LVL BSP_BIT32(9)
228
229
/* field: SET_TX_INT_LVL - Set transmitter interrupt level. */
230
#define TMS570_SCI_SETINTLVL_SET_TX_INT_LVL BSP_BIT32(8)
231
232
/* field: SET_WAKEUP_INT_LVL - Set wakeup interrupt level. */
233
#define TMS570_SCI_SETINTLVL_SET_WAKEUP_INT_LVL BSP_BIT32(1)
234
235
/* field: SET_BRKDT_INT_LVL - SET BRKDT INT LVL */
236
#define TMS570_SCI_SETINTLVL_SET_BRKDT_INT_LVL BSP_BIT32(0)
237
238
239
/*-------------------TMS570_SCI_CLEARINTLVL-------------------*/
240
/* field: CLR_FE_INT_LVL - Clear framing-error interrupt. */
241
#define TMS570_SCI_CLEARINTLVL_CLR_FE_INT_LVL BSP_BIT32(26)
242
243
/* field: CLR_CE_INT_LVL - CLR CE INT LVL */
244
#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25)
245
246
/* field: CLR_CE_INT_LVL - CLR CE INT LVL */
247
#define TMS570_SCI_CLEARINTLVL_CLR_CE_INT_LVL BSP_BIT32(25)
248
249
/* field: CLR_PE_INT_LVL - */
250
#define TMS570_SCI_CLEARINTLVL_CLR_PE_INT_LVL BSP_BIT32(24)
251
252
/* field: CLR_RX_DMA_ALL_LVL - Clear receive DMA interrupt level. */
253
#define TMS570_SCI_CLEARINTLVL_CLR_RX_DMA_ALL_LVL BSP_BIT32(18)
254
255
/* field: CLR_RX_INT_LVL - Clear receiver interrupt. */
256
#define TMS570_SCI_CLEARINTLVL_CLR_RX_INT_LVL BSP_BIT32(9)
257
258
/* field: 8 - CLR TX INT LVL Clear transmitter interrupt. */
259
#define TMS570_SCI_CLEARINTLVL_8 BSP_BIT32(8)
260
261
/* field: CLR_WAKEUP_INT_LVL - Clear wakeup interrupt. */
262
#define TMS570_SCI_CLEARINTLVL_CLR_WAKEUP_INT_LVL BSP_BIT32(1)
263
264
/* field: CLR_BRKDT_INT_LVL - Clear breakdetect interrupt. */
265
#define TMS570_SCI_CLEARINTLVL_CLR_BRKDT_INT_LVL BSP_BIT32(0)
266
267
268
/*-----------------------TMS570_SCI_FLR-----------------------*/
269
/* field: FE - Framing error flag. This bit is effective in LIN or SCI-compatible mode. */
270
#define TMS570_SCI_FLR_FE BSP_BIT32(26)
271
272
/* field: OE - Overrun error flag. */
273
#define TMS570_SCI_FLR_OE BSP_BIT32(25)
274
275
/* field: PE - Parity error flag. This bit is set when a parity error is detected in the received data. */
276
#define TMS570_SCI_FLR_PE BSP_BIT32(24)
277
278
/* field: RXWAKE - Receiver wakeup detect flag. */
279
#define TMS570_SCI_FLR_RXWAKE BSP_BIT32(12)
280
281
/* field: TX_EMPTY - Transmitter empty flag. */
282
#define TMS570_SCI_FLR_TX_EMPTY BSP_BIT32(11)
283
284
/* field: TXWAKE - Transmitter wakeup method select. */
285
#define TMS570_SCI_FLR_TXWAKE BSP_BIT32(10)
286
287
/* field: RXRDY - Receiver ready flag. */
288
#define TMS570_SCI_FLR_RXRDY BSP_BIT32(9)
289
290
/* field: TXRDY - Transmitter buffer register ready flag. */
291
#define TMS570_SCI_FLR_TXRDY BSP_BIT32(8)
292
293
/* field: BUSY - Bus busy flag. TThis bit indicates whether the receiver is in the process of receiving a frame. */
294
#define TMS570_SCI_FLR_BUSY BSP_BIT32(3)
295
296
/* field: IDLE - SCI receiver in idle state. */
297
#define TMS570_SCI_FLR_IDLE BSP_BIT32(2)
298
299
/* field: WAKEUP - Wakeup flag. */
300
#define TMS570_SCI_FLR_WAKEUP BSP_BIT32(1)
301
302
/* field: BRKDT - SCI break-detect flag. This bit is set when the SCI detects a break condition on the LINRX pin. */
303
#define TMS570_SCI_FLR_BRKDT BSP_BIT32(0)
304
305
306
/*--------------------TMS570_SCI_INTVECT0--------------------*/
307
/* field: INVECT0 - Interrupt vector offset for INT0. This register indicates the offset for interrupt line INT0. */
308
#define TMS570_SCI_INTVECT0_INVECT0(val) BSP_FLD32(val,0, 3)
309
#define TMS570_SCI_INTVECT0_INVECT0_GET(reg) BSP_FLD32GET(reg,0, 3)
310
#define TMS570_SCI_INTVECT0_INVECT0_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
311
312
313
/*--------------------TMS570_SCI_INTVECT1--------------------*/
314
/* field: INVECT1 - Interrupt vector offset for INT1. This register indicates the offset for interrupt line INT1. */
315
#define TMS570_SCI_INTVECT1_INVECT1(val) BSP_FLD32(val,0, 3)
316
#define TMS570_SCI_INTVECT1_INVECT1_GET(reg) BSP_FLD32GET(reg,0, 3)
317
#define TMS570_SCI_INTVECT1_INVECT1_SET(reg,val) BSP_FLD32SET(reg, val,0, 3)
318
319
320
/*---------------------TMS570_SCI_FORMAT---------------------*/
321
/* field: CHAR - Character length control bits. These bits set the SCI character length from 1 to 8 bits. */
322
#define TMS570_SCI_FORMAT_CHAR(val) BSP_FLD32(val,0, 2)
323
#define TMS570_SCI_FORMAT_CHAR_GET(reg) BSP_FLD32GET(reg,0, 2)
324
#define TMS570_SCI_FORMAT_CHAR_SET(reg,val) BSP_FLD32SET(reg, val,0, 2)
325
326
327
/*-----------------------TMS570_SCI_BRS-----------------------*/
328
/* field: BAUD - SCI 24-bit baud selection. */
329
#define TMS570_SCI_BRS_BAUD(val) BSP_FLD32(val,0, 23)
330
#define TMS570_SCI_BRS_BAUD_GET(reg) BSP_FLD32GET(reg,0, 23)
331
#define TMS570_SCI_BRS_BAUD_SET(reg,val) BSP_FLD32SET(reg, val,0, 23)
332
333
334
/*-----------------------TMS570_SCI_ED-----------------------*/
335
/* field: ED - Emulator data. Reading SCIED[7:0] does not clear the RXRDY flag, unlike reading SCIRD. */
336
#define TMS570_SCI_ED_ED(val) BSP_FLD32(val,0, 7)
337
#define TMS570_SCI_ED_ED_GET(reg) BSP_FLD32GET(reg,0, 7)
338
#define TMS570_SCI_ED_ED_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
339
340
341
/*-----------------------TMS570_SCI_RD-----------------------*/
342
/* field: RD - Receiver data. */
343
#define TMS570_SCI_RD_RD(val) BSP_FLD32(val,0, 7)
344
#define TMS570_SCI_RD_RD_GET(reg) BSP_FLD32GET(reg,0, 7)
345
#define TMS570_SCI_RD_RD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
346
347
348
/*-----------------------TMS570_SCI_TD-----------------------*/
349
/* field: TD - Transmit data. Data to be transmitted is written to the SCITD register. */
350
#define TMS570_SCI_TD_TD(val) BSP_FLD32(val,0, 7)
351
#define TMS570_SCI_TD_TD_GET(reg) BSP_FLD32GET(reg,0, 7)
352
#define TMS570_SCI_TD_TD_SET(reg,val) BSP_FLD32SET(reg, val,0, 7)
353
354
355
/*----------------------TMS570_SCI_PIO0----------------------*/
356
/* field: TX_FUNC - Transfer function. This bit defines the function of pin SCITX. */
357
#define TMS570_SCI_PIO0_TX_FUNC BSP_BIT32(2)
358
359
/* field: RX_FUNC - Receive function.This bit defines the function of pin SCIRX. */
360
#define TMS570_SCI_PIO0_RX_FUNC BSP_BIT32(1)
361
362
363
/*----------------------TMS570_SCI_PIO1----------------------*/
364
/* field: TX_DIR - Transmit pin direction. */
365
#define TMS570_SCI_PIO1_TX_DIR BSP_BIT32(2)
366
367
/* field: RX_DIR - Receive pin direction. */
368
#define TMS570_SCI_PIO1_RX_DIR BSP_BIT32(1)
369
370
371
/*----------------------TMS570_SCI_PIO2----------------------*/
372
/* field: TX_IN - Transmit pin in. This bit contains the current value on the SCITX pin. */
373
#define TMS570_SCI_PIO2_TX_IN BSP_BIT32(2)
374
375
/* field: RX_IN - Receive pin in. This bit contains the current value on the SCIRX pin. */
376
#define TMS570_SCI_PIO2_RX_IN BSP_BIT32(1)
377
378
379
/*----------------------TMS570_SCI_PIO3----------------------*/
380
/* field: TX_OUT - Transmit pin out. */
381
#define TMS570_SCI_PIO3_TX_OUT BSP_BIT32(2)
382
383
/* field: RX_OUT - Receive pin out. */
384
#define TMS570_SCI_PIO3_RX_OUT BSP_BIT32(1)
385
386
387
/*----------------------TMS570_SCI_PIO4----------------------*/
388
/* field: TX_SET - Transmit pin set. */
389
#define TMS570_SCI_PIO4_TX_SET BSP_BIT32(2)
390
391
/* field: RX_SET - Receive pin set. */
392
#define TMS570_SCI_PIO4_RX_SET BSP_BIT32(1)
393
394
395
/*----------------------TMS570_SCI_PIO5----------------------*/
396
/* field: TX_CLR - Transmit pin clear. */
397
#define TMS570_SCI_PIO5_TX_CLR BSP_BIT32(2)
398
399
/* field: RX_CLR - Receive pin clear. */
400
#define TMS570_SCI_PIO5_RX_CLR BSP_BIT32(1)
401
402
403
/*----------------------TMS570_SCI_PIO6----------------------*/
404
/* field: TX_PDR - Transmit pin open drain enable. */
405
#define TMS570_SCI_PIO6_TX_PDR BSP_BIT32(2)
406
407
/* field: RX_PDR - Receive pin open drain enable. */
408
#define TMS570_SCI_PIO6_RX_PDR BSP_BIT32(1)
409
410
411
/*----------------------TMS570_SCI_PIO7----------------------*/
412
/* field: TX_PD - Transmit pin pull control disable. This bit disables pull control capability on the input pin SCITX. */
413
#define TMS570_SCI_PIO7_TX_PD BSP_BIT32(2)
414
415
/* field: RX_PD - Receive pin pull control disable. This bit disables pull control capability on the input pin SCIRX. */
416
#define TMS570_SCI_PIO7_RX_PD BSP_BIT32(1)
417
418
419
/*----------------------TMS570_SCI_PIO8----------------------*/
420
/* field: TX_PSL - TX pin pull select. This bit selects pull type in the input pin SCITX. */
421
#define TMS570_SCI_PIO8_TX_PSL BSP_BIT32(2)
422
423
/* field: RX_PSL - RX pin pull select. This bit selects pull type in the input pin SCIRX. */
424
#define TMS570_SCI_PIO8_RX_PSL BSP_BIT32(1)
425
426
427
/*--------------------TMS570_SCI_IODFTCTRL--------------------*/
428
/* field: FEN - Frame error enable. This bit is used to create a frame error. */
429
#define TMS570_SCI_IODFTCTRL_FEN BSP_BIT32(26)
430
431
/* field: PEN - Parity error enable. This bit is used to create a parity error. */
432
#define TMS570_SCI_IODFTCTRL_PEN BSP_BIT32(25)
433
434
/* field: BRKD_TENA - Break detect error enable. This bit is used to create a BRKDT error. */
435
#define TMS570_SCI_IODFTCTRL_BRKD_TENA BSP_BIT32(24)
436
437
/* field: PIN_SAMPLE_MASK - Pin sample mask. */
438
#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK(val) BSP_FLD32(val,19, 20)
439
#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_GET(reg) BSP_FLD32GET(reg,19, 20)
440
#define TMS570_SCI_IODFTCTRL_PIN_SAMPLE_MASK_SET(reg,val) BSP_FLD32SET(reg, val,19, 20)
441
442
/* field: TX_SHIFT - Transmit shift. */
443
#define TMS570_SCI_IODFTCTRL_TX_SHIFT(val) BSP_FLD32(val,16, 18)
444
#define TMS570_SCI_IODFTCTRL_TX_SHIFT_GET(reg) BSP_FLD32GET(reg,16, 18)
445
#define TMS570_SCI_IODFTCTRL_TX_SHIFT_SET(reg,val) BSP_FLD32SET(reg, val,16, 18)
446
447
/* field: IODFTENA - IODFT enable key. Write access permitted in Privilege mode only. */
448
#define TMS570_SCI_IODFTCTRL_IODFTENA(val) BSP_FLD32(val,8, 11)
449
#define TMS570_SCI_IODFTCTRL_IODFTENA_GET(reg) BSP_FLD32GET(reg,8, 11)
450
#define TMS570_SCI_IODFTCTRL_IODFTENA_SET(reg,val) BSP_FLD32SET(reg, val,8, 11)
451
452
/* field: LPBENA - Module loopback enable. Write access permitted in Privilege mode only. */
453
#define TMS570_SCI_IODFTCTRL_LPBENA BSP_BIT32(1)
454
455
/* field: RXPENA - Module analog loopback through receive pin enable. */
456
#define TMS570_SCI_IODFTCTRL_RXPENA BSP_BIT32(0)
457
458
459
460
#endif
/* LIBBSP_ARM_TMS570_SCI */
utility.h
This header file provides utility macros for BSPs.
tms570_sci_t
Definition:
reg_sci.h:54
Generated by
1.9.6
1.9.6