RTEMS 6.1-rc4
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Macros

Macros

#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)
 
#define IS_TIM_DMA_BASE(__BASE__)
 
#define IS_TIM_EVENT_SOURCE(__SOURCE__)   ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
 
#define IS_TIM_COUNTER_MODE(__MODE__)
 
#define IS_TIM_UIFREMAP_MODE(__MODE__)
 
#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)
 
#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD)
 
#define IS_TIM_FAST_STATE(__STATE__)
 
#define IS_TIM_OC_POLARITY(__POLARITY__)
 
#define IS_TIM_OCN_POLARITY(__POLARITY__)
 
#define IS_TIM_OCIDLE_STATE(__STATE__)
 
#define IS_TIM_OCNIDLE_STATE(__STATE__)
 
#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)
 
#define IS_TIM_IC_POLARITY(__POLARITY__)
 
#define IS_TIM_IC_SELECTION(__SELECTION__)
 
#define IS_TIM_IC_PRESCALER(__PRESCALER__)
 
#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__)
 
#define IS_TIM_OPM_MODE(__MODE__)
 
#define IS_TIM_ENCODER_MODE(__MODE__)
 
#define IS_TIM_DMA_SOURCE(__SOURCE__)   ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
 
#define IS_TIM_CHANNELS(__CHANNEL__)
 
#define IS_TIM_OPM_CHANNELS(__CHANNEL__)
 
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__)
 
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__)
 
#define IS_TIM_CLOCKSOURCE(__CLOCK__)
 
#define IS_TIM_CLOCKPOLARITY(__POLARITY__)
 
#define IS_TIM_CLOCKPRESCALER(__PRESCALER__)
 
#define IS_TIM_CLOCKFILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
 
#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__)
 
#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__)
 
#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
 
#define IS_TIM_OSSR_STATE(__STATE__)
 
#define IS_TIM_OSSI_STATE(__STATE__)
 
#define IS_TIM_LOCK_LEVEL(__LEVEL__)
 
#define IS_TIM_BREAK_FILTER(__BRKFILTER__)   ((__BRKFILTER__) <= 0xFUL)
 
#define IS_TIM_BREAK_STATE(__STATE__)
 
#define IS_TIM_BREAK_POLARITY(__POLARITY__)
 
#define IS_TIM_BREAK2_STATE(__STATE__)
 
#define IS_TIM_BREAK2_POLARITY(__POLARITY__)
 
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__)
 
#define IS_TIM_GROUPCH5(__OCREF__)   ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))
 
#define IS_TIM_TRGO_SOURCE(__SOURCE__)
 
#define IS_TIM_TRGO2_SOURCE(__SOURCE__)
 
#define IS_TIM_MSM_STATE(__STATE__)
 
#define IS_TIM_SLAVE_MODE(__MODE__)
 
#define IS_TIM_PWM_MODE(__MODE__)
 
#define IS_TIM_OC_MODE(__MODE__)
 
#define IS_TIM_TRIGGER_SELECTION(__SELECTION__)
 
#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__)
 
#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)
 
#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__)
 
#define IS_TIM_TRIGGERFILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
 
#define IS_TIM_TI1SELECTION(__TI1SELECTION__)
 
#define IS_TIM_DMA_LENGTH(__LENGTH__)
 
#define IS_TIM_DMA_DATA_LENGTH(LENGTH)   (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))
 
#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)
 
#define IS_TIM_DEADTIME(__DEADTIME__)   ((__DEADTIME__) <= 0xFFU)
 
#define IS_TIM_BREAK_SYSTEM(__CONFIG__)
 
#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__)
 
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__)
 
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__)
 
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)
 
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__)
 
#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)
 
#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__)
 
#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)
 
#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)
 
#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__)
 
#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)
 

Detailed Description

Macro Definition Documentation

◆ IS_TIM_AUTOMATIC_OUTPUT_STATE

#define IS_TIM_AUTOMATIC_OUTPUT_STATE (   __STATE__)
Value:
(((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
#define TIM_AUTOMATICOUTPUT_ENABLE
Definition: stm32h7xx_hal_tim.h:994
#define TIM_AUTOMATICOUTPUT_DISABLE
Definition: stm32h7xx_hal_tim.h:993

◆ IS_TIM_AUTORELOAD_PRELOAD

#define IS_TIM_AUTORELOAD_PRELOAD (   PRELOAD)
Value:
(((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
#define TIM_AUTORELOAD_PRELOAD_DISABLE
Definition: stm32h7xx_hal_tim.h:602
#define TIM_AUTORELOAD_PRELOAD_ENABLE
Definition: stm32h7xx_hal_tim.h:603

◆ IS_TIM_BREAK2_POLARITY

#define IS_TIM_BREAK2_POLARITY (   __POLARITY__)
Value:
(((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \
((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))
#define TIM_BREAK2POLARITY_HIGH
Definition: stm32h7xx_hal_tim.h:972
#define TIM_BREAK2POLARITY_LOW
Definition: stm32h7xx_hal_tim.h:971

◆ IS_TIM_BREAK2_STATE

#define IS_TIM_BREAK2_STATE (   __STATE__)
Value:
(((__STATE__) == TIM_BREAK2_ENABLE) || \
((__STATE__) == TIM_BREAK2_DISABLE))
#define TIM_BREAK2_DISABLE
Definition: stm32h7xx_hal_tim.h:961
#define TIM_BREAK2_ENABLE
Definition: stm32h7xx_hal_tim.h:962

◆ IS_TIM_BREAK_POLARITY

#define IS_TIM_BREAK_POLARITY (   __POLARITY__)
Value:
(((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
#define TIM_BREAKPOLARITY_LOW
Definition: stm32h7xx_hal_tim.h:939
#define TIM_BREAKPOLARITY_HIGH
Definition: stm32h7xx_hal_tim.h:940

◆ IS_TIM_BREAK_STATE

#define IS_TIM_BREAK_STATE (   __STATE__)
Value:
(((__STATE__) == TIM_BREAK_ENABLE) || \
((__STATE__) == TIM_BREAK_DISABLE))
#define TIM_BREAK_ENABLE
Definition: stm32h7xx_hal_tim.h:929
#define TIM_BREAK_DISABLE
Definition: stm32h7xx_hal_tim.h:930

◆ IS_TIM_BREAK_SYSTEM

#define IS_TIM_BREAK_SYSTEM (   __CONFIG__)
Value:
(((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \
((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \
((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \
((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))
#define TIM_BREAK_SYSTEM_ECC
Definition: stm32h7xx_hal_tim.h:1216
#define TIM_BREAK_SYSTEM_PVD
Definition: stm32h7xx_hal_tim.h:1217
#define TIM_BREAK_SYSTEM_LOCKUP
Definition: stm32h7xx_hal_tim.h:1219
#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR
Definition: stm32h7xx_hal_tim.h:1218

◆ IS_TIM_CCX_CHANNEL

#define IS_TIM_CCX_CHANNEL (   __INSTANCE__,
  __CHANNEL__ 
)
Value:
(IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
((__CHANNEL__) != (TIM_CHANNEL_5)) && \
((__CHANNEL__) != (TIM_CHANNEL_6)))
#define TIM_CHANNEL_5
Definition: stm32h7xx_hal_tim.h:817
#define TIM_CHANNEL_6
Definition: stm32h7xx_hal_tim.h:818

◆ IS_TIM_CHANNELS

#define IS_TIM_CHANNELS (   __CHANNEL__)
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
((__CHANNEL__) == TIM_CHANNEL_3) || \
((__CHANNEL__) == TIM_CHANNEL_4) || \
((__CHANNEL__) == TIM_CHANNEL_5) || \
((__CHANNEL__) == TIM_CHANNEL_6) || \
((__CHANNEL__) == TIM_CHANNEL_ALL))
#define TIM_CHANNEL_2
Definition: stm32h7xx_hal_tim.h:814
#define TIM_CHANNEL_3
Definition: stm32h7xx_hal_tim.h:815
#define TIM_CHANNEL_ALL
Definition: stm32h7xx_hal_tim.h:819
#define TIM_CHANNEL_1
Definition: stm32h7xx_hal_tim.h:813
#define TIM_CHANNEL_4
Definition: stm32h7xx_hal_tim.h:816

◆ IS_TIM_CLEARINPUT_POLARITY

#define IS_TIM_CLEARINPUT_POLARITY (   __POLARITY__)
Value:
(((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
#define TIM_CLEARINPUTPOLARITY_INVERTED
Definition: stm32h7xx_hal_tim.h:876
#define TIM_CLEARINPUTPOLARITY_NONINVERTED
Definition: stm32h7xx_hal_tim.h:877

◆ IS_TIM_CLEARINPUT_PRESCALER

#define IS_TIM_CLEARINPUT_PRESCALER (   __PRESCALER__)
Value:
(((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
#define TIM_CLEARINPUTPRESCALER_DIV8
Definition: stm32h7xx_hal_tim.h:889
#define TIM_CLEARINPUTPRESCALER_DIV4
Definition: stm32h7xx_hal_tim.h:888
#define TIM_CLEARINPUTPRESCALER_DIV2
Definition: stm32h7xx_hal_tim.h:887
#define TIM_CLEARINPUTPRESCALER_DIV1
Definition: stm32h7xx_hal_tim.h:886

◆ IS_TIM_CLEARINPUT_SOURCE

#define IS_TIM_CLEARINPUT_SOURCE (   __MODE__)
Value:
(((__MODE__) == TIM_CLEARINPUTSOURCE_NONE) || \
((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))
#define TIM_CLEARINPUTSOURCE_NONE
Definition: stm32h7xx_hal_tim.h:462
#define TIM_CLEARINPUTSOURCE_ETR
Definition: stm32h7xx_hal_tim.h:463

◆ IS_TIM_CLOCKDIVISION_DIV

#define IS_TIM_CLOCKDIVISION_DIV (   __DIV__)
Value:
(((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
((__DIV__) == TIM_CLOCKDIVISION_DIV4))
#define TIM_CLOCKDIVISION_DIV1
Definition: stm32h7xx_hal_tim.h:581
#define TIM_CLOCKDIVISION_DIV4
Definition: stm32h7xx_hal_tim.h:583
#define TIM_CLOCKDIVISION_DIV2
Definition: stm32h7xx_hal_tim.h:582

◆ IS_TIM_CLOCKPOLARITY

#define IS_TIM_CLOCKPOLARITY (   __POLARITY__)
Value:
(((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
#define TIM_CLOCKPOLARITY_RISING
Definition: stm32h7xx_hal_tim.h:853
#define TIM_CLOCKPOLARITY_BOTHEDGE
Definition: stm32h7xx_hal_tim.h:855
#define TIM_CLOCKPOLARITY_FALLING
Definition: stm32h7xx_hal_tim.h:854
#define TIM_CLOCKPOLARITY_NONINVERTED
Definition: stm32h7xx_hal_tim.h:852
#define TIM_CLOCKPOLARITY_INVERTED
Definition: stm32h7xx_hal_tim.h:851

◆ IS_TIM_CLOCKPRESCALER

#define IS_TIM_CLOCKPRESCALER (   __PRESCALER__)
Value:
(((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
#define TIM_CLOCKPRESCALER_DIV4
Definition: stm32h7xx_hal_tim.h:866
#define TIM_CLOCKPRESCALER_DIV1
Definition: stm32h7xx_hal_tim.h:864
#define TIM_CLOCKPRESCALER_DIV8
Definition: stm32h7xx_hal_tim.h:867
#define TIM_CLOCKPRESCALER_DIV2
Definition: stm32h7xx_hal_tim.h:865

◆ IS_TIM_CLOCKSOURCE

#define IS_TIM_CLOCKSOURCE (   __CLOCK__)
Value:
(((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
((__CLOCK__) == TIM_CLOCKSOURCE_ITR3))
#define TIM_CLOCKSOURCE_TI1
Definition: stm32h7xx_hal_tim.h:832
#define TIM_CLOCKSOURCE_ITR3
Definition: stm32h7xx_hal_tim.h:837
#define TIM_CLOCKSOURCE_ITR0
Definition: stm32h7xx_hal_tim.h:834
#define TIM_CLOCKSOURCE_TI2
Definition: stm32h7xx_hal_tim.h:833
#define TIM_CLOCKSOURCE_INTERNAL
Definition: stm32h7xx_hal_tim.h:828
#define TIM_CLOCKSOURCE_ETRMODE1
Definition: stm32h7xx_hal_tim.h:829
#define TIM_CLOCKSOURCE_ETRMODE2
Definition: stm32h7xx_hal_tim.h:830
#define TIM_CLOCKSOURCE_TI1ED
Definition: stm32h7xx_hal_tim.h:831
#define TIM_CLOCKSOURCE_ITR1
Definition: stm32h7xx_hal_tim.h:835
#define TIM_CLOCKSOURCE_ITR2
Definition: stm32h7xx_hal_tim.h:836

◆ IS_TIM_COMPLEMENTARY_CHANNELS

#define IS_TIM_COMPLEMENTARY_CHANNELS (   __CHANNEL__)
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2) || \
((__CHANNEL__) == TIM_CHANNEL_3))

◆ IS_TIM_COUNTER_MODE

#define IS_TIM_COUNTER_MODE (   __MODE__)
Value:
(((__MODE__) == TIM_COUNTERMODE_UP) || \
((__MODE__) == TIM_COUNTERMODE_DOWN) || \
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
#define TIM_COUNTERMODE_CENTERALIGNED1
Definition: stm32h7xx_hal_tim.h:560
#define TIM_COUNTERMODE_DOWN
Definition: stm32h7xx_hal_tim.h:559
#define TIM_COUNTERMODE_UP
Definition: stm32h7xx_hal_tim.h:558
#define TIM_COUNTERMODE_CENTERALIGNED2
Definition: stm32h7xx_hal_tim.h:561
#define TIM_COUNTERMODE_CENTERALIGNED3
Definition: stm32h7xx_hal_tim.h:562

◆ IS_TIM_DMA_BASE

#define IS_TIM_DMA_BASE (   __BASE__)
Value:
(((__BASE__) == TIM_DMABASE_CR1) || \
((__BASE__) == TIM_DMABASE_CR2) || \
((__BASE__) == TIM_DMABASE_SMCR) || \
((__BASE__) == TIM_DMABASE_DIER) || \
((__BASE__) == TIM_DMABASE_SR) || \
((__BASE__) == TIM_DMABASE_EGR) || \
((__BASE__) == TIM_DMABASE_CCMR1) || \
((__BASE__) == TIM_DMABASE_CCMR2) || \
((__BASE__) == TIM_DMABASE_CCER) || \
((__BASE__) == TIM_DMABASE_CNT) || \
((__BASE__) == TIM_DMABASE_PSC) || \
((__BASE__) == TIM_DMABASE_ARR) || \
((__BASE__) == TIM_DMABASE_RCR) || \
((__BASE__) == TIM_DMABASE_CCR1) || \
((__BASE__) == TIM_DMABASE_CCR2) || \
((__BASE__) == TIM_DMABASE_CCR3) || \
((__BASE__) == TIM_DMABASE_CCR4) || \
((__BASE__) == TIM_DMABASE_BDTR) || \
((__BASE__) == TIM_DMABASE_CCMR3) || \
((__BASE__) == TIM_DMABASE_CCR5) || \
((__BASE__) == TIM_DMABASE_CCR6) || \
((__BASE__) == TIM_DMABASE_AF1) || \
((__BASE__) == TIM_DMABASE_AF2) || \
((__BASE__) == TIM_DMABASE_TISEL))

◆ IS_TIM_DMA_LENGTH

#define IS_TIM_DMA_LENGTH (   __LENGTH__)
Value:
(((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
#define TIM_DMABURSTLENGTH_13TRANSFERS
Definition: stm32h7xx_hal_tim.h:1175
#define TIM_DMABURSTLENGTH_14TRANSFERS
Definition: stm32h7xx_hal_tim.h:1176
#define TIM_DMABURSTLENGTH_9TRANSFERS
Definition: stm32h7xx_hal_tim.h:1171
#define TIM_DMABURSTLENGTH_5TRANSFERS
Definition: stm32h7xx_hal_tim.h:1167
#define TIM_DMABURSTLENGTH_1TRANSFER
Definition: stm32h7xx_hal_tim.h:1163
#define TIM_DMABURSTLENGTH_10TRANSFERS
Definition: stm32h7xx_hal_tim.h:1172
#define TIM_DMABURSTLENGTH_11TRANSFERS
Definition: stm32h7xx_hal_tim.h:1173
#define TIM_DMABURSTLENGTH_6TRANSFERS
Definition: stm32h7xx_hal_tim.h:1168
#define TIM_DMABURSTLENGTH_15TRANSFERS
Definition: stm32h7xx_hal_tim.h:1177
#define TIM_DMABURSTLENGTH_4TRANSFERS
Definition: stm32h7xx_hal_tim.h:1166
#define TIM_DMABURSTLENGTH_2TRANSFERS
Definition: stm32h7xx_hal_tim.h:1164
#define TIM_DMABURSTLENGTH_18TRANSFERS
Definition: stm32h7xx_hal_tim.h:1180
#define TIM_DMABURSTLENGTH_8TRANSFERS
Definition: stm32h7xx_hal_tim.h:1170
#define TIM_DMABURSTLENGTH_17TRANSFERS
Definition: stm32h7xx_hal_tim.h:1179
#define TIM_DMABURSTLENGTH_3TRANSFERS
Definition: stm32h7xx_hal_tim.h:1165
#define TIM_DMABURSTLENGTH_7TRANSFERS
Definition: stm32h7xx_hal_tim.h:1169
#define TIM_DMABURSTLENGTH_16TRANSFERS
Definition: stm32h7xx_hal_tim.h:1178
#define TIM_DMABURSTLENGTH_12TRANSFERS
Definition: stm32h7xx_hal_tim.h:1174

◆ IS_TIM_ENCODER_MODE

#define IS_TIM_ENCODER_MODE (   __MODE__)
Value:
(((__MODE__) == TIM_ENCODERMODE_TI1) || \
((__MODE__) == TIM_ENCODERMODE_TI2) || \
((__MODE__) == TIM_ENCODERMODE_TI12))
#define TIM_ENCODERMODE_TI12
Definition: stm32h7xx_hal_tim.h:729
#define TIM_ENCODERMODE_TI2
Definition: stm32h7xx_hal_tim.h:728
#define TIM_ENCODERMODE_TI1
Definition: stm32h7xx_hal_tim.h:727

◆ IS_TIM_ENCODERINPUT_POLARITY

#define IS_TIM_ENCODERINPUT_POLARITY (   __POLARITY__)
Value:
(((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
#define TIM_ENCODERINPUTPOLARITY_RISING
Definition: stm32h7xx_hal_tim.h:684
#define TIM_ENCODERINPUTPOLARITY_FALLING
Definition: stm32h7xx_hal_tim.h:685

◆ IS_TIM_FAST_STATE

#define IS_TIM_FAST_STATE (   __STATE__)
Value:
(((__STATE__) == TIM_OCFAST_DISABLE) || \
((__STATE__) == TIM_OCFAST_ENABLE))
#define TIM_OCFAST_ENABLE
Definition: stm32h7xx_hal_tim.h:614
#define TIM_OCFAST_DISABLE
Definition: stm32h7xx_hal_tim.h:613

◆ IS_TIM_IC_POLARITY

#define IS_TIM_IC_POLARITY (   __POLARITY__)
Value:
(((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
#define TIM_ICPOLARITY_BOTHEDGE
Definition: stm32h7xx_hal_tim.h:675
#define TIM_ICPOLARITY_RISING
Definition: stm32h7xx_hal_tim.h:673
#define TIM_ICPOLARITY_FALLING
Definition: stm32h7xx_hal_tim.h:674

◆ IS_TIM_IC_PRESCALER

#define IS_TIM_IC_PRESCALER (   __PRESCALER__)
Value:
(((__PRESCALER__) == TIM_ICPSC_DIV1) || \
((__PRESCALER__) == TIM_ICPSC_DIV2) || \
((__PRESCALER__) == TIM_ICPSC_DIV4) || \
((__PRESCALER__) == TIM_ICPSC_DIV8))
#define TIM_ICPSC_DIV2
Definition: stm32h7xx_hal_tim.h:706
#define TIM_ICPSC_DIV8
Definition: stm32h7xx_hal_tim.h:708
#define TIM_ICPSC_DIV1
Definition: stm32h7xx_hal_tim.h:705
#define TIM_ICPSC_DIV4
Definition: stm32h7xx_hal_tim.h:707

◆ IS_TIM_IC_SELECTION

#define IS_TIM_IC_SELECTION (   __SELECTION__)
Value:
(((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
((__SELECTION__) == TIM_ICSELECTION_TRC))
#define TIM_ICSELECTION_TRC
Definition: stm32h7xx_hal_tim.h:696
#define TIM_ICSELECTION_INDIRECTTI
Definition: stm32h7xx_hal_tim.h:695
#define TIM_ICSELECTION_DIRECTTI
Definition: stm32h7xx_hal_tim.h:694

◆ IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION

#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION (   __SELECTION__)
Value:
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR12) || \
((__SELECTION__) == TIM_TS_ITR13) || \
((__SELECTION__) == TIM_TS_NONE))
#define TIM_TS_ITR12
Definition: stm32h7xx_hal_tim.h:1113
#define TIM_TS_NONE
Definition: stm32h7xx_hal_tim.h:1119
#define TIM_TS_ITR6
Definition: stm32h7xx_hal_tim.h:1107
#define TIM_TS_ITR7
Definition: stm32h7xx_hal_tim.h:1108
#define TIM_TS_ITR3
Definition: stm32h7xx_hal_tim.h:1104
#define TIM_TS_ITR2
Definition: stm32h7xx_hal_tim.h:1103
#define TIM_TS_ITR4
Definition: stm32h7xx_hal_tim.h:1105
#define TIM_TS_ITR0
Definition: stm32h7xx_hal_tim.h:1101
#define TIM_TS_ITR8
Definition: stm32h7xx_hal_tim.h:1109
#define TIM_TS_ITR13
Definition: stm32h7xx_hal_tim.h:1114
#define TIM_TS_ITR5
Definition: stm32h7xx_hal_tim.h:1106
#define TIM_TS_ITR1
Definition: stm32h7xx_hal_tim.h:1102

◆ IS_TIM_LOCK_LEVEL

#define IS_TIM_LOCK_LEVEL (   __LEVEL__)
Value:
(((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
((__LEVEL__) == TIM_LOCKLEVEL_1) || \
((__LEVEL__) == TIM_LOCKLEVEL_2) || \
((__LEVEL__) == TIM_LOCKLEVEL_3))
#define TIM_LOCKLEVEL_2
Definition: stm32h7xx_hal_tim.h:919
#define TIM_LOCKLEVEL_OFF
Definition: stm32h7xx_hal_tim.h:917
#define TIM_LOCKLEVEL_1
Definition: stm32h7xx_hal_tim.h:918
#define TIM_LOCKLEVEL_3
Definition: stm32h7xx_hal_tim.h:920

◆ IS_TIM_MSM_STATE

#define IS_TIM_MSM_STATE (   __STATE__)
Value:
(((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
#define TIM_MASTERSLAVEMODE_DISABLE
Definition: stm32h7xx_hal_tim.h:1056
#define TIM_MASTERSLAVEMODE_ENABLE
Definition: stm32h7xx_hal_tim.h:1055

◆ IS_TIM_OC_MODE

#define IS_TIM_OC_MODE (   __MODE__)
Value:
(((__MODE__) == TIM_OCMODE_TIMING) || \
((__MODE__) == TIM_OCMODE_ACTIVE) || \
((__MODE__) == TIM_OCMODE_INACTIVE) || \
((__MODE__) == TIM_OCMODE_TOGGLE) || \
((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \
((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \
((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \
#define TIM_OCMODE_FORCED_ACTIVE
Definition: stm32h7xx_hal_tim.h:1085
#define TIM_OCMODE_ACTIVE
Definition: stm32h7xx_hal_tim.h:1080
#define TIM_OCMODE_TOGGLE
Definition: stm32h7xx_hal_tim.h:1082
#define TIM_OCMODE_FORCED_INACTIVE
Definition: stm32h7xx_hal_tim.h:1086
#define TIM_OCMODE_RETRIGERRABLE_OPM1
Definition: stm32h7xx_hal_tim.h:1087
#define TIM_OCMODE_RETRIGERRABLE_OPM2
Definition: stm32h7xx_hal_tim.h:1088
#define TIM_OCMODE_INACTIVE
Definition: stm32h7xx_hal_tim.h:1081
#define TIM_OCMODE_TIMING
Definition: stm32h7xx_hal_tim.h:1079

◆ IS_TIM_OC_POLARITY

#define IS_TIM_OC_POLARITY (   __POLARITY__)
Value:
(((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
((__POLARITY__) == TIM_OCPOLARITY_LOW))
#define TIM_OCPOLARITY_LOW
Definition: stm32h7xx_hal_tim.h:634
#define TIM_OCPOLARITY_HIGH
Definition: stm32h7xx_hal_tim.h:633

◆ IS_TIM_OCIDLE_STATE

#define IS_TIM_OCIDLE_STATE (   __STATE__)
Value:
(((__STATE__) == TIM_OCIDLESTATE_SET) || \
((__STATE__) == TIM_OCIDLESTATE_RESET))
#define TIM_OCIDLESTATE_RESET
Definition: stm32h7xx_hal_tim.h:654
#define TIM_OCIDLESTATE_SET
Definition: stm32h7xx_hal_tim.h:653

◆ IS_TIM_OCN_POLARITY

#define IS_TIM_OCN_POLARITY (   __POLARITY__)
Value:
(((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
((__POLARITY__) == TIM_OCNPOLARITY_LOW))
#define TIM_OCNPOLARITY_HIGH
Definition: stm32h7xx_hal_tim.h:643
#define TIM_OCNPOLARITY_LOW
Definition: stm32h7xx_hal_tim.h:644

◆ IS_TIM_OCNIDLE_STATE

#define IS_TIM_OCNIDLE_STATE (   __STATE__)
Value:
(((__STATE__) == TIM_OCNIDLESTATE_SET) || \
((__STATE__) == TIM_OCNIDLESTATE_RESET))
#define TIM_OCNIDLESTATE_SET
Definition: stm32h7xx_hal_tim.h:663
#define TIM_OCNIDLESTATE_RESET
Definition: stm32h7xx_hal_tim.h:664

◆ IS_TIM_OPM_CHANNELS

#define IS_TIM_OPM_CHANNELS (   __CHANNEL__)
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) || \
((__CHANNEL__) == TIM_CHANNEL_2))

◆ IS_TIM_OPM_MODE

#define IS_TIM_OPM_MODE (   __MODE__)
Value:
(((__MODE__) == TIM_OPMODE_SINGLE) || \
((__MODE__) == TIM_OPMODE_REPETITIVE))
#define TIM_OPMODE_REPETITIVE
Definition: stm32h7xx_hal_tim.h:718
#define TIM_OPMODE_SINGLE
Definition: stm32h7xx_hal_tim.h:717

◆ IS_TIM_OSSI_STATE

#define IS_TIM_OSSI_STATE (   __STATE__)
Value:
(((__STATE__) == TIM_OSSI_ENABLE) || \
((__STATE__) == TIM_OSSI_DISABLE))
#define TIM_OSSI_DISABLE
Definition: stm32h7xx_hal_tim.h:909
#define TIM_OSSI_ENABLE
Definition: stm32h7xx_hal_tim.h:908

◆ IS_TIM_OSSR_STATE

#define IS_TIM_OSSR_STATE (   __STATE__)
Value:
(((__STATE__) == TIM_OSSR_ENABLE) || \
((__STATE__) == TIM_OSSR_DISABLE))
#define TIM_OSSR_ENABLE
Definition: stm32h7xx_hal_tim.h:898
#define TIM_OSSR_DISABLE
Definition: stm32h7xx_hal_tim.h:899

◆ IS_TIM_PERIOD

#define IS_TIM_PERIOD (   __HANDLE__,
  __PERIOD__ 
)
Value:
((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
(((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
((__PERIOD__) > 0U))

◆ IS_TIM_PWM_MODE

#define IS_TIM_PWM_MODE (   __MODE__)
Value:
(((__MODE__) == TIM_OCMODE_PWM1) || \
((__MODE__) == TIM_OCMODE_PWM2) || \
((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \
((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
#define TIM_OCMODE_ASYMMETRIC_PWM2
Definition: stm32h7xx_hal_tim.h:1092
#define TIM_OCMODE_PWM1
Definition: stm32h7xx_hal_tim.h:1083
#define TIM_OCMODE_PWM2
Definition: stm32h7xx_hal_tim.h:1084
#define TIM_OCMODE_COMBINED_PWM1
Definition: stm32h7xx_hal_tim.h:1089
#define TIM_OCMODE_ASYMMETRIC_PWM1
Definition: stm32h7xx_hal_tim.h:1091
#define TIM_OCMODE_COMBINED_PWM2
Definition: stm32h7xx_hal_tim.h:1090

◆ IS_TIM_SLAVE_MODE

#define IS_TIM_SLAVE_MODE (   __MODE__)
Value:
(((__MODE__) == TIM_SLAVEMODE_DISABLE) || \
((__MODE__) == TIM_SLAVEMODE_RESET) || \
((__MODE__) == TIM_SLAVEMODE_GATED) || \
((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \
((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \
#define TIM_SLAVEMODE_TRIGGER
Definition: stm32h7xx_hal_tim.h:1068
#define TIM_SLAVEMODE_DISABLE
Definition: stm32h7xx_hal_tim.h:1065
#define TIM_SLAVEMODE_GATED
Definition: stm32h7xx_hal_tim.h:1067
#define TIM_SLAVEMODE_EXTERNAL1
Definition: stm32h7xx_hal_tim.h:1069
#define TIM_SLAVEMODE_RESET
Definition: stm32h7xx_hal_tim.h:1066
#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER
Definition: stm32h7xx_hal_tim.h:1070

◆ IS_TIM_SLAVEMODE_TRIGGER_ENABLED

#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED (   __TRIGGER__)
Value:
(((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \

◆ IS_TIM_TI1SELECTION

#define IS_TIM_TI1SELECTION (   __TI1SELECTION__)
Value:
(((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
#define TIM_TI1SELECTION_XORCOMBINATION
Definition: stm32h7xx_hal_tim.h:1154
#define TIM_TI1SELECTION_CH1
Definition: stm32h7xx_hal_tim.h:1153

◆ IS_TIM_TRGO2_SOURCE

#define IS_TIM_TRGO2_SOURCE (   __SOURCE__)
Value:
(((__SOURCE__) == TIM_TRGO2_RESET) || \
((__SOURCE__) == TIM_TRGO2_ENABLE) || \
((__SOURCE__) == TIM_TRGO2_UPDATE) || \
((__SOURCE__) == TIM_TRGO2_OC1) || \
((__SOURCE__) == TIM_TRGO2_OC1REF) || \
((__SOURCE__) == TIM_TRGO2_OC2REF) || \
((__SOURCE__) == TIM_TRGO2_OC3REF) || \
((__SOURCE__) == TIM_TRGO2_OC3REF) || \
((__SOURCE__) == TIM_TRGO2_OC4REF) || \
((__SOURCE__) == TIM_TRGO2_OC5REF) || \
((__SOURCE__) == TIM_TRGO2_OC6REF) || \
((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \
((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \
#define TIM_TRGO2_OC4REF_RISINGFALLING
Definition: stm32h7xx_hal_tim.h:1041
#define TIM_TRGO2_RESET
Definition: stm32h7xx_hal_tim.h:1031
#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING
Definition: stm32h7xx_hal_tim.h:1044
#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING
Definition: stm32h7xx_hal_tim.h:1043
#define TIM_TRGO2_OC1
Definition: stm32h7xx_hal_tim.h:1034
#define TIM_TRGO2_OC3REF
Definition: stm32h7xx_hal_tim.h:1037
#define TIM_TRGO2_UPDATE
Definition: stm32h7xx_hal_tim.h:1033
#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING
Definition: stm32h7xx_hal_tim.h:1046
#define TIM_TRGO2_OC5REF
Definition: stm32h7xx_hal_tim.h:1039
#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING
Definition: stm32h7xx_hal_tim.h:1045
#define TIM_TRGO2_OC4REF
Definition: stm32h7xx_hal_tim.h:1038
#define TIM_TRGO2_OC2REF
Definition: stm32h7xx_hal_tim.h:1036
#define TIM_TRGO2_ENABLE
Definition: stm32h7xx_hal_tim.h:1032
#define TIM_TRGO2_OC1REF
Definition: stm32h7xx_hal_tim.h:1035
#define TIM_TRGO2_OC6REF
Definition: stm32h7xx_hal_tim.h:1040
#define TIM_TRGO2_OC6REF_RISINGFALLING
Definition: stm32h7xx_hal_tim.h:1042

◆ IS_TIM_TRGO_SOURCE

#define IS_TIM_TRGO_SOURCE (   __SOURCE__)
Value:
(((__SOURCE__) == TIM_TRGO_RESET) || \
((__SOURCE__) == TIM_TRGO_ENABLE) || \
((__SOURCE__) == TIM_TRGO_UPDATE) || \
((__SOURCE__) == TIM_TRGO_OC1) || \
((__SOURCE__) == TIM_TRGO_OC1REF) || \
((__SOURCE__) == TIM_TRGO_OC2REF) || \
((__SOURCE__) == TIM_TRGO_OC3REF) || \
((__SOURCE__) == TIM_TRGO_OC4REF))
#define TIM_TRGO_UPDATE
Definition: stm32h7xx_hal_tim.h:1017
#define TIM_TRGO_RESET
Definition: stm32h7xx_hal_tim.h:1015
#define TIM_TRGO_ENABLE
Definition: stm32h7xx_hal_tim.h:1016
#define TIM_TRGO_OC3REF
Definition: stm32h7xx_hal_tim.h:1021
#define TIM_TRGO_OC4REF
Definition: stm32h7xx_hal_tim.h:1022
#define TIM_TRGO_OC1
Definition: stm32h7xx_hal_tim.h:1018
#define TIM_TRGO_OC2REF
Definition: stm32h7xx_hal_tim.h:1020
#define TIM_TRGO_OC1REF
Definition: stm32h7xx_hal_tim.h:1019

◆ IS_TIM_TRIGGER_SELECTION

#define IS_TIM_TRIGGER_SELECTION (   __SELECTION__)
Value:
(((__SELECTION__) == TIM_TS_ITR0) || \
((__SELECTION__) == TIM_TS_ITR1) || \
((__SELECTION__) == TIM_TS_ITR2) || \
((__SELECTION__) == TIM_TS_ITR3) || \
((__SELECTION__) == TIM_TS_ITR4) || \
((__SELECTION__) == TIM_TS_ITR5) || \
((__SELECTION__) == TIM_TS_ITR6) || \
((__SELECTION__) == TIM_TS_ITR7) || \
((__SELECTION__) == TIM_TS_ITR8) || \
((__SELECTION__) == TIM_TS_ITR12) || \
((__SELECTION__) == TIM_TS_ITR13) || \
((__SELECTION__) == TIM_TS_TI1F_ED) || \
((__SELECTION__) == TIM_TS_TI1FP1) || \
((__SELECTION__) == TIM_TS_TI2FP2) || \
((__SELECTION__) == TIM_TS_ETRF))
#define TIM_TS_TI2FP2
Definition: stm32h7xx_hal_tim.h:1117
#define TIM_TS_TI1FP1
Definition: stm32h7xx_hal_tim.h:1116
#define TIM_TS_TI1F_ED
Definition: stm32h7xx_hal_tim.h:1115
#define TIM_TS_ETRF
Definition: stm32h7xx_hal_tim.h:1118

◆ IS_TIM_TRIGGERPOLARITY

#define IS_TIM_TRIGGERPOLARITY (   __POLARITY__)
Value:
(((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
#define TIM_TRIGGERPOLARITY_INVERTED
Definition: stm32h7xx_hal_tim.h:1128
#define TIM_TRIGGERPOLARITY_RISING
Definition: stm32h7xx_hal_tim.h:1130
#define TIM_TRIGGERPOLARITY_FALLING
Definition: stm32h7xx_hal_tim.h:1131
#define TIM_TRIGGERPOLARITY_BOTHEDGE
Definition: stm32h7xx_hal_tim.h:1132
#define TIM_TRIGGERPOLARITY_NONINVERTED
Definition: stm32h7xx_hal_tim.h:1129

◆ IS_TIM_TRIGGERPRESCALER

#define IS_TIM_TRIGGERPRESCALER (   __PRESCALER__)
Value:
(((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
#define TIM_TRIGGERPRESCALER_DIV1
Definition: stm32h7xx_hal_tim.h:1141
#define TIM_TRIGGERPRESCALER_DIV2
Definition: stm32h7xx_hal_tim.h:1142
#define TIM_TRIGGERPRESCALER_DIV4
Definition: stm32h7xx_hal_tim.h:1143
#define TIM_TRIGGERPRESCALER_DIV8
Definition: stm32h7xx_hal_tim.h:1144

◆ IS_TIM_UIFREMAP_MODE

#define IS_TIM_UIFREMAP_MODE (   __MODE__)
Value:
(((__MODE__) == TIM_UIFREMAP_DISABLE) || \
((__MODE__) == TIM_UIFREMAP_ENABLE))
#define TIM_UIFREMAP_ENABLE
Definition: stm32h7xx_hal_tim.h:572
#define TIM_UIFREMAP_DISABLE
Definition: stm32h7xx_hal_tim.h:571

◆ TIM_CHANNEL_N_STATE_GET

#define TIM_CHANNEL_N_STATE_GET (   __HANDLE__,
  __CHANNEL__ 
)
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\
(__HANDLE__)->ChannelNState[3])

◆ TIM_CHANNEL_N_STATE_SET

#define TIM_CHANNEL_N_STATE_SET (   __HANDLE__,
  __CHANNEL__,
  __CHANNEL_STATE__ 
)
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\
((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__)))

◆ TIM_CHANNEL_N_STATE_SET_ALL

#define TIM_CHANNEL_N_STATE_SET_ALL (   __HANDLE__,
  __CHANNEL_STATE__ 
)
Value:
do { \
(__HANDLE__)->ChannelNState[0] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[1] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[2] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelNState[3] = \
(__CHANNEL_STATE__); \
} while(0)

◆ TIM_CHANNEL_STATE_GET

#define TIM_CHANNEL_STATE_GET (   __HANDLE__,
  __CHANNEL__ 
)
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\
((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\
((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\
((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\
((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\
(__HANDLE__)->ChannelState[5])

◆ TIM_CHANNEL_STATE_SET

#define TIM_CHANNEL_STATE_SET (   __HANDLE__,
  __CHANNEL__,
  __CHANNEL_STATE__ 
)
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\
((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__)))

◆ TIM_CHANNEL_STATE_SET_ALL

#define TIM_CHANNEL_STATE_SET_ALL (   __HANDLE__,
  __CHANNEL_STATE__ 
)
Value:
do { \
(__HANDLE__)->ChannelState[0] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[1] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[2] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[3] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[4] = \
(__CHANNEL_STATE__); \
(__HANDLE__)->ChannelState[5] = \
(__CHANNEL_STATE__); \
} while(0)

◆ TIM_RESET_CAPTUREPOLARITY

#define TIM_RESET_CAPTUREPOLARITY (   __HANDLE__,
  __CHANNEL__ 
)
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
#define TIM_CCER_CC1P
Definition: stm32h723xx.h:19643
#define TIM_CCER_CC2P
Definition: stm32h723xx.h:19655
#define TIM_CCER_CC2NP
Definition: stm32h723xx.h:19661
#define TIM_CCER_CC4P
Definition: stm32h723xx.h:19679
#define TIM_CCER_CC3NP
Definition: stm32h723xx.h:19673
#define TIM_CCER_CC1NP
Definition: stm32h723xx.h:19649
#define TIM_CCER_CC4NP
Definition: stm32h723xx.h:19682
#define TIM_CCER_CC3P
Definition: stm32h723xx.h:19667

◆ TIM_RESET_ICPRESCALERVALUE

#define TIM_RESET_ICPRESCALERVALUE (   __HANDLE__,
  __CHANNEL__ 
)
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
#define TIM_CCMR1_IC2PSC
Definition: stm32h723xx.h:19544
#define TIM_CCMR2_IC4PSC
Definition: stm32h723xx.h:19625
#define TIM_CCMR1_IC1PSC
Definition: stm32h723xx.h:19530
#define TIM_CCMR2_IC3PSC
Definition: stm32h723xx.h:19611

◆ TIM_SET_CAPTUREPOLARITY

#define TIM_SET_CAPTUREPOLARITY (   __HANDLE__,
  __CHANNEL__,
  __POLARITY__ 
)
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))

◆ TIM_SET_ICPRESCALERVALUE

#define TIM_SET_ICPRESCALERVALUE (   __HANDLE__,
  __CHANNEL__,
  __ICPSC__ 
)
Value:
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))