Macros
#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	USART10 ((USART_TypeDef *) USART10_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	UART9 ((USART_TypeDef *) UART9_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	I2C5 ((I2C_TypeDef *) I2C5_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)

#define	TIM23 ((TIM_TypeDef *) TIM23_BASE)

#define	TIM24 ((TIM_TypeDef *) TIM24_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	DTS ((DTS_TypeDef *) DTS_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	PSSI ((PSSI_TypeDef *) PSSI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	FMAC ((FMAC_TypeDef *) FMAC_BASE)

#define	CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

#define	DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

#define	OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

#define	DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

#define	OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	USART10 ((USART_TypeDef *) USART10_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	UART9 ((USART_TypeDef *) UART9_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	I2C5 ((I2C_TypeDef *) I2C5_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)

#define	TIM23 ((TIM_TypeDef *) TIM23_BASE)

#define	TIM24 ((TIM_TypeDef *) TIM24_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	DTS ((DTS_TypeDef *) DTS_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	PSSI ((PSSI_TypeDef *) PSSI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	FMAC ((FMAC_TypeDef *) FMAC_BASE)

#define	CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

#define	DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

#define	OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

#define	DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

#define	OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	USART10 ((USART_TypeDef *) USART10_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	UART9 ((USART_TypeDef *) UART9_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	I2C5 ((I2C_TypeDef *) I2C5_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)

#define	TIM23 ((TIM_TypeDef *) TIM23_BASE)

#define	TIM24 ((TIM_TypeDef *) TIM24_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	DTS ((DTS_TypeDef *) DTS_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	PSSI ((PSSI_TypeDef *) PSSI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	CRYP ((CRYP_TypeDef *) CRYP_BASE)

#define	HASH ((HASH_TypeDef *) HASH_BASE)

#define	HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	FMAC ((FMAC_TypeDef *) FMAC_BASE)

#define	CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

#define	DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

#define	OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

#define	DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

#define	OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

#define	OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE)

#define	OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)

#define	OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)

#define	OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)

#define	OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)

#define	OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE)

#define	OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)

#define	OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)

#define	OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)

#define	OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	USART10 ((USART_TypeDef *) USART10_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	UART9 ((USART_TypeDef *) UART9_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	I2C5 ((I2C_TypeDef *) I2C5_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)

#define	TIM23 ((TIM_TypeDef *) TIM23_BASE)

#define	TIM24 ((TIM_TypeDef *) TIM24_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	DTS ((DTS_TypeDef *) DTS_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	PSSI ((PSSI_TypeDef *) PSSI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	CRYP ((CRYP_TypeDef *) CRYP_BASE)

#define	HASH ((HASH_TypeDef *) HASH_BASE)

#define	HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	FMAC ((FMAC_TypeDef *) FMAC_BASE)

#define	CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

#define	DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

#define	OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

#define	DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

#define	OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

#define	OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE)

#define	OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)

#define	OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)

#define	OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)

#define	OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)

#define	OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE)

#define	OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)

#define	OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)

#define	OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)

#define	OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	USART10 ((USART_TypeDef *) USART10_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	UART9 ((USART_TypeDef *) UART9_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	I2C5 ((I2C_TypeDef *) I2C5_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)

#define	TIM23 ((TIM_TypeDef *) TIM23_BASE)

#define	TIM24 ((TIM_TypeDef *) TIM24_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	DTS ((DTS_TypeDef *) DTS_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	PSSI ((PSSI_TypeDef *) PSSI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	CRYP ((CRYP_TypeDef *) CRYP_BASE)

#define	HASH ((HASH_TypeDef *) HASH_BASE)

#define	HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	FMAC ((FMAC_TypeDef *) FMAC_BASE)

#define	CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

#define	DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

#define	OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

#define	DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

#define	OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

#define	OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE)

#define	OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)

#define	OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)

#define	OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)

#define	OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)

#define	OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE)

#define	OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)

#define	OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)

#define	OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)

#define	OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	USART10 ((USART_TypeDef *) USART10_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	UART9 ((USART_TypeDef *) UART9_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	I2C5 ((I2C_TypeDef *) I2C5_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	FDCAN3 ((FDCAN_GlobalTypeDef *) FDCAN3_BASE)

#define	TIM23 ((TIM_TypeDef *) TIM23_BASE)

#define	TIM24 ((TIM_TypeDef *) TIM24_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	DTS ((DTS_TypeDef *) DTS_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	PSSI ((PSSI_TypeDef *) PSSI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	CRYP ((CRYP_TypeDef *) CRYP_BASE)

#define	HASH ((HASH_TypeDef *) HASH_BASE)

#define	HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	FMAC ((FMAC_TypeDef *) FMAC_BASE)

#define	CORDIC ((CORDIC_TypeDef *) CORDIC_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC1_Monitor6 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor6_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

#define	DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

#define	OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

#define	DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

#define	OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

#define	OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE)

#define	OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)

#define	OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)

#define	OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)

#define	OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)

#define	OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE)

#define	OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)

#define	OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)

#define	OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)

#define	OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)

#define	HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

#define	HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

#define	HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

#define	HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

#define	HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

#define	HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SAI3 ((SAI_TypeDef *) SAI3_BASE)

#define	SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

#define	SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

#define	RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)

#define	DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	USB_OTG_FS USB2_OTG_FS

#define	USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)

#define	HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

#define	HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

#define	HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

#define	HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

#define	HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

#define	HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SAI3 ((SAI_TypeDef *) SAI3_BASE)

#define	SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

#define	SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

#define	RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)

#define	DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	JPEG ((JPEG_TypeDef *) JPGDEC_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	USB_OTG_FS USB2_OTG_FS

#define	USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	WWDG2 ((WWDG_TypeDef *) WWDG2_BASE)

#define	IWDG2 ((IWDG_TypeDef *) IWDG2_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)

#define	HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

#define	HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

#define	HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

#define	HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

#define	HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

#define	HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SAI3 ((SAI_TypeDef *) SAI3_BASE)

#define	SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

#define	SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)

#define	RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE)

#define	ART ((ART_TypeDef *) ART_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

#define	RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)

#define	DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	JPEG ((JPEG_TypeDef *) JPGDEC_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	USB_OTG_FS USB2_OTG_FS

#define	USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	WWDG2 ((WWDG_TypeDef *) WWDG2_BASE)

#define	IWDG2 ((IWDG_TypeDef *) IWDG2_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)

#define	HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

#define	HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

#define	HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

#define	HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

#define	HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

#define	HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SAI3 ((SAI_TypeDef *) SAI3_BASE)

#define	SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

#define	SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)

#define	RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE)

#define	ART ((ART_TypeDef *) ART_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

#define	RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)

#define	DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	JPEG ((JPEG_TypeDef *) JPGDEC_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	USB_OTG_FS USB2_OTG_FS

#define	USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	WWDG2 ((WWDG_TypeDef *) WWDG2_BASE)

#define	IWDG2 ((IWDG_TypeDef *) IWDG2_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)

#define	HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

#define	HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

#define	HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

#define	HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

#define	HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

#define	HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SAI3 ((SAI_TypeDef *) SAI3_BASE)

#define	SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

#define	SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)

#define	RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE)

#define	ART ((ART_TypeDef *) ART_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

#define	RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)

#define	DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	JPEG ((JPEG_TypeDef *) JPGDEC_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	DSI ((DSI_TypeDef *)DSI_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	USB_OTG_FS USB2_OTG_FS

#define	USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	WWDG2 ((WWDG_TypeDef *) WWDG2_BASE)

#define	IWDG2 ((IWDG_TypeDef *) IWDG2_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)

#define	HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

#define	HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

#define	HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

#define	HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

#define	HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

#define	HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SAI3 ((SAI_TypeDef *) SAI3_BASE)

#define	SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

#define	SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)

#define	RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE)

#define	ART ((ART_TypeDef *) ART_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

#define	RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)

#define	DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	JPEG ((JPEG_TypeDef *) JPGDEC_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	DSI ((DSI_TypeDef *)DSI_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	USB_OTG_FS USB2_OTG_FS

#define	USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)

#define	HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

#define	HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

#define	HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

#define	HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

#define	HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

#define	HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SAI3 ((SAI_TypeDef *) SAI3_BASE)

#define	SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

#define	SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	CRYP ((CRYP_TypeDef *) CRYP_BASE)

#define	HASH ((HASH_TypeDef *) HASH_BASE)

#define	HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

#define	RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)

#define	DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	JPEG ((JPEG_TypeDef *) JPGDEC_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	USB_OTG_FS USB2_OTG_FS

#define	USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)

#define	HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

#define	HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

#define	HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

#define	HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

#define	HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

#define	HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SAI3 ((SAI_TypeDef *) SAI3_BASE)

#define	SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

#define	SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	CRYP ((CRYP_TypeDef *) CRYP_BASE)

#define	HASH ((HASH_TypeDef *) HASH_BASE)

#define	HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

#define	RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)

#define	DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	JPEG ((JPEG_TypeDef *) JPGDEC_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	USB_OTG_FS USB2_OTG_FS

#define	USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	WWDG2 ((WWDG_TypeDef *) WWDG2_BASE)

#define	IWDG2 ((IWDG_TypeDef *) IWDG2_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)

#define	HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

#define	HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

#define	HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

#define	HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

#define	HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

#define	HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SAI3 ((SAI_TypeDef *) SAI3_BASE)

#define	SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

#define	SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)

#define	RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE)

#define	ART ((ART_TypeDef *) ART_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	CRYP ((CRYP_TypeDef *) CRYP_BASE)

#define	HASH ((HASH_TypeDef *) HASH_BASE)

#define	HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

#define	RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)

#define	DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	JPEG ((JPEG_TypeDef *) JPGDEC_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	USB_OTG_FS USB2_OTG_FS

#define	USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	WWDG2 ((WWDG_TypeDef *) WWDG2_BASE)

#define	IWDG2 ((IWDG_TypeDef *) IWDG2_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)

#define	LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)

#define	HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

#define	HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

#define	HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

#define	HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

#define	HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

#define	HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SAI3 ((SAI_TypeDef *) SAI3_BASE)

#define	SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

#define	SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

#define	SAI4 ((SAI_TypeDef *) SAI4_BASE)

#define	SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

#define	SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)

#define	RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE)

#define	ART ((ART_TypeDef *) ART_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC3 ((ADC_TypeDef *) ADC3_BASE)

#define	ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	CRYP ((CRYP_TypeDef *) CRYP_BASE)

#define	HASH ((HASH_TypeDef *) HASH_BASE)

#define	HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA ((BDMA_TypeDef *) BDMA_BASE)

#define	BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

#define	BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

#define	BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

#define	BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

#define	BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

#define	BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

#define	BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

#define	BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

#define	RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)

#define	RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

#define	RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

#define	RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

#define	RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

#define	RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

#define	RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)

#define	RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

#define	RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

#define	RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

#define	RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

#define	RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

#define	RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)

#define	RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

#define	RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)

#define	DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	JPEG ((JPEG_TypeDef *) JPGDEC_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	DSI ((DSI_TypeDef *)DSI_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	ETH ((ETH_TypeDef *)ETH_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	USB_OTG_FS USB2_OTG_FS

#define	USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	TAMP ((TAMP_TypeDef *) TAMP_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	USART10 ((USART_TypeDef *) USART10_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	UART9 ((USART_TypeDef *) UART9_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	DTS ((DTS_TypeDef *) DTS_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DFSDM1_Filter4 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)

#define	DFSDM1_Filter5 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)

#define	DFSDM1_Filter6 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)

#define	DFSDM1_Filter7 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)

#define	DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)

#define	DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)

#define	DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	PSSI ((PSSI_TypeDef *) PSSI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA1 ((BDMA_TypeDef *) BDMA1_BASE)

#define	BDMA1_Channel0 ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)

#define	BDMA1_Channel1 ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)

#define	BDMA1_Channel2 ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)

#define	BDMA1_Channel3 ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)

#define	BDMA1_Channel4 ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)

#define	BDMA1_Channel5 ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)

#define	BDMA1_Channel6 ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)

#define	BDMA1_Channel7 ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)

#define	BDMA2 ((BDMA_TypeDef *) BDMA2_BASE)

#define	BDMA2_Channel0 ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)

#define	BDMA2_Channel1 ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)

#define	BDMA2_Channel2 ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)

#define	BDMA2_Channel3 ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)

#define	BDMA2_Channel4 ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)

#define	BDMA2_Channel5 ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)

#define	BDMA2_Channel6 ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)

#define	BDMA2_Channel7 ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)

#define	RAMECC ((RAMECC_TypeDef *)RAMECC_BASE)

#define	RAMECC_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)

#define	RAMECC_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)

#define	RAMECC_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	DAC2 ((DAC_TypeDef *) DAC2_BASE)

#define	OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

#define	DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

#define	OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

#define	DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

#define	OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

#define	GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	JPEG ((JPEG_TypeDef *) JPGDEC_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	TAMP ((TAMP_TypeDef *) TAMP_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	USART10 ((USART_TypeDef *) USART10_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	UART9 ((USART_TypeDef *) UART9_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	DTS ((DTS_TypeDef *) DTS_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DFSDM1_Filter4 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)

#define	DFSDM1_Filter5 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)

#define	DFSDM1_Filter6 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)

#define	DFSDM1_Filter7 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)

#define	DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)

#define	DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)

#define	DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	PSSI ((PSSI_TypeDef *) PSSI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA1 ((BDMA_TypeDef *) BDMA1_BASE)

#define	BDMA1_Channel0 ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)

#define	BDMA1_Channel1 ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)

#define	BDMA1_Channel2 ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)

#define	BDMA1_Channel3 ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)

#define	BDMA1_Channel4 ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)

#define	BDMA1_Channel5 ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)

#define	BDMA1_Channel6 ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)

#define	BDMA1_Channel7 ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)

#define	BDMA2 ((BDMA_TypeDef *) BDMA2_BASE)

#define	BDMA2_Channel0 ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)

#define	BDMA2_Channel1 ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)

#define	BDMA2_Channel2 ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)

#define	BDMA2_Channel3 ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)

#define	BDMA2_Channel4 ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)

#define	BDMA2_Channel5 ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)

#define	BDMA2_Channel6 ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)

#define	BDMA2_Channel7 ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)

#define	RAMECC ((RAMECC_TypeDef *)RAMECC_BASE)

#define	RAMECC_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)

#define	RAMECC_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)

#define	RAMECC_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	DAC2 ((DAC_TypeDef *) DAC2_BASE)

#define	OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

#define	DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

#define	OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

#define	DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

#define	OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

#define	GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	JPEG ((JPEG_TypeDef *) JPGDEC_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	TAMP ((TAMP_TypeDef *) TAMP_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	USART10 ((USART_TypeDef *) USART10_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	UART9 ((USART_TypeDef *) UART9_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	DTS ((DTS_TypeDef *) DTS_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DFSDM1_Filter4 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)

#define	DFSDM1_Filter5 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)

#define	DFSDM1_Filter6 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)

#define	DFSDM1_Filter7 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)

#define	DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)

#define	DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)

#define	DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	PSSI ((PSSI_TypeDef *) PSSI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	CRYP ((CRYP_TypeDef *) CRYP_BASE)

#define	HASH ((HASH_TypeDef *) HASH_BASE)

#define	HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA1 ((BDMA_TypeDef *) BDMA1_BASE)

#define	BDMA1_Channel0 ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)

#define	BDMA1_Channel1 ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)

#define	BDMA1_Channel2 ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)

#define	BDMA1_Channel3 ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)

#define	BDMA1_Channel4 ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)

#define	BDMA1_Channel5 ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)

#define	BDMA1_Channel6 ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)

#define	BDMA1_Channel7 ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)

#define	BDMA2 ((BDMA_TypeDef *) BDMA2_BASE)

#define	BDMA2_Channel0 ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)

#define	BDMA2_Channel1 ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)

#define	BDMA2_Channel2 ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)

#define	BDMA2_Channel3 ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)

#define	BDMA2_Channel4 ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)

#define	BDMA2_Channel5 ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)

#define	BDMA2_Channel6 ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)

#define	BDMA2_Channel7 ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)

#define	RAMECC ((RAMECC_TypeDef *)RAMECC_BASE)

#define	RAMECC_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)

#define	RAMECC_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)

#define	RAMECC_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	DAC2 ((DAC_TypeDef *) DAC2_BASE)

#define	OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

#define	DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

#define	OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

#define	DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

#define	OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

#define	OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE)

#define	OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)

#define	OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)

#define	OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)

#define	OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)

#define	OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE)

#define	OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)

#define	OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)

#define	OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)

#define	OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)

#define	GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	JPEG ((JPEG_TypeDef *) JPGDEC_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	TAMP ((TAMP_TypeDef *) TAMP_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	USART10 ((USART_TypeDef *) USART10_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	UART9 ((USART_TypeDef *) UART9_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	DTS ((DTS_TypeDef *) DTS_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DFSDM1_Filter4 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)

#define	DFSDM1_Filter5 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)

#define	DFSDM1_Filter6 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)

#define	DFSDM1_Filter7 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)

#define	DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)

#define	DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)

#define	DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	PSSI ((PSSI_TypeDef *) PSSI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	CRYP ((CRYP_TypeDef *) CRYP_BASE)

#define	HASH ((HASH_TypeDef *) HASH_BASE)

#define	HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA1 ((BDMA_TypeDef *) BDMA1_BASE)

#define	BDMA1_Channel0 ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)

#define	BDMA1_Channel1 ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)

#define	BDMA1_Channel2 ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)

#define	BDMA1_Channel3 ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)

#define	BDMA1_Channel4 ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)

#define	BDMA1_Channel5 ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)

#define	BDMA1_Channel6 ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)

#define	BDMA1_Channel7 ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)

#define	BDMA2 ((BDMA_TypeDef *) BDMA2_BASE)

#define	BDMA2_Channel0 ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)

#define	BDMA2_Channel1 ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)

#define	BDMA2_Channel2 ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)

#define	BDMA2_Channel3 ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)

#define	BDMA2_Channel4 ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)

#define	BDMA2_Channel5 ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)

#define	BDMA2_Channel6 ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)

#define	BDMA2_Channel7 ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)

#define	RAMECC ((RAMECC_TypeDef *)RAMECC_BASE)

#define	RAMECC_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)

#define	RAMECC_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)

#define	RAMECC_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	DAC2 ((DAC_TypeDef *) DAC2_BASE)

#define	OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

#define	DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

#define	OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

#define	DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

#define	OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

#define	OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE)

#define	OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)

#define	OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)

#define	OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)

#define	OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)

#define	OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE)

#define	OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)

#define	OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)

#define	OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)

#define	OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)

#define	GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	JPEG ((JPEG_TypeDef *) JPGDEC_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	TAMP ((TAMP_TypeDef *) TAMP_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	USART10 ((USART_TypeDef *) USART10_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	UART9 ((USART_TypeDef *) UART9_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	DTS ((DTS_TypeDef *) DTS_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DFSDM1_Filter4 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)

#define	DFSDM1_Filter5 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)

#define	DFSDM1_Filter6 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)

#define	DFSDM1_Filter7 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)

#define	DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)

#define	DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)

#define	DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	PSSI ((PSSI_TypeDef *) PSSI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	CRYP ((CRYP_TypeDef *) CRYP_BASE)

#define	HASH ((HASH_TypeDef *) HASH_BASE)

#define	HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA1 ((BDMA_TypeDef *) BDMA1_BASE)

#define	BDMA1_Channel0 ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)

#define	BDMA1_Channel1 ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)

#define	BDMA1_Channel2 ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)

#define	BDMA1_Channel3 ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)

#define	BDMA1_Channel4 ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)

#define	BDMA1_Channel5 ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)

#define	BDMA1_Channel6 ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)

#define	BDMA1_Channel7 ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)

#define	BDMA2 ((BDMA_TypeDef *) BDMA2_BASE)

#define	BDMA2_Channel0 ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)

#define	BDMA2_Channel1 ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)

#define	BDMA2_Channel2 ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)

#define	BDMA2_Channel3 ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)

#define	BDMA2_Channel4 ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)

#define	BDMA2_Channel5 ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)

#define	BDMA2_Channel6 ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)

#define	BDMA2_Channel7 ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)

#define	RAMECC ((RAMECC_TypeDef *)RAMECC_BASE)

#define	RAMECC_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)

#define	RAMECC_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)

#define	RAMECC_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	DAC2 ((DAC_TypeDef *) DAC2_BASE)

#define	OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

#define	DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

#define	OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

#define	DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

#define	OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

#define	OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE)

#define	OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)

#define	OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)

#define	OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)

#define	OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)

#define	OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE)

#define	OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)

#define	OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)

#define	OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)

#define	OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)

#define	GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	JPEG ((JPEG_TypeDef *) JPGDEC_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

#define	TIM2 ((TIM_TypeDef *) TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *) TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *) TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *) TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *) TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *) TIM7_BASE)

#define	TIM13 ((TIM_TypeDef *) TIM13_BASE)

#define	TIM14 ((TIM_TypeDef *) TIM14_BASE)

#define	VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)

#define	RTC ((RTC_TypeDef *) RTC_BASE)

#define	TAMP ((TAMP_TypeDef *) TAMP_BASE)

#define	WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)

#define	IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)

#define	SPI2 ((SPI_TypeDef *) SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *) SPI3_BASE)

#define	SPI4 ((SPI_TypeDef *) SPI4_BASE)

#define	SPI5 ((SPI_TypeDef *) SPI5_BASE)

#define	SPI6 ((SPI_TypeDef *) SPI6_BASE)

#define	USART2 ((USART_TypeDef *) USART2_BASE)

#define	USART3 ((USART_TypeDef *) USART3_BASE)

#define	USART6 ((USART_TypeDef *) USART6_BASE)

#define	USART10 ((USART_TypeDef *) USART10_BASE)

#define	UART7 ((USART_TypeDef *) UART7_BASE)

#define	UART8 ((USART_TypeDef *) UART8_BASE)

#define	UART9 ((USART_TypeDef *) UART9_BASE)

#define	CRS ((CRS_TypeDef *) CRS_BASE)

#define	UART4 ((USART_TypeDef *) UART4_BASE)

#define	UART5 ((USART_TypeDef *) UART5_BASE)

#define	I2C1 ((I2C_TypeDef *) I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *) I2C2_BASE)

#define	I2C3 ((I2C_TypeDef *) I2C3_BASE)

#define	I2C4 ((I2C_TypeDef *) I2C4_BASE)

#define	FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

#define	FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

#define	FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

#define	CEC ((CEC_TypeDef *) CEC_BASE)

#define	LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)

#define	PWR ((PWR_TypeDef *) PWR_BASE)

#define	DAC1 ((DAC_TypeDef *) DAC1_BASE)

#define	LPUART1 ((USART_TypeDef *) LPUART1_BASE)

#define	SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)

#define	LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)

#define	LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)

#define	DTS ((DTS_TypeDef *) DTS_BASE)

#define	SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)

#define	COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)

#define	COMP1 ((COMP_TypeDef *) COMP1_BASE)

#define	COMP2 ((COMP_TypeDef *) COMP2_BASE)

#define	COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)

#define	OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)

#define	OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)

#define	OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)

#define	EXTI ((EXTI_TypeDef *) EXTI_BASE)

#define	EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

#define	TIM1 ((TIM_TypeDef *) TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *) SPI1_BASE)

#define	TIM8 ((TIM_TypeDef *) TIM8_BASE)

#define	USART1 ((USART_TypeDef *) USART1_BASE)

#define	TIM12 ((TIM_TypeDef *) TIM12_BASE)

#define	TIM15 ((TIM_TypeDef *) TIM15_BASE)

#define	TIM16 ((TIM_TypeDef *) TIM16_BASE)

#define	TIM17 ((TIM_TypeDef *) TIM17_BASE)

#define	SAI1 ((SAI_TypeDef *) SAI1_BASE)

#define	SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

#define	SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

#define	SAI2 ((SAI_TypeDef *) SAI2_BASE)

#define	SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

#define	SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

#define	SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

#define	DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

#define	DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

#define	DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

#define	DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

#define	DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

#define	DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

#define	DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

#define	DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

#define	DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

#define	DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

#define	DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

#define	DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

#define	DFSDM1_Filter4 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)

#define	DFSDM1_Filter5 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)

#define	DFSDM1_Filter6 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)

#define	DFSDM1_Filter7 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)

#define	DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)

#define	DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)

#define	DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)

#define	DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)

#define	DCMI ((DCMI_TypeDef *) DCMI_BASE)

#define	PSSI ((PSSI_TypeDef *) PSSI_BASE)

#define	RCC ((RCC_TypeDef *) RCC_BASE)

#define	FLASH ((FLASH_TypeDef *) FLASH_R_BASE)

#define	CRC ((CRC_TypeDef *) CRC_BASE)

#define	GPIOA ((GPIO_TypeDef *) GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *) GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *) GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *) GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *) GPIOE_BASE)

#define	GPIOF ((GPIO_TypeDef *) GPIOF_BASE)

#define	GPIOG ((GPIO_TypeDef *) GPIOG_BASE)

#define	GPIOH ((GPIO_TypeDef *) GPIOH_BASE)

#define	GPIOI ((GPIO_TypeDef *) GPIOI_BASE)

#define	GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)

#define	GPIOK ((GPIO_TypeDef *) GPIOK_BASE)

#define	ADC1 ((ADC_TypeDef *) ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *) ADC2_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

#define	CRYP ((CRYP_TypeDef *) CRYP_BASE)

#define	HASH ((HASH_TypeDef *) HASH_BASE)

#define	HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

#define	RNG ((RNG_TypeDef *) RNG_BASE)

#define	SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)

#define	DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

#define	BDMA1 ((BDMA_TypeDef *) BDMA1_BASE)

#define	BDMA1_Channel0 ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)

#define	BDMA1_Channel1 ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)

#define	BDMA1_Channel2 ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)

#define	BDMA1_Channel3 ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)

#define	BDMA1_Channel4 ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)

#define	BDMA1_Channel5 ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)

#define	BDMA1_Channel6 ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)

#define	BDMA1_Channel7 ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)

#define	BDMA2 ((BDMA_TypeDef *) BDMA2_BASE)

#define	BDMA2_Channel0 ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)

#define	BDMA2_Channel1 ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)

#define	BDMA2_Channel2 ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)

#define	BDMA2_Channel3 ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)

#define	BDMA2_Channel4 ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)

#define	BDMA2_Channel5 ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)

#define	BDMA2_Channel6 ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)

#define	BDMA2_Channel7 ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)

#define	RAMECC ((RAMECC_TypeDef *)RAMECC_BASE)

#define	RAMECC_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)

#define	RAMECC_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)

#define	RAMECC_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)

#define	DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

#define	DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

#define	DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

#define	DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

#define	DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

#define	DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

#define	DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

#define	DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

#define	DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

#define	DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

#define	DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

#define	DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

#define	DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

#define	DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

#define	DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

#define	DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

#define	DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

#define	DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

#define	DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

#define	DMA2 ((DMA_TypeDef *) DMA2_BASE)

#define	DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

#define	DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

#define	DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

#define	DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

#define	DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

#define	DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

#define	DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

#define	DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

#define	DMA1 ((DMA_TypeDef *) DMA1_BASE)

#define	DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

#define	DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

#define	DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

#define	DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

#define	DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

#define	DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

#define	DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

#define	DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

#define	DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

#define	DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

#define	DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

#define	DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

#define	DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

#define	DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

#define	DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

#define	DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

#define	DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

#define	DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

#define	DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

#define	DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

#define	DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

#define	DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

#define	DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

#define	DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

#define	DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

#define	DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

#define	DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

#define	DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

#define	DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

#define	DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

#define	DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

#define	DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

#define	DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

#define	DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)

#define	DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

#define	FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

#define	FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

#define	FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

#define	FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

#define	FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

#define	DAC2 ((DAC_TypeDef *) DAC2_BASE)

#define	OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

#define	DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

#define	OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

#define	DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

#define	OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

#define	OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE)

#define	OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)

#define	OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)

#define	OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)

#define	OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)

#define	OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE)

#define	OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)

#define	OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)

#define	OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)

#define	OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)

#define	GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE)

#define	SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)

#define	DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)

#define	JPEG ((JPEG_TypeDef *) JPGDEC_BASE)

#define	HSEM ((HSEM_TypeDef *) HSEM_BASE)

#define	HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

#define	LTDC ((LTDC_TypeDef *)LTDC_BASE)

#define	LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

#define	LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

#define	MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)

#define	MDMA ((MDMA_TypeDef *)MDMA_BASE)

#define	MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

#define	MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

#define	MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

#define	MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

#define	MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

#define	MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

#define	MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

#define	MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

#define	MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

#define	MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

#define	MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

#define	MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

#define	MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

#define	MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

#define	MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

#define	MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

#define	USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

#define	USB_OTG_HS USB1_OTG_HS

#define	USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE

#define	GPV ((GPV_TypeDef *) GPV_BASE)

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