PWR Exported Macro

Macros
#define	__HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)
	Configure the main internal regulator output voltage.
#define	__HAL_PWR_GET_FLAG(__FLAG__)
	Check PWR flags are set or not.
#define	__HAL_PWR_GET_WAKEUPFLAG(__FLAG__)   ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)
	Check PWR wake up flags are set or not.
#define	__HAL_PWR_CLEAR_FLAG(__FLAG__)   SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)
	Clear CPU PWR flags.
#define	__HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__)   SET_BIT(PWR->WKUPCR, (__FLAG__))
	Clear PWR wake up flags.
#define	__HAL_PWR_PVD_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
	Enable the PVD EXTI Line 16.
#define	__HAL_PWR_PVD_EXTI_DISABLE_IT()   CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
	Disable the PVD EXTI Line 16.
#define	__HAL_PWR_PVD_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
	Enable event on PVD EXTI Line 16.
#define	__HAL_PWR_PVD_EXTI_DISABLE_EVENT()   CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
	Disable event on PVD EXTI Line 16.
#define	__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
	Enable the PVD Rising Interrupt Trigger.
#define	__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
	Disable the PVD Rising Interrupt Trigger.
#define	__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
	Enable the PVD Falling Interrupt Trigger.
#define	__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()   CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
	Disable the PVD Falling Interrupt Trigger.
#define	__HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()
	Enable the PVD Rising & Falling Interrupt Trigger.
#define	__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()
	Disable the PVD Rising & Falling Interrupt Trigger.
#define	__HAL_PWR_PVD_EXTI_GET_FLAG()   ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
	Check whether the specified PVD EXTI interrupt flag is set or not.
#define	__HAL_PWR_PVD_EXTI_CLEAR_FLAG()   SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)
	Clear the PVD EXTI flag.
#define	__HAL_PWR_PVD_EXTI_GENERATE_SWIT()   SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
	Generates a Software interrupt on PVD EXTI line.

Detailed Description

Macro Definition Documentation

__HAL_PWR_CLEAR_FLAG

#define __HAL_PWR_CLEAR_FLAG

(

__FLAG__

)

SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)

Clear CPU PWR flags.

Parameters

__FLAG__

: Specifies the flag to clear.

Note

This parameter is not used for the STM32H7 family and is kept as parameter just to maintain compatibility with other families.

This macro clear all CPU flags. For single core devices except STM32H7Axxx and STM32H7Bxxx, CPU flags are STOPF, SBF, SBF_D1 and SBF_D2. For STM32H7Axxx and STM32H7Bxxx lines, CPU flags are STOPF and SBF.

Return values

None.

__HAL_PWR_CLEAR_WAKEUPFLAG

#define __HAL_PWR_CLEAR_WAKEUPFLAG

(

__FLAG__

)

SET_BIT(PWR->WKUPCR, (__FLAG__))

Clear PWR wake up flags.

Parameters

__FLAG__

: Specifies the wake up flag to be cleared. This parameter can be one of the following values : PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag. PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag. PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag. PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.

Note

The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices that support GPIOI port.

Return values

None.

__HAL_PWR_GET_FLAG

#define __HAL_PWR_GET_FLAG

(

__FLAG__

)

Value:

(((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\
 ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\
 ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\
 ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\
 ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\
 ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\
 ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\
 ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\
 ((__FLAG__) == PWR_FLAG_MMCVDO)    ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\
 ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\
 ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\
 ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\
 ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\
 ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))

Check PWR flags are set or not.

Parameters

__FLAG__

: Specifies the flag to check. This parameter can be one of the following values: PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD is enabled by the HAL_PWR_EnablePVD() function. The PVD is stopped by STANDBY mode. For this reason, this bit is equal to 0 after STANDBY or reset until the PVDE bit is set. PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD is enabled by the HAL_PWREx_EnableAVD() function. The AVD is stopped by STANDBY mode. For this reason, this bit is equal to 0 after STANDBY or reset until the AVDE bit is set. PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator voltage scaling output selection is ready. PWR_FLAG_BRR : Backup regulator ready flag. This bit is not reset when the device wakes up from STANDBY mode or by a system reset or power-on reset. PWR_FLAG_VOSRDY : This flag indicates that the Regulator voltage scaling output selection is ready. mode or by a system reset or power-on reset. PWR_FLAG_USB33RDY : This flag indicates that the USB supply from regulator is ready. PWR_FLAG_TEMPH : This flag indicates that the temperature equal or above high threshold level. PWR_FLAG_TEMPL : This flag indicates that the temperature equal or below low threshold level. PWR_FLAG_VBATH : This flag indicates that VBAT level equal or above high threshold level. PWR_FLAG_VBATL : This flag indicates that VBAT level equal or below low threshold level. PWR_FLAG_STOP : This flag indicates that the system entered in STOP mode. PWR_FLAG_SB : This flag indicates that the system entered in STANDBY mode. PWR_FLAG_SB_D1 : This flag indicates that the D1 domain entered in STANDBY mode. PWR_FLAG_SB_D2 : This flag indicates that the D2 domain entered in STANDBY mode. PWR_FLAG2_STOP : This flag indicates that the system entered in STOP mode. PWR_FLAG2_SB : This flag indicates that the system entered in STANDBY mode. PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain entered in STANDBY mode. PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain entered in STANDBY mode. PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes up with hold. PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes up with hold. PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS External supply is sready. PWR_FLAG_SCUEN : This flag indicates that the supply configuration update is enabled. PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is above or equal to 1.2 V.

Note

The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR, PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL, PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags are used for all H7 family lines. The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2, PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7 dual core lines. The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7 family except STM32H7Axxx and STM32H7Bxxx lines. The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and STM32H7Bxxx lines. The PWR_FLAG_SCUEN flag is used for devices that support only LDO regulator. The PWR_FLAG_SMPSEXTRDY flag is used for devices that support LDO and SMPS regulators.

Return values

The	(FLAG) state (TRUE or FALSE).

__HAL_PWR_GET_WAKEUPFLAG

#define __HAL_PWR_GET_WAKEUPFLAG

(

__FLAG__

)

((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)

Check PWR wake up flags are set or not.

Parameters

__FLAG__

specifies the wake up flag to check. This parameter can be one of the following values: PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag. PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag. PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag. PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag. PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag. PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.

Note

The PWR_FLAG_WKUP3 and PWR_FLAG_WKUP5 are available only for devices that support GPIOI port.

Return values

The	(FLAG) state (TRUE or FALSE).

__HAL_PWR_PVD_EXTI_CLEAR_FLAG

#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG

(

)

SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)

Clear the PVD EXTI flag.

Return values

None.

__HAL_PWR_PVD_EXTI_DISABLE_EVENT

#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT

(

)

CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)

Disable event on PVD EXTI Line 16.

Return values

None.

__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE

#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE

(

)

CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)

Disable the PVD Falling Interrupt Trigger.

Return values

None.

__HAL_PWR_PVD_EXTI_DISABLE_IT

#define __HAL_PWR_PVD_EXTI_DISABLE_IT

(

)

CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)

Disable the PVD EXTI Line 16.

Return values

None.

__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE

(

)

CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)

Disable the PVD Rising Interrupt Trigger.

Return values

None.

__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE

#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE

(

)

Value:

do {                                                     \
      __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();          \
      __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();         \
} while(0);

Disable the PVD Rising & Falling Interrupt Trigger.

Return values

None.

__HAL_PWR_PVD_EXTI_ENABLE_EVENT

#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT

(

)

SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)

Enable event on PVD EXTI Line 16.

Return values

None.

__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE

#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE

(

)

SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)

Enable the PVD Falling Interrupt Trigger.

Return values

None.

__HAL_PWR_PVD_EXTI_ENABLE_IT

#define __HAL_PWR_PVD_EXTI_ENABLE_IT

(

)

SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)

Enable the PVD EXTI Line 16.

Return values

None.

__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE

(

)

SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)

Enable the PVD Rising Interrupt Trigger.

Return values

None.

__HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE

#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE

(

)

Value:

do {                                                    \
      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();          \
      __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();         \
} while(0);

Enable the PVD Rising & Falling Interrupt Trigger.

Return values

None.

__HAL_PWR_PVD_EXTI_GENERATE_SWIT

#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT

(

)

SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)

Generates a Software interrupt on PVD EXTI line.

Return values

None.

__HAL_PWR_PVD_EXTI_GET_FLAG

#define __HAL_PWR_PVD_EXTI_GET_FLAG

(

)

((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)

Check whether the specified PVD EXTI interrupt flag is set or not.

Return values

EXTI	PVD Line Status.

__HAL_PWR_VOLTAGESCALING_CONFIG

#define __HAL_PWR_VOLTAGESCALING_CONFIG

(

__REGULATOR__

)

Value:

do {                                                                           \
      __IO uint32_t tmpreg = 0x00;                                             \
      /* Configure the Voltage Scaling */                                      \
      MODIFY_REG (PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__));                   \
      /* Delay after setting the voltage scaling */                            \
      tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                              \
      UNUSED(tmpreg);                                                          \
} while(0)

Configure the main internal regulator output voltage.

Parameters

__REGULATOR__

: Specifies the regulator output voltage to achieve a trade-off between performance and power consumption when the device does not operate at the maximum frequency (refer to the datasheet for more details). This parameter can be one of the following values: PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output Scale 0 mode. PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output Scale 1 mode. PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output Scale 2 mode. PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output Scale 3 mode.

Note

For STM32H74x and STM32H75x lines, configuring Voltage Scale 0 is only possible when Vcore is supplied from LDO (Low DropOut). The SYSCFG Clock must be enabled through __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage Scale 0 using __HAL_PWR_VOLTAGESCALING_CONFIG(). Transition to Voltage Scale 0 is only possible when the system is already in Voltage Scale 1. Transition from Voltage Scale 0 is only possible to Voltage Scale 1 then once in Voltage Scale 1 it is possible to switch to another voltage scale. After each regulator voltage setting, wait on VOSRDY flag to be set using macro __HAL_PWR_GET_FLAG(). To enter low power mode , and if current regulator voltage is Voltage Scale 0 then first switch to Voltage Scale 1 before entering low power mode.

Return values

None.