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#define | ERC32_INTERRUPT_MASKED_ERRORS 1 |
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#define | ERC32_INTERRUPT_EXTERNAL_1 2 |
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#define | ERC32_INTERRUPT_EXTERNAL_2 3 |
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#define | ERC32_INTERRUPT_UART_A_RX_TX 4 |
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#define | ERC32_INTERRUPT_UART_B_RX_TX 5 |
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#define | ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR 6 |
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#define | ERC32_INTERRUPT_UART_ERROR 7 |
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#define | ERC32_INTERRUPT_DMA_ACCESS_ERROR 8 |
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#define | ERC32_INTERRUPT_DMA_TIMEOUT 9 |
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#define | ERC32_INTERRUPT_EXTERNAL_3 10 |
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#define | ERC32_INTERRUPT_EXTERNAL_4 11 |
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#define | ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER 12 |
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#define | ERC32_INTERRUPT_REAL_TIME_CLOCK 13 |
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#define | ERC32_INTERRUPT_EXTERNAL_5 14 |
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#define | ERC32_INTERRUPT_WATCHDOG_TIMEOUT 15 |
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#define | ERC32_TRAP_TYPE(_source) SPARC_INTERRUPT_SOURCE_TO_TRAP( _source ) |
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#define | ERC32_TRAP_SOURCE(_trap) SPARC_INTERRUPT_TRAP_TO_SOURCE( _trap ) |
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#define | ERC32_Is_MEC_Trap(_trap) SPARC_IS_INTERRUPT_TRAP( _trap ) |
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#define | ERC32_CONFIGURATION_POWER_DOWN_MASK 0x00000001 |
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#define | ERC32_CONFIGURATION_POWER_DOWN_ALLOWED 0x00000001 |
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#define | ERC32_CONFIGURATION_POWER_DOWN_DISABLED 0x00000000 |
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#define | ERC32_CONFIGURATION_SOFTWARE_RESET_MASK 0x00000002 |
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#define | ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED 0x00000002 |
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#define | ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED 0x00000000 |
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#define | ERC32_CONFIGURATION_BUS_TIMEOUT_MASK 0x00000004 |
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#define | ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED 0x00000004 |
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#define | ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED 0x00000000 |
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#define | ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK 0x00000008 |
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#define | ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED 0x00000008 |
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#define | ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED 0x00000000 |
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#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001C00 |
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#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K ( 0 << 10 ) |
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#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K ( 1 << 10 ) |
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#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB ( 2 << 10 ) |
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#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB ( 3 << 10 ) |
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#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB ( 4 << 10 ) |
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#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB ( 5 << 10 ) |
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#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB ( 6 << 10 ) |
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#define | ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB ( 7 << 10 ) |
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#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x001C0000 |
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#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K ( 0 << 18 ) |
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#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K ( 1 << 18 ) |
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#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K ( 2 << 18 ) |
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#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M ( 3 << 18 ) |
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#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M ( 4 << 18 ) |
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#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M ( 5 << 18 ) |
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#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M ( 6 << 18 ) |
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#define | ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M ( 7 << 18 ) |
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#define | ERC32_MEC_TIMER_CONTROL_GCR 0x00000001 /* 1 = reload at 0 */ |
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#define | ERC32_MEC_TIMER_CONTROL_GCL 0x00000002 /* 1 = load and start */ |
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#define | ERC32_MEC_TIMER_CONTROL_GSE 0x00000004 /* 1 = enable counting */ |
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#define | ERC32_MEC_TIMER_CONTROL_GSL 0x00000008 /* 1 = load scalar and start*/ |
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#define | ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100 /* 1 = reload at 0 */ |
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#define | ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200 /* 1 = load and start */ |
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#define | ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400 /* 1 = enable counting */ |
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#define | ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800 /* 1 = load scalar and start*/ |
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#define | ERC32_MEC_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ |
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#define | ERC32_MEC_UART_STATUS_DR 0x00000001 /* Data Ready */ |
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#define | ERC32_MEC_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ |
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#define | ERC32_MEC_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ |
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#define | ERC32_MEC_UART_STATUS_FE 0x00000010 /* RX Framing Error */ |
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#define | ERC32_MEC_UART_STATUS_PE 0x00000020 /* RX Parity Error */ |
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#define | ERC32_MEC_UART_STATUS_OE 0x00000040 /* RX Overrun Error */ |
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#define | ERC32_MEC_UART_STATUS_CU 0x00000080 /* Clear Errors */ |
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#define | ERC32_MEC_UART_STATUS_TXE 0x00000006 /* TX Empty */ |
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#define | ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */ |
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#define | ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */ |
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#define | ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */ |
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#define | ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */ |
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#define | ERC32_MEC_UART_STATUS_DRA (ERC32_MEC_UART_STATUS_DR << 0) |
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#define | ERC32_MEC_UART_STATUS_TSEA (ERC32_MEC_UART_STATUS_TSE << 0) |
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#define | ERC32_MEC_UART_STATUS_THEA (ERC32_MEC_UART_STATUS_THE << 0) |
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#define | ERC32_MEC_UART_STATUS_FEA (ERC32_MEC_UART_STATUS_FE << 0) |
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#define | ERC32_MEC_UART_STATUS_PEA (ERC32_MEC_UART_STATUS_PE << 0) |
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#define | ERC32_MEC_UART_STATUS_OEA (ERC32_MEC_UART_STATUS_OE << 0) |
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#define | ERC32_MEC_UART_STATUS_CUA (ERC32_MEC_UART_STATUS_CU << 0) |
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#define | ERC32_MEC_UART_STATUS_TXEA (ERC32_MEC_UART_STATUS_TXE << 0) |
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#define | ERC32_MEC_UART_STATUS_DRB (ERC32_MEC_UART_STATUS_DR << 16) |
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#define | ERC32_MEC_UART_STATUS_TSEB (ERC32_MEC_UART_STATUS_TSE << 16) |
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#define | ERC32_MEC_UART_STATUS_THEB (ERC32_MEC_UART_STATUS_THE << 16) |
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#define | ERC32_MEC_UART_STATUS_FEB (ERC32_MEC_UART_STATUS_FE << 16) |
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#define | ERC32_MEC_UART_STATUS_PEB (ERC32_MEC_UART_STATUS_PE << 16) |
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#define | ERC32_MEC_UART_STATUS_OEB (ERC32_MEC_UART_STATUS_OE << 16) |
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#define | ERC32_MEC_UART_STATUS_CUB (ERC32_MEC_UART_STATUS_CU << 16) |
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#define | ERC32_MEC_UART_STATUS_TXEB (ERC32_MEC_UART_STATUS_TXE << 16) |
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#define | ERC32_Clear_interrupt(_source) |
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#define | ERC32_Force_interrupt(_source) |
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#define | ERC32_Is_interrupt_pending(_source) (ERC32_MEC.Interrupt_Pending & (1 << (_source))) |
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#define | ERC32_Is_interrupt_masked(_source) (ERC32_MEC.Interrupt_Mask & (1 << (_source))) |
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#define | ERC32_Mask_interrupt(_source) |
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#define | ERC32_Unmask_interrupt(_source) |
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#define | ERC32_Disable_interrupt(_source, _previous) |
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#define | ERC32_Restore_interrupt(_source, _previous) |
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#define | BSP_Clear_interrupt(_source) ERC32_Clear_interrupt(_source) |
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#define | BSP_Force_interrupt(_source) ERC32_Force_interrupt(_source) |
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#define | BSP_Clear_forced_interrupt(_source) |
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#define | BSP_Is_interrupt_pending(_source) ERC32_Is_interrupt_pending(_source) |
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#define | BSP_Is_interrupt_forced(_source) (ERC32_MEC.Interrupt_Force & (1 << (_source))) |
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#define | BSP_Is_interrupt_masked(_source) ERC32_Is_interrupt_masked(_source) |
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#define | BSP_Unmask_interrupt(_source) ERC32_Unmask_interrupt(_source) |
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#define | BSP_Mask_interrupt(_source) ERC32_Mask_interrupt(_source) |
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#define | BSP_Disable_interrupt(_source, _previous) ERC32_Disable_interrupt(_source, _prev) |
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#define | BSP_Restore_interrupt(_source, _previous) ERC32_Restore_interrupt(_source, _previous) |
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#define | BSP_Cpu_Is_interrupt_masked(_source, _cpu) BSP_Is_interrupt_masked(_source) |
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#define | BSP_Cpu_Unmask_interrupt(_source, _cpu) BSP_Unmask_interrupt(_source) |
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#define | BSP_Cpu_Mask_interrupt(_source, _cpu) BSP_Mask_interrupt(_source) |
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#define | BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) BSP_Disable_interrupt(_source, _prev) |
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#define | BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) BSP_Cpu_Restore_interrupt(_source, _previous) |
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#define | ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000001 |
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#define | ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 |
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#define | ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER 0x00000002 |
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#define | ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING 0x00000004 |
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#define | ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 |
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#define | ERC32_MEC_TIMER_COUNTER_LOAD_SCALER 0x00000008 |
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#define | ERC32_MEC_TIMER_COUNTER_RELOAD_MASK 0x00000001 |
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#define | ERC32_MEC_TIMER_COUNTER_ENABLE_MASK 0x00000004 |
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#define | ERC32_MEC_TIMER_COUNTER_DEFINED_MASK 0x0000000F |
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#define | ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000005 |
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#define | ERC32_MEC_Set_General_Purpose_Timer_Control(_value) |
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#define | ERC32_MEC_Get_General_Purpose_Timer_Control(_value) |
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#define | ERC32_MEC_Set_Real_Time_Clock_Timer_Control(_value) |
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#define | ERC32_MEC_Get_Real_Time_Clock_Timer_Control(_value) |
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Contains information pertaining to the ERC32.