42#ifndef _INCLUDE_ERC32_h
43#define _INCLUDE_ERC32_h
59#define ERC32_INTERRUPT_MASKED_ERRORS 1
60#define ERC32_INTERRUPT_EXTERNAL_1 2
61#define ERC32_INTERRUPT_EXTERNAL_2 3
62#define ERC32_INTERRUPT_UART_A_RX_TX 4
63#define ERC32_INTERRUPT_UART_B_RX_TX 5
64#define ERC32_INTERRUPT_CORRECTABLE_MEMORY_ERROR 6
65#define ERC32_INTERRUPT_UART_ERROR 7
66#define ERC32_INTERRUPT_DMA_ACCESS_ERROR 8
67#define ERC32_INTERRUPT_DMA_TIMEOUT 9
68#define ERC32_INTERRUPT_EXTERNAL_3 10
69#define ERC32_INTERRUPT_EXTERNAL_4 11
70#define ERC32_INTERRUPT_GENERAL_PURPOSE_TIMER 12
71#define ERC32_INTERRUPT_REAL_TIME_CLOCK 13
72#define ERC32_INTERRUPT_EXTERNAL_5 14
73#define ERC32_INTERRUPT_WATCHDOG_TIMEOUT 15
86#define ERC32_TRAP_TYPE( _source ) SPARC_INTERRUPT_SOURCE_TO_TRAP( _source )
88#define ERC32_TRAP_SOURCE( _trap ) SPARC_INTERRUPT_TRAP_TO_SOURCE( _trap )
90#define ERC32_Is_MEC_Trap( _trap ) SPARC_IS_INTERRUPT_TRAP( _trap )
103 volatile uint32_t Control;
104 volatile uint32_t Software_Reset;
105 volatile uint32_t Power_Down;
106 volatile uint32_t Unimplemented_0;
107 volatile uint32_t Memory_Configuration;
108 volatile uint32_t IO_Configuration;
109 volatile uint32_t Wait_State_Configuration;
110 volatile uint32_t Unimplemented_1;
111 volatile uint32_t Memory_Access_0;
112 volatile uint32_t Memory_Access_1;
113 volatile uint32_t Unimplemented_2[ 7 ];
114 volatile uint32_t Interrupt_Shape;
115 volatile uint32_t Interrupt_Pending;
116 volatile uint32_t Interrupt_Mask;
117 volatile uint32_t Interrupt_Clear;
118 volatile uint32_t Interrupt_Force;
119 volatile uint32_t Unimplemented_3[ 2 ];
121 volatile uint32_t Watchdog_Program_and_Timeout_Acknowledge;
122 volatile uint32_t Watchdog_Trap_Door_Set;
123 volatile uint32_t Unimplemented_4[ 6 ];
124 volatile uint32_t Real_Time_Clock_Counter;
125 volatile uint32_t Real_Time_Clock_Scalar;
126 volatile uint32_t General_Purpose_Timer_Counter;
127 volatile uint32_t General_Purpose_Timer_Scalar;
128 volatile uint32_t Unimplemented_5[ 2 ];
130 volatile uint32_t Unimplemented_6;
131 volatile uint32_t System_Fault_Status;
132 volatile uint32_t First_Failing_Address;
133 volatile uint32_t First_Failing_Data;
134 volatile uint32_t First_Failing_Syndrome_and_Check_Bits;
135 volatile uint32_t Error_and_Reset_Status;
136 volatile uint32_t Error_Mask;
137 volatile uint32_t Unimplemented_7[ 2 ];
138 volatile uint32_t Debug_Control;
139 volatile uint32_t Breakpoint;
140 volatile uint32_t Watchpoint;
141 volatile uint32_t Unimplemented_8;
142 volatile uint32_t Test_Control;
143 volatile uint32_t Test_Data;
144 volatile uint32_t Unimplemented_9[ 2 ];
145 volatile uint32_t UART_Channel_A;
146 volatile uint32_t UART_Channel_B;
147 volatile uint32_t UART_Status;
163#define ERC32_MEC_CONTROL_OFFSET 0x00
164#define ERC32_MEC_SOFTWARE_RESET_OFFSET 0x04
165#define ERC32_MEC_POWER_DOWN_OFFSET 0x08
166#define ERC32_MEC_UNIMPLEMENTED_0_OFFSET 0x0C
167#define ERC32_MEC_MEMORY_CONFIGURATION_OFFSET 0x10
168#define ERC32_MEC_IO_CONFIGURATION_OFFSET 0x14
169#define ERC32_MEC_WAIT_STATE_CONFIGURATION_OFFSET 0x18
170#define ERC32_MEC_UNIMPLEMENTED_1_OFFSET 0x1C
171#define ERC32_MEC_MEMORY_ACCESS_0_OFFSET 0x20
172#define ERC32_MEC_MEMORY_ACCESS_1_OFFSET 0x24
173#define ERC32_MEC_UNIMPLEMENTED_2_OFFSET 0x28
174#define ERC32_MEC_INTERRUPT_SHAPE_OFFSET 0x44
175#define ERC32_MEC_INTERRUPT_PENDING_OFFSET 0x48
176#define ERC32_MEC_INTERRUPT_MASK_OFFSET 0x4C
177#define ERC32_MEC_INTERRUPT_CLEAR_OFFSET 0x50
178#define ERC32_MEC_INTERRUPT_FORCE_OFFSET 0x54
179#define ERC32_MEC_UNIMPLEMENTED_3_OFFSET 0x58
180#define ERC32_MEC_WATCHDOG_PROGRAM_AND_TIMEOUT_ACKNOWLEDGE_OFFSET 0x60
181#define ERC32_MEC_WATCHDOG_TRAP_DOOR_SET_OFFSET 0x64
182#define ERC32_MEC_UNIMPLEMENTED_4_OFFSET 0x6C
183#define ERC32_MEC_REAL_TIME_CLOCK_COUNTER_OFFSET 0x80
184#define ERC32_MEC_REAL_TIME_CLOCK_SCALAR_OFFSET 0x84
185#define ERC32_MEC_GENERAL_PURPOSE_TIMER_COUNTER_OFFSET 0x88
186#define ERC32_MEC_GENERAL_PURPOSE_TIMER_SCALAR_OFFSET 0x8C
187#define ERC32_MEC_UNIMPLEMENTED_5_OFFSET 0x90
188#define ERC32_MEC_TIMER_CONTROL_OFFSET 0x98
189#define ERC32_MEC_UNIMPLEMENTED_6_OFFSET 0x9C
190#define ERC32_MEC_SYSTEM_FAULT_STATUS_OFFSET 0xA0
191#define ERC32_MEC_FIRST_FAILING_ADDRESS_OFFSET 0xA4
192#define ERC32_MEC_FIRST_FAILING_DATA_OFFSET 0xA8
193#define ERC32_MEC_FIRST_FAILING_SYNDROME_AND_CHECK_BITS_OFFSET 0xAC
194#define ERC32_MEC_ERROR_AND_RESET_STATUS_OFFSET 0xB0
195#define ERC32_MEC_ERROR_MASK_OFFSET 0xB4
196#define ERC32_MEC_UNIMPLEMENTED_7_OFFSET 0xB8
197#define ERC32_MEC_DEBUG_CONTROL_OFFSET 0xC0
198#define ERC32_MEC_BREAKPOINT_OFFSET 0xC4
199#define ERC32_MEC_WATCHPOINT_OFFSET 0xC8
200#define ERC32_MEC_UNIMPLEMENTED_8_OFFSET 0xCC
201#define ERC32_MEC_TEST_CONTROL_OFFSET 0xD0
202#define ERC32_MEC_TEST_DATA_OFFSET 0xD4
203#define ERC32_MEC_UNIMPLEMENTED_9_OFFSET 0xD8
204#define ERC32_MEC_UART_CHANNEL_A_OFFSET 0xE0
205#define ERC32_MEC_UART_CHANNEL_B_OFFSET 0xE4
206#define ERC32_MEC_UART_STATUS_OFFSET 0xE8
214#define ERC32_CONFIGURATION_POWER_DOWN_MASK 0x00000001
215#define ERC32_CONFIGURATION_POWER_DOWN_ALLOWED 0x00000001
216#define ERC32_CONFIGURATION_POWER_DOWN_DISABLED 0x00000000
218#define ERC32_CONFIGURATION_SOFTWARE_RESET_MASK 0x00000002
219#define ERC32_CONFIGURATION_SOFTWARE_RESET_ALLOWED 0x00000002
220#define ERC32_CONFIGURATION_SOFTWARE_RESET_DISABLED 0x00000000
222#define ERC32_CONFIGURATION_BUS_TIMEOUT_MASK 0x00000004
223#define ERC32_CONFIGURATION_BUS_TIMEOUT_ENABLED 0x00000004
224#define ERC32_CONFIGURATION_BUS_TIMEOUT_DISABLED 0x00000000
226#define ERC32_CONFIGURATION_ACCESS_PROTECTION_MASK 0x00000008
227#define ERC32_CONFIGURATION_ACCESS_PROTECTION_ENABLED 0x00000008
228#define ERC32_CONFIGURATION_ACCESS_PROTECTION_DISABLED 0x00000000
234#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001C00
235#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_256K ( 0 << 10 )
236#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_512K ( 1 << 10 )
237#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_1MB ( 2 << 10 )
238#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_2MB ( 3 << 10 )
239#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_4MB ( 4 << 10 )
240#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_8MB ( 5 << 10 )
241#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_16MB ( 6 << 10 )
242#define ERC32_MEMORY_CONFIGURATION_RAM_SIZE_32MB ( 7 << 10 )
244#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x001C0000
245#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K ( 0 << 18 )
246#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K ( 1 << 18 )
247#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K ( 2 << 18 )
248#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M ( 3 << 18 )
249#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M ( 4 << 18 )
250#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M ( 5 << 18 )
251#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M ( 6 << 18 )
252#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M ( 7 << 18 )
258#define ERC32_MEC_TIMER_CONTROL_GCR 0x00000001
260#define ERC32_MEC_TIMER_CONTROL_GCL 0x00000002
262#define ERC32_MEC_TIMER_CONTROL_GSE 0x00000004
264#define ERC32_MEC_TIMER_CONTROL_GSL 0x00000008
267#define ERC32_MEC_TIMER_CONTROL_RTCCR 0x00000100
269#define ERC32_MEC_TIMER_CONTROL_RTCCL 0x00000200
271#define ERC32_MEC_TIMER_CONTROL_RTCSE 0x00000400
273#define ERC32_MEC_TIMER_CONTROL_RTCSL 0x00000800
281#define ERC32_MEC_UART_CONTROL_RTD 0x000000FF
287#define ERC32_MEC_UART_STATUS_DR 0x00000001
288#define ERC32_MEC_UART_STATUS_TSE 0x00000002
289#define ERC32_MEC_UART_STATUS_THE 0x00000004
290#define ERC32_MEC_UART_STATUS_FE 0x00000010
291#define ERC32_MEC_UART_STATUS_PE 0x00000020
292#define ERC32_MEC_UART_STATUS_OE 0x00000040
293#define ERC32_MEC_UART_STATUS_CU 0x00000080
294#define ERC32_MEC_UART_STATUS_TXE 0x00000006
295#define ERC32_MEC_UART_STATUS_CLRA 0x00000080
296#define ERC32_MEC_UART_STATUS_CLRB 0x00800000
297#define ERC32_MEC_UART_STATUS_ERRA 0x00000070
298#define ERC32_MEC_UART_STATUS_ERRB 0x00700000
300#define ERC32_MEC_UART_STATUS_DRA (ERC32_MEC_UART_STATUS_DR << 0)
301#define ERC32_MEC_UART_STATUS_TSEA (ERC32_MEC_UART_STATUS_TSE << 0)
302#define ERC32_MEC_UART_STATUS_THEA (ERC32_MEC_UART_STATUS_THE << 0)
303#define ERC32_MEC_UART_STATUS_FEA (ERC32_MEC_UART_STATUS_FE << 0)
304#define ERC32_MEC_UART_STATUS_PEA (ERC32_MEC_UART_STATUS_PE << 0)
305#define ERC32_MEC_UART_STATUS_OEA (ERC32_MEC_UART_STATUS_OE << 0)
306#define ERC32_MEC_UART_STATUS_CUA (ERC32_MEC_UART_STATUS_CU << 0)
307#define ERC32_MEC_UART_STATUS_TXEA (ERC32_MEC_UART_STATUS_TXE << 0)
309#define ERC32_MEC_UART_STATUS_DRB (ERC32_MEC_UART_STATUS_DR << 16)
310#define ERC32_MEC_UART_STATUS_TSEB (ERC32_MEC_UART_STATUS_TSE << 16)
311#define ERC32_MEC_UART_STATUS_THEB (ERC32_MEC_UART_STATUS_THE << 16)
312#define ERC32_MEC_UART_STATUS_FEB (ERC32_MEC_UART_STATUS_FE << 16)
313#define ERC32_MEC_UART_STATUS_PEB (ERC32_MEC_UART_STATUS_PE << 16)
314#define ERC32_MEC_UART_STATUS_OEB (ERC32_MEC_UART_STATUS_OE << 16)
315#define ERC32_MEC_UART_STATUS_CUB (ERC32_MEC_UART_STATUS_CU << 16)
316#define ERC32_MEC_UART_STATUS_TXEB (ERC32_MEC_UART_STATUS_TXE << 16)
339#define ERC32_Clear_interrupt( _source ) \
341 ERC32_MEC.Interrupt_Clear = (1 << (_source)); \
344#define ERC32_Force_interrupt( _source ) \
348 _level = sparc_disable_interrupts(); \
349 ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \
350 ERC32_MEC.Interrupt_Force |= (1 << (_source)); \
351 sparc_enable_interrupts( _level ); \
354#define ERC32_Is_interrupt_pending( _source ) \
355 (ERC32_MEC.Interrupt_Pending & (1 << (_source)))
357#define ERC32_Is_interrupt_masked( _source ) \
358 (ERC32_MEC.Interrupt_Mask & (1 << (_source)))
360#define ERC32_Mask_interrupt( _source ) \
364 _level = sparc_disable_interrupts(); \
365 ERC32_MEC.Interrupt_Mask |= (1 << (_source)); \
366 sparc_enable_interrupts( _level ); \
369#define ERC32_Unmask_interrupt( _source ) \
373 _level = sparc_disable_interrupts(); \
374 ERC32_MEC.Interrupt_Mask &= ~(1 << (_source)); \
375 sparc_enable_interrupts( _level ); \
378#define ERC32_Disable_interrupt( _source, _previous ) \
381 uint32_t _mask = 1 << (_source); \
383 _level = sparc_disable_interrupts(); \
384 (_previous) = ERC32_MEC.Interrupt_Mask; \
385 ERC32_MEC.Interrupt_Mask = _previous | _mask; \
386 sparc_enable_interrupts( _level ); \
387 (_previous) &= _mask; \
390#define ERC32_Restore_interrupt( _source, _previous ) \
393 uint32_t _mask = 1 << (_source); \
395 _level = sparc_disable_interrupts(); \
396 ERC32_MEC.Interrupt_Mask = \
397 (ERC32_MEC.Interrupt_Mask & ~_mask) | (_previous); \
398 sparc_enable_interrupts( _level ); \
402#define BSP_Clear_interrupt(_source) ERC32_Clear_interrupt(_source)
403#define BSP_Force_interrupt(_source) ERC32_Force_interrupt(_source)
404#define BSP_Clear_forced_interrupt( _source ) \
408 _level = sparc_disable_interrupts(); \
409 ERC32_MEC.Interrupt_Force &= ~(1 << (_source)); \
410 sparc_enable_interrupts( _level ); \
412#define BSP_Is_interrupt_pending(_source) ERC32_Is_interrupt_pending(_source)
413#define BSP_Is_interrupt_forced(_source) \
414 (ERC32_MEC.Interrupt_Force & (1 << (_source)))
415#define BSP_Is_interrupt_masked(_source) ERC32_Is_interrupt_masked(_source)
416#define BSP_Unmask_interrupt(_source) ERC32_Unmask_interrupt(_source)
417#define BSP_Mask_interrupt(_source) ERC32_Mask_interrupt(_source)
418#define BSP_Disable_interrupt(_source, _previous) \
419 ERC32_Disable_interrupt(_source, _prev)
420#define BSP_Restore_interrupt(_source, _previous) \
421 ERC32_Restore_interrupt(_source, _previous)
424#define BSP_Cpu_Is_interrupt_masked(_source, _cpu) \
425 BSP_Is_interrupt_masked(_source)
426#define BSP_Cpu_Unmask_interrupt(_source, _cpu) \
427 BSP_Unmask_interrupt(_source)
428#define BSP_Cpu_Mask_interrupt(_source, _cpu) \
429 BSP_Mask_interrupt(_source)
430#define BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) \
431 BSP_Disable_interrupt(_source, _prev)
432#define BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) \
433 BSP_Cpu_Restore_interrupt(_source, _previous)
470#define ERC32_MEC_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000001
471#define ERC32_MEC_TIMER_COUNTER_STOP_AT_ZERO 0x00000000
473#define ERC32_MEC_TIMER_COUNTER_LOAD_COUNTER 0x00000002
475#define ERC32_MEC_TIMER_COUNTER_ENABLE_COUNTING 0x00000004
476#define ERC32_MEC_TIMER_COUNTER_DISABLE_COUNTING 0x00000000
478#define ERC32_MEC_TIMER_COUNTER_LOAD_SCALER 0x00000008
480#define ERC32_MEC_TIMER_COUNTER_RELOAD_MASK 0x00000001
481#define ERC32_MEC_TIMER_COUNTER_ENABLE_MASK 0x00000004
483#define ERC32_MEC_TIMER_COUNTER_DEFINED_MASK 0x0000000F
484#define ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000005
486extern uint32_t _ERC32_MEC_Timer_Control_Mirror;
494#define ERC32_MEC_Set_General_Purpose_Timer_Control( _value ) \
500 __value = ((_value) & 0x0f); \
501 _level = sparc_disable_interrupts(); \
502 _control = _ERC32_MEC_Timer_Control_Mirror; \
503 _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \
504 _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
505 _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \
506 _control |= __value; \
508 ERC32_MEC.Timer_Control = _control; \
509 sparc_enable_interrupts( _level ); \
512#define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \
514 (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
523#define ERC32_MEC_Set_Real_Time_Clock_Timer_Control( _value ) \
529 __value = ((_value) & 0x0f) << 8; \
530 _level = sparc_disable_interrupts(); \
531 _control = _ERC32_MEC_Timer_Control_Mirror; \
532 _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \
533 _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
534 _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \
535 _control |= __value; \
537 ERC32_MEC.Timer_Control = _control; \
538 sparc_enable_interrupts( _level ); \
541#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
543 (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
This header file provides information required to build RTEMS for a particular member of the SPARC fa...
Definition: timerdata.h:61