RTEMS 6.1-rc4
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armv4.h
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
12/*
13 * Copyright (c) 2013 embedded brains GmbH & Co. KG
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
28 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34 * POSSIBILITY OF SUCH DAMAGE.
35 */
36
37#ifndef RTEMS_SCORE_ARMV4_H
38#define RTEMS_SCORE_ARMV4_H
39
40#include <rtems/score/cpu.h>
41
42#ifdef __cplusplus
43extern "C" {
44#endif /* __cplusplus */
45
52#ifdef ARM_MULTILIB_ARCH_V4
53
54void bsp_interrupt_dispatch( void );
55
56void _ARMV4_Exception_interrupt( void );
57
58typedef void ARMV4_Exception_abort_handler( CPU_Exception_frame *frame );
59
60void _ARMV4_Exception_data_abort_set_handler(
61 ARMV4_Exception_abort_handler handler
62);
63
64void _ARMV4_Exception_data_abort( void );
65
66void _ARMV4_Exception_prefetch_abort_set_handler(
67 ARMV4_Exception_abort_handler handler
68);
69
70void _ARMV4_Exception_prefetch_abort( void );
71
72void _ARMV4_Exception_undef_default( void );
73
74void _ARMV4_Exception_swi_default( void );
75
76void _ARMV4_Exception_data_abort_default( void );
77
78void _ARMV4_Exception_pref_abort_default( void );
79
80void _ARMV4_Exception_fiq_default( void );
81
82static inline uint32_t _ARMV4_Status_irq_enable( void )
83{
84 uint32_t arm_switch_reg;
85 uint32_t psr;
86
88
89 __asm__ volatile (
90 ARM_SWITCH_TO_ARM
91 "mrs %[psr], cpsr\n"
92 "bic %[arm_switch_reg], %[psr], #0x80\n"
93 "msr cpsr, %[arm_switch_reg]\n"
94 ARM_SWITCH_BACK
95 : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr)
96 );
97
98 return psr;
99}
100
101static inline void _ARMV4_Status_restore( uint32_t psr )
102{
103 ARM_SWITCH_REGISTERS;
104
105 __asm__ volatile (
106 ARM_SWITCH_TO_ARM
107 "msr cpsr, %[psr]\n"
108 ARM_SWITCH_BACK
109 : ARM_SWITCH_OUTPUT
110 : [psr] "r" (psr)
111 );
112
114}
115
116#endif /* ARM_MULTILIB_ARCH_V4 */
117
120#ifdef __cplusplus
121}
122#endif /* __cplusplus */
123
124#endif /* RTEMS_SCORE_ARMV4_H */
#define RTEMS_COMPILER_MEMORY_BARRIER()
This macro forbids the compiler to reorder read and write commands around it.
Definition: basedefs.h:258
The set of registers that specifies the complete processor state.
Definition: cpu.h:446