RTEMS 6.1-rc2
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xqspipsu_hw.h
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1/******************************************************************************
2* Copyright (C) 2014 - 2022 Xilinx, Inc. All rights reserved.
3* SPDX-License-Identifier: MIT
4******************************************************************************/
5
6/*****************************************************************************/
37#ifndef XQSPIPSU_HW_H
38#define XQSPIPSU_HW_H
40#ifdef __cplusplus
41extern "C" {
42#endif
43
44/***************************** Include Files *********************************/
45
46#include "xil_types.h"
47#include "xil_assert.h"
48#include "xil_io.h"
49#include "xparameters.h"
50
51/************************** Constant Definitions *****************************/
60#if defined (versal)
61#define XQSPIPS_BASEADDR 0XF1030000U
62#else
63#define XQSPIPS_BASEADDR 0XFF0F0000U
64#endif
65
66#if defined (versal)
67#define XQSPIPSU_BASEADDR 0XF1030100U
68#else
69#define XQSPIPSU_BASEADDR 0xFF0F0100U
70#endif
71#define XQSPIPSU_OFFSET 0x100U
82#define XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014U )
83#define XQSPIPS_EN_SHIFT 0U
84#define XQSPIPS_EN_WIDTH 1U
85#define XQSPIPS_EN_MASK 0X00000001U
96#define XQSPIPSU_CFG_OFFSET 0X00000000U
97
98#define XQSPIPSU_CFG_MODE_EN_SHIFT 30U
99#define XQSPIPSU_CFG_MODE_EN_WIDTH 2U
100#define XQSPIPSU_CFG_MODE_EN_MASK 0XC0000000U
101#define XQSPIPSU_CFG_MODE_EN_DMA_MASK 0X80000000U
102
103#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT 29U
104#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH 1U
105#define XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK 0X20000000U
106
107#define XQSPIPSU_CFG_START_GEN_FIFO_SHIFT 28U
108#define XQSPIPSU_CFG_START_GEN_FIFO_WIDTH 1U
109#define XQSPIPSU_CFG_START_GEN_FIFO_MASK 0X10000000U
110
111#define XQSPIPSU_CFG_ENDIAN_SHIFT 26U
112#define XQSPIPSU_CFG_ENDIAN_WIDTH 1U
113#define XQSPIPSU_CFG_ENDIAN_MASK 0X04000000U
114
115#define XQSPIPSU_CFG_EN_POLL_TO_SHIFT 20U
116#define XQSPIPSU_CFG_EN_POLL_TO_WIDTH 1U
117#define XQSPIPSU_CFG_EN_POLL_TO_MASK 0X00100000U
118
119#define XQSPIPSU_CFG_WP_HOLD_SHIFT 19U
120#define XQSPIPSU_CFG_WP_HOLD_WIDTH 1U
121#define XQSPIPSU_CFG_WP_HOLD_MASK 0X00080000U
122
123#define XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT 3U
124#define XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH 3U
125#define XQSPIPSU_CFG_BAUD_RATE_DIV_MASK 0X00000038U
126
127#define XQSPIPSU_CFG_CLK_PHA_SHIFT 2U
128#define XQSPIPSU_CFG_CLK_PHA_WIDTH 1U
129#define XQSPIPSU_CFG_CLK_PHA_MASK 0X00000004U
130
131#define XQSPIPSU_CFG_CLK_POL_SHIFT 1U
132#define XQSPIPSU_CFG_CLK_POL_WIDTH 1U
133#define XQSPIPSU_CFG_CLK_POL_MASK 0X00000002U
144#if !defined (versal)
145#define XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U
146#define XQSPIPSU_LQSPI_CR_LINEAR_MASK 0x80000000U
147#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK 0x40000000U
148#define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK 0x20000000U
149#define XQSPIPSU_LQSPI_CR_U_PAGE_MASK 0x10000000U
150#define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK 0x01000000U
151#define XQSPIPSU_LQSPI_CR_MODE_EN_MASK 0x02000000U
152#define XQSPIPSU_LQSPI_CR_MODE_ON_MASK 0x01000000U
153#define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK 0x00FF0000U
155#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FFU
156#define XQSPIPS_LQSPI_CR_RST_STATE 0x80000003U
157#define XQSPIPS_LQSPI_CR_4_BYTE_STATE 0x88000013U
158#define XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1U
159#endif
170#define XQSPIPSU_ISR_OFFSET 0X00000004U
171
172#define XQSPIPSU_ISR_RXEMPTY_SHIFT 11U
173#define XQSPIPSU_ISR_RXEMPTY_WIDTH 1U
174#define XQSPIPSU_ISR_RXEMPTY_MASK 0X00000800U
175
176#define XQSPIPSU_ISR_GENFIFOFULL_SHIFT 10U
177#define XQSPIPSU_ISR_GENFIFOFULL_WIDTH 1U
178#define XQSPIPSU_ISR_GENFIFOFULL_MASK 0X00000400U
179
180#define XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT 9U
181#define XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH 1U
182#define XQSPIPSU_ISR_GENFIFONOT_FULL_MASK 0X00000200U
183
184#define XQSPIPSU_ISR_TXEMPTY_SHIFT 8U
185#define XQSPIPSU_ISR_TXEMPTY_WIDTH 1U
186#define XQSPIPSU_ISR_TXEMPTY_MASK 0X00000100U
187
188#define XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT 7U
189#define XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH 1U
190#define XQSPIPSU_ISR_GENFIFOEMPTY_MASK 0X00000080U
191
192#define XQSPIPSU_ISR_RXFULL_SHIFT 5U
193#define XQSPIPSU_ISR_RXFULL_WIDTH 1U
194#define XQSPIPSU_ISR_RXFULL_MASK 0X00000020U
195
196#define XQSPIPSU_ISR_RXNEMPTY_SHIFT 4U
197#define XQSPIPSU_ISR_RXNEMPTY_WIDTH 1U
198#define XQSPIPSU_ISR_RXNEMPTY_MASK 0X00000010U
199
200#define XQSPIPSU_ISR_TXFULL_SHIFT 3U
201#define XQSPIPSU_ISR_TXFULL_WIDTH 1U
202#define XQSPIPSU_ISR_TXFULL_MASK 0X00000008U
203
204#define XQSPIPSU_ISR_TXNOT_FULL_SHIFT 2U
205#define XQSPIPSU_ISR_TXNOT_FULL_WIDTH 1U
206#define XQSPIPSU_ISR_TXNOT_FULL_MASK 0X00000004U
207
208#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT 1U
209#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH 1U
210#define XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK 0X00000002U
211
212#define XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002U
223#define XQSPIPSU_IER_OFFSET 0X00000008U
224
225#define XQSPIPSU_IER_RXEMPTY_SHIFT 11U
226#define XQSPIPSU_IER_RXEMPTY_WIDTH 1U
227#define XQSPIPSU_IER_RXEMPTY_MASK 0X00000800U
228
229#define XQSPIPSU_IER_GENFIFOFULL_SHIFT 10U
230#define XQSPIPSU_IER_GENFIFOFULL_WIDTH 1U
231#define XQSPIPSU_IER_GENFIFOFULL_MASK 0X00000400U
232
233#define XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT 9U
234#define XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH 1U
235#define XQSPIPSU_IER_GENFIFONOT_FULL_MASK 0X00000200U
236
237#define XQSPIPSU_IER_TXEMPTY_SHIFT 8U
238#define XQSPIPSU_IER_TXEMPTY_WIDTH 1U
239#define XQSPIPSU_IER_TXEMPTY_MASK 0X00000100U
240
241#define XQSPIPSU_IER_GENFIFOEMPTY_SHIFT 7U
242#define XQSPIPSU_IER_GENFIFOEMPTY_WIDTH 1U
243#define XQSPIPSU_IER_GENFIFOEMPTY_MASK 0X00000080U
244
245#define XQSPIPSU_IER_RXFULL_SHIFT 5U
246#define XQSPIPSU_IER_RXFULL_WIDTH 1U
247#define XQSPIPSU_IER_RXFULL_MASK 0X00000020U
248
249#define XQSPIPSU_IER_RXNEMPTY_SHIFT 4U
250#define XQSPIPSU_IER_RXNEMPTY_WIDTH 1U
251#define XQSPIPSU_IER_RXNEMPTY_MASK 0X00000010U
252
253#define XQSPIPSU_IER_TXFULL_SHIFT 3U
254#define XQSPIPSU_IER_TXFULL_WIDTH 1U
255#define XQSPIPSU_IER_TXFULL_MASK 0X00000008U
256
257#define XQSPIPSU_IER_TXNOT_FULL_SHIFT 2U
258#define XQSPIPSU_IER_TXNOT_FULL_WIDTH 1U
259#define XQSPIPSU_IER_TXNOT_FULL_MASK 0X00000004U
260
261#define XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT 1U
262#define XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH 1U
263#define XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK 0X00000002U
274#define XQSPIPSU_IDR_OFFSET 0X0000000CU
275
276#define XQSPIPSU_IDR_RXEMPTY_SHIFT 11U
277#define XQSPIPSU_IDR_RXEMPTY_WIDTH 1U
278#define XQSPIPSU_IDR_RXEMPTY_MASK 0X00000800U
279
280#define XQSPIPSU_IDR_GENFIFOFULL_SHIFT 10U
281#define XQSPIPSU_IDR_GENFIFOFULL_WIDTH 1U
282#define XQSPIPSU_IDR_GENFIFOFULL_MASK 0X00000400U
283
284#define XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT 9U
285#define XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH 1U
286#define XQSPIPSU_IDR_GENFIFONOT_FULL_MASK 0X00000200U
287
288#define XQSPIPSU_IDR_TXEMPTY_SHIFT 8U
289#define XQSPIPSU_IDR_TXEMPTY_WIDTH 1U
290#define XQSPIPSU_IDR_TXEMPTY_MASK 0X00000100U
291
292#define XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT 7U
293#define XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH 1U
294#define XQSPIPSU_IDR_GENFIFOEMPTY_MASK 0X00000080U
295
296#define XQSPIPSU_IDR_RXFULL_SHIFT 5U
297#define XQSPIPSU_IDR_RXFULL_WIDTH 1U
298#define XQSPIPSU_IDR_RXFULL_MASK 0X00000020U
299
300#define XQSPIPSU_IDR_RXNEMPTY_SHIFT 4U
301#define XQSPIPSU_IDR_RXNEMPTY_WIDTH 1U
302#define XQSPIPSU_IDR_RXNEMPTY_MASK 0X00000010U
303
304#define XQSPIPSU_IDR_TXFULL_SHIFT 3U
305#define XQSPIPSU_IDR_TXFULL_WIDTH 1U
306#define XQSPIPSU_IDR_TXFULL_MASK 0X00000008U
307
308#define XQSPIPSU_IDR_TXNOT_FULL_SHIFT 2U
309#define XQSPIPSU_IDR_TXNOT_FULL_WIDTH 1U
310#define XQSPIPSU_IDR_TXNOT_FULL_MASK 0X00000004U
311
312#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT 1U
313#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH 1U
314#define XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK 0X00000002U
315
316#define XQSPIPSU_IDR_ALL_MASK 0X0FBEU
327#define XQSPIPSU_IMR_OFFSET 0X00000010U
328
329#define XQSPIPSU_IMR_RXEMPTY_SHIFT 11U
330#define XQSPIPSU_IMR_RXEMPTY_WIDTH 1U
331#define XQSPIPSU_IMR_RXEMPTY_MASK 0X00000800U
332
333#define XQSPIPSU_IMR_GENFIFOFULL_SHIFT 10U
334#define XQSPIPSU_IMR_GENFIFOFULL_WIDTH 1U
335#define XQSPIPSU_IMR_GENFIFOFULL_MASK 0X00000400U
336
337#define XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT 9U
338#define XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH 1U
339#define XQSPIPSU_IMR_GENFIFONOT_FULL_MASK 0X00000200U
340
341#define XQSPIPSU_IMR_TXEMPTY_SHIFT 8U
342#define XQSPIPSU_IMR_TXEMPTY_WIDTH 1U
343#define XQSPIPSU_IMR_TXEMPTY_MASK 0X00000100U
344
345#define XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT 7U
346#define XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH 1U
347#define XQSPIPSU_IMR_GENFIFOEMPTY_MASK 0X00000080U
348
349#define XQSPIPSU_IMR_RXFULL_SHIFT 5U
350#define XQSPIPSU_IMR_RXFULL_WIDTH 1U
351#define XQSPIPSU_IMR_RXFULL_MASK 0X00000020U
352
353#define XQSPIPSU_IMR_RXNEMPTY_SHIFT 4U
354#define XQSPIPSU_IMR_RXNEMPTY_WIDTH 1U
355#define XQSPIPSU_IMR_RXNEMPTY_MASK 0X00000010U
356
357#define XQSPIPSU_IMR_TXFULL_SHIFT 3U
358#define XQSPIPSU_IMR_TXFULL_WIDTH 1U
359#define XQSPIPSU_IMR_TXFULL_MASK 0X00000008U
360
361#define XQSPIPSU_IMR_TXNOT_FULL_SHIFT 2U
362#define XQSPIPSU_IMR_TXNOT_FULL_WIDTH 1U
363#define XQSPIPSU_IMR_TXNOT_FULL_MASK 0X00000004U
364
365#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT 1U
366#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH 1U
367#define XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK 0X00000002U
378#define XQSPIPSU_EN_OFFSET 0X00000014U
379
380#define XQSPIPSU_EN_SHIFT 0U
381#define XQSPIPSU_EN_WIDTH 1U
382#define XQSPIPSU_EN_MASK 0X00000001U
393#define XQSPIPSU_TXD_OFFSET 0X0000001CU
394
395#define XQSPIPSU_TXD_SHIFT 0U
396#define XQSPIPSU_TXD_WIDTH 32U
397#define XQSPIPSU_TXD_MASK 0XFFFFFFFFU
398
399#define XQSPIPSU_TXD_DEPTH 64
410#define XQSPIPSU_RXD_OFFSET 0X00000020U
411
412#define XQSPIPSU_RXD_SHIFT 0U
413#define XQSPIPSU_RXD_WIDTH 32U
414#define XQSPIPSU_RXD_MASK 0XFFFFFFFFU
425#define XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028U
426
427#define XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT 0U
428#define XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH 6U
429#define XQSPIPSU_TX_FIFO_THRESHOLD_MASK 0X0000003FU
430#define XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL 0X01U
431
432#define XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002CU
433
434#define XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT 0U
435#define XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH 6U
436#define XQSPIPSU_RX_FIFO_THRESHOLD_MASK 0X0000003FU
437#define XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL 0X01U
438
439#define XQSPIPSU_RXFIFO_THRESHOLD_OPT 32U
449#define XQSPIPSU_GPIO_OFFSET 0X00000030U
450
451#define XQSPIPSU_GPIO_WP_N_SHIFT 0U
452#define XQSPIPSU_GPIO_WP_N_WIDTH 1U
453#define XQSPIPSU_GPIO_WP_N_MASK 0X00000001U
464#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038U
465
466#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT 5U
467#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH 1U
468#define XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK 0X00000020U
469
470#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT 3U
471#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH 2U
472#define XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK 0X00000018U
473
474#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT 0U
475#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH 3U
476#define XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK 0X00000007U
487#define XQSPIPSU_GEN_FIFO_OFFSET 0X00000040U
488
489#define XQSPIPSU_GEN_FIFO_DATA_SHIFT 0U
490#define XQSPIPSU_GEN_FIFO_DATA_WIDTH 20U
491#define XQSPIPSU_GEN_FIFO_DATA_MASK 0X000FFFFFU
502#define XQSPIPSU_SEL_OFFSET 0X00000044U
503
504#define XQSPIPSU_SEL_SHIFT 0U
505#define XQSPIPSU_SEL_WIDTH 1U
506#if !defined (versal)
507#define XQSPIPSU_SEL_LQSPI_MASK 0X0U
508#endif
509#define XQSPIPSU_SEL_GQSPI_MASK 0X00000001U
520#define XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004CU
521
522#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT 2U
523#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH 1U
524#define XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK 0X00000004U
525
526#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT 1U
527#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH 1U
528#define XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK 0X00000002U
529
530#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT 0U
531#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH 1U
532#define XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK 0X00000001U
543#define XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050U
544
545#define XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT 0U
546#define XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH 5U
547#define XQSPIPSU_GEN_FIFO_THRESHOLD_MASK 0X0000001FU
548#define XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL 0X10U
559#define XQSPIPSU_POLL_CFG_OFFSET 0X00000054U
560
561#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT 31U
562#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH 1U
563#define XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK 0X80000000U
564
565#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT 30U
566#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH 1U
567#define XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK 0X40000000U
568
569#define XQSPIPSU_POLL_CFG_MASK_EN_SHIFT 8U
570#define XQSPIPSU_POLL_CFG_MASK_EN_WIDTH 8U
571#define XQSPIPSU_POLL_CFG_MASK_EN_MASK 0X0000FF00U
572
573#define XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT 0U
574#define XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH 8U
575#define XQSPIPSU_POLL_CFG_DATA_VALUE_MASK 0X000000FFU
576
577#define XQSPIPSU_P_TO_OFFSET 0X00000058U
578
579#define XQSPIPSU_P_TO_VALUE_SHIFT 0U
580#define XQSPIPSU_P_TO_VALUE_WIDTH 32U
581#define XQSPIPSU_P_TO_VALUE_MASK 0XFFFFFFFFU
592#define XQSPIPSU_XFER_STS_OFFSET 0X0000005CU
593
594#define XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT 0U
595#define XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH 32U
596#define XQSPIPSU_XFER_STS_PEND_BYTES_MASK 0XFFFFFFFFU
607#define XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060U
608
609#define XQSPIPSU_GF_SNAPSHOT_SHIFT 0U
610#define XQSPIPSU_GF_SNAPSHOT_WIDTH 20U
611#define XQSPIPSU_GF_SNAPSHOT_MASK 0X000FFFFFU
621#define XQSPIPSU_RX_COPY_OFFSET 0X00000064U
622
623#define XQSPIPSU_RX_COPY_UPPER_SHIFT 8U
624#define XQSPIPSU_RX_COPY_UPPER_WIDTH 8U
625#define XQSPIPSU_RX_COPY_UPPER_MASK 0X0000FF00U
626
627#define XQSPIPSU_RX_COPY_LOWER_SHIFT 0U
628#define XQSPIPSU_RX_COPY_LOWER_WIDTH 8U
629#define XQSPIPSU_RX_COPY_LOWER_MASK 0X000000FFU
639#define XQSPIPSU_MOD_ID_OFFSET 0X000000FCU
640
641#define XQSPIPSU_MOD_ID_SHIFT 0U
642#define XQSPIPSU_MOD_ID_WIDTH 32U
643#define XQSPIPSU_MOD_ID_MASK 0XFFFFFFFFU
654#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700U
655
656#define XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT 2U
657#define XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH 30U
658#define XQSPIPSU_QSPIDMA_DST_ADDR_MASK 0XFFFFFFFCU
659
660#define XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704U
661
662#define XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT 2U
663#define XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH 27U
664#define XQSPIPSU_QSPIDMA_DST_SIZE_MASK 0X1FFFFFFCU
665
666#define XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708U
667
668#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT 13U
669#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH 3U
670#define XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK 0X0000E000U
671
672#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT 5U
673#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH 8U
674#define XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK 0X00001FE0U
675
676#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT 1U
677#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH 4U
678#define XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK 0X0000001EU
679
680#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT 0U
681#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH 1U
682#define XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001U
683
684#define XQSPIPSU_QSPIDMA_DST_STS_WTC 0xE000U
685
686#define XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070CU
687
688#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT 25U
689#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH 7U
690#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK 0XFE000000U
691
692#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT 24U
693#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH 1U
694#define XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK 0X01000000U
695
696#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT 23U
697#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH 1U
698#define XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK 0X00800000U
699
700#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT 22U
701#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH 1U
702#define XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK 0X00400000U
703
704#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT 10U
705#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH 12U
706#define XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK 0X003FFC00U
707
708#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT 2U
709#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH 8U
710#define XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK 0X000003FCU
711
712#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT 1U
713#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH 1U
714#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK 0X00000002U
715
716#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT 0U
717#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH 1U
718#define XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001U
719
720#define XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x403FFA00U
721
722#define XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714U
723
724#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT 7U
725#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH 1U
726#define XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK 0X00000080U
727
728#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT 6U
729#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH 1U
730#define XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK 0X00000040U
731
732#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT 5U
733#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH 1U
734#define XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK 0X00000020U
735
736#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT 4U
737#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH 1U
738#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK 0X00000010U
739
740#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT 3U
741#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH 1U
742#define XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK 0X00000008U
743
744#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT 2U
745#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH 1U
746#define XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK 0X00000004U
747
748#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT 1U
749#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH 1U
750#define XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002U
751
752#define XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FCU
753#define XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK 0X000000FEU
754
755#define XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718U
756
757#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT 7U
758#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH 1U
759#define XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK 0X00000080U
760
761#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT 6U
762#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH 1U
763#define XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK 0X00000040U
764
765#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT 5U
766#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH 1U
767#define XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK 0X00000020U
768
769#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT 4U
770#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH 1U
771#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK 0X00000010U
772
773#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT 3U
774#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH 1U
775#define XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK 0X00000008U
776
777#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT 2U
778#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH 1U
779#define XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK 0X00000004U
780
781#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT 1U
782#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH 1U
783#define XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK 0X00000002U
784
785#define XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071CU
786
787#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT 7U
788#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH 1U
789#define XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK 0X00000080U
790
791#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT 6U
792#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH 1U
793#define XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK 0X00000040U
794
795#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT 5U
796#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH 1U
797#define XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK 0X00000020U
798
799#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT 4U
800#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH 1U
801#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK 0X00000010U
802
803#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT 3U
804#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH 1U
805#define XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK 0X00000008U
806
807#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT 2U
808#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH 1U
809#define XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK 0X00000004U
810
811#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT 1U
812#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH 1U
813#define XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK 0X00000002U
814
815#define XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720U
816
817#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT 7U
818#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH 1U
819#define XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK 0X00000080U
820
821#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT 6U
822#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH 1U
823#define XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK 0X00000040U
824
825#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT 5U
826#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH 1U
827#define XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK 0X00000020U
828
829#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT 4U
830#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH 1U
831#define XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK 0X00000010U
832
833#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT 3U
834#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH 1U
835#define XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK 0X00000008U
836
837#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT 2U
838#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH 1U
839#define XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK 0X00000004U
840
841#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT 1U
842#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH 1U
843#define XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK 0X00000002U
844
845#define XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724U
846
847#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT 27U
848#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH 1U
849#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK 0X08000000U
850
851#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT 24U
852#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH 3U
853#define XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK 0X07000000U
854
855#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT 22U
856#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH 1U
857#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK 0X00400000U
858
859#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT 19U
860#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH 3U
861#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK 0X00380000U
862
863#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT 16U
864#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH 3U
865#define XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK 0X00070000U
866
867#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT 4U
868#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH 12U
869#define XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK 0X0000FFF0U
870
871#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT 0U
872#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH 4U
873#define XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000FU
874
875#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728U
876
877#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT 0U
878#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH 12U
879#define XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK 0X00000FFFU
880
881#define XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFCU
882
883#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT 0U
884#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH 32U
885#define XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK 0XFFFFFFFFU
896#define XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFFU
897#define XQSPIPSU_GENFIFO_DATA_XFER 0x100U
898#define XQSPIPSU_GENFIFO_EXP 0x200U
899#define XQSPIPSU_GENFIFO_MODE_SPI 0x400U
900#define XQSPIPSU_GENFIFO_MODE_DUALSPI 0x800U
901#define XQSPIPSU_GENFIFO_MODE_QUADSPI 0xC00U
902#define XQSPIPSU_GENFIFO_MODE_MASK 0xC00U /* And with ~MASK first */
903#define XQSPIPSU_GENFIFO_CS_LOWER 0x1000U
904#define XQSPIPSU_GENFIFO_CS_UPPER 0x2000U
905#define XQSPIPSU_GENFIFO_BUS_LOWER 0x4000U
906#define XQSPIPSU_GENFIFO_BUS_UPPER 0x8000U
907#define XQSPIPSU_GENFIFO_BUS_BOTH 0xC000U /* inverse is no bus */
908#define XQSPIPSU_GENFIFO_BUS_MASK 0xC000U /* And with ~MASK first */
909#define XQSPIPSU_GENFIFO_TX 0x10000U /* inverse is zero pump */
910#define XQSPIPSU_GENFIFO_RX 0x20000U /* inverse is RX discard */
911#define XQSPIPSU_GENFIFO_STRIPE 0x40000U
912#define XQSPIPSU_GENFIFO_POLL 0x80000U
922#define XQSPIPSU_DATA_DLY_ADJ_OFFSET 0X000000F8U
923
924#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT 31U
925#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_WIDTH 1U
926#define XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK 0X80000000U
927
928#define XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT 28U
929#define XQSPIPSU_DATA_DLY_ADJ_DLY_WIDTH 3U
930#define XQSPIPSU_DATA_DLY_ADJ_DLY_MASK 0X70000000U
941#if defined versal
942#define IOU_TAPDLY_BYPASS_OFFSET 0X0000003CU
943#else
944#define IOU_TAPDLY_BYPASS_OFFSET 0X00000390U
945#endif
946
947#define IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02U
948#if !defined (versal)
949#define IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01U
950#define IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U
951#endif
952
953#if defined versal
954#define IOU_TAPDLY_RESET_STATE 0x4U
955#else
956#define IOU_TAPDLY_RESET_STATE 0x7U
957#endif
960/***************** Macros (Inline Functions) Definitions *********************/
961
962#define XQspiPsu_In32 Xil_In32
963#define XQspiPsu_Out32 Xil_Out32
965/****************************************************************************/
979#define XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset))
980
981/***************************************************************************/
997#define XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))
998
999
1000#ifdef __cplusplus
1001}
1002#endif
1003
1004
1005#endif