Data Structures
struct	XNandPsu_Config

struct	XNandPsu_BbtDesc

struct	XNandPsu_BadBlockPattern

struct	XNandPsu_Geometry

struct	XNandPsu_Features

struct	XNandPsu_EccMatrix

struct	XNandPsu_EccCfg

struct	XNandPsu

struct	__attribute__

struct	OnfiCmdFormat

struct	XQspiPsu_Msg

struct	XQspiPsu_Config

struct	XQspiPsu

struct	OptionsMap

Macros
#define	XNANDPSU_H /* by using protection macros */

#define	XNANDPSU_DEBUG

#define	XNANDPSU_MAX_TARGETS 1U

#define	XNANDPSU_MAX_PKT_SIZE 0x7FFU

#define	XNANDPSU_MAX_PKT_COUNT 0xFFFU

#define	XNANDPSU_PAGE_SIZE_512 512U

#define	XNANDPSU_PAGE_SIZE_2K 2048U

#define	XNANDPSU_PAGE_SIZE_4K 4096U

#define	XNANDPSU_PAGE_SIZE_8K 8192U

#define	XNANDPSU_PAGE_SIZE_16K 16384U

#define	XNANDPSU_PAGE_SIZE_1K_16BIT 1024U

#define	XNANDPSU_MAX_PAGE_SIZE 16384U

#define	XNANDPSU_HAMMING 0x1U

#define	XNANDPSU_BCH 0x2U

#define	XNANDPSU_MAX_BLOCKS 16384U

#define	XNANDPSU_MAX_SPARE_SIZE 0x800U

#define	XNANDPSU_MAX_LUNS 8U

#define	XNANDPSU_MAX_PAGES_PER_BLOCK 512U

#define	XNANDPSU_INTR_POLL_TIMEOUT 0xF000000U

#define	XNANDPSU_SDR_CLK ((u16)100U * (u16)1000U * (u16)1000U)

#define	XNANDPSU_NVDDR_CLK_0 ((u16)20U * (u16)1000U * (u16)1000U)

#define	XNANDPSU_NVDDR_CLK_1 ((u16)33U * (u16)1000U * (u16)1000U)

#define	XNANDPSU_NVDDR_CLK_2 ((u16)50U * (u16)1000U * (u16)1000U)

#define	XNANDPSU_NVDDR_CLK_3 ((u16)66U * (u16)1000U * (u16)1000U)

#define	XNANDPSU_NVDDR_CLK_4 ((u16)83U * (u16)1000U * (u16)1000U)

#define	XNANDPSU_NVDDR_CLK_5 ((u16)100U * (u16)1000U * (u16)1000U)

#define	XNANDPSU_MAX_TIMING_MODE 5

#define	XNandPsu_SetBits(InstancePtr, RegOffset, BitMask)

#define	XNandPsu_ClrBits(InstancePtr, RegOffset, BitMask)

#define	XNandPsu_ReadModifyWrite(InstancePtr, RegOffset, Mask, Value)

#define	XNandPsu_IntrSigEnable(InstancePtr, Mask)

#define	XNandPsu_IntrSigClear(InstancePtr, Mask)

#define	XNandPsu_IntrStsEnable(InstancePtr, Mask)

#define	IS_ONFI(Buff)

#define	XNANDPSU_BBM_H /* by using protection macros */

#define	XNANDPSU_BLOCK_GOOD 0x0U

#define	XNANDPSU_BLOCK_BAD 0x1U

#define	XNANDPSU_BLOCK_RESERVED 0x2U

#define	XNANDPSU_BLOCK_FACTORY_BAD 0x3U

#define	XNANDPSU_FLASH_BLOCK_GOOD 0x3U

#define	XNANDPSU_FLASH_BLOCK_BAD 0x2U

#define	XNANDPSU_FLASH_BLOCK_RESERVED 0x1U

#define	XNANDPSU_FLASH_BLOCK_FAC_BAD 0x0U

#define	XNANDPSU_BBT_SCAN_2ND_PAGE 0x00000001U

#define	XNANDPSU_BBT_DESC_PAGE_OFFSET 0U

#define	XNANDPSU_BBT_DESC_SIG_OFFSET 8U

#define	XNANDPSU_BBT_DESC_VER_OFFSET 12U

#define	XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET 0U

#define	XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET 4U

#define	XNANDPSU_BBT_DESC_SIG_LEN 4U

#define	XNANDPSU_BBT_DESC_MAX_BLOCKS 64U

#define	XNANDPSU_BBT_BLOCK_SHIFT 2U

#define	XNANDPSU_BBT_ENTRY_NUM_BLOCKS 4U

#define	XNANDPSU_BB_PTRN_OFF_SML_PAGE 5U

#define	XNANDPSU_BB_PTRN_LEN_SML_PAGE 1U

#define	XNANDPSU_BB_PTRN_OFF_LARGE_PAGE 0U

#define	XNANDPSU_BB_PTRN_LEN_LARGE_PAGE 2U

#define	XNANDPSU_BB_PATTERN 0xFFU

#define	XNANDPSU_BLOCK_TYPE_MASK 0x03U

#define	XNANDPSU_BLOCK_SHIFT_MASK 0x06U

#define	XNANDPSU_ONDIE_SIG_OFFSET 0x4U

#define	XNANDPSU_ONDIE_VER_OFFSET 0x14U

#define	XNANDPSU_BBT_VERSION_LENGTH 1U

#define	XNANDPSU_BBT_SIG_LENGTH 4U

#define	XNANDPSU_BBT_BUF_LENGTH

#define	XNandPsu_BbtBlockShift(Block) (u8)(((Block) * 2U) & XNANDPSU_BLOCK_SHIFT_MASK)

#define	XNANDPSU_HW_H /* by using protection macros */

#define	XNANDPSU_PKT_OFFSET 0x00U

#define	XNANDPSU_MEM_ADDR1_OFFSET 0x04U

#define	XNANDPSU_MEM_ADDR2_OFFSET 0x08U

#define	XNANDPSU_CMD_OFFSET 0x0CU

#define	XNANDPSU_PROG_OFFSET 0x10U

#define	XNANDPSU_INTR_STS_EN_OFFSET 0x14U

#define	XNANDPSU_INTR_SIG_EN_OFFSET 0x18U

#define	XNANDPSU_INTR_STS_OFFSET 0x1CU

#define	XNANDPSU_READY_BUSY_OFFSET 0x20U

#define	XNANDPSU_FLASH_STS_OFFSET 0x28U

#define	XNANDPSU_TIMING_OFFSET 0x2CU

#define	XNANDPSU_BUF_DATA_PORT_OFFSET 0x30U

#define	XNANDPSU_ECC_OFFSET 0x34U

#define	XNANDPSU_ECC_ERR_CNT_OFFSET 0x38U

#define	XNANDPSU_ECC_SPR_CMD_OFFSET 0x3CU

#define	XNANDPSU_ECC_CNT_1BIT_OFFSET 0x40U

#define	XNANDPSU_ECC_CNT_2BIT_OFFSET 0x44U

#define	XNANDPSU_ECC_CNT_3BIT_OFFSET 0x48U

#define	XNANDPSU_ECC_CNT_4BIT_OFFSET 0x4CU

#define	XNANDPSU_CPU_REL_OFFSET 0x58U

#define	XNANDPSU_ECC_CNT_5BIT_OFFSET 0x5CU

#define	XNANDPSU_ECC_CNT_6BIT_OFFSET 0x60U

#define	XNANDPSU_ECC_CNT_7BIT_OFFSET 0x64U

#define	XNANDPSU_ECC_CNT_8BIT_OFFSET 0x68U

#define	XNANDPSU_DATA_INTF_OFFSET 0x6CU

#define	XNANDPSU_DMA_SYS_ADDR0_OFFSET 0x50U

#define	XNANDPSU_DMA_SYS_ADDR1_OFFSET 0x24U

#define	XNANDPSU_DMA_BUF_BND_OFFSET 0x54U

#define	XNANDPSU_SLV_DMA_CONF_OFFSET 0x80U

#define	XNANDPSU_ONFI_H /* by using protection macros */

#define	ONFI_CMD_RD1 0x00U

#define	ONFI_CMD_RD2 0x30U

#define	ONFI_CMD_CHNG_RD_COL1 0x05U

#define	ONFI_CMD_CHNG_RD_COL2 0xE0U

#define	ONFI_CMD_BLK_ERASE1 0x60U

#define	ONFI_CMD_BLK_ERASE2 0xD0U

#define	ONFI_CMD_RD_STS 0x70U

#define	ONFI_CMD_PG_PROG1 0x80U

#define	ONFI_CMD_PG_PROG2 0x10U

#define	ONFI_CMD_CHNG_WR_COL 0x85U

#define	ONFI_CMD_RD_ID 0x90U

#define	ONFI_CMD_RD_PRM_PG 0xECU

#define	ONFI_CMD_RST 0xFFU

#define	ONFI_CMD_MUL_RD1 0x00U

#define	ONFI_CMD_MUL_RD2 0x32U

#define	ONFI_CMD_CPBK_RD1 0x00U

#define	ONFI_CMD_CPBK_RD2 0x35U

#define	ONFI_CMD_CHNG_RD_COL_ENHCD1 0x06U

#define	ONFI_CMD_CHNG_RD_COL_ENHCD2 0xE0U

#define	ONFI_CMD_RD_CACHE_RND1 0x00U

#define	ONFI_CMD_RD_CACHE_RND2 0x31U

#define	ONFI_CMD_RD_CACHE_SEQ 0x31U

#define	ONFI_CMD_RD_CACHE_END 0x3FU

#define	ONFI_CMD_MUL_BLK_ERASE1 0x60U

#define	ONFI_CMD_MUL_BLK_ERASE2 0xD1U

#define	ONFI_CMD_RD_STS_ENHCD 0x78U

#define	ONFI_CMD_BLK_ERASE_INTRLVD2 0xD1U

#define	ONFI_CMD_MUL_PG_PROG1 0x80U

#define	ONFI_CMD_MUL_PG_PROG2 0x11U

#define	ONFI_CMD_PG_CACHE_PROG1 0x80U

#define	ONFI_CMD_PG_CACHE_PROG2 0x15U

#define	ONFI_CMD_CPBK_PROG1 0x85U

#define	ONFI_CMD_CPBK_PROG2 0x10U

#define	ONFI_CMD_MUL_CPBK_PROG1 0x85U

#define	ONFI_CMD_MUL_CPBK_PROG2 0x10U

#define	ONFI_CMD_SMALL_DATA_MV1 0x85U

#define	ONFI_CMD_SMALL_DATA_MV2 0x10U

#define	ONFI_CMD_CHNG_ROW_ADDR 0x85U

#define	ONFI_CMD_VOL_SEL 0xE1U

#define	ONFI_CMD_ODT_CONF 0xE2U

#define	ONFI_CMD_RD_UNIQID 0xEDU

#define	ONFI_CMD_GET_FEATURES 0xEEU

#define	ONFI_CMD_SET_FEATURES 0xEFU

#define	ONFI_CMD_LUN_GET_FEATURES 0xD4U

#define	ONFI_CMD_LUN_SET_FEATURES 0xD5U

#define	ONFI_CMD_RST_LUN 0xFAU

#define	ONFI_CMD_SYN_RST 0xFCU

#define	ONFI_STS_FAIL 0x01U

#define	ONFI_STS_FAILC 0x02U

#define	ONFI_STS_CSP 0x08U

#define	ONFI_STS_VSP 0x10U

#define	ONFI_STS_ARDY 0x20U

#define	ONFI_STS_RDY 0x40U

#define	ONFI_STS_WP 0x80U

#define	ONFI_CRC_LEN 254U

#define	ONFI_PRM_PG_LEN 256U

#define	ONFI_MND_PRM_PGS 3U

#define	ONFI_SIG_LEN 4U

#define	ONFI_CMD_INVALID 0x00U

#define	ONFI_READ_ID_LEN 4U

#define	ONFI_READ_ID_ADDR 0x20U

#define	ONFI_READ_ID_ADDR_CYCLES 1U

#define	ONFI_PRM_PG_ADDR_CYCLES 1U

#define	XQSPIPSU_H_

#define	BYTES256_PER_PAGE 256U

#define	BYTES512_PER_PAGE 512U

#define	BYTES1024_PER_PAGE 1024U

#define	PAGES16_PER_SECTOR 16U

#define	PAGES128_PER_SECTOR 128U

#define	PAGES256_PER_SECTOR 256U

#define	PAGES512_PER_SECTOR 512U

#define	PAGES1024_PER_SECTOR 1024U

#define	NUM_OF_SECTORS2 2U

#define	NUM_OF_SECTORS4 4U

#define	NUM_OF_SECTORS8 8U

#define	NUM_OF_SECTORS16 16U

#define	NUM_OF_SECTORS32 32U

#define	NUM_OF_SECTORS64 64U

#define	NUM_OF_SECTORS128 128U

#define	NUM_OF_SECTORS256 256U

#define	NUM_OF_SECTORS512 512U

#define	NUM_OF_SECTORS1024 1024U

#define	NUM_OF_SECTORS2048 2048U

#define	NUM_OF_SECTORS4096 4096U

#define	NUM_OF_SECTORS8192 8192U

#define	SECTOR_SIZE_64K 0X10000U

#define	SECTOR_SIZE_128K 0X20000U

#define	SECTOR_SIZE_256K 0X40000U

#define	SECTOR_SIZE_512K 0X80000U

#define	XQSPIPSU_READMODE_DMA 0x0U

#define	XQSPIPSU_READMODE_IO 0x1U

#define	XQSPIPSU_SELECT_FLASH_CS_LOWER 0x1U

#define	XQSPIPSU_SELECT_FLASH_CS_UPPER 0x2U

#define	XQSPIPSU_SELECT_FLASH_CS_BOTH 0x3U

#define	XQSPIPSU_SELECT_FLASH_BUS_LOWER 0x1U

#define	XQSPIPSU_SELECT_FLASH_BUS_UPPER 0x2U

#define	XQSPIPSU_SELECT_FLASH_BUS_BOTH 0x3U

#define	XQSPIPSU_SELECT_MODE_SPI 0x1U

#define	XQSPIPSU_SELECT_MODE_DUALSPI 0x2U

#define	XQSPIPSU_SELECT_MODE_QUADSPI 0x4U

#define	XQSPIPSU_GENFIFO_CS_SETUP 0x05U

#define	XQSPIPSU_GENFIFO_CS_HOLD 0x04U

#define	XQSPIPSU_CLK_ACTIVE_LOW_OPTION 0x2U

#define	XQSPIPSU_CLK_PHASE_1_OPTION 0x4U

#define	XQSPIPSU_MANUAL_START_OPTION 0x8U

#define	XQSPIPSU_LQSPI_MODE_OPTION 0x20U

#define	XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB 1U

#define	XQSPIPSU_GENFIFO_EXP_START 0x100U

#define	XQSPIPSU_DMA_BYTES_MAX 0x10000000U

#define	XQSPIPSU_CLK_PRESCALE_2 0x00U

#define	XQSPIPSU_CLK_PRESCALE_4 0x01U

#define	XQSPIPSU_CLK_PRESCALE_8 0x02U

#define	XQSPIPSU_CLK_PRESCALE_16 0x03U

#define	XQSPIPSU_CLK_PRESCALE_32 0x04U

#define	XQSPIPSU_CLK_PRESCALE_64 0x05U

#define	XQSPIPSU_CLK_PRESCALE_128 0x06U

#define	XQSPIPSU_CLK_PRESCALE_256 0x07U

#define	XQSPIPSU_CR_PRESC_MAXIMUM 7U

#define	XQSPIPSU_CONNECTION_MODE_SINGLE 0U

#define	XQSPIPSU_CONNECTION_MODE_STACKED 1U

#define	XQSPIPSU_CONNECTION_MODE_PARALLEL 2U

#define	XQSPIPSU_FREQ_37_5MHZ 37500000U

#define	XQSPIPSU_FREQ_40MHZ 40000000U

#define	XQSPIPSU_FREQ_100MHZ 100000000U

#define	XQSPIPSU_FREQ_150MHZ 150000000U

#define	XQSPIPSU_MSG_FLAG_STRIPE 0x1U

#define	XQSPIPSU_MSG_FLAG_RX 0x2U

#define	XQSPIPSU_MSG_FLAG_TX 0x4U

#define	XQSPIPSU_MSG_FLAG_POLL 0x8U

#define	XQSPIPSU_RXADDR_OVER_32BIT 0x100000000U

#define	XQSPIPSU_SET_WP 1

#define	XQspiPsu_Select(InstancePtr, Mask)

#define	XQspiPsu_Enable(InstancePtr)

#define	XQspiPsu_Disable(InstancePtr)

#define	XQspiPsu_GetLqspiConfigReg(InstancePtr)

#define	XQSPIPSU_HW_H

#define	XQspiPsu_In32 Xil_In32

#define	XQspiPsu_Out32 Xil_Out32

#define	XQspiPsu_ReadReg(BaseAddress, RegOffset) XQspiPsu_In32((BaseAddress) + (RegOffset))

#define	XQspiPsu_WriteReg(BaseAddress, RegOffset, RegisterValue) XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))

#define	MAX_DELAY_CNT 10000000U

#define	XQSPIPSU_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))

Typedefs
typedef void(*	XQspiPsu_StatusHandler) (const void *CallBackRef, u32 StatusEvent, u32 ByteCount)

Enumerations
enum	XNandPsu_DataInterface { XNANDPSU_SDR = 0U , XNANDPSU_NVDDR }

enum	XNandPsu_TimingMode { XNANDPSU_SDR0 = 0U , XNANDPSU_SDR1 , XNANDPSU_SDR2 , XNANDPSU_SDR3 , XNANDPSU_SDR4 , XNANDPSU_SDR5 , XNANDPSU_NVDDR0 , XNANDPSU_NVDDR1 , XNANDPSU_NVDDR2 , XNANDPSU_NVDDR3 , XNANDPSU_NVDDR4 , XNANDPSU_NVDDR5 }

enum	XNandPsu_SWMode { XNANDPSU_POLLING = 0 , XNANDPSU_INTERRUPT }

enum	XNandPsu_DmaMode { XNANDPSU_PIO = 0 , XNANDPSU_SDMA , XNANDPSU_MDMA }

enum	XNandPsu_EccMode { XNANDPSU_NONE = 0 , XNANDPSU_HWECC , XNANDPSU_EZNAND , XNANDPSU_ONDIE }

enum	OnfiCommandList { READ =0 , MULTIPLANE_READ , COPYBACK_READ , CHANGE_READ_COLUMN , CHANGE_READ_COLUMN_ENHANCED , READ_CACHE_RANDOM , READ_CACHE_SEQUENTIAL , READ_CACHE_END , BLOCK_ERASE , MULTIPLANE_BLOCK_ERASE , READ_STATUS , READ_STATUS_ENHANCED , PAGE_PROGRAM , MULTIPLANE_PAGE_PROGRAM , PAGE_CACHE_PROGRAM , COPYBACK_PROGRAM , MULTIPLANE_COPYBACK_PROGRAM , SMALL_DATA_MOVE , CHANGE_WRITE_COLUMN , CHANGE_ROW_ADDR , READ_ID , VOLUME_SELECT , ODT_CONFIGURE , READ_PARAM_PAGE , READ_UNIQUE_ID , GET_FEATURES , SET_FEATURES , LUN_GET_FEATURES , LUN_SET_FEATURES , RESET_LUN , SYN_RESET , RESET , MAX_CMDS }

Functions
s32	XNandPsu_CfgInitialize (XNandPsu InstancePtr, XNandPsu_Config ConfigPtr, u32 EffectiveAddr)

s32	XNandPsu_Erase (XNandPsu *InstancePtr, u64 Offset, u64 Length)

s32	XNandPsu_Write (XNandPsu InstancePtr, u64 Offset, u64 Length, u8 SrcBuf)

s32	XNandPsu_Read (XNandPsu InstancePtr, u64 Offset, u64 Length, u8 DestBuf)

s32	XNandPsu_EraseBlock (XNandPsu *InstancePtr, u32 Target, u32 Block)

s32	XNandPsu_WriteSpareBytes (XNandPsu InstancePtr, u32 Page, u8 Buf)

s32	XNandPsu_ReadSpareBytes (XNandPsu InstancePtr, u32 Page, u8 Buf)

s32	XNandPsu_ChangeTimingMode (XNandPsu *InstancePtr, XNandPsu_DataInterface NewIntf, XNandPsu_TimingMode NewMode)

s32	XNandPsu_GetFeature (XNandPsu InstancePtr, u32 Target, u8 Feature, u8 Buf)

s32	XNandPsu_SetFeature (XNandPsu InstancePtr, u32 Target, u8 Feature, u8 Buf)

s32	XNandPsu_ScanBbt (XNandPsu *InstancePtr)

s32	XNandPsu_MarkBlockBad (XNandPsu *InstancePtr, u32 Block)

void	XNandPsu_EnableDmaMode (XNandPsu *InstancePtr)

void	XNandPsu_DisableDmaMode (XNandPsu *InstancePtr)

void	XNandPsu_EnableEccMode (XNandPsu *InstancePtr)

void	XNandPsu_DisableEccMode (XNandPsu *InstancePtr)

void	XNandPsu_Prepare_Cmd (XNandPsu *InstancePtr, u8 Cmd1, u8 Cmd2, u8 EccState, u8 DmaMode, u8 AddrCycles)

XNandPsu_Config *	XNandPsu_LookupConfig (u16 DevID)

void	XNandPsu_InitBbtDesc (XNandPsu *InstancePtr)

s32	XNandPsu_IsBlockBad (XNandPsu *InstancePtr, u32 Block)

u32	XNandPsu_OnfiParamPageCrc (u8 *ParamBuf, u32 StartOff, u32 Length)

XQspiPsu_Config *	XQspiPsu_LookupConfig (u16 DeviceId)

s32	XQspiPsu_CfgInitialize (XQspiPsu InstancePtr, const XQspiPsu_Config ConfigPtr, UINTPTR EffectiveAddr)

void	XQspiPsu_Reset (XQspiPsu *InstancePtr)

void	XQspiPsu_Abort (XQspiPsu *InstancePtr)

s32	XQspiPsu_PolledTransfer (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 NumMsg)

s32	XQspiPsu_InterruptTransfer (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 NumMsg)

s32	XQspiPsu_InterruptHandler (XQspiPsu *InstancePtr)

void	XQspiPsu_SetStatusHandler (XQspiPsu InstancePtr, void CallBackRef, XQspiPsu_StatusHandler FuncPointer)

s32	XQspiPsu_StartDmaTransfer (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 NumMsg)

s32	XQspiPsu_CheckDmaDone (XQspiPsu *InstancePtr)

s32	XQspiPsu_SetClkPrescaler (const XQspiPsu *InstancePtr, u8 Prescaler)

void	XQspiPsu_SelectFlash (XQspiPsu *InstancePtr, u8 FlashCS, u8 FlashBus)

s32	XQspiPsu_SetOptions (XQspiPsu *InstancePtr, u32 Options)

s32	XQspiPsu_ClearOptions (XQspiPsu *InstancePtr, u32 Options)

u32	XQspiPsu_GetOptions (const XQspiPsu *InstancePtr)

s32	XQspiPsu_SetReadMode (XQspiPsu *InstancePtr, u32 Mode)

void	XQspiPsu_SetWP (const XQspiPsu *InstancePtr, u8 Value)

void	XQspiPsu_WriteProtectToggle (const XQspiPsu *InstancePtr, u32 Toggle)
	This API enables/ disables Write Protect pin on the flash parts.

void	XQspiPsu_Idle (const XQspiPsu *InstancePtr)

void	XQspiPsu_PollDataHandler (XQspiPsu *InstancePtr, u32 StatusReg)

void	XQspiPsu_GenFifoEntryData (XQspiPsu InstancePtr, XQspiPsu_Msg Msg)

void	XQspiPsu_PollDataConfig (XQspiPsu InstancePtr, XQspiPsu_Msg FlashMsg)

void	XQspiPsu_FillTxFifo (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 Size)

void	XQspiPsu_TXSetup (XQspiPsu InstancePtr, XQspiPsu_Msg Msg)

void	XQspiPsu_SetupRxDma (const XQspiPsu InstancePtr, XQspiPsu_Msg Msg)

void	XQspiPsu_Setup64BRxDma (const XQspiPsu InstancePtr, XQspiPsu_Msg Msg)

u32	XQspiPsu_SetIOMode (XQspiPsu InstancePtr, XQspiPsu_Msg Msg)

void	XQspiPsu_RXSetup (XQspiPsu InstancePtr, XQspiPsu_Msg Msg)

void	XQspiPsu_TXRXSetup (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 *GenFifoEntry)

void	XQspiPsu_GenFifoEntryDataLen (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 *GenFifoEntry)

u32	XQspiPsu_CreatePollDataConfig (const XQspiPsu InstancePtr, const XQspiPsu_Msg FlashMsg)

u32	XQspiPsu_SelectSpiMode (u8 SpiMode)

void	XQspiPsu_SetDefaultConfig (XQspiPsu *InstancePtr)

void	XQspiPsu_ReadRxFifo (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, s32 Size)

void	XQspiPsu_IORead (XQspiPsu InstancePtr, XQspiPsu_Msg Msg, u32 StatusReg)

Variables
const OnfiCmdFormat	OnfiCmd [MAX_CMDS]

XQspiPsu_Config	XQspiPsu_ConfigTable [XPAR_XQSPIPSU_NUM_INSTANCES]

Packet Register bit definitions and masks
#define	XNANDPSU_PKT_PKT_SIZE_MASK 0x000007FFU

#define	XNANDPSU_PKT_PKT_CNT_MASK 0x00FFF000U

#define	XNANDPSU_PKT_PKT_CNT_SHIFT 12U

Memory Address Register 1 bit definitions and masks
#define	XNANDPSU_MEM_ADDR1_COL_ADDR_MASK 0x0000FFFFU

#define	XNANDPSU_MEM_ADDR1_PG_ADDR_MASK 0xFFFF0000U

#define	XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT 16U

Memory Address Register 2 bit definitions and masks
#define	XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK 0x000000FFU

#define	XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK 0x01000000U

#define	XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK 0x0E000000U

#define	XNANDPSU_MEM_ADDR2_MODE_MASK 0x30000000U

#define	XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK 0xC0000000U

#define	XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT 30U

#define	XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT 24U

#define	XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_SHIFT 25U

Command Register bit definitions and masks
#define	XNANDPSU_CMD_CMD1_MASK 0x000000FFU

#define	XNANDPSU_CMD_CMD2_MASK 0x0000FF00U

#define	XNANDPSU_CMD_PG_SIZE_MASK 0x03800000U

#define	XNANDPSU_CMD_DMA_EN_MASK 0x0C000000U

#define	XNANDPSU_CMD_ADDR_CYCLES_MASK 0x70000000U

#define	XNANDPSU_CMD_ECC_ON_MASK 0x80000000U

#define	XNANDPSU_CMD_CMD2_SHIFT 8U

#define	XNANDPSU_CMD_PG_SIZE_SHIFT 23U

#define	XNANDPSU_CMD_DMA_EN_SHIFT 26U

#define	XNANDPSU_CMD_ADDR_CYCLES_SHIFT 28U

#define	XNANDPSU_CMD_ECC_ON_SHIFT 31U

Program Register bit definitions and masks
#define	XNANDPSU_PROG_RD_MASK 0x00000001U

#define	XNANDPSU_PROG_MUL_DIE_MASK 0x00000002U

#define	XNANDPSU_PROG_BLK_ERASE_MASK 0x00000004U

#define	XNANDPSU_PROG_RD_STS_MASK 0x00000008U

#define	XNANDPSU_PROG_PG_PROG_MASK 0x00000010U

#define	XNANDPSU_PROG_MUL_DIE_RD_MASK 0x00000020U

#define	XNANDPSU_PROG_RD_ID_MASK 0x00000040U

#define	XNANDPSU_PROG_RD_PRM_PG_MASK 0x00000080U

#define	XNANDPSU_PROG_RST_MASK 0x00000100U

#define	XNANDPSU_PROG_GET_FEATURES_MASK 0x00000200U

#define	XNANDPSU_PROG_SET_FEATURES_MASK 0x00000400U

#define	XNANDPSU_PROG_RD_UNQ_ID_MASK 0x00000800U

#define	XNANDPSU_PROG_RD_STS_ENH_MASK 0x00001000U

#define	XNANDPSU_PROG_RD_INTRLVD_MASK 0x00002000U

#define	XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK 0x00004000U

#define	XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK 0x00008000U

#define	XNANDPSU_PROG_RD_CACHE_START_MASK 0x00010000U

#define	XNANDPSU_PROG_RD_CACHE_SEQ_MASK 0x00020000U

#define	XNANDPSU_PROG_RD_CACHE_RAND_MASK 0x00040000U

#define	XNANDPSU_PROG_RD_CACHE_END_MASK 0x00080000U

#define	XNANDPSU_PROG_SMALL_DATA_MOVE_MASK 0x00100000U

#define	XNANDPSU_PROG_CHNG_ROW_ADDR_MASK 0x00200000U

#define	XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK 0x00400000U

#define	XNANDPSU_PROG_RST_LUN_MASK 0x00800000U

#define	XNANDPSU_PROG_PGM_PG_CLR_MASK 0x01000000U

#define	XNANDPSU_PROG_VOL_SEL_MASK 0x02000000U

#define	XNANDPSU_PROG_ODT_CONF_MASK 0x04000000U

Interrupt Status Enable Register bit definitions and masks
#define	XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

#define	XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

#define	XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK 0x00000004U

#define	XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

#define	XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK 0x00000010U

#define	XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK 0x00000040U

#define	XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK 0x00000080U

Interrupt Signal Enable Register bit definitions and masks
#define	XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

#define	XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

#define	XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK 0x00000004U

#define	XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

#define	XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK 0x00000010U

#define	XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK 0x00000040U

#define	XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK 0x00000080U

Interrupt Status Register bit definitions and masks
#define	XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

#define	XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

#define	XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK 0x00000004U

#define	XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

#define	XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK 0x00000010U

#define	XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK 0x00000040U

#define	XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK 0x00000080U

Interrupt bit definitions and masks
#define	XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

#define	XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

#define	XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK 0x00000004U

#define	XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

#define	XNANDPSU_INTR_ERR_INTR_STS_EN_MASK 0x00000010U

#define	XNANDPSU_INTR_DMA_INT_STS_EN_MASK 0x00000040U

#define	XNANDPSU_INTR_ERR_AHB_STS_EN_MASK 0x00000080U

ID2 Register bit definitions and masks
#define	XNANDPSU_ID2_DEVICE_ID2_MASK 0x000000FFU

Flash Status Register bit definitions and masks
#define	XNANDPSU_FLASH_STS_FLASH_STS_MASK 0x0000FFFFU

Timing Register bit definitions and masks
#define	XNANDPSU_TIMING_TCCS_TIME_MASK 0x00000003U

#define	XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK 0x00000004U

#define	XNANDPSU_TIMING_DQS_BUFF_SEL_MASK 0x00000078U

#define	XNANDPSU_TIMING_TADL_TIME_MASK 0x00007F80U

ECC Register bit definitions and masks
#define	XNANDPSU_ECC_ADDR_MASK 0x0000FFFFU

#define	XNANDPSU_ECC_SIZE_MASK 0x01FF0000U

#define	XNANDPSU_ECC_HAMMING_BCH_MASK 0x02000000U

ECC Error Count Register bit definitions and masks
#define	XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK 0x000000FFU

#define	XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK 0x0000FF00U

ECC Spare Command Register bit definitions and masks
#define	XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK 0x000000FFU

#define	XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK 0x70000000U

Data Interface Register bit definitions and masks
#define	XNANDPSU_DATA_INTF_SDR_MASK 0x00000007U

#define	XNANDPSU_DATA_INTF_NVDDR_MASK 0x00000038U

#define	XNANDPSU_DATA_INTF_NVDDR2_MASK 0x000001C0U

#define	XNANDPSU_DATA_INTF_DATA_INTF_MASK 0x00000600U

#define	XNANDPSU_DATA_INTF_NVDDR_SHIFT 3U

#define	XNANDPSU_DATA_INTF_DATA_INTF_SHIFT 9U

DMA Buffer Boundary Register bit definitions and masks
#define	XNANDPSU_DMA_BUF_BND_BND_MASK 0x00000007U

#define	XNANDPSU_DMA_BUF_BND_4K 0x0U

#define	XNANDPSU_DMA_BUF_BND_8K 0x1U

#define	XNANDPSU_DMA_BUF_BND_16K 0x2U

#define	XNANDPSU_DMA_BUF_BND_32K 0x3U

#define	XNANDPSU_DMA_BUF_BND_64K 0x4U

#define	XNANDPSU_DMA_BUF_BND_128K 0x5U

#define	XNANDPSU_DMA_BUF_BND_256K 0x6U

#define	XNANDPSU_DMA_BUF_BND_512K 0x7U

Slave DMA Configuration Register bit definitions and masks
#define	XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK 0x00000001U

#define	XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK 0x001FFFFEU

#define	XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK 0x00E00000U

#define	XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK 0x0F000000U

#define	XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK 0x10000000U

#define	XNandPsu_ReadReg(BaseAddress, RegOffset) Xil_In32((BaseAddress) + (RegOffset))

#define	XNandPsu_WriteReg(BaseAddress, RegOffset, Data) Xil_Out32(((BaseAddress) + (RegOffset)), (Data))

Device Base Address
Below macros gives QSPI, QSPIPSU base address.
#define	XQSPIPS_BASEADDR 0XFF0F0000U

#define	XQSPIPSU_BASEADDR 0xFF0F0100U

#define	XQSPIPSU_OFFSET 0x100U

XQSPIPS Enable Register information
QSPIPSU Enable Register
#define	XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014U )

#define	XQSPIPS_EN_SHIFT 0U

#define	XQSPIPS_EN_WIDTH 1U

#define	XQSPIPS_EN_MASK 0X00000001U

XQSPIPSU configuration Register information
This register contains bits for configuring GQSPI controller
#define	XQSPIPSU_CFG_OFFSET 0X00000000U

#define	XQSPIPSU_CFG_MODE_EN_SHIFT 30U

#define	XQSPIPSU_CFG_MODE_EN_WIDTH 2U

#define	XQSPIPSU_CFG_MODE_EN_MASK 0XC0000000U

#define	XQSPIPSU_CFG_MODE_EN_DMA_MASK 0X80000000U

#define	XQSPIPSU_CFG_GEN_FIFO_START_MODE_SHIFT 29U

#define	XQSPIPSU_CFG_GEN_FIFO_START_MODE_WIDTH 1U

#define	XQSPIPSU_CFG_GEN_FIFO_START_MODE_MASK 0X20000000U

#define	XQSPIPSU_CFG_START_GEN_FIFO_SHIFT 28U

#define	XQSPIPSU_CFG_START_GEN_FIFO_WIDTH 1U

#define	XQSPIPSU_CFG_START_GEN_FIFO_MASK 0X10000000U

#define	XQSPIPSU_CFG_ENDIAN_SHIFT 26U

#define	XQSPIPSU_CFG_ENDIAN_WIDTH 1U

#define	XQSPIPSU_CFG_ENDIAN_MASK 0X04000000U

#define	XQSPIPSU_CFG_EN_POLL_TO_SHIFT 20U

#define	XQSPIPSU_CFG_EN_POLL_TO_WIDTH 1U

#define	XQSPIPSU_CFG_EN_POLL_TO_MASK 0X00100000U

#define	XQSPIPSU_CFG_WP_HOLD_SHIFT 19U

#define	XQSPIPSU_CFG_WP_HOLD_WIDTH 1U

#define	XQSPIPSU_CFG_WP_HOLD_MASK 0X00080000U

#define	XQSPIPSU_CFG_BAUD_RATE_DIV_SHIFT 3U

#define	XQSPIPSU_CFG_BAUD_RATE_DIV_WIDTH 3U

#define	XQSPIPSU_CFG_BAUD_RATE_DIV_MASK 0X00000038U

#define	XQSPIPSU_CFG_CLK_PHA_SHIFT 2U

#define	XQSPIPSU_CFG_CLK_PHA_WIDTH 1U

#define	XQSPIPSU_CFG_CLK_PHA_MASK 0X00000004U

#define	XQSPIPSU_CFG_CLK_POL_SHIFT 1U

#define	XQSPIPSU_CFG_CLK_POL_WIDTH 1U

#define	XQSPIPSU_CFG_CLK_POL_MASK 0X00000002U

XQSPIPSU LQSPI Register information
This register contains bits for configuring LQSPI
#define	XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U

#define	XQSPIPSU_LQSPI_CR_LINEAR_MASK 0x80000000U

#define	XQSPIPSU_LQSPI_CR_TWO_MEM_MASK 0x40000000U

#define	XQSPIPSU_LQSPI_CR_SEP_BUS_MASK 0x20000000U

#define	XQSPIPSU_LQSPI_CR_U_PAGE_MASK 0x10000000U

#define	XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK 0x01000000U

#define	XQSPIPSU_LQSPI_CR_MODE_EN_MASK 0x02000000U

#define	XQSPIPSU_LQSPI_CR_MODE_ON_MASK 0x01000000U

#define	XQSPIPSU_LQSPI_CR_MODE_BITS_MASK 0x00FF0000U

#define	XQSPIPS_LQSPI_CR_INST_MASK 0x000000FFU

#define	XQSPIPS_LQSPI_CR_RST_STATE 0x80000003U

#define	XQSPIPS_LQSPI_CR_4_BYTE_STATE 0x88000013U

#define	XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1U

XQSPIPSU Interrupt Status Register information
QSPIPSU Interrupt Status Register
#define	XQSPIPSU_ISR_OFFSET 0X00000004U

#define	XQSPIPSU_ISR_RXEMPTY_SHIFT 11U

#define	XQSPIPSU_ISR_RXEMPTY_WIDTH 1U

#define	XQSPIPSU_ISR_RXEMPTY_MASK 0X00000800U

#define	XQSPIPSU_ISR_GENFIFOFULL_SHIFT 10U

#define	XQSPIPSU_ISR_GENFIFOFULL_WIDTH 1U

#define	XQSPIPSU_ISR_GENFIFOFULL_MASK 0X00000400U

#define	XQSPIPSU_ISR_GENFIFONOT_FULL_SHIFT 9U

#define	XQSPIPSU_ISR_GENFIFONOT_FULL_WIDTH 1U

#define	XQSPIPSU_ISR_GENFIFONOT_FULL_MASK 0X00000200U

#define	XQSPIPSU_ISR_TXEMPTY_SHIFT 8U

#define	XQSPIPSU_ISR_TXEMPTY_WIDTH 1U

#define	XQSPIPSU_ISR_TXEMPTY_MASK 0X00000100U

#define	XQSPIPSU_ISR_GENFIFOEMPTY_SHIFT 7U

#define	XQSPIPSU_ISR_GENFIFOEMPTY_WIDTH 1U

#define	XQSPIPSU_ISR_GENFIFOEMPTY_MASK 0X00000080U

#define	XQSPIPSU_ISR_RXFULL_SHIFT 5U

#define	XQSPIPSU_ISR_RXFULL_WIDTH 1U

#define	XQSPIPSU_ISR_RXFULL_MASK 0X00000020U

#define	XQSPIPSU_ISR_RXNEMPTY_SHIFT 4U

#define	XQSPIPSU_ISR_RXNEMPTY_WIDTH 1U

#define	XQSPIPSU_ISR_RXNEMPTY_MASK 0X00000010U

#define	XQSPIPSU_ISR_TXFULL_SHIFT 3U

#define	XQSPIPSU_ISR_TXFULL_WIDTH 1U

#define	XQSPIPSU_ISR_TXFULL_MASK 0X00000008U

#define	XQSPIPSU_ISR_TXNOT_FULL_SHIFT 2U

#define	XQSPIPSU_ISR_TXNOT_FULL_WIDTH 1U

#define	XQSPIPSU_ISR_TXNOT_FULL_MASK 0X00000004U

#define	XQSPIPSU_ISR_POLL_TIME_EXPIRE_SHIFT 1U

#define	XQSPIPSU_ISR_POLL_TIME_EXPIRE_WIDTH 1U

#define	XQSPIPSU_ISR_POLL_TIME_EXPIRE_MASK 0X00000002U

#define	XQSPIPSU_ISR_WR_TO_CLR_MASK 0X00000002U

XQSPIPSU Interrupt Enable Register information
This register bits for enabling interrupts
#define	XQSPIPSU_IER_OFFSET 0X00000008U

#define	XQSPIPSU_IER_RXEMPTY_SHIFT 11U

#define	XQSPIPSU_IER_RXEMPTY_WIDTH 1U

#define	XQSPIPSU_IER_RXEMPTY_MASK 0X00000800U

#define	XQSPIPSU_IER_GENFIFOFULL_SHIFT 10U

#define	XQSPIPSU_IER_GENFIFOFULL_WIDTH 1U

#define	XQSPIPSU_IER_GENFIFOFULL_MASK 0X00000400U

#define	XQSPIPSU_IER_GENFIFONOT_FULL_SHIFT 9U

#define	XQSPIPSU_IER_GENFIFONOT_FULL_WIDTH 1U

#define	XQSPIPSU_IER_GENFIFONOT_FULL_MASK 0X00000200U

#define	XQSPIPSU_IER_TXEMPTY_SHIFT 8U

#define	XQSPIPSU_IER_TXEMPTY_WIDTH 1U

#define	XQSPIPSU_IER_TXEMPTY_MASK 0X00000100U

#define	XQSPIPSU_IER_GENFIFOEMPTY_SHIFT 7U

#define	XQSPIPSU_IER_GENFIFOEMPTY_WIDTH 1U

#define	XQSPIPSU_IER_GENFIFOEMPTY_MASK 0X00000080U

#define	XQSPIPSU_IER_RXFULL_SHIFT 5U

#define	XQSPIPSU_IER_RXFULL_WIDTH 1U

#define	XQSPIPSU_IER_RXFULL_MASK 0X00000020U

#define	XQSPIPSU_IER_RXNEMPTY_SHIFT 4U

#define	XQSPIPSU_IER_RXNEMPTY_WIDTH 1U

#define	XQSPIPSU_IER_RXNEMPTY_MASK 0X00000010U

#define	XQSPIPSU_IER_TXFULL_SHIFT 3U

#define	XQSPIPSU_IER_TXFULL_WIDTH 1U

#define	XQSPIPSU_IER_TXFULL_MASK 0X00000008U

#define	XQSPIPSU_IER_TXNOT_FULL_SHIFT 2U

#define	XQSPIPSU_IER_TXNOT_FULL_WIDTH 1U

#define	XQSPIPSU_IER_TXNOT_FULL_MASK 0X00000004U

#define	XQSPIPSU_IER_POLL_TIME_EXPIRE_SHIFT 1U

#define	XQSPIPSU_IER_POLL_TIME_EXPIRE_WIDTH 1U

#define	XQSPIPSU_IER_POLL_TIME_EXPIRE_MASK 0X00000002U

XQSPIPSU Interrupt Disable Register information
This register bits for disabling interrupts
#define	XQSPIPSU_IDR_OFFSET 0X0000000CU

#define	XQSPIPSU_IDR_RXEMPTY_SHIFT 11U

#define	XQSPIPSU_IDR_RXEMPTY_WIDTH 1U

#define	XQSPIPSU_IDR_RXEMPTY_MASK 0X00000800U

#define	XQSPIPSU_IDR_GENFIFOFULL_SHIFT 10U

#define	XQSPIPSU_IDR_GENFIFOFULL_WIDTH 1U

#define	XQSPIPSU_IDR_GENFIFOFULL_MASK 0X00000400U

#define	XQSPIPSU_IDR_GENFIFONOT_FULL_SHIFT 9U

#define	XQSPIPSU_IDR_GENFIFONOT_FULL_WIDTH 1U

#define	XQSPIPSU_IDR_GENFIFONOT_FULL_MASK 0X00000200U

#define	XQSPIPSU_IDR_TXEMPTY_SHIFT 8U

#define	XQSPIPSU_IDR_TXEMPTY_WIDTH 1U

#define	XQSPIPSU_IDR_TXEMPTY_MASK 0X00000100U

#define	XQSPIPSU_IDR_GENFIFOEMPTY_SHIFT 7U

#define	XQSPIPSU_IDR_GENFIFOEMPTY_WIDTH 1U

#define	XQSPIPSU_IDR_GENFIFOEMPTY_MASK 0X00000080U

#define	XQSPIPSU_IDR_RXFULL_SHIFT 5U

#define	XQSPIPSU_IDR_RXFULL_WIDTH 1U

#define	XQSPIPSU_IDR_RXFULL_MASK 0X00000020U

#define	XQSPIPSU_IDR_RXNEMPTY_SHIFT 4U

#define	XQSPIPSU_IDR_RXNEMPTY_WIDTH 1U

#define	XQSPIPSU_IDR_RXNEMPTY_MASK 0X00000010U

#define	XQSPIPSU_IDR_TXFULL_SHIFT 3U

#define	XQSPIPSU_IDR_TXFULL_WIDTH 1U

#define	XQSPIPSU_IDR_TXFULL_MASK 0X00000008U

#define	XQSPIPSU_IDR_TXNOT_FULL_SHIFT 2U

#define	XQSPIPSU_IDR_TXNOT_FULL_WIDTH 1U

#define	XQSPIPSU_IDR_TXNOT_FULL_MASK 0X00000004U

#define	XQSPIPSU_IDR_POLL_TIME_EXPIRE_SHIFT 1U

#define	XQSPIPSU_IDR_POLL_TIME_EXPIRE_WIDTH 1U

#define	XQSPIPSU_IDR_POLL_TIME_EXPIRE_MASK 0X00000002U

#define	XQSPIPSU_IDR_ALL_MASK 0X0FBEU

XQSPIPSU Interrupt Mask Register information
This register bits for masking interrupts
#define	XQSPIPSU_IMR_OFFSET 0X00000010U

#define	XQSPIPSU_IMR_RXEMPTY_SHIFT 11U

#define	XQSPIPSU_IMR_RXEMPTY_WIDTH 1U

#define	XQSPIPSU_IMR_RXEMPTY_MASK 0X00000800U

#define	XQSPIPSU_IMR_GENFIFOFULL_SHIFT 10U

#define	XQSPIPSU_IMR_GENFIFOFULL_WIDTH 1U

#define	XQSPIPSU_IMR_GENFIFOFULL_MASK 0X00000400U

#define	XQSPIPSU_IMR_GENFIFONOT_FULL_SHIFT 9U

#define	XQSPIPSU_IMR_GENFIFONOT_FULL_WIDTH 1U

#define	XQSPIPSU_IMR_GENFIFONOT_FULL_MASK 0X00000200U

#define	XQSPIPSU_IMR_TXEMPTY_SHIFT 8U

#define	XQSPIPSU_IMR_TXEMPTY_WIDTH 1U

#define	XQSPIPSU_IMR_TXEMPTY_MASK 0X00000100U

#define	XQSPIPSU_IMR_GENFIFOEMPTY_SHIFT 7U

#define	XQSPIPSU_IMR_GENFIFOEMPTY_WIDTH 1U

#define	XQSPIPSU_IMR_GENFIFOEMPTY_MASK 0X00000080U

#define	XQSPIPSU_IMR_RXFULL_SHIFT 5U

#define	XQSPIPSU_IMR_RXFULL_WIDTH 1U

#define	XQSPIPSU_IMR_RXFULL_MASK 0X00000020U

#define	XQSPIPSU_IMR_RXNEMPTY_SHIFT 4U

#define	XQSPIPSU_IMR_RXNEMPTY_WIDTH 1U

#define	XQSPIPSU_IMR_RXNEMPTY_MASK 0X00000010U

#define	XQSPIPSU_IMR_TXFULL_SHIFT 3U

#define	XQSPIPSU_IMR_TXFULL_WIDTH 1U

#define	XQSPIPSU_IMR_TXFULL_MASK 0X00000008U

#define	XQSPIPSU_IMR_TXNOT_FULL_SHIFT 2U

#define	XQSPIPSU_IMR_TXNOT_FULL_WIDTH 1U

#define	XQSPIPSU_IMR_TXNOT_FULL_MASK 0X00000004U

#define	XQSPIPSU_IMR_POLL_TIME_EXPIRE_SHIFT 1U

#define	XQSPIPSU_IMR_POLL_TIME_EXPIRE_WIDTH 1U

#define	XQSPIPSU_IMR_POLL_TIME_EXPIRE_MASK 0X00000002U

XQSPIPSU Enable Register information
This register bits for enabling QSPI controller
#define	XQSPIPSU_EN_OFFSET 0X00000014U

#define	XQSPIPSU_EN_SHIFT 0U

#define	XQSPIPSU_EN_WIDTH 1U

#define	XQSPIPSU_EN_MASK 0X00000001U

XQSPIPSU TX Data Register information
This register bits for configuring TXFIFO
#define	XQSPIPSU_TXD_OFFSET 0X0000001CU

#define	XQSPIPSU_TXD_SHIFT 0U

#define	XQSPIPSU_TXD_WIDTH 32U

#define	XQSPIPSU_TXD_MASK 0XFFFFFFFFU

#define	XQSPIPSU_TXD_DEPTH 64

XQSPIPSU RX Data Register information
This register bits for configuring RXFIFO
#define	XQSPIPSU_RXD_OFFSET 0X00000020U

#define	XQSPIPSU_RXD_SHIFT 0U

#define	XQSPIPSU_RXD_WIDTH 32U

#define	XQSPIPSU_RXD_MASK 0XFFFFFFFFU

XQSPIPSU TX/RX Threshold Register information
This register bits for configuring TX/RX Threshold
#define	XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028U

#define	XQSPIPSU_TX_FIFO_THRESHOLD_SHIFT 0U

#define	XQSPIPSU_TX_FIFO_THRESHOLD_WIDTH 6U

#define	XQSPIPSU_TX_FIFO_THRESHOLD_MASK 0X0000003FU

#define	XQSPIPSU_TX_FIFO_THRESHOLD_RESET_VAL 0X01U

#define	XQSPIPSU_RX_THRESHOLD_OFFSET 0X0000002CU

#define	XQSPIPSU_RX_FIFO_THRESHOLD_SHIFT 0U

#define	XQSPIPSU_RX_FIFO_THRESHOLD_WIDTH 6U

#define	XQSPIPSU_RX_FIFO_THRESHOLD_MASK 0X0000003FU

#define	XQSPIPSU_RX_FIFO_THRESHOLD_RESET_VAL 0X01U

#define	XQSPIPSU_RXFIFO_THRESHOLD_OPT 32U

XQSPIPSU GPIO Register information
#define	XQSPIPSU_GPIO_OFFSET 0X00000030U

#define	XQSPIPSU_GPIO_WP_N_SHIFT 0U

#define	XQSPIPSU_GPIO_WP_N_WIDTH 1U

#define	XQSPIPSU_GPIO_WP_N_MASK 0X00000001U

XQSPIPSU Loopback Master Clock Delay Adjustment Register information
This register contains bits for configuring loopback
#define	XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038U

#define	XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_SHIFT 5U

#define	XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_WIDTH 1U

#define	XQSPIPSU_LPBK_DLY_ADJ_USE_LPBK_MASK 0X00000020U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY1_SHIFT 3U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY1_WIDTH 2U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY1_MASK 0X00000018U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY0_SHIFT 0U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY0_WIDTH 3U

#define	XQSPIPSU_LPBK_DLY_ADJ_DLY0_MASK 0X00000007U

XQSPIPSU GEN_FIFO Register information
This register contains bits for configuring GENFIFO
#define	XQSPIPSU_GEN_FIFO_OFFSET 0X00000040U

#define	XQSPIPSU_GEN_FIFO_DATA_SHIFT 0U

#define	XQSPIPSU_GEN_FIFO_DATA_WIDTH 20U

#define	XQSPIPSU_GEN_FIFO_DATA_MASK 0X000FFFFFU

XQSPIPSU Select Register information
This register contains bits for selection GQSPI/LQSPI controller
#define	XQSPIPSU_SEL_OFFSET 0X00000044U

#define	XQSPIPSU_SEL_SHIFT 0U

#define	XQSPIPSU_SEL_WIDTH 1U

#define	XQSPIPSU_SEL_LQSPI_MASK 0X0U

#define	XQSPIPSU_SEL_GQSPI_MASK 0X00000001U

XQSPIPSU FIFO Control Register information
This register contains bits for controlling TXFIFO and RXFIFO
#define	XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004CU

#define	XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_SHIFT 2U

#define	XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_WIDTH 1U

#define	XQSPIPSU_FIFO_CTRL_RST_RX_FIFO_MASK 0X00000004U

#define	XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_SHIFT 1U

#define	XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_WIDTH 1U

#define	XQSPIPSU_FIFO_CTRL_RST_TX_FIFO_MASK 0X00000002U

#define	XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_SHIFT 0U

#define	XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_WIDTH 1U

#define	XQSPIPSU_FIFO_CTRL_RST_GEN_FIFO_MASK 0X00000001U

XQSPIPSU GENFIFO Threshold Register information
This register contains bits for configuring GENFIFO threshold
#define	XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050U

#define	XQSPIPSU_GEN_FIFO_THRESHOLD_SHIFT 0U

#define	XQSPIPSU_GEN_FIFO_THRESHOLD_WIDTH 5U

#define	XQSPIPSU_GEN_FIFO_THRESHOLD_MASK 0X0000001FU

#define	XQSPIPSU_GEN_FIFO_THRESHOLD_RESET_VAL 0X10U

XQSPIPSU Poll configuration Register information
This register contains bits for configuring Poll feature
#define	XQSPIPSU_POLL_CFG_OFFSET 0X00000054U

#define	XQSPIPSU_POLL_CFG_EN_MASK_UPPER_SHIFT 31U

#define	XQSPIPSU_POLL_CFG_EN_MASK_UPPER_WIDTH 1U

#define	XQSPIPSU_POLL_CFG_EN_MASK_UPPER_MASK 0X80000000U

#define	XQSPIPSU_POLL_CFG_EN_MASK_LOWER_SHIFT 30U

#define	XQSPIPSU_POLL_CFG_EN_MASK_LOWER_WIDTH 1U

#define	XQSPIPSU_POLL_CFG_EN_MASK_LOWER_MASK 0X40000000U

#define	XQSPIPSU_POLL_CFG_MASK_EN_SHIFT 8U

#define	XQSPIPSU_POLL_CFG_MASK_EN_WIDTH 8U

#define	XQSPIPSU_POLL_CFG_MASK_EN_MASK 0X0000FF00U

#define	XQSPIPSU_POLL_CFG_DATA_VALUE_SHIFT 0U

#define	XQSPIPSU_POLL_CFG_DATA_VALUE_WIDTH 8U

#define	XQSPIPSU_POLL_CFG_DATA_VALUE_MASK 0X000000FFU

#define	XQSPIPSU_P_TO_OFFSET 0X00000058U

#define	XQSPIPSU_P_TO_VALUE_SHIFT 0U

#define	XQSPIPSU_P_TO_VALUE_WIDTH 32U

#define	XQSPIPSU_P_TO_VALUE_MASK 0XFFFFFFFFU

XQSPIPSU Transfer Status Register information
This register contains bits for transfer status
#define	XQSPIPSU_XFER_STS_OFFSET 0X0000005CU

#define	XQSPIPSU_XFER_STS_PEND_BYTES_SHIFT 0U

#define	XQSPIPSU_XFER_STS_PEND_BYTES_WIDTH 32U

#define	XQSPIPSU_XFER_STS_PEND_BYTES_MASK 0XFFFFFFFFU

XQSPIPSU GEN_FIFO Snapshot Register information
This register contains bits for configuring GENFIFO
#define	XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060U

#define	XQSPIPSU_GF_SNAPSHOT_SHIFT 0U

#define	XQSPIPSU_GF_SNAPSHOT_WIDTH 20U

#define	XQSPIPSU_GF_SNAPSHOT_MASK 0X000FFFFFU

XQSPIPSU Receive Data Copy Register information
#define	XQSPIPSU_RX_COPY_OFFSET 0X00000064U

#define	XQSPIPSU_RX_COPY_UPPER_SHIFT 8U

#define	XQSPIPSU_RX_COPY_UPPER_WIDTH 8U

#define	XQSPIPSU_RX_COPY_UPPER_MASK 0X0000FF00U

#define	XQSPIPSU_RX_COPY_LOWER_SHIFT 0U

#define	XQSPIPSU_RX_COPY_LOWER_WIDTH 8U

#define	XQSPIPSU_RX_COPY_LOWER_MASK 0X000000FFU

XQSPIPSU Module Identification Register information
#define	XQSPIPSU_MOD_ID_OFFSET 0X000000FCU

#define	XQSPIPSU_MOD_ID_SHIFT 0U

#define	XQSPIPSU_MOD_ID_WIDTH 32U

#define	XQSPIPSU_MOD_ID_MASK 0XFFFFFFFFU

XQSPIPSU DMA Transfer Register information
This register contains bits for configuring DMA
#define	XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_WIDTH 30U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_MASK 0XFFFFFFFCU

#define	XQSPIPSU_QSPIDMA_DST_SIZE_OFFSET 0X00000704U

#define	XQSPIPSU_QSPIDMA_DST_SIZE_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_SIZE_WIDTH 27U

#define	XQSPIPSU_QSPIDMA_DST_SIZE_MASK 0X1FFFFFFCU

#define	XQSPIPSU_QSPIDMA_DST_STS_OFFSET 0X00000708U

#define	XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_SHIFT 13U

#define	XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_WIDTH 3U

#define	XQSPIPSU_QSPIDMA_DST_STS_DONE_CNT_MASK 0X0000E000U

#define	XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_SHIFT 5U

#define	XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_WIDTH 8U

#define	XQSPIPSU_QSPIDMA_DST_STS_DST_FIFO_LEVEL_MASK 0X00001FE0U

#define	XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_WIDTH 4U

#define	XQSPIPSU_QSPIDMA_DST_STS_WR_OUTSTANDING_MASK 0X0000001EU

#define	XQSPIPSU_QSPIDMA_DST_STS_BUSY_SHIFT 0U

#define	XQSPIPSU_QSPIDMA_DST_STS_BUSY_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_STS_BUSY_MASK 0X00000001U

#define	XQSPIPSU_QSPIDMA_DST_STS_WTC 0xE000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_OFFSET 0X0000070CU

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_SHIFT 25U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_WIDTH 7U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_LVL_HIT_THRESHOLD_MASK 0XFE000000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_SHIFT 24U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_APB_ERR_RESP_MASK 0X01000000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_SHIFT 23U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_ENDIAN_MASK 0X00800000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_SHIFT 22U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_AXI_BRST_TYPE_MASK 0X00400000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_SHIFT 10U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_WIDTH 12U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_TO_VAL_MASK 0X003FFC00U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_WIDTH 8U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_FIFO_THRESHOLD_MASK 0X000003FCU

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_STRM_MASK 0X00000002U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_SHIFT 0U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_PAUSE_MEM_MASK 0X00000001U

#define	XQSPIPSU_QSPIDMA_DST_CTRL_RESET_VAL 0x403FFA00U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_OFFSET 0X00000714U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_SHIFT 7U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_FIFO_OF_MASK 0X00000080U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_SHIFT 6U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_INVALID_APB_MASK 0X00000040U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_SHIFT 5U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_THRESHOLD_HIT_MASK 0X00000020U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_SHIFT 4U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_MEM_MASK 0X00000010U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_SHIFT 3U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_TO_STRM_MASK 0X00000008U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_AXI_BRESP_ERR_MASK 0X00000004U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_DONE_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_DONE_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_STS_DONE_MASK 0X00000002U

#define	XQSPIPSU_QSPIDMA_DST_INTR_ERR_MASK 0X000000FCU

#define	XQSPIPSU_QSPIDMA_DST_INTR_ALL_MASK 0X000000FEU

#define	XQSPIPSU_QSPIDMA_DST_I_EN_OFFSET 0X00000718U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_SHIFT 7U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_FIFO_OF_MASK 0X00000080U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_SHIFT 6U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_INVALID_APB_MASK 0X00000040U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_SHIFT 5U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_THRESHOLD_HIT_MASK 0X00000020U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_SHIFT 4U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_MEM_MASK 0X00000010U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_SHIFT 3U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_TO_STRM_MASK 0X00000008U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_AXI_BRESP_ERR_MASK 0X00000004U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_DONE_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_DONE_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_EN_DONE_MASK 0X00000002U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_OFFSET 0X0000071CU

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_SHIFT 7U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_FIFO_OF_MASK 0X00000080U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_SHIFT 6U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_INVALID_APB_MASK 0X00000040U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_SHIFT 5U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_THRESHOLD_HIT_MASK 0X00000020U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_SHIFT 4U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_MEM_MASK 0X00000010U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_SHIFT 3U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_TO_STRM_MASK 0X00000008U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_AXI_BRESP_ERR_MASK 0X00000004U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_I_DIS_DONE_MASK 0X00000002U

#define	XQSPIPSU_QSPIDMA_DST_IMR_OFFSET 0X00000720U

#define	XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_SHIFT 7U

#define	XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_FIFO_OF_MASK 0X00000080U

#define	XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_SHIFT 6U

#define	XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_INVALID_APB_MASK 0X00000040U

#define	XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_SHIFT 5U

#define	XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_THRESHOLD_HIT_MASK 0X00000020U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_SHIFT 4U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_MEM_MASK 0X00000010U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_SHIFT 3U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_TO_STRM_MASK 0X00000008U

#define	XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_SHIFT 2U

#define	XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_AXI_BRESP_ERR_MASK 0X00000004U

#define	XQSPIPSU_QSPIDMA_DST_IMR_DONE_SHIFT 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_DONE_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_IMR_DONE_MASK 0X00000002U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_OFFSET 0X00000724U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_SHIFT 27U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMASA_MASK 0X08000000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_SHIFT 24U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_WIDTH 3U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_AWCACHE_MASK 0X07000000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_SHIFT 22U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_WIDTH 1U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_EN_MASK 0X00400000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_SHIFT 19U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_WIDTH 3U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAB_MASK 0X00380000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_SHIFT 16U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_WIDTH 3U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_RAM_EMAA_MASK 0X00070000U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_SHIFT 4U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_WIDTH 12U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_TO_PRE_MASK 0X0000FFF0U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_SHIFT 0U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_WIDTH 4U

#define	XQSPIPSU_QSPIDMA_DST_CTRL2_MAX_OUTS_CMDS_MASK 0X0000000FU

#define	XQSPIPSU_QSPIDMA_DST_ADDR_MSB_OFFSET 0X00000728U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_MSB_SHIFT 0U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_MSB_WIDTH 12U

#define	XQSPIPSU_QSPIDMA_DST_ADDR_MSB_MASK 0X00000FFFU

#define	XQSPIPSU_QSPIDMA_FUTURE_ECO_OFFSET 0X00000EFCU

#define	XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_SHIFT 0U

#define	XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_WIDTH 32U

#define	XQSPIPSU_QSPIDMA_FUTURE_ECO_VAL_MASK 0XFFFFFFFFU

XQSPIPSU Generic FIFO masks information
Generic FIFO masks information
#define	XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFFU

#define	XQSPIPSU_GENFIFO_DATA_XFER 0x100U

#define	XQSPIPSU_GENFIFO_EXP 0x200U

#define	XQSPIPSU_GENFIFO_MODE_SPI 0x400U

#define	XQSPIPSU_GENFIFO_MODE_DUALSPI 0x800U

#define	XQSPIPSU_GENFIFO_MODE_QUADSPI 0xC00U

#define	XQSPIPSU_GENFIFO_MODE_MASK 0xC00U /* And with ~MASK first */

#define	XQSPIPSU_GENFIFO_CS_LOWER 0x1000U

#define	XQSPIPSU_GENFIFO_CS_UPPER 0x2000U

#define	XQSPIPSU_GENFIFO_BUS_LOWER 0x4000U

#define	XQSPIPSU_GENFIFO_BUS_UPPER 0x8000U

#define	XQSPIPSU_GENFIFO_BUS_BOTH 0xC000U /* inverse is no bus */

#define	XQSPIPSU_GENFIFO_BUS_MASK 0xC000U /* And with ~MASK first */

#define	XQSPIPSU_GENFIFO_TX 0x10000U /* inverse is zero pump */

#define	XQSPIPSU_GENFIFO_RX 0x20000U /* inverse is RX discard */

#define	XQSPIPSU_GENFIFO_STRIPE 0x40000U

#define	XQSPIPSU_GENFIFO_POLL 0x80000U

XQSPIPSU RX Data Delay Register information
#define	XQSPIPSU_DATA_DLY_ADJ_OFFSET 0X000000F8U

#define	XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_SHIFT 31U

#define	XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_WIDTH 1U

#define	XQSPIPSU_DATA_DLY_ADJ_USE_DATA_DLY_MASK 0X80000000U

#define	XQSPIPSU_DATA_DLY_ADJ_DLY_SHIFT 28U

#define	XQSPIPSU_DATA_DLY_ADJ_DLY_WIDTH 3U

#define	XQSPIPSU_DATA_DLY_ADJ_DLY_MASK 0X70000000U

TAPDLY Bypass register information
#define	IOU_TAPDLY_BYPASS_OFFSET 0X00000390U

#define	IOU_TAPDLY_BYPASS_LQSPI_RX_SHIFT 0X02U

#define	IOU_TAPDLY_BYPASS_LQSPI_RX_WIDTH 0X01U

#define	IOU_TAPDLY_BYPASS_LQSPI_RX_MASK 0x00000004U

#define	IOU_TAPDLY_RESET_STATE 0x7U

Detailed Description

This file implements a driver to support Arasan NAND controller present in Zynq Ultrascale Mp.

Driver Initialization

The function call XNandPsu_CfgInitialize() should be called by the application before any other function in the driver. The initialization function takes device specific data (like device id, instance id, and base address) and initializes the XNandPsu instance with the device specific data.

Device Geometry

NAND flash device is memory device and it is segmented into areas called Logical Unit(s) (LUN) and further in to blocks and pages. A NAND flash device can have multiple LUN. LUN is sequential raw of multiple blocks of the same size. A block is the smallest erasable unit of data within the Flash array of a LUN. The size of each block is based on a power of 2. There is no restriction on the number of blocks within the LUN. A block contains a number of pages. A page is the smallest addressable unit for read and program operations. The arrangement of LUN, blocks, and pages is referred to by this module as the part's geometry.

The cells within the part can be programmed from a logic 1 to a logic 0 and not the other way around. To change a cell back to a logic 1, the entire block containing that cell must be erased. When a block is erased all bytes contain the value 0xFF. The number of times a block can be erased is finite. Eventually the block will wear out and will no longer be capable of erasure. As of this writing, the typical flash block can be erased 100,000 or more times.

The jobs done by this driver typically are:

8-bit operational mode
Read, Write, and Erase operation

Write Operation

The write call can be used to write a minimum of one byte and a maximum entire flash. If the address offset specified to write is out of flash or if the number of bytes specified from the offset exceed flash boundaries an error is reported back to the user. The write is blocking in nature in that the control is returned back to user only after the write operation is completed successfully or an error is reported.

Read Operation

The read call can be used to read a minimum of one byte and maximum of entire flash. If the address offset specified to read is out of flash or if the number of bytes specified from the offset exceed flash boundaries an error is reported back to the user. The read is blocking in nature in that the control is returned back to user only after the read operation is completed successfully or an error is reported.

Erase Operation

The erase operations are provided to erase a Block in the Flash memory. The erase call is blocking in nature in that the control is returned back to user only after the erase operation is completed successfully or an error is reported.

Note: Driver has been renamed to nandpsu after change in naming convention.

This driver is intended to be RTOS and processor independent. It works with physical addresses only. Any needs for dynamic memory management, threads, mutual exclusion, virtual memory, cache control, or HW write protection management must be satisfied by the layer above this driver.

  MODIFICATION HISTORY:

  Ver   Who    Date    Changes
  ----- ----   ----------  -----------------------------------------------
  1.0   nm     05/06/2014  First release
  2.0   sb     01/12/2015  Removed Null checks for Buffer passed
               as parameter to Read API's
XNandPsu_Read()
XNandPsu_ReadPage
               Modified
XNandPsu_SetFeature()
XNandPsu_GetFeature()
               and made them public.
               Removed Failure Return for BCF Error check in
               XNandPsu_ReadPage() and added BCH_Error counter
               in the instance pointer structure.
               Added XNandPsu_Prepare_Cmd API
               Replaced
XNandPsu_IntrStsEnable
XNandPsu_IntrStsClear
XNandPsu_IntrClear
XNandPsu_SetProgramReg
               with XNandPsu_WriteReg call
               Modified xnandpsu.c file API's with above changes.
               Corrected the program command for Set Feature API.
               Modified
XNandPsu_OnfiReadStatus
XNandPsu_GetFeature
XNandPsu_SetFeature
               to add support for DDR mode.
               Changed Convention for SLC/MLC
               SLC --> HAMMING
               MLC --> BCH
               SlcMlc --> IsBCH
               Added support for writing BBT signature and version
               in page section by enabling XNANDPSU_BBT_NO_OOB.
               Removed extra DMA mode initialization from
               the XNandPsu_CfgInitialize API.
               Modified
XNandPsu_SetEccAddrSize
               ECC address now is calculated based upon the
               size of spare area
               Modified Block Erase API, removed clearing of
               packet register before erase.
               Clearing Data Interface Register before
               XNandPsu_OnfiReset call.
               Modified XNandPsu_ChangeTimingMode API supporting
               SDR and NVDDR interface for timing modes 0 to 5.
               Modified Bbt Signature and Version Offset value for
               Oob and No-Oob region.
  1.0   kpc    17/06/2015  Increased the timeout for complete event to avoid
               timeout errors for erase operation on slower devices.
  1.1   mi     09/16/16 Removed compilation warnings with extra compiler flags.
  1.1   nsk    11/07/16    Change memcpy to Xil_MemCpy, CR#960462
  1.2   nsk    01/19/17    Fix for the failure of reading nand first redundant
                           parameter page. CR#966603
        ms     02/12/17    Fix for the compilation warning in _g.c file.
        ms     03/17/17    Added readme.txt file in examples folder for doxygen
                           generation.
        ms     04/10/17    Modified Comment lines in nandpsu_example.c to
                           follow doxygen rules.
  1.2   nsk    08/08/17    Added support to import example in SDK
  1.4   nsk    04/10/18    Added ICCARM compiler support. CR#997552.
  1.5   mus    11/08/18    Updated BBT signature array size  in
                           XNandPsu_BbtDesc structure to fix the compilation
                           warnings.
# 1.6   sd     06/02/20    Added Clock support
  1.6   sd     20/03/20    Added compilation flag
  1.8   sg     03/18/21    Added validation check for parameter page.
  1.9   akm    07/15/21    Initialize NandInstPtr with Data Interface & Timing mode info.
  1.10  akm    10/20/21    Fix gcc warnings.
  1.10  akm    12/21/21    Validate input parameters before use.
  1.10  akm    01/05/22    Remove assert checks form static and internal APIs.
  1.11  akm    03/31/22    Fix unused parameter warning.
  1.11  akm    03/31/22    Fix misleading-indentation warning.

This file implements the Bad Block Management(BBM) functionality. This is
similar to the Bad Block Management which is a part of the MTD subsystem in
Linux.  The factory marked bad blocks are scanned initially and a Bad Block
Table(BBT) is created in the memory.  This table is also written to the flash
so that upon reboot, the BBT is read back from the flash and loaded into the
memory instead of scanning every time. The Bad Block Table(BBT) is written
into one of the the last four blocks in the flash memory. The last four
blocks are marked as Reserved so that user can't erase/program those blocks.

There are two bad block tables, a primary table and a mirror table. The
tables are versioned and incrementing version number is used to detect and
recover from interrupted updates. Each table is stored in a separate block,
beginning in the first page of that block. Only two blocks would be necessary
in the absence of bad blocks within the last four; the range of four provides
a little slack in case one or two of those blocks is bad. These blocks are
marked as reserved and cannot be programmed by the user. A NAND Flash device
with 3 or more factory bad blocks in the last 4 cannot be used. The bad block
table signature is written into the spare data area of the pages containing
bad block table so that upon rebooting the bad block table signature is
searched and the bad block table is loaded into RAM. The signature is "Bbt0"
for primary Bad Block Table and "1tbB" for Mirror Bad Block Table. The
version offset follows the signature offset in the spare data area. The
version number increments on every update to the bad block table and the
version wraps at 0xff.

Each block in the Bad Block Table(BBT) is represented by 2 bits.
The two bits are encoded as follows in RAM BBT.
0'b00 -> Good Block
0'b01 -> Block is bad due to wear
0'b10 -> Reserved block
0'b11 -> Factory marked bad block

While writing to the flash the two bits are encoded as follows.
0'b00 -> Factory marked bad block
0'b01 -> Reserved block
0'b10 -> Block is bad due to wear
0'b11 -> Good Block

The user can check for the validity of the block using the API
XNandPsu_IsBlockBad and take the action based on the return value. Also user
can update the bad block table using XNandPsu_MarkBlockBad API.

Note
None
MODIFICATION HISTORY:

Ver   Who    Date        Changes
----- ----   ----------  -----------------------------------------------
1.0   nm     05/06/2014  First release
2.0   sb     01/12/2015  Added support for writing BBT signature and version
           in page section by enabling XNANDPSU_BBT_NO_OOB.
           Modified Bbt Signature and Version Offset value for
           Oob and No-Oob region.

This file contains identifiers and low-level macros/functions for the Arasan
NAND flash controller driver.

See xnandpsu.h for more information.

Note
None
MODIFICATION HISTORY:

Ver   Who    Date        Changes
----- ----   ----------  -----------------------------------------------
1.0   nm     05/06/2014  First Release
2.0   sb     11/04/2014  Changed XNANDPSU_ECC_SLC_MLC_MASK to
           XNANDPSU_ECC_HAMMING_BCH_MASK.
1.7 akm    09/03/20    Updated the Makefile to support parallel make
               execution.

This file defines all the ONFI 3.1 specific commands and values.

Note
None
MODIFICATION HISTORY:

Ver   Who    Date      Changes
----- ----   ----------  -----------------------------------------------
1.0   nm     05/06/2014  First release
1.4 nsk    04/10/2018  Added ICCARM compiler support.

This section explains the implementation the functions required to use the
QSPIPSU hardware to perform a transfer. These are accessible to the user
via xqspipsu.h.

Generic QSPI interface allows for communication to any QSPI slave device.
GQSPI contains a GENFIFO into which the bus transfers required are to be
pushed with appropriate configuration. The controller provides TX and RX
FIFO's and a DMA to be used for RX transfers. The controller executes each
GENFIFO entry noting the configuration and places data on the bus as required

The different options in GENFIFO are as follows:
IMM_DATA : Can be one byte of data to be transmitted, number of clocks or
             number of bytes in transfer.
DATA_XFER : Indicates that data/clocks need to be transmitted or received.
EXPONENT : e when 2^e bytes are involved in transfer.
SPI_MODE : SPI/Dual SPI/Quad SPI
CS : Lower or Upper CS or Both
Bus : Lower or Upper Bus or Both
TX : When selected, controller transmits data in IMM or fetches number of
       bytes mentioned form TX FIFO. If not selected, dummies are pumped.
RX : When selected, controller receives and fills the RX FIFO/allows RX DMA
       of requested number of bytes. If not selected, RX data is discarded.
Stripe : Byte stripe over lower and upper bus or not.
Poll : Polls response to match for to a set value (used along with POLL_CFG
         registers) and then proceeds to next GENFIFO entry.
         This feature is not currently used in the driver.

GENFIFO has manual and auto start options.
All DMA requests need a 4-byte aligned destination address buffer and
size of transfer should also be a multiple of 4.
This driver supports DMA RX and IO RX.

Initialization & Configuration

This driver uses the GQSPI controller with RX DMA. It supports both
interrupt and polled transfers. Manual start of GENFIFO is used.
XQspiPsu_CfgInitialize() initializes the instance variables.
Additional setting can be done using SetOptions/ClearOptions functions
and SelectSlave function.

Transfer

Polled or Interrupt transfers can be done. The transfer function needs the
message(s) to be transmitted in the form of an array of type XQspiPsu_Msg.
This is supposed to contain the byte count and any TX/RX buffers as required.
Flags can be used indicate further information such as whether the message
should be striped. The transfer functions form and write GENFIFO entries,
check the status of the transfer and report back to the application
when done.

MODIFICATION HISTORY:

Ver   Who Date     Changes
----- --- -------- -----------------------------------------------.
1.0   hk  08/21/14 First release
      sk  03/13/15 Added IO mode support.
      hk  03/18/15 Switch to I/O mode before clearing RX FIFO.
                   Clear and disable DMA interrupts/status in abort.
                   Use DMA DONE bit instead of BUSY as recommended.
      sk  04/24/15 Modified the code according to MISRAC-2012.
      sk  06/17/15 Removed NULL checks for Rx/Tx buffers. As
                   writing/reading from 0x0 location is permitted.
1.1   sk  04/12/16 Added debug message prints.
1.2 nsk 07/01/16 Added LQSPI support
                 Modified XQspiPsu_Select() macro in xqspipsu.h
                 Added XQspiPsu_GetLqspiConfigReg() in xqspipsu.h
                 Added required macros in xqspipsu_hw.h
                 Modified XQspiPsu_SetOptions() to support
                 LQSPI options and updated OptionsTable in
                 xqspipsu_options.c
      rk  07/15/16 Added support for TapDelays at different frequencies.
    nsk 08/05/16 Added example support PollData and PollTimeout
                 Added  XQSPIPSU_MSG_FLAG_POLL macro in xqspipsu.h
                 Added XQspiPsu_Create_PollConfigData and
                 XQspiPsu_PollData() functions in xqspipsu.c
1.3 nsk 09/16/16 Update PollData and Polltimeout support for dual parallel
                 configuration. Updated XQspiPsu_PollData() and
                 XQspiPsu_Create_PollConfigData() functions in xqspipsu.c
                   and also modified the polldata example
      ms  03/17/17 Added readme.txt file in examples folder for doxygen
                   generation.
      ms  04/05/17 Modified Comment lines in functions of qspipsu
                   examples to recognize it as documentation block
                   and modified filename tag to include them in
                   doxygen examples.
1.4 tjs 05/26/17 Added support for accessing upper DDR (0x800000000)
                 while booting images from QSPI
1.5 tjs 08/08/17 Added index.html file for importing examples
                 from system.mss
1.5 nsk 08/14/17 Added CCI support
1.5 tjs 09/14/17 Modified the checks for 4 byte addressing and commands.
1.6 tjs 10/16/17 Flow for accessing flash is made similar to u-boot
                 and linux For CR-984966
1.6   tjs 11/02/17 Resolved the compilation errors for ICCARM. CR-988625
1.7   tjs 11/16/17 Removed the unsupported 4 Byte write and sector erase
                   commands.
1.7 tjs 12/01/17 Added support for MT25QL02G Flash from Micron. CR-990642
1.7 tjs 12/19/17 Added support for S25FL064L from Spansion. CR-990724
1.7 tjs 01/11/18 Added support for MX66L1G45G flash from Macronix CR-992367
1.7 tjs 01/16/18 Removed the check for DMA MSB to be written. (CR#992560)
1.7 tjs 01/17/18 Added support to toggle the WP pin of flash. (PR#2448)
                   Added XQspiPsu_SetWP() in xqspipsu_options.c
                   Added XQspiPsu_WriteProtectToggle() in xqspipsu.c and
                   also added write protect example.
1.7 tjs 03/14/18 Added support in EL1 NS mode (CR#974882)
1.7 tjs 26/03/18 In dual parallel mode enable both CS when issuing Write
                    enable command. CR-998478
1.8 tjs 05/02/18 Added support for IS25LP064 and IS25WP064.
1.8 tjs 06/26/18 Added an example for accessing 64bit dma within
                 32 bit application. CR#1004701
1.8 tjs 06/26/18 Removed checkpatch warnings
1.8 tjs 07/09/19 Fixed cppcheck, doxygen and gcc warnings.
1.8 tjs 07/18/18 Setup64BRxDma() should be called only if the RxAddress is
                 greater than 32 bit address space. (CR#1006862)
1.8 tjs 07/18/18 Added support for the low density ISSI flash parts.
1.8 tjs 09/06/18 Fixed the code in XQspiPsu_GenFifoEntryData() for data
                 transfer length up to 255 for reducing the extra loop.
1.9 tjs 11/22/17 Added the check for A72 and R5 processors (CR-987075)
1.9 tjs 04/17/18 Updated register addresses as per the latest revision
        of versal (CR#999610)
1.9  aru 01/17/19 Fixed the violations for  MISRAC-2012
                 in safety mode .Done changes such as added U suffix,
                 Declared pointer param as const.
1.9  nsk 02/01/19 Clear DMA_DST_ADDR_MSB register on 32bit machine, if the
         address is of only 32bit (CR#1020031)
1.9  nsk 02/01/19 Added QSPI idling support

1.9 akm 03/08/19 Set recommended clock and data tap delay values for 40MHZ,
                 100MHZ and 150MHZ frequencies(CR#1023187)
1.9  nsk 03/27/19 Update 64bit dma support
         (CR#1018102).
1.9  akm 04/03/19 Fixed data alignment warnings on IAR compiler.
1.9  akm 04/03/19 Fixed compilation error in XQspiPsu_LqspiRead()
                    function on IAR compiler.
1.10 sk  08/20/19 Fixed issues in poll timeout feature.
1.10 akm 08/22/19 Set recommended tap delay values for 37.5MHZ, 100MHZ and
         150MHZ frequencies in Versal.
1.10 akm 09/05/19 Added Multi Die Erase and Muti Die Read support.
1.11 akm 11/07/19 Removed LQSPI register access in Versal.
1.11    akm 11/15/19 Fixed Coverity deadcode warning in
                XQspipsu_Calculate_Tapdelay().
1.11 akm 02/19/20 Added XQspiPsu_StartDmaTransfer() and XQspiPsu_CheckDmaDone()
             APIs for non-blocking transfer.
1.11 sd  01/02/20 Added clocking support
1.11 akm 03/09/20 Reorganize the source code, enable qspi controller and
         interrupts in XQspiPsu_CfgInitialize() API.
1.11 akm 03/26/20 Fixed issue by updating XQspiPsu_CfgInitialize to return
         XST_DEVICE_IS_STARTED instead of asserting, when the
         instance is already configured(CR#1058525).
1.12    akm 09/02/20 Updated the Makefile to support parallel make execution.
1.13 akm 01/04/21 Fix MISRA-C violations.
1.13 sne 04/23/21 Fixed doxygen warnings.
1.14 akm 06/24/21 Allow enough time for the controller to reset the FIFOs.
1.14 akm 08/12/21 Perform Dcache invalidate at the end of the DMA transfer.

This is the header file for the implementation of QSPIPSU driver.
Generic QSPI interface allows for communication to any QSPI slave device.
GQSPI contains a GENFIFO into which the bus transfers required are to be
pushed with appropriate configuration. The controller provides TX and RX
FIFO's and a DMA to be used for RX transfers. The controller executes each
GENFIFO entry noting the configuration and places data on the bus as required

MODIFICATION HISTORY:

Ver   Who Date     Changes
----- --- -------- -----------------------------------------------.
1.11   akm  03/09/20 First release
1.13   akm  01/04/21 Fix MISRA-C violations.
1.15   akm  03/03/22 Enable tapdelay settings for applications on
             Microblaze platform.

This file contains low level access functions using the base address
directly without an instance.

MODIFICATION HISTORY:

Ver   Who Date     Changes
----- --- -------- -----------------------------------------------.
1.0   hk  08/21/14 First release
      hk  03/18/15 Add DMA status register masks required.
      sk  04/24/15 Modified the code according to MISRAC-2012.
1.2 nsk 07/01/16 Added LQSPI supported Masks
      rk  07/15/16 Added support for TapDelays at different frequencies.
1.7 tjs 03/14/18 Added support in EL1 NS mode.
1.9 tjs 04/17/18 Updated register addresses as per the latest revision
                     of versal (CR#999610)
1.9  aru 01/17/19 Fixed the violations for  MISRAC-2012
                 in safety mode .Done changes such as added U suffix
1.11    akm 11/07/19 Removed LQSPI register access in Versal.
1.15    akm 12/02/21 Fix Doxygen warnings.

This file contains the implementation of the interface functions for
XNandPsu driver. Refer to the header file xnandpsu.h for more detailed
information.

This module supports for NAND flash memory devices that conform to the
"Open NAND Flash Interface" (ONFI) 3.0 Specification. This modules
implements basic flash operations like read, write and erase.

Note
Driver has been renamed to nandpsu after change in
    naming convention.
MODIFICATION HISTORY:

Ver   Who    Date      Changes
----- ----   ----------  -----------------------------------------------
1.0   nm     05/06/2014  First release
2.0   sb     01/12/2015  Removed Null checks for Buffer passed
           as parameter to Read API's
XNandPsu_Read()
XNandPsu_ReadPage
           Modified
XNandPsu_SetFeature()
XNandPsu_GetFeature()
           and made them public.
           Removed Failure Return for BCF Error check in
           XNandPsu_ReadPage() and added BCH_Error counter
           in the instance pointer structure.
               Added XNandPsu_Prepare_Cmd API
           Replaced
XNandPsu_IntrStsEnable
XNandPsu_IntrStsClear
XNandPsu_IntrClear
XNandPsu_SetProgramReg
           with XNandPsu_WriteReg call
           Modified xnandpsu.c file API's with above changes.
               Corrected the program command for Set Feature API.
           Modified
XNandPsu_OnfiReadStatus
XNandPsu_GetFeature
XNandPsu_SetFeature
           to add support for DDR mode.
           Changed Convention for SLC/MLC
           SLC --> HAMMING
           MLC --> BCH
           SlcMlc --> IsBCH
           Removed extra DMA mode initialization from
           the XNandPsu_CfgInitialize API.
           Modified
XNandPsu_SetEccAddrSize
           ECC address now is calculated based upon the
           size of spare area
           Modified Block Erase API, removed clearing of
           packet register before erase.
           Clearing Data Interface Register before
           XNandPsu_OnfiReset call.
           Modified XNandPsu_ChangeTimingMode API supporting
           SDR and NVDDR interface for timing modes 0 to 5.
           Modified Bbt Signature and Version Offset value for
           Oob and No-Oob region.
1.0   kpc    17/6/2015   Added timer based timeout intsead of sw counter.
1.1   mi     09/16/16 Removed compilation warnings with extra compiler flags.
1.1 nsk    11/07/16    Change memcpy to Xil_MemCpy to handle word aligned
                     data access.
1.2 nsk    01/19/17    Fix for the failure of reading nand first redundant
                       parameter page. CR#966603
1.3 nsk    08/14/17    Added CCI support
1.4 nsk    04/10/18    Added ICCARM compiler support. CR#997552.
1.5   mus    11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
1.5   mus    11/05/18 Updated XNandPsu_ChangeClockFreq to fix compilation
                      warnings.
1.6 sd     06/02/20    Added Clock support
1.6 sd     20/03/20    Added compilation flag
1.8   sg     03/18/21      Added validation check for parameter page.
1.9   akm    07/15/21    Initialize NandInstPtr with Data Interface & Timing mode info.
1.10  akm    10/20/21    Fix gcc warnings.
1.10  akm    12/21/21    Validate input parameters before use.
1.10  akm    01/05/22    Remove assert checks form static and internal APIs.
1.11  akm    03/31/22    Fix unused parameter warning.
1.11  akm    03/31/22    Fix misleading-indentation warning.

This file implements the Bad Block Management (BBM) functionality.
See xnandpsu_bbm.h for more details.

Note
None
MODIFICATION HISTORY:

Ver   Who    Date        Changes
----- ----   ----------  -----------------------------------------------
1.0   nm     05/06/2014  First release
2.0   sb     01/12/2015  Added support for writing BBT signature and version
           in page section by enabling XNANDPSU_BBT_NO_OOB.
           Modified Bbt Signature and Version Offset value for
           Oob and No-Oob region.
1.1 nsk    11/07/16    Change memcpy to Xil_MemCpy to handle word aligned
                     data access.
1.4 nsk    04/10/18    Added ICCARM compiler support.
1.10    akm    01/05/22    Remove assert checks form static and internal APIs.

This file contains the implementation of ONFI specific functions.

Note
None
MODIFICATION HISTORY:

Ver   Who    Date      Changes
----- ----   ----------  -----------------------------------------------
1.0   nm     05/06/2014  First release

This file implements the functions required to use the QSPIPSU hardware to
perform a transfer. These are accessible to the user via xqspipsu.h.

MODIFICATION HISTORY:

Ver   Who Date     Changes
----- --- -------- -----------------------------------------------
1.0   hk  08/21/14 First release
      sk  03/13/15 Added IO mode support.
      hk  03/18/15 Switch to I/O mode before clearing RX FIFO.
                   Clear and disable DMA interrupts/status in abort.
                   Use DMA DONE bit instead of BUSY as recommended.
      sk  04/24/15 Modified the code according to MISRAC-2012.
      sk  06/17/15 Removed NULL checks for Rx/Tx buffers. As
                   writing/reading from 0x0 location is permitted.
1.1   sk  04/12/16 Added debug message prints.
1.2 nsk 07/01/16 Changed XQspiPsu_Select to support GQSPI and LQSPI
                 selection.
      rk  07/15/16 Added support for TapDelays at different frequencies.
    nsk 08/05/16 Added example support PollData and PollTimeout
1.3 nsk 09/16/16 Update PollData and PollTimeout support for dual
                 parallel configurations, modified XQspiPsu_PollData()
                 and XQspiPsu_Create_PollConfigData()
1,5 nsk 08/14/17 Added CCI support
1.7 tjs 01/16/18 Removed the check for DMA MSB to be written. (CR#992560)
1.7 tjs 01/17/18 Added a support to toggle WP pin of the flash.
1.7 tjs 03/14/18 Added support in EL1 NS mode (CR#974882)
1.8 tjs 06/26/18 Added an example for accessing 64bit dma within
                 32 bit application. CR#1004701
1.8 tjs 06/26/18 Removed checkpatch warnings.
1.8 tjs 07/09/18 Fixed cppcheck and doxygen warnings. (CR#1006336)
1.8 tjs 07/18/18 Setup64BRxDma() should be called only if the RxAddress is
                 greater than 32 bit address space. (CR#1006862)
1.8 tjs 09/06/18 Fixed the code in XQspiPsu_GenFifoEntryData() for data
                 transfer length up to 255 for reducing the extra loop.
1.8  mus 11/05/18 Support 64 bit DMA addresses for Microblaze-X platform.
1.9 tjs 11/22/17 Added the check for A72 and R5 processors (CR-987075)
1.9 tjs 04/17/18 Updated register addresses as per the latest revision
        of versal (CR#999610)
1.9  aru 01/17/19 Fixes violations according to MISRAC-2012
                 in safety mode and modified the code such as
                 Added UNITPTR inplace of INTPTR,Declared the pointer param
        as Pointer to const .
1.9  nsk 02/01/19 Clear DMA_DST_ADDR_MSB register on 32bit machine, if the
         address is of only 32bit (CR#1020031)
1.9  nsk 02/01/19 Added QSPI idling support.
1.9  rama 03/13/19 Fixed MISRA violations related to UR data anamoly,
                  expression is not a boolean
1.9  nsk 03/27/19 Update 64bit dma support
1.10 sk  08/20/19 Fixed issues in poll timeout feature.
1.11 akm 02/19/20 Added XQspiPsu_StartDmaTransfer() and XQspiPsu_CheckDmaDone()
             APIs for non-blocking transfer.
1.11 sd  01/02/20 Added clocking support
1.11 akm 03/09/20 Reorganize the source code, enable qspi controller and
         interrupts in XQspiPsu_CfgInitialize() API.
1.11 akm 03/26/20 Fixed issue by updating XQspiPsu_CfgInitialize to return
         XST_DEVICE_IS_STARTED instead of asserting, when the
         instance is already configured.
1.13 akm 01/04/21 Fix MISRA-C violations.
1.14 akm 06/24/21 Allow enough time for the controller to reset the FIFOs.
1.14 akm 08/12/21 Perform Dcache invalidate at the end of the DMA transfer.
1.15 akm 10/21/21 Fix MISRA-C violations.

This file contains intermediate control functions used by functions
in xqspipsu.c and xqspipsu_options.c files.

MODIFICATION HISTORY:

Ver   Who Date     Changes
----- --- -------- -----------------------------------------------
1.11   akm  03/09/20 First release
1.13   akm  01/04/21 Fix MISRA-C violations.
1.15   akm  10/21/21 Fix MISRA-C violations.
1.15   akm  03/03/22 Enable tapdelay settings for applications on
             Microblaze platform.

This file contains functions to reads RXFifo, writes TXFifo and setup
RX DMA operation, used by xqspipsu_control.c and xqspipsu_lowlevel.c files.

MODIFICATION HISTORY:

Ver   Who Date     Changes
----- --- -------- -----------------------------------------------
1.11   akm  03/09/20 First release
        mn  03/30/20 Add xil_smc.h include for Xil_Smc calls
1.13   akm  01/04/21 Fix MISRA-C violations.
1.15   akm  10/21/21 Fix MISRA-C violations.
1.15   akm  11/16/21 Typecast function parameter with appropriate
            data type.
1.15   akm  11/30/21 Fix compilation warnings reported with -Wundef flag
1.15   akm  03/03/22 Enable tapdelay settings for applications on
             Microblaze platform.

This file implements functions to configure the QSPIPSU component,
specifically some optional settings, clock and flash related information.

MODIFICATION HISTORY:

Ver   Who Date     Changes
----- --- -------- -----------------------------------------------
1.0   hk  08/21/14 First release
      sk  03/13/15 Added IO mode support.
      sk  04/24/15 Modified the code according to MISRAC-2012.
1.1   sk  04/12/16 Added debug message prints.
1.2 nsk 07/01/16 Modified XQspiPsu_SetOptions() to support
         LQSPI options and updated OptionsTable
      rk  07/15/16 Added support for TapDelays at different frequencies.
1.7 tjs 01/17/18 Added support to toggle the WP pin of flash. (PR#2448)
1.7 tjs 03/14/18 Added support in EL1 NS mode. (CR#974882)
1.8  tjs 05/02/18 Added support for IS25LP064 and IS25WP064.
1.8  tjs 07/26/18 Resolved cppcheck errors. (CR#1006336)
1.9 tjs 04/17/18 Updated register addresses as per the latest revision
                     of versal (CR#999610)
1.9  aru 01/17/19 Fixes violations according to MISRAC-2012
                 in safety mode and modified the code such as
                 Added Xil_MemCpy inplace of memcpy,Declared the pointer param
                 as Pointer to const, declared XQspi_Set_TapDelay() as static.
1.9 akm 03/08/19 Set recommended clock and data tap delay values for 40MHZ,
       100MHZ and 150MHZ frequencies(CR#1023187)
1.10 akm 08/22/19 Set recommended tap delay values for 37.5MHZ, 100MHZ and
        150MHZ frequencies in Versal.
1.11    akm 11/07/19 Removed LQSPI register access in Versal.
1.11    akm 11/15/19 Fixed Coverity deadcode warning in
                XQspipsu_Calculate_Tapdelay().
1.11 akm 03/09/20 Reorganize the source code, enable qspi controller and
         interrupts in XQspiPsu_CfgInitialize() API.
1.13 akm 01/04/21 Fix MISRA-C violations.
1.15 akm 03/03/22 Enable tapdelay settings for applications on Microblaze
             platform.

Macro Definition Documentation

◆ BYTES1024_PER_PAGE

#define BYTES1024_PER_PAGE 1024U

1024 Bytes per Page

◆ BYTES256_PER_PAGE

#define BYTES256_PER_PAGE 256U

Definitions for Intel, STM, Winbond and Spansion Serial Flash Device geometry. 256 Bytes per Page

◆ BYTES512_PER_PAGE

#define BYTES512_PER_PAGE 512U

512 Bytes per Page

◆ IOU_TAPDLY_BYPASS_OFFSET

#define IOU_TAPDLY_BYPASS_OFFSET 0X00000390U

Tapdelay Bypass register

◆ IS_ONFI

#define IS_ONFI ( Buff )

Value:

((Buff)[0] == (u8)'O') && ((Buff)[1] == (u8)'N') && \

((Buff)[2] == (u8)'F') && ((Buff)[3] == (u8)'I')

This macro checks for the ONFI ID.

Parameters

Buff	is the buffer holding ONFI ID

Note: none.

◆ MAX_DELAY_CNT

#define MAX_DELAY_CNT 10000000U

Max delay count

◆ NUM_OF_SECTORS1024

#define NUM_OF_SECTORS1024 1024U

1024 Sectors

◆ NUM_OF_SECTORS128

#define NUM_OF_SECTORS128 128U

128 Sectors

◆ NUM_OF_SECTORS16

#define NUM_OF_SECTORS16 16U

16 Sectors

◆ NUM_OF_SECTORS2

#define NUM_OF_SECTORS2 2U

2 Sectors

◆ NUM_OF_SECTORS2048

#define NUM_OF_SECTORS2048 2048U

2048 Sectors

◆ NUM_OF_SECTORS256

#define NUM_OF_SECTORS256 256U

256 Sectors

◆ NUM_OF_SECTORS32

#define NUM_OF_SECTORS32 32U

32 Sectors

◆ NUM_OF_SECTORS4

#define NUM_OF_SECTORS4 4U

4 Sectors

◆ NUM_OF_SECTORS4096

#define NUM_OF_SECTORS4096 4096U

4096 Sectors

◆ NUM_OF_SECTORS512

#define NUM_OF_SECTORS512 512U

512 Sectors

◆ NUM_OF_SECTORS64

#define NUM_OF_SECTORS64 64U

64 Sectors

◆ NUM_OF_SECTORS8

#define NUM_OF_SECTORS8 8U

8 Sector

◆ NUM_OF_SECTORS8192

#define NUM_OF_SECTORS8192 8192U

8192 Sectors

◆ ONFI_CMD_BLK_ERASE1

#define ONFI_CMD_BLK_ERASE1 0x60U

Block Erase (1st cycle)

◆ ONFI_CMD_BLK_ERASE2

#define ONFI_CMD_BLK_ERASE2 0xD0U

Block Erase (2nd cycle)

◆ ONFI_CMD_BLK_ERASE_INTRLVD2

#define ONFI_CMD_BLK_ERASE_INTRLVD2 0xD1U

Block Erase Interleaved (2nd cycle)

◆ ONFI_CMD_CHNG_RD_COL1

#define ONFI_CMD_CHNG_RD_COL1 0x05U

Change Read Column (1st cycle)

◆ ONFI_CMD_CHNG_RD_COL2

#define ONFI_CMD_CHNG_RD_COL2 0xE0U

Change Read Column (2nd cycle)

◆ ONFI_CMD_CHNG_RD_COL_ENHCD1

#define ONFI_CMD_CHNG_RD_COL_ENHCD1 0x06U

Change Read Column Enhanced (1st cycle)

◆ ONFI_CMD_CHNG_RD_COL_ENHCD2

#define ONFI_CMD_CHNG_RD_COL_ENHCD2 0xE0U

Change Read Column Enhanced (2nd cycle)

◆ ONFI_CMD_CHNG_ROW_ADDR

#define ONFI_CMD_CHNG_ROW_ADDR 0x85U

Change Row Address

◆ ONFI_CMD_CHNG_WR_COL

#define ONFI_CMD_CHNG_WR_COL 0x85U

Change Write Column

◆ ONFI_CMD_CPBK_PROG1

#define ONFI_CMD_CPBK_PROG1 0x85U

Copyback Program (1st cycle)

◆ ONFI_CMD_CPBK_PROG2

#define ONFI_CMD_CPBK_PROG2 0x10U

Copyback Program (2nd cycle)

◆ ONFI_CMD_CPBK_RD1

#define ONFI_CMD_CPBK_RD1 0x00U

Copyback Read (1st cycle)

◆ ONFI_CMD_CPBK_RD2

#define ONFI_CMD_CPBK_RD2 0x35U

Copyback Read (2nd cycle)

◆ ONFI_CMD_GET_FEATURES

#define ONFI_CMD_GET_FEATURES 0xEEU

Get Features

◆ ONFI_CMD_INVALID

#define ONFI_CMD_INVALID 0x00U

Invalid Command

◆ ONFI_CMD_LUN_GET_FEATURES

#define ONFI_CMD_LUN_GET_FEATURES 0xD4U

LUN Get Features

◆ ONFI_CMD_LUN_SET_FEATURES

#define ONFI_CMD_LUN_SET_FEATURES 0xD5U

LUN Set Features

◆ ONFI_CMD_MUL_BLK_ERASE1

#define ONFI_CMD_MUL_BLK_ERASE1 0x60U

Multiplane Block Erase (1st cycle)

◆ ONFI_CMD_MUL_BLK_ERASE2

#define ONFI_CMD_MUL_BLK_ERASE2 0xD1U

Multiplane Block Erase (2nd cycle)

◆ ONFI_CMD_MUL_CPBK_PROG1

#define ONFI_CMD_MUL_CPBK_PROG1 0x85U

Multiplane Copyback Program (1st cycle)

◆ ONFI_CMD_MUL_CPBK_PROG2

#define ONFI_CMD_MUL_CPBK_PROG2 0x10U

Multiplane Copyback Program (2nd cycle)

◆ ONFI_CMD_MUL_PG_PROG1

#define ONFI_CMD_MUL_PG_PROG1 0x80U

Multiplane Page Program (1st cycle)

◆ ONFI_CMD_MUL_PG_PROG2

#define ONFI_CMD_MUL_PG_PROG2 0x11U

Multiplane Page Program (2nd cycle)

◆ ONFI_CMD_MUL_RD1

#define ONFI_CMD_MUL_RD1 0x00U

Multiplane Read (1st cycle)

◆ ONFI_CMD_MUL_RD2

#define ONFI_CMD_MUL_RD2 0x32U

Multiplane Read (2nd cycle)

◆ ONFI_CMD_ODT_CONF

#define ONFI_CMD_ODT_CONF 0xE2U

ODT Configure

◆ ONFI_CMD_PG_CACHE_PROG1

#define ONFI_CMD_PG_CACHE_PROG1 0x80U

Page Cache Program (1st cycle)

◆ ONFI_CMD_PG_CACHE_PROG2

#define ONFI_CMD_PG_CACHE_PROG2 0x15U

Page Cache Program (2nd cycle)

◆ ONFI_CMD_PG_PROG1

#define ONFI_CMD_PG_PROG1 0x80U

Page Program(1st cycle)

◆ ONFI_CMD_PG_PROG2

#define ONFI_CMD_PG_PROG2 0x10U

Page Program(2nd cycle)

◆ ONFI_CMD_RD1

#define ONFI_CMD_RD1 0x00U

Read (1st cycle)

◆ ONFI_CMD_RD2

#define ONFI_CMD_RD2 0x30U

Read (2nd cycle)

◆ ONFI_CMD_RD_CACHE_END

#define ONFI_CMD_RD_CACHE_END 0x3FU

Read Cache End

◆ ONFI_CMD_RD_CACHE_RND1

#define ONFI_CMD_RD_CACHE_RND1 0x00U

Read Cache Random (1st cycle)

◆ ONFI_CMD_RD_CACHE_RND2

#define ONFI_CMD_RD_CACHE_RND2 0x31U

Read Cache Random (2nd cycle)

◆ ONFI_CMD_RD_CACHE_SEQ

#define ONFI_CMD_RD_CACHE_SEQ 0x31U

Read Cache Sequential

◆ ONFI_CMD_RD_ID

#define ONFI_CMD_RD_ID 0x90U

Read ID

◆ ONFI_CMD_RD_PRM_PG

#define ONFI_CMD_RD_PRM_PG 0xECU

Read Parameter Page

◆ ONFI_CMD_RD_STS

#define ONFI_CMD_RD_STS 0x70U

Read Status

◆ ONFI_CMD_RD_STS_ENHCD

#define ONFI_CMD_RD_STS_ENHCD 0x78U

Read Status Enhanced

◆ ONFI_CMD_RD_UNIQID

#define ONFI_CMD_RD_UNIQID 0xEDU

Read Unique ID

◆ ONFI_CMD_RST

#define ONFI_CMD_RST 0xFFU

Reset

◆ ONFI_CMD_RST_LUN

#define ONFI_CMD_RST_LUN 0xFAU

Reset LUN

◆ ONFI_CMD_SET_FEATURES

#define ONFI_CMD_SET_FEATURES 0xEFU

Set Features

◆ ONFI_CMD_SMALL_DATA_MV1

#define ONFI_CMD_SMALL_DATA_MV1 0x85U

Small Data Move (1st cycle)

◆ ONFI_CMD_SMALL_DATA_MV2

#define ONFI_CMD_SMALL_DATA_MV2 0x10U

Small Data Move (2nd cycle)

◆ ONFI_CMD_SYN_RST

#define ONFI_CMD_SYN_RST 0xFCU

Synchronous Reset

◆ ONFI_CMD_VOL_SEL

#define ONFI_CMD_VOL_SEL 0xE1U

Volume Select

◆ ONFI_CRC_LEN

#define ONFI_CRC_LEN 254U

ONFI CRC Buf Length

◆ ONFI_MND_PRM_PGS

#define ONFI_MND_PRM_PGS 3U

Number of mandatory parameter pages

◆ ONFI_PRM_PG_ADDR_CYCLES

#define ONFI_PRM_PG_ADDR_CYCLES 1U

ONFI Read Parameter page address cycles

◆ ONFI_PRM_PG_LEN

#define ONFI_PRM_PG_LEN 256U

Parameter Page Length

◆ ONFI_READ_ID_ADDR

#define ONFI_READ_ID_ADDR 0x20U

ONFI Read ID Address

◆ ONFI_READ_ID_ADDR_CYCLES

#define ONFI_READ_ID_ADDR_CYCLES 1U

ONFI Read ID Address cycles

◆ ONFI_READ_ID_LEN

#define ONFI_READ_ID_LEN 4U

ONFI ID length

◆ ONFI_SIG_LEN

#define ONFI_SIG_LEN 4U

Signature Length

◆ ONFI_STS_ARDY

#define ONFI_STS_ARDY 0x20U

ARDY

◆ ONFI_STS_CSP

#define ONFI_STS_CSP 0x08U

CSP

◆ ONFI_STS_FAIL

#define ONFI_STS_FAIL 0x01U

FAIL

◆ ONFI_STS_FAILC

#define ONFI_STS_FAILC 0x02U

FAILC

◆ ONFI_STS_RDY

#define ONFI_STS_RDY 0x40U

RDY

◆ ONFI_STS_VSP

#define ONFI_STS_VSP 0x10U

VSP

◆ ONFI_STS_WP

#define ONFI_STS_WP 0x80U

WP_n

◆ PAGES1024_PER_SECTOR

#define PAGES1024_PER_SECTOR 1024U

1024 Pages per Sector

◆ PAGES128_PER_SECTOR

#define PAGES128_PER_SECTOR 128U

128 Pages per Sector

◆ PAGES16_PER_SECTOR

#define PAGES16_PER_SECTOR 16U

16 Pages per Sector

◆ PAGES256_PER_SECTOR

#define PAGES256_PER_SECTOR 256U

256 Pages per Sector

◆ PAGES512_PER_SECTOR

#define PAGES512_PER_SECTOR 512U

512 Pages per Sector

◆ SECTOR_SIZE_128K

#define SECTOR_SIZE_128K 0X20000U

128K Sector

◆ SECTOR_SIZE_256K

#define SECTOR_SIZE_256K 0X40000U

256K Sector

◆ SECTOR_SIZE_512K

#define SECTOR_SIZE_512K 0X80000U

512K Sector

◆ SECTOR_SIZE_64K

#define SECTOR_SIZE_64K 0X10000U

64K Sector

◆ XNANDPSU_BB_PATTERN

#define XNANDPSU_BB_PATTERN 0xFFU

Bad block pattern to search in a page

◆ XNANDPSU_BB_PTRN_LEN_LARGE_PAGE

#define XNANDPSU_BB_PTRN_LEN_LARGE_PAGE 2U

Bad block pattern length

◆ XNANDPSU_BB_PTRN_LEN_SML_PAGE

#define XNANDPSU_BB_PTRN_LEN_SML_PAGE 1U

Bad block pattern length

◆ XNANDPSU_BB_PTRN_OFF_LARGE_PAGE

#define XNANDPSU_BB_PTRN_OFF_LARGE_PAGE 0U

Bad block pattern offset in a large page

◆ XNANDPSU_BB_PTRN_OFF_SML_PAGE

#define XNANDPSU_BB_PTRN_OFF_SML_PAGE 5U

Bad block pattern offset in a page

◆ XNANDPSU_BBT_BLOCK_SHIFT

#define XNANDPSU_BBT_BLOCK_SHIFT 2U

Block shift value for a block in BBT

◆ XNANDPSU_BBT_BUF_LENGTH

#define XNANDPSU_BBT_BUF_LENGTH

Value:

                     ((XNANDPSU_MAX_BLOCKS >>       \
                     XNANDPSU_BBT_BLOCK_SHIFT) +    \
                    (XNANDPSU_BBT_DESC_SIG_OFFSET + \
                     XNANDPSU_BBT_SIG_LENGTH +  \
                     XNANDPSU_BBT_VERSION_LENGTH))

◆ XNANDPSU_BBT_DESC_MAX_BLOCKS

#define XNANDPSU_BBT_DESC_MAX_BLOCKS 64U

Bad block Table max blocks

◆ XNANDPSU_BBT_DESC_PAGE_OFFSET

#define XNANDPSU_BBT_DESC_PAGE_OFFSET 0U

Page offset of Bad Block Table Desc

◆ XNANDPSU_BBT_DESC_SIG_LEN

#define XNANDPSU_BBT_DESC_SIG_LEN 4U

Bad block Table signature length

◆ XNANDPSU_BBT_DESC_SIG_OFFSET

#define XNANDPSU_BBT_DESC_SIG_OFFSET 8U

Bad Block Table signature offset

◆ XNANDPSU_BBT_DESC_VER_OFFSET

#define XNANDPSU_BBT_DESC_VER_OFFSET 12U

Bad block Table version offset

◆ XNANDPSU_BBT_ENTRY_NUM_BLOCKS

#define XNANDPSU_BBT_ENTRY_NUM_BLOCKS 4U

Num of blocks in one BBT entry

◆ XNANDPSU_BBT_SCAN_2ND_PAGE

#define XNANDPSU_BBT_SCAN_2ND_PAGE 0x00000001U

Scan the second page for bad block information

◆ XNandPsu_BbtBlockShift

#define XNandPsu_BbtBlockShift ( Block ) (u8)(((Block) * 2U) & XNANDPSU_BLOCK_SHIFT_MASK)

This macro returns the Block shift value corresponding to a Block.

Parameters

Block is the block number.

Returns: Block shift value

Note: None.

◆ XNANDPSU_BCH

#define XNANDPSU_BCH 0x2U

BCH Flash

◆ XNANDPSU_BLOCK_BAD

#define XNANDPSU_BLOCK_BAD 0x1U

Block is bad

◆ XNANDPSU_BLOCK_FACTORY_BAD

#define XNANDPSU_BLOCK_FACTORY_BAD 0x3U

Factory marked bad block

◆ XNANDPSU_BLOCK_GOOD

#define XNANDPSU_BLOCK_GOOD 0x0U

Block is good

◆ XNANDPSU_BLOCK_RESERVED

#define XNANDPSU_BLOCK_RESERVED 0x2U

Reserved block

◆ XNANDPSU_BLOCK_SHIFT_MASK

#define XNANDPSU_BLOCK_SHIFT_MASK 0x06U

Block shift mask for a Bad Block Table entry byte

◆ XNANDPSU_BLOCK_TYPE_MASK

#define XNANDPSU_BLOCK_TYPE_MASK 0x03U

Block type mask

◆ XNANDPSU_BUF_DATA_PORT_OFFSET

#define XNANDPSU_BUF_DATA_PORT_OFFSET 0x30U

Buffer Data Port Register

◆ XNandPsu_ClrBits

#define XNandPsu_ClrBits	(	InstancePtr,
		RegOffset,
		BitMask
	)

Value:

    XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,        \
        (RegOffset),                        \
    ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,  \
        (RegOffset)) & ~(BitMask))))

This macro clears the bitmask in the register.

Parameters

InstancePtr	is a pointer to the XNandPsu instance of the controller.
RegOffset	is the register offset.
BitMask	is the bitmask.

Note: C-style signature: void XNandPsu_ClrBits(XNandPsu *InstancePtr, u32 RegOffset, u32 BitMask)

◆ XNANDPSU_CMD_ADDR_CYCLES_MASK

#define XNANDPSU_CMD_ADDR_CYCLES_MASK 0x70000000U

Number of Address Cycles

◆ XNANDPSU_CMD_ADDR_CYCLES_SHIFT

#define XNANDPSU_CMD_ADDR_CYCLES_SHIFT 28U

Number of Address Cycles Shift

◆ XNANDPSU_CMD_CMD1_MASK

#define XNANDPSU_CMD_CMD1_MASK 0x000000FFU

1st Cycle Command

◆ XNANDPSU_CMD_CMD2_MASK

#define XNANDPSU_CMD_CMD2_MASK 0x0000FF00U

2nd Cycle Command

◆ XNANDPSU_CMD_CMD2_SHIFT

#define XNANDPSU_CMD_CMD2_SHIFT 8U

2nd Cycle Command Shift

◆ XNANDPSU_CMD_DMA_EN_MASK

#define XNANDPSU_CMD_DMA_EN_MASK 0x0C000000U

DMA Enable Mode

◆ XNANDPSU_CMD_DMA_EN_SHIFT

#define XNANDPSU_CMD_DMA_EN_SHIFT 26U

DMA Enable Shift

◆ XNANDPSU_CMD_ECC_ON_MASK

#define XNANDPSU_CMD_ECC_ON_MASK 0x80000000U

ECC ON/OFF

◆ XNANDPSU_CMD_ECC_ON_SHIFT

#define XNANDPSU_CMD_ECC_ON_SHIFT 31U

ECC ON/OFF

◆ XNANDPSU_CMD_OFFSET

#define XNANDPSU_CMD_OFFSET 0x0CU

Command Register

◆ XNANDPSU_CMD_PG_SIZE_MASK

#define XNANDPSU_CMD_PG_SIZE_MASK 0x03800000U

Page Size

◆ XNANDPSU_CMD_PG_SIZE_SHIFT

#define XNANDPSU_CMD_PG_SIZE_SHIFT 23U

Page Size Shift

◆ XNANDPSU_CPU_REL_OFFSET

#define XNANDPSU_CPU_REL_OFFSET 0x58U

CPU Release Register

◆ XNANDPSU_DATA_INTF_DATA_INTF_MASK

#define XNANDPSU_DATA_INTF_DATA_INTF_MASK 0x00000600U

Data Interface

◆ XNANDPSU_DATA_INTF_DATA_INTF_SHIFT

#define XNANDPSU_DATA_INTF_DATA_INTF_SHIFT 9U

Data Interface Shift

◆ XNANDPSU_DATA_INTF_NVDDR2_MASK

#define XNANDPSU_DATA_INTF_NVDDR2_MASK 0x000001C0U

NVDDR2 mode

◆ XNANDPSU_DATA_INTF_NVDDR_MASK

#define XNANDPSU_DATA_INTF_NVDDR_MASK 0x00000038U

NVDDR mode

◆ XNANDPSU_DATA_INTF_NVDDR_SHIFT

#define XNANDPSU_DATA_INTF_NVDDR_SHIFT 3U

NVDDR mode shift

◆ XNANDPSU_DATA_INTF_OFFSET

#define XNANDPSU_DATA_INTF_OFFSET 0x6CU

Data Interface Register

◆ XNANDPSU_DATA_INTF_SDR_MASK

#define XNANDPSU_DATA_INTF_SDR_MASK 0x00000007U

SDR mode

◆ XNANDPSU_DMA_BUF_BND_BND_MASK

#define XNANDPSU_DMA_BUF_BND_BND_MASK 0x00000007U

DMA buffer boundary

◆ XNANDPSU_DMA_BUF_BND_OFFSET

#define XNANDPSU_DMA_BUF_BND_OFFSET 0x54U

DMA Buffer Boundary Register

◆ XNANDPSU_DMA_SYS_ADDR0_OFFSET

#define XNANDPSU_DMA_SYS_ADDR0_OFFSET 0x50U

DMA System Address 0 Register

◆ XNANDPSU_DMA_SYS_ADDR1_OFFSET

#define XNANDPSU_DMA_SYS_ADDR1_OFFSET 0x24U

DMA System Address 1 Register

◆ XNANDPSU_ECC_ADDR_MASK

#define XNANDPSU_ECC_ADDR_MASK 0x0000FFFFU

ECC address

◆ XNANDPSU_ECC_CNT_1BIT_OFFSET

#define XNANDPSU_ECC_CNT_1BIT_OFFSET 0x40U

Error Count 1bit Register

◆ XNANDPSU_ECC_CNT_2BIT_OFFSET

#define XNANDPSU_ECC_CNT_2BIT_OFFSET 0x44U

Error Count 2bit Register

◆ XNANDPSU_ECC_CNT_3BIT_OFFSET

#define XNANDPSU_ECC_CNT_3BIT_OFFSET 0x48U

Error Count 3bit Register

◆ XNANDPSU_ECC_CNT_4BIT_OFFSET

#define XNANDPSU_ECC_CNT_4BIT_OFFSET 0x4CU

Error Count 4bit Register

◆ XNANDPSU_ECC_CNT_5BIT_OFFSET

#define XNANDPSU_ECC_CNT_5BIT_OFFSET 0x5CU

Error Count 5bit Register

◆ XNANDPSU_ECC_CNT_6BIT_OFFSET

#define XNANDPSU_ECC_CNT_6BIT_OFFSET 0x60U

Error Count 6bit Register

◆ XNANDPSU_ECC_CNT_7BIT_OFFSET

#define XNANDPSU_ECC_CNT_7BIT_OFFSET 0x64U

Error Count 7bit Register

◆ XNANDPSU_ECC_CNT_8BIT_OFFSET

#define XNANDPSU_ECC_CNT_8BIT_OFFSET 0x68U

Error Count 8bit Register

◆ XNANDPSU_ECC_ERR_CNT_OFFSET

#define XNANDPSU_ECC_ERR_CNT_OFFSET 0x38U

ECC Error Count Register

◆ XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK

#define XNANDPSU_ECC_ERR_CNT_PG_BND_ERR_CNT_MASK 0x0000FF00U

Page bound error count

◆ XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK

#define XNANDPSU_ECC_ERR_CNT_PKT_BND_ERR_CNT_MASK 0x000000FFU

Packet bound error count

◆ XNANDPSU_ECC_HAMMING_BCH_MASK

#define XNANDPSU_ECC_HAMMING_BCH_MASK 0x02000000U

Hamming/BCH support

◆ XNANDPSU_ECC_OFFSET

#define XNANDPSU_ECC_OFFSET 0x34U

ECC Register

◆ XNANDPSU_ECC_SIZE_MASK

#define XNANDPSU_ECC_SIZE_MASK 0x01FF0000U

ECC size

◆ XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK

#define XNANDPSU_ECC_SPR_CMD_ECC_ADDR_CYCLES_MASK 0x70000000U

Number of ECC/ spare address cycles

◆ XNANDPSU_ECC_SPR_CMD_OFFSET

#define XNANDPSU_ECC_SPR_CMD_OFFSET 0x3CU

ECC Spare Command Register

◆ XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK

#define XNANDPSU_ECC_SPR_CMD_SPR_CMD_MASK 0x000000FFU

ECC spare command

◆ XNANDPSU_FLASH_BLOCK_BAD

#define XNANDPSU_FLASH_BLOCK_BAD 0x2U

Block is bad

◆ XNANDPSU_FLASH_BLOCK_FAC_BAD

#define XNANDPSU_FLASH_BLOCK_FAC_BAD 0x0U

Factory marked bad block

◆ XNANDPSU_FLASH_BLOCK_GOOD

#define XNANDPSU_FLASH_BLOCK_GOOD 0x3U

Block is good

◆ XNANDPSU_FLASH_BLOCK_RESERVED

#define XNANDPSU_FLASH_BLOCK_RESERVED 0x1U

Reserved block

◆ XNANDPSU_FLASH_STS_FLASH_STS_MASK

#define XNANDPSU_FLASH_STS_FLASH_STS_MASK 0x0000FFFFU

Flash Status Value

◆ XNANDPSU_FLASH_STS_OFFSET

#define XNANDPSU_FLASH_STS_OFFSET 0x28U

Flash Status Register

◆ XNANDPSU_HAMMING

#define XNANDPSU_HAMMING 0x1U

Hamming Flash

◆ XNANDPSU_ID2_DEVICE_ID2_MASK

#define XNANDPSU_ID2_DEVICE_ID2_MASK 0x000000FFU

MSB Device ID

◆ XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK

#define XNANDPSU_INTR_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

Buffer Read Ready Status Enable

◆ XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK

#define XNANDPSU_INTR_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

Buffer Write Ready Status Enable

◆ XNANDPSU_INTR_DMA_INT_STS_EN_MASK

#define XNANDPSU_INTR_DMA_INT_STS_EN_MASK 0x00000040U

DMA Status Enable

◆ XNANDPSU_INTR_ERR_AHB_STS_EN_MASK

#define XNANDPSU_INTR_ERR_AHB_STS_EN_MASK 0x00000080U

Error AHB Status Enable

◆ XNANDPSU_INTR_ERR_INTR_STS_EN_MASK

#define XNANDPSU_INTR_ERR_INTR_STS_EN_MASK 0x00000010U

Single Bit Error Status Enable, BCH Detect Error Status Enable

◆ XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK

#define XNANDPSU_INTR_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

Multi Bit Error Status Enable

◆ XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK

#define XNANDPSU_INTR_SIG_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

Buffer Read Ready Signal Enable

◆ XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK

#define XNANDPSU_INTR_SIG_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

Buffer Write Ready Signal Enable

◆ XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK

#define XNANDPSU_INTR_SIG_EN_DMA_INT_STS_EN_MASK 0x00000040U

DMA Signal Enable

◆ XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK

#define XNANDPSU_INTR_SIG_EN_ERR_AHB_STS_EN_MASK 0x00000080U

Error AHB Signal Enable

◆ XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK

#define XNANDPSU_INTR_SIG_EN_ERR_INTR_STS_EN_MASK 0x00000010U

Single Bit Error Signal Enable, BCH Detect Error Signal Enable

◆ XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK

#define XNANDPSU_INTR_SIG_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

Multi Bit Error Signal Enable

◆ XNANDPSU_INTR_SIG_EN_OFFSET

#define XNANDPSU_INTR_SIG_EN_OFFSET 0x18U

Interrupt Signal Enable Register

◆ XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK

#define XNANDPSU_INTR_SIG_EN_TRANS_COMP_STS_EN_MASK 0x00000004U

Transfer Complete Signal Enable

◆ XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK

#define XNANDPSU_INTR_STS_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

Buffer Read Ready

◆ XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK

#define XNANDPSU_INTR_STS_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

Buffer Write Ready

◆ XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK

#define XNANDPSU_INTR_STS_DMA_INT_STS_EN_MASK 0x00000040U

DMA Interrupt

◆ XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK

#define XNANDPSU_INTR_STS_EN_BUFF_RD_RDY_STS_EN_MASK 0x00000002U

Buffer Read Ready Status Enable

◆ XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK

#define XNANDPSU_INTR_STS_EN_BUFF_WR_RDY_STS_EN_MASK 0x00000001U

Buffer Write Ready Status Enable

◆ XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK

#define XNANDPSU_INTR_STS_EN_DMA_INT_STS_EN_MASK 0x00000040U

DMA Status Enable

◆ XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK

#define XNANDPSU_INTR_STS_EN_ERR_AHB_STS_EN_MASK 0x00000080U

Error AHB Status Enable

◆ XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK

#define XNANDPSU_INTR_STS_EN_ERR_INTR_STS_EN_MASK 0x00000010U

Single Bit Error Status Enable, BCH Detect Error Status Enable

◆ XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK

#define XNANDPSU_INTR_STS_EN_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

Multi Bit Error Status Enable

◆ XNANDPSU_INTR_STS_EN_OFFSET

#define XNANDPSU_INTR_STS_EN_OFFSET 0x14U

Interrupt Status Enable Register

◆ XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK

#define XNANDPSU_INTR_STS_EN_TRANS_COMP_STS_EN_MASK 0x00000004U

Transfer Complete Status Enable

◆ XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK

#define XNANDPSU_INTR_STS_ERR_AHB_STS_EN_MASK 0x00000080U

Error AHB

◆ XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK

#define XNANDPSU_INTR_STS_ERR_INTR_STS_EN_MASK 0x00000010U

Single Bit Error, BCH Detect Error

◆ XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK

#define XNANDPSU_INTR_STS_MUL_BIT_ERR_STS_EN_MASK 0x00000008U

Multi Bit Error

◆ XNANDPSU_INTR_STS_OFFSET

#define XNANDPSU_INTR_STS_OFFSET 0x1CU

Interrupt Status Register

◆ XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK

#define XNANDPSU_INTR_STS_TRANS_COMP_STS_EN_MASK 0x00000004U

Transfer Complete

◆ XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK

#define XNANDPSU_INTR_TRANS_COMP_STS_EN_MASK 0x00000004U

Transfer Complete Status Enable

◆ XNandPsu_IntrSigClear

#define XNandPsu_IntrSigClear	(	InstancePtr,
		Mask
	)

Value:

        XNandPsu_ClrBits((InstancePtr),             \
            XNANDPSU_INTR_SIG_EN_OFFSET,            \
            (Mask))

This macro clears bitmask in Interrupt Signal Enable register.

Parameters

InstancePtr	is a pointer to the XNandPsu instance of the controller.
Mask	is the bitmask.

Note: C-style signature: void XNandPsu_IntrSigClear(XNandPsu *InstancePtr, u32 Mask)

◆ XNandPsu_IntrSigEnable

#define XNandPsu_IntrSigEnable	(	InstancePtr,
		Mask
	)

Value:

        XNandPsu_SetBits((InstancePtr),             \
            XNANDPSU_INTR_SIG_EN_OFFSET,            \
            (Mask))

This macro enables bitmask in Interrupt Signal Enable register.

Parameters

InstancePtr	is a pointer to the XNandPsu instance of the controller.
Mask	is the bitmask.

Note: C-style signature: void XNandPsu_IntrSigEnable(XNandPsu *InstancePtr, u32 Mask)

◆ XNandPsu_IntrStsEnable

#define XNandPsu_IntrStsEnable	(	InstancePtr,
		Mask
	)

Value:

        XNandPsu_SetBits((InstancePtr),             \
            XNANDPSU_INTR_STS_EN_OFFSET,            \
            (Mask))

This macro enables bitmask in Interrupt Status Enable register.

Parameters

InstancePtr	is a pointer to the XNandPsu instance of the controller.
Mask	is the bitmask.

Note: C-style signature: void XNandPsu_IntrStsEnable(XNandPsu *InstancePtr, u32 Mask)

◆ XNANDPSU_MAX_BLOCKS

#define XNANDPSU_MAX_BLOCKS 16384U

Max number of Blocks

◆ XNANDPSU_MAX_LUNS

#define XNANDPSU_MAX_LUNS 8U

Max number of LUNs

◆ XNANDPSU_MAX_PAGE_SIZE

#define XNANDPSU_MAX_PAGE_SIZE 16384U

Max page size supported

◆ XNANDPSU_MAX_PAGES_PER_BLOCK

#define XNANDPSU_MAX_PAGES_PER_BLOCK 512U

Max number pages per block

◆ XNANDPSU_MAX_PKT_COUNT

#define XNANDPSU_MAX_PKT_COUNT 0xFFFU

Max packet count

◆ XNANDPSU_MAX_PKT_SIZE

#define XNANDPSU_MAX_PKT_SIZE 0x7FFU

Max packet size

◆ XNANDPSU_MAX_SPARE_SIZE

#define XNANDPSU_MAX_SPARE_SIZE 0x800U

Max spare bytes of a NAND flash page of 16K

◆ XNANDPSU_MAX_TARGETS

#define XNANDPSU_MAX_TARGETS 1U

ce_n0, ce_n1

◆ XNANDPSU_MEM_ADDR1_COL_ADDR_MASK

#define XNANDPSU_MEM_ADDR1_COL_ADDR_MASK 0x0000FFFFU

Column Address Mask

◆ XNANDPSU_MEM_ADDR1_OFFSET

#define XNANDPSU_MEM_ADDR1_OFFSET 0x04U

Memory Address Register 1

◆ XNANDPSU_MEM_ADDR1_PG_ADDR_MASK

#define XNANDPSU_MEM_ADDR1_PG_ADDR_MASK 0xFFFF0000U

Page, Block Address Mask

◆ XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT

#define XNANDPSU_MEM_ADDR1_PG_ADDR_SHIFT 16U

Page Shift

◆ XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK

#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_MASK 0x01000000U

Bus Width

◆ XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT

#define XNANDPSU_MEM_ADDR2_BUS_WIDTH_SHIFT 24U

Bus width shift

◆ XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK

#define XNANDPSU_MEM_ADDR2_CHIP_SEL_MASK 0xC0000000U

Chip Select

◆ XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT

#define XNANDPSU_MEM_ADDR2_CHIP_SEL_SHIFT 30U

Chip select shift

◆ XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK

#define XNANDPSU_MEM_ADDR2_MEM_ADDR_MASK 0x000000FFU

Memory Address

◆ XNANDPSU_MEM_ADDR2_MODE_MASK

#define XNANDPSU_MEM_ADDR2_MODE_MASK 0x30000000U

Flash Connection Mode

◆ XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK

#define XNANDPSU_MEM_ADDR2_NFC_BCH_MODE_MASK 0x0E000000U

BCH Mode Value

◆ XNANDPSU_MEM_ADDR2_OFFSET

#define XNANDPSU_MEM_ADDR2_OFFSET 0x08U

Memory Address Register 2

◆ XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET

#define XNANDPSU_NO_OOB_BBT_DESC_SIG_OFFSET 0U

Bad Block Table signature offset in page memory

◆ XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET

#define XNANDPSU_NO_OOB_BBT_DESC_VER_OFFSET 4U

Bad block Table version offset in page memory

◆ XNANDPSU_PAGE_SIZE_16K

#define XNANDPSU_PAGE_SIZE_16K 16384U

16K bytes page

◆ XNANDPSU_PAGE_SIZE_1K_16BIT

#define XNANDPSU_PAGE_SIZE_1K_16BIT 1024U

16-bit 2K bytes page

◆ XNANDPSU_PAGE_SIZE_2K

#define XNANDPSU_PAGE_SIZE_2K 2048U

2K bytes page

◆ XNANDPSU_PAGE_SIZE_4K

#define XNANDPSU_PAGE_SIZE_4K 4096U

4K bytes page

◆ XNANDPSU_PAGE_SIZE_512

#define XNANDPSU_PAGE_SIZE_512 512U

512 bytes page

◆ XNANDPSU_PAGE_SIZE_8K

#define XNANDPSU_PAGE_SIZE_8K 8192U

8K bytes page

◆ XNANDPSU_PKT_OFFSET

#define XNANDPSU_PKT_OFFSET 0x00U

Packet Register

◆ XNANDPSU_PKT_PKT_CNT_MASK

#define XNANDPSU_PKT_PKT_CNT_MASK 0x00FFF000U

Packet Count

◆ XNANDPSU_PKT_PKT_CNT_SHIFT

#define XNANDPSU_PKT_PKT_CNT_SHIFT 12U

Packet Count Shift

◆ XNANDPSU_PKT_PKT_SIZE_MASK

#define XNANDPSU_PKT_PKT_SIZE_MASK 0x000007FFU

Packet Size

◆ XNANDPSU_PROG_BLK_ERASE_MASK

#define XNANDPSU_PROG_BLK_ERASE_MASK 0x00000004U

Block Erase

◆ XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK

#define XNANDPSU_PROG_CHNG_RD_COL_ENH_MASK 0x00004000U

Change Read Column Enhanced

◆ XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK

#define XNANDPSU_PROG_CHNG_ROW_ADDR_END_MASK 0x00400000U

Change Row Address End

◆ XNANDPSU_PROG_CHNG_ROW_ADDR_MASK

#define XNANDPSU_PROG_CHNG_ROW_ADDR_MASK 0x00200000U

Change Row Address

◆ XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK

#define XNANDPSU_PROG_COPY_BACK_INTRLVD_MASK 0x00008000U

Copy Back Interleaved

◆ XNANDPSU_PROG_GET_FEATURES_MASK

#define XNANDPSU_PROG_GET_FEATURES_MASK 0x00000200U

Get Features

◆ XNANDPSU_PROG_MUL_DIE_MASK

#define XNANDPSU_PROG_MUL_DIE_MASK 0x00000002U

Multi Die

◆ XNANDPSU_PROG_MUL_DIE_RD_MASK

#define XNANDPSU_PROG_MUL_DIE_RD_MASK 0x00000020U

Multi Die Rd

◆ XNANDPSU_PROG_ODT_CONF_MASK

#define XNANDPSU_PROG_ODT_CONF_MASK 0x04000000U

ODT Configure

◆ XNANDPSU_PROG_OFFSET

#define XNANDPSU_PROG_OFFSET 0x10U

Program Register

◆ XNANDPSU_PROG_PG_PROG_MASK

#define XNANDPSU_PROG_PG_PROG_MASK 0x00000010U

Page Program

◆ XNANDPSU_PROG_PGM_PG_CLR_MASK

#define XNANDPSU_PROG_PGM_PG_CLR_MASK 0x01000000U

Enhanced Program Page Register Clear

◆ XNANDPSU_PROG_RD_CACHE_END_MASK

#define XNANDPSU_PROG_RD_CACHE_END_MASK 0x00080000U

Read Cache End

◆ XNANDPSU_PROG_RD_CACHE_RAND_MASK

#define XNANDPSU_PROG_RD_CACHE_RAND_MASK 0x00040000U

Read Cache Random

◆ XNANDPSU_PROG_RD_CACHE_SEQ_MASK

#define XNANDPSU_PROG_RD_CACHE_SEQ_MASK 0x00020000U

Read Cache Sequential

◆ XNANDPSU_PROG_RD_CACHE_START_MASK

#define XNANDPSU_PROG_RD_CACHE_START_MASK 0x00010000U

Read Cache Start

◆ XNANDPSU_PROG_RD_ID_MASK

#define XNANDPSU_PROG_RD_ID_MASK 0x00000040U

Read ID

◆ XNANDPSU_PROG_RD_INTRLVD_MASK

#define XNANDPSU_PROG_RD_INTRLVD_MASK 0x00002000U

Read Interleaved

◆ XNANDPSU_PROG_RD_MASK

#define XNANDPSU_PROG_RD_MASK 0x00000001U

Read

◆ XNANDPSU_PROG_RD_PRM_PG_MASK

#define XNANDPSU_PROG_RD_PRM_PG_MASK 0x00000080U

Read Param Page

◆ XNANDPSU_PROG_RD_STS_ENH_MASK

#define XNANDPSU_PROG_RD_STS_ENH_MASK 0x00001000U

Read Status Enhanced

◆ XNANDPSU_PROG_RD_STS_MASK

#define XNANDPSU_PROG_RD_STS_MASK 0x00000008U

Read Status

◆ XNANDPSU_PROG_RD_UNQ_ID_MASK

#define XNANDPSU_PROG_RD_UNQ_ID_MASK 0x00000800U

Read Unique ID

◆ XNANDPSU_PROG_RST_LUN_MASK

#define XNANDPSU_PROG_RST_LUN_MASK 0x00800000U

Reset LUN

◆ XNANDPSU_PROG_RST_MASK

#define XNANDPSU_PROG_RST_MASK 0x00000100U

Reset

◆ XNANDPSU_PROG_SET_FEATURES_MASK

#define XNANDPSU_PROG_SET_FEATURES_MASK 0x00000400U

Set Features

◆ XNANDPSU_PROG_SMALL_DATA_MOVE_MASK

#define XNANDPSU_PROG_SMALL_DATA_MOVE_MASK 0x00100000U

Small Data Move

◆ XNANDPSU_PROG_VOL_SEL_MASK

#define XNANDPSU_PROG_VOL_SEL_MASK 0x02000000U

Volume Select

◆ XNandPsu_ReadModifyWrite

#define XNandPsu_ReadModifyWrite	(	InstancePtr,
		RegOffset,
		Mask,
		Value
	)

Value:

    XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,        \
        (RegOffset),                        \
    ((u32)((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,\
        (u32)(RegOffset)) & (u32)(~(Mask))) | (u32)(Value))))

This macro clears and updates the bitmask in the register.

Parameters

InstancePtr	is a pointer to the XNandPsu instance of the controller.
RegOffset	is the register offset.
Mask	is the bitmask.
Value	is the register value to write.

Note: C-style signature: void XNandPsu_ReadModifyWrite(XNandPsu *InstancePtr, u32 RegOffset, u32 Mask, u32 Val)

◆ XNandPsu_ReadReg

#define XNandPsu_ReadReg	(	BaseAddress,
		RegOffset
	)	Xil_In32((BaseAddress) + (RegOffset))

This macro reads the given register.

Parameters

BaseAddress	is the base address of controller registers.
RegOffset	is the register offset to be read.

Returns: The 32-bit value of the register.

Note: C-style signature: u32 XNandPsu_ReadReg(u32 BaseAddress, u32 RegOffset)

◆ XNANDPSU_READY_BUSY_OFFSET

#define XNANDPSU_READY_BUSY_OFFSET 0x20U

Ready/Busy status Register

◆ XNandPsu_SetBits

#define XNandPsu_SetBits	(	InstancePtr,
		RegOffset,
		BitMask
	)

Value:

    XNandPsu_WriteReg((InstancePtr)->Config.BaseAddress,        \
        (RegOffset),                        \
    ((u32)(XNandPsu_ReadReg((InstancePtr)->Config.BaseAddress,  \
        (RegOffset)) | (BitMask))))

This macro sets the bitmask in the register.

Parameters

InstancePtr	is a pointer to the XNandPsu instance of the controller.
RegOffset	is the register offset.
BitMask	is the bitmask.

Note: C-style signature: void XNandPsu_SetBits(XNandPsu *InstancePtr, u32 RegOffset, u32 BitMask)

◆ XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK

#define XNANDPSU_SLV_DMA_CONF_DMA_BURST_SIZE_MASK 0x00E00000U

Slave DMA Burst Size

◆ XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK

#define XNANDPSU_SLV_DMA_CONF_DMA_TMOUT_CNT_VAL_MASK 0x0F000000U

DMA Timeout Counter Value

◆ XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK

#define XNANDPSU_SLV_DMA_CONF_DMA_TRANS_CNT_MASK 0x001FFFFEU

Slave DMA Transfer Count

◆ XNANDPSU_SLV_DMA_CONF_OFFSET

#define XNANDPSU_SLV_DMA_CONF_OFFSET 0x80U

Slave DMA Configuration Register

◆ XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK

#define XNANDPSU_SLV_DMA_CONF_SDMA_EN_MASK 0x10000000U

Slave DMA Enable

◆ XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK

#define XNANDPSU_SLV_DMA_CONF_SDMA_TX_RX_MASK 0x00000001U

Slave DMA Transfer Direction

◆ XNANDPSU_TIMING_DQS_BUFF_SEL_MASK

#define XNANDPSU_TIMING_DQS_BUFF_SEL_MASK 0x00000078U

Write/Read data transaction value

◆ XNANDPSU_TIMING_OFFSET

#define XNANDPSU_TIMING_OFFSET 0x2CU

Timing Register

◆ XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK

#define XNANDPSU_TIMING_SLOW_FAST_TCAD_MASK 0x00000004U

Slow/Fast device

◆ XNANDPSU_TIMING_TADL_TIME_MASK

#define XNANDPSU_TIMING_TADL_TIME_MASK 0x00007F80U

Address latch enable to Data loading time

◆ XNANDPSU_TIMING_TCCS_TIME_MASK

#define XNANDPSU_TIMING_TCCS_TIME_MASK 0x00000003U

Change column setup time

◆ XNandPsu_WriteReg

#define XNandPsu_WriteReg	(	BaseAddress,
		RegOffset,
		Data
	)	Xil_Out32(((BaseAddress) + (RegOffset)), (Data))

This macro writes the given register.

Parameters

BaseAddress	is the the base address of controller registers.
RegOffset	is the register offset to be written.
Data	is the the 32-bit value to write to the register.

Returns: None.

Note: C-style signature: void XNandPsu_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)

◆ XQSPIPS_BASEADDR

#define XQSPIPS_BASEADDR 0XFF0F0000U

QSPI Base Address

◆ XQSPIPS_EN_REG

#define XQSPIPS_EN_REG ( ( XQSPIPS_BASEADDR ) + 0X00000014U )

Register: XQSPIPS_EN_REG

◆ XQSPIPS_LQSPI_CFG_RST_STATE

#define XQSPIPS_LQSPI_CFG_RST_STATE 0x800238C1U

Default LQSPI CFG value

◆ XQSPIPS_LQSPI_CR_4_BYTE_STATE

#define XQSPIPS_LQSPI_CR_4_BYTE_STATE 0x88000013U

Default 4 Byte LQSPI CR value

◆ XQSPIPS_LQSPI_CR_INST_MASK

#define XQSPIPS_LQSPI_CR_INST_MASK 0x000000FFU

Read instr code

◆ XQSPIPS_LQSPI_CR_RST_STATE

#define XQSPIPS_LQSPI_CR_RST_STATE 0x80000003U

Default LQSPI CR value

◆ XQSPIPSU_CFG_OFFSET

#define XQSPIPSU_CFG_OFFSET 0X00000000U

Register: XQSPIPSU_CFG

◆ XQSPIPSU_CLK_ACTIVE_LOW_OPTION

#define XQSPIPSU_CLK_ACTIVE_LOW_OPTION 0x2U

Clk Active low option

◆ XQSPIPSU_CLK_PHASE_1_OPTION

#define XQSPIPSU_CLK_PHASE_1_OPTION 0x4U

Clk phase 1 option

◆ XQSPIPSU_CLK_PRESCALE_128

#define XQSPIPSU_CLK_PRESCALE_128 0x06U

Clock prescale 128

◆ XQSPIPSU_CLK_PRESCALE_16

#define XQSPIPSU_CLK_PRESCALE_16 0x03U

Clock prescale 16

◆ XQSPIPSU_CLK_PRESCALE_2

#define XQSPIPSU_CLK_PRESCALE_2 0x00U

Clock prescale 2

◆ XQSPIPSU_CLK_PRESCALE_256

#define XQSPIPSU_CLK_PRESCALE_256 0x07U

Clock prescale 256

◆ XQSPIPSU_CLK_PRESCALE_32

#define XQSPIPSU_CLK_PRESCALE_32 0x04U

Clock prescale 32

◆ XQSPIPSU_CLK_PRESCALE_4

#define XQSPIPSU_CLK_PRESCALE_4 0x01U

Clock prescale 4

◆ XQSPIPSU_CLK_PRESCALE_64

#define XQSPIPSU_CLK_PRESCALE_64 0x05U

Clock prescale 64

◆ XQSPIPSU_CLK_PRESCALE_8

#define XQSPIPSU_CLK_PRESCALE_8 0x02U

Clock prescale 8

◆ XQSPIPSU_CONNECTION_MODE_PARALLEL

#define XQSPIPSU_CONNECTION_MODE_PARALLEL 2U

Parallel mode connection

◆ XQSPIPSU_CONNECTION_MODE_SINGLE

#define XQSPIPSU_CONNECTION_MODE_SINGLE 0U

Single mode connection

◆ XQSPIPSU_CONNECTION_MODE_STACKED

#define XQSPIPSU_CONNECTION_MODE_STACKED 1U

Stacked mode connection

◆ XQSPIPSU_CR_PRESC_MAXIMUM

#define XQSPIPSU_CR_PRESC_MAXIMUM 7U

Prescale max

◆ XQSPIPSU_DATA_DLY_ADJ_OFFSET

#define XQSPIPSU_DATA_DLY_ADJ_OFFSET 0X000000F8U

QSPI Data delay register

◆ XQspiPsu_Disable

#define XQspiPsu_Disable ( InstancePtr )

Value:

XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \

XQSPIPSU_EN_OFFSET, 0x0U)

XQSPIPSU_EN_OFFSET

#define XQSPIPSU_EN_OFFSET

Definition: xqspipsu_hw.h:378

XQspiPsu_Out32

#define XQspiPsu_Out32

Definition: xqspipsu_hw.h:963

Disable QSPI controller

◆ XQSPIPSU_DMA_BYTES_MAX

#define XQSPIPSU_DMA_BYTES_MAX 0x10000000U

DMA bytes max

◆ XQSPIPSU_EN_OFFSET

#define XQSPIPSU_EN_OFFSET 0X00000014U

Register: XQSPIPSU_EN_REG

◆ XQspiPsu_Enable

#define XQspiPsu_Enable ( InstancePtr )

Value:

XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \

XQSPIPSU_EN_OFFSET, XQSPIPSU_EN_MASK)

Enable QSPI Controller

◆ XQSPIPSU_FIFO_CTRL_OFFSET

#define XQSPIPSU_FIFO_CTRL_OFFSET 0X0000004CU

Register: XQSPIPSU_FIFO_CTRL

◆ XQSPIPSU_FREQ_100MHZ

#define XQSPIPSU_FREQ_100MHZ 100000000U

Frequency 100 Mhz

◆ XQSPIPSU_FREQ_150MHZ

#define XQSPIPSU_FREQ_150MHZ 150000000U

Frequency 150 Mhz

◆ XQSPIPSU_FREQ_37_5MHZ

#define XQSPIPSU_FREQ_37_5MHZ 37500000U

Frequency 375 Mhz

◆ XQSPIPSU_FREQ_40MHZ

#define XQSPIPSU_FREQ_40MHZ 40000000U

Frequency 40 Mhz

◆ XQSPIPSU_GEN_FIFO_OFFSET

#define XQSPIPSU_GEN_FIFO_OFFSET 0X00000040U

Register: XQSPIPSU_GEN_FIFO

◆ XQSPIPSU_GENFIFO_CS_HOLD

#define XQSPIPSU_GENFIFO_CS_HOLD 0x04U

Chip select hold in GENFIFO

◆ XQSPIPSU_GENFIFO_CS_SETUP

#define XQSPIPSU_GENFIFO_CS_SETUP 0x05U

Chip select setup in GENFIO

◆ XQSPIPSU_GENFIFO_EXP_START

#define XQSPIPSU_GENFIFO_EXP_START 0x100U

Genfifo start

◆ XQSPIPSU_GENFIFO_IMM_DATA_MASK

#define XQSPIPSU_GENFIFO_IMM_DATA_MASK 0xFFU

Generic FIFO masks

◆ XQspiPsu_GetLqspiConfigReg

#define XQspiPsu_GetLqspiConfigReg ( InstancePtr )

Value:

XQspiPsu_In32((XQSPIPS_BASEADDR) + \

XQSPIPSU_LQSPI_CR_OFFSET)

XQSPIPSU_LQSPI_CR_OFFSET

#define XQSPIPSU_LQSPI_CR_OFFSET

Definition: xqspipsu_hw.h:145

XQSPIPS_BASEADDR

#define XQSPIPS_BASEADDR

Definition: xqspipsu_hw.h:63

XQspiPsu_In32

#define XQspiPsu_In32

Definition: xqspipsu_hw.h:962

Read Configuration register of LQSPI Controller

◆ XQSPIPSU_GF_SNAPSHOT_OFFSET

#define XQSPIPSU_GF_SNAPSHOT_OFFSET 0X00000060U

Register: XQSPIPSU_GF_SNAPSHOT

◆ XQSPIPSU_GF_THRESHOLD_OFFSET

#define XQSPIPSU_GF_THRESHOLD_OFFSET 0X00000050U

Register: XQSPIPSU_GF_THRESHOLD

◆ XQSPIPSU_GPIO_OFFSET

#define XQSPIPSU_GPIO_OFFSET 0X00000030U

Register: XQSPIPSU_GPIO

◆ XQSPIPSU_H_

#define XQSPIPSU_H_

< prevent circular inclusions by using protection macros

◆ XQSPIPSU_HW_H

#define XQSPIPSU_HW_H

< prevent circular inclusions by using protection macros

◆ XQSPIPSU_IDR_OFFSET

#define XQSPIPSU_IDR_OFFSET 0X0000000CU

Register: XQSPIPSU_IDR

◆ XQSPIPSU_IER_OFFSET

#define XQSPIPSU_IER_OFFSET 0X00000008U

Register: XQSPIPSU_IER

◆ XQSPIPSU_IMR_OFFSET

#define XQSPIPSU_IMR_OFFSET 0X00000010U

Register: XQSPIPSU_IMR

◆ XQspiPsu_In32

#define XQspiPsu_In32 Xil_In32

Read the 32 bit register value

◆ XQSPIPSU_ISR_OFFSET

#define XQSPIPSU_ISR_OFFSET 0X00000004U

Register: XQSPIPSU_ISR

◆ XQSPIPSU_LPBK_DLY_ADJ_OFFSET

#define XQSPIPSU_LPBK_DLY_ADJ_OFFSET 0X00000038U

Register: XQSPIPSU_LPBK_DLY_ADJ

◆ XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK

#define XQSPIPSU_LQSPI_CR_ADDR_32BIT_MASK 0x01000000U

Upper memory page

◆ XQSPIPSU_LQSPI_CR_LINEAR_MASK

#define XQSPIPSU_LQSPI_CR_LINEAR_MASK 0x80000000U

LQSPI mode enable

◆ XQSPIPSU_LQSPI_CR_MODE_BITS_MASK

#define XQSPIPSU_LQSPI_CR_MODE_BITS_MASK 0x00FF0000U

Mode value for dual I/O or quad I/O

◆ XQSPIPSU_LQSPI_CR_MODE_EN_MASK

#define XQSPIPSU_LQSPI_CR_MODE_EN_MASK 0x02000000U

Enable mode bits

◆ XQSPIPSU_LQSPI_CR_MODE_ON_MASK

#define XQSPIPSU_LQSPI_CR_MODE_ON_MASK 0x01000000U

Mode on

◆ XQSPIPSU_LQSPI_CR_OFFSET

#define XQSPIPSU_LQSPI_CR_OFFSET 0X000000A0U

Register: XQSPIPSU_LQSPI

◆ XQSPIPSU_LQSPI_CR_SEP_BUS_MASK

#define XQSPIPSU_LQSPI_CR_SEP_BUS_MASK 0x20000000U

Separate memory bus

◆ XQSPIPSU_LQSPI_CR_TWO_MEM_MASK

#define XQSPIPSU_LQSPI_CR_TWO_MEM_MASK 0x40000000U

Both memories or one

◆ XQSPIPSU_LQSPI_CR_U_PAGE_MASK

#define XQSPIPSU_LQSPI_CR_U_PAGE_MASK 0x10000000U

Upper memory page

◆ XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB

#define XQSPIPSU_LQSPI_LESS_THEN_SIXTEENMB 1U

LQSPI less Than 16 MB

◆ XQSPIPSU_LQSPI_MODE_OPTION

#define XQSPIPSU_LQSPI_MODE_OPTION 0x20U

LQSPI mode option

◆ XQSPIPSU_MANUAL_START_OPTION

#define XQSPIPSU_MANUAL_START_OPTION 0x8U

Manual start option

◆ XQSPIPSU_MOD_ID_OFFSET

#define XQSPIPSU_MOD_ID_OFFSET 0X000000FCU

Register: XQSPIPSU_MOD_ID

◆ XQSPIPSU_MSG_FLAG_POLL

#define XQSPIPSU_MSG_FLAG_POLL 0x8U

POLL Msg flag

◆ XQSPIPSU_MSG_FLAG_RX

#define XQSPIPSU_MSG_FLAG_RX 0x2U

Rx Msg flag

◆ XQSPIPSU_MSG_FLAG_STRIPE

#define XQSPIPSU_MSG_FLAG_STRIPE 0x1U

Stripe Msg flag

◆ XQSPIPSU_MSG_FLAG_TX

#define XQSPIPSU_MSG_FLAG_TX 0x4U

Tx Msg flag

◆ XQSPIPSU_NUM_OPTIONS

#define XQSPIPSU_NUM_OPTIONS (sizeof(OptionsTable) / sizeof(OptionsMap))

Number of options in option table

◆ XQspiPsu_Out32

#define XQspiPsu_Out32 Xil_Out32

Write the 32 bit register value

◆ XQSPIPSU_POLL_CFG_OFFSET

#define XQSPIPSU_POLL_CFG_OFFSET 0X00000054U

Register: XQSPIPSU_POLL_CFG

◆ XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET

#define XQSPIPSU_QSPIDMA_DST_ADDR_OFFSET 0X00000700U

Register: XQSPIPSU_QSPIDMA_DST_ADDR

◆ XQSPIPSU_READMODE_DMA

#define XQSPIPSU_READMODE_DMA 0x0U

DMA read mode

◆ XQSPIPSU_READMODE_IO

#define XQSPIPSU_READMODE_IO 0x1U

IO read mode

◆ XQspiPsu_ReadReg

#define XQspiPsu_ReadReg	(	BaseAddress,
		RegOffset
	)	XQspiPsu_In32((BaseAddress) + (RegOffset))

Read a register.

Parameters

BaseAddress	contains the base address of the device.
RegOffset	contains the offset from the 1st register of the device to the target register.

Returns: The value read from the register.

Note: C-Style signature: u32 XQspiPsu_ReadReg(u32 BaseAddress. s32 RegOffset)

◆ XQSPIPSU_RX_COPY_OFFSET

#define XQSPIPSU_RX_COPY_OFFSET 0X00000064U

Register: XQSPIPSU_RX_COPY

◆ XQSPIPSU_RXADDR_OVER_32BIT

#define XQSPIPSU_RXADDR_OVER_32BIT 0x100000000U

Rx address over 32 bit

◆ XQSPIPSU_RXD_OFFSET

#define XQSPIPSU_RXD_OFFSET 0X00000020U

Register: XQSPIPSU_RXD

◆ XQSPIPSU_SEL_OFFSET

#define XQSPIPSU_SEL_OFFSET 0X00000044U

Register: XQSPIPSU_SEL

◆ XQspiPsu_Select

#define XQspiPsu_Select	(	InstancePtr,
		Mask
	)

Value:

XQspiPsu_Out32(((InstancePtr)->Config.BaseAddress) + \

XQSPIPSU_SEL_OFFSET, (Mask))

XQSPIPSU_SEL_OFFSET

#define XQSPIPSU_SEL_OFFSET

Definition: xqspipsu_hw.h:502

select QSPI controller

◆ XQSPIPSU_SELECT_FLASH_BUS_BOTH

#define XQSPIPSU_SELECT_FLASH_BUS_BOTH 0x3U

Select both bus flash

◆ XQSPIPSU_SELECT_FLASH_BUS_LOWER

#define XQSPIPSU_SELECT_FLASH_BUS_LOWER 0x1U

Select lower bus flash

◆ XQSPIPSU_SELECT_FLASH_BUS_UPPER

#define XQSPIPSU_SELECT_FLASH_BUS_UPPER 0x2U

Select upper bus flash

◆ XQSPIPSU_SELECT_FLASH_CS_BOTH

#define XQSPIPSU_SELECT_FLASH_CS_BOTH 0x3U

Select both flash

◆ XQSPIPSU_SELECT_FLASH_CS_LOWER

#define XQSPIPSU_SELECT_FLASH_CS_LOWER 0x1U

Select lower flash

◆ XQSPIPSU_SELECT_FLASH_CS_UPPER

#define XQSPIPSU_SELECT_FLASH_CS_UPPER 0x2U

Select upper flash

◆ XQSPIPSU_SELECT_MODE_DUALSPI

#define XQSPIPSU_SELECT_MODE_DUALSPI 0x2U

Select dual SPI mode

◆ XQSPIPSU_SELECT_MODE_QUADSPI

#define XQSPIPSU_SELECT_MODE_QUADSPI 0x4U

Select quad SPI mode

◆ XQSPIPSU_SELECT_MODE_SPI

#define XQSPIPSU_SELECT_MODE_SPI 0x1U

Select SPI mode

◆ XQSPIPSU_SET_WP

#define XQSPIPSU_SET_WP 1

GQSPI configuration to toggle WP of flash

◆ XQSPIPSU_TX_THRESHOLD_OFFSET

#define XQSPIPSU_TX_THRESHOLD_OFFSET 0X00000028U

Register: XQSPIPSU_TX_THRESHOLD

◆ XQSPIPSU_TXD_OFFSET

#define XQSPIPSU_TXD_OFFSET 0X0000001CU

Register: XQSPIPSU_TXD

◆ XQspiPsu_WriteReg

#define XQspiPsu_WriteReg	(	BaseAddress,
		RegOffset,
		RegisterValue
	)	XQspiPsu_Out32((BaseAddress) + (RegOffset), (RegisterValue))

Write to a register.

Parameters

BaseAddress	contains the base address of the device.
RegOffset	contains the offset from the 1st register of the device to target register.
RegisterValue	is the value to be written to the register.

Returns: None.

Note: C-Style signature: void XQspiPsu_WriteReg(u32 BaseAddress, s32 RegOffset, u32 RegisterValue) XQSPIPSU_H

◆ XQSPIPSU_XFER_STS_OFFSET

#define XQSPIPSU_XFER_STS_OFFSET 0X0000005CU

Register: XQSPIPSU_XFER_STS

Typedef Documentation

◆ XQspiPsu_StatusHandler

typedef void(* XQspiPsu_StatusHandler) (const void *CallBackRef, u32 StatusEvent, u32 ByteCount)

The handler data type allows the user to define a callback function to handle the asynchronous processing for the QSPIPSU device. The application using this driver is expected to define a handler of this type to support interrupt driven mode. The handler executes in an interrupt context, so only minimal processing should be performed.

Parameters

CallBackRef	is the callback reference passed in by the upper layer when setting the callback functions, and passed back to the upper layer when the callback is invoked. Its type is not important to the driver, so it is a void pointer.
StatusEvent	holds one or more status events that have occurred. See the XQspiPsu_SetStatusHandler() for details on the status events that can be passed in the callback.
ByteCount	indicates how many bytes of data were successfully transferred. This may be less than the number of bytes requested if the status event indicates an error.

Enumeration Type Documentation

◆ OnfiCommandList

enum OnfiCommandList

This enum defines the ONFI 3.1 commands.

Enumerator
READ	Read
MULTIPLANE_READ	Multiplane Read
COPYBACK_READ	Copyback Read
CHANGE_READ_COLUMN	Change Read Column
CHANGE_READ_COLUMN_ENHANCED	Change Read Column Enhanced
READ_CACHE_RANDOM	Read Cache Random
READ_CACHE_SEQUENTIAL	Read Cache Sequential
READ_CACHE_END	Read Cache End
BLOCK_ERASE	Block Erase
MULTIPLANE_BLOCK_ERASE	Multiplane Block Erase
READ_STATUS	Read Status
READ_STATUS_ENHANCED	Read Status Enhanced
PAGE_PROGRAM	Page Program
MULTIPLANE_PAGE_PROGRAM	Multiplane Page Program
PAGE_CACHE_PROGRAM	Page Cache Program
COPYBACK_PROGRAM	Copyback Program
MULTIPLANE_COPYBACK_PROGRAM	Multiplance Copyback Program
SMALL_DATA_MOVE	Small Data Move
CHANGE_WRITE_COLUMN	Change Write Column
CHANGE_ROW_ADDR	Change Row Address
READ_ID	Read ID
VOLUME_SELECT	Volume Select
ODT_CONFIGURE	ODT Configure
READ_PARAM_PAGE	Read Parameter Page
READ_UNIQUE_ID	Read Unique ID
GET_FEATURES	Get Features
SET_FEATURES	Set Features
LUN_GET_FEATURES	LUN Get Features
LUN_SET_FEATURES	LUN Set Features
RESET_LUN	Reset LUN
SYN_RESET	Synchronous Reset
RESET	Reset
MAX_CMDS	Dummy Command

◆ XNandPsu_DataInterface

enum XNandPsu_DataInterface

The XNandPsu_DataInterface enum contains flash operating mode.

Enumerator
XNANDPSU_SDR	Single Data Rate
XNANDPSU_NVDDR	Double Data Rate

◆ XNandPsu_DmaMode

enum XNandPsu_DmaMode

The XNandPsu_DmaMode enum contains the controller MDMA mode.

Enumerator
XNANDPSU_PIO	PIO Mode
XNANDPSU_SDMA	SDMA Mode
XNANDPSU_MDMA	MDMA Mode

◆ XNandPsu_EccMode

enum XNandPsu_EccMode

The XNandPsu_EccMode enum contains ECC functionality.

◆ XNandPsu_SWMode

enum XNandPsu_SWMode

The XNandPsu_SWMode enum contains the driver operating mode.

Enumerator
XNANDPSU_POLLING	Polling
XNANDPSU_INTERRUPT	Interrupt

◆ XNandPsu_TimingMode

enum XNandPsu_TimingMode

XNandPsu_TimingMode enum contains timing modes.

Function Documentation

◆ XNandPsu_CfgInitialize()

s32 XNandPsu_CfgInitialize	(	XNandPsu *	InstancePtr,
		XNandPsu_Config *	ConfigPtr,
		u32	EffectiveAddr
	)

This function initializes a specific XNandPsu instance. This function must be called prior to using the NAND flash device to read or write any data.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
ConfigPtr	points to XNandPsu device configuration structure.
EffectiveAddr	is the base address of NAND flash controller.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

Note: The user needs to first call the XNandPsu_LookupConfig() API which returns the Configuration structure pointer which is passed as a parameter to the XNandPsu_CfgInitialize() API.

◆ XNandPsu_ChangeTimingMode()

s32 XNandPsu_ChangeTimingMode	(	XNandPsu *	InstancePtr,
		XNandPsu_DataInterface	NewIntf,
		XNandPsu_TimingMode	NewMode
	)

This function changes the data interface and timing mode.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
NewIntf	is the new data interface.
NewMode	is the new timing mode.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

◆ XNandPsu_DisableDmaMode()

void XNandPsu_DisableDmaMode ( XNandPsu * InstancePtr )

This function disables DMA mode of driver/controller operation.

Parameters

InstancePtr is a pointer to the XNandPsu instance.

Returns: None

Note: None

◆ XNandPsu_DisableEccMode()

void XNandPsu_DisableEccMode ( XNandPsu * InstancePtr )

This function disables ECC mode of driver/controller operation.

Parameters

InstancePtr is a pointer to the XNandPsu instance.

Returns: None

Note: None

◆ XNandPsu_EnableDmaMode()

void XNandPsu_EnableDmaMode ( XNandPsu * InstancePtr )

This function enables DMA mode of controller operation.

Parameters

InstancePtr is a pointer to the XNandPsu instance.

Returns: None

Note: None

◆ XNandPsu_EnableEccMode()

void XNandPsu_EnableEccMode ( XNandPsu * InstancePtr )

This function enables ECC mode of driver/controller operation.

Parameters

InstancePtr is a pointer to the XNandPsu instance.

Returns: None

Note: None

◆ XNandPsu_Erase()

s32 XNandPsu_Erase	(	XNandPsu *	InstancePtr,
		u64	Offset,
		u64	Length
	)

This function erases the flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Offset	is the starting offset of flash to erase.
Length	is the number of bytes to erase.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: The Offset and Length should be aligned to block size boundary to get better results.

◆ XNandPsu_EraseBlock()

s32 XNandPsu_EraseBlock	(	XNandPsu *	InstancePtr,
		u32	Target,
		u32	Block
	)

This function sends ONFI block erase command to the flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Target	is the chip select value.
Block	is the block to erase.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

◆ XNandPsu_GetFeature()

s32 XNandPsu_GetFeature	(	XNandPsu *	InstancePtr,
		u32	Target,
		u8	Feature,
		u8 *	Buf
	)

This function sends ONFI Get Feature command to flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Target	is the chip select value.
Feature	is the feature selector.
Buf	is the buffer to fill feature value.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

◆ XNandPsu_InitBbtDesc()

void XNandPsu_InitBbtDesc ( XNandPsu * InstancePtr )

This function initializes the Bad Block Table(BBT) descriptors with a predefined pattern for searching Bad Block Table(BBT) in flash.

Parameters

InstancePtr is a pointer to the XNandPsu instance.

Returns

NONE

◆ XNandPsu_IsBlockBad()

s32 XNandPsu_IsBlockBad	(	XNandPsu *	InstancePtr,
		u32	Block
	)

This function checks whether a block is bad or not.

Parameters

InstancePtr	is the pointer to the XNandPsu instance.
Block	is the block number.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

◆ XNandPsu_MarkBlockBad()

s32 XNandPsu_MarkBlockBad	(	XNandPsu *	InstancePtr,
		u32	Block
	)

This function marks a block as bad in the RAM based Bad Block Table(BBT). It also updates the Bad Block Table(BBT) in the flash.

Parameters

InstancePtr	is the pointer to the XNandPsu instance.
Block	is the block number.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

◆ XNandPsu_OnfiParamPageCrc()

u32 XNandPsu_OnfiParamPageCrc	(	u8 *	ParamBuf,
		u32	StartOff,
		u32	Length
	)

This function calculates ONFI parameter page CRC.

Parameters

ParamBuf	is a pointer to the ONFI parameter page buffer.
StartOff	is the starting offset in buffer to calculate CRC.
Length	is the number of bytes for which CRC is calculated.

Returns: CRC value.

Note: None.

◆ XNandPsu_Prepare_Cmd()

void XNandPsu_Prepare_Cmd	(	XNandPsu *	InstancePtr,
		u8	Cmd1,
		u8	Cmd2,
		u8	EccState,
		u8	DmaMode,
		u8	AddrCycles
	)

This function prepares command to be written into command register.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Cmd1	is the first Onfi Command.
Cmd2	is the second Onfi Command.
EccState	is the flag to set Ecc State.
DmaMode	is the flag to set DMA mode.
AddrCycles	is the number of Address Cycles.

Returns: None

Note: None

◆ XNandPsu_Read()

s32 XNandPsu_Read	(	XNandPsu *	InstancePtr,
		u64	Offset,
		u64	Length,
		u8 *	DestBuf
	)

This function reads from the flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Offset	is the starting offset of flash to read.
Length	is the number of bytes to read.
DestBuf	is the destination data buffer to fill in.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

◆ XNandPsu_ReadSpareBytes()

s32 XNandPsu_ReadSpareBytes	(	XNandPsu *	InstancePtr,
		u32	Page,
		u8 *	Buf
	)

This function reads spare bytes from flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Page	is the page address value to read.
Buf	is the data buffer to fill in.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

◆ XNandPsu_ScanBbt()

s32 XNandPsu_ScanBbt ( XNandPsu * InstancePtr )

This function reads the Bad Block Table(BBT) if present in flash. If not it scans the flash for detecting factory marked bad blocks and creates a bad block table and write the Bad Block Table(BBT) into the flash.

Parameters

InstancePtr is a pointer to the XNandPsu instance.

Returns

XST_SUCCESS if successful.
XST_FAILURE if fail.

◆ XNandPsu_SetFeature()

s32 XNandPsu_SetFeature	(	XNandPsu *	InstancePtr,
		u32	Target,
		u8	Feature,
		u8 *	Buf
	)

This function sends ONFI Set Feature command to flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Target	is the chip select value.
Feature	is the feature selector.
Buf	is the feature value to send.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

◆ XNandPsu_Write()

s32 XNandPsu_Write	(	XNandPsu *	InstancePtr,
		u64	Offset,
		u64	Length,
		u8 *	SrcBuf
	)

This function writes to the flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Offset	is the starting offset of flash to write.
Length	is the number of bytes to write.
SrcBuf	is the source data buffer to write.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

◆ XNandPsu_WriteSpareBytes()

s32 XNandPsu_WriteSpareBytes	(	XNandPsu *	InstancePtr,
		u32	Page,
		u8 *	Buf
	)

This function sends ONFI Program Page command to flash.

Parameters

InstancePtr	is a pointer to the XNandPsu instance.
Page	is the page address value to program.
Buf	is the data buffer to program.

Returns

XST_SUCCESS if successful.
XST_FAILURE if failed.

Note: None

◆ XQspiPsu_Abort()

void XQspiPsu_Abort ( XQspiPsu * InstancePtr )

Aborts a transfer in progress.

Parameters

InstancePtr is a pointer to the XQspiPsu instance.

Returns: None.

Note: None.

◆ XQspiPsu_CfgInitialize()

s32 XQspiPsu_CfgInitialize	(	XQspiPsu *	InstancePtr,
		const XQspiPsu_Config *	ConfigPtr,
		UINTPTR	EffectiveAddr
	)

Initializes a specific XQspiPsu instance as such the driver is ready to use.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
ConfigPtr	is a reference to a structure containing information about a specific QSPIPSU device. This function initializes an InstancePtr object for a specific device specified by the contents of Config.
EffectiveAddr	is the device base address in the virtual memory address space. The caller is responsible for keeping the address mapping from EffectiveAddr to the device physical base address unchanged once this function is invoked. Unexpected errors may occur if the address mapping changes after this function is called. If address translation is not used, use ConfigPtr->Config.BaseAddress for this device.

Returns

XST_SUCCESS if successful.
XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.

Note: None.

◆ XQspiPsu_CheckDmaDone()

s32 XQspiPsu_CheckDmaDone ( XQspiPsu * InstancePtr )

This function check for DMA transfer complete.

Parameters

InstancePtr is a pointer to the XQspiPsu instance.

Returns

XST_SUCCESS if DMA transfer complete.
XST_FAILURE if DMA transfer is not completed.

Note: None.

◆ XQspiPsu_ClearOptions()

s32 XQspiPsu_ClearOptions	(	XQspiPsu *	InstancePtr,
		u32	Options
	)

This function resets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus. The device must be idle rather than busy transferring data before setting these device options.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Options	contains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned OFF and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file xqspipsu.h.

Returns

XST_SUCCESS if options are successfully set.
XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.

Note: This function is not thread-safe.

◆ XQspiPsu_CreatePollDataConfig()

u32 XQspiPsu_CreatePollDataConfig	(	const XQspiPsu *	InstancePtr,
		const XQspiPsu_Msg *	FlashMsg
	)

This function creates Poll config register data to write

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
FlashMsg	is a pointer to the structure containing transfer data.

Returns: None

Note: None.

◆ XQspiPsu_FillTxFifo()

void XQspiPsu_FillTxFifo	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	Size
	)

Fills the TX FIFO as long as there is room in the FIFO or the bytes required to be transmitted.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
Size	is the number of bytes to be transmitted.

Returns: None

Note: None.

◆ XQspiPsu_GenFifoEntryData()

void XQspiPsu_GenFifoEntryData	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

This function writes the GENFIFO entries to transmit the messages requested.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

◆ XQspiPsu_GenFifoEntryDataLen()

void XQspiPsu_GenFifoEntryDataLen	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32 *	GenFifoEntry
	)

This function writes the Data length to GENFIFO entries that need to be transmitted or received.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
GenFifoEntry	is index of the current message to be handled.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

◆ XQspiPsu_GetOptions()

u32 XQspiPsu_GetOptions ( const XQspiPsu * InstancePtr )

This function gets the options for the QSPIPSU device. The options control how the device behaves relative to the QSPIPSU bus.

Parameters

InstancePtr is a pointer to the XQspiPsu instance.

Returns

Options contains the specified options currently set. This is a bit value where a 1 means the option is on, and a 0 means the option is off. See the bit definitions named XQSPIPSU_*_OPTIONS in file xqspipsu.h.

Note: None.

◆ XQspiPsu_Idle()

void XQspiPsu_Idle ( const XQspiPsu * InstancePtr )

Stops the transfer of data to internal DST FIFO from stream interface and also stops the issuing of new write commands to memory.

By calling this API, any ongoing Dma transfers will be paused and DMA will not issue AXI write commands to memory

Parameters

InstancePtr is a pointer to the XQspiPsu instance.

Returns: None.

Note: None.

◆ XQspiPsu_InterruptHandler()

s32 XQspiPsu_InterruptHandler ( XQspiPsu * InstancePtr )

Handles interrupt based transfers by acting on GENFIFO and DMA interurpts.

Parameters

InstancePtr is a pointer to the XQspiPsu instance.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.

Note: None.

◆ XQspiPsu_InterruptTransfer()

s32 XQspiPsu_InterruptTransfer	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	NumMsg
	)

This function initiates a transfer on the bus and enables interrupts. The transfer is completed by the interrupt handler. The messages passed are all transferred on the bus between one CS assert and de-assert.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
NumMsg	is the number of messages to be transferred.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

◆ XQspiPsu_IORead()

void XQspiPsu_IORead	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	StatusReg
	)

This function reads data from RXFifo in IO mode.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
StatusReg	is the Interrupt status Register value.

Returns: None.

Note: None.

◆ XQspiPsu_PollDataConfig()

void XQspiPsu_PollDataConfig	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	FlashMsg
	)

This function enables the polling functionality of controller

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
FlashMsg	is a pointer to the structure containing transfer data

Returns: None

Note: None.

◆ XQspiPsu_PollDataHandler()

void XQspiPsu_PollDataHandler	(	XQspiPsu *	InstancePtr,
		u32	StatusReg
	)

This is the handler for polling functionality of controller. It reads data from RXFIFO, since when data from the flash device (status data) matched with configured value in poll_cfg, then controller writes the matched data into RXFIFO.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
StatusReg	is the Interrupt status Register value.

Returns: None.

Note: None.

◆ XQspiPsu_PolledTransfer()

s32 XQspiPsu_PolledTransfer	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	NumMsg
	)

This function performs a transfer on the bus in polled mode. The messages passed are all transferred on the bus between one CS assert and de-assert.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
NumMsg	is the number of messages to be transferred.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

◆ XQspiPsu_ReadRxFifo()

void XQspiPsu_ReadRxFifo	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		s32	Size
	)

Read the specified number of bytes from RX FIFO

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
Size	is the number of bytes to be read.

Returns: None

Note: None.

◆ XQspiPsu_Reset()

void XQspiPsu_Reset ( XQspiPsu * InstancePtr )

Resets the QSPIPSU device. Reset must only be called after the driver has been initialized. Any data transfer that is in progress is aborted.

The upper layer software is responsible for re-configuring (if necessary) and restarting the QSPIPSU device after the reset.

Parameters

InstancePtr is a pointer to the XQspiPsu instance.

Returns: None.

Note: None.

◆ XQspiPsu_RXSetup()

void XQspiPsu_RXSetup	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

This function checks the RX buffers in the message and setup the RX DMA as required.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.

Returns: None

Note: None.

◆ XQspiPsu_SelectFlash()

void XQspiPsu_SelectFlash	(	XQspiPsu *	InstancePtr,
		u8	FlashCS,
		u8	FlashBus
	)

This function should be used to tell the QSPIPSU driver the HW flash configuration being used. This API should be called at least once in the application. If desired, it can be called multiple times when switching between communicating to different flahs devices/using different configs.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
FlashCS	- Flash Chip Select.
FlashBus	- Flash Bus (Upper, Lower or Both).

Returns

XST_SUCCESS if successful.
XST_DEVICE_IS_STARTED if the device is already started. It must be stopped to re-initialize.

Note: If this function is not called at least once in the application, the driver assumes there is a single flash connected to the lower bus and CS line.

◆ XQspiPsu_SelectSpiMode()

u32 XQspiPsu_SelectSpiMode ( u8 SpiMode )

Selects SPI mode - x1 or x2 or x4.

Parameters

SpiMode - spi or dual or quad.

Returns: Mask to set desired SPI mode in GENFIFO entry.

Note: None.

◆ XQspiPsu_SetClkPrescaler()

s32 XQspiPsu_SetClkPrescaler	(	const XQspiPsu *	InstancePtr,
		u8	Prescaler
	)

Configures the clock according to the prescaler passed.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Prescaler	- clock prescaler to be set.

Returns

XST_SUCCESS if successful.
XST_DEVICE_IS_STARTED if the device is already started.
XST_DEVICE_BUSY if the device is currently transferring data. It must be stopped to re-initialize.

Note: None.

◆ XQspiPsu_SetDefaultConfig()

void XQspiPsu_SetDefaultConfig ( XQspiPsu * InstancePtr )

Enable and initialize DMA Mode, set little endain, disable poll timeout, clear prescalar bits and reset thresholds

Parameters

InstancePtr is a pointer to the XQspiPsu instance.

Returns: None.

Note: None.

◆ XQspiPsu_SetIOMode()

u32 XQspiPsu_SetIOMode	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

This function reads remaining bytes, after the completion of a DMA transfer, using IO mode

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.

Returns

XST_SUCCESS if successful.
XST_FAILURE if transfer fails.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

◆ XQspiPsu_SetOptions()

s32 XQspiPsu_SetOptions	(	XQspiPsu *	InstancePtr,
		u32	Options
	)

This function sets the options for the QSPIPSU device driver.The options control how the device behaves relative to the QSPIPSU bus. The device must be idle rather than busy transferring data before setting these device options.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Options	contains the specified options to be set. This is a bit mask where a 1 indicates the option should be turned ON and a 0 indicates no action. One or more bit values may be contained in the mask. See the bit definitions named XQSPIPSU_*_OPTIONS in the file xqspipsu.h.

Returns

XST_SUCCESS if options are successfully set.
XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting options.

Note: This function is not thread-safe.

◆ XQspiPsu_SetReadMode()

s32 XQspiPsu_SetReadMode	(	XQspiPsu *	InstancePtr,
		u32	Mode
	)

This function sets the Read mode for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Read mode options.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Mode	contains the specified Mode to be set. See the bit definitions named XQSPIPSU_READMODE_* in the file xqspipsu.h.

Returns

XST_SUCCESS if options are successfully set.
XST_DEVICE_BUSY if the device is currently transferring data. The transfer must complete or be aborted before setting Mode.

Note: This function is not thread-safe.

◆ XQspiPsu_SetStatusHandler()

void XQspiPsu_SetStatusHandler	(	XQspiPsu *	InstancePtr,
		void *	CallBackRef,
		XQspiPsu_StatusHandler	FuncPointer
	)

Sets the status callback function, the status handler, which the driver calls when it encounters conditions that should be reported to upper layer software. The handler executes in an interrupt context, so it must minimize the amount of processing performed. One of the following status events is passed to the status handler.


XST_SPI_TRANSFER_DONE       The requested data transfer is done

XST_SPI_TRANSMIT_UNDERRUN   As a slave device, the master clocked data
            but there were none available in the transmit
            register/FIFO. This typically means the slave
            application did not issue a transfer request
            fast enough, or the processor/driver could not
            fill the transmit register/FIFO fast enough.

XST_SPI_RECEIVE_OVERRUN The QSPIPSU device lost data. Data was received
            but the receive data register/FIFO was full.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
CallBackRef	is the upper layer callback reference passed back when the callback function is invoked.
FuncPointer	is the pointer to the callback function.

Returns: None.

Note

The handler is called within interrupt context, so it should do its work quickly and queue potentially time-consuming work to a task-level thread.

◆ XQspiPsu_Setup64BRxDma()

void XQspiPsu_Setup64BRxDma	(	const XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

This function sets up the RX DMA operation on a 32bit Machine For 64bit Dma transfers.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.

Returns: None

Note: None.

◆ XQspiPsu_SetupRxDma()

void XQspiPsu_SetupRxDma	(	const XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

This function sets up the RX DMA operation.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.

Returns: None

Note: None.

◆ XQspiPsu_SetWP()

void XQspiPsu_SetWP	(	const XQspiPsu *	InstancePtr,
		u8	Value
	)

This function sets the Write Protect and Hold options for the QSPIPSU device driver.The device must be idle rather than busy transferring data before setting Write Protect and Hold options.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Value	of the WP_HOLD bit in configuration register

Returns: None

Note: This function is not thread-safe. This function can only be used with single flash configuration and x1/x2 data mode. This function cannot be used with x4 data mode and dual parallel and stacked flash configuration.

◆ XQspiPsu_StartDmaTransfer()

s32 XQspiPsu_StartDmaTransfer	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32	NumMsg
	)

This function start a DMA transfer.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
NumMsg	is the number of messages to be transferred.

Returns

XST_SUCCESS if successful.
XST_FAILURE if ByteCount is greater than XQSPIPSU_DMA_BYTES_MAX.
XST_DEVICE_BUSY if a transfer is already in progress.

Note: None.

◆ XQspiPsu_TXRXSetup()

void XQspiPsu_TXRXSetup	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg,
		u32 *	GenFifoEntry
	)

This function checks the TX/RX buffers in the message and setups up the GENFIFO entries, TX FIFO or RX DMA as required.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.
GenFifoEntry	is pointer to the variable in which GENFIFO mask is returned to calling function

Returns: None

Note: None.

◆ XQspiPsu_TXSetup()

void XQspiPsu_TXSetup	(	XQspiPsu *	InstancePtr,
		XQspiPsu_Msg *	Msg
	)

This function checks the TX buffer in the message and setup the TX FIFO as required.

Parameters

InstancePtr	is a pointer to the XQspiPsu instance.
Msg	is a pointer to the structure containing transfer data.

Returns: None

Note: None.

◆ XQspiPsu_WriteProtectToggle()

void XQspiPsu_WriteProtectToggle	(	const XQspiPsu *	InstancePtr,
		u32	Toggle
	)

This API enables/ disables Write Protect pin on the flash parts.

Parameters

InstancePtr	is a pointer to the QSPIPSU driver component to use.
Toggle	is a value of the GPIO pin

Returns: None

Note: By default WP pin as per the QSPI controller is driven High which means no write protection. Calling this function once will enable the protection.

Variable Documentation

◆ XQspiPsu_ConfigTable

XQspiPsu_Config XQspiPsu_ConfigTable[XPAR_XQSPIPSU_NUM_INSTANCES]

extern

This table contains configuration information for each QSPIPSU device in the system.

Data Structures

Macros

Typedefs

Enumerations

Functions

Variables

Packet Register bit definitions and masks

Memory Address Register 1 bit definitions and masks

Memory Address Register 2 bit definitions and masks

Command Register bit definitions and masks

Program Register bit definitions and masks

Interrupt Status Enable Register bit definitions and masks

Interrupt Signal Enable Register bit definitions and masks

Interrupt Status Register bit definitions and masks

Interrupt bit definitions and masks

ID2 Register bit definitions and masks

Flash Status Register bit definitions and masks

Timing Register bit definitions and masks

ECC Register bit definitions and masks

ECC Error Count Register bit definitions and masks

ECC Spare Command Register bit definitions and masks

Data Interface Register bit definitions and masks

DMA Buffer Boundary Register bit definitions and masks

Slave DMA Configuration Register bit definitions and masks

Device Base Address

XQSPIPS Enable Register information

XQSPIPSU configuration Register information

XQSPIPSU LQSPI Register information

XQSPIPSU Interrupt Status Register information

XQSPIPSU Interrupt Enable Register information

XQSPIPSU Interrupt Disable Register information

XQSPIPSU Interrupt Mask Register information

XQSPIPSU Enable Register information

XQSPIPSU TX Data Register information

XQSPIPSU RX Data Register information

XQSPIPSU TX/RX Threshold Register information

XQSPIPSU GPIO Register information

XQSPIPSU Loopback Master Clock Delay Adjustment Register information

XQSPIPSU GEN_FIFO Register information

XQSPIPSU Select Register information

XQSPIPSU FIFO Control Register information

XQSPIPSU GENFIFO Threshold Register information

XQSPIPSU Poll configuration Register information

XQSPIPSU Transfer Status Register information

XQSPIPSU GEN_FIFO Snapshot Register information

XQSPIPSU Receive Data Copy Register information

XQSPIPSU Module Identification Register information

XQSPIPSU DMA Transfer Register information

XQSPIPSU Generic FIFO masks information

XQSPIPSU RX Data Delay Register information

TAPDLY Bypass register information

Detailed Description

Macro Definition Documentation

◆ BYTES1024_PER_PAGE

◆ BYTES256_PER_PAGE

◆ BYTES512_PER_PAGE

◆ IOU_TAPDLY_BYPASS_OFFSET

◆ IS_ONFI

◆ MAX_DELAY_CNT

◆ NUM_OF_SECTORS1024

◆ NUM_OF_SECTORS128

◆ NUM_OF_SECTORS16

◆ NUM_OF_SECTORS2

◆ NUM_OF_SECTORS2048

◆ NUM_OF_SECTORS256

◆ NUM_OF_SECTORS32

◆ NUM_OF_SECTORS4

◆ NUM_OF_SECTORS4096

◆ NUM_OF_SECTORS512

◆ NUM_OF_SECTORS64

◆ NUM_OF_SECTORS8

◆ NUM_OF_SECTORS8192

◆ ONFI_CMD_BLK_ERASE1

◆ ONFI_CMD_BLK_ERASE2

◆ ONFI_CMD_BLK_ERASE_INTRLVD2

◆ ONFI_CMD_CHNG_RD_COL1

◆ ONFI_CMD_CHNG_RD_COL2

◆ ONFI_CMD_CHNG_RD_COL_ENHCD1

◆ ONFI_CMD_CHNG_RD_COL_ENHCD2

◆ ONFI_CMD_CHNG_ROW_ADDR