RTEMS 6.1-rc2
Loading...
Searching...
No Matches
xnandpsu_onfi.h
Go to the documentation of this file.
1/******************************************************************************
2* Copyright (C) 2015 - 2022 Xilinx, Inc. All rights reserved.
3* SPDX-License-Identifier: MIT
4******************************************************************************/
5
6/*****************************************************************************/
27#ifndef XNANDPSU_ONFI_H /* prevent circular inclusions */
28#define XNANDPSU_ONFI_H /* by using protection macros */
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
34/***************************** Include Files *********************************/
35#include "xil_types.h"
36
37/************************** Constant Definitions *****************************/
38/* Standard ONFI 3.1 Commands */
39/* ONFI 3.1 Mandatory Commands */
40#define ONFI_CMD_RD1 0x00U
41#define ONFI_CMD_RD2 0x30U
42#define ONFI_CMD_CHNG_RD_COL1 0x05U
44#define ONFI_CMD_CHNG_RD_COL2 0xE0U
46#define ONFI_CMD_BLK_ERASE1 0x60U
47#define ONFI_CMD_BLK_ERASE2 0xD0U
48#define ONFI_CMD_RD_STS 0x70U
49#define ONFI_CMD_PG_PROG1 0x80U
50#define ONFI_CMD_PG_PROG2 0x10U
51#define ONFI_CMD_CHNG_WR_COL 0x85U
52#define ONFI_CMD_RD_ID 0x90U
53#define ONFI_CMD_RD_PRM_PG 0xECU
54#define ONFI_CMD_RST 0xFFU
55/* ONFI 3.1 Optional Commands */
56#define ONFI_CMD_MUL_RD1 0x00U
58#define ONFI_CMD_MUL_RD2 0x32U
60#define ONFI_CMD_CPBK_RD1 0x00U
62#define ONFI_CMD_CPBK_RD2 0x35U
64#define ONFI_CMD_CHNG_RD_COL_ENHCD1 0x06U
66#define ONFI_CMD_CHNG_RD_COL_ENHCD2 0xE0U
68#define ONFI_CMD_RD_CACHE_RND1 0x00U
70#define ONFI_CMD_RD_CACHE_RND2 0x31U
72#define ONFI_CMD_RD_CACHE_SEQ 0x31U
73#define ONFI_CMD_RD_CACHE_END 0x3FU
74#define ONFI_CMD_MUL_BLK_ERASE1 0x60U
76#define ONFI_CMD_MUL_BLK_ERASE2 0xD1U
78#define ONFI_CMD_RD_STS_ENHCD 0x78U
79#define ONFI_CMD_BLK_ERASE_INTRLVD2 0xD1U
81#define ONFI_CMD_MUL_PG_PROG1 0x80U
83#define ONFI_CMD_MUL_PG_PROG2 0x11U
85#define ONFI_CMD_PG_CACHE_PROG1 0x80U
87#define ONFI_CMD_PG_CACHE_PROG2 0x15U
89#define ONFI_CMD_CPBK_PROG1 0x85U
91#define ONFI_CMD_CPBK_PROG2 0x10U
93#define ONFI_CMD_MUL_CPBK_PROG1 0x85U
95#define ONFI_CMD_MUL_CPBK_PROG2 0x10U
97#define ONFI_CMD_SMALL_DATA_MV1 0x85U
99#define ONFI_CMD_SMALL_DATA_MV2 0x10U
101#define ONFI_CMD_CHNG_ROW_ADDR 0x85U
102#define ONFI_CMD_VOL_SEL 0xE1U
103#define ONFI_CMD_ODT_CONF 0xE2U
104#define ONFI_CMD_RD_UNIQID 0xEDU
105#define ONFI_CMD_GET_FEATURES 0xEEU
106#define ONFI_CMD_SET_FEATURES 0xEFU
107#define ONFI_CMD_LUN_GET_FEATURES 0xD4U
108#define ONFI_CMD_LUN_SET_FEATURES 0xD5U
109#define ONFI_CMD_RST_LUN 0xFAU
110#define ONFI_CMD_SYN_RST 0xFCU
112/* ONFI Status Register bit offsets */
113#define ONFI_STS_FAIL 0x01U
114#define ONFI_STS_FAILC 0x02U
115#define ONFI_STS_CSP 0x08U
116#define ONFI_STS_VSP 0x10U
117#define ONFI_STS_ARDY 0x20U
118#define ONFI_STS_RDY 0x40U
119#define ONFI_STS_WP 0x80U
121/* ONFI constants */
122#define ONFI_CRC_LEN 254U
123#define ONFI_PRM_PG_LEN 256U
124#define ONFI_MND_PRM_PGS 3U
126#define ONFI_SIG_LEN 4U
127#define ONFI_CMD_INVALID 0x00U
129#define ONFI_READ_ID_LEN 4U
130#define ONFI_READ_ID_ADDR 0x20U
131#define ONFI_READ_ID_ADDR_CYCLES 1U
134#define ONFI_PRM_PG_ADDR_CYCLES 1U
173 MAX_CMDS
175
176/**************************** Type Definitions *******************************/
177/* Parameter page structure of ONFI 3.1 specification. */
178#ifdef __ICCARM__
179#pragma pack(push, 1)
180#endif
181typedef struct {
182 /* Revision information and features block */
183 u8 Signature[4];
192 u8 Reserved1[17];
193 /* Manufacturer information block */
194 u8 DeviceManufacturer[12];
195 u8 DeviceModel[20];
197 u8 DateCode[2];
198 u8 Reserved2[13];
199 /* Memory organization block */
225 u8 Reserved3[12];
226 /* Electrical parameters block */
230 u16 TProg;
231 u16 TBers;
232 u16 TR;
233 u16 TCcs;
243 u16 TMr;
244 u16 TAdl;
246 u16 TEr;
250 u8 Reserved4[4];
251 /* Vendor block */
253 u8 VendorSpecific[88];
254 u16 Crc;
255#ifdef __ICCARM__
256} OnfiParamPage;
257#pragma pack(pop)
258#else
259}__attribute__((packed))OnfiParamPage;
260#endif
261
262/* ONFI extended parameter page structure. */
263#ifdef __ICCARM__
264#pragma pack(push, 1)
265#endif
266typedef struct {
267 u16 Crc;
268 u8 Sig[4];
269 u8 Reserved1[10];
270 u8 Section0Type;
271 u8 Section0Len;
272 u8 Section1Type;
273 u8 Section1Len;
274 u8 ResSection[12];
275 u8 SectionData[256];
276#ifdef __ICCARM__
277} OnfiExtPrmPage;
278#pragma pack(pop)
279#else
280}__attribute__((packed))OnfiExtPrmPage;
281#endif
282
283/* Driver extended parameter page information. */
284#ifdef __ICCARM__
285#pragma pack(push, 1)
286#endif
287typedef struct {
288 u8 NumEccBits;
289 u8 CodeWordSize;
290 u16 MaxBadBlocks;
291 u16 BlockEndurance;
292 u16 Reserved;
293#ifdef __ICCARM__
294} OnfiExtEccBlock;
295#pragma pack(pop)
296#else
297}__attribute__((packed))OnfiExtEccBlock;
298#endif
299
300typedef struct {
304
305extern const OnfiCmdFormat OnfiCmd[MAX_CMDS];
306
307/************************** Function Prototypes ******************************/
308
309u32 XNandPsu_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length);
310
311#ifdef __cplusplus
312}
313#endif
314
315#endif /* XNANDPSU_ONFI_H end of protection macro */
u32 XNandPsu_OnfiParamPageCrc(u8 *ParamBuf, u32 StartOff, u32 Length)
Definition: xnandpsu_onfi.c:54
OnfiCommandList
Definition: xnandpsu_onfi.h:140
@ BLOCK_ERASE
Definition: xnandpsu_onfi.h:149
@ READ_ID
Definition: xnandpsu_onfi.h:161
@ READ_STATUS_ENHANCED
Definition: xnandpsu_onfi.h:152
@ READ_PARAM_PAGE
Definition: xnandpsu_onfi.h:164
@ SYN_RESET
Definition: xnandpsu_onfi.h:171
@ VOLUME_SELECT
Definition: xnandpsu_onfi.h:162
@ SMALL_DATA_MOVE
Definition: xnandpsu_onfi.h:158
@ LUN_GET_FEATURES
Definition: xnandpsu_onfi.h:168
@ READ_STATUS
Definition: xnandpsu_onfi.h:151
@ MAX_CMDS
Definition: xnandpsu_onfi.h:173
@ SET_FEATURES
Definition: xnandpsu_onfi.h:167
@ RESET
Definition: xnandpsu_onfi.h:172
@ COPYBACK_READ
Definition: xnandpsu_onfi.h:143
@ MULTIPLANE_BLOCK_ERASE
Definition: xnandpsu_onfi.h:150
@ READ_CACHE_SEQUENTIAL
Definition: xnandpsu_onfi.h:147
@ CHANGE_ROW_ADDR
Definition: xnandpsu_onfi.h:160
@ CHANGE_WRITE_COLUMN
Definition: xnandpsu_onfi.h:159
@ COPYBACK_PROGRAM
Definition: xnandpsu_onfi.h:156
@ READ_CACHE_RANDOM
Definition: xnandpsu_onfi.h:146
@ ODT_CONFIGURE
Definition: xnandpsu_onfi.h:163
@ PAGE_CACHE_PROGRAM
Definition: xnandpsu_onfi.h:155
@ CHANGE_READ_COLUMN
Definition: xnandpsu_onfi.h:144
@ GET_FEATURES
Definition: xnandpsu_onfi.h:166
@ MULTIPLANE_PAGE_PROGRAM
Definition: xnandpsu_onfi.h:154
@ LUN_SET_FEATURES
Definition: xnandpsu_onfi.h:169
@ CHANGE_READ_COLUMN_ENHANCED
Definition: xnandpsu_onfi.h:145
@ PAGE_PROGRAM
Definition: xnandpsu_onfi.h:153
@ MULTIPLANE_READ
Definition: xnandpsu_onfi.h:142
@ READ
Definition: xnandpsu_onfi.h:141
@ READ_UNIQUE_ID
Definition: xnandpsu_onfi.h:165
@ RESET_LUN
Definition: xnandpsu_onfi.h:170
@ MULTIPLANE_COPYBACK_PROGRAM
Definition: xnandpsu_onfi.h:157
@ READ_CACHE_END
Definition: xnandpsu_onfi.h:148
Definition: xnandpsu_onfi.h:300
u8 Command1
Definition: xnandpsu_onfi.h:301
u8 Command2
Definition: xnandpsu_onfi.h:302
Definition: xnandpsu_onfi.h:181
u16 SDRPagecacheTimingMode
Definition: xnandpsu_onfi.h:229
u8 ProgramsPerPage
Definition: xnandpsu_onfi.h:217
u16 SpareBytesPerPage
Definition: xnandpsu_onfi.h:201
u8 GuaranteedValidBlock
Definition: xnandpsu_onfi.h:213
u16 OptionalCmds
Definition: xnandpsu_onfi.h:186
u16 InputPinCap
Definition: xnandpsu_onfi.h:240
u16 SDRTimingMode
Definition: xnandpsu_onfi.h:228
u32 PagesPerBlock
Definition: xnandpsu_onfi.h:206
u16 SpareBytesPerPartialPage
Definition: xnandpsu_onfi.h:204
u32 BytesPerPartialPage
Definition: xnandpsu_onfi.h:202
u8 DrvStrength
Definition: xnandpsu_onfi.h:242
u8 NVDDR2TimingMode
Definition: xnandpsu_onfi.h:236
u8 NVDDRTimingMode
Definition: xnandpsu_onfi.h:235
u8 BitsPerCell
Definition: xnandpsu_onfi.h:210
u16 Revision
Definition: xnandpsu_onfi.h:184
u16 ClkInputPinCap
Definition: xnandpsu_onfi.h:238
u8 PlaneOperationAttr
Definition: xnandpsu_onfi.h:222
u8 SynFeatures
Definition: xnandpsu_onfi.h:237
u16 ExtParamPageLen
Definition: xnandpsu_onfi.h:190
u16 Crc
Definition: xnandpsu_onfi.h:254
u8 PlaneAddrBits
Definition: xnandpsu_onfi.h:221
u16 BlockEnduranceGVB
Definition: xnandpsu_onfi.h:215
u16 TR
Definition: xnandpsu_onfi.h:232
u16 VendorRevisionNum
Definition: xnandpsu_onfi.h:252
u8 PartialProgAttr
Definition: xnandpsu_onfi.h:218
u8 NumLuns
Definition: xnandpsu_onfi.h:208
u16 MaxBadBlocksPerLun
Definition: xnandpsu_onfi.h:211
u8 IOPinCapacitance
Definition: xnandpsu_onfi.h:227
u8 JedecManufacturerId
Definition: xnandpsu_onfi.h:196
u16 TCcs
Definition: xnandpsu_onfi.h:233
u16 IOPinCap
Definition: xnandpsu_onfi.h:239
u8 NVDDR2Features
Definition: xnandpsu_onfi.h:248
u16 TEr
Definition: xnandpsu_onfi.h:246
u16 BlockEndurance
Definition: xnandpsu_onfi.h:212
u8 InputPinCapMax
Definition: xnandpsu_onfi.h:241
u8 Reserved0
Definition: xnandpsu_onfi.h:189
u8 EzNandSupport
Definition: xnandpsu_onfi.h:224
u16 TMr
Definition: xnandpsu_onfi.h:243
u8 NumOfParamPages
Definition: xnandpsu_onfi.h:191
u8 NVDDR2WarmupCycles
Definition: xnandpsu_onfi.h:249
u8 AddrCycles
Definition: xnandpsu_onfi.h:209
u8 JedecJtgPrmAdvCmd
Definition: xnandpsu_onfi.h:187
u8 EccBits
Definition: xnandpsu_onfi.h:219
u16 TAdl
Definition: xnandpsu_onfi.h:244
u16 TProg
Definition: xnandpsu_onfi.h:230
u32 BytesPerPage
Definition: xnandpsu_onfi.h:200
u16 TBers
Definition: xnandpsu_onfi.h:231
u16 Features
Definition: xnandpsu_onfi.h:185
u32 BlocksPerLun
Definition: xnandpsu_onfi.h:207