uartlite_l.h

/******************************************************************************
* Copyright (C) 2002 - 2020 Xilinx, Inc.  All rights reserved.
* SPDX-License-Identifier: MIT
******************************************************************************/
 
/****************************************************************************/
#ifndef XUARTLITE_L_H /* prevent circular inclusions */
#define XUARTLITE_L_H /* by using protection macros */
 
#ifdef __cplusplus
extern "C" {
#endif
 
/***************************** Include Files ********************************/
 
#ifndef __rtems__
#include "xil_types.h"
#include "xil_assert.h"
#include "xil_io.h"
#else
#include <common/xil_types.h>
static inline u32 Xil_In32(UINTPTR Addr)
{
    return *(volatile u32 *) Addr;
}
static inline void Xil_Out32(UINTPTR Addr, u32 Value)
{
    volatile u32 *LocalAddr = (volatile u32 *)Addr;
    *LocalAddr = Value;
}
#endif /* __rtems__ */
 
/*
 * XPAR_XUARTLITE_USE_DCR_BRIDGE has to be set to 1 if the UartLite device is
 * accessed through a DCR bus connected to a bridge.
 */
#define XPAR_XUARTLITE_USE_DCR_BRIDGE 0
 
#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0)
#include "xio_dcr.h"
#endif
 
 
/************************** Constant Definitions ****************************/
 
/* UART Lite register offsets */
 
#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0)
#define XUL_RX_FIFO_OFFSET      0   /* receive FIFO, read only */
#define XUL_TX_FIFO_OFFSET      1   /* transmit FIFO, write only */
#define XUL_STATUS_REG_OFFSET       2   /* status register, read only */
#define XUL_CONTROL_REG_OFFSET      3   /* control reg, write only */
 
#else
 
#define XUL_RX_FIFO_OFFSET      0   /* receive FIFO, read only */
#define XUL_TX_FIFO_OFFSET      4   /* transmit FIFO, write only */
#define XUL_STATUS_REG_OFFSET       8   /* status register, read only */
#define XUL_CONTROL_REG_OFFSET      12  /* control reg, write only */
 
#endif
 
/* Control Register bit positions */
 
#define XUL_CR_ENABLE_INTR      0x10    /* enable interrupt */
#define XUL_CR_FIFO_RX_RESET        0x02    /* reset receive FIFO */
#define XUL_CR_FIFO_TX_RESET        0x01    /* reset transmit FIFO */
 
/* Status Register bit positions */
 
#define XUL_SR_PARITY_ERROR     0x80
#define XUL_SR_FRAMING_ERROR        0x40
#define XUL_SR_OVERRUN_ERROR        0x20
#define XUL_SR_INTR_ENABLED     0x10    /* interrupt enabled */
#define XUL_SR_TX_FIFO_FULL     0x08    /* transmit FIFO full */
#define XUL_SR_TX_FIFO_EMPTY        0x04    /* transmit FIFO empty */
#define XUL_SR_RX_FIFO_FULL     0x02    /* receive FIFO full */
#define XUL_SR_RX_FIFO_VALID_DATA   0x01    /* data in receive FIFO */
 
/* The following constant specifies the size of the Transmit/Receive FIFOs.
 * The FIFO size is fixed to 16 in the Uartlite IP and the size is not
 * configurable. This constant is not used in the driver.
 */
#define XUL_FIFO_SIZE           16
 
/* Stop bits are fixed at 1. Baud, parity, and data bits are fixed on a
 * per instance basis
 */
#define XUL_STOP_BITS           1
 
/* Parity definitions
 */
#define XUL_PARITY_NONE         0
#define XUL_PARITY_ODD          1
#define XUL_PARITY_EVEN         2
 
/**************************** Type Definitions ******************************/
 
/***************** Macros (Inline Functions) Definitions ********************/
 
/*
 * Define the appropriate I/O access method to memory mapped I/O or DCR.
 */
#if (XPAR_XUARTLITE_USE_DCR_BRIDGE != 0)
 
#define XUartLite_In32  XIo_DcrIn
#define XUartLite_Out32 XIo_DcrOut
 
#else
 
#define XUartLite_In32  Xil_In32
#define XUartLite_Out32 Xil_Out32
 
#endif
 
 
/****************************************************************************/
#define XUartLite_WriteReg(BaseAddress, RegOffset, Data) \
    XUartLite_Out32((BaseAddress) + (RegOffset), (u32)(Data))
 
/****************************************************************************/
#define XUartLite_ReadReg(BaseAddress, RegOffset) \
    XUartLite_In32((BaseAddress) + (RegOffset))
 
 
/****************************************************************************/
#define XUartLite_SetControlReg(BaseAddress, Mask) \
    XUartLite_WriteReg((BaseAddress), XUL_CONTROL_REG_OFFSET, (Mask))
 
 
/****************************************************************************/
#define XUartLite_GetStatusReg(BaseAddress) \
        XUartLite_ReadReg((BaseAddress), XUL_STATUS_REG_OFFSET)
 
 
/****************************************************************************/
#define XUartLite_IsReceiveEmpty(BaseAddress) \
  ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_RX_FIFO_VALID_DATA) != \
    XUL_SR_RX_FIFO_VALID_DATA)
 
#ifdef __rtems__
/****************************************************************************/
#define XUartLite_IsTransmitEmpty(BaseAddress) \
  ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_EMPTY) == \
    XUL_SR_TX_FIFO_EMPTY)
#endif /* __rtems__ */
 
/****************************************************************************/
#define XUartLite_IsTransmitFull(BaseAddress) \
    ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_TX_FIFO_FULL) == \
      XUL_SR_TX_FIFO_FULL)
 
 
/****************************************************************************/
#define XUartLite_IsIntrEnabled(BaseAddress) \
    ((XUartLite_GetStatusReg((BaseAddress)) & XUL_SR_INTR_ENABLED) == \
      XUL_SR_INTR_ENABLED)
 
 
/****************************************************************************/
#define XUartLite_EnableIntr(BaseAddress) \
        XUartLite_SetControlReg((BaseAddress), XUL_CR_ENABLE_INTR)
 
 
/****************************************************************************/
#define XUartLite_DisableIntr(BaseAddress) \
        XUartLite_SetControlReg((BaseAddress), 0)
 
/************************** Function Prototypes *****************************/
 
void XUartLite_SendByte(UINTPTR BaseAddress, u8 Data);
u8 XUartLite_RecvByte(UINTPTR BaseAddress);
 
#ifdef __cplusplus
}
#endif
 
#endif /* end of protection macro */