Header file of RCC HAL module. More...

#include "stm32h7xx_hal_def.h"
#include "stm32h7xx_hal_rcc_ex.h"

Data Structures
struct	RCC_PLLInitTypeDef
	RCC PLL configuration structure definition. More...

struct	RCC_OscInitTypeDef
	RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition. More...

struct	RCC_ClkInitTypeDef
	RCC System, AHB and APB busses clock configuration structure definition. More...

Macros
#define	RCC_OSCILLATORTYPE_NONE (0x00000000U)

#define	RCC_OSCILLATORTYPE_HSE (0x00000001U)

#define	RCC_OSCILLATORTYPE_HSI (0x00000002U)

#define	RCC_OSCILLATORTYPE_LSE (0x00000004U)

#define	RCC_OSCILLATORTYPE_LSI (0x00000008U)

#define	RCC_OSCILLATORTYPE_CSI (0x00000010U)

#define	RCC_OSCILLATORTYPE_HSI48 (0x00000020U)

#define	RCC_HSE_OFF (0x00000000U)

#define	RCC_HSE_ON RCC_CR_HSEON

#define	RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP \| RCC_CR_HSEON))

#define	RCC_LSE_OFF (0x00000000U)

#define	RCC_LSE_ON RCC_BDCR_LSEON

#define	RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP \| RCC_BDCR_LSEON))

#define	RCC_HSI_OFF (0x00000000U)

#define	RCC_HSI_ON RCC_CR_HSION

#define	RCC_HSI_DIV1 (RCC_CR_HSIDIV_1 \| RCC_CR_HSION)

#define	RCC_HSI_DIV2 (RCC_CR_HSIDIV_2 \| RCC_CR_HSION)

#define	RCC_HSI_DIV4 (RCC_CR_HSIDIV_4 \| RCC_CR_HSION)

#define	RCC_HSI_DIV8 (RCC_CR_HSIDIV \| RCC_CR_HSION)

#define	RCC_HSICALIBRATION_DEFAULT (0x40U) /* Default HSI calibration trimming value for STM32H7 rev.V and above. (0x20 value for rev.Y handled within __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST macro ) */

#define	RCC_HSI48_OFF ((uint8_t)0x00)

#define	RCC_HSI48_ON ((uint8_t)0x01)

#define	RCC_LSI_OFF (0x00000000U)

#define	RCC_LSI_ON RCC_CSR_LSION

#define	RCC_CSI_OFF (0x00000000U)

#define	RCC_CSI_ON RCC_CR_CSION

#define	RCC_CSICALIBRATION_DEFAULT (0x20U) /* Default CSI calibration trimming value for STM32H7 rev.V and above. (0x10 value for rev.Y handled within __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST macro ) */

#define	RCC_PLL_NONE (0x00000000U)

#define	RCC_PLL_OFF (0x00000001U)

#define	RCC_PLL_ON (0x00000002U)

#define	RCC_PLLSOURCE_HSI (0x00000000U)

#define	RCC_PLLSOURCE_CSI (0x00000001U)

#define	RCC_PLLSOURCE_HSE (0x00000002U)

#define	RCC_PLLSOURCE_NONE (0x00000003U)

#define	RCC_PLL1_DIVP RCC_PLLCFGR_DIVP1EN

#define	RCC_PLL1_DIVQ RCC_PLLCFGR_DIVQ1EN

#define	RCC_PLL1_DIVR RCC_PLLCFGR_DIVR1EN

#define	RCC_PLL1VCIRANGE_0 RCC_PLLCFGR_PLL1RGE_0

#define	RCC_PLL1VCIRANGE_1 RCC_PLLCFGR_PLL1RGE_1

#define	RCC_PLL1VCIRANGE_2 RCC_PLLCFGR_PLL1RGE_2

#define	RCC_PLL1VCIRANGE_3 RCC_PLLCFGR_PLL1RGE_3

#define	RCC_PLL1VCOWIDE (0x00000000U)

#define	RCC_PLL1VCOMEDIUM RCC_PLLCFGR_PLL1VCOSEL

#define	RCC_CLOCKTYPE_SYSCLK (0x00000001U)

#define	RCC_CLOCKTYPE_HCLK (0x00000002U)

#define	RCC_CLOCKTYPE_D1PCLK1 (0x00000004U)

#define	RCC_CLOCKTYPE_PCLK1 (0x00000008U)

#define	RCC_CLOCKTYPE_PCLK2 (0x00000010U)

#define	RCC_CLOCKTYPE_D3PCLK1 (0x00000020U)

#define	RCC_SYSCLKSOURCE_CSI RCC_CFGR_SW_CSI

#define	RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI

#define	RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE

#define	RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL1

#define	RCC_SYSCLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI

#define	RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI

#define	RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE

#define	RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1

#define	RCC_SYSCLK_DIV1 RCC_CDCFGR1_CDCPRE_DIV1

#define	RCC_SYSCLK_DIV2 RCC_CDCFGR1_CDCPRE_DIV2

#define	RCC_SYSCLK_DIV4 RCC_CDCFGR1_CDCPRE_DIV4

#define	RCC_SYSCLK_DIV8 RCC_CDCFGR1_CDCPRE_DIV8

#define	RCC_SYSCLK_DIV16 RCC_CDCFGR1_CDCPRE_DIV16

#define	RCC_SYSCLK_DIV64 RCC_CDCFGR1_CDCPRE_DIV64

#define	RCC_SYSCLK_DIV128 RCC_CDCFGR1_CDCPRE_DIV128

#define	RCC_SYSCLK_DIV256 RCC_CDCFGR1_CDCPRE_DIV256

#define	RCC_SYSCLK_DIV512 RCC_CDCFGR1_CDCPRE_DIV512

#define	RCC_HCLK_DIV1 RCC_CDCFGR1_HPRE_DIV1

#define	RCC_HCLK_DIV2 RCC_CDCFGR1_HPRE_DIV2

#define	RCC_HCLK_DIV4 RCC_CDCFGR1_HPRE_DIV4

#define	RCC_HCLK_DIV8 RCC_CDCFGR1_HPRE_DIV8

#define	RCC_HCLK_DIV16 RCC_CDCFGR1_HPRE_DIV16

#define	RCC_HCLK_DIV64 RCC_CDCFGR1_HPRE_DIV64

#define	RCC_HCLK_DIV128 RCC_CDCFGR1_HPRE_DIV128

#define	RCC_HCLK_DIV256 RCC_CDCFGR1_HPRE_DIV256

#define	RCC_HCLK_DIV512 RCC_CDCFGR1_HPRE_DIV512

#define	RCC_APB3_DIV1 RCC_CDCFGR1_CDPPRE_DIV1

#define	RCC_APB3_DIV2 RCC_CDCFGR1_CDPPRE_DIV2

#define	RCC_APB3_DIV4 RCC_CDCFGR1_CDPPRE_DIV4

#define	RCC_APB3_DIV8 RCC_CDCFGR1_CDPPRE_DIV8

#define	RCC_APB3_DIV16 RCC_CDCFGR1_CDPPRE_DIV16

#define	RCC_APB1_DIV1 RCC_CDCFGR2_CDPPRE1_DIV1

#define	RCC_APB1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2

#define	RCC_APB1_DIV4 RCC_CDCFGR2_CDPPRE1_DIV4

#define	RCC_APB1_DIV8 RCC_CDCFGR2_CDPPRE1_DIV8

#define	RCC_APB1_DIV16 RCC_CDCFGR2_CDPPRE1_DIV16

#define	RCC_APB2_DIV1 RCC_CDCFGR2_CDPPRE2_DIV1

#define	RCC_APB2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2

#define	RCC_APB2_DIV4 RCC_CDCFGR2_CDPPRE2_DIV4

#define	RCC_APB2_DIV8 RCC_CDCFGR2_CDPPRE2_DIV8

#define	RCC_APB2_DIV16 RCC_CDCFGR2_CDPPRE2_DIV16

#define	RCC_APB4_DIV1 RCC_SRDCFGR_SRDPPRE_DIV1

#define	RCC_APB4_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2

#define	RCC_APB4_DIV4 RCC_SRDCFGR_SRDPPRE_DIV4

#define	RCC_APB4_DIV8 RCC_SRDCFGR_SRDPPRE_DIV8

#define	RCC_APB4_DIV16 RCC_SRDCFGR_SRDPPRE_DIV16

#define	RCC_RTCCLKSOURCE_NO_CLK (0x00000000U)

#define	RCC_RTCCLKSOURCE_LSE (0x00000100U)

#define	RCC_RTCCLKSOURCE_LSI (0x00000200U)

#define	RCC_RTCCLKSOURCE_HSE_DIV2 (0x00002300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV3 (0x00003300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV4 (0x00004300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV5 (0x00005300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV6 (0x00006300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV7 (0x00007300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV8 (0x00008300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV9 (0x00009300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV10 (0x0000A300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV11 (0x0000B300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV12 (0x0000C300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV13 (0x0000D300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV14 (0x0000E300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV15 (0x0000F300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV16 (0x00010300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV17 (0x00011300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV18 (0x00012300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV19 (0x00013300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV20 (0x00014300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV21 (0x00015300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV22 (0x00016300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV23 (0x00017300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV24 (0x00018300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV25 (0x00019300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV26 (0x0001A300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV27 (0x0001B300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV28 (0x0001C300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV29 (0x0001D300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV30 (0x0001E300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV31 (0x0001F300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV32 (0x00020300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV33 (0x00021300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV34 (0x00022300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV35 (0x00023300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV36 (0x00024300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV37 (0x00025300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV38 (0x00026300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV39 (0x00027300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV40 (0x00028300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV41 (0x00029300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV42 (0x0002A300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV43 (0x0002B300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV44 (0x0002C300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV45 (0x0002D300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV46 (0x0002E300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV47 (0x0002F300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV48 (0x00030300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV49 (0x00031300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV50 (0x00032300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV51 (0x00033300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV52 (0x00034300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV53 (0x00035300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV54 (0x00036300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV55 (0x00037300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV56 (0x00038300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV57 (0x00039300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV58 (0x0003A300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV59 (0x0003B300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV60 (0x0003C300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV61 (0x0003D300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV62 (0x0003E300U)

#define	RCC_RTCCLKSOURCE_HSE_DIV63 (0x0003F300U)

#define	RCC_MCO1 (0x00000000U)

#define	RCC_MCO2 (0x00000001U)

#define	RCC_MCO1SOURCE_HSI (0x00000000U)

#define	RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0

#define	RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1

#define	RCC_MCO1SOURCE_PLL1QCLK ((uint32_t)RCC_CFGR_MCO1_0 \| RCC_CFGR_MCO1_1)

#define	RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCO1_2

#define	RCC_MCO2SOURCE_SYSCLK (0x00000000U)

#define	RCC_MCO2SOURCE_PLL2PCLK RCC_CFGR_MCO2_0

#define	RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1

#define	RCC_MCO2SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO2_0 \| RCC_CFGR_MCO2_1)

#define	RCC_MCO2SOURCE_CSICLK RCC_CFGR_MCO2_2

#define	RCC_MCO2SOURCE_LSICLK ((uint32_t)RCC_CFGR_MCO2_0 \| RCC_CFGR_MCO2_2)

#define	RCC_MCODIV_1 RCC_CFGR_MCO1PRE_0

#define	RCC_MCODIV_2 RCC_CFGR_MCO1PRE_1

#define	RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_1)

#define	RCC_MCODIV_4 RCC_CFGR_MCO1PRE_2

#define	RCC_MCODIV_5 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)

#define	RCC_MCODIV_6 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)

#define	RCC_MCODIV_7 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)

#define	RCC_MCODIV_8 RCC_CFGR_MCO1PRE_3

#define	RCC_MCODIV_9 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_3)

#define	RCC_MCODIV_10 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_3)

#define	RCC_MCODIV_11 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_3)

#define	RCC_MCODIV_12 ((uint32_t)RCC_CFGR_MCO1PRE_2 \| RCC_CFGR_MCO1PRE_3)

#define	RCC_MCODIV_13 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2 \| RCC_CFGR_MCO1PRE_3)

#define	RCC_MCODIV_14 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2 \| RCC_CFGR_MCO1PRE_3)

#define	RCC_MCODIV_15 RCC_CFGR_MCO1PRE

#define	RCC_IT_LSIRDY (0x00000001U)

#define	RCC_IT_LSERDY (0x00000002U)

#define	RCC_IT_HSIRDY (0x00000004U)

#define	RCC_IT_HSERDY (0x00000008U)

#define	RCC_IT_CSIRDY (0x00000010U)

#define	RCC_IT_HSI48RDY (0x00000020U)

#define	RCC_IT_PLLRDY (0x00000040U)

#define	RCC_IT_PLL2RDY (0x00000080U)

#define	RCC_IT_PLL3RDY (0x00000100U)

#define	RCC_IT_LSECSS (0x00000200U)

#define	RCC_IT_CSS (0x00000400U)

#define	RCC_FLAG_HSIRDY ((uint8_t)0x22)

#define	RCC_FLAG_HSIDIV ((uint8_t)0x25)

#define	RCC_FLAG_CSIRDY ((uint8_t)0x28)

#define	RCC_FLAG_HSI48RDY ((uint8_t)0x2D)

#define	RCC_FLAG_CPUCKRDY ((uint8_t)0x2E)

#define	RCC_FLAG_D1CKRDY RCC_FLAG_CPUCKRDY /* alias */

#define	RCC_FLAG_CDCKRDY ((uint8_t)0x2F)

#define	RCC_FLAG_D2CKRDY RCC_FLAG_CDCKRDY /* alias */

#define	RCC_FLAG_HSERDY ((uint8_t)0x31)

#define	RCC_FLAG_PLLRDY ((uint8_t)0x39)

#define	RCC_FLAG_PLL2RDY ((uint8_t)0x3B)

#define	RCC_FLAG_PLL3RDY ((uint8_t)0x3D)

#define	RCC_FLAG_LSERDY ((uint8_t)0x41)

#define	RCC_FLAG_LSIRDY ((uint8_t)0x61)

#define	RCC_FLAG_CDRST ((uint8_t)0x93)

#define	RCC_FLAG_BORRST ((uint8_t)0x95)

#define	RCC_FLAG_PINRST ((uint8_t)0x96)

#define	RCC_FLAG_PORRST ((uint8_t)0x97)

#define	RCC_FLAG_SFTRST ((uint8_t)0x98)

#define	RCC_FLAG_IWDG1RST ((uint8_t)0x9A)

#define	RCC_FLAG_WWDG1RST ((uint8_t)0x9C)

#define	RCC_FLAG_LPWR1RST ((uint8_t)0x9E)

#define	RCC_FLAG_LPWR2RST ((uint8_t)0x9F)

#define	RCC_LSEDRIVE_LOW (0x00000000U)

#define	RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0

#define	RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1

#define	RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV

#define	RCC_STOP_WAKEUPCLOCK_HSI (0x00000000U)

#define	RCC_STOP_WAKEUPCLOCK_CSI RCC_CFGR_STOPWUCK

#define	RCC_STOP_KERWAKEUPCLOCK_HSI (0x00000000U)

#define	RCC_STOP_KERWAKEUPCLOCK_CSI RCC_CFGR_STOPKERWUCK

#define	__HAL_RCC_MDMA_CLK_ENABLE()
	Enable or disable the AHB3 peripheral clock.

#define	__HAL_RCC_DMA2D_CLK_ENABLE()

#define	__HAL_RCC_FMC_CLK_ENABLE()

#define	__HAL_RCC_SDMMC1_CLK_ENABLE()

#define	__HAL_RCC_MDMA_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))

#define	__HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))

#define	__HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))

#define	__HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))

#define	__HAL_RCC_MDMA_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) != 0U)
	Get the enable or disable status of the AHB3 peripheral clock.

#define	__HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) != 0U)

#define	__HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) != 0U)

#define	__HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)

#define	__HAL_RCC_MDMA_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN) == 0U)

#define	__HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN) == 0U)

#define	__HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN) == 0U)

#define	__HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)

#define	__HAL_RCC_DMA1_CLK_ENABLE()
	Enable or disable the AHB1 peripheral clock.

#define	__HAL_RCC_DMA2_CLK_ENABLE()

#define	__HAL_RCC_ADC12_CLK_ENABLE()

#define	__HAL_RCC_USB1_OTG_HS_CLK_ENABLE()

#define	__HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()

#define	__HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))

#define	__HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))

#define	__HAL_RCC_ADC12_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))

#define	__HAL_RCC_USB1_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))

#define	__HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))

#define	__HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) != 0U)
	Get the enable or disable status of the AHB1 peripheral clock.

#define	__HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) != 0U)

#define	__HAL_RCC_ADC12_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) != 0U)

#define	__HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) != 0U)

#define	__HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)

#define	__HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN) == 0U)

#define	__HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN) == 0U)

#define	__HAL_RCC_ADC12_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN) == 0U)

#define	__HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN) == 0U)

#define	__HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)

#define	__HAL_RCC_DCMI_CLK_ENABLE()
	Enable or disable the AHB2 peripheral clock.

#define	__HAL_RCC_RNG_CLK_ENABLE()

#define	__HAL_RCC_SDMMC2_CLK_ENABLE()

#define	__HAL_RCC_AHBSRAM1_CLK_ENABLE()

#define	__HAL_RCC_AHBSRAM2_CLK_ENABLE()

#define	__HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))

#define	__HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))

#define	__HAL_RCC_SDMMC2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))

#define	__HAL_RCC_AHBSRAM1_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN))

#define	__HAL_RCC_AHBSRAM2_CLK_DISABLE() (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN))

#define	__HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) != 0U)
	Get the enable or disable status of the AHB2 peripheral clock.

#define	__HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) != 0U)

#define	__HAL_RCC_SDMMC2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) != 0U)

#define	__HAL_RCC_AHBSRAM1_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U)

#define	__HAL_RCC_AHBSRAM2_IS_CLK_ENABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U)

#define	__HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN) == 0U)

#define	__HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN) == 0U)

#define	__HAL_RCC_SDMMC2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN) == 0U)

#define	__HAL_RCC_AHBSRAM1_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U)

#define	__HAL_RCC_AHBSRAM2_IS_CLK_DISABLED() ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U)

#define	__HAL_RCC_GPIOA_CLK_ENABLE()
	Enable or disable the AHB4 peripheral clock.

#define	__HAL_RCC_GPIOB_CLK_ENABLE()

#define	__HAL_RCC_GPIOC_CLK_ENABLE()

#define	__HAL_RCC_GPIOD_CLK_ENABLE()

#define	__HAL_RCC_GPIOE_CLK_ENABLE()

#define	__HAL_RCC_GPIOF_CLK_ENABLE()

#define	__HAL_RCC_GPIOG_CLK_ENABLE()

#define	__HAL_RCC_GPIOH_CLK_ENABLE()

#define	__HAL_RCC_GPIOJ_CLK_ENABLE()

#define	__HAL_RCC_GPIOK_CLK_ENABLE()

#define	__HAL_RCC_BDMA_CLK_ENABLE()

#define	__HAL_RCC_BKPRAM_CLK_ENABLE()

#define	__HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)

#define	__HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)

#define	__HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)

#define	__HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)

#define	__HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)

#define	__HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)

#define	__HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)

#define	__HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)

#define	__HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)

#define	__HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)

#define	__HAL_RCC_BDMA_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)

#define	__HAL_RCC_BKPRAM_CLK_DISABLE() (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)

#define	__HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) != 0U)
	Get the enable or disable status of the AHB4 peripheral clock.

#define	__HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) != 0U)

#define	__HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) != 0U)

#define	__HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) != 0U)

#define	__HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) != 0U)

#define	__HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) != 0U)

#define	__HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) != 0U)

#define	__HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) != 0U)

#define	__HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) != 0U)

#define	__HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) != 0U)

#define	__HAL_RCC_BDMA_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) != 0U)

#define	__HAL_RCC_BKPRAM_IS_CLK_ENABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)

#define	__HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN) == 0U)

#define	__HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN) == 0U)

#define	__HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN) == 0U)

#define	__HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN) == 0U)

#define	__HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN) == 0U)

#define	__HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN) == 0U)

#define	__HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN) == 0U)

#define	__HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN) == 0U)

#define	__HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN) == 0U)

#define	__HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN) == 0U)

#define	__HAL_RCC_BDMA_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN) == 0U)

#define	__HAL_RCC_BKPRAM_IS_CLK_DISABLED() ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)

#define	__HAL_RCC_WWDG1_CLK_ENABLE()
	Enable or disable the APB3 peripheral clock.

#define	__HAL_RCC_WWDG1_CLK_DISABLE() (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)

#define	__HAL_RCC_WWDG1_IS_CLK_ENABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)
	Get the enable or disable status of the APB3 peripheral clock.

#define	__HAL_RCC_WWDG1_IS_CLK_DISABLED() ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)

#define	__HAL_RCC_TIM2_CLK_ENABLE()
	Enable or disable the APB1 peripheral clock.

#define	__HAL_RCC_TIM3_CLK_ENABLE()

#define	__HAL_RCC_TIM4_CLK_ENABLE()

#define	__HAL_RCC_TIM5_CLK_ENABLE()

#define	__HAL_RCC_TIM6_CLK_ENABLE()

#define	__HAL_RCC_TIM7_CLK_ENABLE()

#define	__HAL_RCC_TIM12_CLK_ENABLE()

#define	__HAL_RCC_TIM13_CLK_ENABLE()

#define	__HAL_RCC_TIM14_CLK_ENABLE()

#define	__HAL_RCC_LPTIM1_CLK_ENABLE()

#define	__HAL_RCC_SPI2_CLK_ENABLE()

#define	__HAL_RCC_SPI3_CLK_ENABLE()

#define	__HAL_RCC_SPDIFRX_CLK_ENABLE()

#define	__HAL_RCC_USART2_CLK_ENABLE()

#define	__HAL_RCC_USART3_CLK_ENABLE()

#define	__HAL_RCC_UART4_CLK_ENABLE()

#define	__HAL_RCC_UART5_CLK_ENABLE()

#define	__HAL_RCC_I2C1_CLK_ENABLE()

#define	__HAL_RCC_I2C2_CLK_ENABLE()

#define	__HAL_RCC_I2C3_CLK_ENABLE()

#define	__HAL_RCC_CEC_CLK_ENABLE()

#define	__HAL_RCC_DAC12_CLK_ENABLE()

#define	__HAL_RCC_UART7_CLK_ENABLE()

#define	__HAL_RCC_UART8_CLK_ENABLE()

#define	__HAL_RCC_CRS_CLK_ENABLE()

#define	__HAL_RCC_SWPMI1_CLK_ENABLE()

#define	__HAL_RCC_OPAMP_CLK_ENABLE()

#define	__HAL_RCC_MDIOS_CLK_ENABLE()

#define	__HAL_RCC_FDCAN_CLK_ENABLE()

#define	__HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)

#define	__HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)

#define	__HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)

#define	__HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)

#define	__HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)

#define	__HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)

#define	__HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)

#define	__HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)

#define	__HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)

#define	__HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)

#define	__HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)

#define	__HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)

#define	__HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)

#define	__HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)

#define	__HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)

#define	__HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)

#define	__HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)

#define	__HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)

#define	__HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)

#define	__HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)

#define	__HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)

#define	__HAL_RCC_DAC12_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)

#define	__HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)

#define	__HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)

#define	__HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)

#define	__HAL_RCC_SWPMI1_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)

#define	__HAL_RCC_OPAMP_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)

#define	__HAL_RCC_MDIOS_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)

#define	__HAL_RCC_FDCAN_CLK_DISABLE() (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)

#define	__HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) != 0U)
	Get the enable or disable status of the APB1 peripheral clock.

#define	__HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) != 0U)

#define	__HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) != 0U)

#define	__HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) != 0U)

#define	__HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) != 0U)

#define	__HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) != 0U)

#define	__HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) != 0U)

#define	__HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) != 0U)

#define	__HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) != 0U)

#define	__HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) != 0U)

#define	__HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) != 0U)

#define	__HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) != 0U)

#define	__HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)

#define	__HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) != 0U)

#define	__HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) != 0U)

#define	__HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) != 0U)

#define	__HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) != 0U)

#define	__HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) != 0U)

#define	__HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) != 0U)

#define	__HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) != 0U)

#define	__HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) != 0U)

#define	__HAL_RCC_DAC12_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) != 0U)

#define	__HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) != 0U)

#define	__HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) != 0U)

#define	__HAL_RCC_CRS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) != 0U)

#define	__HAL_RCC_SWPMI1_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) != 0U)

#define	__HAL_RCC_OPAMP_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) != 0U)

#define	__HAL_RCC_MDIOS_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) != 0U)

#define	__HAL_RCC_FDCAN_IS_CLK_ENABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) != 0U)

#define	__HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN) == 0U)

#define	__HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN) == 0U)

#define	__HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN) == 0U)

#define	__HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN) == 0U)

#define	__HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN) == 0U)

#define	__HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN) == 0U)

#define	__HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN) == 0U)

#define	__HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN) == 0U)

#define	__HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN) == 0U)

#define	__HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN) == 0U)

#define	__HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN) == 0U)

#define	__HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN) == 0U)

#define	__HAL_RCC_SPDIFRX_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)

#define	__HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART2EN) == 0U)

#define	__HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_USART3EN) == 0U)

#define	__HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART4EN) == 0U)

#define	__HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART5EN) == 0U)

#define	__HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN) == 0U)

#define	__HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN) == 0U)

#define	__HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN) == 0U)

#define	__HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_CECEN) == 0U)

#define	__HAL_RCC_DAC12_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN) == 0U)

#define	__HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART7EN) == 0U)

#define	__HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1LENR & RCC_APB1LENR_UART8EN) == 0U)

#define	__HAL_RCC_CRS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_CRSEN) == 0U)

#define	__HAL_RCC_SWPMI1_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN) == 0U)

#define	__HAL_RCC_OPAMP_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN) == 0U)

#define	__HAL_RCC_MDIOS_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN) == 0U)

#define	__HAL_RCC_FDCAN_IS_CLK_DISABLED() ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN) == 0U)

#define	__HAL_RCC_TIM1_CLK_ENABLE()
	Enable or disable the APB2 peripheral clock.

#define	__HAL_RCC_TIM8_CLK_ENABLE()

#define	__HAL_RCC_USART1_CLK_ENABLE()

#define	__HAL_RCC_USART6_CLK_ENABLE()

#define	__HAL_RCC_SPI1_CLK_ENABLE()

#define	__HAL_RCC_SPI4_CLK_ENABLE()

#define	__HAL_RCC_TIM15_CLK_ENABLE()

#define	__HAL_RCC_TIM16_CLK_ENABLE()

#define	__HAL_RCC_TIM17_CLK_ENABLE()

#define	__HAL_RCC_SPI5_CLK_ENABLE()

#define	__HAL_RCC_SAI1_CLK_ENABLE()

#define	__HAL_RCC_DFSDM1_CLK_ENABLE()

#define	__HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)

#define	__HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)

#define	__HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)

#define	__HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)

#define	__HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)

#define	__HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)

#define	__HAL_RCC_TIM15_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)

#define	__HAL_RCC_TIM16_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)

#define	__HAL_RCC_TIM17_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)

#define	__HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)

#define	__HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)

#define	__HAL_RCC_DFSDM1_CLK_DISABLE() (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)

#define	__HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) != 0U)
	Get the enable or disable status of the APB2 peripheral clock.

#define	__HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) != 0U)

#define	__HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)

#define	__HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)

#define	__HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) != 0U)

#define	__HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) != 0U)

#define	__HAL_RCC_TIM15_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) != 0U)

#define	__HAL_RCC_TIM16_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) != 0U)

#define	__HAL_RCC_TIM17_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) != 0U)

#define	__HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) != 0U)

#define	__HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) != 0U)

#define	__HAL_RCC_DFSDM1_IS_CLK_ENABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)

#define	__HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN) == 0U)

#define	__HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN) == 0U)

#define	__HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)

#define	__HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)

#define	__HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN) == 0U)

#define	__HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN) == 0U)

#define	__HAL_RCC_TIM15_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN) == 0U)

#define	__HAL_RCC_TIM16_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN) == 0U)

#define	__HAL_RCC_TIM17_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN) == 0U)

#define	__HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN) == 0U)

#define	__HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN) == 0U)

#define	__HAL_RCC_DFSDM1_IS_CLK_DISABLED() ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)

#define	__HAL_RCC_SYSCFG_CLK_ENABLE()
	Enable or disable the APB4 peripheral clock.

#define	__HAL_RCC_LPUART1_CLK_ENABLE()

#define	__HAL_RCC_SPI6_CLK_ENABLE()

#define	__HAL_RCC_I2C4_CLK_ENABLE()

#define	__HAL_RCC_LPTIM2_CLK_ENABLE()

#define	__HAL_RCC_LPTIM3_CLK_ENABLE()

#define	__HAL_RCC_COMP12_CLK_ENABLE()

#define	__HAL_RCC_VREF_CLK_ENABLE()

#define	__HAL_RCC_RTC_CLK_ENABLE()

#define	__HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)

#define	__HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)

#define	__HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)

#define	__HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)

#define	__HAL_RCC_LPTIM2_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)

#define	__HAL_RCC_LPTIM3_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)

#define	__HAL_RCC_COMP12_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)

#define	__HAL_RCC_VREF_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)

#define	__HAL_RCC_RTC_CLK_DISABLE() (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)

#define	__HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) != 0U)
	Get the enable or disable status of the APB4 peripheral clock.

#define	__HAL_RCC_LPUART1_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)

#define	__HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) != 0U)

#define	__HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) != 0U)

#define	__HAL_RCC_LPTIM2_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) != 0U)

#define	__HAL_RCC_LPTIM3_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) != 0U)

#define	__HAL_RCC_COMP12_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) != 0U)

#define	__HAL_RCC_VREF_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) != 0U)

#define	__HAL_RCC_RTC_IS_CLK_ENABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) != 0U)

#define	__HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN) == 0U)

#define	__HAL_RCC_LPUART1_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)

#define	__HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN) == 0U)

#define	__HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN) == 0U)

#define	__HAL_RCC_LPTIM2_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN) == 0U)

#define	__HAL_RCC_LPTIM3_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN) == 0U)

#define	__HAL_RCC_COMP12_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN) == 0U)

#define	__HAL_RCC_VREF_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_VREFEN) == 0U)

#define	__HAL_RCC_RTC_IS_CLK_DISABLED() ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN) == 0U)

#define	__HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0x00E95011U) /* Resets MDMA, DMA2D, FMC, OSPI1, SDMMC1, OSPI2, IOMNGR, OTFD1, OTFD2 */
	Enable or disable the AHB3 peripheral reset.

#define	__HAL_RCC_MDMA_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_MDMARST))

#define	__HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_DMA2DRST))

#define	__HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_FMCRST))

#define	__HAL_RCC_SDMMC1_FORCE_RESET() (RCC->AHB3RSTR \|= (RCC_AHB3RSTR_SDMMC1RST))

#define	__HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)

#define	__HAL_RCC_MDMA_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))

#define	__HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))

#define	__HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))

#define	__HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))

#define	__HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0x02008023U) /* Resets DMA1, DMA2, ADC12, ETHMAC and USB1OTG */
	Force or release the AHB1 peripheral reset.

#define	__HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))

#define	__HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))

#define	__HAL_RCC_ADC12_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_ADC12RST))

#define	__HAL_RCC_USB1_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_USB1OTGHSRST))

#define	__HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)

#define	__HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))

#define	__HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))

#define	__HAL_RCC_ADC12_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))

#define	__HAL_RCC_USB1_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))

#define	__HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0x00030271U) /* Resets DCMI_PSSI, CRYPT, HASH, RNG, SDMMC2, FMAC and CORDIC */
	Force or release the AHB2 peripheral reset.

#define	__HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_DCMIRST))

#define	__HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))

#define	__HAL_RCC_SDMMC2_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_SDMMC2RST))

#define	__HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00U)

#define	__HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))

#define	__HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))

#define	__HAL_RCC_SDMMC2_RELEASE_RESET() (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))

#define	__HAL_RCC_AHB4_FORCE_RESET() (RCC->AHB4RSTR = 0x032806FFU) /* Resets GPIOA..GPIOH, GPIOJ, GPIOK, CRC, BDMA, ADC3 and HSEM */
	Force or release the AHB4 peripheral reset.

#define	__HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOARST)

#define	__HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOBRST)

#define	__HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOCRST)

#define	__HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIODRST)

#define	__HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOERST)

#define	__HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOFRST)

#define	__HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOGRST)

#define	__HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOHRST)

#define	__HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOJRST)

#define	__HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_GPIOKRST)

#define	__HAL_RCC_BDMA_FORCE_RESET() (RCC->AHB4RSTR) \|= (RCC_AHB4RSTR_BDMARST)

#define	__HAL_RCC_AHB4_RELEASE_RESET() (RCC->AHB4RSTR = 0x00U)

#define	__HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)

#define	__HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)

#define	__HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)

#define	__HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)

#define	__HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)

#define	__HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)

#define	__HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)

#define	__HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)

#define	__HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)

#define	__HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)

#define	__HAL_RCC_BDMA_RELEASE_RESET() (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)

#define	__HAL_RCC_APB3_FORCE_RESET() (RCC->APB3RSTR = 0x00000008U) /* Rests LTDC */
	Force or release the APB3 peripheral reset.

#define	__HAL_RCC_APB3_RELEASE_RESET() (RCC->APB3RSTR = 0x00U)

#define	__HAL_RCC_APB1L_FORCE_RESET() (RCC->APB1LRSTR = 0xEAFFC3FFU) /* Resets TIM2..TIM7, TIM12..TIM14, LPTIM1, SPI2, SPI3, SPDIFRX, USART2, USART3, UART4, UART5, I2C1..I2C3, I2C5, CEC, DAC12, UART7 and UART8 */
	Force or release the APB1 peripheral reset.

#define	__HAL_RCC_APB1H_FORCE_RESET() (RCC->APB1HRSTR = 0x03000136U) /* Resets CRS, SWP, OPAMP, MDIOS, FDCAN, TIM23 and TIM24 */

#define	__HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM2RST)

#define	__HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM3RST)

#define	__HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM4RST)

#define	__HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM5RST)

#define	__HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM6RST)

#define	__HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM7RST)

#define	__HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM12RST)

#define	__HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM13RST)

#define	__HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_TIM14RST)

#define	__HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_LPTIM1RST)

#define	__HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_SPI2RST)

#define	__HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_SPI3RST)

#define	__HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_SPDIFRXRST)

#define	__HAL_RCC_USART2_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_USART2RST)

#define	__HAL_RCC_USART3_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_USART3RST)

#define	__HAL_RCC_UART4_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_UART4RST)

#define	__HAL_RCC_UART5_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_UART5RST)

#define	__HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_I2C1RST)

#define	__HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_I2C2RST)

#define	__HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_I2C3RST)

#define	__HAL_RCC_CEC_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_CECRST)

#define	__HAL_RCC_DAC12_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_DAC12RST)

#define	__HAL_RCC_UART7_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_UART7RST)

#define	__HAL_RCC_UART8_FORCE_RESET() (RCC->APB1LRSTR) \|= (RCC_APB1LRSTR_UART8RST)

#define	__HAL_RCC_CRS_FORCE_RESET() (RCC->APB1HRSTR) \|= (RCC_APB1HRSTR_CRSRST)

#define	__HAL_RCC_SWPMI1_FORCE_RESET() (RCC->APB1HRSTR) \|= (RCC_APB1HRSTR_SWPMIRST)

#define	__HAL_RCC_OPAMP_FORCE_RESET() (RCC->APB1HRSTR) \|= (RCC_APB1HRSTR_OPAMPRST)

#define	__HAL_RCC_MDIOS_FORCE_RESET() (RCC->APB1HRSTR) \|= (RCC_APB1HRSTR_MDIOSRST)

#define	__HAL_RCC_FDCAN_FORCE_RESET() (RCC->APB1HRSTR) \|= (RCC_APB1HRSTR_FDCANRST)

#define	__HAL_RCC_APB1L_RELEASE_RESET() (RCC->APB1LRSTR = 0x00U)

#define	__HAL_RCC_APB1H_RELEASE_RESET() (RCC->APB1HRSTR = 0x00U)

#define	__HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)

#define	__HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)

#define	__HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)

#define	__HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)

#define	__HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)

#define	__HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)

#define	__HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)

#define	__HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)

#define	__HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)

#define	__HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)

#define	__HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)

#define	__HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)

#define	__HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)

#define	__HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)

#define	__HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)

#define	__HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)

#define	__HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)

#define	__HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)

#define	__HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)

#define	__HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)

#define	__HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)

#define	__HAL_RCC_DAC12_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)

#define	__HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)

#define	__HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)

#define	__HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)

#define	__HAL_RCC_SWPMI1_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)

#define	__HAL_RCC_OPAMP_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)

#define	__HAL_RCC_MDIOS_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)

#define	__HAL_RCC_FDCAN_RELEASE_RESET() (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)

#define	__HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0x405730F3U) /* Resets TIM1, TIM8, USART1, USART6, UART9, USART10, SPI1, SPI4, TIM15..TIM17, SPI5, SAI1 and DFSDM1 */
	Force or release the APB2 peripheral reset.

#define	__HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_TIM1RST)

#define	__HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_TIM8RST)

#define	__HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_USART1RST)

#define	__HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_USART6RST)

#define	__HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_SPI1RST)

#define	__HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_SPI4RST)

#define	__HAL_RCC_TIM15_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_TIM15RST)

#define	__HAL_RCC_TIM16_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_TIM16RST)

#define	__HAL_RCC_TIM17_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_TIM17RST)

#define	__HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_SPI5RST)

#define	__HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_SAI1RST)

#define	__HAL_RCC_DFSDM1_FORCE_RESET() (RCC->APB2RSTR) \|= (RCC_APB2RSTR_DFSDM1RST)

#define	__HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)

#define	__HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)

#define	__HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)

#define	__HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)

#define	__HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)

#define	__HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)

#define	__HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)

#define	__HAL_RCC_TIM15_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)

#define	__HAL_RCC_TIM16_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)

#define	__HAL_RCC_TIM17_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)

#define	__HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)

#define	__HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)

#define	__HAL_RCC_DFSDM1_RELEASE_RESET() (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)

#define	__HAL_RCC_APB4_FORCE_RESET() (RCC->APB4RSTR = 0x0420DEAAU) /* Resets SYSCFG, LPUART1, SPI6, I2C4, LPTIM2..LPTIM5, COMP12, VREF, SAI4 and DTS */
	Force or release the APB4 peripheral reset.

#define	__HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_SYSCFGRST)

#define	__HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_LPUART1RST)

#define	__HAL_RCC_SPI6_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_SPI6RST)

#define	__HAL_RCC_I2C4_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_I2C4RST)

#define	__HAL_RCC_LPTIM2_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_LPTIM2RST)

#define	__HAL_RCC_LPTIM3_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_LPTIM3RST)

#define	__HAL_RCC_COMP12_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_COMP12RST)

#define	__HAL_RCC_VREF_FORCE_RESET() (RCC->APB4RSTR) \|= (RCC_APB4RSTR_VREFRST)

#define	__HAL_RCC_APB4_RELEASE_RESET() (RCC->APB4RSTR = 0x00U)

#define	__HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)

#define	__HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)

#define	__HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)

#define	__HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)

#define	__HAL_RCC_LPTIM2_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)

#define	__HAL_RCC_LPTIM3_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)

#define	__HAL_RCC_COMP12_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)

#define	__HAL_RCC_VREF_RELEASE_RESET() (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)

#define	__HAL_RCC_MDMA_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_MDMALPEN))
	Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_DMA2DLPEN))

#define	__HAL_RCC_FLASH_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FLASHLPEN))

#define	__HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_FMCLPEN))

#define	__HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_SDMMC1LPEN))

#define	__HAL_RCC_DTCM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_DTCM1LPEN))

#define	__HAL_RCC_DTCM2_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_DTCM2LPEN))

#define	__HAL_RCC_ITCM_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_ITCMLPEN))

#define	__HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR \|= (RCC_AHB3LPENR_AXISRAM1LPEN))

#define	__HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE /* For backward compatibility */

#define	__HAL_RCC_MDMA_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))

#define	__HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))

#define	__HAL_RCC_FLASH_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))

#define	__HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))

#define	__HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))

#define	__HAL_RCC_DTCM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))

#define	__HAL_RCC_DTCM2_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))

#define	__HAL_RCC_ITCM_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))

#define	__HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN))

#define	__HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE /* For backward compatibility */

#define	__HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) != 0U)
	Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) != 0U)

#define	__HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) != 0U)

#define	__HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) != 0U)

#define	__HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) != 0U)

#define	__HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) != 0U)

#define	__HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) != 0U)

#define	__HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) != 0U)

#define	__HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U)

#define	__HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN) == 0U)

#define	__HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN) == 0U)

#define	__HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN) == 0U)

#define	__HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN) == 0U)

#define	__HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN) == 0U)

#define	__HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN) == 0U)

#define	__HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN) == 0U)

#define	__HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN) == 0U)

#define	__HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U)

#define	__HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
	ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))

#define	__HAL_RCC_ADC12_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_ADC12LPEN))

#define	__HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_USB1OTGHSLPEN))

#define	__HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

#define	__HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))

#define	__HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))

#define	__HAL_RCC_ADC12_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))

#define	__HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))

#define	__HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

#define	__HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) != 0U)
	Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != 0U)

#define	__HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) != 0U)

#define	__HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) != 0U)

#define	__HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)

#define	__HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN)) == 0U)

#define	__HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == 0U)

#define	__HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN)) == 0U)

#define	__HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN)) == 0U)

#define	__HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)

#define	__HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_DCMILPEN))
	ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))

#define	__HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_SDMMC2LPEN))

#define	__HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_AHBSRAM1LPEN))

#define	__HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_AHBSRAM2LPEN))

#define	__HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))

#define	__HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))

#define	__HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))

#define	__HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN))

#define	__HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN))

#define	__HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != 0U)
	Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != 0U)

#define	__HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) != 0U)

#define	__HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U)

#define	__HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U)

#define	__HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == 0U)

#define	__HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == 0U)

#define	__HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN)) == 0U)

#define	__HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U)

#define	__HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U)

#define	__HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOALPEN)
	ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOBLPEN)

#define	__HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOCLPEN)

#define	__HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIODLPEN)

#define	__HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOELPEN)

#define	__HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOFLPEN)

#define	__HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOGLPEN)

#define	__HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOHLPEN)

#define	__HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOJLPEN)

#define	__HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_GPIOKLPEN)

#define	__HAL_RCC_BDMA_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_BDMALPEN)

#define	__HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR) \|= (RCC_AHB4LPENR_BKPRAMLPEN)

#define	__HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB4LPENR \|= (RCC_AHB4LPENR_D3SRAM1LPEN))

#define	__HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)

#define	__HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)

#define	__HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)

#define	__HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)

#define	__HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)

#define	__HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)

#define	__HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)

#define	__HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)

#define	__HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)

#define	__HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)

#define	__HAL_RCC_BDMA_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)

#define	__HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)

#define	__HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB4LPENR &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))

#define	__HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) != 0U)
	Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) != 0U)

#define	__HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) != 0U)

#define	__HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) != 0U)

#define	__HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) != 0U)

#define	__HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) != 0U)

#define	__HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) != 0U)

#define	__HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) != 0U)

#define	__HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) != 0U)

#define	__HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) != 0U)

#define	__HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) != 0U)

#define	__HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) != 0U)

#define	__HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U)

#define	__HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN)) == 0U)

#define	__HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN)) == 0U)

#define	__HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN)) == 0U)

#define	__HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN)) == 0U)

#define	__HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN)) == 0U)

#define	__HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN)) == 0U)

#define	__HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN)) == 0U)

#define	__HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN)) == 0U)

#define	__HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN)) == 0U)

#define	__HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN)) == 0U)

#define	__HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN)) == 0U)

#define	__HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN)) == 0U)

#define	__HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U)

#define	__HAL_RCC_WWDG1_CLK_SLEEP_ENABLE() (RCC->APB3LPENR) \|= (RCC_APB3LPENR_WWDG1LPEN)
	ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_WWDG1_CLK_SLEEP_DISABLE() (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)

#define	__HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)
	Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED() ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)

#define	__HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM2LPEN)
	ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM3LPEN)

#define	__HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM4LPEN)

#define	__HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM5LPEN)

#define	__HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM6LPEN)

#define	__HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM7LPEN)

#define	__HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM12LPEN)

#define	__HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM13LPEN)

#define	__HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_TIM14LPEN)

#define	__HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_LPTIM1LPEN)

#define	__HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_SPI2LPEN)

#define	__HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_SPI3LPEN)

#define	__HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_SPDIFRXLPEN)

#define	__HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_USART2LPEN)

#define	__HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_USART3LPEN)

#define	__HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_UART4LPEN)

#define	__HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_UART5LPEN)

#define	__HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_I2C1LPEN)

#define	__HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_I2C2LPEN)

#define	__HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_I2C3LPEN)

#define	__HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_CECLPEN)

#define	__HAL_RCC_DAC12_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_DAC12LPEN)

#define	__HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_UART7LPEN)

#define	__HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LLPENR) \|= (RCC_APB1LLPENR_UART8LPEN)

#define	__HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) \|= (RCC_APB1HLPENR_CRSLPEN)

#define	__HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) \|= (RCC_APB1HLPENR_SWPMILPEN)

#define	__HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) \|= (RCC_APB1HLPENR_OPAMPLPEN)

#define	__HAL_RCC_MDIOS_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) \|= (RCC_APB1HLPENR_MDIOSLPEN)

#define	__HAL_RCC_FDCAN_CLK_SLEEP_ENABLE() (RCC->APB1HLPENR) \|= (RCC_APB1HLPENR_FDCANLPEN)

#define	__HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)

#define	__HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)

#define	__HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)

#define	__HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)

#define	__HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)

#define	__HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)

#define	__HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)

#define	__HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)

#define	__HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)

#define	__HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)

#define	__HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)

#define	__HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)

#define	__HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)

#define	__HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)

#define	__HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)

#define	__HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)

#define	__HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)

#define	__HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)

#define	__HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)

#define	__HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)

#define	__HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)

#define	__HAL_RCC_DAC12_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)

#define	__HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)

#define	__HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)

#define	__HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)

#define	__HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)

#define	__HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)

#define	__HAL_RCC_MDIOS_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)

#define	__HAL_RCC_FDCAN_CLK_SLEEP_DISABLE() (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)

#define	__HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) != 0U)
	Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) != 0U)

#define	__HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) != 0U)

#define	__HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) != 0U)

#define	__HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) != 0U)

#define	__HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) != 0U)

#define	__HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) != 0U)

#define	__HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) != 0U)

#define	__HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) != 0U)

#define	__HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) != 0U)

#define	__HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) != 0U)

#define	__HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) != 0U)

#define	__HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)

#define	__HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) != 0U)

#define	__HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) != 0U)

#define	__HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) != 0U)

#define	__HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) != 0U)

#define	__HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) != 0U)

#define	__HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) != 0U)

#define	__HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) != 0U)

#define	__HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) != 0U)

#define	__HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) != 0U)

#define	__HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) != 0U)

#define	__HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) != 0U)

#define	__HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) != 0U)

#define	__HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) != 0U)

#define	__HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) != 0U)

#define	__HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) != 0U)

#define	__HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) != 0U)

#define	__HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN)) == 0U)

#define	__HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN)) == 0U)

#define	__HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN)) == 0U)

#define	__HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN)) == 0U)

#define	__HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN)) == 0U)

#define	__HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN)) == 0U)

#define	__HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN)) == 0U)

#define	__HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN)) == 0U)

#define	__HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN)) == 0U)

#define	__HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN)) == 0U)

#define	__HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN)) == 0U)

#define	__HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN)) == 0U)

#define	__HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)

#define	__HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN)) == 0U)

#define	__HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN)) == 0U)

#define	__HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN)) == 0U)

#define	__HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN)) == 0U)

#define	__HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN)) == 0U)

#define	__HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN)) == 0U)

#define	__HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN)) == 0U)

#define	__HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN)) == 0U)

#define	__HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN)) == 0U)

#define	__HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN)) == 0U)

#define	__HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN)) == 0U)

#define	__HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN)) == 0U)

#define	__HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN)) == 0U)

#define	__HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN)) == 0U)

#define	__HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN)) == 0U)

#define	__HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED() ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN)) == 0U)

#define	__HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_TIM1LPEN)
	ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_TIM8LPEN)

#define	__HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_USART1LPEN)

#define	__HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_USART6LPEN)

#define	__HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_SPI1LPEN)

#define	__HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_SPI4LPEN)

#define	__HAL_RCC_TIM15_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_TIM15LPEN)

#define	__HAL_RCC_TIM16_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_TIM16LPEN)

#define	__HAL_RCC_TIM17_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_TIM17LPEN)

#define	__HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_SPI5LPEN)

#define	__HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_SAI1LPEN)

#define	__HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR) \|= (RCC_APB2LPENR_DFSDM1LPEN)

#define	__HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)

#define	__HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)

#define	__HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)

#define	__HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)

#define	__HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)

#define	__HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)

#define	__HAL_RCC_TIM15_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)

#define	__HAL_RCC_TIM16_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)

#define	__HAL_RCC_TIM17_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)

#define	__HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)

#define	__HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)

#define	__HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)

#define	__HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != 0U)
	Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != 0U)

#define	__HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)

#define	__HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)

#define	__HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != 0U)

#define	__HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != 0U)

#define	__HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) != 0U)

#define	__HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) != 0U)

#define	__HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) != 0U)

#define	__HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != 0U)

#define	__HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != 0U)

#define	__HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)

#define	__HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == 0U)

#define	__HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == 0U)

#define	__HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)

#define	__HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)

#define	__HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == 0U)

#define	__HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == 0U)

#define	__HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN)) == 0U)

#define	__HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN)) == 0U)

#define	__HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN)) == 0U)

#define	__HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == 0U)

#define	__HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == 0U)

#define	__HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)

#define	__HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_SYSCFGLPEN)
	ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.

#define	__HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_LPUART1LPEN)

#define	__HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_SPI6LPEN)

#define	__HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_I2C4LPEN)

#define	__HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_LPTIM2LPEN)

#define	__HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_LPTIM3LPEN)

#define	__HAL_RCC_COMP12_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_COMP12LPEN)

#define	__HAL_RCC_VREF_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_VREFLPEN)

#define	__HAL_RCC_RTC_CLK_SLEEP_ENABLE() (RCC->APB4LPENR) \|= (RCC_APB4LPENR_RTCAPBLPEN)

#define	__HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)

#define	__HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)

#define	__HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)

#define	__HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)

#define	__HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)

#define	__HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)

#define	__HAL_RCC_COMP12_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)

#define	__HAL_RCC_VREF_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)

#define	__HAL_RCC_RTC_CLK_SLEEP_DISABLE() (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)

#define	__HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) != 0U)
	Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode.

#define	__HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)

#define	__HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) != 0U)

#define	__HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) != 0U)

#define	__HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) != 0U)

#define	__HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) != 0U)

#define	__HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) != 0U)

#define	__HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) != 0U)

#define	__HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) != 0U)

#define	__HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN)) == 0U)

#define	__HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)

#define	__HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN)) == 0U)

#define	__HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN)) == 0U)

#define	__HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN)) == 0U)

#define	__HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN)) == 0U)

#define	__HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN)) == 0U)

#define	__HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN)) == 0U)

#define	__HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED() ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN)) == 0U)

#define	__HAL_RCC_HSI_CONFIG(__STATE__) MODIFY_REG(RCC->CR, RCC_CR_HSION \| RCC_CR_HSIDIV , (uint32_t)(__STATE__))
	Enable or disable peripheral bus clock when D3 domain is in DRUN.

#define	__HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))
	Macro to get the HSI divider.

#define	__HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
	Macros to enable or disable the Internal High Speed oscillator (HSI).

#define	__HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)

#define	__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);
	Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

#define	__HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
	Macros to enable or disable the force of the Internal High Speed oscillator (HSI) in STOP mode to be quickly available as kernel clock for some peripherals.

#define	__HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)

#define	__HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON);
	Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).

#define	__HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);

#define	__HAL_RCC_CSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSION)
	Macros to enable or disable the Internal oscillator (CSI).

#define	__HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)

#define	__HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)
	Macro Adjusts the Internal oscillator (CSI) calibration value.

#define	__HAL_RCC_CSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_CSIKERON)
	Macros to enable or disable the force of the Low-power Internal oscillator (CSI) in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.

#define	__HAL_RCC_CSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)

#define	__HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
	Macros to enable or disable the Internal Low Speed oscillator (LSI).

#define	__HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)

#define	__HAL_RCC_HSE_CONFIG(__STATE__)
	Macro to configure the External High Speed oscillator (HSE).

#define	__HAL_RCC_LSE_CONFIG(__STATE__)
	Macro to configure the External Low Speed oscillator (LSE).

#define	__HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
	Macros to enable or disable the the RTC clock.

#define	__HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

#define	__HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__)
	Macros to configure the RTC clock (RTCCLK).

#define	__HAL_RCC_RTC_CONFIG(__RTCCLKSource__)

#define	__HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))

#define	__HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
	Macros to force or release the Backup domain reset.

#define	__HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)

#define	__HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON)
	Macros to enable or disable the main PLL.

#define	__HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)

#define	__HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__) SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))
	Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)

#define	__HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__) CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))

#define	__HAL_RCC_PLLFRACN_ENABLE() SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)
	Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO.

#define	__HAL_RCC_PLLFRACN_DISABLE() CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)

#define	__HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__, __PLLR1__)
	Macro to configures the main PLL clock source, multiplication and division factors.

#define	__HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))
	Macro to configure the PLLs clock source.

#define	__HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)
	Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor.

#define	__HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))
	Macro to select the PLL1 reference frequency range.

#define	__HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))
	Macro to select the PLL1 reference frequency range.

#define	__HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
	Macro to get the clock source used as system clock.

#define	__HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
	Macro to configure the system clock source.

#define	__HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))
	Macro to get the oscillator used as PLL clock source.

#define	__HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 \| RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) \| (__MCODIV__)))
	Macro to configure the MCO1 clock.

#define	__HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 \| RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) \| ((__MCODIV__) << 7)));
	Macro to configure the MCO2 clock.

#define	__HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));
	Macro to configure the External Low Speed oscillator (LSE) drive capability.

#define	__HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))
	Macro to configure the wake up from stop clock.

#define	__HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))
	Macro to configure the Kernel wake up from stop clock.

#define	__HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))
	Enable RCC interrupt.

#define	__HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))
	Disable RCC interrupt.

#define	__HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))
	Clear the RCC's interrupt pending bits.

#define	__HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))
	Check the RCC's interrupt has occurred or not.

#define	__HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR \|= RCC_RSR_RMVF)
	Set RMVF bit to clear the reset flags.

#define	RCC_FLAG_MASK ((uint8_t)0x1F)
	Check RCC flag is set or not.

#define	__HAL_RCC_GET_FLAG(__FLAG__)

#define	RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)

#define	HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT

#define	HSI_TIMEOUT_VALUE (2U) /* 2 ms */

#define	HSI48_TIMEOUT_VALUE (2U) /* 2 ms */

#define	CSI_TIMEOUT_VALUE (2U) /* 2 ms */

#define	LSI_TIMEOUT_VALUE (2U) /* 2 ms */

#define	PLL_TIMEOUT_VALUE (2U) /* 2 ms */

#define	PLL_FRAC_TIMEOUT_VALUE (1U) /* PLL Fractional part waiting time before new latch enable : 1 ms */

#define	CLOCKSWITCH_TIMEOUT_VALUE (5000U) /* 5 s */

#define	RCC_DBP_TIMEOUT_VALUE (100U)

#define	RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT

#define	IS_RCC_OSCILLATORTYPE(OSCILLATOR)

#define	IS_RCC_HSE(HSE)

#define	IS_RCC_LSE(LSE)

#define	IS_RCC_HSI(HSI)

#define	IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))

#define	IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))

#define	IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) \|\| ((CSI) == RCC_CSI_ON))

#define	IS_RCC_PLL(PLL)

#define	IS_RCC_PLLSOURCE(SOURCE)

#define	IS_RCC_PLLRGE_VALUE(VALUE)

#define	IS_RCC_PLLVCO_VALUE(VALUE) (((VALUE) == RCC_PLL1VCOWIDE) \|\| ((VALUE) == RCC_PLL1VCOMEDIUM))

#define	IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <= 8191U)

#define	IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))

#define	IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))

#define	IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

#define	IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

#define	IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

#define	IS_RCC_PLLCLOCKOUT_VALUE(VALUE)

#define	IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU))

#define	IS_RCC_SYSCLKSOURCE(SOURCE)

#define	IS_RCC_SYSCLK(SYSCLK)

#define	IS_RCC_HCLK(HCLK)

#define	IS_RCC_CDPCLK1(CDPCLK1)

#define	IS_RCC_D1PCLK1 IS_RCC_CDPCLK1 /* for legacy compatibility between H7 lines */

#define	IS_RCC_PCLK1(PCLK1)

#define	IS_RCC_PCLK2(PCLK2)

#define	IS_RCC_SRDPCLK1(SRDPCLK1)

#define	IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/

#define	IS_RCC_RTCCLKSOURCE(SOURCE)

#define	IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))

#define	IS_RCC_MCO1SOURCE(SOURCE)

#define	IS_RCC_MCO2SOURCE(SOURCE)

#define	IS_RCC_MCODIV(DIV)

#define	IS_RCC_FLAG(FLAG)

#define	IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU)

#define	IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU)

#define	IS_RCC_STOP_WAKEUPCLOCK(SOURCE)

#define	IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE)

Functions
HAL_StatusTypeDef	HAL_RCC_DeInit (void)

HAL_StatusTypeDef	HAL_RCC_OscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)

HAL_StatusTypeDef	HAL_RCC_ClockConfig (RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)

void	HAL_RCC_MCOConfig (uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)

void	HAL_RCC_EnableCSS (void)

void	HAL_RCC_DisableCSS (void)

uint32_t	HAL_RCC_GetSysClockFreq (void)

uint32_t	HAL_RCC_GetHCLKFreq (void)

uint32_t	HAL_RCC_GetPCLK1Freq (void)

uint32_t	HAL_RCC_GetPCLK2Freq (void)

void	HAL_RCC_GetOscConfig (RCC_OscInitTypeDef *RCC_OscInitStruct)

void	HAL_RCC_GetClockConfig (RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency)

void	HAL_RCC_NMI_IRQHandler (void)

void	HAL_RCC_CSSCallback (void)

Detailed Description

Header file of RCC HAL module.

Author: MCD Application Team

Attention

This software is licensed under terms that can be found in the LICENSE file in the root directory of this software component. If no LICENSE file comes with this software, it is provided AS-IS.

Data Structures

Macros

Functions

Detailed Description