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#define | LEON_INTERRUPT_CORRECTABLE_MEMORY_ERROR 1 |
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#define | LEON_INTERRUPT_UART_2_RX_TX 2 |
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#define | LEON_INTERRUPT_UART_1_RX_TX 3 |
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#define | LEON_INTERRUPT_EXTERNAL_0 4 |
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#define | LEON_INTERRUPT_EXTERNAL_1 5 |
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#define | LEON_INTERRUPT_EXTERNAL_2 6 |
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#define | LEON_INTERRUPT_EXTERNAL_3 7 |
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#define | LEON_INTERRUPT_TIMER1 8 |
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#define | LEON_INTERRUPT_TIMER2 9 |
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#define | LEON_INTERRUPT_EMPTY1 10 |
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#define | LEON_INTERRUPT_EMPTY2 11 |
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#define | LEON_INTERRUPT_EMPTY3 12 |
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#define | LEON_INTERRUPT_EMPTY4 13 |
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#define | LEON_INTERRUPT_EMPTY5 14 |
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#define | LEON_INTERRUPT_EMPTY6 15 |
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#define | LEON_TRAP_TYPE(_source) SPARC_INTERRUPT_SOURCE_TO_TRAP( _source ) |
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#define | LEON_TRAP_SOURCE(_trap) SPARC_INTERRUPT_TRAP_TO_SOURCE( _trap ) |
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#define | LEON_INT_TRAP(_trap) SPARC_IS_INTERRUPT_TRAP( _trap ) |
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#define | LEON_MEMORY_CONFIGURATION_PROM_SIZE_MASK 0x0003C000 |
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#define | LEON_MEMORY_CONFIGURATION_RAM_SIZE_MASK 0x00001E00 |
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#define | LEON_REG_TIMER_CONTROL_EN 0x00000001 /* 1 = enable counting */ |
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#define | LEON_REG_TIMER_CONTROL_RL 0x00000002 /* 1 = reload at 0 */ |
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#define | LEON_REG_TIMER_CONTROL_LD 0x00000004 /* 1 = load counter */ |
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#define | LEON_REG_UART_CONTROL_RTD 0x000000FF /* RX/TX data */ |
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#define | LEON_REG_UART_STATUS_CLR 0x00000000 /* Clear all status bits */ |
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#define | LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */ |
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#define | LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */ |
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#define | LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */ |
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#define | LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */ |
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#define | LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */ |
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#define | LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */ |
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#define | LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */ |
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#define | LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */ |
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#define | LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */ |
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#define | LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */ |
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#define | LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */ |
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#define | LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */ |
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#define | LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */ |
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#define | LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */ |
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#define | LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */ |
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#define | LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */ |
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#define | LEON_Clear_interrupt(_source) |
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#define | LEON_Force_interrupt(_source) |
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#define | LEON_Is_interrupt_pending(_source) (LEON_REG.Interrupt_Pending & (1 << (_source))) |
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#define | LEON_Is_interrupt_masked(_source) (!(LEON_REG.Interrupt_Mask & (1 << (_source)))) |
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#define | LEON_Mask_interrupt(_source) |
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#define | LEON_Unmask_interrupt(_source) |
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#define | LEON_Disable_interrupt(_source, _previous) |
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#define | LEON_Restore_interrupt(_source, _previous) |
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#define | BSP_Clear_interrupt(_source) LEON_Clear_interrupt(_source) |
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#define | BSP_Force_interrupt(_source) LEON_Force_interrupt(_source) |
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#define | BSP_Clear_forced_interrupt(_source) |
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#define | BSP_Is_interrupt_pending(_source) LEON_Is_interrupt_pending(_source) |
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#define | BSP_Is_interrupt_forced(_source) (LEON_REG.Interrupt_Force & (1 << (_source))) |
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#define | BSP_Is_interrupt_masked(_source) LEON_Is_interrupt_masked(_source) |
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#define | BSP_Unmask_interrupt(_source) LEON_Unmask_interrupt(_source) |
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#define | BSP_Mask_interrupt(_source) LEON_Mask_interrupt(_source) |
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#define | BSP_Disable_interrupt(_source, _previous) LEON_Disable_interrupt(_source, _prev) |
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#define | BSP_Restore_interrupt(_source, _previous) LEON_Restore_interrupt(_source, _previous) |
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#define | BSP_Cpu_Is_interrupt_masked(_source, _cpu) BSP_Is_interrupt_masked(_source) |
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#define | BSP_Cpu_Unmask_interrupt(_source, _cpu) BSP_Unmask_interrupt(_source) |
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#define | BSP_Cpu_Mask_interrupt(_source, _cpu) BSP_Mask_interrupt(_source) |
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#define | BSP_Cpu_Disable_interrupt(_source, _previous, _cpu) BSP_Disable_interrupt(_source, _prev) |
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#define | BSP_Cpu_Restore_interrupt(_source, _previous, _cpu) BSP_Cpu_Restore_interrupt(_source, _previous) |
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#define | LEON_REG_TIMER_COUNTER_RELOAD_AT_ZERO 0x00000002 |
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#define | LEON_REG_TIMER_COUNTER_STOP_AT_ZERO 0x00000000 |
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#define | LEON_REG_TIMER_COUNTER_LOAD_COUNTER 0x00000004 |
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#define | LEON_REG_TIMER_COUNTER_ENABLE_COUNTING 0x00000001 |
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#define | LEON_REG_TIMER_COUNTER_DISABLE_COUNTING 0x00000000 |
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#define | LEON_REG_TIMER_COUNTER_RELOAD_MASK 0x00000002 |
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#define | LEON_REG_TIMER_COUNTER_ENABLE_MASK 0x00000001 |
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#define | LEON_REG_TIMER_COUNTER_DEFINED_MASK 0x00000003 |
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#define | LEON_REG_TIMER_COUNTER_CURRENT_MODE_MASK 0x00000003 |
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This include file contains information pertaining to the LEON-1. The LEON-1 is a custom SPARC V7 implementation. This CPU has a number of on-board peripherals and was developed by the European Space Agency to target space applications.
NOTE: Other than where absolutely required, this version currently supports only the peripherals and bits used by the basic board support package. This includes at least significant pieces of the following items:
- UART Channels A and B
- Real Time Clock
- Memory Control Register
- Interrupt Control