i386 specific support. More...

Modules
	Processor Dependent Interrupt Management
	i386 Interrupt Management

	i386 Assembler Support
	i386 Assembler Support

	i386 Paravirtualization Support

Data Structures
struct	Context_Control
	Thread register context. More...

struct	Context_Control_fp
	SPARC basic context. More...

struct	CPU_Exception_frame
	The set of registers that specifies the complete processor state. More...

struct	CPU_Interrupt_frame
	Interrupt stack frame (ISF). More...

Macros
#define	CPU_SIMPLE_VECTORED_INTERRUPTS FALSE

#define	CPU_ISR_PASSES_FRAME_POINTER FALSE

#define	CPU_HARDWARE_FP FALSE

#define	CPU_SOFTWARE_FP FALSE

#define	CPU_ALL_TASKS_ARE_FP FALSE

#define	CPU_IDLE_TASK_IS_FP FALSE

#define	CPU_USE_DEFERRED_FP_SWITCH TRUE

#define	CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE

#define	CPU_STACK_GROWS_UP FALSE

#define	CPU_CACHE_LINE_BYTES 64

#define	CPU_STRUCTURE_ALIGNMENT

#define	CPU_MAXIMUM_PROCESSORS 32

#define	I386_CONTEXT_CONTROL_EFLAGS_OFFSET 0

#define	I386_CONTEXT_CONTROL_ESP_OFFSET 4

#define	I386_CONTEXT_CONTROL_EBP_OFFSET 8

#define	I386_CONTEXT_CONTROL_EBX_OFFSET 12

#define	I386_CONTEXT_CONTROL_ESI_OFFSET 16

#define	I386_CONTEXT_CONTROL_EDI_OFFSET 20

#define	I386_CONTEXT_CONTROL_GS_0_OFFSET 24

#define	I386_CONTEXT_CONTROL_GS_1_OFFSET 28

#define	I386_CONTEXT_CONTROL_ISR_DISPATCH_DISABLE 32

#define	_CPU_Context_Get_SP(_context) (uintptr_t) (_context)->esp

#define	CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )

#define	CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */

#define	CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024

#define	CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE

#define	CPU_STACK_MINIMUM_SIZE 4096

#define	CPU_SIZEOF_POINTER 4

#define	CPU_ALIGNMENT 4

#define	CPU_HEAP_ALIGNMENT CPU_ALIGNMENT

#define	CPU_STACK_ALIGNMENT 16

#define	CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES

#define	_CPU_ISR_Disable(_level) i386_disable_interrupts( _level )

#define	_CPU_ISR_Enable(_level) i386_enable_interrupts( _level )

#define	_CPU_ISR_Flash(_level) i386_flash_interrupts( _level )

#define	_CPU_ISR_Set_level(_new_level)

#define	_CPU_Interrupt_stack_setup(_lo, _hi)

#define	CPU_EFLAGS_INTERRUPTS_ON 0x00003202

#define	CPU_EFLAGS_INTERRUPTS_OFF 0x00003002

#define	_CPU_Context_Restart_self(_the_context) _CPU_Context_restore( (_the_context) );

#define	_CPU_Context_Initialize_fp(_fp_area)

#define	CPU_USE_LIBC_INIT_FINI_ARRAY FALSE

#define	CPU_USE_GENERIC_BITFIELD_CODE FALSE

#define	_CPU_Bitfield_Find_first_bit(_value, _output)

#define	_CPU_Priority_Mask(_bit_number) ( 1 << (_bit_number) )

#define	_CPU_Priority_bits_index(_priority) (_priority)

#define	CPU_PER_CPU_CONTROL_SIZE 0

#define	CPU_INTERRUPT_FRAME_SIZE 52

#define	CPU_THREAD_LOCAL_STORAGE_VARIANT 20

Typedefs
typedef void(*	cpuExcHandlerType) (CPU_Exception_frame *)

typedef void(*	CPU_ISR_handler) (void)

typedef uint32_t	CPU_Counter_ticks

Enumerations
enum	Intel_symbolic_exception_name { I386_EXCEPTION_DIVIDE_BY_ZERO = 0 , I386_EXCEPTION_DEBUG = 1 , I386_EXCEPTION_NMI = 2 , I386_EXCEPTION_BREAKPOINT = 3 , I386_EXCEPTION_OVERFLOW = 4 , I386_EXCEPTION_BOUND = 5 , I386_EXCEPTION_ILLEGAL_INSTR = 6 , I386_EXCEPTION_MATH_COPROC_UNAVAIL = 7 , I386_EXCEPTION_DOUBLE_FAULT = 8 , I386_EXCEPTION_I386_COPROC_SEG_ERR = 9 , I386_EXCEPTION_INVALID_TSS = 10 , I386_EXCEPTION_SEGMENT_NOT_PRESENT = 11 , I386_EXCEPTION_STACK_SEGMENT_FAULT = 12 , I386_EXCEPTION_GENERAL_PROT_ERR = 13 , I386_EXCEPTION_PAGE_FAULT = 14 , I386_EXCEPTION_INTEL_RES15 = 15 , I386_EXCEPTION_FLOAT_ERROR = 16 , I386_EXCEPTION_ALIGN_CHECK = 17 , I386_EXCEPTION_MACHINE_CHECK = 18 , I386_EXCEPTION_ENTER_RDBG = 50 }

Functions
void	rtems_exception_init_mngt (void)

uint32_t	_CPU_ISR_Get_level (void)

void	_CPU_Context_Initialize (Context_Control the_context, void stack_area_begin, size_t stack_area_size, uint32_t new_level, void(entry_point)(void), bool is_fp, void tls_area)

void	_CPU_Initialize (void)
	CPU initialization.

void	_CPU_ISR_install_vector (uint32_t vector, CPU_ISR_handler new_handler, CPU_ISR_handler *old_handler)

void *	_CPU_Thread_Idle_body (uintptr_t ignored)

void	_CPU_Context_switch (Context_Control run, Context_Control heir)
	CPU switch context.

RTEMS_NO_RETURN void	_CPU_Context_switch_no_return (Context_Control executing, Context_Control heir)

RTEMS_NO_RETURN void	_CPU_Context_restore (Context_Control *new_context)

void	_CPU_Context_save_fp (Context_Control_fp **fp_context_ptr)

void	_CPU_Context_restore_fp (Context_Control_fp **fp_context_ptr)

void	_CPU_Exception_frame_print (const CPU_Exception_frame *frame)

uint32_t	_CPU_Counter_frequency (void)

CPU_Counter_ticks	_CPU_Counter_read (void)

RTEMS_NO_RETURN void	_CPU_Fatal_halt (uint32_t source, CPU_Uint32ptr error)

Variables
cpuExcHandlerType	_currentExcHandler

Context_Control_fp	_CPU_Null_fp_context

Detailed Description

i386 specific support.

i386 Architecture Support

This include file contains information pertaining to the Intel i386 processor.

This file contains definitions for data structure related to Intel system programming. More information can be found on Intel site and more precisely in the following book :

Pentium Processor familly
Developper's Manual

Volume 3 : Architecture and Programming Manual

Formerly contained in and extracted from libcpu/i386/cpu.h.

Applications must not include this file directly.

This file contains definition and constants related to Intel Cpu

Macro Definition Documentation

◆ _CPU_Bitfield_Find_first_bit

#define _CPU_Bitfield_Find_first_bit	(	_value,
		_output
	)

Value:

  { \
    uint16_t __value_in_register = ( _value ); \
    uint16_t __output = 0; \
    __asm__ volatile ( "bsfw    %0,%1 " \
                    : "=r" ( __value_in_register ), "=r" ( __output ) \
                    : "0"  ( __value_in_register ), "1"  ( __output ) \
    ); \
    ( _output ) = __output; \
  }

◆ _CPU_Context_Initialize_fp

#define _CPU_Context_Initialize_fp ( _fp_area )

Value:

  { \
    memcpy( *_fp_area, &_CPU_Null_fp_context, CPU_CONTEXT_FP_SIZE ); \
  }

◆ _CPU_Interrupt_stack_setup

#define _CPU_Interrupt_stack_setup	(	_lo,
		_hi
	)

Value:

    do {                                        \
        _hi = (void*)(((uintptr_t)(_hi) - 4) & ~ (CPU_STACK_ALIGNMENT - 1)); \
    } while (0)

◆ _CPU_ISR_Set_level

#define _CPU_ISR_Set_level ( _new_level )

Value:

  { \
    if ( _new_level ) __asm__ volatile ( "cli" ); \
    else              __asm__ volatile ( "sti" ); \
  }

Function Documentation

◆ _CPU_Context_restore()

RTEMS_NO_RETURN void _CPU_Context_restore ( Context_Control * new_context )

This routine is generally used only to restart self in an efficient manner. It may simply be a label in _CPU_Context_switch.

Parameters

[in] new_context points to the context to be restored.

Note: May be unnecessary to reload some registers.

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_Context_switch()

void _CPU_Context_switch	(	Context_Control *	run,
		Context_Control *	heir
	)

CPU switch context.

This routine switches from the run context to the heir context.

Parameters

[in]	run	points to the context of the currently executing task
[in]	heir	points to the context of the heir task

Port Specific Information:

XXX document implementation including references if appropriate

◆ _CPU_Fatal_halt()

RTEMS_NO_RETURN void _CPU_Fatal_halt	(	uint32_t	source,
		CPU_Uint32ptr	error
	)

Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:

Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.

THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

◆ _CPU_Initialize()

void _CPU_Initialize ( void )

CPU initialization.

CPU initialize. This routine performs CPU dependent initialization.

CPU initialization.

◆ _CPU_ISR_Get_level()

uint32_t _CPU_ISR_Get_level ( void )

Return the current interrupt disable level for this task in the format used by the interrupt level portion of the task mode.

Note: This routine usually must be implemented as a subroutine.

Port Specific Information:

XXX document implementation including references if appropriate

Modules

Data Structures

Macros

Typedefs

Enumerations

Functions

Variables

Detailed Description

Macro Definition Documentation

◆ _CPU_Bitfield_Find_first_bit

◆ _CPU_Context_Initialize_fp

◆ _CPU_Interrupt_stack_setup

◆ _CPU_ISR_Set_level

Function Documentation

◆ _CPU_Context_restore()

◆ _CPU_Context_switch()

◆ _CPU_Fatal_halt()

◆ _CPU_Initialize()

◆ _CPU_ISR_Get_level()