PWM Peripheral Access Layer

Modules
	PWM Register Masks

Data Structures
struct	PWM_Type

Macros
#define	PWM1_BASE   (0x403DC000u)
#define	PWM1   ((PWM_Type *)PWM1_BASE)
#define	PWM2_BASE   (0x403E0000u)
#define	PWM2   ((PWM_Type *)PWM2_BASE)
#define	PWM3_BASE   (0x403E4000u)
#define	PWM3   ((PWM_Type *)PWM3_BASE)
#define	PWM4_BASE   (0x403E8000u)
#define	PWM4   ((PWM_Type *)PWM4_BASE)
#define	PWM_BASE_ADDRS   { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
#define	PWM_BASE_PTRS   { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
#define	PWM_CMP_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define	PWM_RELOAD_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define	PWM_CAPTURE_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define	PWM_FAULT_IRQS   { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
#define	PWM_RELOAD_ERROR_IRQS   { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
#define	PWM1_BASE   (0x4018C000u)
#define	PWM1   ((PWM_Type *)PWM1_BASE)
#define	PWM2_BASE   (0x40190000u)
#define	PWM2   ((PWM_Type *)PWM2_BASE)
#define	PWM3_BASE   (0x40194000u)
#define	PWM3   ((PWM_Type *)PWM3_BASE)
#define	PWM4_BASE   (0x40198000u)
#define	PWM4   ((PWM_Type *)PWM4_BASE)
#define	PWM_BASE_ADDRS   { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
#define	PWM_BASE_PTRS   { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
#define	PWM_CMP_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define	PWM_RELOAD_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define	PWM_CAPTURE_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define	PWM_FAULT_IRQS   { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
#define	PWM_RELOAD_ERROR_IRQS   { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
#define	PWM1_BASE   (0x4018C000u)
#define	PWM1   ((PWM_Type *)PWM1_BASE)
#define	PWM2_BASE   (0x40190000u)
#define	PWM2   ((PWM_Type *)PWM2_BASE)
#define	PWM3_BASE   (0x40194000u)
#define	PWM3   ((PWM_Type *)PWM3_BASE)
#define	PWM4_BASE   (0x40198000u)
#define	PWM4   ((PWM_Type *)PWM4_BASE)
#define	PWM_BASE_ADDRS   { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
#define	PWM_BASE_PTRS   { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
#define	PWM_CMP_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define	PWM_RELOAD_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define	PWM_CAPTURE_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define	PWM_FAULT_IRQS   { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
#define	PWM_RELOAD_ERROR_IRQS   { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }

Detailed Description

Macro Definition Documentation

PWM1 [1/3]

#define PWM1   ((PWM_Type *)PWM1_BASE)

Peripheral PWM1 base pointer

PWM1 [2/3]

#define PWM1   ((PWM_Type *)PWM1_BASE)

Peripheral PWM1 base pointer

PWM1 [3/3]

#define PWM1   ((PWM_Type *)PWM1_BASE)

Peripheral PWM1 base pointer

PWM1_BASE [1/3]

#define PWM1_BASE   (0x403DC000u)

Peripheral PWM1 base address

PWM1_BASE [2/3]

#define PWM1_BASE   (0x4018C000u)

Peripheral PWM1 base address

PWM1_BASE [3/3]

#define PWM1_BASE   (0x4018C000u)

Peripheral PWM1 base address

PWM2 [1/3]

#define PWM2   ((PWM_Type *)PWM2_BASE)

Peripheral PWM2 base pointer

PWM2 [2/3]

#define PWM2   ((PWM_Type *)PWM2_BASE)

Peripheral PWM2 base pointer

PWM2 [3/3]

#define PWM2   ((PWM_Type *)PWM2_BASE)

Peripheral PWM2 base pointer

PWM2_BASE [1/3]

#define PWM2_BASE   (0x403E0000u)

Peripheral PWM2 base address

PWM2_BASE [2/3]

#define PWM2_BASE   (0x40190000u)

Peripheral PWM2 base address

PWM2_BASE [3/3]

#define PWM2_BASE   (0x40190000u)

Peripheral PWM2 base address

PWM3 [1/3]

#define PWM3   ((PWM_Type *)PWM3_BASE)

Peripheral PWM3 base pointer

PWM3 [2/3]

#define PWM3   ((PWM_Type *)PWM3_BASE)

Peripheral PWM3 base pointer

PWM3 [3/3]

#define PWM3   ((PWM_Type *)PWM3_BASE)

Peripheral PWM3 base pointer

PWM3_BASE [1/3]

#define PWM3_BASE   (0x403E4000u)

Peripheral PWM3 base address

PWM3_BASE [2/3]

#define PWM3_BASE   (0x40194000u)

Peripheral PWM3 base address

PWM3_BASE [3/3]

#define PWM3_BASE   (0x40194000u)

Peripheral PWM3 base address

PWM4 [1/3]

#define PWM4   ((PWM_Type *)PWM4_BASE)

Peripheral PWM4 base pointer

PWM4 [2/3]

#define PWM4   ((PWM_Type *)PWM4_BASE)

Peripheral PWM4 base pointer

PWM4 [3/3]

#define PWM4   ((PWM_Type *)PWM4_BASE)

Peripheral PWM4 base pointer

PWM4_BASE [1/3]

#define PWM4_BASE   (0x403E8000u)

Peripheral PWM4 base address

PWM4_BASE [2/3]

#define PWM4_BASE   (0x40198000u)

Peripheral PWM4 base address

PWM4_BASE [3/3]

#define PWM4_BASE   (0x40198000u)

Peripheral PWM4 base address

PWM_BASE_ADDRS [1/3]

#define PWM_BASE_ADDRS   { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }

Array initializer of PWM peripheral base addresses

PWM_BASE_ADDRS [2/3]

#define PWM_BASE_ADDRS   { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }

Array initializer of PWM peripheral base addresses

PWM_BASE_ADDRS [3/3]

#define PWM_BASE_ADDRS   { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }

Array initializer of PWM peripheral base addresses

PWM_BASE_PTRS [1/3]

#define PWM_BASE_PTRS   { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }

Array initializer of PWM peripheral base pointers

PWM_BASE_PTRS [2/3]

#define PWM_BASE_PTRS   { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }

Array initializer of PWM peripheral base pointers

PWM_BASE_PTRS [3/3]

#define PWM_BASE_PTRS   { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }

Array initializer of PWM peripheral base pointers

PWM_CMP_IRQS [1/3]

#define PWM_CMP_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }

Interrupt vectors for the PWM peripheral type

PWM_CMP_IRQS [2/3]

#define PWM_CMP_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }

Interrupt vectors for the PWM peripheral type

PWM_CMP_IRQS [3/3]

#define PWM_CMP_IRQS   { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }

Interrupt vectors for the PWM peripheral type