VERID - Version ID Register
#define	LPUART_VERID_FEATURE_MASK (0xFFFFU)

#define	LPUART_VERID_FEATURE_SHIFT (0U)

#define	LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)

#define	LPUART_VERID_MINOR_MASK (0xFF0000U)

#define	LPUART_VERID_MINOR_SHIFT (16U)

#define	LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)

#define	LPUART_VERID_MAJOR_MASK (0xFF000000U)

#define	LPUART_VERID_MAJOR_SHIFT (24U)

#define	LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)

PARAM - Parameter Register
#define	LPUART_PARAM_TXFIFO_MASK (0xFFU)

#define	LPUART_PARAM_TXFIFO_SHIFT (0U)

#define	LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)

#define	LPUART_PARAM_RXFIFO_MASK (0xFF00U)

#define	LPUART_PARAM_RXFIFO_SHIFT (8U)

#define	LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)

GLOBAL - LPUART Global Register
#define	LPUART_GLOBAL_RST_MASK (0x2U)

#define	LPUART_GLOBAL_RST_SHIFT (1U)

#define	LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)

PINCFG - LPUART Pin Configuration Register
#define	LPUART_PINCFG_TRGSEL_MASK (0x3U)

#define	LPUART_PINCFG_TRGSEL_SHIFT (0U)

#define	LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)

BAUD - LPUART Baud Rate Register
#define	LPUART_BAUD_SBR_MASK (0x1FFFU)

#define	LPUART_BAUD_SBR_SHIFT (0U)

#define	LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)

#define	LPUART_BAUD_SBNS_MASK (0x2000U)

#define	LPUART_BAUD_SBNS_SHIFT (13U)

#define	LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)

#define	LPUART_BAUD_RXEDGIE_MASK (0x4000U)

#define	LPUART_BAUD_RXEDGIE_SHIFT (14U)

#define	LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)

#define	LPUART_BAUD_LBKDIE_MASK (0x8000U)

#define	LPUART_BAUD_LBKDIE_SHIFT (15U)

#define	LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)

#define	LPUART_BAUD_RESYNCDIS_MASK (0x10000U)

#define	LPUART_BAUD_RESYNCDIS_SHIFT (16U)

#define	LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)

#define	LPUART_BAUD_BOTHEDGE_MASK (0x20000U)

#define	LPUART_BAUD_BOTHEDGE_SHIFT (17U)

#define	LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)

#define	LPUART_BAUD_MATCFG_MASK (0xC0000U)

#define	LPUART_BAUD_MATCFG_SHIFT (18U)

#define	LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)

#define	LPUART_BAUD_RIDMAE_MASK (0x100000U)

#define	LPUART_BAUD_RIDMAE_SHIFT (20U)

#define	LPUART_BAUD_RIDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)

#define	LPUART_BAUD_RDMAE_MASK (0x200000U)

#define	LPUART_BAUD_RDMAE_SHIFT (21U)

#define	LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)

#define	LPUART_BAUD_TDMAE_MASK (0x800000U)

#define	LPUART_BAUD_TDMAE_SHIFT (23U)

#define	LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)

#define	LPUART_BAUD_OSR_MASK (0x1F000000U)

#define	LPUART_BAUD_OSR_SHIFT (24U)

#define	LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)

#define	LPUART_BAUD_M10_MASK (0x20000000U)

#define	LPUART_BAUD_M10_SHIFT (29U)

#define	LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)

#define	LPUART_BAUD_MAEN2_MASK (0x40000000U)

#define	LPUART_BAUD_MAEN2_SHIFT (30U)

#define	LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)

#define	LPUART_BAUD_MAEN1_MASK (0x80000000U)

#define	LPUART_BAUD_MAEN1_SHIFT (31U)

#define	LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)

STAT - LPUART Status Register
#define	LPUART_STAT_MA2F_MASK (0x4000U)

#define	LPUART_STAT_MA2F_SHIFT (14U)

#define	LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)

#define	LPUART_STAT_MA1F_MASK (0x8000U)

#define	LPUART_STAT_MA1F_SHIFT (15U)

#define	LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)

#define	LPUART_STAT_PF_MASK (0x10000U)

#define	LPUART_STAT_PF_SHIFT (16U)

#define	LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)

#define	LPUART_STAT_FE_MASK (0x20000U)

#define	LPUART_STAT_FE_SHIFT (17U)

#define	LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)

#define	LPUART_STAT_NF_MASK (0x40000U)

#define	LPUART_STAT_NF_SHIFT (18U)

#define	LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)

#define	LPUART_STAT_OR_MASK (0x80000U)

#define	LPUART_STAT_OR_SHIFT (19U)

#define	LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)

#define	LPUART_STAT_IDLE_MASK (0x100000U)

#define	LPUART_STAT_IDLE_SHIFT (20U)

#define	LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)

#define	LPUART_STAT_RDRF_MASK (0x200000U)

#define	LPUART_STAT_RDRF_SHIFT (21U)

#define	LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)

#define	LPUART_STAT_TC_MASK (0x400000U)

#define	LPUART_STAT_TC_SHIFT (22U)

#define	LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)

#define	LPUART_STAT_TDRE_MASK (0x800000U)

#define	LPUART_STAT_TDRE_SHIFT (23U)

#define	LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)

#define	LPUART_STAT_RAF_MASK (0x1000000U)

#define	LPUART_STAT_RAF_SHIFT (24U)

#define	LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)

#define	LPUART_STAT_LBKDE_MASK (0x2000000U)

#define	LPUART_STAT_LBKDE_SHIFT (25U)

#define	LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)

#define	LPUART_STAT_BRK13_MASK (0x4000000U)

#define	LPUART_STAT_BRK13_SHIFT (26U)

#define	LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)

#define	LPUART_STAT_RWUID_MASK (0x8000000U)

#define	LPUART_STAT_RWUID_SHIFT (27U)

#define	LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)

#define	LPUART_STAT_RXINV_MASK (0x10000000U)

#define	LPUART_STAT_RXINV_SHIFT (28U)

#define	LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)

#define	LPUART_STAT_MSBF_MASK (0x20000000U)

#define	LPUART_STAT_MSBF_SHIFT (29U)

#define	LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)

#define	LPUART_STAT_RXEDGIF_MASK (0x40000000U)

#define	LPUART_STAT_RXEDGIF_SHIFT (30U)

#define	LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)

#define	LPUART_STAT_LBKDIF_MASK (0x80000000U)

#define	LPUART_STAT_LBKDIF_SHIFT (31U)

#define	LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)

CTRL - LPUART Control Register
#define	LPUART_CTRL_PT_MASK (0x1U)

#define	LPUART_CTRL_PT_SHIFT (0U)

#define	LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)

#define	LPUART_CTRL_PE_MASK (0x2U)

#define	LPUART_CTRL_PE_SHIFT (1U)

#define	LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)

#define	LPUART_CTRL_ILT_MASK (0x4U)

#define	LPUART_CTRL_ILT_SHIFT (2U)

#define	LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)

#define	LPUART_CTRL_WAKE_MASK (0x8U)

#define	LPUART_CTRL_WAKE_SHIFT (3U)

#define	LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)

#define	LPUART_CTRL_M_MASK (0x10U)

#define	LPUART_CTRL_M_SHIFT (4U)

#define	LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)

#define	LPUART_CTRL_RSRC_MASK (0x20U)

#define	LPUART_CTRL_RSRC_SHIFT (5U)

#define	LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)

#define	LPUART_CTRL_DOZEEN_MASK (0x40U)

#define	LPUART_CTRL_DOZEEN_SHIFT (6U)

#define	LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)

#define	LPUART_CTRL_LOOPS_MASK (0x80U)

#define	LPUART_CTRL_LOOPS_SHIFT (7U)

#define	LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)

#define	LPUART_CTRL_IDLECFG_MASK (0x700U)

#define	LPUART_CTRL_IDLECFG_SHIFT (8U)

#define	LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)

#define	LPUART_CTRL_M7_MASK (0x800U)

#define	LPUART_CTRL_M7_SHIFT (11U)

#define	LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)

#define	LPUART_CTRL_MA2IE_MASK (0x4000U)

#define	LPUART_CTRL_MA2IE_SHIFT (14U)

#define	LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)

#define	LPUART_CTRL_MA1IE_MASK (0x8000U)

#define	LPUART_CTRL_MA1IE_SHIFT (15U)

#define	LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)

#define	LPUART_CTRL_SBK_MASK (0x10000U)

#define	LPUART_CTRL_SBK_SHIFT (16U)

#define	LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)

#define	LPUART_CTRL_RWU_MASK (0x20000U)

#define	LPUART_CTRL_RWU_SHIFT (17U)

#define	LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)

#define	LPUART_CTRL_RE_MASK (0x40000U)

#define	LPUART_CTRL_RE_SHIFT (18U)

#define	LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)

#define	LPUART_CTRL_TE_MASK (0x80000U)

#define	LPUART_CTRL_TE_SHIFT (19U)

#define	LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)

#define	LPUART_CTRL_ILIE_MASK (0x100000U)

#define	LPUART_CTRL_ILIE_SHIFT (20U)

#define	LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)

#define	LPUART_CTRL_RIE_MASK (0x200000U)

#define	LPUART_CTRL_RIE_SHIFT (21U)

#define	LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)

#define	LPUART_CTRL_TCIE_MASK (0x400000U)

#define	LPUART_CTRL_TCIE_SHIFT (22U)

#define	LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)

#define	LPUART_CTRL_TIE_MASK (0x800000U)

#define	LPUART_CTRL_TIE_SHIFT (23U)

#define	LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)

#define	LPUART_CTRL_PEIE_MASK (0x1000000U)

#define	LPUART_CTRL_PEIE_SHIFT (24U)

#define	LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)

#define	LPUART_CTRL_FEIE_MASK (0x2000000U)

#define	LPUART_CTRL_FEIE_SHIFT (25U)

#define	LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)

#define	LPUART_CTRL_NEIE_MASK (0x4000000U)

#define	LPUART_CTRL_NEIE_SHIFT (26U)

#define	LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)

#define	LPUART_CTRL_ORIE_MASK (0x8000000U)

#define	LPUART_CTRL_ORIE_SHIFT (27U)

#define	LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)

#define	LPUART_CTRL_TXINV_MASK (0x10000000U)

#define	LPUART_CTRL_TXINV_SHIFT (28U)

#define	LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)

#define	LPUART_CTRL_TXDIR_MASK (0x20000000U)

#define	LPUART_CTRL_TXDIR_SHIFT (29U)

#define	LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)

#define	LPUART_CTRL_R9T8_MASK (0x40000000U)

#define	LPUART_CTRL_R9T8_SHIFT (30U)

#define	LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)

#define	LPUART_CTRL_R8T9_MASK (0x80000000U)

#define	LPUART_CTRL_R8T9_SHIFT (31U)

#define	LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)

DATA - LPUART Data Register
#define	LPUART_DATA_R0T0_MASK (0x1U)

#define	LPUART_DATA_R0T0_SHIFT (0U)

#define	LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)

#define	LPUART_DATA_R1T1_MASK (0x2U)

#define	LPUART_DATA_R1T1_SHIFT (1U)

#define	LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)

#define	LPUART_DATA_R2T2_MASK (0x4U)

#define	LPUART_DATA_R2T2_SHIFT (2U)

#define	LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)

#define	LPUART_DATA_R3T3_MASK (0x8U)

#define	LPUART_DATA_R3T3_SHIFT (3U)

#define	LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)

#define	LPUART_DATA_R4T4_MASK (0x10U)

#define	LPUART_DATA_R4T4_SHIFT (4U)

#define	LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)

#define	LPUART_DATA_R5T5_MASK (0x20U)

#define	LPUART_DATA_R5T5_SHIFT (5U)

#define	LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)

#define	LPUART_DATA_R6T6_MASK (0x40U)

#define	LPUART_DATA_R6T6_SHIFT (6U)

#define	LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)

#define	LPUART_DATA_R7T7_MASK (0x80U)

#define	LPUART_DATA_R7T7_SHIFT (7U)

#define	LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)

#define	LPUART_DATA_R8T8_MASK (0x100U)

#define	LPUART_DATA_R8T8_SHIFT (8U)

#define	LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)

#define	LPUART_DATA_R9T9_MASK (0x200U)

#define	LPUART_DATA_R9T9_SHIFT (9U)

#define	LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)

#define	LPUART_DATA_IDLINE_MASK (0x800U)

#define	LPUART_DATA_IDLINE_SHIFT (11U)

#define	LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)

#define	LPUART_DATA_RXEMPT_MASK (0x1000U)

#define	LPUART_DATA_RXEMPT_SHIFT (12U)

#define	LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)

#define	LPUART_DATA_FRETSC_MASK (0x2000U)

#define	LPUART_DATA_FRETSC_SHIFT (13U)

#define	LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)

#define	LPUART_DATA_PARITYE_MASK (0x4000U)

#define	LPUART_DATA_PARITYE_SHIFT (14U)

#define	LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)

#define	LPUART_DATA_NOISY_MASK (0x8000U)

#define	LPUART_DATA_NOISY_SHIFT (15U)

#define	LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)

MATCH - LPUART Match Address Register
#define	LPUART_MATCH_MA1_MASK (0x3FFU)

#define	LPUART_MATCH_MA1_SHIFT (0U)

#define	LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)

#define	LPUART_MATCH_MA2_MASK (0x3FF0000U)

#define	LPUART_MATCH_MA2_SHIFT (16U)

#define	LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)

MODIR - LPUART Modem IrDA Register
#define	LPUART_MODIR_TXCTSE_MASK (0x1U)

#define	LPUART_MODIR_TXCTSE_SHIFT (0U)

#define	LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)

#define	LPUART_MODIR_TXRTSE_MASK (0x2U)

#define	LPUART_MODIR_TXRTSE_SHIFT (1U)

#define	LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)

#define	LPUART_MODIR_TXRTSPOL_MASK (0x4U)

#define	LPUART_MODIR_TXRTSPOL_SHIFT (2U)

#define	LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)

#define	LPUART_MODIR_RXRTSE_MASK (0x8U)

#define	LPUART_MODIR_RXRTSE_SHIFT (3U)

#define	LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)

#define	LPUART_MODIR_TXCTSC_MASK (0x10U)

#define	LPUART_MODIR_TXCTSC_SHIFT (4U)

#define	LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)

#define	LPUART_MODIR_TXCTSSRC_MASK (0x20U)

#define	LPUART_MODIR_TXCTSSRC_SHIFT (5U)

#define	LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)

#define	LPUART_MODIR_RTSWATER_MASK (0x300U)

#define	LPUART_MODIR_RTSWATER_SHIFT (8U)

#define	LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)

#define	LPUART_MODIR_TNP_MASK (0x30000U)

#define	LPUART_MODIR_TNP_SHIFT (16U)

#define	LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)

#define	LPUART_MODIR_IREN_MASK (0x40000U)

#define	LPUART_MODIR_IREN_SHIFT (18U)

#define	LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)

FIFO - LPUART FIFO Register
#define	LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)

#define	LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)

#define	LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)

#define	LPUART_FIFO_RXFE_MASK (0x8U)

#define	LPUART_FIFO_RXFE_SHIFT (3U)

#define	LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)

#define	LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)

#define	LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)

#define	LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)

#define	LPUART_FIFO_TXFE_MASK (0x80U)

#define	LPUART_FIFO_TXFE_SHIFT (7U)

#define	LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)

#define	LPUART_FIFO_RXUFE_MASK (0x100U)

#define	LPUART_FIFO_RXUFE_SHIFT (8U)

#define	LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)

#define	LPUART_FIFO_TXOFE_MASK (0x200U)

#define	LPUART_FIFO_TXOFE_SHIFT (9U)

#define	LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)

#define	LPUART_FIFO_RXIDEN_MASK (0x1C00U)

#define	LPUART_FIFO_RXIDEN_SHIFT (10U)

#define	LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)

#define	LPUART_FIFO_RXFLUSH_MASK (0x4000U)

#define	LPUART_FIFO_RXFLUSH_SHIFT (14U)

#define	LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)

#define	LPUART_FIFO_TXFLUSH_MASK (0x8000U)

#define	LPUART_FIFO_TXFLUSH_SHIFT (15U)

#define	LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)

#define	LPUART_FIFO_RXUF_MASK (0x10000U)

#define	LPUART_FIFO_RXUF_SHIFT (16U)

#define	LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)

#define	LPUART_FIFO_TXOF_MASK (0x20000U)

#define	LPUART_FIFO_TXOF_SHIFT (17U)

#define	LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)

#define	LPUART_FIFO_RXEMPT_MASK (0x400000U)

#define	LPUART_FIFO_RXEMPT_SHIFT (22U)

#define	LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)

#define	LPUART_FIFO_TXEMPT_MASK (0x800000U)

#define	LPUART_FIFO_TXEMPT_SHIFT (23U)

#define	LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)

WATER - LPUART Watermark Register
#define	LPUART_WATER_TXWATER_MASK (0x3U)

#define	LPUART_WATER_TXWATER_SHIFT (0U)

#define	LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)

#define	LPUART_WATER_TXCOUNT_MASK (0x700U)

#define	LPUART_WATER_TXCOUNT_SHIFT (8U)

#define	LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)

#define	LPUART_WATER_RXWATER_MASK (0x30000U)

#define	LPUART_WATER_RXWATER_SHIFT (16U)

#define	LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)

#define	LPUART_WATER_RXCOUNT_MASK (0x7000000U)

#define	LPUART_WATER_RXCOUNT_SHIFT (24U)

#define	LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)

VERID - Version ID Register
#define	LPUART_VERID_FEATURE_MASK (0xFFFFU)

#define	LPUART_VERID_FEATURE_SHIFT (0U)

#define	LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)

#define	LPUART_VERID_MINOR_MASK (0xFF0000U)

#define	LPUART_VERID_MINOR_SHIFT (16U)

#define	LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)

#define	LPUART_VERID_MAJOR_MASK (0xFF000000U)

#define	LPUART_VERID_MAJOR_SHIFT (24U)

#define	LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)

PARAM - Parameter Register
#define	LPUART_PARAM_TXFIFO_MASK (0xFFU)

#define	LPUART_PARAM_TXFIFO_SHIFT (0U)

#define	LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)

#define	LPUART_PARAM_RXFIFO_MASK (0xFF00U)

#define	LPUART_PARAM_RXFIFO_SHIFT (8U)

#define	LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)

GLOBAL - LPUART Global Register
#define	LPUART_GLOBAL_RST_MASK (0x2U)

#define	LPUART_GLOBAL_RST_SHIFT (1U)

#define	LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)

PINCFG - LPUART Pin Configuration Register
#define	LPUART_PINCFG_TRGSEL_MASK (0x3U)

#define	LPUART_PINCFG_TRGSEL_SHIFT (0U)

#define	LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)

BAUD - LPUART Baud Rate Register
#define	LPUART_BAUD_SBR_MASK (0x1FFFU)

#define	LPUART_BAUD_SBR_SHIFT (0U)

#define	LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)

#define	LPUART_BAUD_SBNS_MASK (0x2000U)

#define	LPUART_BAUD_SBNS_SHIFT (13U)

#define	LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)

#define	LPUART_BAUD_RXEDGIE_MASK (0x4000U)

#define	LPUART_BAUD_RXEDGIE_SHIFT (14U)

#define	LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)

#define	LPUART_BAUD_LBKDIE_MASK (0x8000U)

#define	LPUART_BAUD_LBKDIE_SHIFT (15U)

#define	LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)

#define	LPUART_BAUD_RESYNCDIS_MASK (0x10000U)

#define	LPUART_BAUD_RESYNCDIS_SHIFT (16U)

#define	LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)

#define	LPUART_BAUD_BOTHEDGE_MASK (0x20000U)

#define	LPUART_BAUD_BOTHEDGE_SHIFT (17U)

#define	LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)

#define	LPUART_BAUD_MATCFG_MASK (0xC0000U)

#define	LPUART_BAUD_MATCFG_SHIFT (18U)

#define	LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)

#define	LPUART_BAUD_RDMAE_MASK (0x200000U)

#define	LPUART_BAUD_RDMAE_SHIFT (21U)

#define	LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)

#define	LPUART_BAUD_TDMAE_MASK (0x800000U)

#define	LPUART_BAUD_TDMAE_SHIFT (23U)

#define	LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)

#define	LPUART_BAUD_OSR_MASK (0x1F000000U)

#define	LPUART_BAUD_OSR_SHIFT (24U)

#define	LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)

#define	LPUART_BAUD_M10_MASK (0x20000000U)

#define	LPUART_BAUD_M10_SHIFT (29U)

#define	LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)

#define	LPUART_BAUD_MAEN2_MASK (0x40000000U)

#define	LPUART_BAUD_MAEN2_SHIFT (30U)

#define	LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)

#define	LPUART_BAUD_MAEN1_MASK (0x80000000U)

#define	LPUART_BAUD_MAEN1_SHIFT (31U)

#define	LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)

STAT - LPUART Status Register
#define	LPUART_STAT_MA2F_MASK (0x4000U)

#define	LPUART_STAT_MA2F_SHIFT (14U)

#define	LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)

#define	LPUART_STAT_MA1F_MASK (0x8000U)

#define	LPUART_STAT_MA1F_SHIFT (15U)

#define	LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)

#define	LPUART_STAT_PF_MASK (0x10000U)

#define	LPUART_STAT_PF_SHIFT (16U)

#define	LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)

#define	LPUART_STAT_FE_MASK (0x20000U)

#define	LPUART_STAT_FE_SHIFT (17U)

#define	LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)

#define	LPUART_STAT_NF_MASK (0x40000U)

#define	LPUART_STAT_NF_SHIFT (18U)

#define	LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)

#define	LPUART_STAT_OR_MASK (0x80000U)

#define	LPUART_STAT_OR_SHIFT (19U)

#define	LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)

#define	LPUART_STAT_IDLE_MASK (0x100000U)

#define	LPUART_STAT_IDLE_SHIFT (20U)

#define	LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)

#define	LPUART_STAT_RDRF_MASK (0x200000U)

#define	LPUART_STAT_RDRF_SHIFT (21U)

#define	LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)

#define	LPUART_STAT_TC_MASK (0x400000U)

#define	LPUART_STAT_TC_SHIFT (22U)

#define	LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)

#define	LPUART_STAT_TDRE_MASK (0x800000U)

#define	LPUART_STAT_TDRE_SHIFT (23U)

#define	LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)

#define	LPUART_STAT_RAF_MASK (0x1000000U)

#define	LPUART_STAT_RAF_SHIFT (24U)

#define	LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)

#define	LPUART_STAT_LBKDE_MASK (0x2000000U)

#define	LPUART_STAT_LBKDE_SHIFT (25U)

#define	LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)

#define	LPUART_STAT_BRK13_MASK (0x4000000U)

#define	LPUART_STAT_BRK13_SHIFT (26U)

#define	LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)

#define	LPUART_STAT_RWUID_MASK (0x8000000U)

#define	LPUART_STAT_RWUID_SHIFT (27U)

#define	LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)

#define	LPUART_STAT_RXINV_MASK (0x10000000U)

#define	LPUART_STAT_RXINV_SHIFT (28U)

#define	LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)

#define	LPUART_STAT_MSBF_MASK (0x20000000U)

#define	LPUART_STAT_MSBF_SHIFT (29U)

#define	LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)

#define	LPUART_STAT_RXEDGIF_MASK (0x40000000U)

#define	LPUART_STAT_RXEDGIF_SHIFT (30U)

#define	LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)

#define	LPUART_STAT_LBKDIF_MASK (0x80000000U)

#define	LPUART_STAT_LBKDIF_SHIFT (31U)

#define	LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)

CTRL - LPUART Control Register
#define	LPUART_CTRL_PT_MASK (0x1U)

#define	LPUART_CTRL_PT_SHIFT (0U)

#define	LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)

#define	LPUART_CTRL_PE_MASK (0x2U)

#define	LPUART_CTRL_PE_SHIFT (1U)

#define	LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)

#define	LPUART_CTRL_ILT_MASK (0x4U)

#define	LPUART_CTRL_ILT_SHIFT (2U)

#define	LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)

#define	LPUART_CTRL_WAKE_MASK (0x8U)

#define	LPUART_CTRL_WAKE_SHIFT (3U)

#define	LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)

#define	LPUART_CTRL_M_MASK (0x10U)

#define	LPUART_CTRL_M_SHIFT (4U)

#define	LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)

#define	LPUART_CTRL_RSRC_MASK (0x20U)

#define	LPUART_CTRL_RSRC_SHIFT (5U)

#define	LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)

#define	LPUART_CTRL_DOZEEN_MASK (0x40U)

#define	LPUART_CTRL_DOZEEN_SHIFT (6U)

#define	LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)

#define	LPUART_CTRL_LOOPS_MASK (0x80U)

#define	LPUART_CTRL_LOOPS_SHIFT (7U)

#define	LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)

#define	LPUART_CTRL_IDLECFG_MASK (0x700U)

#define	LPUART_CTRL_IDLECFG_SHIFT (8U)

#define	LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)

#define	LPUART_CTRL_M7_MASK (0x800U)

#define	LPUART_CTRL_M7_SHIFT (11U)

#define	LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)

#define	LPUART_CTRL_MA2IE_MASK (0x4000U)

#define	LPUART_CTRL_MA2IE_SHIFT (14U)

#define	LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)

#define	LPUART_CTRL_MA1IE_MASK (0x8000U)

#define	LPUART_CTRL_MA1IE_SHIFT (15U)

#define	LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)

#define	LPUART_CTRL_SBK_MASK (0x10000U)

#define	LPUART_CTRL_SBK_SHIFT (16U)

#define	LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)

#define	LPUART_CTRL_RWU_MASK (0x20000U)

#define	LPUART_CTRL_RWU_SHIFT (17U)

#define	LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)

#define	LPUART_CTRL_RE_MASK (0x40000U)

#define	LPUART_CTRL_RE_SHIFT (18U)

#define	LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)

#define	LPUART_CTRL_TE_MASK (0x80000U)

#define	LPUART_CTRL_TE_SHIFT (19U)

#define	LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)

#define	LPUART_CTRL_ILIE_MASK (0x100000U)

#define	LPUART_CTRL_ILIE_SHIFT (20U)

#define	LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)

#define	LPUART_CTRL_RIE_MASK (0x200000U)

#define	LPUART_CTRL_RIE_SHIFT (21U)

#define	LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)

#define	LPUART_CTRL_TCIE_MASK (0x400000U)

#define	LPUART_CTRL_TCIE_SHIFT (22U)

#define	LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)

#define	LPUART_CTRL_TIE_MASK (0x800000U)

#define	LPUART_CTRL_TIE_SHIFT (23U)

#define	LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)

#define	LPUART_CTRL_PEIE_MASK (0x1000000U)

#define	LPUART_CTRL_PEIE_SHIFT (24U)

#define	LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)

#define	LPUART_CTRL_FEIE_MASK (0x2000000U)

#define	LPUART_CTRL_FEIE_SHIFT (25U)

#define	LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)

#define	LPUART_CTRL_NEIE_MASK (0x4000000U)

#define	LPUART_CTRL_NEIE_SHIFT (26U)

#define	LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)

#define	LPUART_CTRL_ORIE_MASK (0x8000000U)

#define	LPUART_CTRL_ORIE_SHIFT (27U)

#define	LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)

#define	LPUART_CTRL_TXINV_MASK (0x10000000U)

#define	LPUART_CTRL_TXINV_SHIFT (28U)

#define	LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)

#define	LPUART_CTRL_TXDIR_MASK (0x20000000U)

#define	LPUART_CTRL_TXDIR_SHIFT (29U)

#define	LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)

#define	LPUART_CTRL_R9T8_MASK (0x40000000U)

#define	LPUART_CTRL_R9T8_SHIFT (30U)

#define	LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)

#define	LPUART_CTRL_R8T9_MASK (0x80000000U)

#define	LPUART_CTRL_R8T9_SHIFT (31U)

#define	LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)

DATA - LPUART Data Register
#define	LPUART_DATA_R0T0_MASK (0x1U)

#define	LPUART_DATA_R0T0_SHIFT (0U)

#define	LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)

#define	LPUART_DATA_R1T1_MASK (0x2U)

#define	LPUART_DATA_R1T1_SHIFT (1U)

#define	LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)

#define	LPUART_DATA_R2T2_MASK (0x4U)

#define	LPUART_DATA_R2T2_SHIFT (2U)

#define	LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)

#define	LPUART_DATA_R3T3_MASK (0x8U)

#define	LPUART_DATA_R3T3_SHIFT (3U)

#define	LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)

#define	LPUART_DATA_R4T4_MASK (0x10U)

#define	LPUART_DATA_R4T4_SHIFT (4U)

#define	LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)

#define	LPUART_DATA_R5T5_MASK (0x20U)

#define	LPUART_DATA_R5T5_SHIFT (5U)

#define	LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)

#define	LPUART_DATA_R6T6_MASK (0x40U)

#define	LPUART_DATA_R6T6_SHIFT (6U)

#define	LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)

#define	LPUART_DATA_R7T7_MASK (0x80U)

#define	LPUART_DATA_R7T7_SHIFT (7U)

#define	LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)

#define	LPUART_DATA_R8T8_MASK (0x100U)

#define	LPUART_DATA_R8T8_SHIFT (8U)

#define	LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)

#define	LPUART_DATA_R9T9_MASK (0x200U)

#define	LPUART_DATA_R9T9_SHIFT (9U)

#define	LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)

#define	LPUART_DATA_IDLINE_MASK (0x800U)

#define	LPUART_DATA_IDLINE_SHIFT (11U)

#define	LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)

#define	LPUART_DATA_RXEMPT_MASK (0x1000U)

#define	LPUART_DATA_RXEMPT_SHIFT (12U)

#define	LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)

#define	LPUART_DATA_FRETSC_MASK (0x2000U)

#define	LPUART_DATA_FRETSC_SHIFT (13U)

#define	LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)

#define	LPUART_DATA_PARITYE_MASK (0x4000U)

#define	LPUART_DATA_PARITYE_SHIFT (14U)

#define	LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)

#define	LPUART_DATA_NOISY_MASK (0x8000U)

#define	LPUART_DATA_NOISY_SHIFT (15U)

#define	LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)

MATCH - LPUART Match Address Register
#define	LPUART_MATCH_MA1_MASK (0x3FFU)

#define	LPUART_MATCH_MA1_SHIFT (0U)

#define	LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)

#define	LPUART_MATCH_MA2_MASK (0x3FF0000U)

#define	LPUART_MATCH_MA2_SHIFT (16U)

#define	LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)

MODIR - LPUART Modem IrDA Register
#define	LPUART_MODIR_TXCTSE_MASK (0x1U)

#define	LPUART_MODIR_TXCTSE_SHIFT (0U)

#define	LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)

#define	LPUART_MODIR_TXRTSE_MASK (0x2U)

#define	LPUART_MODIR_TXRTSE_SHIFT (1U)

#define	LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)

#define	LPUART_MODIR_TXRTSPOL_MASK (0x4U)

#define	LPUART_MODIR_TXRTSPOL_SHIFT (2U)

#define	LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)

#define	LPUART_MODIR_RXRTSE_MASK (0x8U)

#define	LPUART_MODIR_RXRTSE_SHIFT (3U)

#define	LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)

#define	LPUART_MODIR_TXCTSC_MASK (0x10U)

#define	LPUART_MODIR_TXCTSC_SHIFT (4U)

#define	LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)

#define	LPUART_MODIR_TXCTSSRC_MASK (0x20U)

#define	LPUART_MODIR_TXCTSSRC_SHIFT (5U)

#define	LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)

#define	LPUART_MODIR_RTSWATER_MASK (0x300U)

#define	LPUART_MODIR_RTSWATER_SHIFT (8U)

#define	LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)

#define	LPUART_MODIR_TNP_MASK (0x30000U)

#define	LPUART_MODIR_TNP_SHIFT (16U)

#define	LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)

#define	LPUART_MODIR_IREN_MASK (0x40000U)

#define	LPUART_MODIR_IREN_SHIFT (18U)

#define	LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)

FIFO - LPUART FIFO Register
#define	LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)

#define	LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)

#define	LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)

#define	LPUART_FIFO_RXFE_MASK (0x8U)

#define	LPUART_FIFO_RXFE_SHIFT (3U)

#define	LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)

#define	LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)

#define	LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)

#define	LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)

#define	LPUART_FIFO_TXFE_MASK (0x80U)

#define	LPUART_FIFO_TXFE_SHIFT (7U)

#define	LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)

#define	LPUART_FIFO_RXUFE_MASK (0x100U)

#define	LPUART_FIFO_RXUFE_SHIFT (8U)

#define	LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)

#define	LPUART_FIFO_TXOFE_MASK (0x200U)

#define	LPUART_FIFO_TXOFE_SHIFT (9U)

#define	LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)

#define	LPUART_FIFO_RXIDEN_MASK (0x1C00U)

#define	LPUART_FIFO_RXIDEN_SHIFT (10U)

#define	LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)

#define	LPUART_FIFO_RXFLUSH_MASK (0x4000U)

#define	LPUART_FIFO_RXFLUSH_SHIFT (14U)

#define	LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)

#define	LPUART_FIFO_TXFLUSH_MASK (0x8000U)

#define	LPUART_FIFO_TXFLUSH_SHIFT (15U)

#define	LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)

#define	LPUART_FIFO_RXUF_MASK (0x10000U)

#define	LPUART_FIFO_RXUF_SHIFT (16U)

#define	LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)

#define	LPUART_FIFO_TXOF_MASK (0x20000U)

#define	LPUART_FIFO_TXOF_SHIFT (17U)

#define	LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)

#define	LPUART_FIFO_RXEMPT_MASK (0x400000U)

#define	LPUART_FIFO_RXEMPT_SHIFT (22U)

#define	LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)

#define	LPUART_FIFO_TXEMPT_MASK (0x800000U)

#define	LPUART_FIFO_TXEMPT_SHIFT (23U)

#define	LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)

WATER - LPUART Watermark Register
#define	LPUART_WATER_TXWATER_MASK (0x3U)

#define	LPUART_WATER_TXWATER_SHIFT (0U)

#define	LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)

#define	LPUART_WATER_TXCOUNT_MASK (0x700U)

#define	LPUART_WATER_TXCOUNT_SHIFT (8U)

#define	LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)

#define	LPUART_WATER_RXWATER_MASK (0x30000U)

#define	LPUART_WATER_RXWATER_SHIFT (16U)

#define	LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)

#define	LPUART_WATER_RXCOUNT_MASK (0x7000000U)

#define	LPUART_WATER_RXCOUNT_SHIFT (24U)

#define	LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)

VERID - Version ID Register
#define	LPUART_VERID_FEATURE_MASK (0xFFFFU)

#define	LPUART_VERID_FEATURE_SHIFT (0U)

#define	LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)

#define	LPUART_VERID_MINOR_MASK (0xFF0000U)

#define	LPUART_VERID_MINOR_SHIFT (16U)

#define	LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)

#define	LPUART_VERID_MAJOR_MASK (0xFF000000U)

#define	LPUART_VERID_MAJOR_SHIFT (24U)

#define	LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)

PARAM - Parameter Register
#define	LPUART_PARAM_TXFIFO_MASK (0xFFU)

#define	LPUART_PARAM_TXFIFO_SHIFT (0U)

#define	LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)

#define	LPUART_PARAM_RXFIFO_MASK (0xFF00U)

#define	LPUART_PARAM_RXFIFO_SHIFT (8U)

#define	LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)

GLOBAL - LPUART Global Register
#define	LPUART_GLOBAL_RST_MASK (0x2U)

#define	LPUART_GLOBAL_RST_SHIFT (1U)

#define	LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)

PINCFG - LPUART Pin Configuration Register
#define	LPUART_PINCFG_TRGSEL_MASK (0x3U)

#define	LPUART_PINCFG_TRGSEL_SHIFT (0U)

#define	LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)

BAUD - LPUART Baud Rate Register
#define	LPUART_BAUD_SBR_MASK (0x1FFFU)

#define	LPUART_BAUD_SBR_SHIFT (0U)

#define	LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)

#define	LPUART_BAUD_SBNS_MASK (0x2000U)

#define	LPUART_BAUD_SBNS_SHIFT (13U)

#define	LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)

#define	LPUART_BAUD_RXEDGIE_MASK (0x4000U)

#define	LPUART_BAUD_RXEDGIE_SHIFT (14U)

#define	LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)

#define	LPUART_BAUD_LBKDIE_MASK (0x8000U)

#define	LPUART_BAUD_LBKDIE_SHIFT (15U)

#define	LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)

#define	LPUART_BAUD_RESYNCDIS_MASK (0x10000U)

#define	LPUART_BAUD_RESYNCDIS_SHIFT (16U)

#define	LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)

#define	LPUART_BAUD_BOTHEDGE_MASK (0x20000U)

#define	LPUART_BAUD_BOTHEDGE_SHIFT (17U)

#define	LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)

#define	LPUART_BAUD_MATCFG_MASK (0xC0000U)

#define	LPUART_BAUD_MATCFG_SHIFT (18U)

#define	LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)

#define	LPUART_BAUD_RDMAE_MASK (0x200000U)

#define	LPUART_BAUD_RDMAE_SHIFT (21U)

#define	LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)

#define	LPUART_BAUD_TDMAE_MASK (0x800000U)

#define	LPUART_BAUD_TDMAE_SHIFT (23U)

#define	LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)

#define	LPUART_BAUD_OSR_MASK (0x1F000000U)

#define	LPUART_BAUD_OSR_SHIFT (24U)

#define	LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)

#define	LPUART_BAUD_M10_MASK (0x20000000U)

#define	LPUART_BAUD_M10_SHIFT (29U)

#define	LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)

#define	LPUART_BAUD_MAEN2_MASK (0x40000000U)

#define	LPUART_BAUD_MAEN2_SHIFT (30U)

#define	LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)

#define	LPUART_BAUD_MAEN1_MASK (0x80000000U)

#define	LPUART_BAUD_MAEN1_SHIFT (31U)

#define	LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)

STAT - LPUART Status Register
#define	LPUART_STAT_MA2F_MASK (0x4000U)

#define	LPUART_STAT_MA2F_SHIFT (14U)

#define	LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)

#define	LPUART_STAT_MA1F_MASK (0x8000U)

#define	LPUART_STAT_MA1F_SHIFT (15U)

#define	LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)

#define	LPUART_STAT_PF_MASK (0x10000U)

#define	LPUART_STAT_PF_SHIFT (16U)

#define	LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)

#define	LPUART_STAT_FE_MASK (0x20000U)

#define	LPUART_STAT_FE_SHIFT (17U)

#define	LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)

#define	LPUART_STAT_NF_MASK (0x40000U)

#define	LPUART_STAT_NF_SHIFT (18U)

#define	LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)

#define	LPUART_STAT_OR_MASK (0x80000U)

#define	LPUART_STAT_OR_SHIFT (19U)

#define	LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)

#define	LPUART_STAT_IDLE_MASK (0x100000U)

#define	LPUART_STAT_IDLE_SHIFT (20U)

#define	LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)

#define	LPUART_STAT_RDRF_MASK (0x200000U)

#define	LPUART_STAT_RDRF_SHIFT (21U)

#define	LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)

#define	LPUART_STAT_TC_MASK (0x400000U)

#define	LPUART_STAT_TC_SHIFT (22U)

#define	LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)

#define	LPUART_STAT_TDRE_MASK (0x800000U)

#define	LPUART_STAT_TDRE_SHIFT (23U)

#define	LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)

#define	LPUART_STAT_RAF_MASK (0x1000000U)

#define	LPUART_STAT_RAF_SHIFT (24U)

#define	LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)

#define	LPUART_STAT_LBKDE_MASK (0x2000000U)

#define	LPUART_STAT_LBKDE_SHIFT (25U)

#define	LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)

#define	LPUART_STAT_BRK13_MASK (0x4000000U)

#define	LPUART_STAT_BRK13_SHIFT (26U)

#define	LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)

#define	LPUART_STAT_RWUID_MASK (0x8000000U)

#define	LPUART_STAT_RWUID_SHIFT (27U)

#define	LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)

#define	LPUART_STAT_RXINV_MASK (0x10000000U)

#define	LPUART_STAT_RXINV_SHIFT (28U)

#define	LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)

#define	LPUART_STAT_MSBF_MASK (0x20000000U)

#define	LPUART_STAT_MSBF_SHIFT (29U)

#define	LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)

#define	LPUART_STAT_RXEDGIF_MASK (0x40000000U)

#define	LPUART_STAT_RXEDGIF_SHIFT (30U)

#define	LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)

#define	LPUART_STAT_LBKDIF_MASK (0x80000000U)

#define	LPUART_STAT_LBKDIF_SHIFT (31U)

#define	LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)

CTRL - LPUART Control Register
#define	LPUART_CTRL_PT_MASK (0x1U)

#define	LPUART_CTRL_PT_SHIFT (0U)

#define	LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)

#define	LPUART_CTRL_PE_MASK (0x2U)

#define	LPUART_CTRL_PE_SHIFT (1U)

#define	LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)

#define	LPUART_CTRL_ILT_MASK (0x4U)

#define	LPUART_CTRL_ILT_SHIFT (2U)

#define	LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)

#define	LPUART_CTRL_WAKE_MASK (0x8U)

#define	LPUART_CTRL_WAKE_SHIFT (3U)

#define	LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)

#define	LPUART_CTRL_M_MASK (0x10U)

#define	LPUART_CTRL_M_SHIFT (4U)

#define	LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)

#define	LPUART_CTRL_RSRC_MASK (0x20U)

#define	LPUART_CTRL_RSRC_SHIFT (5U)

#define	LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)

#define	LPUART_CTRL_DOZEEN_MASK (0x40U)

#define	LPUART_CTRL_DOZEEN_SHIFT (6U)

#define	LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)

#define	LPUART_CTRL_LOOPS_MASK (0x80U)

#define	LPUART_CTRL_LOOPS_SHIFT (7U)

#define	LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)

#define	LPUART_CTRL_IDLECFG_MASK (0x700U)

#define	LPUART_CTRL_IDLECFG_SHIFT (8U)

#define	LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)

#define	LPUART_CTRL_M7_MASK (0x800U)

#define	LPUART_CTRL_M7_SHIFT (11U)

#define	LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)

#define	LPUART_CTRL_MA2IE_MASK (0x4000U)

#define	LPUART_CTRL_MA2IE_SHIFT (14U)

#define	LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)

#define	LPUART_CTRL_MA1IE_MASK (0x8000U)

#define	LPUART_CTRL_MA1IE_SHIFT (15U)

#define	LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)

#define	LPUART_CTRL_SBK_MASK (0x10000U)

#define	LPUART_CTRL_SBK_SHIFT (16U)

#define	LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)

#define	LPUART_CTRL_RWU_MASK (0x20000U)

#define	LPUART_CTRL_RWU_SHIFT (17U)

#define	LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)

#define	LPUART_CTRL_RE_MASK (0x40000U)

#define	LPUART_CTRL_RE_SHIFT (18U)

#define	LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)

#define	LPUART_CTRL_TE_MASK (0x80000U)

#define	LPUART_CTRL_TE_SHIFT (19U)

#define	LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)

#define	LPUART_CTRL_ILIE_MASK (0x100000U)

#define	LPUART_CTRL_ILIE_SHIFT (20U)

#define	LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)

#define	LPUART_CTRL_RIE_MASK (0x200000U)

#define	LPUART_CTRL_RIE_SHIFT (21U)

#define	LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)

#define	LPUART_CTRL_TCIE_MASK (0x400000U)

#define	LPUART_CTRL_TCIE_SHIFT (22U)

#define	LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)

#define	LPUART_CTRL_TIE_MASK (0x800000U)

#define	LPUART_CTRL_TIE_SHIFT (23U)

#define	LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)

#define	LPUART_CTRL_PEIE_MASK (0x1000000U)

#define	LPUART_CTRL_PEIE_SHIFT (24U)

#define	LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)

#define	LPUART_CTRL_FEIE_MASK (0x2000000U)

#define	LPUART_CTRL_FEIE_SHIFT (25U)

#define	LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)

#define	LPUART_CTRL_NEIE_MASK (0x4000000U)

#define	LPUART_CTRL_NEIE_SHIFT (26U)

#define	LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)

#define	LPUART_CTRL_ORIE_MASK (0x8000000U)

#define	LPUART_CTRL_ORIE_SHIFT (27U)

#define	LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)

#define	LPUART_CTRL_TXINV_MASK (0x10000000U)

#define	LPUART_CTRL_TXINV_SHIFT (28U)

#define	LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)

#define	LPUART_CTRL_TXDIR_MASK (0x20000000U)

#define	LPUART_CTRL_TXDIR_SHIFT (29U)

#define	LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)

#define	LPUART_CTRL_R9T8_MASK (0x40000000U)

#define	LPUART_CTRL_R9T8_SHIFT (30U)

#define	LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)

#define	LPUART_CTRL_R8T9_MASK (0x80000000U)

#define	LPUART_CTRL_R8T9_SHIFT (31U)

#define	LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)

DATA - LPUART Data Register
#define	LPUART_DATA_R0T0_MASK (0x1U)

#define	LPUART_DATA_R0T0_SHIFT (0U)

#define	LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)

#define	LPUART_DATA_R1T1_MASK (0x2U)

#define	LPUART_DATA_R1T1_SHIFT (1U)

#define	LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)

#define	LPUART_DATA_R2T2_MASK (0x4U)

#define	LPUART_DATA_R2T2_SHIFT (2U)

#define	LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)

#define	LPUART_DATA_R3T3_MASK (0x8U)

#define	LPUART_DATA_R3T3_SHIFT (3U)

#define	LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)

#define	LPUART_DATA_R4T4_MASK (0x10U)

#define	LPUART_DATA_R4T4_SHIFT (4U)

#define	LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)

#define	LPUART_DATA_R5T5_MASK (0x20U)

#define	LPUART_DATA_R5T5_SHIFT (5U)

#define	LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)

#define	LPUART_DATA_R6T6_MASK (0x40U)

#define	LPUART_DATA_R6T6_SHIFT (6U)

#define	LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)

#define	LPUART_DATA_R7T7_MASK (0x80U)

#define	LPUART_DATA_R7T7_SHIFT (7U)

#define	LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)

#define	LPUART_DATA_R8T8_MASK (0x100U)

#define	LPUART_DATA_R8T8_SHIFT (8U)

#define	LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)

#define	LPUART_DATA_R9T9_MASK (0x200U)

#define	LPUART_DATA_R9T9_SHIFT (9U)

#define	LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)

#define	LPUART_DATA_IDLINE_MASK (0x800U)

#define	LPUART_DATA_IDLINE_SHIFT (11U)

#define	LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)

#define	LPUART_DATA_RXEMPT_MASK (0x1000U)

#define	LPUART_DATA_RXEMPT_SHIFT (12U)

#define	LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)

#define	LPUART_DATA_FRETSC_MASK (0x2000U)

#define	LPUART_DATA_FRETSC_SHIFT (13U)

#define	LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)

#define	LPUART_DATA_PARITYE_MASK (0x4000U)

#define	LPUART_DATA_PARITYE_SHIFT (14U)

#define	LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)

#define	LPUART_DATA_NOISY_MASK (0x8000U)

#define	LPUART_DATA_NOISY_SHIFT (15U)

#define	LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)

MATCH - LPUART Match Address Register
#define	LPUART_MATCH_MA1_MASK (0x3FFU)

#define	LPUART_MATCH_MA1_SHIFT (0U)

#define	LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)

#define	LPUART_MATCH_MA2_MASK (0x3FF0000U)

#define	LPUART_MATCH_MA2_SHIFT (16U)

#define	LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)

MODIR - LPUART Modem IrDA Register
#define	LPUART_MODIR_TXCTSE_MASK (0x1U)

#define	LPUART_MODIR_TXCTSE_SHIFT (0U)

#define	LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)

#define	LPUART_MODIR_TXRTSE_MASK (0x2U)

#define	LPUART_MODIR_TXRTSE_SHIFT (1U)

#define	LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)

#define	LPUART_MODIR_TXRTSPOL_MASK (0x4U)

#define	LPUART_MODIR_TXRTSPOL_SHIFT (2U)

#define	LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)

#define	LPUART_MODIR_RXRTSE_MASK (0x8U)

#define	LPUART_MODIR_RXRTSE_SHIFT (3U)

#define	LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)

#define	LPUART_MODIR_TXCTSC_MASK (0x10U)

#define	LPUART_MODIR_TXCTSC_SHIFT (4U)

#define	LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)

#define	LPUART_MODIR_TXCTSSRC_MASK (0x20U)

#define	LPUART_MODIR_TXCTSSRC_SHIFT (5U)

#define	LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)

#define	LPUART_MODIR_RTSWATER_MASK (0x300U)

#define	LPUART_MODIR_RTSWATER_SHIFT (8U)

#define	LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)

#define	LPUART_MODIR_TNP_MASK (0x30000U)

#define	LPUART_MODIR_TNP_SHIFT (16U)

#define	LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)

#define	LPUART_MODIR_IREN_MASK (0x40000U)

#define	LPUART_MODIR_IREN_SHIFT (18U)

#define	LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)

FIFO - LPUART FIFO Register
#define	LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)

#define	LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)

#define	LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)

#define	LPUART_FIFO_RXFE_MASK (0x8U)

#define	LPUART_FIFO_RXFE_SHIFT (3U)

#define	LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)

#define	LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)

#define	LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)

#define	LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)

#define	LPUART_FIFO_TXFE_MASK (0x80U)

#define	LPUART_FIFO_TXFE_SHIFT (7U)

#define	LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)

#define	LPUART_FIFO_RXUFE_MASK (0x100U)

#define	LPUART_FIFO_RXUFE_SHIFT (8U)

#define	LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)

#define	LPUART_FIFO_TXOFE_MASK (0x200U)

#define	LPUART_FIFO_TXOFE_SHIFT (9U)

#define	LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)

#define	LPUART_FIFO_RXIDEN_MASK (0x1C00U)

#define	LPUART_FIFO_RXIDEN_SHIFT (10U)

#define	LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)

#define	LPUART_FIFO_RXFLUSH_MASK (0x4000U)

#define	LPUART_FIFO_RXFLUSH_SHIFT (14U)

#define	LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)

#define	LPUART_FIFO_TXFLUSH_MASK (0x8000U)

#define	LPUART_FIFO_TXFLUSH_SHIFT (15U)

#define	LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)

#define	LPUART_FIFO_RXUF_MASK (0x10000U)

#define	LPUART_FIFO_RXUF_SHIFT (16U)

#define	LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)

#define	LPUART_FIFO_TXOF_MASK (0x20000U)

#define	LPUART_FIFO_TXOF_SHIFT (17U)

#define	LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)

#define	LPUART_FIFO_RXEMPT_MASK (0x400000U)

#define	LPUART_FIFO_RXEMPT_SHIFT (22U)

#define	LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)

#define	LPUART_FIFO_TXEMPT_MASK (0x800000U)

#define	LPUART_FIFO_TXEMPT_SHIFT (23U)

#define	LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)

WATER - LPUART Watermark Register
#define	LPUART_WATER_TXWATER_MASK (0x3U)

#define	LPUART_WATER_TXWATER_SHIFT (0U)

#define	LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)

#define	LPUART_WATER_TXCOUNT_MASK (0x700U)

#define	LPUART_WATER_TXCOUNT_SHIFT (8U)

#define	LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)

#define	LPUART_WATER_RXWATER_MASK (0x30000U)

#define	LPUART_WATER_RXWATER_SHIFT (16U)

#define	LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)

#define	LPUART_WATER_RXCOUNT_MASK (0x7000000U)

#define	LPUART_WATER_RXCOUNT_SHIFT (24U)

#define	LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)

Detailed Description

Macro Definition Documentation

◆ LPUART_BAUD_BOTHEDGE [1/3]

#define LPUART_BAUD_BOTHEDGE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)

BOTHEDGE - Both Edge Sampling 0b0..Receiver samples input data using the rising edge of the baud rate clock. 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.

◆ LPUART_BAUD_BOTHEDGE [2/3]

#define LPUART_BAUD_BOTHEDGE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)

BOTHEDGE - Both Edge Sampling 0b0..Receiver samples input data using the rising edge of the baud rate clock. 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.

◆ LPUART_BAUD_BOTHEDGE [3/3]

#define LPUART_BAUD_BOTHEDGE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)

BOTHEDGE - Both Edge Sampling 0b0..Receiver samples input data using the rising edge of the baud rate clock. 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.

◆ LPUART_BAUD_LBKDIE [1/3]

#define LPUART_BAUD_LBKDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)

LBKDIE - LIN Break Detect Interrupt Enable 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). 0b1..Hardware interrupt requested when STAT[LBKDIF] flag is 1.

◆ LPUART_BAUD_LBKDIE [2/3]

#define LPUART_BAUD_LBKDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)

LBKDIE - LIN Break Detect Interrupt Enable 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). 0b1..Hardware interrupt is requested when STAT[LBKDIF] flag is 1.

◆ LPUART_BAUD_LBKDIE [3/3]

#define LPUART_BAUD_LBKDIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)

LBKDIE - LIN Break Detect Interrupt Enable 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling). 0b1..Hardware interrupt is requested when STAT[LBKDIF] flag is 1.

◆ LPUART_BAUD_M10 [1/3]

#define LPUART_BAUD_M10 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)

M10 - 10-bit Mode select 0b0..Receiver and transmitter use 7-bit to 9-bit data characters. 0b1..Receiver and transmitter use 10-bit data characters.

◆ LPUART_BAUD_M10 [2/3]

#define LPUART_BAUD_M10 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)

M10 - 10-bit Mode select 0b0..Receiver and transmitter use 7-bit to 9-bit data characters. 0b1..Receiver and transmitter use 10-bit data characters.

◆ LPUART_BAUD_M10 [3/3]

#define LPUART_BAUD_M10 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)

M10 - 10-bit Mode select 0b0..Receiver and transmitter use 7-bit to 9-bit data characters. 0b1..Receiver and transmitter use 10-bit data characters.

◆ LPUART_BAUD_MAEN1 [1/3]

#define LPUART_BAUD_MAEN1 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)

MAEN1 - Match Address Mode Enable 1 0b0..Normal operation. 0b1..Enables automatic address matching or data matching mode for MATCH[MA1].

◆ LPUART_BAUD_MAEN1 [2/3]

#define LPUART_BAUD_MAEN1 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)

MAEN1 - Match Address Mode Enable 1 0b0..Normal operation. 0b1..Enables automatic address matching or data matching mode for MATCH[MA1].

◆ LPUART_BAUD_MAEN1 [3/3]

#define LPUART_BAUD_MAEN1 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)

MAEN1 - Match Address Mode Enable 1 0b0..Normal operation. 0b1..Enables automatic address matching or data matching mode for MATCH[MA1].

◆ LPUART_BAUD_MAEN2 [1/3]

#define LPUART_BAUD_MAEN2 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)

MAEN2 - Match Address Mode Enable 2 0b0..Normal operation. 0b1..Enables automatic address matching or data matching mode for MATCH[MA2].

◆ LPUART_BAUD_MAEN2 [2/3]

#define LPUART_BAUD_MAEN2 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)

MAEN2 - Match Address Mode Enable 2 0b0..Normal operation. 0b1..Enables automatic address matching or data matching mode for MATCH[MA2].

◆ LPUART_BAUD_MAEN2 [3/3]

#define LPUART_BAUD_MAEN2 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)

MAEN2 - Match Address Mode Enable 2 0b0..Normal operation. 0b1..Enables automatic address matching or data matching mode for MATCH[MA2].

◆ LPUART_BAUD_MATCFG [1/3]

#define LPUART_BAUD_MATCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)

MATCFG - Match Configuration 0b00..Address Match Wakeup 0b01..Idle Match Wakeup 0b10..Match On and Match Off 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input

◆ LPUART_BAUD_MATCFG [2/3]

#define LPUART_BAUD_MATCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)

MATCFG - Match Configuration 0b00..Address Match Wakeup 0b01..Idle Match Wakeup 0b10..Match On and Match Off 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input

◆ LPUART_BAUD_MATCFG [3/3]

#define LPUART_BAUD_MATCFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)

MATCFG - Match Configuration 0b00..Address Match Wakeup 0b01..Idle Match Wakeup 0b10..Match On and Match Off 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input

◆ LPUART_BAUD_OSR [1/3]

#define LPUART_BAUD_OSR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)

OSR - Oversampling Ratio 0b00000..Writing 0 to this field results in an oversampling ratio of 16 0b00001..Reserved 0b00010..Reserved 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set. 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set. 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set. 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set. 0b00111..Oversampling ratio of 8. 0b01000..Oversampling ratio of 9. 0b01001..Oversampling ratio of 10. 0b01010..Oversampling ratio of 11. 0b01011..Oversampling ratio of 12. 0b01100..Oversampling ratio of 13. 0b01101..Oversampling ratio of 14. 0b01110..Oversampling ratio of 15. 0b01111..Oversampling ratio of 16. 0b10000..Oversampling ratio of 17. 0b10001..Oversampling ratio of 18. 0b10010..Oversampling ratio of 19. 0b10011..Oversampling ratio of 20. 0b10100..Oversampling ratio of 21. 0b10101..Oversampling ratio of 22. 0b10110..Oversampling ratio of 23. 0b10111..Oversampling ratio of 24. 0b11000..Oversampling ratio of 25. 0b11001..Oversampling ratio of 26. 0b11010..Oversampling ratio of 27. 0b11011..Oversampling ratio of 28. 0b11100..Oversampling ratio of 29. 0b11101..Oversampling ratio of 30. 0b11110..Oversampling ratio of 31. 0b11111..Oversampling ratio of 32.

◆ LPUART_BAUD_OSR [2/3]

#define LPUART_BAUD_OSR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)

OSR - Oversampling Ratio 0b00000..Writing 0 to this field results in an oversampling ratio of 16 0b00001..Reserved 0b00010..Reserved 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set. 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set. 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set. 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set. 0b00111..Oversampling ratio of 8. 0b01000..Oversampling ratio of 9. 0b01001..Oversampling ratio of 10. 0b01010..Oversampling ratio of 11. 0b01011..Oversampling ratio of 12. 0b01100..Oversampling ratio of 13. 0b01101..Oversampling ratio of 14. 0b01110..Oversampling ratio of 15. 0b01111..Oversampling ratio of 16. 0b10000..Oversampling ratio of 17. 0b10001..Oversampling ratio of 18. 0b10010..Oversampling ratio of 19. 0b10011..Oversampling ratio of 20. 0b10100..Oversampling ratio of 21. 0b10101..Oversampling ratio of 22. 0b10110..Oversampling ratio of 23. 0b10111..Oversampling ratio of 24. 0b11000..Oversampling ratio of 25. 0b11001..Oversampling ratio of 26. 0b11010..Oversampling ratio of 27. 0b11011..Oversampling ratio of 28. 0b11100..Oversampling ratio of 29. 0b11101..Oversampling ratio of 30. 0b11110..Oversampling ratio of 31. 0b11111..Oversampling ratio of 32.

◆ LPUART_BAUD_OSR [3/3]

#define LPUART_BAUD_OSR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)

OSR - Oversampling Ratio 0b00000..Writing 0 to this field results in an oversampling ratio of 16 0b00001..Reserved 0b00010..Reserved 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set. 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set. 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set. 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set. 0b00111..Oversampling ratio of 8. 0b01000..Oversampling ratio of 9. 0b01001..Oversampling ratio of 10. 0b01010..Oversampling ratio of 11. 0b01011..Oversampling ratio of 12. 0b01100..Oversampling ratio of 13. 0b01101..Oversampling ratio of 14. 0b01110..Oversampling ratio of 15. 0b01111..Oversampling ratio of 16. 0b10000..Oversampling ratio of 17. 0b10001..Oversampling ratio of 18. 0b10010..Oversampling ratio of 19. 0b10011..Oversampling ratio of 20. 0b10100..Oversampling ratio of 21. 0b10101..Oversampling ratio of 22. 0b10110..Oversampling ratio of 23. 0b10111..Oversampling ratio of 24. 0b11000..Oversampling ratio of 25. 0b11001..Oversampling ratio of 26. 0b11010..Oversampling ratio of 27. 0b11011..Oversampling ratio of 28. 0b11100..Oversampling ratio of 29. 0b11101..Oversampling ratio of 30. 0b11110..Oversampling ratio of 31. 0b11111..Oversampling ratio of 32.

◆ LPUART_BAUD_RDMAE [1/3]

#define LPUART_BAUD_RDMAE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)

RDMAE - Receiver Full DMA Enable 0b0..DMA request disabled. 0b1..DMA request enabled.

◆ LPUART_BAUD_RDMAE [2/3]

#define LPUART_BAUD_RDMAE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)

RDMAE - Receiver Full DMA Enable 0b0..DMA request disabled. 0b1..DMA request enabled.

◆ LPUART_BAUD_RDMAE [3/3]

#define LPUART_BAUD_RDMAE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)

RDMAE - Receiver Full DMA Enable 0b0..DMA request disabled. 0b1..DMA request enabled.

◆ LPUART_BAUD_RESYNCDIS [1/3]

#define LPUART_BAUD_RESYNCDIS ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)

RESYNCDIS - Resynchronization Disable 0b0..Resynchronization during received data word is supported 0b1..Resynchronization during received data word is disabled

◆ LPUART_BAUD_RESYNCDIS [2/3]

#define LPUART_BAUD_RESYNCDIS ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)

RESYNCDIS - Resynchronization Disable 0b0..Resynchronization during received data word is supported. 0b1..Resynchronization during received data word is disabled.

◆ LPUART_BAUD_RESYNCDIS [3/3]

#define LPUART_BAUD_RESYNCDIS ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)

RESYNCDIS - Resynchronization Disable 0b0..Resynchronization during received data word is supported. 0b1..Resynchronization during received data word is disabled.

◆ LPUART_BAUD_RIDMAE

#define LPUART_BAUD_RIDMAE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RIDMAE_SHIFT)) & LPUART_BAUD_RIDMAE_MASK)

RIDMAE - Receiver Idle DMA Enable 0b0..DMA request disabled. 0b1..DMA request enabled.

◆ LPUART_BAUD_RXEDGIE [1/3]

#define LPUART_BAUD_RXEDGIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)

RXEDGIE - RX Input Active Edge Interrupt Enable 0b0..Hardware interrupts from STAT[RXEDGIF] are disabled. 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.

◆ LPUART_BAUD_RXEDGIE [2/3]

#define LPUART_BAUD_RXEDGIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)

RXEDGIE - RX Input Active Edge Interrupt Enable 0b0..Hardware interrupts from STAT[RXEDGIF] are disabled. 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.

◆ LPUART_BAUD_RXEDGIE [3/3]

#define LPUART_BAUD_RXEDGIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)

RXEDGIE - RX Input Active Edge Interrupt Enable 0b0..Hardware interrupts from STAT[RXEDGIF] are disabled. 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.

◆ LPUART_BAUD_SBNS [1/3]

#define LPUART_BAUD_SBNS ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)

SBNS - Stop Bit Number Select 0b0..One stop bit. 0b1..Two stop bits.

◆ LPUART_BAUD_SBNS [2/3]

#define LPUART_BAUD_SBNS ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)

SBNS - Stop Bit Number Select 0b0..One stop bit. 0b1..Two stop bits.

◆ LPUART_BAUD_SBNS [3/3]

#define LPUART_BAUD_SBNS ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)

SBNS - Stop Bit Number Select 0b0..One stop bit. 0b1..Two stop bits.

◆ LPUART_BAUD_SBR [1/3]

#define LPUART_BAUD_SBR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)

SBR - Baud Rate Modulo Divisor.

◆ LPUART_BAUD_SBR [2/3]

#define LPUART_BAUD_SBR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)

SBR - Baud Rate Modulo Divisor.

◆ LPUART_BAUD_SBR [3/3]

#define LPUART_BAUD_SBR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)

SBR - Baud Rate Modulo Divisor.

◆ LPUART_BAUD_TDMAE [1/3]

#define LPUART_BAUD_TDMAE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)

TDMAE - Transmitter DMA Enable 0b0..DMA request disabled. 0b1..DMA request enabled.

◆ LPUART_BAUD_TDMAE [2/3]

#define LPUART_BAUD_TDMAE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)

TDMAE - Transmitter DMA Enable 0b0..DMA request disabled. 0b1..DMA request enabled.

◆ LPUART_BAUD_TDMAE [3/3]

#define LPUART_BAUD_TDMAE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)

TDMAE - Transmitter DMA Enable 0b0..DMA request disabled. 0b1..DMA request enabled.

◆ LPUART_CTRL_DOZEEN [1/3]

#define LPUART_CTRL_DOZEEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)

DOZEEN - Doze Enable 0b0..LPUART is enabled in Doze mode. 0b1..LPUART is disabled in Doze mode.

◆ LPUART_CTRL_DOZEEN [2/3]

#define LPUART_CTRL_DOZEEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)

DOZEEN - Doze Enable 0b0..LPUART is enabled in Doze mode. 0b1..LPUART is disabled in Doze mode .

◆ LPUART_CTRL_DOZEEN [3/3]

#define LPUART_CTRL_DOZEEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)

DOZEEN - Doze Enable 0b0..LPUART is enabled in Doze mode. 0b1..LPUART is disabled in Doze mode .

◆ LPUART_CTRL_FEIE [1/3]

#define LPUART_CTRL_FEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)

FEIE - Framing Error Interrupt Enable 0b0..FE interrupts disabled; use polling. 0b1..Hardware interrupt requested when FE is set.

◆ LPUART_CTRL_FEIE [2/3]

#define LPUART_CTRL_FEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)

FEIE - Framing Error Interrupt Enable 0b0..FE interrupts disabled; use polling. 0b1..Hardware interrupt is requested when FE is set.

◆ LPUART_CTRL_FEIE [3/3]

#define LPUART_CTRL_FEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)

FEIE - Framing Error Interrupt Enable 0b0..FE interrupts disabled; use polling. 0b1..Hardware interrupt is requested when FE is set.

◆ LPUART_CTRL_IDLECFG [1/3]

#define LPUART_CTRL_IDLECFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)

IDLECFG - Idle Configuration 0b000..1 idle character 0b001..2 idle characters 0b010..4 idle characters 0b011..8 idle characters 0b100..16 idle characters 0b101..32 idle characters 0b110..64 idle characters 0b111..128 idle characters

◆ LPUART_CTRL_IDLECFG [2/3]

#define LPUART_CTRL_IDLECFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)

IDLECFG - Idle Configuration 0b000..1 idle character 0b001..2 idle characters 0b010..4 idle characters 0b011..8 idle characters 0b100..16 idle characters 0b101..32 idle characters 0b110..64 idle characters 0b111..128 idle characters

◆ LPUART_CTRL_IDLECFG [3/3]

#define LPUART_CTRL_IDLECFG ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)

IDLECFG - Idle Configuration 0b000..1 idle character 0b001..2 idle characters 0b010..4 idle characters 0b011..8 idle characters 0b100..16 idle characters 0b101..32 idle characters 0b110..64 idle characters 0b111..128 idle characters

◆ LPUART_CTRL_ILIE [1/3]

#define LPUART_CTRL_ILIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)

ILIE - Idle Line Interrupt Enable 0b0..Hardware interrupts from IDLE disabled; use polling. 0b1..Hardware interrupt requested when IDLE flag is 1.

◆ LPUART_CTRL_ILIE [2/3]

#define LPUART_CTRL_ILIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)

ILIE - Idle Line Interrupt Enable 0b0..Hardware interrupts from IDLE disabled; use polling. 0b1..Hardware interrupt is requested when IDLE flag is 1.

◆ LPUART_CTRL_ILIE [3/3]

#define LPUART_CTRL_ILIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)

ILIE - Idle Line Interrupt Enable 0b0..Hardware interrupts from IDLE disabled; use polling. 0b1..Hardware interrupt is requested when IDLE flag is 1.

◆ LPUART_CTRL_ILT [1/3]

#define LPUART_CTRL_ILT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)

ILT - Idle Line Type Select 0b0..Idle character bit count starts after start bit. 0b1..Idle character bit count starts after stop bit.

◆ LPUART_CTRL_ILT [2/3]

#define LPUART_CTRL_ILT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)

ILT - Idle Line Type Select 0b0..Idle character bit count starts after start bit. 0b1..Idle character bit count starts after stop bit.

◆ LPUART_CTRL_ILT [3/3]

#define LPUART_CTRL_ILT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)

ILT - Idle Line Type Select 0b0..Idle character bit count starts after start bit. 0b1..Idle character bit count starts after stop bit.

◆ LPUART_CTRL_LOOPS [1/3]

#define LPUART_CTRL_LOOPS ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)

LOOPS - Loop Mode Select 0b0..Normal operation - RXD and TXD use separate pins. 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).

◆ LPUART_CTRL_LOOPS [2/3]

#define LPUART_CTRL_LOOPS ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)

LOOPS - Loop Mode Select 0b0..Normal operation - RXD and TXD use separate pins. 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).

◆ LPUART_CTRL_LOOPS [3/3]

#define LPUART_CTRL_LOOPS ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)

LOOPS - Loop Mode Select 0b0..Normal operation - RXD and TXD use separate pins. 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).

◆ LPUART_CTRL_M [1/3]

#define LPUART_CTRL_M ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)

M - 9-Bit or 8-Bit Mode Select 0b0..Receiver and transmitter use 8-bit data characters. 0b1..Receiver and transmitter use 9-bit data characters.

◆ LPUART_CTRL_M [2/3]

#define LPUART_CTRL_M ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)

M - 9-Bit or 8-Bit Mode Select 0b0..Receiver and transmitter use 8-bit data characters. 0b1..Receiver and transmitter use 9-bit data characters.

◆ LPUART_CTRL_M [3/3]

#define LPUART_CTRL_M ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)

M - 9-Bit or 8-Bit Mode Select 0b0..Receiver and transmitter use 8-bit data characters. 0b1..Receiver and transmitter use 9-bit data characters.

◆ LPUART_CTRL_M7 [1/3]

#define LPUART_CTRL_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)

M7 - 7-Bit Mode Select 0b0..Receiver and transmitter use 8-bit to 10-bit data characters. 0b1..Receiver and transmitter use 7-bit data characters.

◆ LPUART_CTRL_M7 [2/3]

#define LPUART_CTRL_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)

M7 - 7-Bit Mode Select 0b0..Receiver and transmitter use 8-bit to 10-bit data characters. 0b1..Receiver and transmitter use 7-bit data characters.

◆ LPUART_CTRL_M7 [3/3]

#define LPUART_CTRL_M7 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)

M7 - 7-Bit Mode Select 0b0..Receiver and transmitter use 8-bit to 10-bit data characters. 0b1..Receiver and transmitter use 7-bit data characters.

◆ LPUART_CTRL_MA1IE [1/3]

#define LPUART_CTRL_MA1IE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)

MA1IE - Match 1 Interrupt Enable 0b0..MA1F interrupt disabled 0b1..MA1F interrupt enabled

◆ LPUART_CTRL_MA1IE [2/3]

#define LPUART_CTRL_MA1IE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)

MA1IE - Match 1 Interrupt Enable 0b0..MA1F interrupt disabled 0b1..MA1F interrupt enabled

◆ LPUART_CTRL_MA1IE [3/3]

#define LPUART_CTRL_MA1IE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)

MA1IE - Match 1 Interrupt Enable 0b0..MA1F interrupt disabled 0b1..MA1F interrupt enabled

◆ LPUART_CTRL_MA2IE [1/3]

#define LPUART_CTRL_MA2IE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)

MA2IE - Match 2 Interrupt Enable 0b0..MA2F interrupt disabled 0b1..MA2F interrupt enabled

◆ LPUART_CTRL_MA2IE [2/3]

#define LPUART_CTRL_MA2IE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)

MA2IE - Match 2 Interrupt Enable 0b0..MA2F interrupt disabled 0b1..MA2F interrupt enabled

◆ LPUART_CTRL_MA2IE [3/3]

#define LPUART_CTRL_MA2IE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)

MA2IE - Match 2 Interrupt Enable 0b0..MA2F interrupt disabled 0b1..MA2F interrupt enabled

◆ LPUART_CTRL_NEIE [1/3]

#define LPUART_CTRL_NEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)

NEIE - Noise Error Interrupt Enable 0b0..NF interrupts disabled; use polling. 0b1..Hardware interrupt requested when NF is set.

◆ LPUART_CTRL_NEIE [2/3]

#define LPUART_CTRL_NEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)

NEIE - Noise Error Interrupt Enable 0b0..NF interrupts disabled; use polling. 0b1..Hardware interrupt is requested when NF is set.

◆ LPUART_CTRL_NEIE [3/3]

#define LPUART_CTRL_NEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)

NEIE - Noise Error Interrupt Enable 0b0..NF interrupts disabled; use polling. 0b1..Hardware interrupt is requested when NF is set.

◆ LPUART_CTRL_ORIE [1/3]

#define LPUART_CTRL_ORIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)

ORIE - Overrun Interrupt Enable 0b0..OR interrupts disabled; use polling. 0b1..Hardware interrupt requested when OR is set.

◆ LPUART_CTRL_ORIE [2/3]

#define LPUART_CTRL_ORIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)

ORIE - Overrun Interrupt Enable 0b0..OR interrupts disabled; use polling. 0b1..Hardware interrupt is requested when OR is set.

◆ LPUART_CTRL_ORIE [3/3]

#define LPUART_CTRL_ORIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)

ORIE - Overrun Interrupt Enable 0b0..OR interrupts disabled; use polling. 0b1..Hardware interrupt is requested when OR is set.

◆ LPUART_CTRL_PE [1/3]

#define LPUART_CTRL_PE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)

PE - Parity Enable 0b0..No hardware parity generation or checking. 0b1..Parity enabled.

◆ LPUART_CTRL_PE [2/3]

#define LPUART_CTRL_PE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)

PE - Parity Enable 0b0..No hardware parity generation or checking. 0b1..Parity enabled.

◆ LPUART_CTRL_PE [3/3]

#define LPUART_CTRL_PE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)

PE - Parity Enable 0b0..No hardware parity generation or checking. 0b1..Parity enabled.

◆ LPUART_CTRL_PEIE [1/3]

#define LPUART_CTRL_PEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)

PEIE - Parity Error Interrupt Enable 0b0..PF interrupts disabled; use polling). 0b1..Hardware interrupt requested when PF is set.

◆ LPUART_CTRL_PEIE [2/3]

#define LPUART_CTRL_PEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)

PEIE - Parity Error Interrupt Enable 0b0..PF interrupts disabled; use polling). 0b1..Hardware interrupt is requested when PF is set.

◆ LPUART_CTRL_PEIE [3/3]

#define LPUART_CTRL_PEIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)

PEIE - Parity Error Interrupt Enable 0b0..PF interrupts disabled; use polling). 0b1..Hardware interrupt is requested when PF is set.

◆ LPUART_CTRL_PT [1/3]

#define LPUART_CTRL_PT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)

PT - Parity Type 0b0..Even parity. 0b1..Odd parity.

◆ LPUART_CTRL_PT [2/3]

#define LPUART_CTRL_PT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)

PT - Parity Type 0b0..Even parity. 0b1..Odd parity.

◆ LPUART_CTRL_PT [3/3]

#define LPUART_CTRL_PT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)

PT - Parity Type 0b0..Even parity. 0b1..Odd parity.

◆ LPUART_CTRL_R8T9 [1/3]

#define LPUART_CTRL_R8T9 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)

R8T9 - Receive Bit 8 / Transmit Bit 9

◆ LPUART_CTRL_R8T9 [2/3]

#define LPUART_CTRL_R8T9 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)

R8T9 - Receive Bit 8 / Transmit Bit 9

◆ LPUART_CTRL_R8T9 [3/3]

#define LPUART_CTRL_R8T9 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)

R8T9 - Receive Bit 8 / Transmit Bit 9

◆ LPUART_CTRL_R9T8 [1/3]

#define LPUART_CTRL_R9T8 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)

R9T8 - Receive Bit 9 / Transmit Bit 8

◆ LPUART_CTRL_R9T8 [2/3]

#define LPUART_CTRL_R9T8 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)

R9T8 - Receive Bit 9 / Transmit Bit 8

◆ LPUART_CTRL_R9T8 [3/3]

#define LPUART_CTRL_R9T8 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)

R9T8 - Receive Bit 9 / Transmit Bit 8

◆ LPUART_CTRL_RE [1/3]

#define LPUART_CTRL_RE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)

RE - Receiver Enable 0b0..Receiver disabled. 0b1..Receiver enabled.

◆ LPUART_CTRL_RE [2/3]

#define LPUART_CTRL_RE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)

RE - Receiver Enable 0b0..Receiver disabled. 0b1..Receiver enabled.

◆ LPUART_CTRL_RE [3/3]

#define LPUART_CTRL_RE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)

RE - Receiver Enable 0b0..Receiver disabled. 0b1..Receiver enabled.

◆ LPUART_CTRL_RIE [1/3]

#define LPUART_CTRL_RIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)

RIE - Receiver Interrupt Enable 0b0..Hardware interrupts from RDRF disabled; use polling. 0b1..Hardware interrupt requested when RDRF flag is 1.

◆ LPUART_CTRL_RIE [2/3]

#define LPUART_CTRL_RIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)

RIE - Receiver Interrupt Enable 0b0..Hardware interrupts from RDRF disabled. 0b1..Hardware interrupt is requested when RDRF flag is 1.

◆ LPUART_CTRL_RIE [3/3]

#define LPUART_CTRL_RIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)

RIE - Receiver Interrupt Enable 0b0..Hardware interrupts from RDRF disabled. 0b1..Hardware interrupt is requested when RDRF flag is 1.

◆ LPUART_CTRL_RSRC [1/3]

#define LPUART_CTRL_RSRC ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)

RSRC - Receiver Source Select 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.

◆ LPUART_CTRL_RSRC [2/3]

#define LPUART_CTRL_RSRC ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)

RSRC - Receiver Source Select 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.

◆ LPUART_CTRL_RSRC [3/3]

#define LPUART_CTRL_RSRC ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)

RSRC - Receiver Source Select 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin. 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.

◆ LPUART_CTRL_RWU [1/3]

#define LPUART_CTRL_RWU ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)

RWU - Receiver Wakeup Control 0b0..Normal receiver operation. 0b1..LPUART receiver in standby waiting for wakeup condition.

◆ LPUART_CTRL_RWU [2/3]

#define LPUART_CTRL_RWU ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)

RWU - Receiver Wakeup Control 0b0..Normal receiver operation. 0b1..LPUART receiver in standby waiting for wakeup condition.

◆ LPUART_CTRL_RWU [3/3]

#define LPUART_CTRL_RWU ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)

RWU - Receiver Wakeup Control 0b0..Normal receiver operation. 0b1..LPUART receiver in standby waiting for wakeup condition.

◆ LPUART_CTRL_SBK [1/3]

#define LPUART_CTRL_SBK ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)

SBK - Send Break 0b0..Normal transmitter operation. 0b1..Queue break character(s) to be sent.

◆ LPUART_CTRL_SBK [2/3]

#define LPUART_CTRL_SBK ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)

SBK - Send Break 0b0..Normal transmitter operation. 0b1..Queue break character(s) to be sent.

◆ LPUART_CTRL_SBK [3/3]

#define LPUART_CTRL_SBK ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)

SBK - Send Break 0b0..Normal transmitter operation. 0b1..Queue break character(s) to be sent.

◆ LPUART_CTRL_TCIE [1/3]

#define LPUART_CTRL_TCIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)

TCIE - Transmission Complete Interrupt Enable for 0b0..Hardware interrupts from TC disabled; use polling. 0b1..Hardware interrupt requested when TC flag is 1.

◆ LPUART_CTRL_TCIE [2/3]

#define LPUART_CTRL_TCIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)

TCIE - Transmission Complete Interrupt Enable for 0b0..Hardware interrupts from TC disabled. 0b1..Hardware interrupt is requested when TC flag is 1.

◆ LPUART_CTRL_TCIE [3/3]

#define LPUART_CTRL_TCIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)

TCIE - Transmission Complete Interrupt Enable for 0b0..Hardware interrupts from TC disabled. 0b1..Hardware interrupt is requested when TC flag is 1.

◆ LPUART_CTRL_TE [1/3]

#define LPUART_CTRL_TE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)

TE - Transmitter Enable 0b0..Transmitter disabled. 0b1..Transmitter enabled.

◆ LPUART_CTRL_TE [2/3]

#define LPUART_CTRL_TE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)

TE - Transmitter Enable 0b0..Transmitter disabled. 0b1..Transmitter enabled.

◆ LPUART_CTRL_TE [3/3]

#define LPUART_CTRL_TE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)

TE - Transmitter Enable 0b0..Transmitter disabled. 0b1..Transmitter enabled.

◆ LPUART_CTRL_TIE [1/3]

#define LPUART_CTRL_TIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)

TIE - Transmit Interrupt Enable 0b0..Hardware interrupts from TDRE disabled; use polling. 0b1..Hardware interrupt requested when TDRE flag is 1.

◆ LPUART_CTRL_TIE [2/3]

#define LPUART_CTRL_TIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)

TIE - Transmit Interrupt Enable 0b0..Hardware interrupts from TDRE disabled. 0b1..Hardware interrupt is requested when TDRE flag is 1.

◆ LPUART_CTRL_TIE [3/3]

#define LPUART_CTRL_TIE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)

TIE - Transmit Interrupt Enable 0b0..Hardware interrupts from TDRE disabled. 0b1..Hardware interrupt is requested when TDRE flag is 1.

◆ LPUART_CTRL_TXDIR [1/3]

#define LPUART_CTRL_TXDIR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)

TXDIR - TXD Pin Direction in Single-Wire Mode 0b0..TXD pin is an input in single-wire mode. 0b1..TXD pin is an output in single-wire mode.

◆ LPUART_CTRL_TXDIR [2/3]

#define LPUART_CTRL_TXDIR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)

TXDIR - TXD Pin Direction in Single-Wire Mode 0b0..TXD pin is an input in single-wire mode. 0b1..TXD pin is an output in single-wire mode.

◆ LPUART_CTRL_TXDIR [3/3]

#define LPUART_CTRL_TXDIR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)

TXDIR - TXD Pin Direction in Single-Wire Mode 0b0..TXD pin is an input in single-wire mode. 0b1..TXD pin is an output in single-wire mode.

◆ LPUART_CTRL_TXINV [1/3]

#define LPUART_CTRL_TXINV ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)

TXINV - Transmit Data Inversion 0b0..Transmit data not inverted. 0b1..Transmit data inverted.

◆ LPUART_CTRL_TXINV [2/3]

#define LPUART_CTRL_TXINV ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)

TXINV - Transmit Data Inversion 0b0..Transmit data not inverted. 0b1..Transmit data inverted.

◆ LPUART_CTRL_TXINV [3/3]

#define LPUART_CTRL_TXINV ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)

TXINV - Transmit Data Inversion 0b0..Transmit data not inverted. 0b1..Transmit data inverted.

◆ LPUART_CTRL_WAKE [1/3]

#define LPUART_CTRL_WAKE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)

WAKE - Receiver Wakeup Method Select 0b0..Configures RWU for idle-line wakeup. 0b1..Configures RWU with address-mark wakeup.

◆ LPUART_CTRL_WAKE [2/3]

#define LPUART_CTRL_WAKE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)

WAKE - Receiver Wakeup Method Select 0b0..Configures RWU for idle-line wakeup. 0b1..Configures RWU with address-mark wakeup.

◆ LPUART_CTRL_WAKE [3/3]

#define LPUART_CTRL_WAKE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)

WAKE - Receiver Wakeup Method Select 0b0..Configures RWU for idle-line wakeup. 0b1..Configures RWU with address-mark wakeup.

◆ LPUART_DATA_FRETSC [1/3]

#define LPUART_DATA_FRETSC ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)

FRETSC - Frame Error / Transmit Special Character 0b0..The dataword was received without a frame error on read, or transmit a normal character on write. 0b1..The dataword was received with a frame error, or transmit an idle or break character on transmit.

◆ LPUART_DATA_FRETSC [2/3]

#define LPUART_DATA_FRETSC ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)

FRETSC - Frame Error / Transmit Special Character 0b0..The dataword is received without a frame error on read, or transmit a normal character on write. 0b1..The dataword is received with a frame error, or transmit an idle or break character on transmit.

◆ LPUART_DATA_FRETSC [3/3]

#define LPUART_DATA_FRETSC ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)

FRETSC - Frame Error / Transmit Special Character 0b0..The dataword is received without a frame error on read, or transmit a normal character on write. 0b1..The dataword is received with a frame error, or transmit an idle or break character on transmit.

◆ LPUART_DATA_IDLINE [1/3]

#define LPUART_DATA_IDLINE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)

IDLINE - Idle Line 0b0..Receiver was not idle before receiving this character. 0b1..Receiver was idle before receiving this character.

◆ LPUART_DATA_IDLINE [2/3]

#define LPUART_DATA_IDLINE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)

IDLINE - Idle Line 0b0..Receiver was not idle before receiving this character. 0b1..Receiver was idle before receiving this character.

◆ LPUART_DATA_IDLINE [3/3]

#define LPUART_DATA_IDLINE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)

IDLINE - Idle Line 0b0..Receiver was not idle before receiving this character. 0b1..Receiver was idle before receiving this character.

◆ LPUART_DATA_NOISY [1/3]

#define LPUART_DATA_NOISY ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)

NOISY - NOISY 0b0..The dataword was received without noise. 0b1..The data was received with noise.

◆ LPUART_DATA_NOISY [2/3]

#define LPUART_DATA_NOISY ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)

NOISY - Noisy Data Received 0b0..The dataword is received without noise. 0b1..The data is received with noise.

◆ LPUART_DATA_NOISY [3/3]

#define LPUART_DATA_NOISY ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)

NOISY - Noisy Data Received 0b0..The dataword is received without noise. 0b1..The data is received with noise.

◆ LPUART_DATA_PARITYE [1/3]

#define LPUART_DATA_PARITYE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)

PARITYE - PARITYE 0b0..The dataword was received without a parity error. 0b1..The dataword was received with a parity error.

◆ LPUART_DATA_PARITYE [2/3]

#define LPUART_DATA_PARITYE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)

PARITYE - Parity Error 0b0..The dataword is received without a parity error. 0b1..The dataword is received with a parity error.

◆ LPUART_DATA_PARITYE [3/3]

#define LPUART_DATA_PARITYE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)

PARITYE - Parity Error 0b0..The dataword is received without a parity error. 0b1..The dataword is received with a parity error.

◆ LPUART_DATA_R0T0 [1/3]

#define LPUART_DATA_R0T0 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)

R0T0 - R0T0

◆ LPUART_DATA_R0T0 [2/3]

#define LPUART_DATA_R0T0 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)

R0T0 - R0T0

◆ LPUART_DATA_R0T0 [3/3]

#define LPUART_DATA_R0T0 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)

R0T0 - R0T0

◆ LPUART_DATA_R1T1 [1/3]

#define LPUART_DATA_R1T1 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)

R1T1 - R1T1

◆ LPUART_DATA_R1T1 [2/3]

#define LPUART_DATA_R1T1 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)

R1T1 - R1T1

◆ LPUART_DATA_R1T1 [3/3]

#define LPUART_DATA_R1T1 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)

R1T1 - R1T1

◆ LPUART_DATA_R2T2 [1/3]

#define LPUART_DATA_R2T2 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)

R2T2 - R2T2

◆ LPUART_DATA_R2T2 [2/3]

#define LPUART_DATA_R2T2 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)

R2T2 - R2T2

◆ LPUART_DATA_R2T2 [3/3]

#define LPUART_DATA_R2T2 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)

R2T2 - R2T2

◆ LPUART_DATA_R3T3 [1/3]

#define LPUART_DATA_R3T3 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)

R3T3 - R3T3

◆ LPUART_DATA_R3T3 [2/3]

#define LPUART_DATA_R3T3 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)

R3T3 - R3T3

◆ LPUART_DATA_R3T3 [3/3]

#define LPUART_DATA_R3T3 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)

R3T3 - R3T3

◆ LPUART_DATA_R4T4 [1/3]

#define LPUART_DATA_R4T4 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)

R4T4 - R4T4

◆ LPUART_DATA_R4T4 [2/3]

#define LPUART_DATA_R4T4 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)

R4T4 - R4T4

◆ LPUART_DATA_R4T4 [3/3]

#define LPUART_DATA_R4T4 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)

R4T4 - R4T4

◆ LPUART_DATA_R5T5 [1/3]

#define LPUART_DATA_R5T5 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)

R5T5 - R5T5

◆ LPUART_DATA_R5T5 [2/3]

#define LPUART_DATA_R5T5 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)

R5T5 - R5T5

◆ LPUART_DATA_R5T5 [3/3]

#define LPUART_DATA_R5T5 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)

R5T5 - R5T5

◆ LPUART_DATA_R6T6 [1/3]

#define LPUART_DATA_R6T6 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)

R6T6 - R6T6

◆ LPUART_DATA_R6T6 [2/3]

#define LPUART_DATA_R6T6 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)

R6T6 - R6T6

◆ LPUART_DATA_R6T6 [3/3]

#define LPUART_DATA_R6T6 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)

R6T6 - R6T6

◆ LPUART_DATA_R7T7 [1/3]

#define LPUART_DATA_R7T7 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)

R7T7 - R7T7

◆ LPUART_DATA_R7T7 [2/3]

#define LPUART_DATA_R7T7 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)

R7T7 - R7T7

◆ LPUART_DATA_R7T7 [3/3]

#define LPUART_DATA_R7T7 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)

R7T7 - R7T7

◆ LPUART_DATA_R8T8 [1/3]

#define LPUART_DATA_R8T8 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)

R8T8 - R8T8

◆ LPUART_DATA_R8T8 [2/3]

#define LPUART_DATA_R8T8 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)

R8T8 - R8T8

◆ LPUART_DATA_R8T8 [3/3]

#define LPUART_DATA_R8T8 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)

R8T8 - R8T8

◆ LPUART_DATA_R9T9 [1/3]

#define LPUART_DATA_R9T9 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)

R9T9 - R9T9

◆ LPUART_DATA_R9T9 [2/3]

#define LPUART_DATA_R9T9 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)

R9T9 - R9T9

◆ LPUART_DATA_R9T9 [3/3]

#define LPUART_DATA_R9T9 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)

R9T9 - R9T9

◆ LPUART_DATA_RXEMPT [1/3]

#define LPUART_DATA_RXEMPT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)

RXEMPT - Receive Buffer Empty 0b0..Receive buffer contains valid data. 0b1..Receive buffer is empty, data returned on read is not valid.

◆ LPUART_DATA_RXEMPT [2/3]

#define LPUART_DATA_RXEMPT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)

RXEMPT - Receive Buffer Empty 0b0..Receive buffer contains valid data. 0b1..Receive buffer is empty, data returned on read is not valid.

◆ LPUART_DATA_RXEMPT [3/3]

#define LPUART_DATA_RXEMPT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)

RXEMPT - Receive Buffer Empty 0b0..Receive buffer contains valid data. 0b1..Receive buffer is empty, data returned on read is not valid.

◆ LPUART_FIFO_RXEMPT [1/3]

#define LPUART_FIFO_RXEMPT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)

RXEMPT - Receive Buffer/FIFO Empty 0b0..Receive buffer is not empty. 0b1..Receive buffer is empty.

◆ LPUART_FIFO_RXEMPT [2/3]

#define LPUART_FIFO_RXEMPT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)

RXEMPT - Receive FIFO/Buffer Empty 0b0..Receive buffer is not empty. 0b1..Receive buffer is empty.

◆ LPUART_FIFO_RXEMPT [3/3]

#define LPUART_FIFO_RXEMPT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)

RXEMPT - Receive FIFO/Buffer Empty 0b0..Receive buffer is not empty. 0b1..Receive buffer is empty.

◆ LPUART_FIFO_RXFE [1/3]

#define LPUART_FIFO_RXFE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)

RXFE - Receive FIFO Enable 0b0..Receive FIFO is not enabled. Buffer is depth 1. 0b1..Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.

◆ LPUART_FIFO_RXFE [2/3]

#define LPUART_FIFO_RXFE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)

RXFE - Receive FIFO Enable 0b0..Receive FIFO is not enabled. Buffer depth is 1. 0b1..Receive FIFO is enabled. Buffer depth is indicted by RXFIFOSIZE.

◆ LPUART_FIFO_RXFE [3/3]

#define LPUART_FIFO_RXFE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)

RXFE - Receive FIFO Enable 0b0..Receive FIFO is not enabled. Buffer depth is 1. 0b1..Receive FIFO is enabled. Buffer depth is indicted by RXFIFOSIZE.

◆ LPUART_FIFO_RXFIFOSIZE [1/3]

#define LPUART_FIFO_RXFIFOSIZE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)

RXFIFOSIZE - Receive FIFO Buffer Depth 0b000..Receive FIFO/Buffer depth = 1 dataword. 0b001..Receive FIFO/Buffer depth = 4 datawords. 0b010..Receive FIFO/Buffer depth = 8 datawords. 0b011..Receive FIFO/Buffer depth = 16 datawords. 0b100..Receive FIFO/Buffer depth = 32 datawords. 0b101..Receive FIFO/Buffer depth = 64 datawords. 0b110..Receive FIFO/Buffer depth = 128 datawords. 0b111..Receive FIFO/Buffer depth = 256 datawords.

◆ LPUART_FIFO_RXFIFOSIZE [2/3]

#define LPUART_FIFO_RXFIFOSIZE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)

RXFIFOSIZE - Receive FIFO Buffer Depth 0b000..Receive FIFO/Buffer depth = 1 dataword. 0b001..Receive FIFO/Buffer depth = 4 datawords. 0b010..Receive FIFO/Buffer depth = 8 datawords. 0b011..Receive FIFO/Buffer depth = 16 datawords. 0b100..Receive FIFO/Buffer depth = 32 datawords. 0b101..Receive FIFO/Buffer depth = 64 datawords. 0b110..Receive FIFO/Buffer depth = 128 datawords. 0b111..Receive FIFO/Buffer depth = 256 datawords.

◆ LPUART_FIFO_RXFIFOSIZE [3/3]

#define LPUART_FIFO_RXFIFOSIZE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)

RXFIFOSIZE - Receive FIFO Buffer Depth 0b000..Receive FIFO/Buffer depth = 1 dataword. 0b001..Receive FIFO/Buffer depth = 4 datawords. 0b010..Receive FIFO/Buffer depth = 8 datawords. 0b011..Receive FIFO/Buffer depth = 16 datawords. 0b100..Receive FIFO/Buffer depth = 32 datawords. 0b101..Receive FIFO/Buffer depth = 64 datawords. 0b110..Receive FIFO/Buffer depth = 128 datawords. 0b111..Receive FIFO/Buffer depth = 256 datawords.

◆ LPUART_FIFO_RXFLUSH [1/3]

#define LPUART_FIFO_RXFLUSH ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)

RXFLUSH - Receive FIFO/Buffer Flush 0b0..No flush operation occurs. 0b1..All data in the receive FIFO/buffer is cleared out.

◆ LPUART_FIFO_RXFLUSH [2/3]

#define LPUART_FIFO_RXFLUSH ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)

RXFLUSH - Receive FIFO Flush 0b0..No flush operation occurs. 0b1..All data in the receive FIFO/buffer is cleared out.

◆ LPUART_FIFO_RXFLUSH [3/3]

#define LPUART_FIFO_RXFLUSH ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)

RXFLUSH - Receive FIFO Flush 0b0..No flush operation occurs. 0b1..All data in the receive FIFO/buffer is cleared out.

◆ LPUART_FIFO_RXIDEN [1/3]

#define LPUART_FIFO_RXIDEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)

RXIDEN - Receiver Idle Empty Enable 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle. 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.

◆ LPUART_FIFO_RXIDEN [2/3]

#define LPUART_FIFO_RXIDEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)

RXIDEN - Receiver Idle Empty Enable 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle. 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.

◆ LPUART_FIFO_RXIDEN [3/3]

#define LPUART_FIFO_RXIDEN ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)

RXIDEN - Receiver Idle Empty Enable 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle. 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character. 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters. 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters. 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters. 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters. 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters. 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.

◆ LPUART_FIFO_RXUF [1/3]

#define LPUART_FIFO_RXUF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)

RXUF - Receiver Buffer Underflow Flag 0b0..No receive buffer underflow has occurred since the last time the flag was cleared. 0b1..At least one receive buffer underflow has occurred since the last time the flag was cleared.

◆ LPUART_FIFO_RXUF [2/3]

#define LPUART_FIFO_RXUF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)

RXUF - Receiver FIFO Underflow Flag 0b0..No receive FIFO underflow has occurred since the last time the flag was cleared. 0b1..At least one receive FIFO underflow has occurred since the last time the flag was cleared.

◆ LPUART_FIFO_RXUF [3/3]

#define LPUART_FIFO_RXUF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)

RXUF - Receiver FIFO Underflow Flag 0b0..No receive FIFO underflow has occurred since the last time the flag was cleared. 0b1..At least one receive FIFO underflow has occurred since the last time the flag was cleared.

◆ LPUART_FIFO_RXUFE [1/3]

#define LPUART_FIFO_RXUFE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)

RXUFE - Receive FIFO Underflow Interrupt Enable 0b0..RXUF flag does not generate an interrupt to the host. 0b1..RXUF flag generates an interrupt to the host.

◆ LPUART_FIFO_RXUFE [2/3]

#define LPUART_FIFO_RXUFE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)

RXUFE - Receive FIFO Underflow Interrupt Enable 0b0..RXUF flag does not generate an interrupt to the host. 0b1..RXUF flag generates an interrupt to the host.

◆ LPUART_FIFO_RXUFE [3/3]

#define LPUART_FIFO_RXUFE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)

RXUFE - Receive FIFO Underflow Interrupt Enable 0b0..RXUF flag does not generate an interrupt to the host. 0b1..RXUF flag generates an interrupt to the host.

◆ LPUART_FIFO_TXEMPT [1/3]

#define LPUART_FIFO_TXEMPT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)

TXEMPT - Transmit Buffer/FIFO Empty 0b0..Transmit buffer is not empty. 0b1..Transmit buffer is empty.

◆ LPUART_FIFO_TXEMPT [2/3]

#define LPUART_FIFO_TXEMPT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)

TXEMPT - Transmit FIFO/Buffer Empty 0b0..Transmit buffer is not empty. 0b1..Transmit buffer is empty.

◆ LPUART_FIFO_TXEMPT [3/3]

#define LPUART_FIFO_TXEMPT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)

TXEMPT - Transmit FIFO/Buffer Empty 0b0..Transmit buffer is not empty. 0b1..Transmit buffer is empty.

◆ LPUART_FIFO_TXFE [1/3]

#define LPUART_FIFO_TXFE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)

TXFE - Transmit FIFO Enable 0b0..Transmit FIFO is not enabled. Buffer is depth 1. 0b1..Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.

◆ LPUART_FIFO_TXFE [2/3]

#define LPUART_FIFO_TXFE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)

TXFE - Transmit FIFO Enable 0b0..Transmit FIFO is not enabled. Buffer depth is 1. 0b1..Transmit FIFO is enabled. Buffer depth is indicated by TXFIFOSIZE.

◆ LPUART_FIFO_TXFE [3/3]

#define LPUART_FIFO_TXFE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)

TXFE - Transmit FIFO Enable 0b0..Transmit FIFO is not enabled. Buffer depth is 1. 0b1..Transmit FIFO is enabled. Buffer depth is indicated by TXFIFOSIZE.

◆ LPUART_FIFO_TXFIFOSIZE [1/3]

#define LPUART_FIFO_TXFIFOSIZE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)

TXFIFOSIZE - Transmit FIFO Buffer Depth 0b000..Transmit FIFO/Buffer depth = 1 dataword. 0b001..Transmit FIFO/Buffer depth = 4 datawords. 0b010..Transmit FIFO/Buffer depth = 8 datawords. 0b011..Transmit FIFO/Buffer depth = 16 datawords. 0b100..Transmit FIFO/Buffer depth = 32 datawords. 0b101..Transmit FIFO/Buffer depth = 64 datawords. 0b110..Transmit FIFO/Buffer depth = 128 datawords. 0b111..Transmit FIFO/Buffer depth = 256 datawords

◆ LPUART_FIFO_TXFIFOSIZE [2/3]

#define LPUART_FIFO_TXFIFOSIZE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)

TXFIFOSIZE - Transmit FIFO Buffer Depth 0b000..Transmit FIFO/Buffer depth = 1 dataword. 0b001..Transmit FIFO/Buffer depth = 4 datawords. 0b010..Transmit FIFO/Buffer depth = 8 datawords. 0b011..Transmit FIFO/Buffer depth = 16 datawords. 0b100..Transmit FIFO/Buffer depth = 32 datawords. 0b101..Transmit FIFO/Buffer depth = 64 datawords. 0b110..Transmit FIFO/Buffer depth = 128 datawords. 0b111..Transmit FIFO/Buffer depth = 256 datawords

◆ LPUART_FIFO_TXFIFOSIZE [3/3]

#define LPUART_FIFO_TXFIFOSIZE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)

TXFIFOSIZE - Transmit FIFO Buffer Depth 0b000..Transmit FIFO/Buffer depth = 1 dataword. 0b001..Transmit FIFO/Buffer depth = 4 datawords. 0b010..Transmit FIFO/Buffer depth = 8 datawords. 0b011..Transmit FIFO/Buffer depth = 16 datawords. 0b100..Transmit FIFO/Buffer depth = 32 datawords. 0b101..Transmit FIFO/Buffer depth = 64 datawords. 0b110..Transmit FIFO/Buffer depth = 128 datawords. 0b111..Transmit FIFO/Buffer depth = 256 datawords

◆ LPUART_FIFO_TXFLUSH [1/3]

#define LPUART_FIFO_TXFLUSH ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)

TXFLUSH - Transmit FIFO/Buffer Flush 0b0..No flush operation occurs. 0b1..All data in the transmit FIFO/Buffer is cleared out.

◆ LPUART_FIFO_TXFLUSH [2/3]

#define LPUART_FIFO_TXFLUSH ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)

TXFLUSH - Transmit FIFO Flush 0b0..No flush operation occurs. 0b1..All data in the transmit FIFO is cleared out.

◆ LPUART_FIFO_TXFLUSH [3/3]

#define LPUART_FIFO_TXFLUSH ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)

TXFLUSH - Transmit FIFO Flush 0b0..No flush operation occurs. 0b1..All data in the transmit FIFO is cleared out.

◆ LPUART_FIFO_TXOF [1/3]

#define LPUART_FIFO_TXOF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)

TXOF - Transmitter Buffer Overflow Flag 0b0..No transmit buffer overflow has occurred since the last time the flag was cleared. 0b1..At least one transmit buffer overflow has occurred since the last time the flag was cleared.

◆ LPUART_FIFO_TXOF [2/3]

#define LPUART_FIFO_TXOF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)

TXOF - Transmitter FIFO Overflow Flag 0b0..No transmit FIFO overflow has occurred since the last time the flag was cleared. 0b1..At least one transmit FIFO overflow has occurred since the last time the flag was cleared.

◆ LPUART_FIFO_TXOF [3/3]

#define LPUART_FIFO_TXOF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)

TXOF - Transmitter FIFO Overflow Flag 0b0..No transmit FIFO overflow has occurred since the last time the flag was cleared. 0b1..At least one transmit FIFO overflow has occurred since the last time the flag was cleared.

◆ LPUART_FIFO_TXOFE [1/3]

#define LPUART_FIFO_TXOFE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)

TXOFE - Transmit FIFO Overflow Interrupt Enable 0b0..TXOF flag does not generate an interrupt to the host. 0b1..TXOF flag generates an interrupt to the host.

◆ LPUART_FIFO_TXOFE [2/3]

#define LPUART_FIFO_TXOFE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)

TXOFE - Transmit FIFO Overflow Interrupt Enable 0b0..TXOF flag does not generate an interrupt to the host. 0b1..TXOF flag generates an interrupt to the host.

◆ LPUART_FIFO_TXOFE [3/3]

#define LPUART_FIFO_TXOFE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)

TXOFE - Transmit FIFO Overflow Interrupt Enable 0b0..TXOF flag does not generate an interrupt to the host. 0b1..TXOF flag generates an interrupt to the host.

◆ LPUART_GLOBAL_RST [1/3]

#define LPUART_GLOBAL_RST ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)

RST - Software Reset 0b0..Module is not reset. 0b1..Module is reset.

◆ LPUART_GLOBAL_RST [2/3]

#define LPUART_GLOBAL_RST ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)

RST - Software Reset 0b0..Module is not reset. 0b1..Module is reset.

◆ LPUART_GLOBAL_RST [3/3]

#define LPUART_GLOBAL_RST ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)

RST - Software Reset 0b0..Module is not reset. 0b1..Module is reset.

◆ LPUART_MATCH_MA1 [1/3]

#define LPUART_MATCH_MA1 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)

MA1 - Match Address 1

◆ LPUART_MATCH_MA1 [2/3]

#define LPUART_MATCH_MA1 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)

MA1 - Match Address 1

◆ LPUART_MATCH_MA1 [3/3]

#define LPUART_MATCH_MA1 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)

MA1 - Match Address 1

◆ LPUART_MATCH_MA2 [1/3]

#define LPUART_MATCH_MA2 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)

MA2 - Match Address 2

◆ LPUART_MATCH_MA2 [2/3]

#define LPUART_MATCH_MA2 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)

MA2 - Match Address 2

◆ LPUART_MATCH_MA2 [3/3]

#define LPUART_MATCH_MA2 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)

MA2 - Match Address 2

◆ LPUART_MODIR_IREN [1/3]

#define LPUART_MODIR_IREN ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)

IREN - Infrared enable 0b0..IR disabled. 0b1..IR enabled.

◆ LPUART_MODIR_IREN [2/3]

#define LPUART_MODIR_IREN ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)

IREN - Infrared enable 0b0..IR disabled. 0b1..IR enabled.

◆ LPUART_MODIR_IREN [3/3]

#define LPUART_MODIR_IREN ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)

IREN - Infrared enable 0b0..IR disabled. 0b1..IR enabled.

◆ LPUART_MODIR_RTSWATER [1/3]

#define LPUART_MODIR_RTSWATER ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)

RTSWATER - Receive RTS Configuration

◆ LPUART_MODIR_RTSWATER [2/3]

#define LPUART_MODIR_RTSWATER ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)

RTSWATER - Receive RTS Configuration

◆ LPUART_MODIR_RTSWATER [3/3]

#define LPUART_MODIR_RTSWATER ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)

RTSWATER - Receive RTS Configuration

◆ LPUART_MODIR_RXRTSE [1/3]

#define LPUART_MODIR_RXRTSE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)

RXRTSE - Receiver request-to-send enable 0b0..The receiver has no effect on RTS. 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full.

◆ LPUART_MODIR_RXRTSE [2/3]

#define LPUART_MODIR_RXRTSE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)

RXRTSE - Receiver request-to-send enable 0b0..The receiver has no effect on RTS. 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full.

◆ LPUART_MODIR_RXRTSE [3/3]

#define LPUART_MODIR_RXRTSE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)

RXRTSE - Receiver request-to-send enable 0b0..The receiver has no effect on RTS. 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause the receiver data register to become full. RTS is asserted if the receiver data register is not full and has not detected a start bit that would cause the receiver data register to become full.

◆ LPUART_MODIR_TNP [1/3]

#define LPUART_MODIR_TNP ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)

TNP - Transmitter narrow pulse 0b00..1/OSR. 0b01..2/OSR. 0b10..3/OSR. 0b11..4/OSR.

◆ LPUART_MODIR_TNP [2/3]

#define LPUART_MODIR_TNP ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)

TNP - Transmitter narrow pulse 0b00..1/OSR. 0b01..2/OSR. 0b10..3/OSR. 0b11..4/OSR.

◆ LPUART_MODIR_TNP [3/3]

#define LPUART_MODIR_TNP ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)

TNP - Transmitter narrow pulse 0b00..1/OSR. 0b01..2/OSR. 0b10..3/OSR. 0b11..4/OSR.

◆ LPUART_MODIR_TXCTSC [1/3]

#define LPUART_MODIR_TXCTSC ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)

TXCTSC - Transmit CTS Configuration 0b0..CTS input is sampled at the start of each character. 0b1..CTS input is sampled when the transmitter is idle.

◆ LPUART_MODIR_TXCTSC [2/3]

#define LPUART_MODIR_TXCTSC ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)

TXCTSC - Transmit CTS Configuration 0b0..CTS input is sampled at the start of each character. 0b1..CTS input is sampled when the transmitter is idle.

◆ LPUART_MODIR_TXCTSC [3/3]

#define LPUART_MODIR_TXCTSC ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)

TXCTSC - Transmit CTS Configuration 0b0..CTS input is sampled at the start of each character. 0b1..CTS input is sampled when the transmitter is idle.

◆ LPUART_MODIR_TXCTSE [1/3]

#define LPUART_MODIR_TXCTSE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)

TXCTSE - Transmitter clear-to-send enable 0b0..CTS has no effect on the transmitter. 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.

◆ LPUART_MODIR_TXCTSE [2/3]

#define LPUART_MODIR_TXCTSE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)

TXCTSE - Transmitter clear-to-send enable 0b0..CTS has no effect on the transmitter. 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.

◆ LPUART_MODIR_TXCTSE [3/3]

#define LPUART_MODIR_TXCTSE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)

TXCTSE - Transmitter clear-to-send enable 0b0..CTS has no effect on the transmitter. 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.

◆ LPUART_MODIR_TXCTSSRC [1/3]

#define LPUART_MODIR_TXCTSSRC ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)

TXCTSSRC - Transmit CTS Source 0b0..CTS input is the CTS_B pin. 0b1..CTS input is the inverted Receiver Match result.

◆ LPUART_MODIR_TXCTSSRC [2/3]

#define LPUART_MODIR_TXCTSSRC ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)

TXCTSSRC - Transmit CTS Source 0b0..CTS input is the CTS_B pin. 0b1..CTS input is an internal connection to the receiver address match result.

◆ LPUART_MODIR_TXCTSSRC [3/3]

#define LPUART_MODIR_TXCTSSRC ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)

TXCTSSRC - Transmit CTS Source 0b0..CTS input is the CTS_B pin. 0b1..CTS input is an internal connection to the receiver address match result.

◆ LPUART_MODIR_TXRTSE [1/3]

#define LPUART_MODIR_TXRTSE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)

TXRTSE - Transmitter request-to-send enable 0b0..The transmitter has no effect on RTS. 0b1..When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit.

◆ LPUART_MODIR_TXRTSE [2/3]

#define LPUART_MODIR_TXRTSE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)

TXRTSE - Transmitter request-to-send enable 0b0..The transmitter has no effect on RTS. 0b1..When a character is placed into an empty transmit shift register, RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter FIFO and shift register are completely sent, including the last stop bit.

◆ LPUART_MODIR_TXRTSE [3/3]

#define LPUART_MODIR_TXRTSE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)

TXRTSE - Transmitter request-to-send enable 0b0..The transmitter has no effect on RTS. 0b1..When a character is placed into an empty transmit shift register, RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter FIFO and shift register are completely sent, including the last stop bit.

◆ LPUART_MODIR_TXRTSPOL [1/3]

#define LPUART_MODIR_TXRTSPOL ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)

TXRTSPOL - Transmitter request-to-send polarity 0b0..Transmitter RTS is active low. 0b1..Transmitter RTS is active high.

◆ LPUART_MODIR_TXRTSPOL [2/3]

#define LPUART_MODIR_TXRTSPOL ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)

TXRTSPOL - Transmitter request-to-send polarity 0b0..Transmitter RTS is active low. 0b1..Transmitter RTS is active high.

◆ LPUART_MODIR_TXRTSPOL [3/3]

#define LPUART_MODIR_TXRTSPOL ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)

TXRTSPOL - Transmitter request-to-send polarity 0b0..Transmitter RTS is active low. 0b1..Transmitter RTS is active high.

◆ LPUART_PARAM_RXFIFO [1/3]

#define LPUART_PARAM_RXFIFO ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)

RXFIFO - Receive FIFO Size

◆ LPUART_PARAM_RXFIFO [2/3]

#define LPUART_PARAM_RXFIFO ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)

RXFIFO - Receive FIFO Size

◆ LPUART_PARAM_RXFIFO [3/3]

#define LPUART_PARAM_RXFIFO ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)

RXFIFO - Receive FIFO Size

◆ LPUART_PARAM_TXFIFO [1/3]

#define LPUART_PARAM_TXFIFO ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)

TXFIFO - Transmit FIFO Size

◆ LPUART_PARAM_TXFIFO [2/3]

#define LPUART_PARAM_TXFIFO ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)

TXFIFO - Transmit FIFO Size

◆ LPUART_PARAM_TXFIFO [3/3]

#define LPUART_PARAM_TXFIFO ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)

TXFIFO - Transmit FIFO Size

◆ LPUART_PINCFG_TRGSEL [1/3]

#define LPUART_PINCFG_TRGSEL ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)

TRGSEL - Trigger Select 0b00..Input trigger is disabled. 0b01..Input trigger is used instead of RXD pin input. 0b10..Input trigger is used instead of CTS_B pin input. 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is ANDed with the input trigger.

◆ LPUART_PINCFG_TRGSEL [2/3]

#define LPUART_PINCFG_TRGSEL ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)

TRGSEL - Trigger Select 0b00..Input trigger is disabled. 0b01..Input trigger is used instead of RXD pin input. 0b10..Input trigger is used instead of CTS_B pin input. 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is internally ANDed with the input trigger.

◆ LPUART_PINCFG_TRGSEL [3/3]

#define LPUART_PINCFG_TRGSEL ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)

TRGSEL - Trigger Select 0b00..Input trigger is disabled. 0b01..Input trigger is used instead of RXD pin input. 0b10..Input trigger is used instead of CTS_B pin input. 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is internally ANDed with the input trigger.

◆ LPUART_STAT_BRK13 [1/3]

#define LPUART_STAT_BRK13 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)

BRK13 - Break Character Generation Length 0b0..Break character is transmitted with length of 9 to 13 bit times. 0b1..Break character is transmitted with length of 12 to 15 bit times.

◆ LPUART_STAT_BRK13 [2/3]

#define LPUART_STAT_BRK13 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)

BRK13 - Break Character Generation Length 0b0..Break character is transmitted with length of 9 to 13 bit times. 0b1..Break character is transmitted with length of 12 to 15 bit times.

◆ LPUART_STAT_BRK13 [3/3]

#define LPUART_STAT_BRK13 ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)

BRK13 - Break Character Generation Length 0b0..Break character is transmitted with length of 9 to 13 bit times. 0b1..Break character is transmitted with length of 12 to 15 bit times.

◆ LPUART_STAT_FE [1/3]

#define LPUART_STAT_FE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)

FE - Framing Error Flag 0b0..No framing error detected. This does not guarantee the framing is correct. 0b1..Framing error.

◆ LPUART_STAT_FE [2/3]

#define LPUART_STAT_FE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)

FE - Framing Error Flag 0b0..No framing error detected. This does not guarantee the framing is correct. 0b1..Framing error.

◆ LPUART_STAT_FE [3/3]

#define LPUART_STAT_FE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)

FE - Framing Error Flag 0b0..No framing error detected. This does not guarantee the framing is correct. 0b1..Framing error.

◆ LPUART_STAT_IDLE [1/3]

#define LPUART_STAT_IDLE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)

IDLE - Idle Line Flag 0b0..No idle line detected. 0b1..Idle line was detected.

◆ LPUART_STAT_IDLE [2/3]

#define LPUART_STAT_IDLE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)

IDLE - Idle Line Flag 0b0..No idle line detected. 0b1..Idle line is detected.

◆ LPUART_STAT_IDLE [3/3]

#define LPUART_STAT_IDLE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)

IDLE - Idle Line Flag 0b0..No idle line detected. 0b1..Idle line is detected.

◆ LPUART_STAT_LBKDE [1/3]

#define LPUART_STAT_LBKDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)

LBKDE - LIN Break Detection Enable 0b0..LIN break detect is disabled, normal break character can be detected. 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).

◆ LPUART_STAT_LBKDE [2/3]

#define LPUART_STAT_LBKDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)

LBKDE - LIN Break Detection Enable 0b0..LIN break detect is disabled, normal break character can be detected. 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).

◆ LPUART_STAT_LBKDE [3/3]

#define LPUART_STAT_LBKDE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)

LBKDE - LIN Break Detection Enable 0b0..LIN break detect is disabled, normal break character can be detected. 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).

◆ LPUART_STAT_LBKDIF [1/3]

#define LPUART_STAT_LBKDIF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)

LBKDIF - LIN Break Detect Interrupt Flag 0b0..No LIN break character has been detected. 0b1..LIN break character has been detected.

◆ LPUART_STAT_LBKDIF [2/3]

#define LPUART_STAT_LBKDIF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)

LBKDIF - LIN Break Detect Interrupt Flag 0b0..No LIN break character has been detected. 0b1..LIN break character has been detected.

◆ LPUART_STAT_LBKDIF [3/3]

#define LPUART_STAT_LBKDIF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)

LBKDIF - LIN Break Detect Interrupt Flag 0b0..No LIN break character has been detected. 0b1..LIN break character has been detected.

◆ LPUART_STAT_MA1F [1/3]

#define LPUART_STAT_MA1F ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)

MA1F - Match 1 Flag 0b0..Received data is not equal to MA1 0b1..Received data is equal to MA1

◆ LPUART_STAT_MA1F [2/3]

#define LPUART_STAT_MA1F ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)

MA1F - Match 1 Flag 0b0..Received data is not equal to MA1 0b1..Received data is equal to MA1

◆ LPUART_STAT_MA1F [3/3]

#define LPUART_STAT_MA1F ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)

MA1F - Match 1 Flag 0b0..Received data is not equal to MA1 0b1..Received data is equal to MA1

◆ LPUART_STAT_MA2F [1/3]

#define LPUART_STAT_MA2F ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)

MA2F - Match 2 Flag 0b0..Received data is not equal to MA2 0b1..Received data is equal to MA2

◆ LPUART_STAT_MA2F [2/3]

#define LPUART_STAT_MA2F ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)

MA2F - Match 2 Flag 0b0..Received data is not equal to MA2 0b1..Received data is equal to MA2

◆ LPUART_STAT_MA2F [3/3]

#define LPUART_STAT_MA2F ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)

MA2F - Match 2 Flag 0b0..Received data is not equal to MA2 0b1..Received data is equal to MA2

◆ LPUART_STAT_MSBF [1/3]

#define LPUART_STAT_MSBF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)

MSBF - MSB First 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. 0b1..MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. Further, the first bit received after the start bit is identified as bit9, bit8, bit7 or bit6 depending on the setting of CTRL[M] and CTRL[PE].

◆ LPUART_STAT_MSBF [2/3]

#define LPUART_STAT_MSBF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)

MSBF - MSB First 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. 0b1..MSB (identified as bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. .

◆ LPUART_STAT_MSBF [3/3]

#define LPUART_STAT_MSBF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)

MSBF - MSB First 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. 0b1..MSB (identified as bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. .

◆ LPUART_STAT_NF [1/3]

#define LPUART_STAT_NF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)

NF - Noise Flag 0b0..No noise detected. 0b1..Noise detected in the received character in the DATA register.

◆ LPUART_STAT_NF [2/3]

#define LPUART_STAT_NF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)

NF - Noise Flag 0b0..No noise detected. 0b1..Noise detected in the received character in the DATA register.

◆ LPUART_STAT_NF [3/3]

#define LPUART_STAT_NF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)

NF - Noise Flag 0b0..No noise detected. 0b1..Noise detected in the received character in the DATA register.

◆ LPUART_STAT_OR [1/3]

#define LPUART_STAT_OR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)

OR - Receiver Overrun Flag 0b0..No overrun. 0b1..Receive overrun (new LPUART data lost).

◆ LPUART_STAT_OR [2/3]

#define LPUART_STAT_OR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)

OR - Receiver Overrun Flag 0b0..No overrun. 0b1..Receive overrun (new LPUART data lost).

◆ LPUART_STAT_OR [3/3]

#define LPUART_STAT_OR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)

OR - Receiver Overrun Flag 0b0..No overrun. 0b1..Receive overrun (new LPUART data lost).

◆ LPUART_STAT_PF [1/3]

#define LPUART_STAT_PF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)

PF - Parity Error Flag 0b0..No parity error. 0b1..Parity error.

◆ LPUART_STAT_PF [2/3]

#define LPUART_STAT_PF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)

PF - Parity Error Flag 0b0..No parity error. 0b1..Parity error.

◆ LPUART_STAT_PF [3/3]

#define LPUART_STAT_PF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)

PF - Parity Error Flag 0b0..No parity error. 0b1..Parity error.

◆ LPUART_STAT_RAF [1/3]

#define LPUART_STAT_RAF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)

RAF - Receiver Active Flag 0b0..LPUART receiver idle waiting for a start bit. 0b1..LPUART receiver active (RXD input not idle).

◆ LPUART_STAT_RAF [2/3]

#define LPUART_STAT_RAF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)

RAF - Receiver Active Flag 0b0..LPUART receiver idle waiting for a start bit. 0b1..LPUART receiver active (RXD input not idle).

◆ LPUART_STAT_RAF [3/3]

#define LPUART_STAT_RAF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)

RAF - Receiver Active Flag 0b0..LPUART receiver idle waiting for a start bit. 0b1..LPUART receiver active (RXD input not idle).

◆ LPUART_STAT_RDRF [1/3]

#define LPUART_STAT_RDRF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)

RDRF - Receive Data Register Full Flag 0b0..Receive data buffer empty. 0b1..Receive data buffer full.

◆ LPUART_STAT_RDRF [2/3]

#define LPUART_STAT_RDRF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)

RDRF - Receive Data Register Full Flag 0b0..Receive FIFO level is less than watermark. 0b1..Receive FIFO level is equal or greater than watermark.

◆ LPUART_STAT_RDRF [3/3]

#define LPUART_STAT_RDRF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)

RDRF - Receive Data Register Full Flag 0b0..Receive FIFO level is less than watermark. 0b1..Receive FIFO level is equal or greater than watermark.

◆ LPUART_STAT_RWUID [1/3]

#define LPUART_STAT_RWUID ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)

RWUID - Receive Wake Up Idle Detect 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match.

◆ LPUART_STAT_RWUID [2/3]

#define LPUART_STAT_RWUID ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)

RWUID - Receive Wake Up Idle Detect 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match.

◆ LPUART_STAT_RWUID [3/3]

#define LPUART_STAT_RWUID ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)

RWUID - Receive Wake Up Idle Detect 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle character. During address match wakeup, the IDLE bit does not set when an address does not match. 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During address match wakeup, the IDLE bit does set when an address does not match.

◆ LPUART_STAT_RXEDGIF [1/3]

#define LPUART_STAT_RXEDGIF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)

RXEDGIF - RXD Pin Active Edge Interrupt Flag 0b0..No active edge on the receive pin has occurred. 0b1..An active edge on the receive pin has occurred.

◆ LPUART_STAT_RXEDGIF [2/3]

#define LPUART_STAT_RXEDGIF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)

RXEDGIF - RXD Pin Active Edge Interrupt Flag 0b0..No active edge on the receive pin has occurred. 0b1..An active edge on the receive pin has occurred.

◆ LPUART_STAT_RXEDGIF [3/3]

#define LPUART_STAT_RXEDGIF ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)

RXEDGIF - RXD Pin Active Edge Interrupt Flag 0b0..No active edge on the receive pin has occurred. 0b1..An active edge on the receive pin has occurred.

◆ LPUART_STAT_RXINV [1/3]

#define LPUART_STAT_RXINV ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)

RXINV - Receive Data Inversion 0b0..Receive data not inverted. 0b1..Receive data inverted.

◆ LPUART_STAT_RXINV [2/3]

#define LPUART_STAT_RXINV ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)

RXINV - Receive Data Inversion 0b0..Receive data not inverted. 0b1..Receive data inverted.

◆ LPUART_STAT_RXINV [3/3]

#define LPUART_STAT_RXINV ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)

RXINV - Receive Data Inversion 0b0..Receive data not inverted. 0b1..Receive data inverted.

◆ LPUART_STAT_TC [1/3]

#define LPUART_STAT_TC ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)

TC - Transmission Complete Flag 0b0..Transmitter active (sending data, a preamble, or a break). 0b1..Transmitter idle (transmission activity complete).

◆ LPUART_STAT_TC [2/3]

#define LPUART_STAT_TC ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)

TC - Transmission Complete Flag 0b0..Transmitter active (sending data, a preamble, or a break). 0b1..Transmitter idle (transmission activity complete).

◆ LPUART_STAT_TC [3/3]

#define LPUART_STAT_TC ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)

TC - Transmission Complete Flag 0b0..Transmitter active (sending data, a preamble, or a break). 0b1..Transmitter idle (transmission activity complete).

◆ LPUART_STAT_TDRE [1/3]

#define LPUART_STAT_TDRE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)

TDRE - Transmit Data Register Empty Flag 0b0..Transmit data buffer full. 0b1..Transmit data buffer empty.

◆ LPUART_STAT_TDRE [2/3]

#define LPUART_STAT_TDRE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)

TDRE - Transmit Data Register Empty Flag 0b0..Transmit FIFO level is greater than watermark. 0b1..Transmit FIFO level is equal or less than watermark.

◆ LPUART_STAT_TDRE [3/3]

#define LPUART_STAT_TDRE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)

TDRE - Transmit Data Register Empty Flag 0b0..Transmit FIFO level is greater than watermark. 0b1..Transmit FIFO level is equal or less than watermark.

◆ LPUART_VERID_FEATURE [1/3]

#define LPUART_VERID_FEATURE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)

FEATURE - Feature Identification Number 0b0000000000000001..Standard feature set. 0b0000000000000011..Standard feature set with MODEM/IrDA support.

◆ LPUART_VERID_FEATURE [2/3]

#define LPUART_VERID_FEATURE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)

FEATURE - Feature Identification Number 0b0000000000000001..Standard feature set. 0b0000000000000011..Standard feature set with MODEM/IrDA support.

◆ LPUART_VERID_FEATURE [3/3]

#define LPUART_VERID_FEATURE ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)

FEATURE - Feature Identification Number 0b0000000000000001..Standard feature set. 0b0000000000000011..Standard feature set with MODEM/IrDA support.

◆ LPUART_VERID_MAJOR [1/3]

#define LPUART_VERID_MAJOR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)

MAJOR - Major Version Number

◆ LPUART_VERID_MAJOR [2/3]

#define LPUART_VERID_MAJOR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)

MAJOR - Major Version Number

◆ LPUART_VERID_MAJOR [3/3]

#define LPUART_VERID_MAJOR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)

MAJOR - Major Version Number

◆ LPUART_VERID_MINOR [1/3]

#define LPUART_VERID_MINOR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)

MINOR - Minor Version Number

◆ LPUART_VERID_MINOR [2/3]

#define LPUART_VERID_MINOR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)

MINOR - Minor Version Number

◆ LPUART_VERID_MINOR [3/3]

#define LPUART_VERID_MINOR ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)

MINOR - Minor Version Number

◆ LPUART_WATER_RXCOUNT [1/3]

#define LPUART_WATER_RXCOUNT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)

RXCOUNT - Receive Counter

◆ LPUART_WATER_RXCOUNT [2/3]

#define LPUART_WATER_RXCOUNT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)

RXCOUNT - Receive Counter

◆ LPUART_WATER_RXCOUNT [3/3]

#define LPUART_WATER_RXCOUNT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)

RXCOUNT - Receive Counter

◆ LPUART_WATER_RXWATER [1/3]

#define LPUART_WATER_RXWATER ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)

RXWATER - Receive Watermark

◆ LPUART_WATER_RXWATER [2/3]

#define LPUART_WATER_RXWATER ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)

RXWATER - Receive Watermark

◆ LPUART_WATER_RXWATER [3/3]

#define LPUART_WATER_RXWATER ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)

RXWATER - Receive Watermark

◆ LPUART_WATER_TXCOUNT [1/3]

#define LPUART_WATER_TXCOUNT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)

TXCOUNT - Transmit Counter

◆ LPUART_WATER_TXCOUNT [2/3]

#define LPUART_WATER_TXCOUNT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)

TXCOUNT - Transmit Counter

◆ LPUART_WATER_TXCOUNT [3/3]

#define LPUART_WATER_TXCOUNT ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)

TXCOUNT - Transmit Counter

◆ LPUART_WATER_TXWATER [1/3]

#define LPUART_WATER_TXWATER ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)

TXWATER - Transmit Watermark

◆ LPUART_WATER_TXWATER [2/3]

#define LPUART_WATER_TXWATER ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)

TXWATER - Transmit Watermark

◆ LPUART_WATER_TXWATER [3/3]

#define LPUART_WATER_TXWATER ( x ) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)

TXWATER - Transmit Watermark

VERID - Version ID Register

PARAM - Parameter Register

GLOBAL - LPUART Global Register

PINCFG - LPUART Pin Configuration Register

BAUD - LPUART Baud Rate Register

STAT - LPUART Status Register

CTRL - LPUART Control Register

DATA - LPUART Data Register

MATCH - LPUART Match Address Register

MODIR - LPUART Modem IrDA Register

FIFO - LPUART FIFO Register

WATER - LPUART Watermark Register

VERID - Version ID Register

PARAM - Parameter Register

GLOBAL - LPUART Global Register

PINCFG - LPUART Pin Configuration Register

BAUD - LPUART Baud Rate Register

STAT - LPUART Status Register

CTRL - LPUART Control Register

DATA - LPUART Data Register

MATCH - LPUART Match Address Register

MODIR - LPUART Modem IrDA Register

FIFO - LPUART FIFO Register

WATER - LPUART Watermark Register

VERID - Version ID Register

PARAM - Parameter Register

GLOBAL - LPUART Global Register

PINCFG - LPUART Pin Configuration Register

BAUD - LPUART Baud Rate Register

STAT - LPUART Status Register

CTRL - LPUART Control Register

DATA - LPUART Data Register

MATCH - LPUART Match Address Register

MODIR - LPUART Modem IrDA Register

FIFO - LPUART FIFO Register

WATER - LPUART Watermark Register

Detailed Description

Macro Definition Documentation

◆ LPUART_BAUD_BOTHEDGE [1/3]

◆ LPUART_BAUD_BOTHEDGE [2/3]

◆ LPUART_BAUD_BOTHEDGE [3/3]

◆ LPUART_BAUD_LBKDIE [1/3]

◆ LPUART_BAUD_LBKDIE [2/3]

◆ LPUART_BAUD_LBKDIE [3/3]

◆ LPUART_BAUD_M10 [1/3]

◆ LPUART_BAUD_M10 [2/3]

◆ LPUART_BAUD_M10 [3/3]

◆ LPUART_BAUD_MAEN1 [1/3]

◆ LPUART_BAUD_MAEN1 [2/3]

◆ LPUART_BAUD_MAEN1 [3/3]

◆ LPUART_BAUD_MAEN2 [1/3]

◆ LPUART_BAUD_MAEN2 [2/3]

◆ LPUART_BAUD_MAEN2 [3/3]

◆ LPUART_BAUD_MATCFG [1/3]

◆ LPUART_BAUD_MATCFG [2/3]

◆ LPUART_BAUD_MATCFG [3/3]

◆ LPUART_BAUD_OSR [1/3]

◆ LPUART_BAUD_OSR [2/3]

◆ LPUART_BAUD_OSR [3/3]

◆ LPUART_BAUD_RDMAE [1/3]

◆ LPUART_BAUD_RDMAE [2/3]

◆ LPUART_BAUD_RDMAE [3/3]

◆ LPUART_BAUD_RESYNCDIS [1/3]

◆ LPUART_BAUD_RESYNCDIS [2/3]

◆ LPUART_BAUD_RESYNCDIS [3/3]

◆ LPUART_BAUD_RIDMAE

◆ LPUART_BAUD_RXEDGIE [1/3]

◆ LPUART_BAUD_RXEDGIE [2/3]

◆ LPUART_BAUD_RXEDGIE [3/3]

◆ LPUART_BAUD_SBNS [1/3]

◆ LPUART_BAUD_SBNS [2/3]

◆ LPUART_BAUD_SBNS [3/3]

◆ LPUART_BAUD_SBR [1/3]

◆ LPUART_BAUD_SBR [2/3]

◆ LPUART_BAUD_SBR [3/3]

◆ LPUART_BAUD_TDMAE [1/3]

◆ LPUART_BAUD_TDMAE [2/3]

◆ LPUART_BAUD_TDMAE [3/3]

◆ LPUART_CTRL_DOZEEN [1/3]

◆ LPUART_CTRL_DOZEEN [2/3]