|
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| |
|
#define | IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC) |
| |
|
#define | IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
|
#define | IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
|
#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
|
#define | IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | HASH_RNG_IRQn RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | DCMI_IRQn DCMI_PSSI_IRQn |
| |
|
#define | HASH_RNG_IRQHandler RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| |
|
#define | IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC) |
| |
|
#define | IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
|
#define | IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
|
#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
|
#define | IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | HASH_RNG_IRQn RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | DCMI_IRQn DCMI_PSSI_IRQn |
| |
|
#define | HASH_RNG_IRQHandler RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| |
|
#define | IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC) |
| |
|
#define | IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
|
#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
|
#define | IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | RNG_IRQn HASH_RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | DCMI_IRQn DCMI_PSSI_IRQn |
| |
|
#define | RNG_IRQHandler HASH_RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| |
|
#define | IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC) |
| |
|
#define | IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
|
#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
|
#define | IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | RNG_IRQn HASH_RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | DCMI_IRQn DCMI_PSSI_IRQn |
| |
|
#define | RNG_IRQHandler HASH_RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| |
|
#define | IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC) |
| |
|
#define | IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
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| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
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|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
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#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
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#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
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| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
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| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
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| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
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|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
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| #define | IS_LPTIM_INSTANCE(INSTANCE) |
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| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
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| #define | IS_TIM_INSTANCE(INSTANCE) |
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| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
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| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
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| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
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| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
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| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
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| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
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| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
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| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
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| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
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| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
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| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
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| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
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| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
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| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
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| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
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| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
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| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
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| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
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| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
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| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
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| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
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|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
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| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
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| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
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| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
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| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
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| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
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| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
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| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
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| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
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| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
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| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
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| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
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| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
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| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
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| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
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| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
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| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
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| #define | IS_UART_INSTANCE(INSTANCE) |
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| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
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| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
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| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
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| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
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| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
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| #define | IS_IRDA_INSTANCE(INSTANCE) |
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| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
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|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
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#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
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#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
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#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
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#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
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#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
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| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
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#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
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| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
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#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
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#define | IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
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#define | IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
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#define | RNG_IRQn HASH_RNG_IRQn |
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|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
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|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
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|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
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|
#define | PVD_IRQn PVD_AVD_IRQn |
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|
#define | DCMI_IRQn DCMI_PSSI_IRQn |
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|
#define | RNG_IRQHandler HASH_RNG_IRQHandler |
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|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
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|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
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#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
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|
#define | IS_CORDIC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CORDIC) |
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#define | IS_FMAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == FMAC) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
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|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
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|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
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#define | IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS) |
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#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
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|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
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|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
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|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
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| #define | IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) |
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|
#define | IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
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| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
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|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
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| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
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|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
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#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
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#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
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#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
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#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
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#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
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#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
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#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
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#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
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#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
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#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
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#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
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| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
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#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
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| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
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#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
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#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
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#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
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| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
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| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
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|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
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| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
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| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
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| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
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| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
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|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
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|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
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|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
|
#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
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|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
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|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
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|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
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|
#define | IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
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|
#define | IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
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|
#define | RNG_IRQn HASH_RNG_IRQn |
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|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
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|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
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|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | DCMI_IRQn DCMI_PSSI_IRQn |
| |
|
#define | RNG_IRQHandler HASH_RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1)) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
|
#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
| #define | IS_PCD_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_HCD_ALL_INSTANCE(INSTANCE) |
| |
|
#define | HASH_RNG_IRQn RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | HASH_RNG_IRQHandler RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1)) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
|
#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
| #define | IS_PCD_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_HCD_ALL_INSTANCE(INSTANCE) |
| |
|
#define | HASH_RNG_IRQn RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | HASH_RNG_IRQHandler RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1)) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
| #define | IS_WWDG_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
| #define | IS_PCD_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_HCD_ALL_INSTANCE(INSTANCE) |
| |
|
#define | HASH_RNG_IRQn RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | HASH_RNG_IRQHandler RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1)) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
| #define | IS_WWDG_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
| #define | IS_PCD_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_HCD_ALL_INSTANCE(INSTANCE) |
| |
|
#define | HASH_RNG_IRQn RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | HASH_RNG_IRQHandler RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1)) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
| #define | IS_WWDG_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
| #define | IS_PCD_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_HCD_ALL_INSTANCE(INSTANCE) |
| |
|
#define | HASH_RNG_IRQn RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | HASH_RNG_IRQHandler RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1)) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
| #define | IS_WWDG_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
| #define | IS_PCD_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_HCD_ALL_INSTANCE(INSTANCE) |
| |
|
#define | HASH_RNG_IRQn RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | HASH_RNG_IRQHandler RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1)) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
|
#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
| #define | IS_PCD_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_HCD_ALL_INSTANCE(INSTANCE) |
| |
|
#define | RNG_IRQn HASH_RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | RNG_IRQHandler HASH_RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
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|
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1)) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
|
#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
| #define | IS_PCD_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_HCD_ALL_INSTANCE(INSTANCE) |
| |
|
#define | RNG_IRQn HASH_RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | RNG_IRQHandler HASH_RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1)) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
| #define | IS_WWDG_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
| #define | IS_PCD_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_HCD_ALL_INSTANCE(INSTANCE) |
| |
|
#define | RNG_IRQn HASH_RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | RNG_IRQHandler HASH_RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
| #define | IS_ADC_COMMON_INSTANCE(INSTANCE) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
|
#define | IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (31U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1)) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2)) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
| #define | IS_WWDG_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
| #define | IS_PCD_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_HCD_ALL_INSTANCE(INSTANCE) |
| |
|
#define | RNG_IRQn HASH_RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | RNG_IRQHandler HASH_RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | COMP_IRQHandler COMP1_IRQHandler |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
|
#define | IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
| #define | IS_DAC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
|
#define | IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
|
#define | IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (15U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
|
#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
|
#define | IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | HASH_RNG_IRQn RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | BDMA_Channel0_IRQn BDMA2_Channel0_IRQn |
| |
|
#define | BDMA_Channel1_IRQn BDMA2_Channel1_IRQn |
| |
|
#define | BDMA_Channel2_IRQn BDMA2_Channel2_IRQn |
| |
|
#define | BDMA_Channel3_IRQn BDMA2_Channel3_IRQn |
| |
|
#define | BDMA_Channel4_IRQn BDMA2_Channel4_IRQn |
| |
|
#define | BDMA_Channel5_IRQn BDMA2_Channel5_IRQn |
| |
|
#define | BDMA_Channel6_IRQn BDMA2_Channel6_IRQn |
| |
|
#define | BDMA_Channel7_IRQn BDMA2_Channel7_IRQn |
| |
|
#define | PVD_AVD_IRQn PVD_PVM_IRQn |
| |
|
#define | DCMI_IRQn DCMI_PSSI_IRQn |
| |
|
#define | HASH_RNG_IRQHandler RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | BDMA_Channel0_IRQHandler BDMA2_Channel0_IRQHandler |
| |
|
#define | BDMA_Channel1_IRQHandler BDMA2_Channel1_IRQHandler |
| |
|
#define | BDMA_Channel2_IRQHandler BDMA2_Channel2_IRQHandler |
| |
|
#define | BDMA_Channel3_IRQHandler BDMA2_Channel3_IRQHandler |
| |
|
#define | BDMA_Channel4_IRQHandler BDMA2_Channel4_IRQHandler |
| |
|
#define | BDMA_Channel5_IRQHandler BDMA2_Channel5_IRQHandler |
| |
|
#define | BDMA_Channel6_IRQHandler BDMA2_Channel6_IRQHandler |
| |
|
#define | BDMA_Channel7_IRQHandler BDMA2_Channel7_IRQHandler |
| |
|
#define | PVD_AVD_IRQHandler PVD_PVM_IRQHandler |
| |
|
#define | DCMI_IRQHandler DCMI_PSSI_IRQHandler |
| |
|
#define | BDMA_BASE BDMA2_BASE |
| |
|
#define | BDMA_Channel0_BASE BDMA2_Channel0_BASE |
| |
|
#define | BDMA_Channel1_BASE BDMA2_Channel1_BASE |
| |
|
#define | BDMA_Channel2_BASE BDMA2_Channel2_BASE |
| |
|
#define | BDMA_Channel3_BASE BDMA2_Channel3_BASE |
| |
|
#define | BDMA_Channel4_BASE BDMA2_Channel4_BASE |
| |
|
#define | BDMA_Channel5_BASE BDMA2_Channel5_BASE |
| |
|
#define | BDMA_Channel6_BASE BDMA2_Channel6_BASE |
| |
|
#define | BDMA_Channel7_BASE BDMA2_Channel7_BASE |
| |
|
#define | BDMA BDMA2 |
| |
|
#define | BDMA_Channel0 BDMA2_Channel0 |
| |
|
#define | BDMA_Channel1 BDMA2_Channel1 |
| |
|
#define | BDMA_Channel2 BDMA2_Channel2 |
| |
|
#define | BDMA_Channel3 BDMA2_Channel3 |
| |
|
#define | BDMA_Channel4 BDMA2_Channel4 |
| |
|
#define | BDMA_Channel5 BDMA2_Channel5 |
| |
|
#define | BDMA_Channel6 BDMA2_Channel6 |
| |
|
#define | BDMA_Channel7 BDMA2_Channel7 |
| |
|
#define | PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_SRD |
| |
|
#define | PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_SRD |
| |
|
#define | PWR_CPUCR_PDDS_D1 PWR_CPUCR_RETDS_CD |
| |
|
#define | PWR_D3CR_VOS PWR_SRDCR_VOS |
| |
|
#define | PWR_D3CR_VOS_0 PWR_SRDCR_VOS_0 |
| |
|
#define | PWR_D3CR_VOS_1 PWR_SRDCR_VOS_1 |
| |
|
#define | PWR_D3CR_VOSRDY PWR_SRDCR_VOSRDY |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
|
#define | IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
| #define | IS_DAC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
|
#define | IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
|
#define | IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (15U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
|
#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
|
#define | IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | HASH_RNG_IRQn RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | BDMA_Channel0_IRQn BDMA2_Channel0_IRQn |
| |
|
#define | BDMA_Channel1_IRQn BDMA2_Channel1_IRQn |
| |
|
#define | BDMA_Channel2_IRQn BDMA2_Channel2_IRQn |
| |
|
#define | BDMA_Channel3_IRQn BDMA2_Channel3_IRQn |
| |
|
#define | BDMA_Channel4_IRQn BDMA2_Channel4_IRQn |
| |
|
#define | BDMA_Channel5_IRQn BDMA2_Channel5_IRQn |
| |
|
#define | BDMA_Channel6_IRQn BDMA2_Channel6_IRQn |
| |
|
#define | BDMA_Channel7_IRQn BDMA2_Channel7_IRQn |
| |
|
#define | PVD_AVD_IRQn PVD_PVM_IRQn |
| |
|
#define | DCMI_IRQn DCMI_PSSI_IRQn |
| |
|
#define | HASH_RNG_IRQHandler RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | BDMA_Channel0_IRQHandler BDMA2_Channel0_IRQHandler |
| |
|
#define | BDMA_Channel1_IRQHandler BDMA2_Channel1_IRQHandler |
| |
|
#define | BDMA_Channel2_IRQHandler BDMA2_Channel2_IRQHandler |
| |
|
#define | BDMA_Channel3_IRQHandler BDMA2_Channel3_IRQHandler |
| |
|
#define | BDMA_Channel4_IRQHandler BDMA2_Channel4_IRQHandler |
| |
|
#define | BDMA_Channel5_IRQHandler BDMA2_Channel5_IRQHandler |
| |
|
#define | BDMA_Channel6_IRQHandler BDMA2_Channel6_IRQHandler |
| |
|
#define | BDMA_Channel7_IRQHandler BDMA2_Channel7_IRQHandler |
| |
|
#define | PVD_AVD_IRQHandler PVD_PVM_IRQHandler |
| |
|
#define | DCMI_IRQHandler DCMI_PSSI_IRQHandler |
| |
|
#define | BDMA_BASE BDMA2_BASE |
| |
|
#define | BDMA_Channel0_BASE BDMA2_Channel0_BASE |
| |
|
#define | BDMA_Channel1_BASE BDMA2_Channel1_BASE |
| |
|
#define | BDMA_Channel2_BASE BDMA2_Channel2_BASE |
| |
|
#define | BDMA_Channel3_BASE BDMA2_Channel3_BASE |
| |
|
#define | BDMA_Channel4_BASE BDMA2_Channel4_BASE |
| |
|
#define | BDMA_Channel5_BASE BDMA2_Channel5_BASE |
| |
|
#define | BDMA_Channel6_BASE BDMA2_Channel6_BASE |
| |
|
#define | BDMA_Channel7_BASE BDMA2_Channel7_BASE |
| |
|
#define | BDMA BDMA2 |
| |
|
#define | BDMA_Channel0 BDMA2_Channel0 |
| |
|
#define | BDMA_Channel1 BDMA2_Channel1 |
| |
|
#define | BDMA_Channel2 BDMA2_Channel2 |
| |
|
#define | BDMA_Channel3 BDMA2_Channel3 |
| |
|
#define | BDMA_Channel4 BDMA2_Channel4 |
| |
|
#define | BDMA_Channel5 BDMA2_Channel5 |
| |
|
#define | BDMA_Channel6 BDMA2_Channel6 |
| |
|
#define | BDMA_Channel7 BDMA2_Channel7 |
| |
|
#define | PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_SRD |
| |
|
#define | PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_SRD |
| |
|
#define | PWR_CPUCR_PDDS_D1 PWR_CPUCR_RETDS_CD |
| |
|
#define | PWR_D3CR_VOS PWR_SRDCR_VOS |
| |
|
#define | PWR_D3CR_VOS_0 PWR_SRDCR_VOS_0 |
| |
|
#define | PWR_D3CR_VOS_1 PWR_SRDCR_VOS_1 |
| |
|
#define | PWR_D3CR_VOSRDY PWR_SRDCR_VOSRDY |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
|
#define | IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
| #define | IS_DAC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
|
#define | IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (15U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
|
#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
|
#define | IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | RNG_IRQn HASH_RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | BDMA_Channel0_IRQn BDMA2_Channel0_IRQn |
| |
|
#define | BDMA_Channel1_IRQn BDMA2_Channel1_IRQn |
| |
|
#define | BDMA_Channel2_IRQn BDMA2_Channel2_IRQn |
| |
|
#define | BDMA_Channel3_IRQn BDMA2_Channel3_IRQn |
| |
|
#define | BDMA_Channel4_IRQn BDMA2_Channel4_IRQn |
| |
|
#define | BDMA_Channel5_IRQn BDMA2_Channel5_IRQn |
| |
|
#define | BDMA_Channel6_IRQn BDMA2_Channel6_IRQn |
| |
|
#define | BDMA_Channel7_IRQn BDMA2_Channel7_IRQn |
| |
|
#define | PVD_AVD_IRQn PVD_PVM_IRQn |
| |
|
#define | DCMI_IRQn DCMI_PSSI_IRQn |
| |
|
#define | RNG_IRQHandler HASH_RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | BDMA_Channel0_IRQHandler BDMA2_Channel0_IRQHandler |
| |
|
#define | BDMA_Channel1_IRQHandler BDMA2_Channel1_IRQHandler |
| |
|
#define | BDMA_Channel2_IRQHandler BDMA2_Channel2_IRQHandler |
| |
|
#define | BDMA_Channel3_IRQHandler BDMA2_Channel3_IRQHandler |
| |
|
#define | BDMA_Channel4_IRQHandler BDMA2_Channel4_IRQHandler |
| |
|
#define | BDMA_Channel5_IRQHandler BDMA2_Channel5_IRQHandler |
| |
|
#define | BDMA_Channel6_IRQHandler BDMA2_Channel6_IRQHandler |
| |
|
#define | BDMA_Channel7_IRQHandler BDMA2_Channel7_IRQHandler |
| |
|
#define | PVD_AVD_IRQHandler PVD_PVM_IRQHandler |
| |
|
#define | DCMI_IRQHandler DCMI_PSSI_IRQHandler |
| |
|
#define | BDMA_BASE BDMA2_BASE |
| |
|
#define | BDMA_Channel0_BASE BDMA2_Channel0_BASE |
| |
|
#define | BDMA_Channel1_BASE BDMA2_Channel1_BASE |
| |
|
#define | BDMA_Channel2_BASE BDMA2_Channel2_BASE |
| |
|
#define | BDMA_Channel3_BASE BDMA2_Channel3_BASE |
| |
|
#define | BDMA_Channel4_BASE BDMA2_Channel4_BASE |
| |
|
#define | BDMA_Channel5_BASE BDMA2_Channel5_BASE |
| |
|
#define | BDMA_Channel6_BASE BDMA2_Channel6_BASE |
| |
|
#define | BDMA_Channel7_BASE BDMA2_Channel7_BASE |
| |
|
#define | BDMA BDMA2 |
| |
|
#define | BDMA_Channel0 BDMA2_Channel0 |
| |
|
#define | BDMA_Channel1 BDMA2_Channel1 |
| |
|
#define | BDMA_Channel2 BDMA2_Channel2 |
| |
|
#define | BDMA_Channel3 BDMA2_Channel3 |
| |
|
#define | BDMA_Channel4 BDMA2_Channel4 |
| |
|
#define | BDMA_Channel5 BDMA2_Channel5 |
| |
|
#define | BDMA_Channel6 BDMA2_Channel6 |
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|
#define | BDMA_Channel7 BDMA2_Channel7 |
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|
#define | PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_SRD |
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|
#define | PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_SRD |
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|
#define | PWR_CPUCR_PDDS_D1 PWR_CPUCR_RETDS_CD |
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|
#define | PWR_D3CR_VOS PWR_SRDCR_VOS |
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|
#define | PWR_D3CR_VOS_0 PWR_SRDCR_VOS_0 |
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|
#define | PWR_D3CR_VOS_1 PWR_SRDCR_VOS_1 |
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|
#define | PWR_D3CR_VOSRDY PWR_SRDCR_VOSRDY |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
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|
#define | IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
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|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
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|
#define | IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
| #define | IS_DAC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) |
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|
#define | IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
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|
#define | IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
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|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
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|
#define | HSEM_SEMID_MAX (15U) /* HSEM ID Max */ |
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|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
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|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
|
#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
|
#define | IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | RNG_IRQn HASH_RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | BDMA_Channel0_IRQn BDMA2_Channel0_IRQn |
| |
|
#define | BDMA_Channel1_IRQn BDMA2_Channel1_IRQn |
| |
|
#define | BDMA_Channel2_IRQn BDMA2_Channel2_IRQn |
| |
|
#define | BDMA_Channel3_IRQn BDMA2_Channel3_IRQn |
| |
|
#define | BDMA_Channel4_IRQn BDMA2_Channel4_IRQn |
| |
|
#define | BDMA_Channel5_IRQn BDMA2_Channel5_IRQn |
| |
|
#define | BDMA_Channel6_IRQn BDMA2_Channel6_IRQn |
| |
|
#define | BDMA_Channel7_IRQn BDMA2_Channel7_IRQn |
| |
|
#define | PVD_AVD_IRQn PVD_PVM_IRQn |
| |
|
#define | DCMI_IRQn DCMI_PSSI_IRQn |
| |
|
#define | RNG_IRQHandler HASH_RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | BDMA_Channel0_IRQHandler BDMA2_Channel0_IRQHandler |
| |
|
#define | BDMA_Channel1_IRQHandler BDMA2_Channel1_IRQHandler |
| |
|
#define | BDMA_Channel2_IRQHandler BDMA2_Channel2_IRQHandler |
| |
|
#define | BDMA_Channel3_IRQHandler BDMA2_Channel3_IRQHandler |
| |
|
#define | BDMA_Channel4_IRQHandler BDMA2_Channel4_IRQHandler |
| |
|
#define | BDMA_Channel5_IRQHandler BDMA2_Channel5_IRQHandler |
| |
|
#define | BDMA_Channel6_IRQHandler BDMA2_Channel6_IRQHandler |
| |
|
#define | BDMA_Channel7_IRQHandler BDMA2_Channel7_IRQHandler |
| |
|
#define | PVD_AVD_IRQHandler PVD_PVM_IRQHandler |
| |
|
#define | DCMI_IRQHandler DCMI_PSSI_IRQHandler |
| |
|
#define | BDMA_BASE BDMA2_BASE |
| |
|
#define | BDMA_Channel0_BASE BDMA2_Channel0_BASE |
| |
|
#define | BDMA_Channel1_BASE BDMA2_Channel1_BASE |
| |
|
#define | BDMA_Channel2_BASE BDMA2_Channel2_BASE |
| |
|
#define | BDMA_Channel3_BASE BDMA2_Channel3_BASE |
| |
|
#define | BDMA_Channel4_BASE BDMA2_Channel4_BASE |
| |
|
#define | BDMA_Channel5_BASE BDMA2_Channel5_BASE |
| |
|
#define | BDMA_Channel6_BASE BDMA2_Channel6_BASE |
| |
|
#define | BDMA_Channel7_BASE BDMA2_Channel7_BASE |
| |
|
#define | BDMA BDMA2 |
| |
|
#define | BDMA_Channel0 BDMA2_Channel0 |
| |
|
#define | BDMA_Channel1 BDMA2_Channel1 |
| |
|
#define | BDMA_Channel2 BDMA2_Channel2 |
| |
|
#define | BDMA_Channel3 BDMA2_Channel3 |
| |
|
#define | BDMA_Channel4 BDMA2_Channel4 |
| |
|
#define | BDMA_Channel5 BDMA2_Channel5 |
| |
|
#define | BDMA_Channel6 BDMA2_Channel6 |
| |
|
#define | BDMA_Channel7 BDMA2_Channel7 |
| |
|
#define | PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_SRD |
| |
|
#define | PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_SRD |
| |
|
#define | PWR_CPUCR_PDDS_D1 PWR_CPUCR_RETDS_CD |
| |
|
#define | PWR_D3CR_VOS PWR_SRDCR_VOS |
| |
|
#define | PWR_D3CR_VOS_0 PWR_SRDCR_VOS_0 |
| |
|
#define | PWR_D3CR_VOS_1 PWR_SRDCR_VOS_1 |
| |
|
#define | PWR_D3CR_VOSRDY PWR_SRDCR_VOSRDY |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
| |
|
#define | IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
| |
|
#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
| |
|
#define | IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS) |
| |
|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
| #define | IS_DAC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
|
#define | IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
| |
|
#define | HSEM_SEMID_MAX (15U) /* HSEM ID Max */ |
| |
|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
| |
|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
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|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
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#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
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#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
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#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
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#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
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#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
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| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
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#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
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| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
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#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
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#define | IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
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#define | IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
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#define | RNG_IRQn HASH_RNG_IRQn |
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#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
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#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
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#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
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#define | PVD_IRQn PVD_AVD_IRQn |
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#define | BDMA_Channel0_IRQn BDMA2_Channel0_IRQn |
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#define | BDMA_Channel1_IRQn BDMA2_Channel1_IRQn |
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#define | BDMA_Channel2_IRQn BDMA2_Channel2_IRQn |
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#define | BDMA_Channel3_IRQn BDMA2_Channel3_IRQn |
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#define | BDMA_Channel4_IRQn BDMA2_Channel4_IRQn |
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#define | BDMA_Channel5_IRQn BDMA2_Channel5_IRQn |
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#define | BDMA_Channel6_IRQn BDMA2_Channel6_IRQn |
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#define | BDMA_Channel7_IRQn BDMA2_Channel7_IRQn |
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#define | PVD_AVD_IRQn PVD_PVM_IRQn |
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#define | DCMI_IRQn DCMI_PSSI_IRQn |
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#define | RNG_IRQHandler HASH_RNG_IRQHandler |
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#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
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#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
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#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
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#define | PVD_IRQHandler PVD_AVD_IRQHandler |
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#define | BDMA_Channel0_IRQHandler BDMA2_Channel0_IRQHandler |
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#define | BDMA_Channel1_IRQHandler BDMA2_Channel1_IRQHandler |
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#define | BDMA_Channel2_IRQHandler BDMA2_Channel2_IRQHandler |
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#define | BDMA_Channel3_IRQHandler BDMA2_Channel3_IRQHandler |
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#define | BDMA_Channel4_IRQHandler BDMA2_Channel4_IRQHandler |
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#define | BDMA_Channel5_IRQHandler BDMA2_Channel5_IRQHandler |
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#define | BDMA_Channel6_IRQHandler BDMA2_Channel6_IRQHandler |
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#define | BDMA_Channel7_IRQHandler BDMA2_Channel7_IRQHandler |
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#define | PVD_AVD_IRQHandler PVD_PVM_IRQHandler |
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#define | DCMI_IRQHandler DCMI_PSSI_IRQHandler |
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#define | BDMA_BASE BDMA2_BASE |
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#define | BDMA_Channel0_BASE BDMA2_Channel0_BASE |
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#define | BDMA_Channel1_BASE BDMA2_Channel1_BASE |
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#define | BDMA_Channel2_BASE BDMA2_Channel2_BASE |
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#define | BDMA_Channel3_BASE BDMA2_Channel3_BASE |
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#define | BDMA_Channel4_BASE BDMA2_Channel4_BASE |
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#define | BDMA_Channel5_BASE BDMA2_Channel5_BASE |
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#define | BDMA_Channel6_BASE BDMA2_Channel6_BASE |
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#define | BDMA_Channel7_BASE BDMA2_Channel7_BASE |
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#define | BDMA BDMA2 |
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#define | BDMA_Channel0 BDMA2_Channel0 |
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#define | BDMA_Channel1 BDMA2_Channel1 |
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#define | BDMA_Channel2 BDMA2_Channel2 |
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#define | BDMA_Channel3 BDMA2_Channel3 |
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#define | BDMA_Channel4 BDMA2_Channel4 |
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#define | BDMA_Channel5 BDMA2_Channel5 |
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#define | BDMA_Channel6 BDMA2_Channel6 |
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#define | BDMA_Channel7 BDMA2_Channel7 |
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#define | PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_SRD |
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#define | PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_SRD |
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#define | PWR_CPUCR_PDDS_D1 PWR_CPUCR_RETDS_CD |
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#define | PWR_D3CR_VOS PWR_SRDCR_VOS |
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#define | PWR_D3CR_VOS_0 PWR_SRDCR_VOS_0 |
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#define | PWR_D3CR_VOS_1 PWR_SRDCR_VOS_1 |
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#define | PWR_D3CR_VOSRDY PWR_SRDCR_VOSRDY |
| |
| #define | IS_ADC_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
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|
#define | IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON) |
| |
| #define | IS_COMP_ALL_INSTANCE(INSTANCE) |
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|
#define | IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON) |
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#define | IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2) |
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#define | IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS) |
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|
#define | IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| |
| #define | IS_DAC_ALL_INSTANCE(INSTANCE) |
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|
#define | IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI) |
| |
| #define | IS_DLYB_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) |
| |
| #define | IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D) |
| |
| #define | IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI) |
| |
| #define | IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_FDCAN_ALL_INSTANCE(__INSTANCE__) |
| |
|
#define | IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1) |
| |
|
#define | IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU) |
| |
| #define | IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM) |
| |
|
#define | HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CM7 ID */ |
| |
|
#define | HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
| |
|
#define | HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos) |
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|
#define | HSEM_SEMID_MIN (0U) /* HSEM ID Min*/ |
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|
#define | HSEM_SEMID_MAX (15U) /* HSEM ID Max */ |
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|
#define | HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */ |
| |
|
#define | HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */ |
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|
#define | HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */ |
| |
|
#define | HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */ |
| |
| #define | IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SMBUS_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_I2S_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC) |
| |
|
#define | IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG) |
| |
|
#define | IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| |
| #define | IS_SDMMC_ALL_INSTANCE(_INSTANCE_) |
| |
| #define | IS_SPI_ALL_INSTANCE(INSTANCE) |
| |
| #define | IS_SPI_HIGHEND_INSTANCE(INSTANCE) |
| |
|
#define | IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1) |
| |
| #define | IS_LPTIM_INSTANCE(INSTANCE) |
| |
| #define | IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC3_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC4_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC5_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CC6_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_XOR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMA_CC_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCDMA_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_DMABURST_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REMAP_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ETRSEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_MASTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TRGO2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_TISEL_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) |
| |
|
#define | IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_BREAK_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) |
| |
| #define | IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) |
| |
| #define | IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_BKIN2_INSTANCE(INSTANCE) |
| |
| #define | IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) |
| |
| #define | IS_USART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_FIFO_INSTANCE(INSTANCE) |
| |
| #define | IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_HWFLOW_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_LIN_INSTANCE(INSTANCE) |
| |
| #define | IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) |
| |
| #define | IS_IRDA_INSTANCE(INSTANCE) |
| |
| #define | IS_SMARTCARD_INSTANCE(INSTANCE) |
| |
|
#define | IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) |
| |
|
#define | IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1) |
| |
|
#define | IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB) |
| |
|
#define | IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1) |
| |
|
#define | IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS) |
| |
|
#define | IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC) |
| |
| #define | IS_SAI_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX) |
| |
| #define | IS_OPAMP_ALL_INSTANCE(INSTANCE) |
| |
|
#define | IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON) |
| |
|
#define | IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS) |
| |
|
#define | RNG_IRQn HASH_RNG_IRQn |
| |
|
#define | TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| |
|
#define | TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| |
|
#define | PVD_IRQn PVD_AVD_IRQn |
| |
|
#define | BDMA_Channel0_IRQn BDMA2_Channel0_IRQn |
| |
|
#define | BDMA_Channel1_IRQn BDMA2_Channel1_IRQn |
| |
|
#define | BDMA_Channel2_IRQn BDMA2_Channel2_IRQn |
| |
|
#define | BDMA_Channel3_IRQn BDMA2_Channel3_IRQn |
| |
|
#define | BDMA_Channel4_IRQn BDMA2_Channel4_IRQn |
| |
|
#define | BDMA_Channel5_IRQn BDMA2_Channel5_IRQn |
| |
|
#define | BDMA_Channel6_IRQn BDMA2_Channel6_IRQn |
| |
|
#define | BDMA_Channel7_IRQn BDMA2_Channel7_IRQn |
| |
|
#define | PVD_AVD_IRQn PVD_PVM_IRQn |
| |
|
#define | DCMI_IRQn DCMI_PSSI_IRQn |
| |
|
#define | RNG_IRQHandler HASH_RNG_IRQHandler |
| |
|
#define | TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| |
|
#define | TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler |
| |
|
#define | TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| |
|
#define | PVD_IRQHandler PVD_AVD_IRQHandler |
| |
|
#define | BDMA_Channel0_IRQHandler BDMA2_Channel0_IRQHandler |
| |
|
#define | BDMA_Channel1_IRQHandler BDMA2_Channel1_IRQHandler |
| |
|
#define | BDMA_Channel2_IRQHandler BDMA2_Channel2_IRQHandler |
| |
|
#define | BDMA_Channel3_IRQHandler BDMA2_Channel3_IRQHandler |
| |
|
#define | BDMA_Channel4_IRQHandler BDMA2_Channel4_IRQHandler |
| |
|
#define | BDMA_Channel5_IRQHandler BDMA2_Channel5_IRQHandler |
| |
|
#define | BDMA_Channel6_IRQHandler BDMA2_Channel6_IRQHandler |
| |
|
#define | BDMA_Channel7_IRQHandler BDMA2_Channel7_IRQHandler |
| |
|
#define | PVD_AVD_IRQHandler PVD_PVM_IRQHandler |
| |
|
#define | DCMI_IRQHandler DCMI_PSSI_IRQHandler |
| |
|
#define | BDMA_BASE BDMA2_BASE |
| |
|
#define | BDMA_Channel0_BASE BDMA2_Channel0_BASE |
| |
|
#define | BDMA_Channel1_BASE BDMA2_Channel1_BASE |
| |
|
#define | BDMA_Channel2_BASE BDMA2_Channel2_BASE |
| |
|
#define | BDMA_Channel3_BASE BDMA2_Channel3_BASE |
| |
|
#define | BDMA_Channel4_BASE BDMA2_Channel4_BASE |
| |
|
#define | BDMA_Channel5_BASE BDMA2_Channel5_BASE |
| |
|
#define | BDMA_Channel6_BASE BDMA2_Channel6_BASE |
| |
|
#define | BDMA_Channel7_BASE BDMA2_Channel7_BASE |
| |
|
#define | BDMA BDMA2 |
| |
|
#define | BDMA_Channel0 BDMA2_Channel0 |
| |
|
#define | BDMA_Channel1 BDMA2_Channel1 |
| |
|
#define | BDMA_Channel2 BDMA2_Channel2 |
| |
|
#define | BDMA_Channel3 BDMA2_Channel3 |
| |
|
#define | BDMA_Channel4 BDMA2_Channel4 |
| |
|
#define | BDMA_Channel5 BDMA2_Channel5 |
| |
|
#define | BDMA_Channel6 BDMA2_Channel6 |
| |
|
#define | BDMA_Channel7 BDMA2_Channel7 |
| |
|
#define | PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_SRD |
| |
|
#define | PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_SRD |
| |
|
#define | PWR_CPUCR_PDDS_D1 PWR_CPUCR_RETDS_CD |
| |
|
#define | PWR_D3CR_VOS PWR_SRDCR_VOS |
| |
|
#define | PWR_D3CR_VOS_0 PWR_SRDCR_VOS_0 |
| |
|
#define | PWR_D3CR_VOS_1 PWR_SRDCR_VOS_1 |
| |
|
#define | PWR_D3CR_VOSRDY PWR_SRDCR_VOSRDY |
| |
|
#define | SET_BIT(REG, BIT) ((REG) |= (BIT)) |
| |
|
#define | CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) |
| |
|
#define | READ_BIT(REG, BIT) ((REG) & (BIT)) |
| |
|
#define | CLEAR_REG(REG) ((REG) = (0x0)) |
| |
|
#define | WRITE_REG(REG, VAL) ((REG) = (VAL)) |
| |
|
#define | READ_REG(REG) ((REG)) |
| |
|
#define | MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) |
| |
|
#define | POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) |
| |
| #define | ATOMIC_SET_BIT(REG, BIT) |
| |
| #define | ATOMIC_CLEAR_BIT(REG, BIT) |
| |
| #define | ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) |
| |
| #define | ATOMIC_SETH_BIT(REG, BIT) |
| |
| #define | ATOMIC_CLEARH_BIT(REG, BIT) |
| |
| #define | ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) |
| |
1.9.6