EMVSIM Register Masks

VER_ID - Version ID Register
#define	EMVSIM_VER_ID_VER_MASK   (0xFFFFFFFFU)
#define	EMVSIM_VER_ID_VER_SHIFT   (0U)
#define	EMVSIM_VER_ID_VER(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)

PARAM - Parameter Register
#define	EMVSIM_PARAM_RX_FIFO_DEPTH_MASK   (0xFFU)
#define	EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT   (0U)
#define	EMVSIM_PARAM_RX_FIFO_DEPTH(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
#define	EMVSIM_PARAM_TX_FIFO_DEPTH_MASK   (0xFF00U)
#define	EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT   (8U)
#define	EMVSIM_PARAM_TX_FIFO_DEPTH(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)

CLKCFG - Clock Configuration Register
#define	EMVSIM_CLKCFG_CLK_PRSC_MASK   (0xFFU)
#define	EMVSIM_CLKCFG_CLK_PRSC_SHIFT   (0U)
#define	EMVSIM_CLKCFG_CLK_PRSC(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
#define	EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK   (0x300U)
#define	EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT   (8U)
#define	EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
#define	EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK   (0xC00U)
#define	EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT   (10U)
#define	EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)

DIVISOR - Baud Rate Divisor Register
#define	EMVSIM_DIVISOR_DIVISOR_VALUE_MASK   (0x1FFU)
#define	EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT   (0U)
#define	EMVSIM_DIVISOR_DIVISOR_VALUE(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)

CTRL - Control Register
#define	EMVSIM_CTRL_IC_MASK   (0x1U)
#define	EMVSIM_CTRL_IC_SHIFT   (0U)
#define	EMVSIM_CTRL_IC(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
#define	EMVSIM_CTRL_ICM_MASK   (0x2U)
#define	EMVSIM_CTRL_ICM_SHIFT   (1U)
#define	EMVSIM_CTRL_ICM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
#define	EMVSIM_CTRL_ANACK_MASK   (0x4U)
#define	EMVSIM_CTRL_ANACK_SHIFT   (2U)
#define	EMVSIM_CTRL_ANACK(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
#define	EMVSIM_CTRL_ONACK_MASK   (0x8U)
#define	EMVSIM_CTRL_ONACK_SHIFT   (3U)
#define	EMVSIM_CTRL_ONACK(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
#define	EMVSIM_CTRL_FLSH_RX_MASK   (0x100U)
#define	EMVSIM_CTRL_FLSH_RX_SHIFT   (8U)
#define	EMVSIM_CTRL_FLSH_RX(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
#define	EMVSIM_CTRL_FLSH_TX_MASK   (0x200U)
#define	EMVSIM_CTRL_FLSH_TX_SHIFT   (9U)
#define	EMVSIM_CTRL_FLSH_TX(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
#define	EMVSIM_CTRL_SW_RST_MASK   (0x400U)
#define	EMVSIM_CTRL_SW_RST_SHIFT   (10U)
#define	EMVSIM_CTRL_SW_RST(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
#define	EMVSIM_CTRL_KILL_CLOCKS_MASK   (0x800U)
#define	EMVSIM_CTRL_KILL_CLOCKS_SHIFT   (11U)
#define	EMVSIM_CTRL_KILL_CLOCKS(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
#define	EMVSIM_CTRL_DOZE_EN_MASK   (0x1000U)
#define	EMVSIM_CTRL_DOZE_EN_SHIFT   (12U)
#define	EMVSIM_CTRL_DOZE_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
#define	EMVSIM_CTRL_STOP_EN_MASK   (0x2000U)
#define	EMVSIM_CTRL_STOP_EN_SHIFT   (13U)
#define	EMVSIM_CTRL_STOP_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
#define	EMVSIM_CTRL_RCV_EN_MASK   (0x10000U)
#define	EMVSIM_CTRL_RCV_EN_SHIFT   (16U)
#define	EMVSIM_CTRL_RCV_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
#define	EMVSIM_CTRL_XMT_EN_MASK   (0x20000U)
#define	EMVSIM_CTRL_XMT_EN_SHIFT   (17U)
#define	EMVSIM_CTRL_XMT_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
#define	EMVSIM_CTRL_RCVR_11_MASK   (0x40000U)
#define	EMVSIM_CTRL_RCVR_11_SHIFT   (18U)
#define	EMVSIM_CTRL_RCVR_11(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
#define	EMVSIM_CTRL_RX_DMA_EN_MASK   (0x80000U)
#define	EMVSIM_CTRL_RX_DMA_EN_SHIFT   (19U)
#define	EMVSIM_CTRL_RX_DMA_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
#define	EMVSIM_CTRL_TX_DMA_EN_MASK   (0x100000U)
#define	EMVSIM_CTRL_TX_DMA_EN_SHIFT   (20U)
#define	EMVSIM_CTRL_TX_DMA_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
#define	EMVSIM_CTRL_INV_CRC_VAL_MASK   (0x1000000U)
#define	EMVSIM_CTRL_INV_CRC_VAL_SHIFT   (24U)
#define	EMVSIM_CTRL_INV_CRC_VAL(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
#define	EMVSIM_CTRL_CRC_OUT_FLIP_MASK   (0x2000000U)
#define	EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT   (25U)
#define	EMVSIM_CTRL_CRC_OUT_FLIP(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
#define	EMVSIM_CTRL_CRC_IN_FLIP_MASK   (0x4000000U)
#define	EMVSIM_CTRL_CRC_IN_FLIP_SHIFT   (26U)
#define	EMVSIM_CTRL_CRC_IN_FLIP(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
#define	EMVSIM_CTRL_CWT_EN_MASK   (0x8000000U)
#define	EMVSIM_CTRL_CWT_EN_SHIFT   (27U)
#define	EMVSIM_CTRL_CWT_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
#define	EMVSIM_CTRL_LRC_EN_MASK   (0x10000000U)
#define	EMVSIM_CTRL_LRC_EN_SHIFT   (28U)
#define	EMVSIM_CTRL_LRC_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
#define	EMVSIM_CTRL_CRC_EN_MASK   (0x20000000U)
#define	EMVSIM_CTRL_CRC_EN_SHIFT   (29U)
#define	EMVSIM_CTRL_CRC_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
#define	EMVSIM_CTRL_XMT_CRC_LRC_MASK   (0x40000000U)
#define	EMVSIM_CTRL_XMT_CRC_LRC_SHIFT   (30U)
#define	EMVSIM_CTRL_XMT_CRC_LRC(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
#define	EMVSIM_CTRL_BWT_EN_MASK   (0x80000000U)
#define	EMVSIM_CTRL_BWT_EN_SHIFT   (31U)
#define	EMVSIM_CTRL_BWT_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
#define	ENC_CTRL_CMPIE_MASK   (0x1U)
#define	ENC_CTRL_CMPIE_SHIFT   (0U)
#define	ENC_CTRL_CMPIE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
#define	ENC_CTRL_CMPIRQ_MASK   (0x2U)
#define	ENC_CTRL_CMPIRQ_SHIFT   (1U)
#define	ENC_CTRL_CMPIRQ(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
#define	ENC_CTRL_WDE_MASK   (0x4U)
#define	ENC_CTRL_WDE_SHIFT   (2U)
#define	ENC_CTRL_WDE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
#define	ENC_CTRL_DIE_MASK   (0x8U)
#define	ENC_CTRL_DIE_SHIFT   (3U)
#define	ENC_CTRL_DIE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
#define	ENC_CTRL_DIRQ_MASK   (0x10U)
#define	ENC_CTRL_DIRQ_SHIFT   (4U)
#define	ENC_CTRL_DIRQ(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
#define	ENC_CTRL_XNE_MASK   (0x20U)
#define	ENC_CTRL_XNE_SHIFT   (5U)
#define	ENC_CTRL_XNE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
#define	ENC_CTRL_XIP_MASK   (0x40U)
#define	ENC_CTRL_XIP_SHIFT   (6U)
#define	ENC_CTRL_XIP(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
#define	ENC_CTRL_XIE_MASK   (0x80U)
#define	ENC_CTRL_XIE_SHIFT   (7U)
#define	ENC_CTRL_XIE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
#define	ENC_CTRL_XIRQ_MASK   (0x100U)
#define	ENC_CTRL_XIRQ_SHIFT   (8U)
#define	ENC_CTRL_XIRQ(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
#define	ENC_CTRL_PH1_MASK   (0x200U)
#define	ENC_CTRL_PH1_SHIFT   (9U)
#define	ENC_CTRL_PH1(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
#define	ENC_CTRL_REV_MASK   (0x400U)
#define	ENC_CTRL_REV_SHIFT   (10U)
#define	ENC_CTRL_REV(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
#define	ENC_CTRL_SWIP_MASK   (0x800U)
#define	ENC_CTRL_SWIP_SHIFT   (11U)
#define	ENC_CTRL_SWIP(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
#define	ENC_CTRL_HNE_MASK   (0x1000U)
#define	ENC_CTRL_HNE_SHIFT   (12U)
#define	ENC_CTRL_HNE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
#define	ENC_CTRL_HIP_MASK   (0x2000U)
#define	ENC_CTRL_HIP_SHIFT   (13U)
#define	ENC_CTRL_HIP(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
#define	ENC_CTRL_HIE_MASK   (0x4000U)
#define	ENC_CTRL_HIE_SHIFT   (14U)
#define	ENC_CTRL_HIE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
#define	ENC_CTRL_HIRQ_MASK   (0x8000U)
#define	ENC_CTRL_HIRQ_SHIFT   (15U)
#define	ENC_CTRL_HIRQ(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
#define	EWM_CTRL_EWMEN_MASK   (0x1U)
#define	EWM_CTRL_EWMEN_SHIFT   (0U)
#define	EWM_CTRL_EWMEN(x)   (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
#define	EWM_CTRL_ASSIN_MASK   (0x2U)
#define	EWM_CTRL_ASSIN_SHIFT   (1U)
#define	EWM_CTRL_ASSIN(x)   (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
#define	EWM_CTRL_INEN_MASK   (0x4U)
#define	EWM_CTRL_INEN_SHIFT   (2U)
#define	EWM_CTRL_INEN(x)   (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
#define	EWM_CTRL_INTEN_MASK   (0x8U)
#define	EWM_CTRL_INTEN_SHIFT   (3U)
#define	EWM_CTRL_INTEN(x)   (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
#define	PWM_CTRL_DBLEN_MASK   (0x1U)
#define	PWM_CTRL_DBLEN_SHIFT   (0U)
#define	PWM_CTRL_DBLEN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
#define	PWM_CTRL_DBLX_MASK   (0x2U)
#define	PWM_CTRL_DBLX_SHIFT   (1U)
#define	PWM_CTRL_DBLX(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
#define	PWM_CTRL_LDMOD_MASK   (0x4U)
#define	PWM_CTRL_LDMOD_SHIFT   (2U)
#define	PWM_CTRL_LDMOD(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
#define	PWM_CTRL_SPLIT_MASK   (0x8U)
#define	PWM_CTRL_SPLIT_SHIFT   (3U)
#define	PWM_CTRL_SPLIT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
#define	PWM_CTRL_PRSC_MASK   (0x70U)
#define	PWM_CTRL_PRSC_SHIFT   (4U)
#define	PWM_CTRL_PRSC(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
#define	PWM_CTRL_COMPMODE_MASK   (0x80U)
#define	PWM_CTRL_COMPMODE_SHIFT   (7U)
#define	PWM_CTRL_COMPMODE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
#define	PWM_CTRL_DT_MASK   (0x300U)
#define	PWM_CTRL_DT_SHIFT   (8U)
#define	PWM_CTRL_DT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
#define	PWM_CTRL_FULL_MASK   (0x400U)
#define	PWM_CTRL_FULL_SHIFT   (10U)
#define	PWM_CTRL_FULL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
#define	PWM_CTRL_HALF_MASK   (0x800U)
#define	PWM_CTRL_HALF_SHIFT   (11U)
#define	PWM_CTRL_HALF(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
#define	PWM_CTRL_LDFQ_MASK   (0xF000U)
#define	PWM_CTRL_LDFQ_SHIFT   (12U)
#define	PWM_CTRL_LDFQ(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
#define	SRAM_CTRL_RAM_RD_EN_MASK   (0x1U)
#define	SRAM_CTRL_RAM_RD_EN_SHIFT   (0U)
#define	SRAM_CTRL_RAM_RD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_RD_EN_SHIFT)) & SRAM_CTRL_RAM_RD_EN_MASK)
#define	SRAM_CTRL_RAM_WR_EN_MASK   (0x2U)
#define	SRAM_CTRL_RAM_WR_EN_SHIFT   (1U)
#define	SRAM_CTRL_RAM_WR_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_WR_EN_SHIFT)) & SRAM_CTRL_RAM_WR_EN_MASK)
#define	SRAM_CTRL_PWR_EN_MASK   (0x3CU)
#define	SRAM_CTRL_PWR_EN_SHIFT   (2U)
#define	SRAM_CTRL_PWR_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_PWR_EN_SHIFT)) & SRAM_CTRL_PWR_EN_MASK)
#define	SRAM_CTRL_TAMPER_BLOCK_EN_MASK   (0x40U)
#define	SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT   (6U)
#define	SRAM_CTRL_TAMPER_BLOCK_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT)) & SRAM_CTRL_TAMPER_BLOCK_EN_MASK)
#define	SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK   (0x80U)
#define	SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT   (7U)
#define	SRAM_CTRL_TAMPER_PWR_OFF_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT)) & SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK)
#define	SRAM_CTRL_LOCK_BIT_MASK   (0xFF0000U)
#define	SRAM_CTRL_LOCK_BIT_SHIFT   (16U)
#define	SRAM_CTRL_LOCK_BIT(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_LOCK_BIT_SHIFT)) & SRAM_CTRL_LOCK_BIT_MASK)
#define	SSARC_LP_CTRL_DIS_HW_REQ_MASK   (0x8000000U)
#define	SSARC_LP_CTRL_DIS_HW_REQ_SHIFT   (27U)
#define	SSARC_LP_CTRL_DIS_HW_REQ(x)   (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_DIS_HW_REQ_SHIFT)) & SSARC_LP_CTRL_DIS_HW_REQ_MASK)
#define	SSARC_LP_CTRL_SW_RESET_MASK   (0x80000000U)
#define	SSARC_LP_CTRL_SW_RESET_SHIFT   (31U)
#define	SSARC_LP_CTRL_SW_RESET(x)   (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_SW_RESET_SHIFT)) & SSARC_LP_CTRL_SW_RESET_MASK)

INT_MASK - Interrupt Mask Register
#define	EMVSIM_INT_MASK_RDT_IM_MASK   (0x1U)
#define	EMVSIM_INT_MASK_RDT_IM_SHIFT   (0U)
#define	EMVSIM_INT_MASK_RDT_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
#define	EMVSIM_INT_MASK_TC_IM_MASK   (0x2U)
#define	EMVSIM_INT_MASK_TC_IM_SHIFT   (1U)
#define	EMVSIM_INT_MASK_TC_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
#define	EMVSIM_INT_MASK_RFO_IM_MASK   (0x4U)
#define	EMVSIM_INT_MASK_RFO_IM_SHIFT   (2U)
#define	EMVSIM_INT_MASK_RFO_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
#define	EMVSIM_INT_MASK_ETC_IM_MASK   (0x8U)
#define	EMVSIM_INT_MASK_ETC_IM_SHIFT   (3U)
#define	EMVSIM_INT_MASK_ETC_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
#define	EMVSIM_INT_MASK_TFE_IM_MASK   (0x10U)
#define	EMVSIM_INT_MASK_TFE_IM_SHIFT   (4U)
#define	EMVSIM_INT_MASK_TFE_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
#define	EMVSIM_INT_MASK_TNACK_IM_MASK   (0x20U)
#define	EMVSIM_INT_MASK_TNACK_IM_SHIFT   (5U)
#define	EMVSIM_INT_MASK_TNACK_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
#define	EMVSIM_INT_MASK_TFF_IM_MASK   (0x40U)
#define	EMVSIM_INT_MASK_TFF_IM_SHIFT   (6U)
#define	EMVSIM_INT_MASK_TFF_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
#define	EMVSIM_INT_MASK_TDT_IM_MASK   (0x80U)
#define	EMVSIM_INT_MASK_TDT_IM_SHIFT   (7U)
#define	EMVSIM_INT_MASK_TDT_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
#define	EMVSIM_INT_MASK_GPCNT0_IM_MASK   (0x100U)
#define	EMVSIM_INT_MASK_GPCNT0_IM_SHIFT   (8U)
#define	EMVSIM_INT_MASK_GPCNT0_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
#define	EMVSIM_INT_MASK_CWT_ERR_IM_MASK   (0x200U)
#define	EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT   (9U)
#define	EMVSIM_INT_MASK_CWT_ERR_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
#define	EMVSIM_INT_MASK_RNACK_IM_MASK   (0x400U)
#define	EMVSIM_INT_MASK_RNACK_IM_SHIFT   (10U)
#define	EMVSIM_INT_MASK_RNACK_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
#define	EMVSIM_INT_MASK_BWT_ERR_IM_MASK   (0x800U)
#define	EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT   (11U)
#define	EMVSIM_INT_MASK_BWT_ERR_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
#define	EMVSIM_INT_MASK_BGT_ERR_IM_MASK   (0x1000U)
#define	EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT   (12U)
#define	EMVSIM_INT_MASK_BGT_ERR_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
#define	EMVSIM_INT_MASK_GPCNT1_IM_MASK   (0x2000U)
#define	EMVSIM_INT_MASK_GPCNT1_IM_SHIFT   (13U)
#define	EMVSIM_INT_MASK_GPCNT1_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
#define	EMVSIM_INT_MASK_RX_DATA_IM_MASK   (0x4000U)
#define	EMVSIM_INT_MASK_RX_DATA_IM_SHIFT   (14U)
#define	EMVSIM_INT_MASK_RX_DATA_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
#define	EMVSIM_INT_MASK_PEF_IM_MASK   (0x8000U)
#define	EMVSIM_INT_MASK_PEF_IM_SHIFT   (15U)
#define	EMVSIM_INT_MASK_PEF_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)

RX_THD - Receiver Threshold Register
#define	EMVSIM_RX_THD_RDT_MASK   (0xFU)
#define	EMVSIM_RX_THD_RDT_SHIFT   (0U)
#define	EMVSIM_RX_THD_RDT(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
#define	EMVSIM_RX_THD_RNCK_THD_MASK   (0xF00U)
#define	EMVSIM_RX_THD_RNCK_THD_SHIFT   (8U)
#define	EMVSIM_RX_THD_RNCK_THD(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)

TX_THD - Transmitter Threshold Register
#define	EMVSIM_TX_THD_TDT_MASK   (0xFU)
#define	EMVSIM_TX_THD_TDT_SHIFT   (0U)
#define	EMVSIM_TX_THD_TDT(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
#define	EMVSIM_TX_THD_TNCK_THD_MASK   (0xF00U)
#define	EMVSIM_TX_THD_TNCK_THD_SHIFT   (8U)
#define	EMVSIM_TX_THD_TNCK_THD(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)

RX_STATUS - Receive Status Register
#define	EMVSIM_RX_STATUS_RFO_MASK   (0x1U)
#define	EMVSIM_RX_STATUS_RFO_SHIFT   (0U)
#define	EMVSIM_RX_STATUS_RFO(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
#define	EMVSIM_RX_STATUS_RX_DATA_MASK   (0x10U)
#define	EMVSIM_RX_STATUS_RX_DATA_SHIFT   (4U)
#define	EMVSIM_RX_STATUS_RX_DATA(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
#define	EMVSIM_RX_STATUS_RDTF_MASK   (0x20U)
#define	EMVSIM_RX_STATUS_RDTF_SHIFT   (5U)
#define	EMVSIM_RX_STATUS_RDTF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
#define	EMVSIM_RX_STATUS_LRC_OK_MASK   (0x40U)
#define	EMVSIM_RX_STATUS_LRC_OK_SHIFT   (6U)
#define	EMVSIM_RX_STATUS_LRC_OK(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
#define	EMVSIM_RX_STATUS_CRC_OK_MASK   (0x80U)
#define	EMVSIM_RX_STATUS_CRC_OK_SHIFT   (7U)
#define	EMVSIM_RX_STATUS_CRC_OK(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
#define	EMVSIM_RX_STATUS_CWT_ERR_MASK   (0x100U)
#define	EMVSIM_RX_STATUS_CWT_ERR_SHIFT   (8U)
#define	EMVSIM_RX_STATUS_CWT_ERR(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
#define	EMVSIM_RX_STATUS_RTE_MASK   (0x200U)
#define	EMVSIM_RX_STATUS_RTE_SHIFT   (9U)
#define	EMVSIM_RX_STATUS_RTE(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
#define	EMVSIM_RX_STATUS_BWT_ERR_MASK   (0x400U)
#define	EMVSIM_RX_STATUS_BWT_ERR_SHIFT   (10U)
#define	EMVSIM_RX_STATUS_BWT_ERR(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
#define	EMVSIM_RX_STATUS_BGT_ERR_MASK   (0x800U)
#define	EMVSIM_RX_STATUS_BGT_ERR_SHIFT   (11U)
#define	EMVSIM_RX_STATUS_BGT_ERR(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
#define	EMVSIM_RX_STATUS_PEF_MASK   (0x1000U)
#define	EMVSIM_RX_STATUS_PEF_SHIFT   (12U)
#define	EMVSIM_RX_STATUS_PEF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
#define	EMVSIM_RX_STATUS_FEF_MASK   (0x2000U)
#define	EMVSIM_RX_STATUS_FEF_SHIFT   (13U)
#define	EMVSIM_RX_STATUS_FEF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
#define	EMVSIM_RX_STATUS_RX_WPTR_MASK   (0xF0000U)
#define	EMVSIM_RX_STATUS_RX_WPTR_SHIFT   (16U)
#define	EMVSIM_RX_STATUS_RX_WPTR(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
#define	EMVSIM_RX_STATUS_RX_CNT_MASK   (0xF000000U)
#define	EMVSIM_RX_STATUS_RX_CNT_SHIFT   (24U)
#define	EMVSIM_RX_STATUS_RX_CNT(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)

TX_STATUS - Transmitter Status Register
#define	EMVSIM_TX_STATUS_TNTE_MASK   (0x1U)
#define	EMVSIM_TX_STATUS_TNTE_SHIFT   (0U)
#define	EMVSIM_TX_STATUS_TNTE(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
#define	EMVSIM_TX_STATUS_TFE_MASK   (0x8U)
#define	EMVSIM_TX_STATUS_TFE_SHIFT   (3U)
#define	EMVSIM_TX_STATUS_TFE(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
#define	EMVSIM_TX_STATUS_ETCF_MASK   (0x10U)
#define	EMVSIM_TX_STATUS_ETCF_SHIFT   (4U)
#define	EMVSIM_TX_STATUS_ETCF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
#define	EMVSIM_TX_STATUS_TCF_MASK   (0x20U)
#define	EMVSIM_TX_STATUS_TCF_SHIFT   (5U)
#define	EMVSIM_TX_STATUS_TCF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
#define	EMVSIM_TX_STATUS_TFF_MASK   (0x40U)
#define	EMVSIM_TX_STATUS_TFF_SHIFT   (6U)
#define	EMVSIM_TX_STATUS_TFF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
#define	EMVSIM_TX_STATUS_TDTF_MASK   (0x80U)
#define	EMVSIM_TX_STATUS_TDTF_SHIFT   (7U)
#define	EMVSIM_TX_STATUS_TDTF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
#define	EMVSIM_TX_STATUS_GPCNT0_TO_MASK   (0x100U)
#define	EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT   (8U)
#define	EMVSIM_TX_STATUS_GPCNT0_TO(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
#define	EMVSIM_TX_STATUS_GPCNT1_TO_MASK   (0x200U)
#define	EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT   (9U)
#define	EMVSIM_TX_STATUS_GPCNT1_TO(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
#define	EMVSIM_TX_STATUS_TX_RPTR_MASK   (0xF0000U)
#define	EMVSIM_TX_STATUS_TX_RPTR_SHIFT   (16U)
#define	EMVSIM_TX_STATUS_TX_RPTR(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
#define	EMVSIM_TX_STATUS_TX_CNT_MASK   (0xF000000U)
#define	EMVSIM_TX_STATUS_TX_CNT_SHIFT   (24U)
#define	EMVSIM_TX_STATUS_TX_CNT(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)

PCSR - Port Control and Status Register
#define	EMVSIM_PCSR_SAPD_MASK   (0x1U)
#define	EMVSIM_PCSR_SAPD_SHIFT   (0U)
#define	EMVSIM_PCSR_SAPD(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
#define	EMVSIM_PCSR_SVCC_EN_MASK   (0x2U)
#define	EMVSIM_PCSR_SVCC_EN_SHIFT   (1U)
#define	EMVSIM_PCSR_SVCC_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
#define	EMVSIM_PCSR_VCCENP_MASK   (0x4U)
#define	EMVSIM_PCSR_VCCENP_SHIFT   (2U)
#define	EMVSIM_PCSR_VCCENP(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
#define	EMVSIM_PCSR_SRST_MASK   (0x8U)
#define	EMVSIM_PCSR_SRST_SHIFT   (3U)
#define	EMVSIM_PCSR_SRST(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
#define	EMVSIM_PCSR_SCEN_MASK   (0x10U)
#define	EMVSIM_PCSR_SCEN_SHIFT   (4U)
#define	EMVSIM_PCSR_SCEN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
#define	EMVSIM_PCSR_SCSP_MASK   (0x20U)
#define	EMVSIM_PCSR_SCSP_SHIFT   (5U)
#define	EMVSIM_PCSR_SCSP(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
#define	EMVSIM_PCSR_SPD_MASK   (0x80U)
#define	EMVSIM_PCSR_SPD_SHIFT   (7U)
#define	EMVSIM_PCSR_SPD(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
#define	EMVSIM_PCSR_SPDIM_MASK   (0x1000000U)
#define	EMVSIM_PCSR_SPDIM_SHIFT   (24U)
#define	EMVSIM_PCSR_SPDIM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
#define	EMVSIM_PCSR_SPDIF_MASK   (0x2000000U)
#define	EMVSIM_PCSR_SPDIF_SHIFT   (25U)
#define	EMVSIM_PCSR_SPDIF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
#define	EMVSIM_PCSR_SPDP_MASK   (0x4000000U)
#define	EMVSIM_PCSR_SPDP_SHIFT   (26U)
#define	EMVSIM_PCSR_SPDP(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
#define	EMVSIM_PCSR_SPDES_MASK   (0x8000000U)
#define	EMVSIM_PCSR_SPDES_SHIFT   (27U)
#define	EMVSIM_PCSR_SPDES(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)

RX_BUF - Receive Data Read Buffer
#define	EMVSIM_RX_BUF_RX_BYTE_MASK   (0xFFU)
#define	EMVSIM_RX_BUF_RX_BYTE_SHIFT   (0U)
#define	EMVSIM_RX_BUF_RX_BYTE(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)

TX_BUF - Transmit Data Buffer
#define	EMVSIM_TX_BUF_TX_BYTE_MASK   (0xFFU)
#define	EMVSIM_TX_BUF_TX_BYTE_SHIFT   (0U)
#define	EMVSIM_TX_BUF_TX_BYTE(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)

TX_GETU - Transmitter Guard ETU Value Register
#define	EMVSIM_TX_GETU_GETU_MASK   (0xFFU)
#define	EMVSIM_TX_GETU_GETU_SHIFT   (0U)
#define	EMVSIM_TX_GETU_GETU(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)

CWT_VAL - Character Wait Time Value Register
#define	EMVSIM_CWT_VAL_CWT_MASK   (0xFFFFU)
#define	EMVSIM_CWT_VAL_CWT_SHIFT   (0U)
#define	EMVSIM_CWT_VAL_CWT(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)

BWT_VAL - Block Wait Time Value Register
#define	EMVSIM_BWT_VAL_BWT_MASK   (0xFFFFFFFFU)
#define	EMVSIM_BWT_VAL_BWT_SHIFT   (0U)
#define	EMVSIM_BWT_VAL_BWT(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)

BGT_VAL - Block Guard Time Value Register
#define	EMVSIM_BGT_VAL_BGT_MASK   (0xFFFFU)
#define	EMVSIM_BGT_VAL_BGT_SHIFT   (0U)
#define	EMVSIM_BGT_VAL_BGT(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)

GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register
#define	EMVSIM_GPCNT0_VAL_GPCNT0_MASK   (0xFFFFU)
#define	EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT   (0U)
#define	EMVSIM_GPCNT0_VAL_GPCNT0(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)

GPCNT1_VAL - General Purpose Counter 1 Timeout Value
#define	EMVSIM_GPCNT1_VAL_GPCNT1_MASK   (0xFFFFU)
#define	EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT   (0U)
#define	EMVSIM_GPCNT1_VAL_GPCNT1(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)

VER_ID - Version ID Register
#define	EMVSIM_VER_ID_VER_MASK   (0xFFFFFFFFU)
#define	EMVSIM_VER_ID_VER_SHIFT   (0U)
#define	EMVSIM_VER_ID_VER(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)

PARAM - Parameter Register
#define	EMVSIM_PARAM_RX_FIFO_DEPTH_MASK   (0xFFU)
#define	EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT   (0U)
#define	EMVSIM_PARAM_RX_FIFO_DEPTH(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
#define	EMVSIM_PARAM_TX_FIFO_DEPTH_MASK   (0xFF00U)
#define	EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT   (8U)
#define	EMVSIM_PARAM_TX_FIFO_DEPTH(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)

CLKCFG - Clock Configuration Register
#define	EMVSIM_CLKCFG_CLK_PRSC_MASK   (0xFFU)
#define	EMVSIM_CLKCFG_CLK_PRSC_SHIFT   (0U)
#define	EMVSIM_CLKCFG_CLK_PRSC(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
#define	EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK   (0x300U)
#define	EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT   (8U)
#define	EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
#define	EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK   (0xC00U)
#define	EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT   (10U)
#define	EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)

DIVISOR - Baud Rate Divisor Register
#define	EMVSIM_DIVISOR_DIVISOR_VALUE_MASK   (0x1FFU)
#define	EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT   (0U)
#define	EMVSIM_DIVISOR_DIVISOR_VALUE(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)

CTRL - Control Register
#define	EMVSIM_CTRL_IC_MASK   (0x1U)
#define	EMVSIM_CTRL_IC_SHIFT   (0U)
#define	EMVSIM_CTRL_IC(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
#define	EMVSIM_CTRL_ICM_MASK   (0x2U)
#define	EMVSIM_CTRL_ICM_SHIFT   (1U)
#define	EMVSIM_CTRL_ICM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
#define	EMVSIM_CTRL_ANACK_MASK   (0x4U)
#define	EMVSIM_CTRL_ANACK_SHIFT   (2U)
#define	EMVSIM_CTRL_ANACK(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
#define	EMVSIM_CTRL_ONACK_MASK   (0x8U)
#define	EMVSIM_CTRL_ONACK_SHIFT   (3U)
#define	EMVSIM_CTRL_ONACK(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
#define	EMVSIM_CTRL_FLSH_RX_MASK   (0x100U)
#define	EMVSIM_CTRL_FLSH_RX_SHIFT   (8U)
#define	EMVSIM_CTRL_FLSH_RX(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
#define	EMVSIM_CTRL_FLSH_TX_MASK   (0x200U)
#define	EMVSIM_CTRL_FLSH_TX_SHIFT   (9U)
#define	EMVSIM_CTRL_FLSH_TX(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
#define	EMVSIM_CTRL_SW_RST_MASK   (0x400U)
#define	EMVSIM_CTRL_SW_RST_SHIFT   (10U)
#define	EMVSIM_CTRL_SW_RST(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
#define	EMVSIM_CTRL_KILL_CLOCKS_MASK   (0x800U)
#define	EMVSIM_CTRL_KILL_CLOCKS_SHIFT   (11U)
#define	EMVSIM_CTRL_KILL_CLOCKS(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
#define	EMVSIM_CTRL_DOZE_EN_MASK   (0x1000U)
#define	EMVSIM_CTRL_DOZE_EN_SHIFT   (12U)
#define	EMVSIM_CTRL_DOZE_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
#define	EMVSIM_CTRL_STOP_EN_MASK   (0x2000U)
#define	EMVSIM_CTRL_STOP_EN_SHIFT   (13U)
#define	EMVSIM_CTRL_STOP_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
#define	EMVSIM_CTRL_RCV_EN_MASK   (0x10000U)
#define	EMVSIM_CTRL_RCV_EN_SHIFT   (16U)
#define	EMVSIM_CTRL_RCV_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
#define	EMVSIM_CTRL_XMT_EN_MASK   (0x20000U)
#define	EMVSIM_CTRL_XMT_EN_SHIFT   (17U)
#define	EMVSIM_CTRL_XMT_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
#define	EMVSIM_CTRL_RCVR_11_MASK   (0x40000U)
#define	EMVSIM_CTRL_RCVR_11_SHIFT   (18U)
#define	EMVSIM_CTRL_RCVR_11(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
#define	EMVSIM_CTRL_RX_DMA_EN_MASK   (0x80000U)
#define	EMVSIM_CTRL_RX_DMA_EN_SHIFT   (19U)
#define	EMVSIM_CTRL_RX_DMA_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
#define	EMVSIM_CTRL_TX_DMA_EN_MASK   (0x100000U)
#define	EMVSIM_CTRL_TX_DMA_EN_SHIFT   (20U)
#define	EMVSIM_CTRL_TX_DMA_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
#define	EMVSIM_CTRL_INV_CRC_VAL_MASK   (0x1000000U)
#define	EMVSIM_CTRL_INV_CRC_VAL_SHIFT   (24U)
#define	EMVSIM_CTRL_INV_CRC_VAL(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
#define	EMVSIM_CTRL_CRC_OUT_FLIP_MASK   (0x2000000U)
#define	EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT   (25U)
#define	EMVSIM_CTRL_CRC_OUT_FLIP(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
#define	EMVSIM_CTRL_CRC_IN_FLIP_MASK   (0x4000000U)
#define	EMVSIM_CTRL_CRC_IN_FLIP_SHIFT   (26U)
#define	EMVSIM_CTRL_CRC_IN_FLIP(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
#define	EMVSIM_CTRL_CWT_EN_MASK   (0x8000000U)
#define	EMVSIM_CTRL_CWT_EN_SHIFT   (27U)
#define	EMVSIM_CTRL_CWT_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
#define	EMVSIM_CTRL_LRC_EN_MASK   (0x10000000U)
#define	EMVSIM_CTRL_LRC_EN_SHIFT   (28U)
#define	EMVSIM_CTRL_LRC_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
#define	EMVSIM_CTRL_CRC_EN_MASK   (0x20000000U)
#define	EMVSIM_CTRL_CRC_EN_SHIFT   (29U)
#define	EMVSIM_CTRL_CRC_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
#define	EMVSIM_CTRL_XMT_CRC_LRC_MASK   (0x40000000U)
#define	EMVSIM_CTRL_XMT_CRC_LRC_SHIFT   (30U)
#define	EMVSIM_CTRL_XMT_CRC_LRC(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
#define	EMVSIM_CTRL_BWT_EN_MASK   (0x80000000U)
#define	EMVSIM_CTRL_BWT_EN_SHIFT   (31U)
#define	EMVSIM_CTRL_BWT_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
#define	ENC_CTRL_CMPIE_MASK   (0x1U)
#define	ENC_CTRL_CMPIE_SHIFT   (0U)
#define	ENC_CTRL_CMPIE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
#define	ENC_CTRL_CMPIRQ_MASK   (0x2U)
#define	ENC_CTRL_CMPIRQ_SHIFT   (1U)
#define	ENC_CTRL_CMPIRQ(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
#define	ENC_CTRL_WDE_MASK   (0x4U)
#define	ENC_CTRL_WDE_SHIFT   (2U)
#define	ENC_CTRL_WDE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
#define	ENC_CTRL_DIE_MASK   (0x8U)
#define	ENC_CTRL_DIE_SHIFT   (3U)
#define	ENC_CTRL_DIE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
#define	ENC_CTRL_DIRQ_MASK   (0x10U)
#define	ENC_CTRL_DIRQ_SHIFT   (4U)
#define	ENC_CTRL_DIRQ(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
#define	ENC_CTRL_XNE_MASK   (0x20U)
#define	ENC_CTRL_XNE_SHIFT   (5U)
#define	ENC_CTRL_XNE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
#define	ENC_CTRL_XIP_MASK   (0x40U)
#define	ENC_CTRL_XIP_SHIFT   (6U)
#define	ENC_CTRL_XIP(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
#define	ENC_CTRL_XIE_MASK   (0x80U)
#define	ENC_CTRL_XIE_SHIFT   (7U)
#define	ENC_CTRL_XIE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
#define	ENC_CTRL_XIRQ_MASK   (0x100U)
#define	ENC_CTRL_XIRQ_SHIFT   (8U)
#define	ENC_CTRL_XIRQ(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
#define	ENC_CTRL_PH1_MASK   (0x200U)
#define	ENC_CTRL_PH1_SHIFT   (9U)
#define	ENC_CTRL_PH1(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
#define	ENC_CTRL_REV_MASK   (0x400U)
#define	ENC_CTRL_REV_SHIFT   (10U)
#define	ENC_CTRL_REV(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
#define	ENC_CTRL_SWIP_MASK   (0x800U)
#define	ENC_CTRL_SWIP_SHIFT   (11U)
#define	ENC_CTRL_SWIP(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
#define	ENC_CTRL_HNE_MASK   (0x1000U)
#define	ENC_CTRL_HNE_SHIFT   (12U)
#define	ENC_CTRL_HNE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
#define	ENC_CTRL_HIP_MASK   (0x2000U)
#define	ENC_CTRL_HIP_SHIFT   (13U)
#define	ENC_CTRL_HIP(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
#define	ENC_CTRL_HIE_MASK   (0x4000U)
#define	ENC_CTRL_HIE_SHIFT   (14U)
#define	ENC_CTRL_HIE(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
#define	ENC_CTRL_HIRQ_MASK   (0x8000U)
#define	ENC_CTRL_HIRQ_SHIFT   (15U)
#define	ENC_CTRL_HIRQ(x)   (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
#define	EWM_CTRL_EWMEN_MASK   (0x1U)
#define	EWM_CTRL_EWMEN_SHIFT   (0U)
#define	EWM_CTRL_EWMEN(x)   (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
#define	EWM_CTRL_ASSIN_MASK   (0x2U)
#define	EWM_CTRL_ASSIN_SHIFT   (1U)
#define	EWM_CTRL_ASSIN(x)   (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
#define	EWM_CTRL_INEN_MASK   (0x4U)
#define	EWM_CTRL_INEN_SHIFT   (2U)
#define	EWM_CTRL_INEN(x)   (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
#define	EWM_CTRL_INTEN_MASK   (0x8U)
#define	EWM_CTRL_INTEN_SHIFT   (3U)
#define	EWM_CTRL_INTEN(x)   (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
#define	PWM_CTRL_DBLEN_MASK   (0x1U)
#define	PWM_CTRL_DBLEN_SHIFT   (0U)
#define	PWM_CTRL_DBLEN(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
#define	PWM_CTRL_DBLX_MASK   (0x2U)
#define	PWM_CTRL_DBLX_SHIFT   (1U)
#define	PWM_CTRL_DBLX(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
#define	PWM_CTRL_LDMOD_MASK   (0x4U)
#define	PWM_CTRL_LDMOD_SHIFT   (2U)
#define	PWM_CTRL_LDMOD(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
#define	PWM_CTRL_SPLIT_MASK   (0x8U)
#define	PWM_CTRL_SPLIT_SHIFT   (3U)
#define	PWM_CTRL_SPLIT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
#define	PWM_CTRL_PRSC_MASK   (0x70U)
#define	PWM_CTRL_PRSC_SHIFT   (4U)
#define	PWM_CTRL_PRSC(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
#define	PWM_CTRL_COMPMODE_MASK   (0x80U)
#define	PWM_CTRL_COMPMODE_SHIFT   (7U)
#define	PWM_CTRL_COMPMODE(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
#define	PWM_CTRL_DT_MASK   (0x300U)
#define	PWM_CTRL_DT_SHIFT   (8U)
#define	PWM_CTRL_DT(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
#define	PWM_CTRL_FULL_MASK   (0x400U)
#define	PWM_CTRL_FULL_SHIFT   (10U)
#define	PWM_CTRL_FULL(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
#define	PWM_CTRL_HALF_MASK   (0x800U)
#define	PWM_CTRL_HALF_SHIFT   (11U)
#define	PWM_CTRL_HALF(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
#define	PWM_CTRL_LDFQ_MASK   (0xF000U)
#define	PWM_CTRL_LDFQ_SHIFT   (12U)
#define	PWM_CTRL_LDFQ(x)   (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
#define	SRAM_CTRL_RAM_RD_EN_MASK   (0x1U)
#define	SRAM_CTRL_RAM_RD_EN_SHIFT   (0U)
#define	SRAM_CTRL_RAM_RD_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_RD_EN_SHIFT)) & SRAM_CTRL_RAM_RD_EN_MASK)
#define	SRAM_CTRL_RAM_WR_EN_MASK   (0x2U)
#define	SRAM_CTRL_RAM_WR_EN_SHIFT   (1U)
#define	SRAM_CTRL_RAM_WR_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_WR_EN_SHIFT)) & SRAM_CTRL_RAM_WR_EN_MASK)
#define	SRAM_CTRL_PWR_EN_MASK   (0x3CU)
#define	SRAM_CTRL_PWR_EN_SHIFT   (2U)
#define	SRAM_CTRL_PWR_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_PWR_EN_SHIFT)) & SRAM_CTRL_PWR_EN_MASK)
#define	SRAM_CTRL_TAMPER_BLOCK_EN_MASK   (0x40U)
#define	SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT   (6U)
#define	SRAM_CTRL_TAMPER_BLOCK_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT)) & SRAM_CTRL_TAMPER_BLOCK_EN_MASK)
#define	SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK   (0x80U)
#define	SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT   (7U)
#define	SRAM_CTRL_TAMPER_PWR_OFF_EN(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT)) & SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK)
#define	SRAM_CTRL_LOCK_BIT_MASK   (0xFF0000U)
#define	SRAM_CTRL_LOCK_BIT_SHIFT   (16U)
#define	SRAM_CTRL_LOCK_BIT(x)   (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_LOCK_BIT_SHIFT)) & SRAM_CTRL_LOCK_BIT_MASK)
#define	SSARC_LP_CTRL_DIS_HW_REQ_MASK   (0x8000000U)
#define	SSARC_LP_CTRL_DIS_HW_REQ_SHIFT   (27U)
#define	SSARC_LP_CTRL_DIS_HW_REQ(x)   (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_DIS_HW_REQ_SHIFT)) & SSARC_LP_CTRL_DIS_HW_REQ_MASK)
#define	SSARC_LP_CTRL_SW_RESET_MASK   (0x80000000U)
#define	SSARC_LP_CTRL_SW_RESET_SHIFT   (31U)
#define	SSARC_LP_CTRL_SW_RESET(x)   (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_SW_RESET_SHIFT)) & SSARC_LP_CTRL_SW_RESET_MASK)

INT_MASK - Interrupt Mask Register
#define	EMVSIM_INT_MASK_RDT_IM_MASK   (0x1U)
#define	EMVSIM_INT_MASK_RDT_IM_SHIFT   (0U)
#define	EMVSIM_INT_MASK_RDT_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
#define	EMVSIM_INT_MASK_TC_IM_MASK   (0x2U)
#define	EMVSIM_INT_MASK_TC_IM_SHIFT   (1U)
#define	EMVSIM_INT_MASK_TC_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
#define	EMVSIM_INT_MASK_RFO_IM_MASK   (0x4U)
#define	EMVSIM_INT_MASK_RFO_IM_SHIFT   (2U)
#define	EMVSIM_INT_MASK_RFO_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
#define	EMVSIM_INT_MASK_ETC_IM_MASK   (0x8U)
#define	EMVSIM_INT_MASK_ETC_IM_SHIFT   (3U)
#define	EMVSIM_INT_MASK_ETC_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
#define	EMVSIM_INT_MASK_TFE_IM_MASK   (0x10U)
#define	EMVSIM_INT_MASK_TFE_IM_SHIFT   (4U)
#define	EMVSIM_INT_MASK_TFE_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
#define	EMVSIM_INT_MASK_TNACK_IM_MASK   (0x20U)
#define	EMVSIM_INT_MASK_TNACK_IM_SHIFT   (5U)
#define	EMVSIM_INT_MASK_TNACK_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
#define	EMVSIM_INT_MASK_TFF_IM_MASK   (0x40U)
#define	EMVSIM_INT_MASK_TFF_IM_SHIFT   (6U)
#define	EMVSIM_INT_MASK_TFF_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
#define	EMVSIM_INT_MASK_TDT_IM_MASK   (0x80U)
#define	EMVSIM_INT_MASK_TDT_IM_SHIFT   (7U)
#define	EMVSIM_INT_MASK_TDT_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
#define	EMVSIM_INT_MASK_GPCNT0_IM_MASK   (0x100U)
#define	EMVSIM_INT_MASK_GPCNT0_IM_SHIFT   (8U)
#define	EMVSIM_INT_MASK_GPCNT0_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
#define	EMVSIM_INT_MASK_CWT_ERR_IM_MASK   (0x200U)
#define	EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT   (9U)
#define	EMVSIM_INT_MASK_CWT_ERR_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
#define	EMVSIM_INT_MASK_RNACK_IM_MASK   (0x400U)
#define	EMVSIM_INT_MASK_RNACK_IM_SHIFT   (10U)
#define	EMVSIM_INT_MASK_RNACK_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
#define	EMVSIM_INT_MASK_BWT_ERR_IM_MASK   (0x800U)
#define	EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT   (11U)
#define	EMVSIM_INT_MASK_BWT_ERR_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
#define	EMVSIM_INT_MASK_BGT_ERR_IM_MASK   (0x1000U)
#define	EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT   (12U)
#define	EMVSIM_INT_MASK_BGT_ERR_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
#define	EMVSIM_INT_MASK_GPCNT1_IM_MASK   (0x2000U)
#define	EMVSIM_INT_MASK_GPCNT1_IM_SHIFT   (13U)
#define	EMVSIM_INT_MASK_GPCNT1_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
#define	EMVSIM_INT_MASK_RX_DATA_IM_MASK   (0x4000U)
#define	EMVSIM_INT_MASK_RX_DATA_IM_SHIFT   (14U)
#define	EMVSIM_INT_MASK_RX_DATA_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
#define	EMVSIM_INT_MASK_PEF_IM_MASK   (0x8000U)
#define	EMVSIM_INT_MASK_PEF_IM_SHIFT   (15U)
#define	EMVSIM_INT_MASK_PEF_IM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)

RX_THD - Receiver Threshold Register
#define	EMVSIM_RX_THD_RDT_MASK   (0xFU)
#define	EMVSIM_RX_THD_RDT_SHIFT   (0U)
#define	EMVSIM_RX_THD_RDT(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
#define	EMVSIM_RX_THD_RNCK_THD_MASK   (0xF00U)
#define	EMVSIM_RX_THD_RNCK_THD_SHIFT   (8U)
#define	EMVSIM_RX_THD_RNCK_THD(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)

TX_THD - Transmitter Threshold Register
#define	EMVSIM_TX_THD_TDT_MASK   (0xFU)
#define	EMVSIM_TX_THD_TDT_SHIFT   (0U)
#define	EMVSIM_TX_THD_TDT(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
#define	EMVSIM_TX_THD_TNCK_THD_MASK   (0xF00U)
#define	EMVSIM_TX_THD_TNCK_THD_SHIFT   (8U)
#define	EMVSIM_TX_THD_TNCK_THD(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)

RX_STATUS - Receive Status Register
#define	EMVSIM_RX_STATUS_RFO_MASK   (0x1U)
#define	EMVSIM_RX_STATUS_RFO_SHIFT   (0U)
#define	EMVSIM_RX_STATUS_RFO(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
#define	EMVSIM_RX_STATUS_RX_DATA_MASK   (0x10U)
#define	EMVSIM_RX_STATUS_RX_DATA_SHIFT   (4U)
#define	EMVSIM_RX_STATUS_RX_DATA(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
#define	EMVSIM_RX_STATUS_RDTF_MASK   (0x20U)
#define	EMVSIM_RX_STATUS_RDTF_SHIFT   (5U)
#define	EMVSIM_RX_STATUS_RDTF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
#define	EMVSIM_RX_STATUS_LRC_OK_MASK   (0x40U)
#define	EMVSIM_RX_STATUS_LRC_OK_SHIFT   (6U)
#define	EMVSIM_RX_STATUS_LRC_OK(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
#define	EMVSIM_RX_STATUS_CRC_OK_MASK   (0x80U)
#define	EMVSIM_RX_STATUS_CRC_OK_SHIFT   (7U)
#define	EMVSIM_RX_STATUS_CRC_OK(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
#define	EMVSIM_RX_STATUS_CWT_ERR_MASK   (0x100U)
#define	EMVSIM_RX_STATUS_CWT_ERR_SHIFT   (8U)
#define	EMVSIM_RX_STATUS_CWT_ERR(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
#define	EMVSIM_RX_STATUS_RTE_MASK   (0x200U)
#define	EMVSIM_RX_STATUS_RTE_SHIFT   (9U)
#define	EMVSIM_RX_STATUS_RTE(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
#define	EMVSIM_RX_STATUS_BWT_ERR_MASK   (0x400U)
#define	EMVSIM_RX_STATUS_BWT_ERR_SHIFT   (10U)
#define	EMVSIM_RX_STATUS_BWT_ERR(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
#define	EMVSIM_RX_STATUS_BGT_ERR_MASK   (0x800U)
#define	EMVSIM_RX_STATUS_BGT_ERR_SHIFT   (11U)
#define	EMVSIM_RX_STATUS_BGT_ERR(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
#define	EMVSIM_RX_STATUS_PEF_MASK   (0x1000U)
#define	EMVSIM_RX_STATUS_PEF_SHIFT   (12U)
#define	EMVSIM_RX_STATUS_PEF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
#define	EMVSIM_RX_STATUS_FEF_MASK   (0x2000U)
#define	EMVSIM_RX_STATUS_FEF_SHIFT   (13U)
#define	EMVSIM_RX_STATUS_FEF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
#define	EMVSIM_RX_STATUS_RX_WPTR_MASK   (0xF0000U)
#define	EMVSIM_RX_STATUS_RX_WPTR_SHIFT   (16U)
#define	EMVSIM_RX_STATUS_RX_WPTR(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
#define	EMVSIM_RX_STATUS_RX_CNT_MASK   (0xF000000U)
#define	EMVSIM_RX_STATUS_RX_CNT_SHIFT   (24U)
#define	EMVSIM_RX_STATUS_RX_CNT(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)

TX_STATUS - Transmitter Status Register
#define	EMVSIM_TX_STATUS_TNTE_MASK   (0x1U)
#define	EMVSIM_TX_STATUS_TNTE_SHIFT   (0U)
#define	EMVSIM_TX_STATUS_TNTE(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
#define	EMVSIM_TX_STATUS_TFE_MASK   (0x8U)
#define	EMVSIM_TX_STATUS_TFE_SHIFT   (3U)
#define	EMVSIM_TX_STATUS_TFE(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
#define	EMVSIM_TX_STATUS_ETCF_MASK   (0x10U)
#define	EMVSIM_TX_STATUS_ETCF_SHIFT   (4U)
#define	EMVSIM_TX_STATUS_ETCF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
#define	EMVSIM_TX_STATUS_TCF_MASK   (0x20U)
#define	EMVSIM_TX_STATUS_TCF_SHIFT   (5U)
#define	EMVSIM_TX_STATUS_TCF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
#define	EMVSIM_TX_STATUS_TFF_MASK   (0x40U)
#define	EMVSIM_TX_STATUS_TFF_SHIFT   (6U)
#define	EMVSIM_TX_STATUS_TFF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
#define	EMVSIM_TX_STATUS_TDTF_MASK   (0x80U)
#define	EMVSIM_TX_STATUS_TDTF_SHIFT   (7U)
#define	EMVSIM_TX_STATUS_TDTF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
#define	EMVSIM_TX_STATUS_GPCNT0_TO_MASK   (0x100U)
#define	EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT   (8U)
#define	EMVSIM_TX_STATUS_GPCNT0_TO(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
#define	EMVSIM_TX_STATUS_GPCNT1_TO_MASK   (0x200U)
#define	EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT   (9U)
#define	EMVSIM_TX_STATUS_GPCNT1_TO(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
#define	EMVSIM_TX_STATUS_TX_RPTR_MASK   (0xF0000U)
#define	EMVSIM_TX_STATUS_TX_RPTR_SHIFT   (16U)
#define	EMVSIM_TX_STATUS_TX_RPTR(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
#define	EMVSIM_TX_STATUS_TX_CNT_MASK   (0xF000000U)
#define	EMVSIM_TX_STATUS_TX_CNT_SHIFT   (24U)
#define	EMVSIM_TX_STATUS_TX_CNT(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)

PCSR - Port Control and Status Register
#define	EMVSIM_PCSR_SAPD_MASK   (0x1U)
#define	EMVSIM_PCSR_SAPD_SHIFT   (0U)
#define	EMVSIM_PCSR_SAPD(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
#define	EMVSIM_PCSR_SVCC_EN_MASK   (0x2U)
#define	EMVSIM_PCSR_SVCC_EN_SHIFT   (1U)
#define	EMVSIM_PCSR_SVCC_EN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
#define	EMVSIM_PCSR_VCCENP_MASK   (0x4U)
#define	EMVSIM_PCSR_VCCENP_SHIFT   (2U)
#define	EMVSIM_PCSR_VCCENP(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
#define	EMVSIM_PCSR_SRST_MASK   (0x8U)
#define	EMVSIM_PCSR_SRST_SHIFT   (3U)
#define	EMVSIM_PCSR_SRST(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
#define	EMVSIM_PCSR_SCEN_MASK   (0x10U)
#define	EMVSIM_PCSR_SCEN_SHIFT   (4U)
#define	EMVSIM_PCSR_SCEN(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
#define	EMVSIM_PCSR_SCSP_MASK   (0x20U)
#define	EMVSIM_PCSR_SCSP_SHIFT   (5U)
#define	EMVSIM_PCSR_SCSP(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
#define	EMVSIM_PCSR_SPD_MASK   (0x80U)
#define	EMVSIM_PCSR_SPD_SHIFT   (7U)
#define	EMVSIM_PCSR_SPD(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
#define	EMVSIM_PCSR_SPDIM_MASK   (0x1000000U)
#define	EMVSIM_PCSR_SPDIM_SHIFT   (24U)
#define	EMVSIM_PCSR_SPDIM(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
#define	EMVSIM_PCSR_SPDIF_MASK   (0x2000000U)
#define	EMVSIM_PCSR_SPDIF_SHIFT   (25U)
#define	EMVSIM_PCSR_SPDIF(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
#define	EMVSIM_PCSR_SPDP_MASK   (0x4000000U)
#define	EMVSIM_PCSR_SPDP_SHIFT   (26U)
#define	EMVSIM_PCSR_SPDP(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
#define	EMVSIM_PCSR_SPDES_MASK   (0x8000000U)
#define	EMVSIM_PCSR_SPDES_SHIFT   (27U)
#define	EMVSIM_PCSR_SPDES(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)

RX_BUF - Receive Data Read Buffer
#define	EMVSIM_RX_BUF_RX_BYTE_MASK   (0xFFU)
#define	EMVSIM_RX_BUF_RX_BYTE_SHIFT   (0U)
#define	EMVSIM_RX_BUF_RX_BYTE(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)

TX_BUF - Transmit Data Buffer
#define	EMVSIM_TX_BUF_TX_BYTE_MASK   (0xFFU)
#define	EMVSIM_TX_BUF_TX_BYTE_SHIFT   (0U)
#define	EMVSIM_TX_BUF_TX_BYTE(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)

TX_GETU - Transmitter Guard ETU Value Register
#define	EMVSIM_TX_GETU_GETU_MASK   (0xFFU)
#define	EMVSIM_TX_GETU_GETU_SHIFT   (0U)
#define	EMVSIM_TX_GETU_GETU(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)

CWT_VAL - Character Wait Time Value Register
#define	EMVSIM_CWT_VAL_CWT_MASK   (0xFFFFU)
#define	EMVSIM_CWT_VAL_CWT_SHIFT   (0U)
#define	EMVSIM_CWT_VAL_CWT(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)

BWT_VAL - Block Wait Time Value Register
#define	EMVSIM_BWT_VAL_BWT_MASK   (0xFFFFFFFFU)
#define	EMVSIM_BWT_VAL_BWT_SHIFT   (0U)
#define	EMVSIM_BWT_VAL_BWT(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)

BGT_VAL - Block Guard Time Value Register
#define	EMVSIM_BGT_VAL_BGT_MASK   (0xFFFFU)
#define	EMVSIM_BGT_VAL_BGT_SHIFT   (0U)
#define	EMVSIM_BGT_VAL_BGT(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)

GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register
#define	EMVSIM_GPCNT0_VAL_GPCNT0_MASK   (0xFFFFU)
#define	EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT   (0U)
#define	EMVSIM_GPCNT0_VAL_GPCNT0(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)

GPCNT1_VAL - General Purpose Counter 1 Timeout Value
#define	EMVSIM_GPCNT1_VAL_GPCNT1_MASK   (0xFFFFU)
#define	EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT   (0U)
#define	EMVSIM_GPCNT1_VAL_GPCNT1(x)   (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)

Detailed Description

Macro Definition Documentation

EMVSIM_BGT_VAL_BGT [1/2]

#define EMVSIM_BGT_VAL_BGT

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)

BGT - Block Guard Time Value

EMVSIM_BGT_VAL_BGT [2/2]

#define EMVSIM_BGT_VAL_BGT

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)

BGT - Block Guard Time Value

EMVSIM_BWT_VAL_BWT [1/2]

#define EMVSIM_BWT_VAL_BWT

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)

BWT - Block Wait Time Value

EMVSIM_BWT_VAL_BWT [2/2]

#define EMVSIM_BWT_VAL_BWT

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)

BWT - Block Wait Time Value

EMVSIM_CLKCFG_CLK_PRSC [1/2]

#define EMVSIM_CLKCFG_CLK_PRSC

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)

CLK_PRSC - Clock Prescaler Value

EMVSIM_CLKCFG_CLK_PRSC [2/2]

#define EMVSIM_CLKCFG_CLK_PRSC

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)

CLK_PRSC - Clock Prescaler Value

EMVSIM_CLKCFG_GPCNT0_CLK_SEL [1/2]

#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)

GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select 0b00..Disabled / Reset 0b01..Card Clock 0b10..Receive Clock 0b11..ETU Clock (transmit clock)

EMVSIM_CLKCFG_GPCNT0_CLK_SEL [2/2]

#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)

GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select 0b00..Disabled / Reset 0b01..Card Clock 0b10..Receive Clock 0b11..ETU Clock (transmit clock)

EMVSIM_CLKCFG_GPCNT1_CLK_SEL [1/2]

#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)

GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select 0b00..Disabled / Reset 0b01..Card Clock 0b10..Receive Clock 0b11..ETU Clock (transmit clock)

EMVSIM_CLKCFG_GPCNT1_CLK_SEL [2/2]

#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)

GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select 0b00..Disabled / Reset 0b01..Card Clock 0b10..Receive Clock 0b11..ETU Clock (transmit clock)

EMVSIM_CTRL_ANACK [1/2]

#define EMVSIM_CTRL_ANACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)

ANACK - Auto NACK Enable 0b0..NACK generation on errors disabled 0b1..NACK generation on errors enabled

EMVSIM_CTRL_ANACK [2/2]

#define EMVSIM_CTRL_ANACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)

ANACK - Auto NACK Enable 0b0..NACK generation on errors disabled 0b1..NACK generation on errors enabled

EMVSIM_CTRL_BWT_EN [1/2]

#define EMVSIM_CTRL_BWT_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)

BWT_EN - Block Wait Time Counter Enable 0b0..Disable BWT, BGT Counters 0b1..Enable BWT, BGT Counters

EMVSIM_CTRL_BWT_EN [2/2]

#define EMVSIM_CTRL_BWT_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)

BWT_EN - Block Wait Time Counter Enable 0b0..Disable BWT, BGT Counters 0b1..Enable BWT, BGT Counters

EMVSIM_CTRL_CRC_EN [1/2]

#define EMVSIM_CTRL_CRC_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)

CRC_EN - CRC Enable 0b0..16-bit Cyclic Redundancy Checking disabled 0b1..16-bit Cyclic Redundancy Checking enabled

EMVSIM_CTRL_CRC_EN [2/2]

#define EMVSIM_CTRL_CRC_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)

CRC_EN - CRC Enable 0b0..16-bit Cyclic Redundancy Checking disabled 0b1..16-bit Cyclic Redundancy Checking enabled

EMVSIM_CTRL_CRC_IN_FLIP [1/2]

#define EMVSIM_CTRL_CRC_IN_FLIP

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)

CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control 0b0..Bits in the input byte are not reversed (i.e. 7:0 remain 7:0) before the CRC calculation 0b1..Bits in the input byte are reversed (i.e. 7:0 becomes 0:7) before CRC calculation

EMVSIM_CTRL_CRC_IN_FLIP [2/2]

#define EMVSIM_CTRL_CRC_IN_FLIP

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)

CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control 0b0..Bits in the input byte are not reversed (i.e. 7:0 remain 7:0) before the CRC calculation 0b1..Bits in the input byte are reversed (i.e. 7:0 becomes 0:7) before CRC calculation

EMVSIM_CTRL_CRC_OUT_FLIP [1/2]

#define EMVSIM_CTRL_CRC_OUT_FLIP

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)

CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip 0b0..Bits within the CRC output bytes are not reversed i.e. 15:0 remains 15:0 0b1..Bits within the CRC output bytes are reversed i.e. 15:0 becomes {8:15,0:7}

EMVSIM_CTRL_CRC_OUT_FLIP [2/2]

#define EMVSIM_CTRL_CRC_OUT_FLIP

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)

CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip 0b0..Bits within the CRC output bytes are not reversed i.e. 15:0 remains 15:0 0b1..Bits within the CRC output bytes are reversed i.e. 15:0 becomes {8:15,0:7}

EMVSIM_CTRL_CWT_EN [1/2]

#define EMVSIM_CTRL_CWT_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)

CWT_EN - Character Wait Time Counter Enable 0b0..Character Wait time Counter is disabled 0b1..Character Wait time counter is enabled

EMVSIM_CTRL_CWT_EN [2/2]

#define EMVSIM_CTRL_CWT_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)

CWT_EN - Character Wait Time Counter Enable 0b0..Character Wait time Counter is disabled 0b1..Character Wait time counter is enabled

EMVSIM_CTRL_DOZE_EN [1/2]

#define EMVSIM_CTRL_DOZE_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)

DOZE_EN - Doze Enable 0b0..DOZE instruction gates all internal EMVSIM clocks as well as the Smart Card clock when the transmit FIFO is empty 0b1..DOZE instruction has no effect on EMVSIM module

EMVSIM_CTRL_DOZE_EN [2/2]

#define EMVSIM_CTRL_DOZE_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)

DOZE_EN - Doze Enable 0b0..DOZE instruction gates all internal EMVSIM clocks as well as the Smart Card clock when the transmit FIFO is empty 0b1..DOZE instruction has no effect on EMVSIM module

EMVSIM_CTRL_FLSH_RX [1/2]

#define EMVSIM_CTRL_FLSH_RX

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)

FLSH_RX - Flush Receiver Bit 0b0..EMVSIM Receiver normal operation 0b1..EMVSIM Receiver held in Reset

EMVSIM_CTRL_FLSH_RX [2/2]

#define EMVSIM_CTRL_FLSH_RX

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)

FLSH_RX - Flush Receiver Bit 0b0..EMVSIM Receiver normal operation 0b1..EMVSIM Receiver held in Reset

EMVSIM_CTRL_FLSH_TX [1/2]

#define EMVSIM_CTRL_FLSH_TX

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)

FLSH_TX - Flush Transmitter Bit 0b0..EMVSIM Transmitter normal operation 0b1..EMVSIM Transmitter held in Reset

EMVSIM_CTRL_FLSH_TX [2/2]

#define EMVSIM_CTRL_FLSH_TX

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)

FLSH_TX - Flush Transmitter Bit 0b0..EMVSIM Transmitter normal operation 0b1..EMVSIM Transmitter held in Reset

EMVSIM_CTRL_IC [1/2]

#define EMVSIM_CTRL_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)

IC - Inverse Convention 0b0..Direction convention transfers enabled 0b1..Inverse convention transfers enabled

EMVSIM_CTRL_IC [2/2]

#define EMVSIM_CTRL_IC

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)

IC - Inverse Convention 0b0..Direction convention transfers enabled 0b1..Inverse convention transfers enabled

EMVSIM_CTRL_ICM [1/2]

#define EMVSIM_CTRL_ICM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)

ICM - Initial Character Mode 0b0..Initial Character Mode disabled 0b1..Initial Character Mode enabled

EMVSIM_CTRL_ICM [2/2]

#define EMVSIM_CTRL_ICM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)

ICM - Initial Character Mode 0b0..Initial Character Mode disabled 0b1..Initial Character Mode enabled

EMVSIM_CTRL_INV_CRC_VAL [1/2]

#define EMVSIM_CTRL_INV_CRC_VAL

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)

INV_CRC_VAL - Invert bits in the CRC Output Value 0b0..Bits in CRC Output value are not inverted. 0b1..Bits in CRC Output value are inverted.

EMVSIM_CTRL_INV_CRC_VAL [2/2]

#define EMVSIM_CTRL_INV_CRC_VAL

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)

INV_CRC_VAL - Invert bits in the CRC Output Value 0b0..Bits in CRC Output value are not inverted. 0b1..Bits in CRC Output value are inverted.

EMVSIM_CTRL_KILL_CLOCKS [1/2]

#define EMVSIM_CTRL_KILL_CLOCKS

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)

KILL_CLOCKS - Kill all internal clocks 0b0..EMVSIM input clock enabled 0b1..EMVSIM input clock is disabled

EMVSIM_CTRL_KILL_CLOCKS [2/2]

#define EMVSIM_CTRL_KILL_CLOCKS

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)

KILL_CLOCKS - Kill all internal clocks 0b0..EMVSIM input clock enabled 0b1..EMVSIM input clock is disabled

EMVSIM_CTRL_LRC_EN [1/2]

#define EMVSIM_CTRL_LRC_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)

LRC_EN - LRC Enable 0b0..8-bit Linear Redundancy Checking disabled 0b1..8-bit Linear Redundancy Checking enabled

EMVSIM_CTRL_LRC_EN [2/2]

#define EMVSIM_CTRL_LRC_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)

LRC_EN - LRC Enable 0b0..8-bit Linear Redundancy Checking disabled 0b1..8-bit Linear Redundancy Checking enabled

EMVSIM_CTRL_ONACK [1/2]

#define EMVSIM_CTRL_ONACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)

ONACK - Overrun NACK Enable 0b0..NACK generation on overrun is disabled 0b1..NACK generation on overrun is enabled

EMVSIM_CTRL_ONACK [2/2]

#define EMVSIM_CTRL_ONACK

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)

ONACK - Overrun NACK Enable 0b0..NACK generation on overrun is disabled 0b1..NACK generation on overrun is enabled

EMVSIM_CTRL_RCV_EN [1/2]

#define EMVSIM_CTRL_RCV_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)

RCV_EN - Receiver Enable 0b0..EMVSIM Receiver disabled 0b1..EMVSIM Receiver enabled

EMVSIM_CTRL_RCV_EN [2/2]

#define EMVSIM_CTRL_RCV_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)

RCV_EN - Receiver Enable 0b0..EMVSIM Receiver disabled 0b1..EMVSIM Receiver enabled

EMVSIM_CTRL_RCVR_11 [1/2]

#define EMVSIM_CTRL_RCVR_11

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)

RCVR_11 - Receiver 11 ETU Mode Enable 0b0..Receiver configured for 12 ETU operation mode 0b1..Receiver configured for 11 ETU operation mode

EMVSIM_CTRL_RCVR_11 [2/2]

#define EMVSIM_CTRL_RCVR_11

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)

RCVR_11 - Receiver 11 ETU Mode Enable 0b0..Receiver configured for 12 ETU operation mode 0b1..Receiver configured for 11 ETU operation mode

EMVSIM_CTRL_RX_DMA_EN [1/2]

#define EMVSIM_CTRL_RX_DMA_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)

RX_DMA_EN - Receive DMA Enable 0b0..No DMA Read Request asserted for Receiver 0b1..DMA Read Request asserted for Receiver

EMVSIM_CTRL_RX_DMA_EN [2/2]

#define EMVSIM_CTRL_RX_DMA_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)

RX_DMA_EN - Receive DMA Enable 0b0..No DMA Read Request asserted for Receiver 0b1..DMA Read Request asserted for Receiver

EMVSIM_CTRL_STOP_EN [1/2]

#define EMVSIM_CTRL_STOP_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)

STOP_EN - STOP Enable 0b0..STOP instruction shuts down all EMVSIM clocks 0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card)

EMVSIM_CTRL_STOP_EN [2/2]

#define EMVSIM_CTRL_STOP_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)

STOP_EN - STOP Enable 0b0..STOP instruction shuts down all EMVSIM clocks 0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card)

EMVSIM_CTRL_SW_RST [1/2]

#define EMVSIM_CTRL_SW_RST

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)

SW_RST - Software Reset Bit 0b0..EMVSIM Normal operation 0b1..EMVSIM held in Reset

EMVSIM_CTRL_SW_RST [2/2]

#define EMVSIM_CTRL_SW_RST

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)

SW_RST - Software Reset Bit 0b0..EMVSIM Normal operation 0b1..EMVSIM held in Reset

EMVSIM_CTRL_TX_DMA_EN [1/2]

#define EMVSIM_CTRL_TX_DMA_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)

TX_DMA_EN - Transmit DMA Enable 0b0..No DMA Write Request asserted for Transmitter 0b1..DMA Write Request asserted for Transmitter

EMVSIM_CTRL_TX_DMA_EN [2/2]

#define EMVSIM_CTRL_TX_DMA_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)

TX_DMA_EN - Transmit DMA Enable 0b0..No DMA Write Request asserted for Transmitter 0b1..DMA Write Request asserted for Transmitter

EMVSIM_CTRL_XMT_CRC_LRC [1/2]

#define EMVSIM_CTRL_XMT_CRC_LRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)

XMT_CRC_LRC - Transmit CRC or LRC Enable 0b0..No CRC or LRC value is transmitted 0b1..Transmit LRC or CRC info when FIFO empties (whichever is enabled)

EMVSIM_CTRL_XMT_CRC_LRC [2/2]

#define EMVSIM_CTRL_XMT_CRC_LRC

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)

XMT_CRC_LRC - Transmit CRC or LRC Enable 0b0..No CRC or LRC value is transmitted 0b1..Transmit LRC or CRC info when FIFO empties (whichever is enabled)

EMVSIM_CTRL_XMT_EN [1/2]

#define EMVSIM_CTRL_XMT_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)

XMT_EN - Transmitter Enable 0b0..EMVSIM Transmitter disabled 0b1..EMVSIM Transmitter enabled

EMVSIM_CTRL_XMT_EN [2/2]

#define EMVSIM_CTRL_XMT_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)

XMT_EN - Transmitter Enable 0b0..EMVSIM Transmitter disabled 0b1..EMVSIM Transmitter enabled

EMVSIM_CWT_VAL_CWT [1/2]

#define EMVSIM_CWT_VAL_CWT

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)

CWT - Character Wait Time Value

EMVSIM_CWT_VAL_CWT [2/2]

#define EMVSIM_CWT_VAL_CWT

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)

CWT - Character Wait Time Value

EMVSIM_DIVISOR_DIVISOR_VALUE [1/2]

#define EMVSIM_DIVISOR_DIVISOR_VALUE

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)

DIVISOR_VALUE - Divisor (F/D) Value 0b000000000-0b000000100..Invalid. As per ISO 7816 specification, minimum value of F/D is 5 0b000000101-0b011111111..Divisor value F/D

EMVSIM_DIVISOR_DIVISOR_VALUE [2/2]

#define EMVSIM_DIVISOR_DIVISOR_VALUE

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)

DIVISOR_VALUE - Divisor (F/D) Value 0b000000000-0b000000100..Invalid. As per ISO 7816 specification, minimum value of F/D is 5 0b000000101-0b011111111..Divisor value F/D

EMVSIM_GPCNT0_VAL_GPCNT0 [1/2]

#define EMVSIM_GPCNT0_VAL_GPCNT0

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)

GPCNT0 - General Purpose Counter 0 Timeout Value

EMVSIM_GPCNT0_VAL_GPCNT0 [2/2]

#define EMVSIM_GPCNT0_VAL_GPCNT0

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)

GPCNT0 - General Purpose Counter 0 Timeout Value

EMVSIM_GPCNT1_VAL_GPCNT1 [1/2]

#define EMVSIM_GPCNT1_VAL_GPCNT1

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)

GPCNT1 - General Purpose Counter 1 Timeout Value

EMVSIM_GPCNT1_VAL_GPCNT1 [2/2]

#define EMVSIM_GPCNT1_VAL_GPCNT1

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)

GPCNT1 - General Purpose Counter 1 Timeout Value

EMVSIM_INT_MASK_BGT_ERR_IM [1/2]

#define EMVSIM_INT_MASK_BGT_ERR_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)

BGT_ERR_IM - Block Guard Time Error Interrupt 0b0..BGT_ERR interrupt enabled 0b1..BGT_ERR interrupt masked

EMVSIM_INT_MASK_BGT_ERR_IM [2/2]

#define EMVSIM_INT_MASK_BGT_ERR_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)

BGT_ERR_IM - Block Guard Time Error Interrupt 0b0..BGT_ERR interrupt enabled 0b1..BGT_ERR interrupt masked

EMVSIM_INT_MASK_BWT_ERR_IM [1/2]

#define EMVSIM_INT_MASK_BWT_ERR_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)

BWT_ERR_IM - Block Wait Time Error Interrupt Mask 0b0..BWT_ERR interrupt enabled 0b1..BWT_ERR interrupt masked

EMVSIM_INT_MASK_BWT_ERR_IM [2/2]

#define EMVSIM_INT_MASK_BWT_ERR_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)

BWT_ERR_IM - Block Wait Time Error Interrupt Mask 0b0..BWT_ERR interrupt enabled 0b1..BWT_ERR interrupt masked

EMVSIM_INT_MASK_CWT_ERR_IM [1/2]

#define EMVSIM_INT_MASK_CWT_ERR_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)

CWT_ERR_IM - Character Wait Time Error Interrupt Mask 0b0..CWT_ERR interrupt enabled 0b1..CWT_ERR interrupt masked

EMVSIM_INT_MASK_CWT_ERR_IM [2/2]

#define EMVSIM_INT_MASK_CWT_ERR_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)

CWT_ERR_IM - Character Wait Time Error Interrupt Mask 0b0..CWT_ERR interrupt enabled 0b1..CWT_ERR interrupt masked

EMVSIM_INT_MASK_ETC_IM [1/2]

#define EMVSIM_INT_MASK_ETC_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)

ETC_IM - Early Transmit Complete Interrupt Mask 0b0..ETC interrupt enabled 0b1..ETC interrupt masked

EMVSIM_INT_MASK_ETC_IM [2/2]

#define EMVSIM_INT_MASK_ETC_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)

ETC_IM - Early Transmit Complete Interrupt Mask 0b0..ETC interrupt enabled 0b1..ETC interrupt masked

EMVSIM_INT_MASK_GPCNT0_IM [1/2]

#define EMVSIM_INT_MASK_GPCNT0_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)

GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask 0b0..GPCNT0_TO interrupt enabled 0b1..GPCNT0_TO interrupt masked

EMVSIM_INT_MASK_GPCNT0_IM [2/2]

#define EMVSIM_INT_MASK_GPCNT0_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)

GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask 0b0..GPCNT0_TO interrupt enabled 0b1..GPCNT0_TO interrupt masked

EMVSIM_INT_MASK_GPCNT1_IM [1/2]

#define EMVSIM_INT_MASK_GPCNT1_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)

GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask 0b0..GPCNT1_TO interrupt enabled 0b1..GPCNT1_TO interrupt masked

EMVSIM_INT_MASK_GPCNT1_IM [2/2]

#define EMVSIM_INT_MASK_GPCNT1_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)

GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask 0b0..GPCNT1_TO interrupt enabled 0b1..GPCNT1_TO interrupt masked

EMVSIM_INT_MASK_PEF_IM [1/2]

#define EMVSIM_INT_MASK_PEF_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)

PEF_IM - Parity Error Interrupt Mask 0b0..PEF interrupt enabled 0b1..PEF interrupt masked

EMVSIM_INT_MASK_PEF_IM [2/2]

#define EMVSIM_INT_MASK_PEF_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)

PEF_IM - Parity Error Interrupt Mask 0b0..PEF interrupt enabled 0b1..PEF interrupt masked

EMVSIM_INT_MASK_RDT_IM [1/2]

#define EMVSIM_INT_MASK_RDT_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)

RDT_IM - Receive Data Threshold Interrupt Mask 0b0..RDTF interrupt enabled 0b1..RDTF interrupt masked

EMVSIM_INT_MASK_RDT_IM [2/2]

#define EMVSIM_INT_MASK_RDT_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)

RDT_IM - Receive Data Threshold Interrupt Mask 0b0..RDTF interrupt enabled 0b1..RDTF interrupt masked

EMVSIM_INT_MASK_RFO_IM [1/2]

#define EMVSIM_INT_MASK_RFO_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)

RFO_IM - Receive FIFO Overflow Interrupt Mask 0b0..RFO interrupt enabled 0b1..RFO interrupt masked

EMVSIM_INT_MASK_RFO_IM [2/2]

#define EMVSIM_INT_MASK_RFO_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)

RFO_IM - Receive FIFO Overflow Interrupt Mask 0b0..RFO interrupt enabled 0b1..RFO interrupt masked

EMVSIM_INT_MASK_RNACK_IM [1/2]

#define EMVSIM_INT_MASK_RNACK_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)

RNACK_IM - Receiver NACK Threshold Interrupt Mask 0b0..RTE interrupt enabled 0b1..RTE interrupt masked

EMVSIM_INT_MASK_RNACK_IM [2/2]

#define EMVSIM_INT_MASK_RNACK_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)

RNACK_IM - Receiver NACK Threshold Interrupt Mask 0b0..RTE interrupt enabled 0b1..RTE interrupt masked

EMVSIM_INT_MASK_RX_DATA_IM [1/2]

#define EMVSIM_INT_MASK_RX_DATA_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)

RX_DATA_IM - Receive Data Interrupt Mask 0b0..RX_DATA interrupt enabled 0b1..RX_DATA interrupt masked

EMVSIM_INT_MASK_RX_DATA_IM [2/2]

#define EMVSIM_INT_MASK_RX_DATA_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)

RX_DATA_IM - Receive Data Interrupt Mask 0b0..RX_DATA interrupt enabled 0b1..RX_DATA interrupt masked

EMVSIM_INT_MASK_TC_IM [1/2]

#define EMVSIM_INT_MASK_TC_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)

TC_IM - Transmit Complete Interrupt Mask 0b0..TCF interrupt enabled 0b1..TCF interrupt masked

EMVSIM_INT_MASK_TC_IM [2/2]

#define EMVSIM_INT_MASK_TC_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)

TC_IM - Transmit Complete Interrupt Mask 0b0..TCF interrupt enabled 0b1..TCF interrupt masked

EMVSIM_INT_MASK_TDT_IM [1/2]

#define EMVSIM_INT_MASK_TDT_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)

TDT_IM - Transmit Data Threshold Interrupt Mask 0b0..TDTF interrupt enabled 0b1..TDTF interrupt masked

EMVSIM_INT_MASK_TDT_IM [2/2]

#define EMVSIM_INT_MASK_TDT_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)

TDT_IM - Transmit Data Threshold Interrupt Mask 0b0..TDTF interrupt enabled 0b1..TDTF interrupt masked

EMVSIM_INT_MASK_TFE_IM [1/2]

#define EMVSIM_INT_MASK_TFE_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)

TFE_IM - Transmit FIFO Empty Interrupt Mask 0b0..TFE interrupt enabled 0b1..TFE interrupt masked

EMVSIM_INT_MASK_TFE_IM [2/2]

#define EMVSIM_INT_MASK_TFE_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)

TFE_IM - Transmit FIFO Empty Interrupt Mask 0b0..TFE interrupt enabled 0b1..TFE interrupt masked

EMVSIM_INT_MASK_TFF_IM [1/2]

#define EMVSIM_INT_MASK_TFF_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)

TFF_IM - Transmit FIFO Full Interrupt Mask 0b0..TFF interrupt enabled 0b1..TFF interrupt masked

EMVSIM_INT_MASK_TFF_IM [2/2]

#define EMVSIM_INT_MASK_TFF_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)

TFF_IM - Transmit FIFO Full Interrupt Mask 0b0..TFF interrupt enabled 0b1..TFF interrupt masked

EMVSIM_INT_MASK_TNACK_IM [1/2]

#define EMVSIM_INT_MASK_TNACK_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)

TNACK_IM - Transmit NACK Threshold Interrupt Mask 0b0..TNTE interrupt enabled 0b1..TNTE interrupt masked

EMVSIM_INT_MASK_TNACK_IM [2/2]

#define EMVSIM_INT_MASK_TNACK_IM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)

TNACK_IM - Transmit NACK Threshold Interrupt Mask 0b0..TNTE interrupt enabled 0b1..TNTE interrupt masked

EMVSIM_PARAM_RX_FIFO_DEPTH [1/2]

#define EMVSIM_PARAM_RX_FIFO_DEPTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)

RX_FIFO_DEPTH - Receive FIFO Depth

EMVSIM_PARAM_RX_FIFO_DEPTH [2/2]

#define EMVSIM_PARAM_RX_FIFO_DEPTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)

RX_FIFO_DEPTH - Receive FIFO Depth

EMVSIM_PARAM_TX_FIFO_DEPTH [1/2]

#define EMVSIM_PARAM_TX_FIFO_DEPTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)

TX_FIFO_DEPTH - Transmit FIFO Depth

EMVSIM_PARAM_TX_FIFO_DEPTH [2/2]

#define EMVSIM_PARAM_TX_FIFO_DEPTH

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)

TX_FIFO_DEPTH - Transmit FIFO Depth

EMVSIM_PCSR_SAPD [1/2]

#define EMVSIM_PCSR_SAPD

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)

SAPD - Auto Power Down Enable 0b0..Auto power down disabled 0b1..Auto power down enabled

EMVSIM_PCSR_SAPD [2/2]

#define EMVSIM_PCSR_SAPD

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)

SAPD - Auto Power Down Enable 0b0..Auto power down disabled 0b1..Auto power down enabled

EMVSIM_PCSR_SCEN [1/2]

#define EMVSIM_PCSR_SCEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)

SCEN - Clock Enable for Smart Card 0b0..Smart Card Clock Disabled 0b1..Smart Card Clock Enabled

EMVSIM_PCSR_SCEN [2/2]

#define EMVSIM_PCSR_SCEN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)

SCEN - Clock Enable for Smart Card 0b0..Smart Card Clock Disabled 0b1..Smart Card Clock Enabled

EMVSIM_PCSR_SCSP [1/2]

#define EMVSIM_PCSR_SCSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)

SCSP - Smart Card Clock Stop Polarity 0b0..Clock is logic 0 when stopped by SCEN 0b1..Clock is logic 1 when stopped by SCEN

EMVSIM_PCSR_SCSP [2/2]

#define EMVSIM_PCSR_SCSP

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)

SCSP - Smart Card Clock Stop Polarity 0b0..Clock is logic 0 when stopped by SCEN 0b1..Clock is logic 1 when stopped by SCEN

EMVSIM_PCSR_SPD [1/2]

#define EMVSIM_PCSR_SPD

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)

SPD - Auto Power Down Control 0b0..No effect 0b1..Start Auto Powerdown or Power Down is in progress

EMVSIM_PCSR_SPD [2/2]

#define EMVSIM_PCSR_SPD

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)

SPD - Auto Power Down Control 0b0..No effect 0b1..Start Auto Powerdown or Power Down is in progress

EMVSIM_PCSR_SPDES [1/2]

#define EMVSIM_PCSR_SPDES

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)

SPDES - SIM Presence Detect Edge Select 0b0..Falling edge on the pin 0b1..Rising edge on the pin

EMVSIM_PCSR_SPDES [2/2]

#define EMVSIM_PCSR_SPDES

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)

SPDES - SIM Presence Detect Edge Select 0b0..Falling edge on the pin 0b1..Rising edge on the pin

EMVSIM_PCSR_SPDIF [1/2]

#define EMVSIM_PCSR_SPDIF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)

SPDIF - Smart Card Presence Detect Interrupt Flag 0b0..No insertion or removal of Smart Card detected on Port 0b1..Insertion or removal of Smart Card detected on Port

EMVSIM_PCSR_SPDIF [2/2]

#define EMVSIM_PCSR_SPDIF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)

SPDIF - Smart Card Presence Detect Interrupt Flag 0b0..No insertion or removal of Smart Card detected on Port 0b1..Insertion or removal of Smart Card detected on Port

EMVSIM_PCSR_SPDIM [1/2]

#define EMVSIM_PCSR_SPDIM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)

SPDIM - Smart Card Presence Detect Interrupt Mask 0b0..SIM presence detect interrupt is enabled 0b1..SIM presence detect interrupt is masked

EMVSIM_PCSR_SPDIM [2/2]

#define EMVSIM_PCSR_SPDIM

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)

SPDIM - Smart Card Presence Detect Interrupt Mask 0b0..SIM presence detect interrupt is enabled 0b1..SIM presence detect interrupt is masked

EMVSIM_PCSR_SPDP [1/2]

#define EMVSIM_PCSR_SPDP

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)

SPDP - Smart Card Presence Detect Pin Status 0b0..SIM Presence Detect pin is logic low 0b1..SIM Presence Detectpin is logic high

EMVSIM_PCSR_SPDP [2/2]

#define EMVSIM_PCSR_SPDP

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)

SPDP - Smart Card Presence Detect Pin Status 0b0..SIM Presence Detect pin is logic low 0b1..SIM Presence Detectpin is logic high

EMVSIM_PCSR_SRST [1/2]

#define EMVSIM_PCSR_SRST

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)

SRST - Reset to Smart Card 0b0..Smart Card Reset is asserted 0b1..Smart Card Reset is de-asserted

EMVSIM_PCSR_SRST [2/2]

#define EMVSIM_PCSR_SRST

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)

SRST - Reset to Smart Card 0b0..Smart Card Reset is asserted 0b1..Smart Card Reset is de-asserted

EMVSIM_PCSR_SVCC_EN [1/2]

#define EMVSIM_PCSR_SVCC_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)

SVCC_EN - Vcc Enable for Smart Card 0b0..Smart Card Voltage disabled 0b1..Smart Card Voltage enabled

EMVSIM_PCSR_SVCC_EN [2/2]

#define EMVSIM_PCSR_SVCC_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)

SVCC_EN - Vcc Enable for Smart Card 0b0..Smart Card Voltage disabled 0b1..Smart Card Voltage enabled

EMVSIM_PCSR_VCCENP [1/2]

#define EMVSIM_PCSR_VCCENP

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)

VCCENP - VCC Enable Polarity Control 0b0..SVCC_EN is active high. Polarity of SVCC_EN is unchanged. 0b1..SVCC_EN is active low. Polarity of SVCC_EN is inverted.

EMVSIM_PCSR_VCCENP [2/2]

#define EMVSIM_PCSR_VCCENP

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)

VCCENP - VCC Enable Polarity Control 0b0..SVCC_EN is active high. Polarity of SVCC_EN is unchanged. 0b1..SVCC_EN is active low. Polarity of SVCC_EN is inverted.

EMVSIM_RX_BUF_RX_BYTE [1/2]

#define EMVSIM_RX_BUF_RX_BYTE

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)

RX_BYTE - Receive Data Byte Read

EMVSIM_RX_BUF_RX_BYTE [2/2]

#define EMVSIM_RX_BUF_RX_BYTE

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)

RX_BYTE - Receive Data Byte Read

EMVSIM_RX_STATUS_BGT_ERR [1/2]

#define EMVSIM_RX_STATUS_BGT_ERR

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)

BGT_ERR - Block Guard Time Error Flag 0b0..Block guard time was sufficient 0b1..Block guard time was too small

EMVSIM_RX_STATUS_BGT_ERR [2/2]

#define EMVSIM_RX_STATUS_BGT_ERR

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)

BGT_ERR - Block Guard Time Error Flag 0b0..Block guard time was sufficient 0b1..Block guard time was too small

EMVSIM_RX_STATUS_BWT_ERR [1/2]

#define EMVSIM_RX_STATUS_BWT_ERR

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)

BWT_ERR - Block Wait Time Error Flag 0b0..Block wait time not exceeded 0b1..Block wait time was exceeded

EMVSIM_RX_STATUS_BWT_ERR [2/2]

#define EMVSIM_RX_STATUS_BWT_ERR

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)

BWT_ERR - Block Wait Time Error Flag 0b0..Block wait time not exceeded 0b1..Block wait time was exceeded

EMVSIM_RX_STATUS_CRC_OK [1/2]

#define EMVSIM_RX_STATUS_CRC_OK

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)

CRC_OK - CRC Check OK Flag 0b0..Current CRC value does not match remainder. 0b1..Current calculated CRC value matches the expected result.

EMVSIM_RX_STATUS_CRC_OK [2/2]

#define EMVSIM_RX_STATUS_CRC_OK

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)

CRC_OK - CRC Check OK Flag 0b0..Current CRC value does not match remainder. 0b1..Current calculated CRC value matches the expected result.

EMVSIM_RX_STATUS_CWT_ERR [1/2]

#define EMVSIM_RX_STATUS_CWT_ERR

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)

CWT_ERR - Character Wait Time Error Flag 0b0..No CWT violation has occurred 0b1..Time between two consecutive characters has exceeded the value in CWT_VAL.

EMVSIM_RX_STATUS_CWT_ERR [2/2]

#define EMVSIM_RX_STATUS_CWT_ERR

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)

CWT_ERR - Character Wait Time Error Flag 0b0..No CWT violation has occurred 0b1..Time between two consecutive characters has exceeded the value in CWT_VAL.

EMVSIM_RX_STATUS_FEF [1/2]

#define EMVSIM_RX_STATUS_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)

FEF - Frame Error Flag 0b0..No frame error detected 0b1..Frame error detected

EMVSIM_RX_STATUS_FEF [2/2]

#define EMVSIM_RX_STATUS_FEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)

FEF - Frame Error Flag 0b0..No frame error detected 0b1..Frame error detected

EMVSIM_RX_STATUS_LRC_OK [1/2]

#define EMVSIM_RX_STATUS_LRC_OK

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)

LRC_OK - LRC Check OK Flag 0b0..Current LRC value does not match remainder. 0b1..Current calculated LRC value matches the expected result (i.e. zero).

EMVSIM_RX_STATUS_LRC_OK [2/2]

#define EMVSIM_RX_STATUS_LRC_OK

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)

LRC_OK - LRC Check OK Flag 0b0..Current LRC value does not match remainder. 0b1..Current calculated LRC value matches the expected result (i.e. zero).

EMVSIM_RX_STATUS_PEF [1/2]

#define EMVSIM_RX_STATUS_PEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)

PEF - Parity Error Flag 0b0..No parity error detected 0b1..Parity error detected

EMVSIM_RX_STATUS_PEF [2/2]

#define EMVSIM_RX_STATUS_PEF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)

PEF - Parity Error Flag 0b0..No parity error detected 0b1..Parity error detected

EMVSIM_RX_STATUS_RDTF [1/2]

#define EMVSIM_RX_STATUS_RDTF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)

RDTF - Receive Data Threshold Interrupt Flag 0b0..Number of unread bytes in receive FIFO less than the value set by RDT 0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT.

EMVSIM_RX_STATUS_RDTF [2/2]

#define EMVSIM_RX_STATUS_RDTF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)

RDTF - Receive Data Threshold Interrupt Flag 0b0..Number of unread bytes in receive FIFO less than the value set by RDT 0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT.

EMVSIM_RX_STATUS_RFO [1/2]

#define EMVSIM_RX_STATUS_RFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)

RFO - Receive FIFO Overflow Flag 0b0..No overrun error has occurred 0b1..A byte was received when the received FIFO was already full

EMVSIM_RX_STATUS_RFO [2/2]

#define EMVSIM_RX_STATUS_RFO

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)

RFO - Receive FIFO Overflow Flag 0b0..No overrun error has occurred 0b1..A byte was received when the received FIFO was already full

EMVSIM_RX_STATUS_RTE [1/2]

#define EMVSIM_RX_STATUS_RTE

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)

RTE - Received NACK Threshold Error Flag 0b0..Number of NACKs generated by the receiver is less than the value programmed in RNCK_THD 0b1..Number of NACKs generated by the receiver is equal to the value programmed in RNCK_THD

EMVSIM_RX_STATUS_RTE [2/2]

#define EMVSIM_RX_STATUS_RTE

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)

RTE - Received NACK Threshold Error Flag 0b0..Number of NACKs generated by the receiver is less than the value programmed in RNCK_THD 0b1..Number of NACKs generated by the receiver is equal to the value programmed in RNCK_THD

EMVSIM_RX_STATUS_RX_CNT [1/2]

#define EMVSIM_RX_STATUS_RX_CNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)

RX_CNT - Receive FIFO Byte Count 0b0000..FIFO is emtpy

EMVSIM_RX_STATUS_RX_CNT [2/2]

#define EMVSIM_RX_STATUS_RX_CNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)

RX_CNT - Receive FIFO Byte Count 0b0000..FIFO is emtpy

EMVSIM_RX_STATUS_RX_DATA [1/2]

#define EMVSIM_RX_STATUS_RX_DATA

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)

RX_DATA - Receive Data Interrupt Flag 0b0..No new byte is received 0b1..New byte is received ans stored in Receive FIFO

EMVSIM_RX_STATUS_RX_DATA [2/2]

#define EMVSIM_RX_STATUS_RX_DATA

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)

RX_DATA - Receive Data Interrupt Flag 0b0..No new byte is received 0b1..New byte is received ans stored in Receive FIFO

EMVSIM_RX_STATUS_RX_WPTR [1/2]

#define EMVSIM_RX_STATUS_RX_WPTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)

RX_WPTR - Receive FIFO Write Pointer Value

EMVSIM_RX_STATUS_RX_WPTR [2/2]

#define EMVSIM_RX_STATUS_RX_WPTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)

RX_WPTR - Receive FIFO Write Pointer Value

EMVSIM_RX_THD_RDT [1/2]

#define EMVSIM_RX_THD_RDT

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)

RDT - Receiver Data Threshold Value

EMVSIM_RX_THD_RDT [2/2]

#define EMVSIM_RX_THD_RDT

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)

RDT - Receiver Data Threshold Value

EMVSIM_RX_THD_RNCK_THD [1/2]

#define EMVSIM_RX_THD_RNCK_THD

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)

RNCK_THD - Receiver NACK Threshold Value

EMVSIM_RX_THD_RNCK_THD [2/2]

#define EMVSIM_RX_THD_RNCK_THD

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)

RNCK_THD - Receiver NACK Threshold Value

EMVSIM_TX_BUF_TX_BYTE [1/2]

#define EMVSIM_TX_BUF_TX_BYTE

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)

TX_BYTE - Transmit Data Byte

EMVSIM_TX_BUF_TX_BYTE [2/2]

#define EMVSIM_TX_BUF_TX_BYTE

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)

TX_BYTE - Transmit Data Byte

EMVSIM_TX_GETU_GETU [1/2]

#define EMVSIM_TX_GETU_GETU

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)

GETU - Transmitter Guard Time Value in ETU

EMVSIM_TX_GETU_GETU [2/2]

#define EMVSIM_TX_GETU_GETU

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)

GETU - Transmitter Guard Time Value in ETU

EMVSIM_TX_STATUS_ETCF [1/2]

#define EMVSIM_TX_STATUS_ETCF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)

ETCF - Early Transmit Complete Flag 0b0..Transmit pending or in progress 0b1..Transmit complete

EMVSIM_TX_STATUS_ETCF [2/2]

#define EMVSIM_TX_STATUS_ETCF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)

ETCF - Early Transmit Complete Flag 0b0..Transmit pending or in progress 0b1..Transmit complete

EMVSIM_TX_STATUS_GPCNT0_TO [1/2]

#define EMVSIM_TX_STATUS_GPCNT0_TO

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)

GPCNT0_TO - General Purpose Counter 0 Timeout Flag 0b0..GPCNT0 time not reached, or bit has been cleared. 0b1..General Purpose counter has reached the GPCNT0 value

EMVSIM_TX_STATUS_GPCNT0_TO [2/2]

#define EMVSIM_TX_STATUS_GPCNT0_TO

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)

GPCNT0_TO - General Purpose Counter 0 Timeout Flag 0b0..GPCNT0 time not reached, or bit has been cleared. 0b1..General Purpose counter has reached the GPCNT0 value

EMVSIM_TX_STATUS_GPCNT1_TO [1/2]

#define EMVSIM_TX_STATUS_GPCNT1_TO

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)

GPCNT1_TO - General Purpose Counter 1 Timeout Flag 0b0..GPCNT1 time not reached, or bit has been cleared. 0b1..General Purpose counter has reached the GPCNT1 value

EMVSIM_TX_STATUS_GPCNT1_TO [2/2]

#define EMVSIM_TX_STATUS_GPCNT1_TO

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)

GPCNT1_TO - General Purpose Counter 1 Timeout Flag 0b0..GPCNT1 time not reached, or bit has been cleared. 0b1..General Purpose counter has reached the GPCNT1 value

EMVSIM_TX_STATUS_TCF [1/2]

#define EMVSIM_TX_STATUS_TCF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)

TCF - Transmit Complete Flag 0b0..Transmit pending or in progress 0b1..Transmit complete

EMVSIM_TX_STATUS_TCF [2/2]

#define EMVSIM_TX_STATUS_TCF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)

TCF - Transmit Complete Flag 0b0..Transmit pending or in progress 0b1..Transmit complete

EMVSIM_TX_STATUS_TDTF [1/2]

#define EMVSIM_TX_STATUS_TDTF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)

TDTF - Transmit Data Threshold Flag 0b0..Number of bytes in FIFO is greater than TDT, or bit has been cleared 0b1..Number of bytes in FIFO is less than or equal to TDT

EMVSIM_TX_STATUS_TDTF [2/2]

#define EMVSIM_TX_STATUS_TDTF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)

TDTF - Transmit Data Threshold Flag 0b0..Number of bytes in FIFO is greater than TDT, or bit has been cleared 0b1..Number of bytes in FIFO is less than or equal to TDT

EMVSIM_TX_STATUS_TFE [1/2]

#define EMVSIM_TX_STATUS_TFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)

TFE - Transmit FIFO Empty Flag 0b0..Transmit FIFO is not empty 0b1..Transmit FIFO is empty

EMVSIM_TX_STATUS_TFE [2/2]

#define EMVSIM_TX_STATUS_TFE

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)

TFE - Transmit FIFO Empty Flag 0b0..Transmit FIFO is not empty 0b1..Transmit FIFO is empty

EMVSIM_TX_STATUS_TFF [1/2]

#define EMVSIM_TX_STATUS_TFF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)

TFF - Transmit FIFO Full Flag 0b0..Transmit FIFO Full condition has not occurred 0b1..A Transmit FIFO Full condition has occurred

EMVSIM_TX_STATUS_TFF [2/2]

#define EMVSIM_TX_STATUS_TFF

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)

TFF - Transmit FIFO Full Flag 0b0..Transmit FIFO Full condition has not occurred 0b1..A Transmit FIFO Full condition has occurred

EMVSIM_TX_STATUS_TNTE [1/2]

#define EMVSIM_TX_STATUS_TNTE

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)

TNTE - Transmit NACK Threshold Error Flag 0b0..Transmit NACK threshold has not been reached 0b1..Transmit NACK threshold reached; transmitter frozen

EMVSIM_TX_STATUS_TNTE [2/2]

#define EMVSIM_TX_STATUS_TNTE

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)

TNTE - Transmit NACK Threshold Error Flag 0b0..Transmit NACK threshold has not been reached 0b1..Transmit NACK threshold reached; transmitter frozen

EMVSIM_TX_STATUS_TX_CNT [1/2]

#define EMVSIM_TX_STATUS_TX_CNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)

TX_CNT - Transmit FIFO Byte Count 0b0000..FIFO is emtpy

EMVSIM_TX_STATUS_TX_CNT [2/2]

#define EMVSIM_TX_STATUS_TX_CNT

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)

TX_CNT - Transmit FIFO Byte Count 0b0000..FIFO is emtpy

EMVSIM_TX_STATUS_TX_RPTR [1/2]

#define EMVSIM_TX_STATUS_TX_RPTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)

TX_RPTR - Transmit FIFO Read Pointer

EMVSIM_TX_STATUS_TX_RPTR [2/2]

#define EMVSIM_TX_STATUS_TX_RPTR

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)

TX_RPTR - Transmit FIFO Read Pointer

EMVSIM_TX_THD_TDT [1/2]

#define EMVSIM_TX_THD_TDT

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)

TDT - Transmitter Data Threshold Value

EMVSIM_TX_THD_TDT [2/2]

#define EMVSIM_TX_THD_TDT

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)

TDT - Transmitter Data Threshold Value

EMVSIM_TX_THD_TNCK_THD [1/2]

#define EMVSIM_TX_THD_TNCK_THD

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)

TNCK_THD - Transmitter NACK Threshold Value

EMVSIM_TX_THD_TNCK_THD [2/2]

#define EMVSIM_TX_THD_TNCK_THD

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)

TNCK_THD - Transmitter NACK Threshold Value

EMVSIM_VER_ID_VER [1/2]

#define EMVSIM_VER_ID_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)

VER - Version ID of the module

EMVSIM_VER_ID_VER [2/2]

#define EMVSIM_VER_ID_VER

(

x

)

(((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)

VER - Version ID of the module

ENC_CTRL_CMPIE [1/2]

#define ENC_CTRL_CMPIE

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)

CMPIE - Compare Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_CMPIE [2/2]

#define ENC_CTRL_CMPIE

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)

CMPIE - Compare Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_CMPIRQ [1/2]

#define ENC_CTRL_CMPIRQ

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)

CMPIRQ - Compare Interrupt Request 0b0..No match has occurred (the counter does not match the COMP value) 0b1..COMP match has occurred (the counter matches the COMP value)

ENC_CTRL_CMPIRQ [2/2]

#define ENC_CTRL_CMPIRQ

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)

CMPIRQ - Compare Interrupt Request 0b0..No match has occurred (the counter does not match the COMP value) 0b1..COMP match has occurred (the counter matches the COMP value)

ENC_CTRL_DIE [1/2]

#define ENC_CTRL_DIE

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)

DIE - Watchdog Timeout Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_DIE [2/2]

#define ENC_CTRL_DIE

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)

DIE - Watchdog Timeout Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_DIRQ [1/2]

#define ENC_CTRL_DIRQ

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)

DIRQ - Watchdog Timeout Interrupt Request 0b0..No Watchdog timeout interrupt has occurred 0b1..Watchdog timeout interrupt has occurred

ENC_CTRL_DIRQ [2/2]

#define ENC_CTRL_DIRQ

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)

DIRQ - Watchdog Timeout Interrupt Request 0b0..No Watchdog timeout interrupt has occurred 0b1..Watchdog timeout interrupt has occurred

ENC_CTRL_HIE [1/2]

#define ENC_CTRL_HIE

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)

HIE - HOME Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_HIE [2/2]

#define ENC_CTRL_HIE

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)

HIE - HOME Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_HIP [1/2]

#define ENC_CTRL_HIP

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)

HIP - Enable HOME to Initialize Position Counters UPOS and LPOS 0b0..No action 0b1..HOME signal initializes the position counter

ENC_CTRL_HIP [2/2]

#define ENC_CTRL_HIP

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)

HIP - Enable HOME to Initialize Position Counters UPOS and LPOS 0b0..No action 0b1..HOME signal initializes the position counter

ENC_CTRL_HIRQ [1/2]

#define ENC_CTRL_HIRQ

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)

HIRQ - HOME Signal Transition Interrupt Request 0b0..No transition on the HOME signal has occurred 0b1..A transition on the HOME signal has occurred

ENC_CTRL_HIRQ [2/2]

#define ENC_CTRL_HIRQ

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)

HIRQ - HOME Signal Transition Interrupt Request 0b0..No transition on the HOME signal has occurred 0b1..A transition on the HOME signal has occurred

ENC_CTRL_HNE [1/2]

#define ENC_CTRL_HNE

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)

HNE - Use Negative Edge of HOME Input 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS

ENC_CTRL_HNE [2/2]

#define ENC_CTRL_HNE

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)

HNE - Use Negative Edge of HOME Input 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS

ENC_CTRL_PH1 [1/2]

#define ENC_CTRL_PH1

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)

PH1 - Enable Signal Phase Count Mode 0b0..Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction: If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 1, PHASEB = 1, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down

ENC_CTRL_PH1 [2/2]

#define ENC_CTRL_PH1

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)

PH1 - Enable Signal Phase Count Mode 0b0..Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal. 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The PHASEB input and the REV bit control the counter direction: If CTRL[REV] = 0, PHASEB = 0, then count up If CTRL[REV] = 1, PHASEB = 1, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1, PHASEB = 0, then count down

ENC_CTRL_REV [1/2]

#define ENC_CTRL_REV

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)

REV - Enable Reverse Direction Counting 0b0..Count normally 0b1..Count in the reverse direction

ENC_CTRL_REV [2/2]

#define ENC_CTRL_REV

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)

REV - Enable Reverse Direction Counting 0b0..Count normally 0b1..Count in the reverse direction

ENC_CTRL_SWIP [1/2]

#define ENC_CTRL_SWIP

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)

SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS 0b0..No action 0b1..Initialize position counter (using upper and lower initialization registers, UINIT and LINIT)

ENC_CTRL_SWIP [2/2]

#define ENC_CTRL_SWIP

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)

SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS 0b0..No action 0b1..Initialize position counter (using upper and lower initialization registers, UINIT and LINIT)

ENC_CTRL_WDE [1/2]

#define ENC_CTRL_WDE

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)

WDE - Watchdog Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_WDE [2/2]

#define ENC_CTRL_WDE

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)

WDE - Watchdog Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_XIE [1/2]

#define ENC_CTRL_XIE

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)

XIE - INDEX Pulse Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_XIE [2/2]

#define ENC_CTRL_XIE

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)

XIE - INDEX Pulse Interrupt Enable 0b0..Disabled 0b1..Enabled

ENC_CTRL_XIP [1/2]

#define ENC_CTRL_XIP

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)

XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS 0b0..INDEX pulse does not initialize the position counter 0b1..INDEX pulse initializes the position counter

ENC_CTRL_XIP [2/2]

#define ENC_CTRL_XIP

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)

XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS 0b0..INDEX pulse does not initialize the position counter 0b1..INDEX pulse initializes the position counter

ENC_CTRL_XIRQ [1/2]

#define ENC_CTRL_XIRQ

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)

XIRQ - INDEX Pulse Interrupt Request 0b0..INDEX pulse has not occurred 0b1..INDEX pulse has occurred

ENC_CTRL_XIRQ [2/2]

#define ENC_CTRL_XIRQ

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)

XIRQ - INDEX Pulse Interrupt Request 0b0..INDEX pulse has not occurred 0b1..INDEX pulse has occurred

ENC_CTRL_XNE [1/2]

#define ENC_CTRL_XNE

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)

XNE - Use Negative Edge of INDEX Pulse 0b0..Use positive edge of INDEX pulse 0b1..Use negative edge of INDEX pulse

ENC_CTRL_XNE [2/2]

#define ENC_CTRL_XNE

(

x

)

(((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)

XNE - Use Negative Edge of INDEX Pulse 0b0..Use positive edge of INDEX pulse 0b1..Use negative edge of INDEX pulse

EWM_CTRL_ASSIN [1/2]

#define EWM_CTRL_ASSIN

(

x

)

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)

ASSIN - EWM_in's Assertion State Select. 0b0..Default assert state of the EWM_in signal. 0b1..Inverts the assert state of EWM_in signal.

EWM_CTRL_ASSIN [2/2]

#define EWM_CTRL_ASSIN

(

x

)

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)

ASSIN - EWM_in's Assertion State Select. 0b0..Default assert state of the EWM_in signal. 0b1..Inverts the assert state of EWM_in signal.

EWM_CTRL_EWMEN [1/2]

#define EWM_CTRL_EWMEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)

EWMEN - EWM enable. 0b0..EWM module is disabled. 0b1..EWM module is enabled.

EWM_CTRL_EWMEN [2/2]

#define EWM_CTRL_EWMEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)

EWMEN - EWM enable. 0b0..EWM module is disabled. 0b1..EWM module is enabled.

EWM_CTRL_INEN [1/2]

#define EWM_CTRL_INEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)

INEN - Input Enable. 0b0..EWM_in port is disabled. 0b1..EWM_in port is enabled.

EWM_CTRL_INEN [2/2]

#define EWM_CTRL_INEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)

INEN - Input Enable. 0b0..EWM_in port is disabled. 0b1..EWM_in port is enabled.

EWM_CTRL_INTEN [1/2]

#define EWM_CTRL_INTEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)

INTEN - Interrupt Enable. 0b1..Generates an interrupt request, when EWM_OUT_b is asserted. 0b0..Deasserts the interrupt request.

EWM_CTRL_INTEN [2/2]

#define EWM_CTRL_INTEN

(

x

)

(((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)

INTEN - Interrupt Enable. 0b1..Generates an interrupt request, when EWM_OUT_b is asserted. 0b0..Deasserts the interrupt request.

PWM_CTRL_COMPMODE [1/2]

#define PWM_CTRL_COMPMODE

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)

COMPMODE - Compare Mode 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.

PWM_CTRL_COMPMODE [2/2]

#define PWM_CTRL_COMPMODE

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)

COMPMODE - Compare Mode 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA output that is high at the end of a period will maintain this state until a match with VAL3 clears the output in the following period. 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register values. This implies that a PWMA output that is high at the end of a period could go low at the start of the next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.

PWM_CTRL_DBLEN [1/2]

#define PWM_CTRL_DBLEN

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)

DBLEN - Double Switching Enable 0b0..Double switching disabled. 0b1..Double switching enabled.

PWM_CTRL_DBLEN [2/2]

#define PWM_CTRL_DBLEN

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)

DBLEN - Double Switching Enable 0b0..Double switching disabled. 0b1..Double switching enabled.

PWM_CTRL_DBLX [1/2]

#define PWM_CTRL_DBLX

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)

DBLX - PWMX Double Switching Enable 0b0..PWMX double pulse disabled. 0b1..PWMX double pulse enabled.

PWM_CTRL_DBLX [2/2]

#define PWM_CTRL_DBLX

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)

DBLX - PWMX Double Switching Enable 0b0..PWMX double pulse disabled. 0b1..PWMX double pulse enabled.

PWM_CTRL_DT [1/2]

#define PWM_CTRL_DT

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)

DT - Deadtime

PWM_CTRL_DT [2/2]

#define PWM_CTRL_DT

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)

DT - Deadtime

PWM_CTRL_FULL [1/2]

#define PWM_CTRL_FULL

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)

FULL - Full Cycle Reload 0b0..Full-cycle reloads disabled. 0b1..Full-cycle reloads enabled.

PWM_CTRL_FULL [2/2]

#define PWM_CTRL_FULL

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)

FULL - Full Cycle Reload 0b0..Full-cycle reloads disabled. 0b1..Full-cycle reloads enabled.

PWM_CTRL_HALF [1/2]

#define PWM_CTRL_HALF

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)

HALF - Half Cycle Reload 0b0..Half-cycle reloads disabled. 0b1..Half-cycle reloads enabled.

PWM_CTRL_HALF [2/2]

#define PWM_CTRL_HALF

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)

HALF - Half Cycle Reload 0b0..Half-cycle reloads disabled. 0b1..Half-cycle reloads enabled.

PWM_CTRL_LDFQ [1/2]

#define PWM_CTRL_LDFQ

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)

LDFQ - Load Frequency 0b0000..Every PWM opportunity 0b0001..Every 2 PWM opportunities 0b0010..Every 3 PWM opportunities 0b0011..Every 4 PWM opportunities 0b0100..Every 5 PWM opportunities 0b0101..Every 6 PWM opportunities 0b0110..Every 7 PWM opportunities 0b0111..Every 8 PWM opportunities 0b1000..Every 9 PWM opportunities 0b1001..Every 10 PWM opportunities 0b1010..Every 11 PWM opportunities 0b1011..Every 12 PWM opportunities 0b1100..Every 13 PWM opportunities 0b1101..Every 14 PWM opportunities 0b1110..Every 15 PWM opportunities 0b1111..Every 16 PWM opportunities

PWM_CTRL_LDFQ [2/2]

#define PWM_CTRL_LDFQ

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)

LDFQ - Load Frequency 0b0000..Every PWM opportunity 0b0001..Every 2 PWM opportunities 0b0010..Every 3 PWM opportunities 0b0011..Every 4 PWM opportunities 0b0100..Every 5 PWM opportunities 0b0101..Every 6 PWM opportunities 0b0110..Every 7 PWM opportunities 0b0111..Every 8 PWM opportunities 0b1000..Every 9 PWM opportunities 0b1001..Every 10 PWM opportunities 0b1010..Every 11 PWM opportunities 0b1011..Every 12 PWM opportunities 0b1100..Every 13 PWM opportunities 0b1101..Every 14 PWM opportunities 0b1110..Every 15 PWM opportunities 0b1111..Every 16 PWM opportunities

PWM_CTRL_LDMOD [1/2]

#define PWM_CTRL_LDMOD

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)

LDMOD - Load Mode Select 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].

PWM_CTRL_LDMOD [2/2]

#define PWM_CTRL_LDMOD

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)

LDMOD - Load Mode Select 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set. 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set. In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].

PWM_CTRL_PRSC [1/2]

#define PWM_CTRL_PRSC

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)

PRSC - Prescaler 0b000..Prescaler 1 0b001..Prescaler 2 0b010..Prescaler 4 0b011..Prescaler 8 0b100..Prescaler 16 0b101..Prescaler 32 0b110..Prescaler 64 0b111..Prescaler 128

PWM_CTRL_PRSC [2/2]

#define PWM_CTRL_PRSC

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)

PRSC - Prescaler 0b000..Prescaler 1 0b001..Prescaler 2 0b010..Prescaler 4 0b011..Prescaler 8 0b100..Prescaler 16 0b101..Prescaler 32 0b110..Prescaler 64 0b111..Prescaler 128

PWM_CTRL_SPLIT [1/2]

#define PWM_CTRL_SPLIT

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)

SPLIT - Split the DBLPWM signal to PWMA and PWMB 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses. 0b1..DBLPWM is split to PWMA and PWMB.

PWM_CTRL_SPLIT [2/2]

#define PWM_CTRL_SPLIT

(

x

)

(((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)

SPLIT - Split the DBLPWM signal to PWMA and PWMB 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses. 0b1..DBLPWM is split to PWMA and PWMB.

SRAM_CTRL_LOCK_BIT [1/2]

#define SRAM_CTRL_LOCK_BIT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_LOCK_BIT_SHIFT)) & SRAM_CTRL_LOCK_BIT_MASK)

LOCK_BIT - Lock bits

SRAM_CTRL_LOCK_BIT [2/2]

#define SRAM_CTRL_LOCK_BIT

(

x

)

(((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_LOCK_BIT_SHIFT)) & SRAM_CTRL_LOCK_BIT_MASK)

LOCK_BIT - Lock bits

SRAM_CTRL_PWR_EN [1/2]

#define SRAM_CTRL_PWR_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_PWR_EN_SHIFT)) & SRAM_CTRL_PWR_EN_MASK)

PWR_EN - Power Enable (with lock)

SRAM_CTRL_PWR_EN [2/2]

#define SRAM_CTRL_PWR_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_PWR_EN_SHIFT)) & SRAM_CTRL_PWR_EN_MASK)

PWR_EN - Power Enable (with lock)

SRAM_CTRL_RAM_RD_EN [1/2]

#define SRAM_CTRL_RAM_RD_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_RD_EN_SHIFT)) & SRAM_CTRL_RAM_RD_EN_MASK)

RAM_RD_EN - RAM Read Enable (with lock) 0b0..Disable read access 0b1..Enable read access

SRAM_CTRL_RAM_RD_EN [2/2]

#define SRAM_CTRL_RAM_RD_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_RD_EN_SHIFT)) & SRAM_CTRL_RAM_RD_EN_MASK)

RAM_RD_EN - RAM Read Enable (with lock) 0b0..Disable read access 0b1..Enable read access

SRAM_CTRL_RAM_WR_EN [1/2]

#define SRAM_CTRL_RAM_WR_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_WR_EN_SHIFT)) & SRAM_CTRL_RAM_WR_EN_MASK)

RAM_WR_EN - RAM Write Enable (with lock) 0b0..Disable write access 0b1..Enable write access

SRAM_CTRL_RAM_WR_EN [2/2]

#define SRAM_CTRL_RAM_WR_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_WR_EN_SHIFT)) & SRAM_CTRL_RAM_WR_EN_MASK)

RAM_WR_EN - RAM Write Enable (with lock) 0b0..Disable write access 0b1..Enable write access

SRAM_CTRL_TAMPER_BLOCK_EN [1/2]

#define SRAM_CTRL_TAMPER_BLOCK_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT)) & SRAM_CTRL_TAMPER_BLOCK_EN_MASK)

TAMPER_BLOCK_EN - Tamper Block Enable (with lock) 0b0..Allow R/W access to secure RAM when tamper is detected 0b1..Block R/W access to secure RAM when tamper is detected

SRAM_CTRL_TAMPER_BLOCK_EN [2/2]

#define SRAM_CTRL_TAMPER_BLOCK_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT)) & SRAM_CTRL_TAMPER_BLOCK_EN_MASK)

TAMPER_BLOCK_EN - Tamper Block Enable (with lock) 0b0..Allow R/W access to secure RAM when tamper is detected 0b1..Block R/W access to secure RAM when tamper is detected

SRAM_CTRL_TAMPER_PWR_OFF_EN [1/2]

#define SRAM_CTRL_TAMPER_PWR_OFF_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT)) & SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK)

TAMPER_PWR_OFF_EN - Turn off power on tamper event (with lock) 0b0..Disable the turn off function when tamper is detected 0b1..Turn off power for all secure RAM banks when tamper is detected

SRAM_CTRL_TAMPER_PWR_OFF_EN [2/2]

#define SRAM_CTRL_TAMPER_PWR_OFF_EN

(

x

)

(((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT)) & SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK)

TAMPER_PWR_OFF_EN - Turn off power on tamper event (with lock) 0b0..Disable the turn off function when tamper is detected 0b1..Turn off power for all secure RAM banks when tamper is detected

SSARC_LP_CTRL_DIS_HW_REQ [1/2]

#define SSARC_LP_CTRL_DIS_HW_REQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_DIS_HW_REQ_SHIFT)) & SSARC_LP_CTRL_DIS_HW_REQ_MASK)

DIS_HW_REQ - Save/Restore request disable 0b0..PGMC save/restore requests enabled 0b1..PGMC save/restore requests disabled

SSARC_LP_CTRL_DIS_HW_REQ [2/2]

#define SSARC_LP_CTRL_DIS_HW_REQ

(

x

)

(((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_DIS_HW_REQ_SHIFT)) & SSARC_LP_CTRL_DIS_HW_REQ_MASK)

DIS_HW_REQ - Save/Restore request disable 0b0..PGMC save/restore requests enabled 0b1..PGMC save/restore requests disabled

SSARC_LP_CTRL_SW_RESET [1/2]

#define SSARC_LP_CTRL_SW_RESET

(

x

)

(((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_SW_RESET_SHIFT)) & SSARC_LP_CTRL_SW_RESET_MASK)

SW_RESET - Software reset

SSARC_LP_CTRL_SW_RESET [2/2]

#define SSARC_LP_CTRL_SW_RESET

(

x

)

(((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_SW_RESET_SHIFT)) & SSARC_LP_CTRL_SW_RESET_MASK)

SW_RESET - Software reset