RTEMS 6.1-rc2
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Modules | |
EMVSIM Register Masks | |
Data Structures | |
struct | EMVSIM_Type |
Macros | |
#define | EMVSIM1_BASE (0x40154000u) |
#define | EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) |
#define | EMVSIM2_BASE (0x40158000u) |
#define | EMVSIM2 ((EMVSIM_Type *)EMVSIM2_BASE) |
#define | EMVSIM_BASE_ADDRS { 0u, EMVSIM1_BASE, EMVSIM2_BASE } |
#define | EMVSIM_BASE_PTRS { (EMVSIM_Type *)0u, EMVSIM1, EMVSIM2 } |
#define | EMVSIM_IRQS { NotAvail_IRQn, EMVSIM1_IRQn, EMVSIM2_IRQn } |
#define | EMVSIM1_BASE (0x40154000u) |
#define | EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) |
#define | EMVSIM2_BASE (0x40158000u) |
#define | EMVSIM2 ((EMVSIM_Type *)EMVSIM2_BASE) |
#define | EMVSIM_BASE_ADDRS { 0u, EMVSIM1_BASE, EMVSIM2_BASE } |
#define | EMVSIM_BASE_PTRS { (EMVSIM_Type *)0u, EMVSIM1, EMVSIM2 } |
#define | EMVSIM_IRQS { NotAvail_IRQn, EMVSIM1_IRQn, EMVSIM2_IRQn } |
#define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) |
Peripheral EMVSIM1 base pointer
#define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) |
Peripheral EMVSIM1 base pointer
#define EMVSIM1_BASE (0x40154000u) |
Peripheral EMVSIM1 base address
#define EMVSIM1_BASE (0x40154000u) |
Peripheral EMVSIM1 base address
#define EMVSIM2 ((EMVSIM_Type *)EMVSIM2_BASE) |
Peripheral EMVSIM2 base pointer
#define EMVSIM2 ((EMVSIM_Type *)EMVSIM2_BASE) |
Peripheral EMVSIM2 base pointer
#define EMVSIM2_BASE (0x40158000u) |
Peripheral EMVSIM2 base address
#define EMVSIM2_BASE (0x40158000u) |
Peripheral EMVSIM2 base address
#define EMVSIM_BASE_ADDRS { 0u, EMVSIM1_BASE, EMVSIM2_BASE } |
Array initializer of EMVSIM peripheral base addresses
#define EMVSIM_BASE_ADDRS { 0u, EMVSIM1_BASE, EMVSIM2_BASE } |
Array initializer of EMVSIM peripheral base addresses
#define EMVSIM_BASE_PTRS { (EMVSIM_Type *)0u, EMVSIM1, EMVSIM2 } |
Array initializer of EMVSIM peripheral base pointers
#define EMVSIM_BASE_PTRS { (EMVSIM_Type *)0u, EMVSIM1, EMVSIM2 } |
Array initializer of EMVSIM peripheral base pointers
#define EMVSIM_IRQS { NotAvail_IRQn, EMVSIM1_IRQn, EMVSIM2_IRQn } |
Interrupt vectors for the EMVSIM peripheral type
#define EMVSIM_IRQS { NotAvail_IRQn, EMVSIM1_IRQn, EMVSIM2_IRQn } |
Interrupt vectors for the EMVSIM peripheral type