fsl_pxp.h

/*
 * Copyright 2017-2022 NXP
 * All rights reserved.
 *
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
 
#ifndef _FSL_PXP_H_
#define _FSL_PXP_H_
 
#include "fsl_common.h"
 
/* Compatibility macro map. */
#if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA0_INVERT_MASK))
#define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK
#endif
 
#if defined(PXP_AS_CTRL_ALPHA_INVERT_MASK) && (!defined(PXP_AS_CTRL_ALPHA_INVERT_MASK))
#define PXP_AS_CTRL_ALPHA0_INVERT_MASK PXP_AS_CTRL_ALPHA_INVERT_MASK
#endif
 
#if defined(PXP_STAT_IRQ_MASK) && (!defined(PXP_STAT_IRQ0_MASK))
#define PXP_STAT_IRQ0_MASK PXP_STAT_IRQ_MASK
#endif
 
#if defined(PXP_STAT_AXI_READ_ERROR_MASK) && (!defined(PXP_STAT_AXI_READ_ERROR_0_MASK))
#define PXP_STAT_AXI_READ_ERROR_0_MASK PXP_STAT_AXI_READ_ERROR_MASK
#endif
 
#if defined(PXP_STAT_AXI_WRITE_ERROR_MASK) && (!defined(PXP_STAT_AXI_WRITE_ERROR_0_MASK))
#define PXP_STAT_AXI_WRITE_ERROR_0_MASK PXP_STAT_AXI_WRITE_ERROR_MASK
#endif
 
/*******************************************************************************
 * Definitions
 ******************************************************************************/
 
/* PXP global LUT table is 16K. */
#define PXP_LUT_TABLE_BYTE (16UL * 1024UL)
/* Intenral memory for LUT, the size is 256 bytes. */
#define PXP_INTERNAL_RAM_LUT_BYTE (256)
 
#define FSL_PXP_DRIVER_VERSION (MAKE_VERSION(2, 4, 1))
/* This macto indicates whether the rotate sub module is shared by process surface and output buffer. */
#if defined(PXP_CTRL_ROT_POS_MASK)
#define PXP_SHARE_ROTATE 1
#else
#define PXP_SHARE_ROTATE 0
#endif
 
/* This macto indicates whether PXP needs mux the process path. */
#if defined(PXP_DATA_PATH_CTRL0_MUX0_SEL_MASK)
#define PXP_USE_PATH 1
#else
#define PXP_USE_PATH 0
#endif
 
#if PXP_USE_PATH
#define PXP_PATH(mux, sel)          (((mux) << 8U) | (sel))
#define PXP_GET_MUX_FROM_PATH(path) ((path) >> 8U)
#define PXP_GET_SEL_FROM_PATH(path) ((path)&0x03U)
#endif /* PXP_USE_PATH */
 
enum _pxp_interrupt_enable
{
    kPXP_CompleteInterruptEnable    = PXP_CTRL_IRQ_ENABLE_MASK,      
    kPXP_CommandLoadInterruptEnable = PXP_CTRL_NEXT_IRQ_ENABLE_MASK, 
#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
    kPXP_LutDmaLoadInterruptEnable =
        PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK, 
#endif
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
    kPXP_CompressDoneInterruptEnable =
        PXP_IRQ_MASK_COMPRESS_DONE_IRQ_EN_MASK >> 16U, 
    kPXP_InputFetchCh0InterruptEnable = PXP_IRQ_MASK_FIRST_CH0_PREFETCH_IRQ_EN_MASK
                                        << 16U, 
    kPXP_InputFetchCh1InterruptEnable = PXP_IRQ_MASK_FIRST_CH1_PREFETCH_IRQ_EN_MASK
                                        << 16U, 
    kPXP_InputStoreCh0InterruptEnable = PXP_IRQ_MASK_FIRST_CH0_STORE_IRQ_EN_MASK
                                        << 16U, 
    kPXP_InputStoreCh1InterruptEnable = PXP_IRQ_MASK_FIRST_CH1_STORE_IRQ_EN_MASK
                                        << 16U, 
    kPXP_DitherFetchCh0InterruptEnable = PXP_IRQ_MASK_DITHER_CH0_PREFETCH_IRQ_EN_MASK
                                         << 16U, 
    kPXP_DitherFetchCh1InterruptEnable = PXP_IRQ_MASK_DITHER_CH1_PREFETCH_IRQ_EN_MASK
                                         << 16U, 
    kPXP_DitherStoreCh0InterruptEnable = PXP_IRQ_MASK_DITHER_CH0_STORE_IRQ_EN_MASK
                                         << 16U, 
    kPXP_DitherStoreCh1InterruptEnable = PXP_IRQ_MASK_DITHER_CH1_STORE_IRQ_EN_MASK
                                         << 16U, 
    kPXP_WfeaStoreCh0InterruptEnable = PXP_IRQ_MASK_WFE_A_CH0_STORE_IRQ_EN_MASK
                                       << 16U, 
    kPXP_WfeaStoreCh1InterruptEnable = PXP_IRQ_MASK_WFE_A_CH1_STORE_IRQ_EN_MASK
                                       << 16U, 
    kPXP_WfebStoreCh0InterruptEnable = PXP_IRQ_MASK_WFE_B_CH0_STORE_IRQ_EN_MASK
                                       << 16U, 
    kPXP_WfebStoreCh1InterruptEnable = PXP_IRQ_MASK_WFE_B_CH1_STORE_IRQ_EN_MASK
                                       << 16U, 
    kPXP_InputStoreInterruptEnable  = PXP_IRQ_MASK_FIRST_STORE_IRQ_EN_MASK << 16U, 
    kPXP_DitherStoreInterruptEnable = PXP_IRQ_MASK_DITHER_STORE_IRQ_EN_MASK
                                      << 16U,                                    
    kPXP_WfeaStoreInterruptEnable = PXP_IRQ_MASK_WFE_A_STORE_IRQ_EN_MASK << 16U, 
    kPXP_WfebStoreInterruptEnable = PXP_IRQ_MASK_WFE_B_STORE_IRQ_EN_MASK << 16U, 
#endif                                                                           /* FSL_FEATURE_PXP_V3 */
};
 
enum _pxp_flags
{
    kPXP_CompleteFlag       = PXP_STAT_IRQ0_MASK,              
    kPXP_Axi0WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_0_MASK, 
    kPXP_Axi0ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_0_MASK,   
    kPXP_CommandLoadFlag = PXP_STAT_NEXT_IRQ_MASK, 
#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
    kPXP_LutDmaLoadFlag = PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK, 
#endif
#if defined(PXP_STAT_AXI_READ_ERROR_1_MASK)
    kPXP_Axi1WriteErrorFlag = PXP_STAT_AXI_WRITE_ERROR_1_MASK, 
    kPXP_Axi1ReadErrorFlag = PXP_STAT_AXI_READ_ERROR_1_MASK,   
#endif
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
    kPXP_CompressDoneFlag          = PXP_IRQ_COMPRESS_DONE_IRQ_MASK >> 16U, 
    kPXP_InputFetchCh0CompleteFlag = PXP_IRQ_FIRST_CH0_PREFETCH_IRQ_MASK
                                     << 16U, 
    kPXP_InputFetchCh1CompleteFlag = PXP_IRQ_FIRST_CH1_PREFETCH_IRQ_MASK
                                     << 16U, 
    kPXP_InputStoreCh0CompleteFlag = PXP_IRQ_FIRST_CH0_STORE_IRQ_MASK
                                     << 16U, 
    kPXP_InputStoreCh1CompleteFlag = PXP_IRQ_FIRST_CH1_STORE_IRQ_MASK
                                     << 16U, 
    kPXP_DitherFetchCh0CompleteFlag = PXP_IRQ_DITHER_CH0_PREFETCH_IRQ_MASK
                                      << 16U, 
    kPXP_DitherFetchCh1CompleteFlag = PXP_IRQ_DITHER_CH1_PREFETCH_IRQ_MASK
                                      << 16U, 
    kPXP_DitherStoreCh0CompleteFlag = PXP_IRQ_DITHER_CH0_STORE_IRQ_MASK
                                      << 16U, 
    kPXP_DitherStoreCh1CompleteFlag = PXP_IRQ_DITHER_CH1_STORE_IRQ_MASK
                                      << 16U, 
    kPXP_WfeaStoreCh0CompleteFlag = PXP_IRQ_WFE_A_CH0_STORE_IRQ_MASK
                                    << 16U, 
    kPXP_WfeaStoreCh1CompleteFlag = PXP_IRQ_WFE_A_CH1_STORE_IRQ_MASK
                                    << 16U, 
    kPXP_WfebStoreCh0CompleteFlag = PXP_IRQ_WFE_B_CH0_STORE_IRQ_MASK
                                    << 16U, 
    kPXP_WfebStoreCh1CompleteFlag = PXP_IRQ_WFE_B_CH1_STORE_IRQ_MASK
                                    << 16U,                              
    kPXP_InputStoreCompleteFlag  = PXP_IRQ_FIRST_STORE_IRQ_MASK << 16U,  
    kPXP_DitherStoreCompleteFlag = PXP_IRQ_DITHER_STORE_IRQ_MASK << 16U, 
    kPXP_WfeaStoreCompleteFlag   = PXP_IRQ_WFE_A_STORE_IRQ_MASK << 16U,  
    kPXP_WfebStoreCompleteFlag   = PXP_IRQ_WFE_B_STORE_IRQ_MASK << 16U,  
#endif                                                                   /* FSL_FEATURE_PXP_V3 */
};
 
#if PXP_USE_PATH
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
typedef enum _pxp_path
{
    kPXP_Mux0SelectProcessSurfaceEngine     = PXP_PATH(0U, 0U), 
    kPXP_Mux0SelectInputFetchEngineChannel0 = PXP_PATH(0U, 1U), 
    kPXP_Mux0SelectInputFetchEngineChannel1 = PXP_PATH(0U, 2U), 
    kPXP_Mux0SelectNone                     = PXP_PATH(0U, 3U), 
    kPXP_Mux1SelectInputFetchEngineChannel0 = PXP_PATH(1U, 0U), 
    kPXP_Mux1SelectRotation1Engine          = PXP_PATH(1U, 1U), 
    kPXP_Mux1SelectNone                     = PXP_PATH(1U, 2U), 
    kPXP_Mux2SelectInputFetchEngineChannel1 = PXP_PATH(2U, 0U), 
    kPXP_Mux2SelectRotation1Engine          = PXP_PATH(2U, 1U), 
    kPXP_Mux2SelectNone                     = PXP_PATH(2U, 2U), 
    kPXP_Mux3SelectCsc1Engine               = PXP_PATH(3U, 0U), 
    kPXP_Mux3SelectRotation1Engine          = PXP_PATH(3U, 1U), 
    kPXP_Mux3SelectNone                     = PXP_PATH(3U, 2U), 
    kPXP_Mux5SelectMux1                     = PXP_PATH(5U, 0U), 
    kPXP_Mux5SelectAlphaBlending1       = PXP_PATH(5U, 1U),  
    kPXP_Mux5SelectNone                 = PXP_PATH(5U, 2U),  
    kPXP_Mux6SelectAlphaBlending1       = PXP_PATH(6U, 0U),  
    kPXP_Mux6SelectAlphaBlending0       = PXP_PATH(6U, 1U),  
    kPXP_Mux6SelectNone                 = PXP_PATH(6U, 2U),  
    kPXP_Mux7SelectMux5                 = PXP_PATH(7U, 0U),  
    kPXP_Mux7SelectCsc2Engine           = PXP_PATH(7U, 1U),  
    kPXP_Mux7SelectNone                 = PXP_PATH(7U, 2U),  
    kPXP_Mux8SelectCsc2Engine           = PXP_PATH(8U, 0U),  
    kPXP_Mux8SelectAlphaBlending0       = PXP_PATH(8U, 1U),  
    kPXP_Mux8SelectNone                 = PXP_PATH(8U, 2U),  
    kPXP_Mux9SelectMux7                 = PXP_PATH(9U, 0U),  
    kPXP_Mux9SelectMux8                 = PXP_PATH(9U, 1U),  
    kPXP_Mux9SelectNone                 = PXP_PATH(9U, 2U),  
    kPXP_Mux10SelectMux7                = PXP_PATH(10U, 0U), 
    kPXP_Mux10SelectLut                 = PXP_PATH(10U, 1U), 
    kPXP_Mux10SelectNone                = PXP_PATH(10U, 2U), 
    kPXP_Mux11SelectLut                 = PXP_PATH(11U, 0U), 
    kPXP_Mux11SelectMux8                = PXP_PATH(11U, 1U), 
    kPXP_Mux11SelectNone                = PXP_PATH(11U, 2U), 
    kPXP_Mux12SelectMux10               = PXP_PATH(12U, 0U), 
    kPXP_Mux12SelectMux11               = PXP_PATH(12U, 1U), 
    kPXP_Mux12SelectNone                = PXP_PATH(12U, 2U), 
    kPXP_Mux13SelectNone                = PXP_PATH(13U, 0U), 
    kPXP_Mux13SelectFetchEngineChannel1 = PXP_PATH(13U, 1U), 
    kPXP_Mux14SelectRotation0Engine     = PXP_PATH(14U, 0U), 
    kPXP_Mux14SelectMux11               = PXP_PATH(14U, 1U), 
    kPXP_Mux14SelectNone                = PXP_PATH(14U, 2U), 
    kPXP_Mux15SelectFetchEngineChannel0 = PXP_PATH(15U, 0U), 
    kPXP_Mux15SelectMux10               = PXP_PATH(15U, 1U), 
    kPXP_Mux15SelectNone                = PXP_PATH(15U, 2U), 
    kPXP_Mux16SelectAluA                = PXP_PATH(16U, 0U), 
    kPXP_Mux16SelectOutput              = PXP_PATH(16U, 1U), 
    kPXP_Mux16SelectAluB                = PXP_PATH(16U, 2U), 
    kPXP_Mux16SelectNone                = PXP_PATH(16U, 3U), 
    kPXP_Mux17SelectAluA                = PXP_PATH(17U, 0U), 
    kPXP_Mux17SelectAluB                = PXP_PATH(17U, 1U), 
    kPXP_Mux17SelectNone                = PXP_PATH(17U, 2U), 
} pxp_path_t;
#else
typedef enum _pxp_path
{
    kPXP_Mux0SelectFetchDataArray   = PXP_PATH(0U, 0U),  
    kPXP_Mux0SelectAlu              = PXP_PATH(0U, 1U),  
    kPXP_Mux0SelectNone             = PXP_PATH(0U, 2U),  
    kPXP_Mux1SelectLut              = PXP_PATH(1U, 0U),  
    kPXP_Mux1SelectMux0             = PXP_PATH(1U, 1U),  
    kPXP_Mux1SelectNone             = PXP_PATH(1U, 2U),  
    kPXP_Mux3SelectRotation1Engine  = PXP_PATH(3U, 0U),  
    kPXP_Mux3SelectCsc1Engine       = PXP_PATH(3U, 1U),  
    kPXP_Mux3SelectNone             = PXP_PATH(3U, 2U),  
    kPXP_Mux8SelectCsc2Engine       = PXP_PATH(8U, 0U),  
    kPXP_Mux8SelectAlphaBlending0   = PXP_PATH(8U, 1U),  
    kPXP_Mux8SelectNone             = PXP_PATH(8U, 2U),  
    kPXP_Mux9SelectMux0             = PXP_PATH(9U, 0U),  
    kPXP_Mux9SelectMux8             = PXP_PATH(9U, 1U),  
    kPXP_Mux9SelectNone             = PXP_PATH(9U, 2U),  
    kPXP_Mux11SelectLut             = PXP_PATH(11U, 0U), 
    kPXP_Mux11SelectMux8            = PXP_PATH(11U, 1U), 
    kPXP_Mux11SelectNone            = PXP_PATH(11U, 2U), 
    kPXP_Mux12SelectRotation0Engine = PXP_PATH(12U, 0U), 
    kPXP_Mux12SelectMux11           = PXP_PATH(12U, 1U), 
    kPXP_Mux12SelectNone            = PXP_PATH(12U, 2U), 
    kPXP_Mux14SelectDitherEngine    = PXP_PATH(14U, 0U), 
    kPXP_Mux14SelectMux12           = PXP_PATH(14U, 1U), 
    kPXP_Mux14SelectNone            = PXP_PATH(14U, 2U), 
    kPXP_Mux16SelectOutputBuffer    = PXP_PATH(16U, 0U), 
    kPXP_Mux16SelectStoreEngine     = PXP_PATH(16U, 1U), 
    kPXP_Mux16SelectNone            = PXP_PATH(16U, 2U), 
    kPXP_Mux17SelectOutputBuffer    = PXP_PATH(17U, 0U), 
    kPXP_Mux17SelectStoreEngine     = PXP_PATH(17U, 1U), 
    kPXP_Mux17SelectNone            = PXP_PATH(17U, 2U), 
} pxp_path_t;
#endif /* FSL_FEATURE_PXP_V3 */
#endif /* PXP_USE_PATH */
 
typedef enum _pxp_flip_mode
{
    kPXP_FlipDisable    = 0U,    
    kPXP_FlipHorizontal = 0x01U, 
    kPXP_FlipVertical   = 0x02U, 
    kPXP_FlipBoth       = 0x03U, 
} pxp_flip_mode_t;
 
typedef enum _pxp_rotate_position
{
    kPXP_RotateOutputBuffer = 0U, 
    kPXP_RotateProcessSurface,    
} pxp_rotate_position_t;
 
typedef enum _pxp_rotate_degree
{
    kPXP_Rotate0 = 0U, 
    kPXP_Rotate90,     
    kPXP_Rotate180,    
    kPXP_Rotate270,    
} pxp_rotate_degree_t;
 
typedef enum _pxp_interlaced_output_mode
{
    kPXP_OutputProgressive = 0U, 
    kPXP_OutputField0,           
    kPXP_OutputField1,           
    kPXP_OutputInterlaced,       
} pxp_interlaced_output_mode_t;
 
typedef enum _pxp_output_pixel_format
{
    kPXP_OutputPixelFormatARGB8888  = 0x0,  
    kPXP_OutputPixelFormatRGB888    = 0x4,  
    kPXP_OutputPixelFormatRGB888P   = 0x5,  
    kPXP_OutputPixelFormatARGB1555  = 0x8,  
    kPXP_OutputPixelFormatARGB4444  = 0x9,  
    kPXP_OutputPixelFormatRGB555    = 0xC,  
    kPXP_OutputPixelFormatRGB444    = 0xD,  
    kPXP_OutputPixelFormatRGB565    = 0xE,  
    kPXP_OutputPixelFormatYUV1P444  = 0x10, 
    kPXP_OutputPixelFormatUYVY1P422 = 0x12, 
    kPXP_OutputPixelFormatVYUY1P422 = 0x13, 
    kPXP_OutputPixelFormatY8        = 0x14, 
    kPXP_OutputPixelFormatY4        = 0x15, 
    kPXP_OutputPixelFormatYUV2P422  = 0x18, 
    kPXP_OutputPixelFormatYUV2P420  = 0x19, 
    kPXP_OutputPixelFormatYVU2P422  = 0x1A, 
    kPXP_OutputPixelFormatYVU2P420  = 0x1B, 
} pxp_output_pixel_format_t;
 
typedef struct _pxp_output_buffer_config
{
    pxp_output_pixel_format_t pixelFormat;       
    pxp_interlaced_output_mode_t interlacedMode; 
    uint32_t buffer0Addr;                        
    uint32_t buffer1Addr;                        
    uint16_t pitchBytes;                         
    uint16_t width;                              
    uint16_t height;                             
} pxp_output_buffer_config_t;
 
typedef enum _pxp_ps_pixel_format
{
    kPXP_PsPixelFormatRGB888    = 0x4,  
    kPXP_PsPixelFormatRGB555    = 0xC,  
    kPXP_PsPixelFormatRGB444    = 0xD,  
    kPXP_PsPixelFormatRGB565    = 0xE,  
    kPXP_PsPixelFormatYUV1P444  = 0x10, 
    kPXP_PsPixelFormatUYVY1P422 = 0x12, 
    kPXP_PsPixelFormatVYUY1P422 = 0x13, 
    kPXP_PsPixelFormatY8        = 0x14, 
    kPXP_PsPixelFormatY4        = 0x15, 
    kPXP_PsPixelFormatYUV2P422  = 0x18, 
    kPXP_PsPixelFormatYUV2P420  = 0x19, 
    kPXP_PsPixelFormatYVU2P422  = 0x1A, 
    kPXP_PsPixelFormatYVU2P420  = 0x1B, 
    kPXP_PsPixelFormatYVU422    = 0x1E, 
    kPXP_PsPixelFormatYVU420    = 0x1F, 
} pxp_ps_pixel_format_t;
 
typedef enum _pxp_ps_yuv_format
{
    kPXP_PsYUVFormatYUV = 0U, 
    kPXP_PsYUVFormatYCbCr,    
} pxp_ps_yuv_format_t;
 
typedef struct _pxp_ps_buffer_config
{
    pxp_ps_pixel_format_t pixelFormat; 
    bool swapByte;                     
    uint32_t bufferAddr;               
    uint32_t bufferAddrU;              
    uint32_t bufferAddrV;              
    uint16_t pitchBytes;               
} pxp_ps_buffer_config_t;
 
typedef enum _pxp_as_pixel_format
{
    kPXP_AsPixelFormatARGB8888 = 0x0, 
    kPXP_AsPixelFormatRGB888   = 0x4, 
    kPXP_AsPixelFormatARGB1555 = 0x8, 
    kPXP_AsPixelFormatARGB4444 = 0x9, 
    kPXP_AsPixelFormatRGB555   = 0xC, 
    kPXP_AsPixelFormatRGB444   = 0xD, 
    kPXP_AsPixelFormatRGB565   = 0xE, 
} pxp_as_pixel_format_t;
 
typedef struct _pxp_as_buffer_config
{
    pxp_as_pixel_format_t pixelFormat; 
    uint32_t bufferAddr;               
    uint16_t pitchBytes;               
} pxp_as_buffer_config_t;
 
typedef enum _pxp_alpha_mode
{
    kPXP_AlphaEmbedded, 
    kPXP_AlphaOverride, 
    kPXP_AlphaMultiply, 
    kPXP_AlphaRop       
} pxp_alpha_mode_t;
 
typedef enum _pxp_rop_mode
{
    kPXP_RopMaskAs     = 0x0, 
    kPXP_RopMaskNotAs  = 0x1, 
    kPXP_RopMaskAsNot  = 0x2, 
    kPXP_RopMergeAs    = 0x3, 
    kPXP_RopMergeNotAs = 0x4, 
    kPXP_RopMergeAsNot = 0x5, 
    kPXP_RopNotCopyAs  = 0x6, 
    kPXP_RopNot        = 0x7, 
    kPXP_RopNotMaskAs  = 0x8, 
    kPXP_RopNotMergeAs = 0x9, 
    kPXP_RopXorAs      = 0xA, 
    kPXP_RopNotXorAs   = 0xB  
} pxp_rop_mode_t;
 
typedef struct _pxp_as_blend_config
{
    uint8_t alpha;    
    bool invertAlpha; 
    pxp_alpha_mode_t alphaMode; 
    pxp_rop_mode_t ropMode;     
} pxp_as_blend_config_t;
 
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
typedef struct _pxp_as_blend_secondary_config
{
    bool invertAlpha;       
    bool ropEnable;         
    pxp_rop_mode_t ropMode; 
} pxp_as_blend_secondary_config_t;
#endif /* FSL_FEATURE_PXP_V3 */
 
typedef enum _pxp_block_size
{
    kPXP_BlockSize8 = 0U, 
    kPXP_BlockSize16,     
} pxp_block_size_t;
 
typedef enum _pxp_csc1_mode
{
    kPXP_Csc1YUV2RGB = 0U, 
    kPXP_Csc1YCbCr2RGB,    
} pxp_csc1_mode_t;
 
typedef enum _pxp_csc2_mode
{
    kPXP_Csc2YUV2RGB = 0U, 
    kPXP_Csc2YCbCr2RGB,    
    kPXP_Csc2RGB2YUV,      
    kPXP_Csc2RGB2YCbCr,    
} pxp_csc2_mode_t;
 
typedef struct _pxp_csc2_config
{
    pxp_csc2_mode_t mode; 
    float A1;             
    float A2;             
    float A3;             
    float B1;             
    float B2;             
    float B3;             
    float C1;             
    float C2;             
    float C3;             
    int16_t D1;           
    int16_t D2;           
    int16_t D3;           
} pxp_csc2_config_t;
 
#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
typedef enum _pxp_lut_lookup_mode
{
    kPXP_LutCacheRGB565 = 0U, 
    kPXP_LutDirectY8,         
    kPXP_LutDirectRGB444,     
    kPXP_LutDirectRGB454,     
} pxp_lut_lookup_mode_t;
 
typedef enum _pxp_lut_out_mode
{
    kPXP_LutOutY8 = 1U,     
    kPXP_LutOutRGBW4444CFA, 
    kPXP_LutOutRGB888,      
} pxp_lut_out_mode_t;
 
typedef enum _pxp_lut_8k_bank
{
    kPXP_Lut8kBank0 = 0U, 
    kPXP_Lut8kBank1,      
} pxp_lut_8k_bank_t;
 
typedef struct _pxp_lut_config
{
    pxp_lut_lookup_mode_t lookupMode; 
    pxp_lut_out_mode_t outMode;       
    uint32_t cfaValue;                
} pxp_lut_config_t;
#endif /* FSL_FEATURE_PXP_HAS_NO_LUT */
 
typedef enum _pxp_ram
{
    kPXP_RamDither0Lut = 0U, 
    kPXP_RamDither1Lut = 3U, 
    kPXP_RamDither2Lut = 4U, 
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
    kPXP_RamDither0Err0 = 1U, 
    kPXP_RamDither0Err1 = 2U, 
    kPXP_RamAluA        = 5U, 
    kPXP_RamAluB        = 6U, 
    kPXP_WfeAFetch      = 7U, 
    kPXP_WfeBFetch      = 8U, 
#endif                        /* FSL_FEATURE_PXP_V3 */
} pxp_ram_t;
 
enum _pxp_dither_mode
{
    kPXP_DitherPassThrough    = 0U, 
    kPXP_DitherFloydSteinberg = 1U, 
    kPXP_DitherAtkinson       = 2U, 
    kPXP_DitherOrdered        = 3U, 
    kPXP_DitherQuantOnly      = 4U, 
    kPXP_DitherSierra         = 5U, 
};
 
enum _pxp_dither_lut_mode
{
    kPXP_DitherLutOff = 0U,   
    kPXP_DitherLutPreDither,  
    kPXP_DitherLutPostDither, 
};
 
enum _pxp_dither_matrix_size
{
    kPXP_DitherMatrix4 = 0, 
    kPXP_DitherMatrix8,     
    kPXP_DitherMatrix16,    
};
 
typedef struct _pxp_dither_final_lut_data
{
    uint32_t data_3_0;   
    uint32_t data_7_4;   
    uint32_t data_11_8;  
    uint32_t data_15_12; 
} pxp_dither_final_lut_data_t;
 
typedef struct _pxp_dither_config
{
    uint32_t enableDither0 : 1;  
    uint32_t enableDither1 : 1;  
    uint32_t enableDither2 : 1;  
    uint32_t ditherMode0 : 3;    
    uint32_t ditherMode1 : 3;    
    uint32_t ditherMode2 : 3;    
    uint32_t quantBitNum : 3;    
    uint32_t lutMode : 2;        
    uint32_t idxMatrixSize0 : 2; 
    uint32_t idxMatrixSize1 : 2; 
    uint32_t idxMatrixSize2 : 2; 
    uint32_t enableFinalLut : 1; 
    uint32_t : 8;
} pxp_dither_config_t;
 
enum
{
    kPXP_PorterDuffFactorOne = 0U, 
    kPXP_PorterDuffFactorZero,     
    kPXP_PorterDuffFactorStraight, 
    kPXP_PorterDuffFactorInversed, 
};
 
enum
{
    kPXP_PorterDuffGlobalAlpha = 0U, 
    kPXP_PorterDuffLocalAlpha,       
    kPXP_PorterDuffScaledAlpha,      
};
 
enum
{
    kPXP_PorterDuffAlphaStraight = 0U, 
    kPXP_PorterDuffAlphaInversed       
};
 
enum
{
    kPXP_PorterDuffColorStraight  = 0, 
    kPXP_PorterDuffColorInversed  = 1, 
    kPXP_PorterDuffColorNoAlpha   = 0, 
    kPXP_PorterDuffColorWithAlpha = 1, 
};
 
typedef struct
{
    uint32_t enable : 1;             
    uint32_t srcFactorMode : 2;      
    uint32_t dstGlobalAlphaMode : 2; 
    uint32_t dstAlphaMode : 1; 
    uint32_t dstColorMode : 1; 
    uint32_t : 1;
    uint32_t dstFactorMode : 2; 
    uint32_t srcGlobalAlphaMode : 2; 
    uint32_t srcAlphaMode : 1;       
    uint32_t srcColorMode : 1;       
    uint32_t : 2;
    uint32_t dstGlobalAlpha : 8; 
    uint32_t srcGlobalAlpha : 8; 
} pxp_porter_duff_config_t;
 
typedef enum _pxp_porter_duff_blend_mode
{
    kPXP_PorterDuffSrc = 0, 
    kPXP_PorterDuffAtop,    
    kPXP_PorterDuffOver,    
    kPXP_PorterDuffIn,      
    kPXP_PorterDuffOut,     
    kPXP_PorterDuffDst,     
    kPXP_PorterDuffDstAtop, 
    kPXP_PorterDuffDstOver, 
    kPXP_PorterDuffDstIn,   
    kPXP_PorterDuffDstOut,  
    kPXP_PorterDuffXor,     
    kPXP_PorterDuffClear,   
    kPXP_PorterDuffMax,
} pxp_porter_duff_blend_mode_t;
 
typedef struct _pxp_pic_copy_config
{
    uint32_t srcPicBaseAddr;           
    uint16_t srcPitchBytes;            
    uint16_t srcOffsetX;               
    uint16_t srcOffsetY;               
    uint32_t destPicBaseAddr;          
    uint16_t destPitchBytes;           
    uint16_t destOffsetX;              
    uint16_t destOffsetY;              
    uint16_t width;                    
    uint16_t height;                   
    pxp_as_pixel_format_t pixelFormat; 
} pxp_pic_copy_config_t;
 
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
 
typedef enum _pxp_process_engine_name
{
    kPXP_PsAsOutEngine         = PXP_CTRL_ENABLE_PS_AS_OUT_MASK,
    kPXP_DitherEngine          = PXP_CTRL_ENABLE_DITHER_MASK,
    kPXP_WfeaEngine            = PXP_CTRL_ENABLE_WFE_A_MASK,
    kPXP_WfebEngine            = PXP_CTRL_ENABLE_WFE_B_MASK,
    kPXP_InputFetchStoreEngine = PXP_CTRL_ENABLE_INPUT_FETCH_STORE_MASK,
    kPXP_Alpha1Engine          = PXP_CTRL_ENABLE_ALPHA_B_MASK,
    kPXP_Csc2Engine            = PXP_CTRL_ENABLE_CSC2_MASK,
    kPXP_LutEngine             = PXP_CTRL_ENABLE_LUT_MASK,
    kPXP_Rotate0Engine         = PXP_CTRL_ENABLE_ROTATE0_MASK,
    kPXP_Rotate1Engine         = PXP_CTRL_ENABLE_ROTATE1_MASK,
} pxp_process_engine_name_t;
 
/* Fetch engine configuration. */
typedef enum _pxp_fetch_engine_name
{
    kPXP_FetchInput,
    kPXP_FetchDither,
} pxp_fetch_engine_name_t;
 
typedef enum _pxp_fetch_interface_mode
{
    kPXP_FetchModeNormal    = 0U,
    kPXP_FetchModeHandshake = 0x1U,
    kPXP_FetchModeBypass    = 0x2U,
} pxp_fetch_interface_mode_t;
 
typedef enum _pxp_scanline_burst
{
    kPXP_Scanline8bytes,
    kPXP_Scanline16bytes,
    kPXP_Scanline32bytes,
    kPXP_Scanline64bytes,
} pxp_scanline_burst_t;
 
typedef struct _pxp_block_format_config
{
    bool
        enableblock;  
    bool blockSize16; 
    pxp_scanline_burst_t burstLength; 
} pxp_block_config_t;
 
typedef enum _pxp_activeBits
{
    kPXP_Active8Bits  = 0x0,
    kPXP_Active16Bits = 0x1,
    kPXP_Active32Bits = 0x2,
    kPXP_Active64Bits = 0x3,
} pxp_active_bits_t;
 
typedef enum _pxp_fetch_output_word_order
{
    kPXP_FetchOutputChannel1channel0 = 0x0, 
    kPXP_FetchOutputChannel0channel1 = 0x1, 
} pxp_fetch_output_word_order_t;
 
typedef struct _pxp_fetch_shift_component
{
    uint8_t offset;
    uint8_t width;
} pxp_fetch_shift_component_t;
 
typedef struct _pxp_fetch_shift_config
{
    bool shiftBypass; /* Bypass the shift */
    pxp_fetch_shift_component_t component0;
    pxp_fetch_shift_component_t component1;
    pxp_fetch_shift_component_t component2;
    pxp_fetch_shift_component_t component3;
} pxp_fetch_shift_config_t;
 
typedef enum _pxp_fetch_pixel_format
{
    kPXP_FetchFormatRGB565     = 0x0,
    kPXP_FetchFormatRGB555     = 0x1,
    kPXP_FetchFormatARGB1555   = 0x2,
    kPXP_FetchFormatRGB444     = 0x3,
    kPXP_FetchFormatARGB4444   = 0x4,
    kPXP_FetchFormatYUYVorYVYU = 0x5,
    kPXP_FetchFormatUYVYorVYUY = 0x6,
    kPXP_FetchFormatYUV422_2P  = 0x7,
} pxp_fetch_pixel_format_t;
 
typedef struct _pxp_fetch_engine_config
{
    bool channelEnable; 
    /* Address configuration */
    uint32_t inputBaseAddr0; 
    uint32_t inputBaseAddr1; 
    /* Size configuration */
    uint16_t totalHeight; 
    uint16_t totalWidth;  
    uint16_t pitchBytes;  
    uint16_t
        ulcX; 
    uint16_t
        ulcY; 
    uint16_t
        lrcX; 
    uint16_t
        lrcY; 
    /* Interface configuration */
    pxp_fetch_interface_mode_t interface; 
    /* Pixel configuration */
    pxp_active_bits_t activeBits;         
    pxp_fetch_pixel_format_t pixelFormat; 
    bool expandEnable; 
    /* Fetch format configuration */
    pxp_flip_mode_t flipMode;         
    pxp_rotate_degree_t rotateDegree; 
    pxp_block_config_t
        fetchFormat; 
    /* Output configuration. */
    pxp_fetch_shift_config_t shiftConfig;    
    pxp_fetch_output_word_order_t wordOrder; 
} pxp_fetch_engine_config_t;
 
/* Store engine configuration. */
 
typedef enum _pxp_store_engine_name
{
    kPXP_StoreInput,
    kPXP_StoreDither,
} pxp_store_engine_name_t;
 
typedef enum _pxp_store_interface_mode
{
    kPXP_StoreModeBypass    = 0x20U,
    kPXP_StoreModeNormal    = 0x40U,
    kPXP_StoreModeHandshake = 0x43U,
    kPXP_StoreModeDual      = 0x60U, 
} pxp_store_interface_mode_t;
 
typedef enum _pxp_store_yuv_mode
{
    kPXP_StoreYUVDisable = 0U, 
    kPXP_StoreYUVPlane1 =
        0x1U, 
    kPXP_StoreYUVPlane2 =
        0x2U, 
} pxp_store_yuv_mode_t;
 
typedef struct _pxp_store_shift_config
{
    /* Data/Flag shift */
    bool shiftBypass;         
    uint64_t *pDataShiftMask; 
    uint8_t *pDataShiftWidth; 
    uint8_t *pFlagShiftMask;  
    uint8_t *pFlagShiftWidth; 
} pxp_store_shift_config_t;
 
typedef struct _pxp_store_engine_config
{
    bool channelEnable; 
    /* Address configuration */
    uint32_t outputBaseAddr0; 
    uint32_t outputBaseAddr1; 
    /* Size configuration */
    uint16_t totalHeight; 
    uint16_t totalWidth;  
    uint16_t pitchBytes;  
    /* Interface configuration */
    pxp_store_interface_mode_t interface; 
    /* pxp_store_handshake_array_t arraySize; !< If interfase mode is handshake, need to configure the array size. When
                                              block is disabled, the scanline can only be 1. TODO no need now. */
    /* Pixel configuration */
    pxp_active_bits_t activeBits; 
    pxp_store_yuv_mode_t yuvMode; 
    /* Fixed data configuration, only apply for channel 0. */
    bool useFixedData; 
    uint32_t fixedData; 
    /* Data packing */
    bool packInSelect; 
    /* Data store format */
    pxp_block_config_t storeFormat;       
    pxp_store_shift_config_t shiftConfig; 
} pxp_store_engine_config_t;
 
/* Pre-dither CFA engine configuration */
 
typedef enum _pxp_cfa_input_format
{
    kPXP_CfaRGB888,
    kPXP_CfaRGB444,
} pxp_cfa_input_format_t;
 
typedef struct _pxp_cfa_config
{
    bool bypass;                          
    pxp_cfa_input_format_t pixelInFormat; 
    uint8_t arrayWidth;                   
    uint8_t arrayHeight;                  
    uint16_t totalHeight; 
    uint16_t totalWidth;  
    uint32_t *cfaValue; 
} pxp_cfa_config_t;
 
/* Histogram configuration and status */
 
typedef enum _pxp_histogram_mask_condition
{
    kPXP_HistogramMaskEqual    = 0x0U, 
    kPXP_HistogramMaskNotequal = 0x1U, 
    kPXP_HistogramMaskIn  = 0x2U, 
    kPXP_HistogramMaskOut = 0x3U, 
} pxp_histogram_mask_condition_t;
 
typedef struct _pxp_histogram_config
{
    bool enable;            
    uint8_t *pParamValue;   
    uint8_t lutValueOffset; 
    uint8_t lutValueWidth;  
    /* Mask configuration */
    bool enableMask;    
    uint8_t maskValue0; 
    uint8_t maskValue1; 
    uint8_t maskOffset; 
    uint8_t maskWidth;  
    pxp_histogram_mask_condition_t condition; 
    /* Size configuration */
    uint16_t totalHeight; 
    uint16_t totalWidth; 
} pxp_histogram_config_t;
 
typedef struct _pxp_histogram_mask_result
{
    uint32_t pixelCount; 
    uint32_t minX;       
    uint32_t minY;       
    uint32_t maxX;       
    uint32_t maxY;       
    uint64_t lutlist; 
} pxp_histogram_mask_result_t;
 
enum _pxp_histgram_flags
{
    kPXP_Histogram2levelMatch  = 1 << 0U, /* Bitmap pixels are fully contained within the HIST2 histogram. */
    kPXP_Histogram4levelMatch  = 1 << 1U, /* Bitmap pixels are fully contained within the HIST4 histogram. */
    kPXP_Histogram8levelMatch  = 1 << 2U, /* Bitmap pixels are fully contained within the HIST8 histogram. */
    kPXP_Histogram16levelMatch = 1 << 3U, /* Bitmap pixels are fully contained within the HIST16 histogram. */
    kPXP_Histogram32levelMatch = 1 << 4U, /* Bitmap pixels are fully contained within the HIST32 histogram. */
};
 
typedef struct _pxp_wfea_engine_config
{
    uint32_t y4Addr;       
    uint32_t y4cAddr;      
    uint32_t wbAddr;       
    uint16_t updateWidth;  
    uint16_t updateHeight; 
    uint16_t updatePitch;  
    uint16_t ulcX;         
    uint16_t ulcY;         
    uint16_t resX;         
    uint8_t lutNum;        
    bool fullUpdateEnable; 
    bool alphaEnable; 
    bool detectionOnly; 
} pxp_wfea_engine_config_t;
 
#endif /* FSL_FEATURE_PXP_V3 */
 
/*******************************************************************************
 * API
 ******************************************************************************/
 
#if defined(__cplusplus)
extern "C" {
#endif
 
void PXP_Init(PXP_Type *base);
 
void PXP_Deinit(PXP_Type *base);
 
void PXP_Reset(PXP_Type *base);
 
void PXP_ResetControl(PXP_Type *base);
/* @} */
 
static inline void PXP_Start(PXP_Type *base)
{
    base->CTRL_SET = PXP_CTRL_ENABLE_MASK;
}
 
static inline void PXP_EnableLcdHandShake(PXP_Type *base, bool enable)
{
#if defined(PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
    if (enable)
    {
        base->CTRL_SET = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK;
    }
    else
    {
        base->CTRL_CLR = PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK;
    }
#else
    if (enable)
    {
        base->CTRL_SET = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK;
    }
    else
    {
        base->CTRL_CLR = PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK;
    }
#endif
}
 
#if (defined(FSL_FEATURE_PXP_HAS_EN_REPEAT) && FSL_FEATURE_PXP_HAS_EN_REPEAT)
static inline void PXP_EnableContinousRun(PXP_Type *base, bool enable)
{
    if (enable)
    {
        base->CTRL_SET = PXP_CTRL_EN_REPEAT_MASK;
    }
    else
    {
        base->CTRL_CLR = PXP_CTRL_EN_REPEAT_MASK;
    }
}
#endif /* FSL_FEATURE_PXP_HAS_EN_REPEAT */
 
static inline void PXP_SetProcessBlockSize(PXP_Type *base, pxp_block_size_t size)
{
    base->CTRL = (base->CTRL & ~PXP_CTRL_BLOCK_SIZE_MASK) | PXP_CTRL_BLOCK_SIZE(size);
}
 
#if PXP_USE_PATH
void PXP_SetPath(PXP_Type *base, pxp_path_t path);
#endif /* PXP_USE_PATH */
 
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
static inline void PXP_EnableProcessEngine(PXP_Type *base, uint32_t mask, bool enable)
{
    mask &= 0xF3F0000UL;
 
    if (enable)
    {
        base->CTRL_SET = mask;
    }
    else
    {
        base->CTRL_CLR = mask;
    }
}
#endif /* FSL_FEATURE_PXP_V3 */
 
/* @} */
 
static inline uint32_t PXP_GetStatusFlags(PXP_Type *base)
{
#if defined(PXP_STAT_AXI_READ_ERROR_1_MASK)
    uint32_t status = base->STAT & (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK |
                                    PXP_STAT_AXI_WRITE_ERROR_0_MASK | PXP_STAT_AXI_READ_ERROR_1_MASK |
                                    PXP_STAT_AXI_WRITE_ERROR_1_MASK);
#else
    uint32_t status = base->STAT & (PXP_STAT_NEXT_IRQ_MASK | PXP_STAT_IRQ0_MASK | PXP_STAT_AXI_READ_ERROR_0_MASK |
                                    PXP_STAT_AXI_WRITE_ERROR_0_MASK);
#endif
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
    status |= (base->IRQ >> 16U | base->IRQ << 16U);
#endif /* FSL_FEATURE_PXP_V3 */
    return status;
}
 
static inline void PXP_ClearStatusFlags(PXP_Type *base, uint32_t statusMask)
{
    base->STAT_CLR = statusMask;
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
    statusMask &= 0xFFFF8000UL;
    base->IRQ_CLR = (statusMask >> 16U | statusMask << 16U);
#endif /* FSL_FEATURE_PXP_V3 */
}
 
static inline uint8_t PXP_GetAxiErrorId(PXP_Type *base, uint8_t axiIndex)
{
#if defined(PXP_STAT_AXI_ERROR_ID_1_MASK)
    if (0U == axiIndex)
    {
        return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_0_MASK) >> PXP_STAT_AXI_ERROR_ID_0_SHIFT);
    }
    else
    {
        return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_1_MASK) >> PXP_STAT_AXI_ERROR_ID_1_SHIFT);
    }
#else
    return (uint8_t)((base->STAT & PXP_STAT_AXI_ERROR_ID_MASK) >> PXP_STAT_AXI_ERROR_ID_SHIFT);
#endif
}
 
/* @} */
 
static inline void PXP_EnableInterrupts(PXP_Type *base, uint32_t mask)
{
    base->CTRL_SET = (mask & 0xEUL);
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
    mask &= 0xFFFF8000UL;
    base->IRQ_MASK_SET = (mask >> 16U | mask << 16U);
#endif /* FSL_FEATURE_PXP_V3 */
}
 
static inline void PXP_DisableInterrupts(PXP_Type *base, uint32_t mask)
{
    base->CTRL_CLR = (mask & 0xEUL);
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
    mask &= 0xFFFF8000UL;
    base->IRQ_MASK_CLR = (mask >> 16U | mask << 16U);
#endif /* FSL_FEATURE_PXP_V3 */
}
 
/* @} */
 
void PXP_SetAlphaSurfaceBufferConfig(PXP_Type *base, const pxp_as_buffer_config_t *config);
 
void PXP_SetAlphaSurfaceBlendConfig(PXP_Type *base, const pxp_as_blend_config_t *config);
 
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
void PXP_SetAlphaSurfaceBlendSecondaryConfig(PXP_Type *base, const pxp_as_blend_secondary_config_t *config);
 
void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh);
 
static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t num, bool enable)
{
    switch (num)
    {
        case 0:
            base->AS_CTRL =
                (base->AS_CTRL & ~PXP_AS_CTRL_ENABLE_COLORKEY_MASK) | PXP_AS_CTRL_ENABLE_COLORKEY((uint32_t)enable);
            break;
 
        case 1:
            base->ALPHA_B_CTRL_1 = (base->ALPHA_B_CTRL_1 & ~PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE_MASK) |
                                   PXP_ALPHA_B_CTRL_1_OL_CLRKEY_ENABLE((uint32_t)enable);
            break;
 
        default:
            /* Only 2 alpha process engine instances are supported. */
            assert(false);
            break;
    }
}
#else
void PXP_SetAlphaSurfaceOverlayColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh);
 
static inline void PXP_EnableAlphaSurfaceOverlayColorKey(PXP_Type *base, bool enable)
{
    if (enable)
    {
        base->AS_CTRL |= PXP_AS_CTRL_ENABLE_COLORKEY_MASK;
    }
    else
    {
        base->AS_CTRL &= ~PXP_AS_CTRL_ENABLE_COLORKEY_MASK;
    }
}
#endif /* FSL_FEATURE_PXP_V3 */
 
void PXP_SetAlphaSurfacePosition(
    PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY);
/* @} */
 
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint8_t num, uint32_t backGroundColor)
{
    switch (num)
    {
        case 0:
            base->PS_BACKGROUND_0 = backGroundColor;
            break;
 
        case 1:
            base->PS_BACKGROUND_1 = backGroundColor;
            break;
 
        default:
            /* Only 2 alpha process engine instances are supported. */
            assert(false);
            break;
    }
}
#else
static inline void PXP_SetProcessSurfaceBackGroundColor(PXP_Type *base, uint32_t backGroundColor)
{
#if defined(PXP_PS_BACKGROUND_0_COLOR_MASK)
    base->PS_BACKGROUND_0 = backGroundColor;
#else
    base->PS_BACKGROUND = backGroundColor;
#endif
}
#endif /* FSL_FEATURE_PXP_V3 */
 
void PXP_SetProcessSurfaceBufferConfig(PXP_Type *base, const pxp_ps_buffer_config_t *config);
 
void PXP_SetProcessSurfaceScaler(
    PXP_Type *base, uint16_t inputWidth, uint16_t inputHeight, uint16_t outputWidth, uint16_t outputHeight);
 
void PXP_SetProcessSurfacePosition(
    PXP_Type *base, uint16_t upperLeftX, uint16_t upperLeftY, uint16_t lowerRightX, uint16_t lowerRightY);
 
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint8_t num, uint32_t colorKeyLow, uint32_t colorKeyHigh);
#else
void PXP_SetProcessSurfaceColorKey(PXP_Type *base, uint32_t colorKeyLow, uint32_t colorKeyHigh);
#endif /* FSL_FEATURE_PXP_V3 */
 
static inline void PXP_SetProcessSurfaceYUVFormat(PXP_Type *base, pxp_ps_yuv_format_t format)
{
    if (kPXP_PsYUVFormatYUV == format)
    {
        base->CSC1_COEF0 &= ~PXP_CSC1_COEF0_YCBCR_MODE_MASK;
    }
    else
    {
        base->CSC1_COEF0 |= PXP_CSC1_COEF0_YCBCR_MODE_MASK;
    }
}
/* @} */
 
void PXP_SetOutputBufferConfig(PXP_Type *base, const pxp_output_buffer_config_t *config);
 
static inline void PXP_SetOverwrittenAlphaValue(PXP_Type *base, uint8_t alpha)
{
    base->OUT_CTRL = (base->OUT_CTRL & ~PXP_OUT_CTRL_ALPHA_MASK) | PXP_OUT_CTRL_ALPHA(alpha);
}
 
static inline void PXP_EnableOverWrittenAlpha(PXP_Type *base, bool enable)
{
    if (enable)
    {
        base->OUT_CTRL_SET = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK;
    }
    else
    {
        base->OUT_CTRL_CLR = PXP_OUT_CTRL_ALPHA_OUTPUT_MASK;
    }
}
 
static inline void PXP_SetRotateConfig(PXP_Type *base,
                                       pxp_rotate_position_t position,
                                       pxp_rotate_degree_t degree,
                                       pxp_flip_mode_t flipMode)
{
#if PXP_SHARE_ROTATE
    base->CTRL =
        (base->CTRL & ~(PXP_CTRL_ROTATE_MASK | PXP_CTRL_ROT_POS_MASK | PXP_CTRL_VFLIP_MASK | PXP_CTRL_HFLIP_MASK)) |
        PXP_CTRL_ROTATE(degree) | PXP_CTRL_ROT_POS(position) | ((uint32_t)flipMode << PXP_CTRL_HFLIP_SHIFT);
#else
    uint32_t ctrl = base->CTRL;
 
    if (kPXP_RotateOutputBuffer == position)
    {
        ctrl &= ~(PXP_CTRL_HFLIP0_MASK | PXP_CTRL_VFLIP0_MASK | PXP_CTRL_ROTATE0_MASK);
        ctrl |= (PXP_CTRL_ROTATE0(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP0_SHIFT));
    }
    else
    {
        ctrl &= ~(PXP_CTRL_HFLIP1_MASK | PXP_CTRL_VFLIP1_MASK | PXP_CTRL_ROTATE1_MASK);
        ctrl |= (PXP_CTRL_ROTATE1(degree) | ((uint32_t)flipMode << PXP_CTRL_HFLIP1_SHIFT));
    }
 
    base->CTRL = ctrl;
#endif
}
 
void PXP_BuildRect(PXP_Type *base,
                   pxp_output_pixel_format_t outFormat,
                   uint32_t value,
                   uint16_t width,
                   uint16_t height,
                   uint16_t pitch,
                   uint32_t outAddr);
/* @} */
 
void PXP_SetNextCommand(PXP_Type *base, void *commandAddr);
 
static inline bool PXP_IsNextCommandPending(PXP_Type *base)
{
    return (bool)(base->NEXT & PXP_NEXT_ENABLED_MASK);
}
 
static inline void PXP_CancelNextCommand(PXP_Type *base)
{
    /* Write PXP_NEXT_ENABLED_MASK to the register NEXT_CLR to canel the command. */
    uint32_t regAddr = (uint32_t) & (base->NEXT);
    regAddr += 8U;
    *(uint32_t *)regAddr = PXP_NEXT_ENABLED_MASK;
}
 
/* @} */
 
#if !(defined(FSL_FEATURE_PXP_HAS_NO_CSC2) && FSL_FEATURE_PXP_HAS_NO_CSC2)
void PXP_SetCsc2Config(PXP_Type *base, const pxp_csc2_config_t *config);
 
static inline void PXP_EnableCsc2(PXP_Type *base, bool enable)
{
    if (enable)
    {
        base->CSC2_CTRL &= ~PXP_CSC2_CTRL_BYPASS_MASK;
    }
    else
    {
        base->CSC2_CTRL |= PXP_CSC2_CTRL_BYPASS_MASK;
    }
}
#endif /* FSL_FEATURE_PXP_HAS_NO_CSC2 */
 
void PXP_SetCsc1Mode(PXP_Type *base, pxp_csc1_mode_t mode);
 
static inline void PXP_EnableCsc1(PXP_Type *base, bool enable)
{
    if (enable)
    {
        base->CSC1_COEF0 &= ~PXP_CSC1_COEF0_BYPASS_MASK;
    }
    else
    {
        base->CSC1_COEF0 |= PXP_CSC1_COEF0_BYPASS_MASK;
    }
}
/* @} */
 
#if !(defined(FSL_FEATURE_PXP_HAS_NO_LUT) && FSL_FEATURE_PXP_HAS_NO_LUT)
void PXP_SetLutConfig(PXP_Type *base, const pxp_lut_config_t *config);
 
status_t PXP_LoadLutTable(
    PXP_Type *base, pxp_lut_lookup_mode_t lookupMode, uint32_t bytesNum, uint32_t memAddr, uint16_t lutStartAddr);
 
static inline void PXP_EnableLut(PXP_Type *base, bool enable)
{
    if (enable)
    {
        base->LUT_CTRL &= ~PXP_LUT_CTRL_BYPASS_MASK;
    }
    else
    {
        base->LUT_CTRL |= PXP_LUT_CTRL_BYPASS_MASK;
    }
}
 
static inline void PXP_Select8kLutBank(PXP_Type *base, pxp_lut_8k_bank_t bank)
{
    base->LUT_CTRL = (base->LUT_CTRL & ~PXP_LUT_CTRL_SEL_8KB_MASK) | PXP_LUT_CTRL_SEL_8KB(bank);
}
/* @} */
#endif /* FSL_FEATURE_PXP_HAS_NO_LUT */
 
#if (defined(FSL_FEATURE_PXP_HAS_DITHER) && FSL_FEATURE_PXP_HAS_DITHER)
void PXP_SetInternalRamData(PXP_Type *base, pxp_ram_t ram, uint32_t bytesNum, uint8_t *data, uint16_t memStartAddr);
 
void PXP_SetDitherFinalLutData(PXP_Type *base, const pxp_dither_final_lut_data_t *data);
 
static inline void PXP_SetDitherConfig(PXP_Type *base, const pxp_dither_config_t *config)
{
    typedef union
    {
        pxp_dither_config_t _dither_config;
        uint32_t _u32;
    } pxp_reg_convert_t;
 
    pxp_reg_convert_t pid;
 
    pid._dither_config = *config;
    base->DITHER_CTRL  = pid._u32 & 0x00FFFFFFU;
}
 
void PXP_EnableDither(PXP_Type *base, bool enable);
 
/* @} */
 
#endif /* FSL_FEATURE_PXP_HAS_DITHER */
 
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
void PXP_SetPorterDuffConfig(PXP_Type *base, uint8_t num, const pxp_porter_duff_config_t *config);
#endif /* FSL_FEATURE_PXP_V3 */
 
#if !(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL)
void PXP_SetPorterDuffConfig(PXP_Type *base, const pxp_porter_duff_config_t *config);
#endif /* FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL */
 
#if (!(defined(FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL) && FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL)) || \
    (defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3)
status_t PXP_GetPorterDuffConfig(pxp_porter_duff_blend_mode_t mode, pxp_porter_duff_config_t *config);
 
/* @} */
#endif /* FSL_FEATURE_PXP_V3 || FSL_FEATURE_PXP_HAS_NO_PORTER_DUFF_CTRL  */
 
/* @} */
 
status_t PXP_StartPictureCopy(PXP_Type *base, const pxp_pic_copy_config_t *config);
 
status_t PXP_StartMemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32_t size);
 
status_t PXP_MemCopy(PXP_Type *base, uint32_t srcAddr, uint32_t destAddr, uint32_t size);
 
/* @} */
 
#if defined(FSL_FEATURE_PXP_V3) && FSL_FEATURE_PXP_V3
 
status_t PXP_SetFetchEngineConfig(PXP_Type *base,
                                  pxp_fetch_engine_name_t name,
                                  uint8_t channel,
                                  const pxp_fetch_engine_config_t *config);
 
static inline void PXP_EnableFetchEngine(PXP_Type *base, pxp_fetch_engine_name_t name, uint8_t channel, bool enable)
{
    if (enable)
    {
        if (name == kPXP_FetchInput)
        {
            switch (channel)
            {
                case 0:
                    base->INPUT_FETCH_CTRL_CH0_SET = PXP_INPUT_FETCH_CTRL_CH0_CH_EN_MASK;
                    break;
 
                case 1:
                    base->INPUT_FETCH_CTRL_CH1_SET = PXP_INPUT_FETCH_CTRL_CH1_CH_EN_MASK;
                    break;
 
                default:
                    /* Only 2 channels are supported per fetch engine. */
                    assert(false);
                    break;
            }
        }
        else
        {
            switch (channel)
            {
                case 0:
                    base->DITHER_FETCH_CTRL_CH0_SET = PXP_DITHER_FETCH_CTRL_CH0_CH_EN_MASK;
                    break;
 
                case 1:
                    base->DITHER_FETCH_CTRL_CH1_SET = PXP_DITHER_FETCH_CTRL_CH1_CH_EN_MASK;
                    break;
 
                default:
                    /* Only 2 channels are supported per fetch engine. */
                    assert(false);
                    break;
            }
        }
    }
    else
    {
        if (name == kPXP_FetchInput)
        {
            switch (channel)
            {
                case 0:
                    base->INPUT_FETCH_CTRL_CH0_CLR = PXP_INPUT_FETCH_CTRL_CH0_CH_EN_MASK;
                    break;
 
                case 1:
                    base->INPUT_FETCH_CTRL_CH1_CLR = PXP_INPUT_FETCH_CTRL_CH1_CH_EN_MASK;
                    break;
 
                default:
                    /* Only 2 channels are supported per fetch engine. */
                    assert(false);
                    break;
            }
        }
        else
        {
            switch (channel)
            {
                case 0:
                    base->DITHER_FETCH_CTRL_CH0_CLR = PXP_DITHER_FETCH_CTRL_CH0_CH_EN_MASK;
                    break;
 
                case 1:
                    base->DITHER_FETCH_CTRL_CH1_CLR = PXP_DITHER_FETCH_CTRL_CH1_CH_EN_MASK;
                    break;
 
                default:
                    /* Only 2 channels are supported per fetch engine. */
                    assert(false);
                    break;
            }
        }
    }
}
/* @} */
 
status_t PXP_SetStoreEngineConfig(PXP_Type *base,
                                  pxp_store_engine_name_t name,
                                  uint8_t channel,
                                  const pxp_store_engine_config_t *config);
 
static inline void PXP_EnableStoreEngine(PXP_Type *base, pxp_store_engine_name_t name, uint8_t channel, bool enable)
{
    if (enable)
    {
        if (name == kPXP_StoreInput)
        {
            switch (channel)
            {
                case 0:
                    base->INPUT_STORE_CTRL_CH0_SET = PXP_INPUT_STORE_CTRL_CH0_CH_EN_MASK;
                    break;
 
                case 1:
                    base->INPUT_STORE_CTRL_CH1_SET = PXP_INPUT_STORE_CTRL_CH1_CH_EN_MASK;
                    break;
 
                default:
                    /* Only 2 channels are supported per fetch engine. */
                    assert(false);
                    break;
            }
        }
        else
        {
            switch (channel)
            {
                case 0:
                    base->DITHER_STORE_CTRL_CH0_SET = PXP_DITHER_STORE_CTRL_CH0_CH_EN_MASK;
                    break;
 
                case 1:
                    base->DITHER_STORE_CTRL_CH1_SET = PXP_DITHER_STORE_CTRL_CH1_CH_EN_MASK;
                    break;
 
                default:
                    /* Only 2 channels are supported per fetch engine. */
                    assert(false);
                    break;
            }
        }
    }
    else
    {
        if (name == kPXP_StoreInput)
        {
            switch (channel)
            {
                case 0:
                    base->INPUT_STORE_CTRL_CH0_CLR = PXP_INPUT_STORE_CTRL_CH0_CH_EN_MASK;
                    break;
 
                case 1:
                    base->INPUT_STORE_CTRL_CH1_CLR = PXP_INPUT_STORE_CTRL_CH1_CH_EN_MASK;
                    break;
 
                default:
                    /* Only 2 channels are supported per fetch engine. */
                    assert(false);
                    break;
            }
        }
        else
        {
            switch (channel)
            {
                case 0:
                    base->DITHER_STORE_CTRL_CH0_CLR = PXP_DITHER_STORE_CTRL_CH0_CH_EN_MASK;
                    break;
 
                case 1:
                    base->DITHER_STORE_CTRL_CH1_CLR = PXP_DITHER_STORE_CTRL_CH1_CH_EN_MASK;
                    break;
 
                default:
                    /* Only 2 channels are supported per fetch engine. */
                    assert(false);
                    break;
            }
        }
    }
}
 
static inline void PXP_CombineStoreEngineChannel(PXP_Type *base, pxp_store_engine_name_t name, bool combine)
{
    if (name == kPXP_StoreInput)
    {
        if (combine)
        {
            base->INPUT_STORE_CTRL_CH0_SET = PXP_INPUT_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK;
        }
        else
        {
            base->INPUT_STORE_CTRL_CH0_CLR = PXP_INPUT_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK;
        }
    }
    else
    {
        if (combine)
        {
            base->DITHER_STORE_CTRL_CH0_SET = PXP_DITHER_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK;
        }
        else
        {
            base->DITHER_STORE_CTRL_CH0_CLR = PXP_DITHER_STORE_CTRL_CH0_SET_COMBINE_2CHANNEL_MASK;
        }
    }
}
/* @} */
 
status_t PXP_SetCfaConfig(PXP_Type *base, const pxp_cfa_config_t *config);
 
static inline void PXP_EnableCfa(PXP_Type *base, bool enable)
{
    if (enable)
    {
        base->CFA_CTRL_CLR = PXP_CFA_CTRL_CFA_BYPASS_MASK;
    }
    else
    {
        base->CFA_CTRL_SET = PXP_CFA_CTRL_CFA_BYPASS_MASK;
    }
}
/* @} */
 
status_t PXP_SetHistogramConfig(PXP_Type *base, uint8_t num, const pxp_histogram_config_t *config);
 
static inline void PXP_EnableHistogram(PXP_Type *base, uint8_t num, bool enable)
{
    switch (num)
    {
        case 0:
            base->HIST_A_CTRL =
                (base->HIST_A_CTRL & ~PXP_HIST_A_CTRL_ENABLE_MASK) | PXP_HIST_A_CTRL_ENABLE((uint32_t)enable);
            break;
 
        case 1:
            base->HIST_B_CTRL =
                (base->HIST_B_CTRL & ~PXP_HIST_B_CTRL_ENABLE_MASK) | PXP_HIST_B_CTRL_ENABLE((uint32_t)enable);
            break;
 
        default:
            /* Only 2 instances are supported per fetch engine. */
            assert(false);
            break;
    }
}
 
void PXP_GetHistogramMaskResult(PXP_Type *base, uint8_t num, pxp_histogram_mask_result_t *result);
 
static inline uint8_t PXP_GetHistogramMatchResult(PXP_Type *base, uint8_t num)
{
    uint8_t result = 0U;
    switch (num)
    {
        case 0:
            result = (uint8_t)((base->HIST_A_CTRL & PXP_HIST_A_CTRL_STATUS_MASK) >> PXP_HIST_A_CTRL_STATUS_SHIFT);
            break;
 
        case 1:
            result = (uint8_t)((base->HIST_B_CTRL & PXP_HIST_B_CTRL_STATUS_MASK) >> PXP_HIST_B_CTRL_STATUS_SHIFT);
            break;
 
        default:
            /* Only 2 histogram instances are supported. */
            assert(false);
            break;
    }
 
    return result;
}
 
static inline void PXP_ClearHistogramResult(PXP_Type *base, uint8_t num)
{
    switch (num)
    {
        case 0:
            base->HIST_A_CTRL |= PXP_HIST_A_CTRL_CLEAR_MASK;
            break;
 
        case 1:
            base->HIST_B_CTRL |= PXP_HIST_B_CTRL_CLEAR_MASK;
            break;
 
        default:
            /* Only 2 histogram instances are supported. */
            assert(false);
            break;
    }
}
 
static inline void PXP_SetHistogramSize(PXP_Type *base, uint8_t num, uint16_t width, uint16_t height)
{
    switch (num)
    {
        case 0:
            base->HIST_A_BUF_SIZE = ((uint32_t)height << 16U) | (uint32_t)width;
            break;
 
        case 1:
            base->HIST_B_BUF_SIZE = ((uint32_t)height << 16U) | (uint32_t)width;
            break;
 
        default:
            /* Only 2 histogram instances are supported. */
            assert(false);
            break;
    }
}
/* @} */
 
void PXP_WfeaInit(PXP_Type *base, bool ditherHandshake);
 
static inline void PXP_WfeaEnableDitherHandshake(PXP_Type *base, bool enable)
{
    if (enable)
    {
        base->WFA_FETCH_CTRL |= PXP_WFA_FETCH_CTRL_BF1_HSK_MODE_MASK;
    }
    else
    {
        base->WFA_FETCH_CTRL &= ~PXP_WFA_FETCH_CTRL_BF1_HSK_MODE_MASK;
    }
}
 
void PXP_SetWfeaConfig(PXP_Type *base, const pxp_wfea_engine_config_t *config);
 
static inline void PXP_SetLutUsage(PXP_Type *base, uint64_t lutStatus)
{
    base->WFE_A_STG1_8X1_OUT0_0 |= (uint32_t)lutStatus;
    base->WFE_A_STG1_8X1_OUT0_1 |= (uint32_t)(lutStatus >> 32U);
}
 
static inline void PXP_ClearLutUsage(PXP_Type *base, uint64_t lutStatus)
{
    base->WFE_A_STG1_8X1_OUT0_0 &= ~(uint32_t)lutStatus;
    base->WFE_A_STG1_8X1_OUT0_1 &= ~(uint32_t)(lutStatus >> 32U);
}
 
static inline uint64_t PXP_GetLutUsage(PXP_Type *base)
{
    return ((uint64_t)base->WFE_A_STG1_8X1_OUT0_0 | (uint64_t)base->WFE_A_STG1_8X1_OUT0_1 << 32U);
}
 
/* @} */
 
#endif /* FSL_FEATURE_PXP_V3 */
 
#if defined(__cplusplus)
}
#endif
 
#endif /* _FSL_PXP_H_ */