RTEMS 6.1-rc2
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fsl_pgmc.h
1/*
2 * Copyright 2019-2021, NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9#ifndef _FSL_PGMC_H_
10#define _FSL_PGMC_H_
11
12#include "fsl_common.h"
13
19/*******************************************************************************
20 * Definitions
21 ******************************************************************************/
22
26#define FSL_PGMC_RIVER_VERSION (MAKE_VERSION(2, 1, 1))
32enum
33{
34 kPGMC_SetPoint0 = 1UL << 0UL,
35 kPGMC_SetPoint1 = 1UL << 1UL,
36 kPGMC_SetPoint2 = 1UL << 2UL,
37 kPGMC_SetPoint3 = 1UL << 3UL,
38 kPGMC_SetPoint4 = 1UL << 4UL,
39 kPGMC_SetPoint5 = 1UL << 5UL,
40 kPGMC_SetPoint6 = 1UL << 6UL,
41 kPGMC_SetPoint7 = 1UL << 7UL,
42 kPGMC_SetPoint8 = 1UL << 8UL,
43 kPGMC_SetPoint9 = 1UL << 9UL,
44 kPGMC_SetPoint10 = 1UL << 10UL,
45 kPGMC_SetPoint11 = 1UL << 11UL,
46 kPGMC_SetPoint12 = 1UL << 12UL,
47 kPGMC_SetPoint13 = 1UL << 13UL,
48 kPGMC_SetPoint14 = 1UL << 14UL,
49 kPGMC_SetPoint15 = 1UL << 15UL,
50};
51
56{
68};
69
74{
76 kPGMC_CM4Core = 1U
78
80typedef enum _pgmc_cpu_mode
81{
82 kPGMC_RunMode = 0x0UL,
87
90{
91 kPGMC_DisableLowPowerControl = 0UL,
92 kPGMC_ControlledByCpuPowerMode = 1UL,
93 kPGMC_ControlledBySetPoint = 2UL,
95
100{
114
119{
132
137{
143 bool powerOff;
147
152{
156 bool powerOff;
160
161/*******************************************************************************
162 * API
163 ******************************************************************************/
164#if defined(__cplusplus)
165extern "C" {
166#endif
167
184 pgmc_cpu_mode_t mode,
186
199 uint32_t setPointMap,
200 const pgmc_bpc_setpoint_mode_option_t *option);
201
213
219static inline void PGMC_BPC_DisableLowPower(PGMC_BPC_Type *base)
220{
221 base->BPC_MODE = PGMC_BPC_BPC_MODE_CTRL_MODE(kPGMC_DisableLowPowerControl);
222}
223
229static inline void PGMC_BPC_RequestStateRestoreAtRunMode(PGMC_BPC_Type *base)
230{
231 base->BPC_SSAR_RESTORE_CTRL |= PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK;
232}
233
241static inline void PGMC_BPC_RequestStateRestoreAtSetPoint(PGMC_BPC_Type *base, uint32_t setPointMap)
242{
243 base->BPC_SSAR_RESTORE_CTRL |= PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP(setPointMap & 0xFFFFU);
244}
245
256static inline void PGMC_BPC_AllowUserModeAccess(PGMC_BPC_Type *base, bool enable)
257{
258 if (enable)
259 {
260 base->BPC_AUTHEN_CTRL |= PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK;
261 }
262 else
263 {
264 base->BPC_AUTHEN_CTRL &= ~PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK;
265 }
266}
267
278static inline void PGMC_BPC_AllowNonSecureModeAccess(PGMC_BPC_Type *base, bool enable)
279{
280 if (enable)
281 {
282 base->BPC_AUTHEN_CTRL |= PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK;
283 }
284 else
285 {
286 base->BPC_AUTHEN_CTRL &= ~PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK;
287 }
288}
289
298static inline void PGMC_BPC_LockAccessSetting(PGMC_BPC_Type *base)
299{
300 base->BPC_AUTHEN_CTRL |= PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK;
301}
302
311static inline void PGMC_BPC_SetDomainIdWhiteList(PGMC_BPC_Type *base, uint8_t domainId)
312{
313 base->BPC_AUTHEN_CTRL = (base->BPC_AUTHEN_CTRL & (~PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK)) |
315}
316
324static inline void PGMC_BPC_LockDomainIDWhiteList(PGMC_BPC_Type *base)
325{
326 base->BPC_AUTHEN_CTRL |= PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK;
327}
328
336static inline void PGMC_BPC_LockLowPowerConfigurationFields(PGMC_BPC_Type *base)
337{
338 base->BPC_AUTHEN_CTRL |= PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK;
339}
340
357
366static inline void PGMC_CPC_CORE_PowerOffBySoftwareMode(PGMC_CPC_Type *base, bool powerOff)
367{
368 if (powerOff)
369 {
370 base->CPC_CORE_POWER_CTRL |=
371 (PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK | PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK);
372 }
373 else
374 {
375 base->CPC_CORE_POWER_CTRL |=
376 (PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK | PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK);
377 }
378}
379
385static inline void PGMC_CPC_CORE_DisableLowPower(PGMC_CPC_Type *base)
386{
387 base->CPC_CORE_MODE = PGMC_CPC_CPC_CORE_MODE_CTRL_MODE(kPGMC_DisableLowPowerControl);
388}
389
400 pgmc_cpu_mode_t mode,
401 pgmc_memory_low_power_level_t memoryLowPowerLevel);
402
415 uint32_t setPointMap,
416 pgmc_memory_low_power_level_t memoryLowPowerLevel);
417
423static inline void PGMC_CPC_CACHE_DisableLowPower(PGMC_CPC_Type *base)
424{
425 base->CPC_CACHE_MODE = PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(kPGMC_DisableLowPowerControl);
426}
427
436
447 pgmc_cpu_mode_t mode,
448 pgmc_memory_low_power_level_t memoryLowPowerLevel);
449
462 uint32_t setPointMap,
463 pgmc_memory_low_power_level_t memoryLowPowerLevel);
464
470static inline void PGMC_CPC_LMEM_DisableLowPower(PGMC_CPC_Type *base)
471{
472 base->CPC_LMEM_MODE = PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(kPGMC_DisableLowPowerControl);
473}
474
483
494static inline void PGMC_CPC_AllowUserModeAccess(PGMC_CPC_Type *base, bool enable)
495{
496 if (enable)
497 {
498 base->CPC_AUTHEN_CTRL |= PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK;
499 }
500 else
501 {
502 base->CPC_AUTHEN_CTRL &= ~PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK;
503 }
504}
505
516static inline void PGMC_CPC_AllowNonSecureModeAccess(PGMC_CPC_Type *base, bool enable)
517{
518 if (enable)
519 {
520 base->CPC_AUTHEN_CTRL |= PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK;
521 }
522 else
523 {
524 base->CPC_AUTHEN_CTRL &= ~PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK;
525 }
526}
527
536static inline void PGMC_CPC_LockAccessSetting(PGMC_CPC_Type *base)
537{
538 base->CPC_AUTHEN_CTRL |= PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK;
539}
540
549static inline void PGMC_CPC_SetDomainIdWhiteList(PGMC_CPC_Type *base, uint8_t domainId)
550{
551 base->CPC_AUTHEN_CTRL = (base->CPC_AUTHEN_CTRL & (~PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK)) |
553}
554
562static inline void PGMC_CPC_LockDomainIDWhiteList(PGMC_CPC_Type *base)
563{
564 base->CPC_AUTHEN_CTRL |= PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK;
565}
566
574static inline void PGMC_CPC_LockLowPowerConfigurationFields(PGMC_CPC_Type *base)
575{
576 base->CPC_AUTHEN_CTRL |= PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK;
577}
578
605void PGMC_MIF_SetSignalBehaviour(PGMC_MIF_Type *base, pgmc_memory_low_power_level_t memoryLevel, uint32_t mask);
606
614static inline void PGMC_MIF_LockLowPowerConfigurationFields(PGMC_MIF_Type *base)
615{
616 base->MIF_AUTHEN_CTRL |= PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK;
617}
618
634static inline void PGMC_PPC_TriggerPMICStandbySoftMode(PGMC_PPC_Type *base, bool enable)
635{
636 if (enable)
637 {
638 PGMC_PPC0->PPC_STBY_CM_CTRL |= PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK;
639 }
640 else
641 {
642 PGMC_PPC0->PPC_STBY_CM_CTRL |= PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK;
643 }
644}
645
653
666void PGMC_PPC_ControlBySetPointMode(PGMC_PPC_Type *base, uint32_t setPointMap, bool enableStandby);
667
673static inline void PGMC_PPC_DisableLowPower(PGMC_PPC_Type *base)
674{
675 base->PPC_MODE = PGMC_PPC_PPC_MODE_CTRL_MODE(kPGMC_DisableLowPowerControl);
676}
677
688static inline void PGMC_PPC_AllowUserModeAccess(PGMC_PPC_Type *base, bool enable)
689{
690 if (enable)
691 {
692 base->PPC_AUTHEN_CTRL |= PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK;
693 }
694 else
695 {
696 base->PPC_AUTHEN_CTRL &= ~PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK;
697 }
698}
699
710static inline void PGMC_PPC_AllowNonSecureModeAccess(PGMC_PPC_Type *base, bool enable)
711{
712 if (enable)
713 {
714 base->PPC_AUTHEN_CTRL |= PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK;
715 }
716 else
717 {
718 base->PPC_AUTHEN_CTRL &= ~PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK;
719 }
720}
721
730static inline void PGMC_PPC_LockAccessSetting(PGMC_PPC_Type *base)
731{
732 base->PPC_AUTHEN_CTRL |= PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK;
733}
734
743static inline void PGMC_PPC_SetDomainIdWhiteList(PGMC_PPC_Type *base, uint8_t domainId)
744{
745 base->PPC_AUTHEN_CTRL = (base->PPC_AUTHEN_CTRL & (~PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK)) |
747}
748
756static inline void PGMC_PPC_LockDomainIDWhiteList(PGMC_PPC_Type *base)
757{
758 base->PPC_AUTHEN_CTRL |= PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK;
759}
760
768static inline void PGMC_PPC_LockLowPowerConfigurationFields(PGMC_PPC_Type *base)
769{
770 base->PPC_AUTHEN_CTRL |= PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK;
771}
772
777#if defined(__cplusplus)
778}
779#endif
783#endif /* _FSL_PGMC_H_ */
#define PGMC_BPC_BPC_MODE_CTRL_MODE(x)
Definition: MIMXRT1166_cm4.h:66628
#define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST(x)
Definition: MIMXRT1166_cm4.h:66602
#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP(x)
Definition: MIMXRT1166_cm4.h:66750
#define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE(x)
Definition: MIMXRT1166_cm4.h:66892
#define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(x)
Definition: MIMXRT1166_cm4.h:67114
#define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(x)
Definition: MIMXRT1166_cm4.h:66962
#define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST(x)
Definition: MIMXRT1166_cm4.h:66866
#define PGMC_PPC0
Definition: MIMXRT1166_cm4.h:67614
#define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST(x)
Definition: MIMXRT1166_cm4.h:67514
#define PGMC_PPC_PPC_MODE_CTRL_MODE(x)
Definition: MIMXRT1166_cm4.h:67540
enum _pgmc_mif_signal pgmc_mif_signal_t
The enumeration of MIF signal.
void PGMC_BPC_ControlPowerDomainBySetPointMode(PGMC_BPC_Type *base, uint32_t setPointMap, const pgmc_bpc_setpoint_mode_option_t *option)
Makes the BPC module controlled by the target set points.
Definition: fsl_pgmc.c:106
_pgmc_control_mode
PGMC control modes.
Definition: fsl_pgmc.h:90
_pgmc_cpu_mode
CPU mode.
Definition: fsl_pgmc.h:81
enum _pgmc_memory_low_power_level pgmc_memory_low_power_level_t
The enumeration of memory low power level.
void PGMC_CPC_CACHE_ControlByCpuPowerMode(PGMC_CPC_Type *base, pgmc_cpu_mode_t mode, pgmc_memory_low_power_level_t memoryLowPowerLevel)
Makes the CPC CACHE module controlled by the target CPU power mode, such as Wait mode.
Definition: fsl_pgmc.c:185
void PGMC_PPC_ControlByCpuPowerMode(PGMC_PPC_Type *base, pgmc_cpu_mode_t mode)
Makes the PMIC module controlled by the target CPU power mode, such as Wait mode.
Definition: fsl_pgmc.c:413
void PGMC_CPC_LMEM_ControlBySetPointMode(PGMC_CPC_Type *base, uint32_t setPointMap, pgmc_memory_low_power_level_t memoryLowPowerLevel)
Makes the CPC LMEM module controlled by the target set points.
Definition: fsl_pgmc.c:328
_pgmc_bpc_assign_domain
PGMC BPC assign domain enumeration.
Definition: fsl_pgmc.h:74
enum _pgmc_control_mode pgmc_control_mode_t
PGMC control modes.
void PGMC_CPC_CACHE_ControlBySetPointMode(PGMC_CPC_Type *base, uint32_t setPointMap, pgmc_memory_low_power_level_t memoryLowPowerLevel)
Makes the CPC CACHE module controlled by the target set points.
Definition: fsl_pgmc.c:228
void PGMC_MIF_SetSignalBehaviour(PGMC_MIF_Type *base, pgmc_memory_low_power_level_t memoryLevel, uint32_t mask)
Sets the behaviour of each signal in MIF, such as Sleep signal.
Definition: fsl_pgmc.c:392
_pgmc_mif_signal
The enumeration of MIF signal.
Definition: fsl_pgmc.h:119
void PGMC_CPC_LMEM_ControlByCpuPowerMode(PGMC_CPC_Type *base, pgmc_cpu_mode_t mode, pgmc_memory_low_power_level_t memoryLowPowerLevel)
Makes the CPC LMEM module controlled by the target CPU power mode, such as Wait mode.
Definition: fsl_pgmc.c:284
void PGMC_CPC_CACHE_TriggerMLPLSoftwareChange(PGMC_CPC_Type *base)
Requests CPC cache module's memory low power level change by software mode.
Definition: fsl_pgmc.c:265
_pgmc_memory_low_power_level
The enumeration of memory low power level.
Definition: fsl_pgmc.h:100
_pgmc_mif_signal_behaviour
The enumeration of MIF signal behaviour(Such as Sleep Signal, Standby Signal, and so on).
Definition: fsl_pgmc.h:56
struct _pgmc_bpc_cpu_power_mode_option pgmc_bpc_cpu_power_mode_option_t
The control option of the power domain controlled by CPU power mode.
void PGMC_PPC_ControlBySetPointMode(PGMC_PPC_Type *base, uint32_t setPointMap, bool enableStandby)
Makes the PMIC module controlled by the target set points.
Definition: fsl_pgmc.c:447
void PGMC_BPC_ControlPowerDomainBySoftwareMode(PGMC_BPC_Type *base, bool powerOff)
Controls the selected power domain by software mode.
Definition: fsl_pgmc.c:136
enum _pgmc_cpu_mode pgmc_cpu_mode_t
CPU mode.
void PGMC_BPC_ControlPowerDomainByCpuPowerMode(PGMC_BPC_Type *base, pgmc_cpu_mode_t mode, const pgmc_bpc_cpu_power_mode_option_t *option)
Makes the BPC module controlled by the target CPU power mode, such as Wait mode.
Definition: fsl_pgmc.c:48
enum _pgmc_bpc_assign_domain pgmc_bpc_assign_domain_t
PGMC BPC assign domain enumeration.
void PGMC_CPC_CORE_PowerOffByCpuPowerMode(PGMC_CPC_Type *base, pgmc_cpu_mode_t mode)
Powers off the CPC core module by the target CPU power mode, such as Wait mode.
Definition: fsl_pgmc.c:154
struct _pgmc_bpc_setpoint_mode_option pgmc_bpc_setpoint_mode_option_t
The control option of the power domain controlled by setpoint mode.
void PGMC_CPC_LMEM_TriggerMLPLSoftwareChange(PGMC_CPC_Type *base)
Requests CPC LMEM module's memory low power level change in software mode.
Definition: fsl_pgmc.c:365
@ kPGMC_StopMode
Definition: fsl_pgmc.h:84
@ kPGMC_WaitMode
Definition: fsl_pgmc.h:83
@ kPGMC_RunMode
Definition: fsl_pgmc.h:82
@ kPGMC_SuspendMode
Definition: fsl_pgmc.h:85
@ kPGMC_CM4Core
Definition: fsl_pgmc.h:76
@ kPGMC_CM7Core
Definition: fsl_pgmc.h:75
@ kPGMC_SetPoint9
Definition: fsl_pgmc.h:43
@ kPGMC_SetPoint2
Definition: fsl_pgmc.h:36
@ kPGMC_SetPoint7
Definition: fsl_pgmc.h:41
@ kPGMC_SetPoint4
Definition: fsl_pgmc.h:38
@ kPGMC_SetPoint8
Definition: fsl_pgmc.h:42
@ kPGMC_SetPoint11
Definition: fsl_pgmc.h:45
@ kPGMC_SetPoint10
Definition: fsl_pgmc.h:44
@ kPGMC_SetPoint13
Definition: fsl_pgmc.h:47
@ kPGMC_SetPoint0
Definition: fsl_pgmc.h:34
@ kPGMC_SetPoint14
Definition: fsl_pgmc.h:48
@ kPGMC_SetPoint5
Definition: fsl_pgmc.h:39
@ kPGMC_SetPoint15
Definition: fsl_pgmc.h:49
@ kPGMC_SetPoint3
Definition: fsl_pgmc.h:37
@ kPGMC_SetPoint1
Definition: fsl_pgmc.h:35
@ kPGMC_SetPoint6
Definition: fsl_pgmc.h:40
@ kPGMC_SetPoint12
Definition: fsl_pgmc.h:46
@ kPGMC_PeripheralPowerDownSignal
Definition: fsl_pgmc.h:126
@ kPGMC_Switch2OffSignal
Definition: fsl_pgmc.h:129
@ kPGMC_InitnSignal
Definition: fsl_pgmc.h:127
@ kPGMC_HighSpeedSignal
Definition: fsl_pgmc.h:123
@ kPGMC_StandbySignal
Definition: fsl_pgmc.h:124
@ kPGMC_ArrayPowerDownSignal
Definition: fsl_pgmc.h:125
@ kPGMC_Switch1OffSignal
Definition: fsl_pgmc.h:128
@ kPGMC_InputGateSignal
Definition: fsl_pgmc.h:121
@ kPGMC_IsoSignal
Definition: fsl_pgmc.h:130
@ kPGMC_LowSpeedSignal
Definition: fsl_pgmc.h:122
@ kPGMC_SleepSignal
Definition: fsl_pgmc.h:120
@ kPGMC_MLPLArrOffPerOn
Definition: fsl_pgmc.h:108
@ kPGMC_MLPLInputGating
Definition: fsl_pgmc.h:104
@ kPGMC_MLPLArrOffPerOff
Definition: fsl_pgmc.h:109
@ kPGMC_MLPLArrOnPerOff
Definition: fsl_pgmc.h:107
@ kPGMC_MLPLNormal
Definition: fsl_pgmc.h:102
@ kPGMC_MLPLSw2PerOff
Definition: fsl_pgmc.h:111
@ kPGMC_MLPLSleep
Definition: fsl_pgmc.h:106
@ kPGMC_MLPLLowSpeed
Definition: fsl_pgmc.h:103
@ kPGMC_MLPLStandby
Definition: fsl_pgmc.h:105
@ kPGMC_MLPLSw1PerOff
Definition: fsl_pgmc.h:112
@ kPGMC_MLPLHighSpeed
Definition: fsl_pgmc.h:101
@ kPGMC_MLPLSw2
Definition: fsl_pgmc.h:110
@ kPGMC_AssertStandbySignal
Definition: fsl_pgmc.h:61
@ kPGMC_AssertSwitch2OffSignal
Definition: fsl_pgmc.h:66
@ kPGMC_AssetLowSpeedSignal
Definition: fsl_pgmc.h:59
@ kPGMC_AssertIsoSignal
Definition: fsl_pgmc.h:67
@ kPGMC_AssertPeripheralPowerDownSignal
Definition: fsl_pgmc.h:63
@ kPGMC_AssertSwitch1OffSignal
Definition: fsl_pgmc.h:65
@ kPGMC_AssertHighSpeedSignal
Definition: fsl_pgmc.h:60
@ kPGMC_AssertInitnSignal
Definition: fsl_pgmc.h:64
@ kPGMC_AssertInputGateSignal
Definition: fsl_pgmc.h:58
@ kPGMC_AssertArrayPowerDownSignal
Definition: fsl_pgmc.h:62
@ kPGMC_AssertSleepSignal
Definition: fsl_pgmc.h:57
Definition: MIMXRT1166_cm4.h:66551
Definition: MIMXRT1166_cm4.h:66812
Definition: MIMXRT1166_cm4.h:67290
Definition: MIMXRT1166_cm4.h:67471
The control option of the power domain controlled by CPU power mode.
Definition: fsl_pgmc.h:137
bool stateSave
Definition: fsl_pgmc.h:140
pgmc_bpc_assign_domain_t assignDomain
Definition: fsl_pgmc.h:138
bool powerOff
Definition: fsl_pgmc.h:143
The control option of the power domain controlled by setpoint mode.
Definition: fsl_pgmc.h:152
bool powerOff
Definition: fsl_pgmc.h:156
bool stateSave
Definition: fsl_pgmc.h:153