CPC_AUTHEN_CTRL - CPC Authentication Control
#define	PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK (0x1U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT (0U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK)

CPC_CORE_MODE - CPC Core Mode
#define	PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK (0x3U)

#define	PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT (0U)

#define	PGMC_CPC_CPC_CORE_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK)

CPC_CORE_POWER_CTRL - CPC core power control
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK)

CPC_FLAG - CPC flag
#define	PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK (0x1U)

#define	PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT (0U)

#define	PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT)) & PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK)

CPC_CACHE_MODE - CPC Cache Mode
#define	PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK (0x3U)

#define	PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT (0U)

#define	PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK)

CPC_CACHE_CM_CTRL - CPC cache CPU mode control
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK (0xFU)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT (0U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT (8U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK (0x10000U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT (16U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK)

CPC_CACHE_SP_CTRL_0 - CPC cache Setpoint control 0
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK)

CPC_CACHE_SP_CTRL_1 - CPC cache Setpoint control 1
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK)

CPC_LMEM_MODE - CPC local memory Mode
#define	PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK (0x3U)

#define	PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT (0U)

#define	PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK)

CPC_LMEM_CM_CTRL - CPC local memory CPU mode control
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK (0xFU)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT (0U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT (8U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK (0x10000U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT (16U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK)

CPC_LMEM_SP_CTRL_0 - CPC local memory Setpoint control 0
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK)

CPC_LMEM_SP_CTRL_1 - CPC local memory Setpoint control 1
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK)

CPC_AUTHEN_CTRL - CPC Authentication Control
#define	PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK (0x1U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT (0U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)

#define	PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK)

CPC_CORE_MODE - CPC Core Mode
#define	PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK (0x3U)

#define	PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT (0U)

#define	PGMC_CPC_CPC_CORE_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK)

CPC_CORE_POWER_CTRL - CPC core power control
#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U)

#define	PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK)

CPC_FLAG - CPC flag
#define	PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK (0x1U)

#define	PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT (0U)

#define	PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT)) & PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK)

CPC_CACHE_MODE - CPC Cache Mode
#define	PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK (0x3U)

#define	PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT (0U)

#define	PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK)

CPC_CACHE_CM_CTRL - CPC cache CPU mode control
#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK (0xFU)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT (0U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT (8U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK (0x10000U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT (16U)

#define	PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK)

CPC_CACHE_SP_CTRL_0 - CPC cache Setpoint control 0
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK)

CPC_CACHE_SP_CTRL_1 - CPC cache Setpoint control 1
#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U)

#define	PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK)

CPC_LMEM_MODE - CPC local memory Mode
#define	PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK (0x3U)

#define	PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT (0U)

#define	PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK)

CPC_LMEM_CM_CTRL - CPC local memory CPU mode control
#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK (0xFU)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT (0U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT (8U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK (0x10000U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT (16U)

#define	PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK)

CPC_LMEM_SP_CTRL_0 - CPC local memory Setpoint control 0
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK)

CPC_LMEM_SP_CTRL_1 - CPC local memory Setpoint control 1
#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U)

#define	PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK)

Detailed Description

Macro Definition Documentation

◆ PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG [1/2]

#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK)

LOCK_CFG - Configuration lock

◆ PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG [2/2]

#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK)

LOCK_CFG - Configuration lock

◆ PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST [1/2]

#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST [2/2]

#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK)

LOCK_LIST - White list lock

◆ PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING [1/2]

#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING [2/2]

#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK)

LOCK_SETTING - Lock NONSECURE and USER

◆ PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE [1/2]

#define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE [2/2]

#define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK)

NONSECURE - Allow non-secure mode access

◆ PGMC_CPC_CPC_AUTHEN_CTRL_USER [1/2]

#define PGMC_CPC_CPC_AUTHEN_CTRL_USER ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK)

USER - Allow user mode access

◆ PGMC_CPC_CPC_AUTHEN_CTRL_USER [2/2]

#define PGMC_CPC_CPC_AUTHEN_CTRL_USER ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK)

USER - Allow user mode access

◆ PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST [1/2]

#define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST [2/2]

#define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK)

WHITE_LIST - Domain ID white list

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN [1/2]

#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK)

MLPL_AT_RUN - Memory Low Power Level (MLPL) at RUN mode

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN [2/2]

#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK)

MLPL_AT_RUN - Memory Low Power Level (MLPL) at RUN mode

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP [1/2]

#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK)

MLPL_AT_STOP - Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP [2/2]

#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK)

MLPL_AT_STOP - Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND [1/2]

#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK)

MLPL_AT_SUSPEND - Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND [2/2]

#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK)

MLPL_AT_SUSPEND - Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT [1/2]

#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK)

MLPL_AT_WAIT - Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT [2/2]

#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK)

MLPL_AT_WAIT - Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT [1/2]

#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK)

MLPL_SOFT - Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT [2/2]

#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK)

MLPL_SOFT - Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete

◆ PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE [1/2]

#define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK)

CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0b00..Not affected by any low power mode 0b01..Controlled by CPU power mode of the domain 0b10..Controlled by Setpoint 0b11..Reserved

◆ PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE [2/2]

#define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK)

CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0b00..Not affected by any low power mode 0b01..Controlled by CPU power mode of the domain 0b10..Controlled by Setpoint 0b11..Reserved

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK)

MLPL_AT_SP0 - Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK)

MLPL_AT_SP0 - Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK)

MLPL_AT_SP1 - Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK)

MLPL_AT_SP1 - Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK)

MLPL_AT_SP2 - Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK)

MLPL_AT_SP2 - Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK)

MLPL_AT_SP3 - Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK)

MLPL_AT_SP3 - Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK)

MLPL_AT_SP4 - Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK)

MLPL_AT_SP4 - Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK)

MLPL_AT_SP5 - Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK)

MLPL_AT_SP5 - Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK)

MLPL_AT_SP6 - Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK)

MLPL_AT_SP6 - Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK)

MLPL_AT_SP7 - Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK)

MLPL_AT_SP7 - Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK)

MLPL_AT_SP10 - Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK)

MLPL_AT_SP10 - Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK)

MLPL_AT_SP11 - Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK)

MLPL_AT_SP11 - Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK)

MLPL_AT_SP12 - Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK)

MLPL_AT_SP12 - Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK)

MLPL_AT_SP13 - Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK)

MLPL_AT_SP13 - Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK)

MLPL_AT_SP14 - Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK)

MLPL_AT_SP14 - Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK)

MLPL_AT_SP15 - Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK)

MLPL_AT_SP15 - Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK)

MLPL_AT_SP8 - Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK)

MLPL_AT_SP8 - Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9 [1/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK)

MLPL_AT_SP9 - Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9 [2/2]

#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK)

MLPL_AT_SP9 - Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_CORE_MODE_CTRL_MODE [1/2]

#define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK)

CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0b00..Not affected by any low power mode 0b01..Controlled by CPU power mode of the domain 0b10..Reserved 0b11..Reserved

◆ PGMC_CPC_CPC_CORE_MODE_CTRL_MODE [2/2]

#define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK)

CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0b00..Not affected by any low power mode 0b01..Controlled by CPU power mode of the domain 0b10..Reserved 0b11..Reserved

◆ PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT [1/2]

#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK)

ISO_OFF_SOFT - Software isolation off trigger

◆ PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT [2/2]

#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK)

ISO_OFF_SOFT - Software isolation off trigger

◆ PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT [1/2]

#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK)

ISO_ON_SOFT - Software isolation on trigger

◆ PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT [2/2]

#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK)

ISO_ON_SOFT - Software isolation on trigger

◆ PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT [1/2]

#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK)

PSW_OFF_SOFT - Software power off trigger

◆ PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT [2/2]

#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK)

PSW_OFF_SOFT - Software power off trigger

◆ PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT [1/2]

#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK)

PSW_ON_SOFT - Software power on trigger

◆ PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT [2/2]

#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK)

PSW_ON_SOFT - Software power on trigger

◆ PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP [1/2]

#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK)

PWR_OFF_AT_STOP - Power off when domain enters STOP mode

◆ PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP [2/2]

#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK)

PWR_OFF_AT_STOP - Power off when domain enters STOP mode

◆ PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND [1/2]

#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK)

PWR_OFF_AT_SUSPEND - Power off when domain enters SUSPEND mode

◆ PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND [2/2]

#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK)

PWR_OFF_AT_SUSPEND - Power off when domain enters SUSPEND mode

◆ PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT [1/2]

#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK)

PWR_OFF_AT_WAIT - Power off when domain enters WAIT mode

◆ PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT [2/2]

#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK)

PWR_OFF_AT_WAIT - Power off when domain enters WAIT mode

◆ PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG [1/2]

#define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT)) & PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK)

CORE_PDN_FLAG - set to 1 after core power switch off, cleared by writing 1

◆ PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG [2/2]

#define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT)) & PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK)

CORE_PDN_FLAG - set to 1 after core power switch off, cleared by writing 1

◆ PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN [1/2]

#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK)

MLPL_AT_RUN - Memory Low Power Level (MLPL) at RUN mode

◆ PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN [2/2]

#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK)

MLPL_AT_RUN - Memory Low Power Level (MLPL) at RUN mode

◆ PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP [1/2]

#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK)

MLPL_AT_STOP - Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP [2/2]

#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK)

MLPL_AT_STOP - Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND [1/2]

#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK)

MLPL_AT_SUSPEND - Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND [2/2]

#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK)

MLPL_AT_SUSPEND - Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT [1/2]

#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK)

MLPL_AT_WAIT - Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT [2/2]

#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK)

MLPL_AT_WAIT - Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT [1/2]

#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK)

MLPL_SOFT - Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete

◆ PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT [2/2]

#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK)

MLPL_SOFT - Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete

◆ PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE [1/2]

#define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK)

CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0b00..Not affected by any low power mode 0b01..Controlled by CPU power mode of the domain 0b10..Controlled by Setpoint 0b11..Reserved

◆ PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE [2/2]

#define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK)

CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field. 0b00..Not affected by any low power mode 0b01..Controlled by CPU power mode of the domain 0b10..Controlled by Setpoint 0b11..Reserved

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK)

MLPL_AT_SP0 - Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK)

MLPL_AT_SP0 - Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK)

MLPL_AT_SP1 - Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK)

MLPL_AT_SP1 - Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK)

MLPL_AT_SP2 - Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK)

MLPL_AT_SP2 - Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK)

MLPL_AT_SP3 - Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK)

MLPL_AT_SP3 - Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK)

MLPL_AT_SP4 - Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK)

MLPL_AT_SP4 - Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK)

MLPL_AT_SP5 - Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK)

MLPL_AT_SP5 - Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK)

MLPL_AT_SP6 - Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK)

MLPL_AT_SP6 - Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK)

MLPL_AT_SP7 - Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK)

MLPL_AT_SP7 - Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK)

MLPL_AT_SP10 - Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK)

MLPL_AT_SP10 - Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK)

MLPL_AT_SP11 - Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK)

MLPL_AT_SP11 - Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK)

MLPL_AT_SP12 - Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK)

MLPL_AT_SP12 - Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK)

MLPL_AT_SP13 - Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK)

MLPL_AT_SP13 - Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK)

MLPL_AT_SP14 - Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK)

MLPL_AT_SP14 - Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK)

MLPL_AT_SP15 - Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK)

MLPL_AT_SP15 - Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK)

MLPL_AT_SP8 - Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK)

MLPL_AT_SP8 - Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9 [1/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK)

MLPL_AT_SP9 - Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

◆ PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9 [2/2]

#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9 ( x ) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK)

MLPL_AT_SP9 - Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.

CPC_AUTHEN_CTRL - CPC Authentication Control

CPC_CORE_MODE - CPC Core Mode

CPC_CORE_POWER_CTRL - CPC core power control

CPC_FLAG - CPC flag

CPC_CACHE_MODE - CPC Cache Mode

CPC_CACHE_CM_CTRL - CPC cache CPU mode control

CPC_CACHE_SP_CTRL_0 - CPC cache Setpoint control 0

CPC_CACHE_SP_CTRL_1 - CPC cache Setpoint control 1

CPC_LMEM_MODE - CPC local memory Mode

CPC_LMEM_CM_CTRL - CPC local memory CPU mode control

CPC_LMEM_SP_CTRL_0 - CPC local memory Setpoint control 0

CPC_LMEM_SP_CTRL_1 - CPC local memory Setpoint control 1

CPC_AUTHEN_CTRL - CPC Authentication Control

CPC_CORE_MODE - CPC Core Mode

CPC_CORE_POWER_CTRL - CPC core power control

CPC_FLAG - CPC flag

CPC_CACHE_MODE - CPC Cache Mode

CPC_CACHE_CM_CTRL - CPC cache CPU mode control

CPC_CACHE_SP_CTRL_0 - CPC cache Setpoint control 0

CPC_CACHE_SP_CTRL_1 - CPC cache Setpoint control 1

CPC_LMEM_MODE - CPC local memory Mode

CPC_LMEM_CM_CTRL - CPC local memory CPU mode control

CPC_LMEM_SP_CTRL_0 - CPC local memory Setpoint control 0

CPC_LMEM_SP_CTRL_1 - CPC local memory Setpoint control 1

Detailed Description

Macro Definition Documentation

◆ PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG [1/2]

◆ PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG [2/2]

◆ PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST [1/2]

◆ PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST [2/2]

◆ PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING [1/2]

◆ PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING [2/2]

◆ PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE [1/2]

◆ PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE [2/2]

◆ PGMC_CPC_CPC_AUTHEN_CTRL_USER [1/2]

◆ PGMC_CPC_CPC_AUTHEN_CTRL_USER [2/2]

◆ PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST [1/2]

◆ PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST [2/2]

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN [1/2]

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN [2/2]

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP [1/2]

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP [2/2]

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND [1/2]

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND [2/2]

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT [1/2]

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT [2/2]

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT [1/2]

◆ PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT [2/2]

◆ PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE [1/2]

◆ PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE [2/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0 [1/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0 [2/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1 [1/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1 [2/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2 [1/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2 [2/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3 [1/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3 [2/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4 [1/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4 [2/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5 [1/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5 [2/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6 [1/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6 [2/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7 [1/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7 [2/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10 [1/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10 [2/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11 [1/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11 [2/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12 [1/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12 [2/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13 [1/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13 [2/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14 [1/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14 [2/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15 [1/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15 [2/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8 [1/2]

◆ PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8 [2/2]