This header file provides the API to read and write the AArch32 system registers. More...

#include <stdint.h>

Macros
#define	AARCH32_APSR_GE(_val) ( ( _val ) << 16 )

#define	AARCH32_APSR_GE_SHIFT 16

#define	AARCH32_APSR_GE_MASK 0xf0000U

#define	AARCH32_APSR_GE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_APSR_Q 0x8000000U

#define	AARCH32_APSR_V 0x10000000U

#define	AARCH32_APSR_C 0x20000000U

#define	AARCH32_APSR_Z 0x40000000U

#define	AARCH32_APSR_N 0x80000000U

#define	AARCH32_CCSIDR_LINESIZE(_val) ( ( _val ) << 0 )

#define	AARCH32_CCSIDR_LINESIZE_SHIFT 0

#define	AARCH32_CCSIDR_LINESIZE_MASK 0x7U

#define	AARCH32_CCSIDR_LINESIZE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x7U )

#define	AARCH32_CCSIDR_ASSOCIATIVITY_0(_val) ( ( _val ) << 3 )

#define	AARCH32_CCSIDR_ASSOCIATIVITY_SHIFT_0 3

#define	AARCH32_CCSIDR_ASSOCIATIVITY_MASK_0 0x1ff8U

#define	AARCH32_CCSIDR_ASSOCIATIVITY_GET_0(_reg) ( ( ( _reg ) >> 3 ) & 0x3ffU )

#define	AARCH32_CCSIDR_ASSOCIATIVITY_1(_val) ( ( _val ) << 3 )

#define	AARCH32_CCSIDR_ASSOCIATIVITY_SHIFT_1 3

#define	AARCH32_CCSIDR_ASSOCIATIVITY_MASK_1 0xfffff8U

#define	AARCH32_CCSIDR_ASSOCIATIVITY_GET_1(_reg) ( ( ( _reg ) >> 3 ) & 0x1fffffU )

#define	AARCH32_CCSIDR_NUMSETS(_val) ( ( _val ) << 13 )

#define	AARCH32_CCSIDR_NUMSETS_SHIFT 13

#define	AARCH32_CCSIDR_NUMSETS_MASK 0xfffe000U

#define	AARCH32_CCSIDR_NUMSETS_GET(_reg) ( ( ( _reg ) >> 13 ) & 0x7fffU )

#define	AARCH32_CCSIDR2_NUMSETS(_val) ( ( _val ) << 0 )

#define	AARCH32_CCSIDR2_NUMSETS_SHIFT 0

#define	AARCH32_CCSIDR2_NUMSETS_MASK 0xffffffU

#define	AARCH32_CCSIDR2_NUMSETS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffU )

#define	AARCH32_CFPRCTX_ASID(_val) ( ( _val ) << 0 )

#define	AARCH32_CFPRCTX_ASID_SHIFT 0

#define	AARCH32_CFPRCTX_ASID_MASK 0xffU

#define	AARCH32_CFPRCTX_ASID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_CFPRCTX_GASID 0x100U

#define	AARCH32_CFPRCTX_VMID(_val) ( ( _val ) << 16 )

#define	AARCH32_CFPRCTX_VMID_SHIFT 16

#define	AARCH32_CFPRCTX_VMID_MASK 0xff0000U

#define	AARCH32_CFPRCTX_VMID_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xffU )

#define	AARCH32_CFPRCTX_EL(_val) ( ( _val ) << 24 )

#define	AARCH32_CFPRCTX_EL_SHIFT 24

#define	AARCH32_CFPRCTX_EL_MASK 0x3000000U

#define	AARCH32_CFPRCTX_EL_GET(_reg) ( ( ( _reg ) >> 24 ) & 0x3U )

#define	AARCH32_CFPRCTX_NS 0x4000000U

#define	AARCH32_CFPRCTX_GVMID 0x8000000U

#define	AARCH32_CLIDR_LOUIS(_val) ( ( _val ) << 21 )

#define	AARCH32_CLIDR_LOUIS_SHIFT 21

#define	AARCH32_CLIDR_LOUIS_MASK 0xe00000U

#define	AARCH32_CLIDR_LOUIS_GET(_reg) ( ( ( _reg ) >> 21 ) & 0x7U )

#define	AARCH32_CLIDR_LOC(_val) ( ( _val ) << 24 )

#define	AARCH32_CLIDR_LOC_SHIFT 24

#define	AARCH32_CLIDR_LOC_MASK 0x7000000U

#define	AARCH32_CLIDR_LOC_GET(_reg) ( ( ( _reg ) >> 24 ) & 0x7U )

#define	AARCH32_CLIDR_LOUU(_val) ( ( _val ) << 27 )

#define	AARCH32_CLIDR_LOUU_SHIFT 27

#define	AARCH32_CLIDR_LOUU_MASK 0x38000000U

#define	AARCH32_CLIDR_LOUU_GET(_reg) ( ( ( _reg ) >> 27 ) & 0x7U )

#define	AARCH32_CLIDR_ICB(_val) ( ( _val ) << 30 )

#define	AARCH32_CLIDR_ICB_SHIFT 30

#define	AARCH32_CLIDR_ICB_MASK 0xc0000000U

#define	AARCH32_CLIDR_ICB_GET(_reg) ( ( ( _reg ) >> 30 ) & 0x3U )

#define	AARCH32_CONTEXTIDR_ASID(_val) ( ( _val ) << 0 )

#define	AARCH32_CONTEXTIDR_ASID_SHIFT 0

#define	AARCH32_CONTEXTIDR_ASID_MASK 0xffU

#define	AARCH32_CONTEXTIDR_ASID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_CONTEXTIDR_PROCID(_val) ( ( _val ) << 8 )

#define	AARCH32_CONTEXTIDR_PROCID_SHIFT 8

#define	AARCH32_CONTEXTIDR_PROCID_MASK 0xffffff00U

#define	AARCH32_CONTEXTIDR_PROCID_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xffffffU )

#define	AARCH32_CPACR_CP10(_val) ( ( _val ) << 20 )

#define	AARCH32_CPACR_CP10_SHIFT 20

#define	AARCH32_CPACR_CP10_MASK 0x300000U

#define	AARCH32_CPACR_CP10_GET(_reg) ( ( ( _reg ) >> 20 ) & 0x3U )

#define	AARCH32_CPACR_CP11(_val) ( ( _val ) << 22 )

#define	AARCH32_CPACR_CP11_SHIFT 22

#define	AARCH32_CPACR_CP11_MASK 0xc00000U

#define	AARCH32_CPACR_CP11_GET(_reg) ( ( ( _reg ) >> 22 ) & 0x3U )

#define	AARCH32_CPACR_TRCDIS 0x10000000U

#define	AARCH32_CPACR_ASEDIS 0x80000000U

#define	AARCH32_CPSR_M(_val) ( ( _val ) << 0 )

#define	AARCH32_CPSR_M_SHIFT 0

#define	AARCH32_CPSR_M_MASK 0xfU

#define	AARCH32_CPSR_M_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_CPSR_F 0x40U

#define	AARCH32_CPSR_I 0x80U

#define	AARCH32_CPSR_A 0x100U

#define	AARCH32_CPSR_E 0x200U

#define	AARCH32_CPSR_GE(_val) ( ( _val ) << 16 )

#define	AARCH32_CPSR_GE_SHIFT 16

#define	AARCH32_CPSR_GE_MASK 0xf0000U

#define	AARCH32_CPSR_GE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_CPSR_DIT 0x200000U

#define	AARCH32_CPSR_PAN 0x400000U

#define	AARCH32_CPSR_SSBS 0x800000U

#define	AARCH32_CPSR_Q 0x8000000U

#define	AARCH32_CPSR_V 0x10000000U

#define	AARCH32_CPSR_C 0x20000000U

#define	AARCH32_CPSR_Z 0x40000000U

#define	AARCH32_CPSR_N 0x80000000U

#define	AARCH32_CPPRCTX_ASID(_val) ( ( _val ) << 0 )

#define	AARCH32_CPPRCTX_ASID_SHIFT 0

#define	AARCH32_CPPRCTX_ASID_MASK 0xffU

#define	AARCH32_CPPRCTX_ASID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_CPPRCTX_GASID 0x100U

#define	AARCH32_CPPRCTX_VMID(_val) ( ( _val ) << 16 )

#define	AARCH32_CPPRCTX_VMID_SHIFT 16

#define	AARCH32_CPPRCTX_VMID_MASK 0xff0000U

#define	AARCH32_CPPRCTX_VMID_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xffU )

#define	AARCH32_CPPRCTX_EL(_val) ( ( _val ) << 24 )

#define	AARCH32_CPPRCTX_EL_SHIFT 24

#define	AARCH32_CPPRCTX_EL_MASK 0x3000000U

#define	AARCH32_CPPRCTX_EL_GET(_reg) ( ( ( _reg ) >> 24 ) & 0x3U )

#define	AARCH32_CPPRCTX_NS 0x4000000U

#define	AARCH32_CPPRCTX_GVMID 0x8000000U

#define	AARCH32_CSSELR_IND 0x1U

#define	AARCH32_CSSELR_LEVEL(_val) ( ( _val ) << 1 )

#define	AARCH32_CSSELR_LEVEL_SHIFT 1

#define	AARCH32_CSSELR_LEVEL_MASK 0xeU

#define	AARCH32_CSSELR_LEVEL_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7U )

#define	AARCH32_CTR_IMINLINE(_val) ( ( _val ) << 0 )

#define	AARCH32_CTR_IMINLINE_SHIFT 0

#define	AARCH32_CTR_IMINLINE_MASK 0xfU

#define	AARCH32_CTR_IMINLINE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_CTR_L1IP(_val) ( ( _val ) << 14 )

#define	AARCH32_CTR_L1IP_SHIFT 14

#define	AARCH32_CTR_L1IP_MASK 0xc000U

#define	AARCH32_CTR_L1IP_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U )

#define	AARCH32_CTR_DMINLINE(_val) ( ( _val ) << 16 )

#define	AARCH32_CTR_DMINLINE_SHIFT 16

#define	AARCH32_CTR_DMINLINE_MASK 0xf0000U

#define	AARCH32_CTR_DMINLINE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_CTR_ERG(_val) ( ( _val ) << 20 )

#define	AARCH32_CTR_ERG_SHIFT 20

#define	AARCH32_CTR_ERG_MASK 0xf00000U

#define	AARCH32_CTR_ERG_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_CTR_CWG(_val) ( ( _val ) << 24 )

#define	AARCH32_CTR_CWG_SHIFT 24

#define	AARCH32_CTR_CWG_MASK 0xf000000U

#define	AARCH32_CTR_CWG_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_CTR_IDC 0x10000000U

#define	AARCH32_CTR_DIC 0x20000000U

#define	AARCH32_DCCISW_LEVEL(_val) ( ( _val ) << 1 )

#define	AARCH32_DCCISW_LEVEL_SHIFT 1

#define	AARCH32_DCCISW_LEVEL_MASK 0xeU

#define	AARCH32_DCCISW_LEVEL_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7U )

#define	AARCH32_DCCISW_SETWAY(_val) ( ( _val ) << 4 )

#define	AARCH32_DCCISW_SETWAY_SHIFT 4

#define	AARCH32_DCCISW_SETWAY_MASK 0xfffffff0U

#define	AARCH32_DCCISW_SETWAY_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfffffffU )

#define	AARCH32_DCCSW_LEVEL(_val) ( ( _val ) << 1 )

#define	AARCH32_DCCSW_LEVEL_SHIFT 1

#define	AARCH32_DCCSW_LEVEL_MASK 0xeU

#define	AARCH32_DCCSW_LEVEL_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7U )

#define	AARCH32_DCCSW_SETWAY(_val) ( ( _val ) << 4 )

#define	AARCH32_DCCSW_SETWAY_SHIFT 4

#define	AARCH32_DCCSW_SETWAY_MASK 0xfffffff0U

#define	AARCH32_DCCSW_SETWAY_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfffffffU )

#define	AARCH32_DCISW_LEVEL(_val) ( ( _val ) << 1 )

#define	AARCH32_DCISW_LEVEL_SHIFT 1

#define	AARCH32_DCISW_LEVEL_MASK 0xeU

#define	AARCH32_DCISW_LEVEL_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7U )

#define	AARCH32_DCISW_SETWAY(_val) ( ( _val ) << 4 )

#define	AARCH32_DCISW_SETWAY_SHIFT 4

#define	AARCH32_DCISW_SETWAY_MASK 0xfffffff0U

#define	AARCH32_DCISW_SETWAY_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfffffffU )

#define	AARCH32_DFSR_FS_3_0(_val) ( ( _val ) << 0 )

#define	AARCH32_DFSR_FS_3_0_SHIFT 0

#define	AARCH32_DFSR_FS_3_0_MASK 0xfU

#define	AARCH32_DFSR_FS_3_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_DFSR_STATUS(_val) ( ( _val ) << 0 )

#define	AARCH32_DFSR_STATUS_SHIFT 0

#define	AARCH32_DFSR_STATUS_MASK 0x3fU

#define	AARCH32_DFSR_STATUS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU )

#define	AARCH32_DFSR_DOMAIN(_val) ( ( _val ) << 4 )

#define	AARCH32_DFSR_DOMAIN_SHIFT 4

#define	AARCH32_DFSR_DOMAIN_MASK 0xf0U

#define	AARCH32_DFSR_DOMAIN_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_DFSR_LPAE 0x200U

#define	AARCH32_DFSR_FS_4 0x400U

#define	AARCH32_DFSR_WNR 0x800U

#define	AARCH32_DFSR_EXT 0x1000U

#define	AARCH32_DFSR_CM 0x2000U

#define	AARCH32_DFSR_AET(_val) ( ( _val ) << 14 )

#define	AARCH32_DFSR_AET_SHIFT 14

#define	AARCH32_DFSR_AET_MASK 0xc000U

#define	AARCH32_DFSR_AET_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U )

#define	AARCH32_DFSR_FNV 0x10000U

#define	AARCH32_DTLBIASID_ASID(_val) ( ( _val ) << 0 )

#define	AARCH32_DTLBIASID_ASID_SHIFT 0

#define	AARCH32_DTLBIASID_ASID_MASK 0xffU

#define	AARCH32_DTLBIASID_ASID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_DTLBIMVA_ASID(_val) ( ( _val ) << 0 )

#define	AARCH32_DTLBIMVA_ASID_SHIFT 0

#define	AARCH32_DTLBIMVA_ASID_MASK 0xffU

#define	AARCH32_DTLBIMVA_ASID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_DTLBIMVA_VA(_val) ( ( _val ) << 12 )

#define	AARCH32_DTLBIMVA_VA_SHIFT 12

#define	AARCH32_DTLBIMVA_VA_MASK 0xfffff000U

#define	AARCH32_DTLBIMVA_VA_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffU )

#define	AARCH32_DVPRCTX_ASID(_val) ( ( _val ) << 0 )

#define	AARCH32_DVPRCTX_ASID_SHIFT 0

#define	AARCH32_DVPRCTX_ASID_MASK 0xffU

#define	AARCH32_DVPRCTX_ASID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_DVPRCTX_GASID 0x100U

#define	AARCH32_DVPRCTX_VMID(_val) ( ( _val ) << 16 )

#define	AARCH32_DVPRCTX_VMID_SHIFT 16

#define	AARCH32_DVPRCTX_VMID_MASK 0xff0000U

#define	AARCH32_DVPRCTX_VMID_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xffU )

#define	AARCH32_DVPRCTX_EL(_val) ( ( _val ) << 24 )

#define	AARCH32_DVPRCTX_EL_SHIFT 24

#define	AARCH32_DVPRCTX_EL_MASK 0x3000000U

#define	AARCH32_DVPRCTX_EL_GET(_reg) ( ( ( _reg ) >> 24 ) & 0x3U )

#define	AARCH32_DVPRCTX_NS 0x4000000U

#define	AARCH32_DVPRCTX_GVMID 0x8000000U

#define	AARCH32_FPEXC_IOF 0x1U

#define	AARCH32_FPEXC_DZF 0x2U

#define	AARCH32_FPEXC_OFF 0x4U

#define	AARCH32_FPEXC_UFF 0x8U

#define	AARCH32_FPEXC_IXF 0x10U

#define	AARCH32_FPEXC_IDF 0x80U

#define	AARCH32_FPEXC_VECITR(_val) ( ( _val ) << 8 )

#define	AARCH32_FPEXC_VECITR_SHIFT 8

#define	AARCH32_FPEXC_VECITR_MASK 0x700U

#define	AARCH32_FPEXC_VECITR_GET(_reg) ( ( ( _reg ) >> 8 ) & 0x7U )

#define	AARCH32_FPEXC_TFV 0x4000000U

#define	AARCH32_FPEXC_VV 0x8000000U

#define	AARCH32_FPEXC_FP2V 0x10000000U

#define	AARCH32_FPEXC_DEX 0x20000000U

#define	AARCH32_FPEXC_EN 0x40000000U

#define	AARCH32_FPEXC_EX 0x80000000U

#define	AARCH32_FPSCR_IOC 0x1U

#define	AARCH32_FPSCR_DZC 0x2U

#define	AARCH32_FPSCR_OFC 0x4U

#define	AARCH32_FPSCR_UFC 0x8U

#define	AARCH32_FPSCR_IXC 0x10U

#define	AARCH32_FPSCR_IDC 0x80U

#define	AARCH32_FPSCR_IOE 0x100U

#define	AARCH32_FPSCR_DZE 0x200U

#define	AARCH32_FPSCR_OFE 0x400U

#define	AARCH32_FPSCR_UFE 0x800U

#define	AARCH32_FPSCR_IXE 0x1000U

#define	AARCH32_FPSCR_IDE 0x8000U

#define	AARCH32_FPSCR_LEN(_val) ( ( _val ) << 16 )

#define	AARCH32_FPSCR_LEN_SHIFT 16

#define	AARCH32_FPSCR_LEN_MASK 0x70000U

#define	AARCH32_FPSCR_LEN_GET(_reg) ( ( ( _reg ) >> 16 ) & 0x7U )

#define	AARCH32_FPSCR_FZ16 0x80000U

#define	AARCH32_FPSCR_STRIDE(_val) ( ( _val ) << 20 )

#define	AARCH32_FPSCR_STRIDE_SHIFT 20

#define	AARCH32_FPSCR_STRIDE_MASK 0x300000U

#define	AARCH32_FPSCR_STRIDE_GET(_reg) ( ( ( _reg ) >> 20 ) & 0x3U )

#define	AARCH32_FPSCR_RMODE(_val) ( ( _val ) << 22 )

#define	AARCH32_FPSCR_RMODE_SHIFT 22

#define	AARCH32_FPSCR_RMODE_MASK 0xc00000U

#define	AARCH32_FPSCR_RMODE_GET(_reg) ( ( ( _reg ) >> 22 ) & 0x3U )

#define	AARCH32_FPSCR_FZ 0x1000000U

#define	AARCH32_FPSCR_DN 0x2000000U

#define	AARCH32_FPSCR_AHP 0x4000000U

#define	AARCH32_FPSCR_QC 0x8000000U

#define	AARCH32_FPSCR_V 0x10000000U

#define	AARCH32_FPSCR_C 0x20000000U

#define	AARCH32_FPSCR_Z 0x40000000U

#define	AARCH32_FPSCR_N 0x80000000U

#define	AARCH32_FPSID_REVISION(_val) ( ( _val ) << 0 )

#define	AARCH32_FPSID_REVISION_SHIFT 0

#define	AARCH32_FPSID_REVISION_MASK 0xfU

#define	AARCH32_FPSID_REVISION_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_FPSID_VARIANT(_val) ( ( _val ) << 4 )

#define	AARCH32_FPSID_VARIANT_SHIFT 4

#define	AARCH32_FPSID_VARIANT_MASK 0xf0U

#define	AARCH32_FPSID_VARIANT_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_FPSID_PARTNUM(_val) ( ( _val ) << 8 )

#define	AARCH32_FPSID_PARTNUM_SHIFT 8

#define	AARCH32_FPSID_PARTNUM_MASK 0xff00U

#define	AARCH32_FPSID_PARTNUM_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xffU )

#define	AARCH32_FPSID_SUBARCHITECTURE(_val) ( ( _val ) << 16 )

#define	AARCH32_FPSID_SUBARCHITECTURE_SHIFT 16

#define	AARCH32_FPSID_SUBARCHITECTURE_MASK 0x7f0000U

#define	AARCH32_FPSID_SUBARCHITECTURE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0x7fU )

#define	AARCH32_FPSID_SW 0x800000U

#define	AARCH32_FPSID_IMPLEMENTER(_val) ( ( _val ) << 24 )

#define	AARCH32_FPSID_IMPLEMENTER_SHIFT 24

#define	AARCH32_FPSID_IMPLEMENTER_MASK 0xff000000U

#define	AARCH32_FPSID_IMPLEMENTER_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xffU )

#define	AARCH32_HCPTR_TCP10 0x400U

#define	AARCH32_HCPTR_TCP11 0x800U

#define	AARCH32_HCPTR_TASE 0x8000U

#define	AARCH32_HCPTR_TTA 0x100000U

#define	AARCH32_HCPTR_TAM 0x40000000U

#define	AARCH32_HCPTR_TCPAC 0x80000000U

#define	AARCH32_HCR_VM 0x1U

#define	AARCH32_HCR_SWIO 0x2U

#define	AARCH32_HCR_PTW 0x4U

#define	AARCH32_HCR_FMO 0x8U

#define	AARCH32_HCR_IMO 0x10U

#define	AARCH32_HCR_AMO 0x20U

#define	AARCH32_HCR_VF 0x40U

#define	AARCH32_HCR_VI 0x80U

#define	AARCH32_HCR_VA 0x100U

#define	AARCH32_HCR_FB 0x200U

#define	AARCH32_HCR_BSU(_val) ( ( _val ) << 10 )

#define	AARCH32_HCR_BSU_SHIFT 10

#define	AARCH32_HCR_BSU_MASK 0xc00U

#define	AARCH32_HCR_BSU_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3U )

#define	AARCH32_HCR_DC 0x1000U

#define	AARCH32_HCR_TWI 0x2000U

#define	AARCH32_HCR_TWE 0x4000U

#define	AARCH32_HCR_TID0 0x8000U

#define	AARCH32_HCR_TID1 0x10000U

#define	AARCH32_HCR_TID2 0x20000U

#define	AARCH32_HCR_TID3 0x40000U

#define	AARCH32_HCR_TSC 0x80000U

#define	AARCH32_HCR_TIDCP 0x100000U

#define	AARCH32_HCR_TAC 0x200000U

#define	AARCH32_HCR_TSW 0x400000U

#define	AARCH32_HCR_TPC 0x800000U

#define	AARCH32_HCR_TPU 0x1000000U

#define	AARCH32_HCR_TTLB 0x2000000U

#define	AARCH32_HCR_TVM 0x4000000U

#define	AARCH32_HCR_TGE 0x8000000U

#define	AARCH32_HCR_HCD 0x20000000U

#define	AARCH32_HCR_TRVM 0x40000000U

#define	AARCH32_HCR2_CD 0x1U

#define	AARCH32_HCR2_ID 0x2U

#define	AARCH32_HCR2_TERR 0x10U

#define	AARCH32_HCR2_TEA 0x20U

#define	AARCH32_HCR2_MIOCNCE 0x40U

#define	AARCH32_HCR2_TID4 0x20000U

#define	AARCH32_HCR2_TICAB 0x40000U

#define	AARCH32_HCR2_TOCU 0x100000U

#define	AARCH32_HCR2_TTLBIS 0x400000U

#define	AARCH32_HPFAR_FIPA_39_12(_val) ( ( _val ) << 4 )

#define	AARCH32_HPFAR_FIPA_39_12_SHIFT 4

#define	AARCH32_HPFAR_FIPA_39_12_MASK 0xfffffff0U

#define	AARCH32_HPFAR_FIPA_39_12_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfffffffU )

#define	AARCH32_HRMR_AA64 0x1U

#define	AARCH32_HRMR_RR 0x2U

#define	AARCH32_HSCTLR_M 0x1U

#define	AARCH32_HSCTLR_A 0x2U

#define	AARCH32_HSCTLR_C 0x4U

#define	AARCH32_HSCTLR_NTLSMD 0x8U

#define	AARCH32_HSCTLR_LSMAOE 0x10U

#define	AARCH32_HSCTLR_CP15BEN 0x20U

#define	AARCH32_HSCTLR_ITD 0x80U

#define	AARCH32_HSCTLR_SED 0x100U

#define	AARCH32_HSCTLR_I 0x1000U

#define	AARCH32_HSCTLR_BR 0x20000U

#define	AARCH32_HSCTLR_WXN 0x80000U

#define	AARCH32_HSCTLR_FI 0x200000U

#define	AARCH32_HSCTLR_EE 0x2000000U

#define	AARCH32_HSCTLR_TE 0x40000000U

#define	AARCH32_HSCTLR_DSSBS 0x80000000U

#define	AARCH32_HSR_DIRECTION 0x1U

#define	AARCH32_HSR_TI 0x1U

#define	AARCH32_HSR_COPROC(_val) ( ( _val ) << 0 )

#define	AARCH32_HSR_COPROC_SHIFT 0

#define	AARCH32_HSR_COPROC_MASK 0xfU

#define	AARCH32_HSR_COPROC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_HSR_DFSC(_val) ( ( _val ) << 0 )

#define	AARCH32_HSR_DFSC_SHIFT 0

#define	AARCH32_HSR_DFSC_MASK 0x3fU

#define	AARCH32_HSR_DFSC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU )

#define	AARCH32_HSR_IFSC(_val) ( ( _val ) << 0 )

#define	AARCH32_HSR_IFSC_SHIFT 0

#define	AARCH32_HSR_IFSC_MASK 0x3fU

#define	AARCH32_HSR_IFSC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU )

#define	AARCH32_HSR_IMM16(_val) ( ( _val ) << 0 )

#define	AARCH32_HSR_IMM16_SHIFT 0

#define	AARCH32_HSR_IMM16_MASK 0xffffU

#define	AARCH32_HSR_IMM16_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU )

#define	AARCH32_HSR_ISS(_val) ( ( _val ) << 0 )

#define	AARCH32_HSR_ISS_SHIFT 0

#define	AARCH32_HSR_ISS_MASK 0x1ffffffU

#define	AARCH32_HSR_ISS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1ffffffU )

#define	AARCH32_HSR_AM(_val) ( ( _val ) << 1 )

#define	AARCH32_HSR_AM_SHIFT 1

#define	AARCH32_HSR_AM_MASK 0xeU

#define	AARCH32_HSR_AM_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7U )

#define	AARCH32_HSR_CRM(_val) ( ( _val ) << 1 )

#define	AARCH32_HSR_CRM_SHIFT 1

#define	AARCH32_HSR_CRM_MASK 0x1eU

#define	AARCH32_HSR_CRM_GET(_reg) ( ( ( _reg ) >> 1 ) & 0xfU )

#define	AARCH32_HSR_OFFSET 0x10U

#define	AARCH32_HSR_TA 0x20U

#define	AARCH32_HSR_RN(_val) ( ( _val ) << 5 )

#define	AARCH32_HSR_RN_SHIFT 5

#define	AARCH32_HSR_RN_MASK 0x1e0U

#define	AARCH32_HSR_RN_GET(_reg) ( ( ( _reg ) >> 5 ) & 0xfU )

#define	AARCH32_HSR_RT(_val) ( ( _val ) << 5 )

#define	AARCH32_HSR_RT_SHIFT 5

#define	AARCH32_HSR_RT_MASK 0x1e0U

#define	AARCH32_HSR_RT_GET(_reg) ( ( ( _reg ) >> 5 ) & 0xfU )

#define	AARCH32_HSR_WNR 0x40U

#define	AARCH32_HSR_S1PTW 0x80U

#define	AARCH32_HSR_CM 0x100U

#define	AARCH32_HSR_EA 0x200U

#define	AARCH32_HSR_FNV 0x400U

#define	AARCH32_HSR_AET(_val) ( ( _val ) << 10 )

#define	AARCH32_HSR_AET_SHIFT 10

#define	AARCH32_HSR_AET_MASK 0xc00U

#define	AARCH32_HSR_AET_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3U )

#define	AARCH32_HSR_CRN(_val) ( ( _val ) << 10 )

#define	AARCH32_HSR_CRN_SHIFT 10

#define	AARCH32_HSR_CRN_MASK 0x3c00U

#define	AARCH32_HSR_CRN_GET(_reg) ( ( ( _reg ) >> 10 ) & 0xfU )

#define	AARCH32_HSR_RT2(_val) ( ( _val ) << 10 )

#define	AARCH32_HSR_RT2_SHIFT 10

#define	AARCH32_HSR_RT2_MASK 0x3c00U

#define	AARCH32_HSR_RT2_GET(_reg) ( ( ( _reg ) >> 10 ) & 0xfU )

#define	AARCH32_HSR_IMM8(_val) ( ( _val ) << 12 )

#define	AARCH32_HSR_IMM8_SHIFT 12

#define	AARCH32_HSR_IMM8_MASK 0xff000U

#define	AARCH32_HSR_IMM8_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xffU )

#define	AARCH32_HSR_AR 0x4000U

#define	AARCH32_HSR_OPC1_0(_val) ( ( _val ) << 14 )

#define	AARCH32_HSR_OPC1_SHIFT_0 14

#define	AARCH32_HSR_OPC1_MASK_0 0x1c000U

#define	AARCH32_HSR_OPC1_GET_0(_reg) ( ( ( _reg ) >> 14 ) & 0x7U )

#define	AARCH32_HSR_OPC1_1(_val) ( ( _val ) << 16 )

#define	AARCH32_HSR_OPC1_SHIFT_1 16

#define	AARCH32_HSR_OPC1_MASK_1 0xf0000U

#define	AARCH32_HSR_OPC1_GET_1(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_HSR_SRT(_val) ( ( _val ) << 16 )

#define	AARCH32_HSR_SRT_SHIFT 16

#define	AARCH32_HSR_SRT_MASK 0xf0000U

#define	AARCH32_HSR_SRT_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_HSR_OPC2(_val) ( ( _val ) << 17 )

#define	AARCH32_HSR_OPC2_SHIFT 17

#define	AARCH32_HSR_OPC2_MASK 0xe0000U

#define	AARCH32_HSR_OPC2_GET(_reg) ( ( ( _reg ) >> 17 ) & 0x7U )

#define	AARCH32_HSR_CCKNOWNPASS 0x80000U

#define	AARCH32_HSR_COND(_val) ( ( _val ) << 20 )

#define	AARCH32_HSR_COND_SHIFT 20

#define	AARCH32_HSR_COND_MASK 0xf00000U

#define	AARCH32_HSR_COND_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_HSR_SSE 0x200000U

#define	AARCH32_HSR_SAS(_val) ( ( _val ) << 22 )

#define	AARCH32_HSR_SAS_SHIFT 22

#define	AARCH32_HSR_SAS_MASK 0xc00000U

#define	AARCH32_HSR_SAS_GET(_reg) ( ( ( _reg ) >> 22 ) & 0x3U )

#define	AARCH32_HSR_CV 0x1000000U

#define	AARCH32_HSR_ISV 0x1000000U

#define	AARCH32_HSR_IL 0x2000000U

#define	AARCH32_HSR_EC(_val) ( ( _val ) << 26 )

#define	AARCH32_HSR_EC_SHIFT 26

#define	AARCH32_HSR_EC_MASK 0xfc000000U

#define	AARCH32_HSR_EC_GET(_reg) ( ( ( _reg ) >> 26 ) & 0x3fU )

#define	AARCH32_HTCR_T0SZ(_val) ( ( _val ) << 0 )

#define	AARCH32_HTCR_T0SZ_SHIFT 0

#define	AARCH32_HTCR_T0SZ_MASK 0x7U

#define	AARCH32_HTCR_T0SZ_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x7U )

#define	AARCH32_HTCR_IRGN0(_val) ( ( _val ) << 8 )

#define	AARCH32_HTCR_IRGN0_SHIFT 8

#define	AARCH32_HTCR_IRGN0_MASK 0x300U

#define	AARCH32_HTCR_IRGN0_GET(_reg) ( ( ( _reg ) >> 8 ) & 0x3U )

#define	AARCH32_HTCR_ORGN0(_val) ( ( _val ) << 10 )

#define	AARCH32_HTCR_ORGN0_SHIFT 10

#define	AARCH32_HTCR_ORGN0_MASK 0xc00U

#define	AARCH32_HTCR_ORGN0_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3U )

#define	AARCH32_HTCR_SH0(_val) ( ( _val ) << 12 )

#define	AARCH32_HTCR_SH0_SHIFT 12

#define	AARCH32_HTCR_SH0_MASK 0x3000U

#define	AARCH32_HTCR_SH0_GET(_reg) ( ( ( _reg ) >> 12 ) & 0x3U )

#define	AARCH32_HTCR_HPD 0x1000000U

#define	AARCH32_HTCR_HWU59 0x2000000U

#define	AARCH32_HTCR_HWU60 0x4000000U

#define	AARCH32_HTCR_HWU61 0x8000000U

#define	AARCH32_HTCR_HWU62 0x10000000U

#define	AARCH32_HTTBR_CNP 0x1U

#define	AARCH32_HTTBR_BADDR(_val) ( ( _val ) << 1 )

#define	AARCH32_HTTBR_BADDR_SHIFT 1

#define	AARCH32_HTTBR_BADDR_MASK 0xfffffffffffeULL

#define	AARCH32_HTTBR_BADDR_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL )

#define	AARCH32_ID_DFR0_COPDBG(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_DFR0_COPDBG_SHIFT 0

#define	AARCH32_ID_DFR0_COPDBG_MASK 0xfU

#define	AARCH32_ID_DFR0_COPDBG_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_DFR0_COPSDBG(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_DFR0_COPSDBG_SHIFT 4

#define	AARCH32_ID_DFR0_COPSDBG_MASK 0xf0U

#define	AARCH32_ID_DFR0_COPSDBG_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_DFR0_MMAPDBG(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_DFR0_MMAPDBG_SHIFT 8

#define	AARCH32_ID_DFR0_MMAPDBG_MASK 0xf00U

#define	AARCH32_ID_DFR0_MMAPDBG_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_ID_DFR0_COPTRC(_val) ( ( _val ) << 12 )

#define	AARCH32_ID_DFR0_COPTRC_SHIFT 12

#define	AARCH32_ID_DFR0_COPTRC_MASK 0xf000U

#define	AARCH32_ID_DFR0_COPTRC_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_ID_DFR0_MMAPTRC(_val) ( ( _val ) << 16 )

#define	AARCH32_ID_DFR0_MMAPTRC_SHIFT 16

#define	AARCH32_ID_DFR0_MMAPTRC_MASK 0xf0000U

#define	AARCH32_ID_DFR0_MMAPTRC_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_ID_DFR0_MPROFDBG(_val) ( ( _val ) << 20 )

#define	AARCH32_ID_DFR0_MPROFDBG_SHIFT 20

#define	AARCH32_ID_DFR0_MPROFDBG_MASK 0xf00000U

#define	AARCH32_ID_DFR0_MPROFDBG_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_ID_DFR0_PERFMON(_val) ( ( _val ) << 24 )

#define	AARCH32_ID_DFR0_PERFMON_SHIFT 24

#define	AARCH32_ID_DFR0_PERFMON_MASK 0xf000000U

#define	AARCH32_ID_DFR0_PERFMON_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_ID_DFR0_TRACEFILT(_val) ( ( _val ) << 28 )

#define	AARCH32_ID_DFR0_TRACEFILT_SHIFT 28

#define	AARCH32_ID_DFR0_TRACEFILT_MASK 0xf0000000U

#define	AARCH32_ID_DFR0_TRACEFILT_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_ID_DFR1_MTPMU(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_DFR1_MTPMU_SHIFT 0

#define	AARCH32_ID_DFR1_MTPMU_MASK 0xfU

#define	AARCH32_ID_DFR1_MTPMU_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_ISAR0_SWAP(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_ISAR0_SWAP_SHIFT 0

#define	AARCH32_ID_ISAR0_SWAP_MASK 0xfU

#define	AARCH32_ID_ISAR0_SWAP_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_ISAR0_BITCOUNT(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_ISAR0_BITCOUNT_SHIFT 4

#define	AARCH32_ID_ISAR0_BITCOUNT_MASK 0xf0U

#define	AARCH32_ID_ISAR0_BITCOUNT_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_ISAR0_BITFIELD(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_ISAR0_BITFIELD_SHIFT 8

#define	AARCH32_ID_ISAR0_BITFIELD_MASK 0xf00U

#define	AARCH32_ID_ISAR0_BITFIELD_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_ID_ISAR0_CMPBRANCH(_val) ( ( _val ) << 12 )

#define	AARCH32_ID_ISAR0_CMPBRANCH_SHIFT 12

#define	AARCH32_ID_ISAR0_CMPBRANCH_MASK 0xf000U

#define	AARCH32_ID_ISAR0_CMPBRANCH_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_ID_ISAR0_COPROC(_val) ( ( _val ) << 16 )

#define	AARCH32_ID_ISAR0_COPROC_SHIFT 16

#define	AARCH32_ID_ISAR0_COPROC_MASK 0xf0000U

#define	AARCH32_ID_ISAR0_COPROC_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_ID_ISAR0_DEBUG(_val) ( ( _val ) << 20 )

#define	AARCH32_ID_ISAR0_DEBUG_SHIFT 20

#define	AARCH32_ID_ISAR0_DEBUG_MASK 0xf00000U

#define	AARCH32_ID_ISAR0_DEBUG_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_ID_ISAR0_DIVIDE(_val) ( ( _val ) << 24 )

#define	AARCH32_ID_ISAR0_DIVIDE_SHIFT 24

#define	AARCH32_ID_ISAR0_DIVIDE_MASK 0xf000000U

#define	AARCH32_ID_ISAR0_DIVIDE_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_ID_ISAR1_ENDIAN(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_ISAR1_ENDIAN_SHIFT 0

#define	AARCH32_ID_ISAR1_ENDIAN_MASK 0xfU

#define	AARCH32_ID_ISAR1_ENDIAN_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_ISAR1_EXCEPT(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_ISAR1_EXCEPT_SHIFT 4

#define	AARCH32_ID_ISAR1_EXCEPT_MASK 0xf0U

#define	AARCH32_ID_ISAR1_EXCEPT_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_ISAR1_EXCEPT_AR(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_ISAR1_EXCEPT_AR_SHIFT 8

#define	AARCH32_ID_ISAR1_EXCEPT_AR_MASK 0xf00U

#define	AARCH32_ID_ISAR1_EXCEPT_AR_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_ID_ISAR1_EXTEND(_val) ( ( _val ) << 12 )

#define	AARCH32_ID_ISAR1_EXTEND_SHIFT 12

#define	AARCH32_ID_ISAR1_EXTEND_MASK 0xf000U

#define	AARCH32_ID_ISAR1_EXTEND_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_ID_ISAR1_IFTHEN(_val) ( ( _val ) << 16 )

#define	AARCH32_ID_ISAR1_IFTHEN_SHIFT 16

#define	AARCH32_ID_ISAR1_IFTHEN_MASK 0xf0000U

#define	AARCH32_ID_ISAR1_IFTHEN_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_ID_ISAR1_IMMEDIATE(_val) ( ( _val ) << 20 )

#define	AARCH32_ID_ISAR1_IMMEDIATE_SHIFT 20

#define	AARCH32_ID_ISAR1_IMMEDIATE_MASK 0xf00000U

#define	AARCH32_ID_ISAR1_IMMEDIATE_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_ID_ISAR1_INTERWORK(_val) ( ( _val ) << 24 )

#define	AARCH32_ID_ISAR1_INTERWORK_SHIFT 24

#define	AARCH32_ID_ISAR1_INTERWORK_MASK 0xf000000U

#define	AARCH32_ID_ISAR1_INTERWORK_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_ID_ISAR1_JAZELLE(_val) ( ( _val ) << 28 )

#define	AARCH32_ID_ISAR1_JAZELLE_SHIFT 28

#define	AARCH32_ID_ISAR1_JAZELLE_MASK 0xf0000000U

#define	AARCH32_ID_ISAR1_JAZELLE_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_ID_ISAR2_LOADSTORE(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_ISAR2_LOADSTORE_SHIFT 0

#define	AARCH32_ID_ISAR2_LOADSTORE_MASK 0xfU

#define	AARCH32_ID_ISAR2_LOADSTORE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_ISAR2_MEMHINT(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_ISAR2_MEMHINT_SHIFT 4

#define	AARCH32_ID_ISAR2_MEMHINT_MASK 0xf0U

#define	AARCH32_ID_ISAR2_MEMHINT_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_ISAR2_MULTIACCESSINT(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_ISAR2_MULTIACCESSINT_SHIFT 8

#define	AARCH32_ID_ISAR2_MULTIACCESSINT_MASK 0xf00U

#define	AARCH32_ID_ISAR2_MULTIACCESSINT_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_ID_ISAR2_MULT(_val) ( ( _val ) << 12 )

#define	AARCH32_ID_ISAR2_MULT_SHIFT 12

#define	AARCH32_ID_ISAR2_MULT_MASK 0xf000U

#define	AARCH32_ID_ISAR2_MULT_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_ID_ISAR2_MULTS(_val) ( ( _val ) << 16 )

#define	AARCH32_ID_ISAR2_MULTS_SHIFT 16

#define	AARCH32_ID_ISAR2_MULTS_MASK 0xf0000U

#define	AARCH32_ID_ISAR2_MULTS_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_ID_ISAR2_MULTU(_val) ( ( _val ) << 20 )

#define	AARCH32_ID_ISAR2_MULTU_SHIFT 20

#define	AARCH32_ID_ISAR2_MULTU_MASK 0xf00000U

#define	AARCH32_ID_ISAR2_MULTU_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_ID_ISAR2_PSR_AR(_val) ( ( _val ) << 24 )

#define	AARCH32_ID_ISAR2_PSR_AR_SHIFT 24

#define	AARCH32_ID_ISAR2_PSR_AR_MASK 0xf000000U

#define	AARCH32_ID_ISAR2_PSR_AR_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_ID_ISAR2_REVERSAL(_val) ( ( _val ) << 28 )

#define	AARCH32_ID_ISAR2_REVERSAL_SHIFT 28

#define	AARCH32_ID_ISAR2_REVERSAL_MASK 0xf0000000U

#define	AARCH32_ID_ISAR2_REVERSAL_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_ID_ISAR3_SATURATE(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_ISAR3_SATURATE_SHIFT 0

#define	AARCH32_ID_ISAR3_SATURATE_MASK 0xfU

#define	AARCH32_ID_ISAR3_SATURATE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_ISAR3_SIMD(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_ISAR3_SIMD_SHIFT 4

#define	AARCH32_ID_ISAR3_SIMD_MASK 0xf0U

#define	AARCH32_ID_ISAR3_SIMD_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_ISAR3_SVC(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_ISAR3_SVC_SHIFT 8

#define	AARCH32_ID_ISAR3_SVC_MASK 0xf00U

#define	AARCH32_ID_ISAR3_SVC_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_ID_ISAR3_SYNCHPRIM(_val) ( ( _val ) << 12 )

#define	AARCH32_ID_ISAR3_SYNCHPRIM_SHIFT 12

#define	AARCH32_ID_ISAR3_SYNCHPRIM_MASK 0xf000U

#define	AARCH32_ID_ISAR3_SYNCHPRIM_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_ID_ISAR3_TABBRANCH(_val) ( ( _val ) << 16 )

#define	AARCH32_ID_ISAR3_TABBRANCH_SHIFT 16

#define	AARCH32_ID_ISAR3_TABBRANCH_MASK 0xf0000U

#define	AARCH32_ID_ISAR3_TABBRANCH_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_ID_ISAR3_T32COPY(_val) ( ( _val ) << 20 )

#define	AARCH32_ID_ISAR3_T32COPY_SHIFT 20

#define	AARCH32_ID_ISAR3_T32COPY_MASK 0xf00000U

#define	AARCH32_ID_ISAR3_T32COPY_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_ID_ISAR3_TRUENOP(_val) ( ( _val ) << 24 )

#define	AARCH32_ID_ISAR3_TRUENOP_SHIFT 24

#define	AARCH32_ID_ISAR3_TRUENOP_MASK 0xf000000U

#define	AARCH32_ID_ISAR3_TRUENOP_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_ID_ISAR3_T32EE(_val) ( ( _val ) << 28 )

#define	AARCH32_ID_ISAR3_T32EE_SHIFT 28

#define	AARCH32_ID_ISAR3_T32EE_MASK 0xf0000000U

#define	AARCH32_ID_ISAR3_T32EE_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_ID_ISAR4_UNPRIV(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_ISAR4_UNPRIV_SHIFT 0

#define	AARCH32_ID_ISAR4_UNPRIV_MASK 0xfU

#define	AARCH32_ID_ISAR4_UNPRIV_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_ISAR4_WITHSHIFTS(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_ISAR4_WITHSHIFTS_SHIFT 4

#define	AARCH32_ID_ISAR4_WITHSHIFTS_MASK 0xf0U

#define	AARCH32_ID_ISAR4_WITHSHIFTS_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_ISAR4_WRITEBACK(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_ISAR4_WRITEBACK_SHIFT 8

#define	AARCH32_ID_ISAR4_WRITEBACK_MASK 0xf00U

#define	AARCH32_ID_ISAR4_WRITEBACK_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_ID_ISAR4_SMC(_val) ( ( _val ) << 12 )

#define	AARCH32_ID_ISAR4_SMC_SHIFT 12

#define	AARCH32_ID_ISAR4_SMC_MASK 0xf000U

#define	AARCH32_ID_ISAR4_SMC_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_ID_ISAR4_BARRIER(_val) ( ( _val ) << 16 )

#define	AARCH32_ID_ISAR4_BARRIER_SHIFT 16

#define	AARCH32_ID_ISAR4_BARRIER_MASK 0xf0000U

#define	AARCH32_ID_ISAR4_BARRIER_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_ID_ISAR4_SYNCHPRIM_FRAC(_val) ( ( _val ) << 20 )

#define	AARCH32_ID_ISAR4_SYNCHPRIM_FRAC_SHIFT 20

#define	AARCH32_ID_ISAR4_SYNCHPRIM_FRAC_MASK 0xf00000U

#define	AARCH32_ID_ISAR4_SYNCHPRIM_FRAC_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_ID_ISAR4_PSR_M(_val) ( ( _val ) << 24 )

#define	AARCH32_ID_ISAR4_PSR_M_SHIFT 24

#define	AARCH32_ID_ISAR4_PSR_M_MASK 0xf000000U

#define	AARCH32_ID_ISAR4_PSR_M_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_ID_ISAR4_SWP_FRAC(_val) ( ( _val ) << 28 )

#define	AARCH32_ID_ISAR4_SWP_FRAC_SHIFT 28

#define	AARCH32_ID_ISAR4_SWP_FRAC_MASK 0xf0000000U

#define	AARCH32_ID_ISAR4_SWP_FRAC_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_ID_ISAR5_SEVL(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_ISAR5_SEVL_SHIFT 0

#define	AARCH32_ID_ISAR5_SEVL_MASK 0xfU

#define	AARCH32_ID_ISAR5_SEVL_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_ISAR5_AES(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_ISAR5_AES_SHIFT 4

#define	AARCH32_ID_ISAR5_AES_MASK 0xf0U

#define	AARCH32_ID_ISAR5_AES_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_ISAR5_SHA1(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_ISAR5_SHA1_SHIFT 8

#define	AARCH32_ID_ISAR5_SHA1_MASK 0xf00U

#define	AARCH32_ID_ISAR5_SHA1_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_ID_ISAR5_SHA2(_val) ( ( _val ) << 12 )

#define	AARCH32_ID_ISAR5_SHA2_SHIFT 12

#define	AARCH32_ID_ISAR5_SHA2_MASK 0xf000U

#define	AARCH32_ID_ISAR5_SHA2_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_ID_ISAR5_CRC32(_val) ( ( _val ) << 16 )

#define	AARCH32_ID_ISAR5_CRC32_SHIFT 16

#define	AARCH32_ID_ISAR5_CRC32_MASK 0xf0000U

#define	AARCH32_ID_ISAR5_CRC32_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_ID_ISAR5_RDM(_val) ( ( _val ) << 24 )

#define	AARCH32_ID_ISAR5_RDM_SHIFT 24

#define	AARCH32_ID_ISAR5_RDM_MASK 0xf000000U

#define	AARCH32_ID_ISAR5_RDM_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_ID_ISAR5_VCMA(_val) ( ( _val ) << 28 )

#define	AARCH32_ID_ISAR5_VCMA_SHIFT 28

#define	AARCH32_ID_ISAR5_VCMA_MASK 0xf0000000U

#define	AARCH32_ID_ISAR5_VCMA_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_ID_ISAR6_JSCVT(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_ISAR6_JSCVT_SHIFT 0

#define	AARCH32_ID_ISAR6_JSCVT_MASK 0xfU

#define	AARCH32_ID_ISAR6_JSCVT_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_ISAR6_DP(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_ISAR6_DP_SHIFT 4

#define	AARCH32_ID_ISAR6_DP_MASK 0xf0U

#define	AARCH32_ID_ISAR6_DP_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_ISAR6_FHM(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_ISAR6_FHM_SHIFT 8

#define	AARCH32_ID_ISAR6_FHM_MASK 0xf00U

#define	AARCH32_ID_ISAR6_FHM_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_ID_ISAR6_SB(_val) ( ( _val ) << 12 )

#define	AARCH32_ID_ISAR6_SB_SHIFT 12

#define	AARCH32_ID_ISAR6_SB_MASK 0xf000U

#define	AARCH32_ID_ISAR6_SB_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_ID_ISAR6_SPECRES(_val) ( ( _val ) << 16 )

#define	AARCH32_ID_ISAR6_SPECRES_SHIFT 16

#define	AARCH32_ID_ISAR6_SPECRES_MASK 0xf0000U

#define	AARCH32_ID_ISAR6_SPECRES_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_ID_ISAR6_BF16(_val) ( ( _val ) << 20 )

#define	AARCH32_ID_ISAR6_BF16_SHIFT 20

#define	AARCH32_ID_ISAR6_BF16_MASK 0xf00000U

#define	AARCH32_ID_ISAR6_BF16_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_ID_ISAR6_I8MM(_val) ( ( _val ) << 24 )

#define	AARCH32_ID_ISAR6_I8MM_SHIFT 24

#define	AARCH32_ID_ISAR6_I8MM_MASK 0xf000000U

#define	AARCH32_ID_ISAR6_I8MM_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_ID_MMFR0_VMSA(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_MMFR0_VMSA_SHIFT 0

#define	AARCH32_ID_MMFR0_VMSA_MASK 0xfU

#define	AARCH32_ID_MMFR0_VMSA_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_MMFR0_PMSA(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_MMFR0_PMSA_SHIFT 4

#define	AARCH32_ID_MMFR0_PMSA_MASK 0xf0U

#define	AARCH32_ID_MMFR0_PMSA_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_MMFR0_OUTERSHR(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_MMFR0_OUTERSHR_SHIFT 8

#define	AARCH32_ID_MMFR0_OUTERSHR_MASK 0xf00U

#define	AARCH32_ID_MMFR0_OUTERSHR_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_ID_MMFR0_SHARELVL(_val) ( ( _val ) << 12 )

#define	AARCH32_ID_MMFR0_SHARELVL_SHIFT 12

#define	AARCH32_ID_MMFR0_SHARELVL_MASK 0xf000U

#define	AARCH32_ID_MMFR0_SHARELVL_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_ID_MMFR0_TCM(_val) ( ( _val ) << 16 )

#define	AARCH32_ID_MMFR0_TCM_SHIFT 16

#define	AARCH32_ID_MMFR0_TCM_MASK 0xf0000U

#define	AARCH32_ID_MMFR0_TCM_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_ID_MMFR0_AUXREG(_val) ( ( _val ) << 20 )

#define	AARCH32_ID_MMFR0_AUXREG_SHIFT 20

#define	AARCH32_ID_MMFR0_AUXREG_MASK 0xf00000U

#define	AARCH32_ID_MMFR0_AUXREG_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_ID_MMFR0_FCSE(_val) ( ( _val ) << 24 )

#define	AARCH32_ID_MMFR0_FCSE_SHIFT 24

#define	AARCH32_ID_MMFR0_FCSE_MASK 0xf000000U

#define	AARCH32_ID_MMFR0_FCSE_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_ID_MMFR0_INNERSHR(_val) ( ( _val ) << 28 )

#define	AARCH32_ID_MMFR0_INNERSHR_SHIFT 28

#define	AARCH32_ID_MMFR0_INNERSHR_MASK 0xf0000000U

#define	AARCH32_ID_MMFR0_INNERSHR_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_ID_MMFR1_L1HVDVA(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_MMFR1_L1HVDVA_SHIFT 0

#define	AARCH32_ID_MMFR1_L1HVDVA_MASK 0xfU

#define	AARCH32_ID_MMFR1_L1HVDVA_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_MMFR1_L1UNIVA(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_MMFR1_L1UNIVA_SHIFT 4

#define	AARCH32_ID_MMFR1_L1UNIVA_MASK 0xf0U

#define	AARCH32_ID_MMFR1_L1UNIVA_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_MMFR1_L1HVDSW(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_MMFR1_L1HVDSW_SHIFT 8

#define	AARCH32_ID_MMFR1_L1HVDSW_MASK 0xf00U

#define	AARCH32_ID_MMFR1_L1HVDSW_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_ID_MMFR1_L1UNISW(_val) ( ( _val ) << 12 )

#define	AARCH32_ID_MMFR1_L1UNISW_SHIFT 12

#define	AARCH32_ID_MMFR1_L1UNISW_MASK 0xf000U

#define	AARCH32_ID_MMFR1_L1UNISW_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_ID_MMFR1_L1HVD(_val) ( ( _val ) << 16 )

#define	AARCH32_ID_MMFR1_L1HVD_SHIFT 16

#define	AARCH32_ID_MMFR1_L1HVD_MASK 0xf0000U

#define	AARCH32_ID_MMFR1_L1HVD_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_ID_MMFR1_L1UNI(_val) ( ( _val ) << 20 )

#define	AARCH32_ID_MMFR1_L1UNI_SHIFT 20

#define	AARCH32_ID_MMFR1_L1UNI_MASK 0xf00000U

#define	AARCH32_ID_MMFR1_L1UNI_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_ID_MMFR1_L1TSTCLN(_val) ( ( _val ) << 24 )

#define	AARCH32_ID_MMFR1_L1TSTCLN_SHIFT 24

#define	AARCH32_ID_MMFR1_L1TSTCLN_MASK 0xf000000U

#define	AARCH32_ID_MMFR1_L1TSTCLN_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_ID_MMFR1_BPRED(_val) ( ( _val ) << 28 )

#define	AARCH32_ID_MMFR1_BPRED_SHIFT 28

#define	AARCH32_ID_MMFR1_BPRED_MASK 0xf0000000U

#define	AARCH32_ID_MMFR1_BPRED_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_ID_MMFR2_L1HVDFG(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_MMFR2_L1HVDFG_SHIFT 0

#define	AARCH32_ID_MMFR2_L1HVDFG_MASK 0xfU

#define	AARCH32_ID_MMFR2_L1HVDFG_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_MMFR2_L1HVDBG(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_MMFR2_L1HVDBG_SHIFT 4

#define	AARCH32_ID_MMFR2_L1HVDBG_MASK 0xf0U

#define	AARCH32_ID_MMFR2_L1HVDBG_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_MMFR2_L1HVDRNG(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_MMFR2_L1HVDRNG_SHIFT 8

#define	AARCH32_ID_MMFR2_L1HVDRNG_MASK 0xf00U

#define	AARCH32_ID_MMFR2_L1HVDRNG_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_ID_MMFR2_HVDTLB(_val) ( ( _val ) << 12 )

#define	AARCH32_ID_MMFR2_HVDTLB_SHIFT 12

#define	AARCH32_ID_MMFR2_HVDTLB_MASK 0xf000U

#define	AARCH32_ID_MMFR2_HVDTLB_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_ID_MMFR2_UNITLB(_val) ( ( _val ) << 16 )

#define	AARCH32_ID_MMFR2_UNITLB_SHIFT 16

#define	AARCH32_ID_MMFR2_UNITLB_MASK 0xf0000U

#define	AARCH32_ID_MMFR2_UNITLB_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_ID_MMFR2_MEMBARR(_val) ( ( _val ) << 20 )

#define	AARCH32_ID_MMFR2_MEMBARR_SHIFT 20

#define	AARCH32_ID_MMFR2_MEMBARR_MASK 0xf00000U

#define	AARCH32_ID_MMFR2_MEMBARR_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_ID_MMFR2_WFISTALL(_val) ( ( _val ) << 24 )

#define	AARCH32_ID_MMFR2_WFISTALL_SHIFT 24

#define	AARCH32_ID_MMFR2_WFISTALL_MASK 0xf000000U

#define	AARCH32_ID_MMFR2_WFISTALL_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_ID_MMFR2_HWACCFLG(_val) ( ( _val ) << 28 )

#define	AARCH32_ID_MMFR2_HWACCFLG_SHIFT 28

#define	AARCH32_ID_MMFR2_HWACCFLG_MASK 0xf0000000U

#define	AARCH32_ID_MMFR2_HWACCFLG_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_ID_MMFR3_CMAINTVA(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_MMFR3_CMAINTVA_SHIFT 0

#define	AARCH32_ID_MMFR3_CMAINTVA_MASK 0xfU

#define	AARCH32_ID_MMFR3_CMAINTVA_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_MMFR3_CMAINTSW(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_MMFR3_CMAINTSW_SHIFT 4

#define	AARCH32_ID_MMFR3_CMAINTSW_MASK 0xf0U

#define	AARCH32_ID_MMFR3_CMAINTSW_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_MMFR3_BPMAINT(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_MMFR3_BPMAINT_SHIFT 8

#define	AARCH32_ID_MMFR3_BPMAINT_MASK 0xf00U

#define	AARCH32_ID_MMFR3_BPMAINT_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_ID_MMFR3_MAINTBCST(_val) ( ( _val ) << 12 )

#define	AARCH32_ID_MMFR3_MAINTBCST_SHIFT 12

#define	AARCH32_ID_MMFR3_MAINTBCST_MASK 0xf000U

#define	AARCH32_ID_MMFR3_MAINTBCST_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_ID_MMFR3_PAN(_val) ( ( _val ) << 16 )

#define	AARCH32_ID_MMFR3_PAN_SHIFT 16

#define	AARCH32_ID_MMFR3_PAN_MASK 0xf0000U

#define	AARCH32_ID_MMFR3_PAN_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_ID_MMFR3_COHWALK(_val) ( ( _val ) << 20 )

#define	AARCH32_ID_MMFR3_COHWALK_SHIFT 20

#define	AARCH32_ID_MMFR3_COHWALK_MASK 0xf00000U

#define	AARCH32_ID_MMFR3_COHWALK_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_ID_MMFR3_CMEMSZ(_val) ( ( _val ) << 24 )

#define	AARCH32_ID_MMFR3_CMEMSZ_SHIFT 24

#define	AARCH32_ID_MMFR3_CMEMSZ_MASK 0xf000000U

#define	AARCH32_ID_MMFR3_CMEMSZ_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_ID_MMFR3_SUPERSEC(_val) ( ( _val ) << 28 )

#define	AARCH32_ID_MMFR3_SUPERSEC_SHIFT 28

#define	AARCH32_ID_MMFR3_SUPERSEC_MASK 0xf0000000U

#define	AARCH32_ID_MMFR3_SUPERSEC_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_ID_MMFR4_SPECSEI(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_MMFR4_SPECSEI_SHIFT 0

#define	AARCH32_ID_MMFR4_SPECSEI_MASK 0xfU

#define	AARCH32_ID_MMFR4_SPECSEI_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_MMFR4_AC2(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_MMFR4_AC2_SHIFT 4

#define	AARCH32_ID_MMFR4_AC2_MASK 0xf0U

#define	AARCH32_ID_MMFR4_AC2_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_MMFR4_XNX(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_MMFR4_XNX_SHIFT 8

#define	AARCH32_ID_MMFR4_XNX_MASK 0xf00U

#define	AARCH32_ID_MMFR4_XNX_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_ID_MMFR4_CNP(_val) ( ( _val ) << 12 )

#define	AARCH32_ID_MMFR4_CNP_SHIFT 12

#define	AARCH32_ID_MMFR4_CNP_MASK 0xf000U

#define	AARCH32_ID_MMFR4_CNP_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_ID_MMFR4_HPDS(_val) ( ( _val ) << 16 )

#define	AARCH32_ID_MMFR4_HPDS_SHIFT 16

#define	AARCH32_ID_MMFR4_HPDS_MASK 0xf0000U

#define	AARCH32_ID_MMFR4_HPDS_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_ID_MMFR4_LSM(_val) ( ( _val ) << 20 )

#define	AARCH32_ID_MMFR4_LSM_SHIFT 20

#define	AARCH32_ID_MMFR4_LSM_MASK 0xf00000U

#define	AARCH32_ID_MMFR4_LSM_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_ID_MMFR4_CCIDX(_val) ( ( _val ) << 24 )

#define	AARCH32_ID_MMFR4_CCIDX_SHIFT 24

#define	AARCH32_ID_MMFR4_CCIDX_MASK 0xf000000U

#define	AARCH32_ID_MMFR4_CCIDX_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_ID_MMFR4_EVT(_val) ( ( _val ) << 28 )

#define	AARCH32_ID_MMFR4_EVT_SHIFT 28

#define	AARCH32_ID_MMFR4_EVT_MASK 0xf0000000U

#define	AARCH32_ID_MMFR4_EVT_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_ID_MMFR5_ETS(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_MMFR5_ETS_SHIFT 0

#define	AARCH32_ID_MMFR5_ETS_MASK 0xfU

#define	AARCH32_ID_MMFR5_ETS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_PFR0_STATE0(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_PFR0_STATE0_SHIFT 0

#define	AARCH32_ID_PFR0_STATE0_MASK 0xfU

#define	AARCH32_ID_PFR0_STATE0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_PFR0_STATE1(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_PFR0_STATE1_SHIFT 4

#define	AARCH32_ID_PFR0_STATE1_MASK 0xf0U

#define	AARCH32_ID_PFR0_STATE1_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_PFR0_STATE2(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_PFR0_STATE2_SHIFT 8

#define	AARCH32_ID_PFR0_STATE2_MASK 0xf00U

#define	AARCH32_ID_PFR0_STATE2_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_ID_PFR0_STATE3(_val) ( ( _val ) << 12 )

#define	AARCH32_ID_PFR0_STATE3_SHIFT 12

#define	AARCH32_ID_PFR0_STATE3_MASK 0xf000U

#define	AARCH32_ID_PFR0_STATE3_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_ID_PFR0_CSV2(_val) ( ( _val ) << 16 )

#define	AARCH32_ID_PFR0_CSV2_SHIFT 16

#define	AARCH32_ID_PFR0_CSV2_MASK 0xf0000U

#define	AARCH32_ID_PFR0_CSV2_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_ID_PFR0_AMU(_val) ( ( _val ) << 20 )

#define	AARCH32_ID_PFR0_AMU_SHIFT 20

#define	AARCH32_ID_PFR0_AMU_MASK 0xf00000U

#define	AARCH32_ID_PFR0_AMU_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_ID_PFR0_DIT(_val) ( ( _val ) << 24 )

#define	AARCH32_ID_PFR0_DIT_SHIFT 24

#define	AARCH32_ID_PFR0_DIT_MASK 0xf000000U

#define	AARCH32_ID_PFR0_DIT_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_ID_PFR0_RAS(_val) ( ( _val ) << 28 )

#define	AARCH32_ID_PFR0_RAS_SHIFT 28

#define	AARCH32_ID_PFR0_RAS_MASK 0xf0000000U

#define	AARCH32_ID_PFR0_RAS_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_ID_PFR1_PROGMOD(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_PFR1_PROGMOD_SHIFT 0

#define	AARCH32_ID_PFR1_PROGMOD_MASK 0xfU

#define	AARCH32_ID_PFR1_PROGMOD_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_PFR1_SECURITY(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_PFR1_SECURITY_SHIFT 4

#define	AARCH32_ID_PFR1_SECURITY_MASK 0xf0U

#define	AARCH32_ID_PFR1_SECURITY_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_PFR1_MPROGMOD(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_PFR1_MPROGMOD_SHIFT 8

#define	AARCH32_ID_PFR1_MPROGMOD_MASK 0xf00U

#define	AARCH32_ID_PFR1_MPROGMOD_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_ID_PFR1_VIRTUALIZATION(_val) ( ( _val ) << 12 )

#define	AARCH32_ID_PFR1_VIRTUALIZATION_SHIFT 12

#define	AARCH32_ID_PFR1_VIRTUALIZATION_MASK 0xf000U

#define	AARCH32_ID_PFR1_VIRTUALIZATION_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_ID_PFR1_GENTIMER(_val) ( ( _val ) << 16 )

#define	AARCH32_ID_PFR1_GENTIMER_SHIFT 16

#define	AARCH32_ID_PFR1_GENTIMER_MASK 0xf0000U

#define	AARCH32_ID_PFR1_GENTIMER_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_ID_PFR1_SEC_FRAC(_val) ( ( _val ) << 20 )

#define	AARCH32_ID_PFR1_SEC_FRAC_SHIFT 20

#define	AARCH32_ID_PFR1_SEC_FRAC_MASK 0xf00000U

#define	AARCH32_ID_PFR1_SEC_FRAC_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_ID_PFR1_VIRT_FRAC(_val) ( ( _val ) << 24 )

#define	AARCH32_ID_PFR1_VIRT_FRAC_SHIFT 24

#define	AARCH32_ID_PFR1_VIRT_FRAC_MASK 0xf000000U

#define	AARCH32_ID_PFR1_VIRT_FRAC_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_ID_PFR1_GIC(_val) ( ( _val ) << 28 )

#define	AARCH32_ID_PFR1_GIC_SHIFT 28

#define	AARCH32_ID_PFR1_GIC_MASK 0xf0000000U

#define	AARCH32_ID_PFR1_GIC_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_ID_PFR2_CSV3(_val) ( ( _val ) << 0 )

#define	AARCH32_ID_PFR2_CSV3_SHIFT 0

#define	AARCH32_ID_PFR2_CSV3_MASK 0xfU

#define	AARCH32_ID_PFR2_CSV3_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_ID_PFR2_SSBS(_val) ( ( _val ) << 4 )

#define	AARCH32_ID_PFR2_SSBS_SHIFT 4

#define	AARCH32_ID_PFR2_SSBS_MASK 0xf0U

#define	AARCH32_ID_PFR2_SSBS_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_ID_PFR2_RAS_FRAC(_val) ( ( _val ) << 8 )

#define	AARCH32_ID_PFR2_RAS_FRAC_SHIFT 8

#define	AARCH32_ID_PFR2_RAS_FRAC_MASK 0xf00U

#define	AARCH32_ID_PFR2_RAS_FRAC_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_IFSR_FS_3_0(_val) ( ( _val ) << 0 )

#define	AARCH32_IFSR_FS_3_0_SHIFT 0

#define	AARCH32_IFSR_FS_3_0_MASK 0xfU

#define	AARCH32_IFSR_FS_3_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_IFSR_STATUS(_val) ( ( _val ) << 0 )

#define	AARCH32_IFSR_STATUS_SHIFT 0

#define	AARCH32_IFSR_STATUS_MASK 0x3fU

#define	AARCH32_IFSR_STATUS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU )

#define	AARCH32_IFSR_LPAE 0x200U

#define	AARCH32_IFSR_FS_4 0x400U

#define	AARCH32_IFSR_EXT 0x1000U

#define	AARCH32_IFSR_FNV 0x10000U

#define	AARCH32_ISR_F 0x40U

#define	AARCH32_ISR_I 0x80U

#define	AARCH32_ISR_A 0x100U

#define	AARCH32_ITLBIASID_ASID(_val) ( ( _val ) << 0 )

#define	AARCH32_ITLBIASID_ASID_SHIFT 0

#define	AARCH32_ITLBIASID_ASID_MASK 0xffU

#define	AARCH32_ITLBIASID_ASID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_ITLBIMVA_ASID(_val) ( ( _val ) << 0 )

#define	AARCH32_ITLBIMVA_ASID_SHIFT 0

#define	AARCH32_ITLBIMVA_ASID_MASK 0xffU

#define	AARCH32_ITLBIMVA_ASID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_ITLBIMVA_VA(_val) ( ( _val ) << 12 )

#define	AARCH32_ITLBIMVA_VA_SHIFT 12

#define	AARCH32_ITLBIMVA_VA_MASK 0xfffff000U

#define	AARCH32_ITLBIMVA_VA_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffU )

#define	AARCH32_MIDR_REVISION(_val) ( ( _val ) << 0 )

#define	AARCH32_MIDR_REVISION_SHIFT 0

#define	AARCH32_MIDR_REVISION_MASK 0xfU

#define	AARCH32_MIDR_REVISION_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_MIDR_PARTNUM(_val) ( ( _val ) << 4 )

#define	AARCH32_MIDR_PARTNUM_SHIFT 4

#define	AARCH32_MIDR_PARTNUM_MASK 0xfff0U

#define	AARCH32_MIDR_PARTNUM_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfffU )

#define	AARCH32_MIDR_ARCHITECTURE(_val) ( ( _val ) << 16 )

#define	AARCH32_MIDR_ARCHITECTURE_SHIFT 16

#define	AARCH32_MIDR_ARCHITECTURE_MASK 0xf0000U

#define	AARCH32_MIDR_ARCHITECTURE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_MIDR_VARIANT(_val) ( ( _val ) << 20 )

#define	AARCH32_MIDR_VARIANT_SHIFT 20

#define	AARCH32_MIDR_VARIANT_MASK 0xf00000U

#define	AARCH32_MIDR_VARIANT_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_MIDR_IMPLEMENTER(_val) ( ( _val ) << 24 )

#define	AARCH32_MIDR_IMPLEMENTER_SHIFT 24

#define	AARCH32_MIDR_IMPLEMENTER_MASK 0xff000000U

#define	AARCH32_MIDR_IMPLEMENTER_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xffU )

#define	AARCH32_MPIDR_AFF0(_val) ( ( _val ) << 0 )

#define	AARCH32_MPIDR_AFF0_SHIFT 0

#define	AARCH32_MPIDR_AFF0_MASK 0xffU

#define	AARCH32_MPIDR_AFF0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_MPIDR_AFF1(_val) ( ( _val ) << 8 )

#define	AARCH32_MPIDR_AFF1_SHIFT 8

#define	AARCH32_MPIDR_AFF1_MASK 0xff00U

#define	AARCH32_MPIDR_AFF1_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xffU )

#define	AARCH32_MPIDR_AFF2(_val) ( ( _val ) << 16 )

#define	AARCH32_MPIDR_AFF2_SHIFT 16

#define	AARCH32_MPIDR_AFF2_MASK 0xff0000U

#define	AARCH32_MPIDR_AFF2_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xffU )

#define	AARCH32_MPIDR_MT 0x1000000U

#define	AARCH32_MPIDR_U 0x40000000U

#define	AARCH32_MPIDR_M 0x80000000U

#define	AARCH32_MVBAR_RESERVED(_val) ( ( _val ) << 0 )

#define	AARCH32_MVBAR_RESERVED_SHIFT 0

#define	AARCH32_MVBAR_RESERVED_MASK 0x1fU

#define	AARCH32_MVBAR_RESERVED_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1fU )

#define	AARCH32_MVFR0_SIMDREG(_val) ( ( _val ) << 0 )

#define	AARCH32_MVFR0_SIMDREG_SHIFT 0

#define	AARCH32_MVFR0_SIMDREG_MASK 0xfU

#define	AARCH32_MVFR0_SIMDREG_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_MVFR0_FPSP(_val) ( ( _val ) << 4 )

#define	AARCH32_MVFR0_FPSP_SHIFT 4

#define	AARCH32_MVFR0_FPSP_MASK 0xf0U

#define	AARCH32_MVFR0_FPSP_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_MVFR0_FPDP(_val) ( ( _val ) << 8 )

#define	AARCH32_MVFR0_FPDP_SHIFT 8

#define	AARCH32_MVFR0_FPDP_MASK 0xf00U

#define	AARCH32_MVFR0_FPDP_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_MVFR0_FPTRAP(_val) ( ( _val ) << 12 )

#define	AARCH32_MVFR0_FPTRAP_SHIFT 12

#define	AARCH32_MVFR0_FPTRAP_MASK 0xf000U

#define	AARCH32_MVFR0_FPTRAP_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_MVFR0_FPDIVIDE(_val) ( ( _val ) << 16 )

#define	AARCH32_MVFR0_FPDIVIDE_SHIFT 16

#define	AARCH32_MVFR0_FPDIVIDE_MASK 0xf0000U

#define	AARCH32_MVFR0_FPDIVIDE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_MVFR0_FPSQRT(_val) ( ( _val ) << 20 )

#define	AARCH32_MVFR0_FPSQRT_SHIFT 20

#define	AARCH32_MVFR0_FPSQRT_MASK 0xf00000U

#define	AARCH32_MVFR0_FPSQRT_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_MVFR0_FPSHVEC(_val) ( ( _val ) << 24 )

#define	AARCH32_MVFR0_FPSHVEC_SHIFT 24

#define	AARCH32_MVFR0_FPSHVEC_MASK 0xf000000U

#define	AARCH32_MVFR0_FPSHVEC_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_MVFR0_FPROUND(_val) ( ( _val ) << 28 )

#define	AARCH32_MVFR0_FPROUND_SHIFT 28

#define	AARCH32_MVFR0_FPROUND_MASK 0xf0000000U

#define	AARCH32_MVFR0_FPROUND_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_MVFR1_FPFTZ(_val) ( ( _val ) << 0 )

#define	AARCH32_MVFR1_FPFTZ_SHIFT 0

#define	AARCH32_MVFR1_FPFTZ_MASK 0xfU

#define	AARCH32_MVFR1_FPFTZ_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_MVFR1_FPDNAN(_val) ( ( _val ) << 4 )

#define	AARCH32_MVFR1_FPDNAN_SHIFT 4

#define	AARCH32_MVFR1_FPDNAN_MASK 0xf0U

#define	AARCH32_MVFR1_FPDNAN_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_MVFR1_SIMDLS(_val) ( ( _val ) << 8 )

#define	AARCH32_MVFR1_SIMDLS_SHIFT 8

#define	AARCH32_MVFR1_SIMDLS_MASK 0xf00U

#define	AARCH32_MVFR1_SIMDLS_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_MVFR1_SIMDINT(_val) ( ( _val ) << 12 )

#define	AARCH32_MVFR1_SIMDINT_SHIFT 12

#define	AARCH32_MVFR1_SIMDINT_MASK 0xf000U

#define	AARCH32_MVFR1_SIMDINT_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_MVFR1_SIMDSP(_val) ( ( _val ) << 16 )

#define	AARCH32_MVFR1_SIMDSP_SHIFT 16

#define	AARCH32_MVFR1_SIMDSP_MASK 0xf0000U

#define	AARCH32_MVFR1_SIMDSP_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_MVFR1_SIMDHP(_val) ( ( _val ) << 20 )

#define	AARCH32_MVFR1_SIMDHP_SHIFT 20

#define	AARCH32_MVFR1_SIMDHP_MASK 0xf00000U

#define	AARCH32_MVFR1_SIMDHP_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_MVFR1_FPHP(_val) ( ( _val ) << 24 )

#define	AARCH32_MVFR1_FPHP_SHIFT 24

#define	AARCH32_MVFR1_FPHP_MASK 0xf000000U

#define	AARCH32_MVFR1_FPHP_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_MVFR1_SIMDFMAC(_val) ( ( _val ) << 28 )

#define	AARCH32_MVFR1_SIMDFMAC_SHIFT 28

#define	AARCH32_MVFR1_SIMDFMAC_MASK 0xf0000000U

#define	AARCH32_MVFR1_SIMDFMAC_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_MVFR2_SIMDMISC(_val) ( ( _val ) << 0 )

#define	AARCH32_MVFR2_SIMDMISC_SHIFT 0

#define	AARCH32_MVFR2_SIMDMISC_MASK 0xfU

#define	AARCH32_MVFR2_SIMDMISC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_MVFR2_FPMISC(_val) ( ( _val ) << 4 )

#define	AARCH32_MVFR2_FPMISC_SHIFT 4

#define	AARCH32_MVFR2_FPMISC_MASK 0xf0U

#define	AARCH32_MVFR2_FPMISC_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_NSACR_CP10 0x400U

#define	AARCH32_NSACR_CP11 0x800U

#define	AARCH32_NSACR_NSASEDIS 0x8000U

#define	AARCH32_NSACR_NSTRCDIS 0x100000U

#define	AARCH32_PAR_F 0x1U

#define	AARCH32_PAR_SS 0x2U

#define	AARCH32_PAR_FS_4_0(_val) ( ( _val ) << 1 )

#define	AARCH32_PAR_FS_4_0_SHIFT 1

#define	AARCH32_PAR_FS_4_0_MASK 0x3eU

#define	AARCH32_PAR_FS_4_0_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x1fU )

#define	AARCH32_PAR_FST(_val) ( ( _val ) << 1 )

#define	AARCH32_PAR_FST_SHIFT 1

#define	AARCH32_PAR_FST_MASK 0x7eU

#define	AARCH32_PAR_FST_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x3fU )

#define	AARCH32_PAR_OUTER_1_0(_val) ( ( _val ) << 2 )

#define	AARCH32_PAR_OUTER_1_0_SHIFT 2

#define	AARCH32_PAR_OUTER_1_0_MASK 0xcU

#define	AARCH32_PAR_OUTER_1_0_GET(_reg) ( ( ( _reg ) >> 2 ) & 0x3U )

#define	AARCH32_PAR_INNER_2_0(_val) ( ( _val ) << 4 )

#define	AARCH32_PAR_INNER_2_0_SHIFT 4

#define	AARCH32_PAR_INNER_2_0_MASK 0x70U

#define	AARCH32_PAR_INNER_2_0_GET(_reg) ( ( ( _reg ) >> 4 ) & 0x7U )

#define	AARCH32_PAR_FS_5 0x40U

#define	AARCH32_PAR_SH_0 0x80U

#define	AARCH32_PAR_SH_1(_val) ( ( _val ) << 7 )

#define	AARCH32_PAR_SH_SHIFT_1 7

#define	AARCH32_PAR_SH_MASK_1 0x180U

#define	AARCH32_PAR_SH_GET_1(_reg) ( ( ( _reg ) >> 7 ) & 0x3U )

#define	AARCH32_PAR_S2WLK 0x100U

#define	AARCH32_PAR_FSTAGE 0x200U

#define	AARCH32_PAR_NS 0x200U

#define	AARCH32_PAR_NOS 0x400U

#define	AARCH32_PAR_LPAE 0x800U

#define	AARCH32_PAR_PA_0(_val) ( ( _val ) << 12 )

#define	AARCH32_PAR_PA_SHIFT_0 12

#define	AARCH32_PAR_PA_MASK_0 0xfffff000U

#define	AARCH32_PAR_PA_GET_0(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffU )

#define	AARCH32_PAR_PA_1(_val) ( ( _val ) << 12 )

#define	AARCH32_PAR_PA_SHIFT_1 12

#define	AARCH32_PAR_PA_MASK_1 0xfffffff000ULL

#define	AARCH32_PAR_PA_GET_1(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffffULL )

#define	AARCH32_PAR_ATTR(_val) ( ( _val ) << 56 )

#define	AARCH32_PAR_ATTR_SHIFT 56

#define	AARCH32_PAR_ATTR_MASK 0xff00000000000000ULL

#define	AARCH32_PAR_ATTR_GET(_reg) ( ( ( _reg ) >> 56 ) & 0xffULL )

#define	AARCH32_PRRR_DS0 0x10000U

#define	AARCH32_PRRR_DS1 0x20000U

#define	AARCH32_PRRR_NS0 0x40000U

#define	AARCH32_PRRR_NS1 0x80000U

#define	AARCH32_RMR_AA64 0x1U

#define	AARCH32_RMR_RR 0x2U

#define	AARCH32_SCR_NS 0x1U

#define	AARCH32_SCR_IRQ 0x2U

#define	AARCH32_SCR_FIQ 0x4U

#define	AARCH32_SCR_EA 0x8U

#define	AARCH32_SCR_FW 0x10U

#define	AARCH32_SCR_AW 0x20U

#define	AARCH32_SCR_NET 0x40U

#define	AARCH32_SCR_SCD 0x80U

#define	AARCH32_SCR_HCE 0x100U

#define	AARCH32_SCR_SIF 0x200U

#define	AARCH32_SCR_TWI 0x1000U

#define	AARCH32_SCR_TWE 0x2000U

#define	AARCH32_SCR_TERR 0x8000U

#define	AARCH32_SCTLR_M 0x1U

#define	AARCH32_SCTLR_A 0x2U

#define	AARCH32_SCTLR_C 0x4U

#define	AARCH32_SCTLR_NTLSMD 0x8U

#define	AARCH32_SCTLR_LSMAOE 0x10U

#define	AARCH32_SCTLR_CP15BEN 0x20U

#define	AARCH32_SCTLR_UNK 0x40U

#define	AARCH32_SCTLR_ITD 0x80U

#define	AARCH32_SCTLR_SED 0x100U

#define	AARCH32_SCTLR_ENRCTX 0x400U

#define	AARCH32_SCTLR_I 0x1000U

#define	AARCH32_SCTLR_V 0x2000U

#define	AARCH32_SCTLR_NTWI 0x10000U

#define	AARCH32_SCTLR_BR 0x20000U

#define	AARCH32_SCTLR_NTWE 0x40000U

#define	AARCH32_SCTLR_WXN 0x80000U

#define	AARCH32_SCTLR_UWXN 0x100000U

#define	AARCH32_SCTLR_FI 0x200000U

#define	AARCH32_SCTLR_SPAN 0x800000U

#define	AARCH32_SCTLR_EE 0x2000000U

#define	AARCH32_SCTLR_TRE 0x10000000U

#define	AARCH32_SCTLR_AFE 0x20000000U

#define	AARCH32_SCTLR_TE 0x40000000U

#define	AARCH32_SCTLR_DSSBS 0x80000000U

#define	AARCH32_SPSR_M_4_0(_val) ( ( _val ) << 0 )

#define	AARCH32_SPSR_M_4_0_SHIFT 0

#define	AARCH32_SPSR_M_4_0_MASK 0x1fU

#define	AARCH32_SPSR_M_4_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1fU )

#define	AARCH32_SPSR_T 0x20U

#define	AARCH32_SPSR_F 0x40U

#define	AARCH32_SPSR_I 0x80U

#define	AARCH32_SPSR_A 0x100U

#define	AARCH32_SPSR_E 0x200U

#define	AARCH32_SPSR_IT_7_2(_val) ( ( _val ) << 10 )

#define	AARCH32_SPSR_IT_7_2_SHIFT 10

#define	AARCH32_SPSR_IT_7_2_MASK 0xfc00U

#define	AARCH32_SPSR_IT_7_2_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3fU )

#define	AARCH32_SPSR_GE(_val) ( ( _val ) << 16 )

#define	AARCH32_SPSR_GE_SHIFT 16

#define	AARCH32_SPSR_GE_MASK 0xf0000U

#define	AARCH32_SPSR_GE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_SPSR_IL 0x100000U

#define	AARCH32_SPSR_DIT 0x200000U

#define	AARCH32_SPSR_PAN 0x400000U

#define	AARCH32_SPSR_SSBS 0x800000U

#define	AARCH32_SPSR_J 0x1000000U

#define	AARCH32_SPSR_IT_1_0(_val) ( ( _val ) << 25 )

#define	AARCH32_SPSR_IT_1_0_SHIFT 25

#define	AARCH32_SPSR_IT_1_0_MASK 0x6000000U

#define	AARCH32_SPSR_IT_1_0_GET(_reg) ( ( ( _reg ) >> 25 ) & 0x3U )

#define	AARCH32_SPSR_Q 0x8000000U

#define	AARCH32_SPSR_V 0x10000000U

#define	AARCH32_SPSR_C 0x20000000U

#define	AARCH32_SPSR_Z 0x40000000U

#define	AARCH32_SPSR_N 0x80000000U

#define	AARCH32_SPSR_ABT_M_4_0(_val) ( ( _val ) << 0 )

#define	AARCH32_SPSR_ABT_M_4_0_SHIFT 0

#define	AARCH32_SPSR_ABT_M_4_0_MASK 0x1fU

#define	AARCH32_SPSR_ABT_M_4_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1fU )

#define	AARCH32_SPSR_ABT_T 0x20U

#define	AARCH32_SPSR_ABT_F 0x40U

#define	AARCH32_SPSR_ABT_I 0x80U

#define	AARCH32_SPSR_ABT_A 0x100U

#define	AARCH32_SPSR_ABT_E 0x200U

#define	AARCH32_SPSR_ABT_IT_7_2(_val) ( ( _val ) << 10 )

#define	AARCH32_SPSR_ABT_IT_7_2_SHIFT 10

#define	AARCH32_SPSR_ABT_IT_7_2_MASK 0xfc00U

#define	AARCH32_SPSR_ABT_IT_7_2_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3fU )

#define	AARCH32_SPSR_ABT_GE(_val) ( ( _val ) << 16 )

#define	AARCH32_SPSR_ABT_GE_SHIFT 16

#define	AARCH32_SPSR_ABT_GE_MASK 0xf0000U

#define	AARCH32_SPSR_ABT_GE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_SPSR_ABT_IL 0x100000U

#define	AARCH32_SPSR_ABT_DIT 0x200000U

#define	AARCH32_SPSR_ABT_PAN 0x400000U

#define	AARCH32_SPSR_ABT_SSBS 0x800000U

#define	AARCH32_SPSR_ABT_J 0x1000000U

#define	AARCH32_SPSR_ABT_IT_1_0(_val) ( ( _val ) << 25 )

#define	AARCH32_SPSR_ABT_IT_1_0_SHIFT 25

#define	AARCH32_SPSR_ABT_IT_1_0_MASK 0x6000000U

#define	AARCH32_SPSR_ABT_IT_1_0_GET(_reg) ( ( ( _reg ) >> 25 ) & 0x3U )

#define	AARCH32_SPSR_ABT_Q 0x8000000U

#define	AARCH32_SPSR_ABT_V 0x10000000U

#define	AARCH32_SPSR_ABT_C 0x20000000U

#define	AARCH32_SPSR_ABT_Z 0x40000000U

#define	AARCH32_SPSR_ABT_N 0x80000000U

#define	AARCH32_SPSR_FIQ_M_4_0(_val) ( ( _val ) << 0 )

#define	AARCH32_SPSR_FIQ_M_4_0_SHIFT 0

#define	AARCH32_SPSR_FIQ_M_4_0_MASK 0x1fU

#define	AARCH32_SPSR_FIQ_M_4_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1fU )

#define	AARCH32_SPSR_FIQ_T 0x20U

#define	AARCH32_SPSR_FIQ_F 0x40U

#define	AARCH32_SPSR_FIQ_I 0x80U

#define	AARCH32_SPSR_FIQ_A 0x100U

#define	AARCH32_SPSR_FIQ_E 0x200U

#define	AARCH32_SPSR_FIQ_IT_7_2(_val) ( ( _val ) << 10 )

#define	AARCH32_SPSR_FIQ_IT_7_2_SHIFT 10

#define	AARCH32_SPSR_FIQ_IT_7_2_MASK 0xfc00U

#define	AARCH32_SPSR_FIQ_IT_7_2_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3fU )

#define	AARCH32_SPSR_FIQ_GE(_val) ( ( _val ) << 16 )

#define	AARCH32_SPSR_FIQ_GE_SHIFT 16

#define	AARCH32_SPSR_FIQ_GE_MASK 0xf0000U

#define	AARCH32_SPSR_FIQ_GE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_SPSR_FIQ_IL 0x100000U

#define	AARCH32_SPSR_FIQ_DIT 0x200000U

#define	AARCH32_SPSR_FIQ_PAN 0x400000U

#define	AARCH32_SPSR_FIQ_SSBS 0x800000U

#define	AARCH32_SPSR_FIQ_J 0x1000000U

#define	AARCH32_SPSR_FIQ_IT_1_0(_val) ( ( _val ) << 25 )

#define	AARCH32_SPSR_FIQ_IT_1_0_SHIFT 25

#define	AARCH32_SPSR_FIQ_IT_1_0_MASK 0x6000000U

#define	AARCH32_SPSR_FIQ_IT_1_0_GET(_reg) ( ( ( _reg ) >> 25 ) & 0x3U )

#define	AARCH32_SPSR_FIQ_Q 0x8000000U

#define	AARCH32_SPSR_FIQ_V 0x10000000U

#define	AARCH32_SPSR_FIQ_C 0x20000000U

#define	AARCH32_SPSR_FIQ_Z 0x40000000U

#define	AARCH32_SPSR_FIQ_N 0x80000000U

#define	AARCH32_SPSR_HYP_M_4_0(_val) ( ( _val ) << 0 )

#define	AARCH32_SPSR_HYP_M_4_0_SHIFT 0

#define	AARCH32_SPSR_HYP_M_4_0_MASK 0x1fU

#define	AARCH32_SPSR_HYP_M_4_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1fU )

#define	AARCH32_SPSR_HYP_T 0x20U

#define	AARCH32_SPSR_HYP_F 0x40U

#define	AARCH32_SPSR_HYP_I 0x80U

#define	AARCH32_SPSR_HYP_A 0x100U

#define	AARCH32_SPSR_HYP_E 0x200U

#define	AARCH32_SPSR_HYP_IT_7_2(_val) ( ( _val ) << 10 )

#define	AARCH32_SPSR_HYP_IT_7_2_SHIFT 10

#define	AARCH32_SPSR_HYP_IT_7_2_MASK 0xfc00U

#define	AARCH32_SPSR_HYP_IT_7_2_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3fU )

#define	AARCH32_SPSR_HYP_GE(_val) ( ( _val ) << 16 )

#define	AARCH32_SPSR_HYP_GE_SHIFT 16

#define	AARCH32_SPSR_HYP_GE_MASK 0xf0000U

#define	AARCH32_SPSR_HYP_GE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_SPSR_HYP_IL 0x100000U

#define	AARCH32_SPSR_HYP_DIT 0x200000U

#define	AARCH32_SPSR_HYP_PAN 0x400000U

#define	AARCH32_SPSR_HYP_SSBS 0x800000U

#define	AARCH32_SPSR_HYP_J 0x1000000U

#define	AARCH32_SPSR_HYP_IT_1_0(_val) ( ( _val ) << 25 )

#define	AARCH32_SPSR_HYP_IT_1_0_SHIFT 25

#define	AARCH32_SPSR_HYP_IT_1_0_MASK 0x6000000U

#define	AARCH32_SPSR_HYP_IT_1_0_GET(_reg) ( ( ( _reg ) >> 25 ) & 0x3U )

#define	AARCH32_SPSR_HYP_Q 0x8000000U

#define	AARCH32_SPSR_HYP_V 0x10000000U

#define	AARCH32_SPSR_HYP_C 0x20000000U

#define	AARCH32_SPSR_HYP_Z 0x40000000U

#define	AARCH32_SPSR_HYP_N 0x80000000U

#define	AARCH32_SPSR_IRQ_M_4_0(_val) ( ( _val ) << 0 )

#define	AARCH32_SPSR_IRQ_M_4_0_SHIFT 0

#define	AARCH32_SPSR_IRQ_M_4_0_MASK 0x1fU

#define	AARCH32_SPSR_IRQ_M_4_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1fU )

#define	AARCH32_SPSR_IRQ_T 0x20U

#define	AARCH32_SPSR_IRQ_F 0x40U

#define	AARCH32_SPSR_IRQ_I 0x80U

#define	AARCH32_SPSR_IRQ_A 0x100U

#define	AARCH32_SPSR_IRQ_E 0x200U

#define	AARCH32_SPSR_IRQ_IT_7_2(_val) ( ( _val ) << 10 )

#define	AARCH32_SPSR_IRQ_IT_7_2_SHIFT 10

#define	AARCH32_SPSR_IRQ_IT_7_2_MASK 0xfc00U

#define	AARCH32_SPSR_IRQ_IT_7_2_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3fU )

#define	AARCH32_SPSR_IRQ_GE(_val) ( ( _val ) << 16 )

#define	AARCH32_SPSR_IRQ_GE_SHIFT 16

#define	AARCH32_SPSR_IRQ_GE_MASK 0xf0000U

#define	AARCH32_SPSR_IRQ_GE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_SPSR_IRQ_IL 0x100000U

#define	AARCH32_SPSR_IRQ_DIT 0x200000U

#define	AARCH32_SPSR_IRQ_PAN 0x400000U

#define	AARCH32_SPSR_IRQ_SSBS 0x800000U

#define	AARCH32_SPSR_IRQ_J 0x1000000U

#define	AARCH32_SPSR_IRQ_IT_1_0(_val) ( ( _val ) << 25 )

#define	AARCH32_SPSR_IRQ_IT_1_0_SHIFT 25

#define	AARCH32_SPSR_IRQ_IT_1_0_MASK 0x6000000U

#define	AARCH32_SPSR_IRQ_IT_1_0_GET(_reg) ( ( ( _reg ) >> 25 ) & 0x3U )

#define	AARCH32_SPSR_IRQ_Q 0x8000000U

#define	AARCH32_SPSR_IRQ_V 0x10000000U

#define	AARCH32_SPSR_IRQ_C 0x20000000U

#define	AARCH32_SPSR_IRQ_Z 0x40000000U

#define	AARCH32_SPSR_IRQ_N 0x80000000U

#define	AARCH32_SPSR_MON_M_4_0(_val) ( ( _val ) << 0 )

#define	AARCH32_SPSR_MON_M_4_0_SHIFT 0

#define	AARCH32_SPSR_MON_M_4_0_MASK 0x1fU

#define	AARCH32_SPSR_MON_M_4_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1fU )

#define	AARCH32_SPSR_MON_T 0x20U

#define	AARCH32_SPSR_MON_F 0x40U

#define	AARCH32_SPSR_MON_I 0x80U

#define	AARCH32_SPSR_MON_A 0x100U

#define	AARCH32_SPSR_MON_E 0x200U

#define	AARCH32_SPSR_MON_IT_7_2(_val) ( ( _val ) << 10 )

#define	AARCH32_SPSR_MON_IT_7_2_SHIFT 10

#define	AARCH32_SPSR_MON_IT_7_2_MASK 0xfc00U

#define	AARCH32_SPSR_MON_IT_7_2_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3fU )

#define	AARCH32_SPSR_MON_GE(_val) ( ( _val ) << 16 )

#define	AARCH32_SPSR_MON_GE_SHIFT 16

#define	AARCH32_SPSR_MON_GE_MASK 0xf0000U

#define	AARCH32_SPSR_MON_GE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_SPSR_MON_IL 0x100000U

#define	AARCH32_SPSR_MON_DIT 0x200000U

#define	AARCH32_SPSR_MON_PAN 0x400000U

#define	AARCH32_SPSR_MON_SSBS 0x800000U

#define	AARCH32_SPSR_MON_J 0x1000000U

#define	AARCH32_SPSR_MON_IT_1_0(_val) ( ( _val ) << 25 )

#define	AARCH32_SPSR_MON_IT_1_0_SHIFT 25

#define	AARCH32_SPSR_MON_IT_1_0_MASK 0x6000000U

#define	AARCH32_SPSR_MON_IT_1_0_GET(_reg) ( ( ( _reg ) >> 25 ) & 0x3U )

#define	AARCH32_SPSR_MON_Q 0x8000000U

#define	AARCH32_SPSR_MON_V 0x10000000U

#define	AARCH32_SPSR_MON_C 0x20000000U

#define	AARCH32_SPSR_MON_Z 0x40000000U

#define	AARCH32_SPSR_MON_N 0x80000000U

#define	AARCH32_SPSR_SVC_M_4_0(_val) ( ( _val ) << 0 )

#define	AARCH32_SPSR_SVC_M_4_0_SHIFT 0

#define	AARCH32_SPSR_SVC_M_4_0_MASK 0x1fU

#define	AARCH32_SPSR_SVC_M_4_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1fU )

#define	AARCH32_SPSR_SVC_T 0x20U

#define	AARCH32_SPSR_SVC_F 0x40U

#define	AARCH32_SPSR_SVC_I 0x80U

#define	AARCH32_SPSR_SVC_A 0x100U

#define	AARCH32_SPSR_SVC_E 0x200U

#define	AARCH32_SPSR_SVC_IT_7_2(_val) ( ( _val ) << 10 )

#define	AARCH32_SPSR_SVC_IT_7_2_SHIFT 10

#define	AARCH32_SPSR_SVC_IT_7_2_MASK 0xfc00U

#define	AARCH32_SPSR_SVC_IT_7_2_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3fU )

#define	AARCH32_SPSR_SVC_GE(_val) ( ( _val ) << 16 )

#define	AARCH32_SPSR_SVC_GE_SHIFT 16

#define	AARCH32_SPSR_SVC_GE_MASK 0xf0000U

#define	AARCH32_SPSR_SVC_GE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_SPSR_SVC_IL 0x100000U

#define	AARCH32_SPSR_SVC_DIT 0x200000U

#define	AARCH32_SPSR_SVC_PAN 0x400000U

#define	AARCH32_SPSR_SVC_SSBS 0x800000U

#define	AARCH32_SPSR_SVC_J 0x1000000U

#define	AARCH32_SPSR_SVC_IT_1_0(_val) ( ( _val ) << 25 )

#define	AARCH32_SPSR_SVC_IT_1_0_SHIFT 25

#define	AARCH32_SPSR_SVC_IT_1_0_MASK 0x6000000U

#define	AARCH32_SPSR_SVC_IT_1_0_GET(_reg) ( ( ( _reg ) >> 25 ) & 0x3U )

#define	AARCH32_SPSR_SVC_Q 0x8000000U

#define	AARCH32_SPSR_SVC_V 0x10000000U

#define	AARCH32_SPSR_SVC_C 0x20000000U

#define	AARCH32_SPSR_SVC_Z 0x40000000U

#define	AARCH32_SPSR_SVC_N 0x80000000U

#define	AARCH32_SPSR_UND_M_4_0(_val) ( ( _val ) << 0 )

#define	AARCH32_SPSR_UND_M_4_0_SHIFT 0

#define	AARCH32_SPSR_UND_M_4_0_MASK 0x1fU

#define	AARCH32_SPSR_UND_M_4_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1fU )

#define	AARCH32_SPSR_UND_T 0x20U

#define	AARCH32_SPSR_UND_F 0x40U

#define	AARCH32_SPSR_UND_I 0x80U

#define	AARCH32_SPSR_UND_A 0x100U

#define	AARCH32_SPSR_UND_E 0x200U

#define	AARCH32_SPSR_UND_IT_7_2(_val) ( ( _val ) << 10 )

#define	AARCH32_SPSR_UND_IT_7_2_SHIFT 10

#define	AARCH32_SPSR_UND_IT_7_2_MASK 0xfc00U

#define	AARCH32_SPSR_UND_IT_7_2_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3fU )

#define	AARCH32_SPSR_UND_GE(_val) ( ( _val ) << 16 )

#define	AARCH32_SPSR_UND_GE_SHIFT 16

#define	AARCH32_SPSR_UND_GE_MASK 0xf0000U

#define	AARCH32_SPSR_UND_GE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_SPSR_UND_IL 0x100000U

#define	AARCH32_SPSR_UND_DIT 0x200000U

#define	AARCH32_SPSR_UND_PAN 0x400000U

#define	AARCH32_SPSR_UND_SSBS 0x800000U

#define	AARCH32_SPSR_UND_J 0x1000000U

#define	AARCH32_SPSR_UND_IT_1_0(_val) ( ( _val ) << 25 )

#define	AARCH32_SPSR_UND_IT_1_0_SHIFT 25

#define	AARCH32_SPSR_UND_IT_1_0_MASK 0x6000000U

#define	AARCH32_SPSR_UND_IT_1_0_GET(_reg) ( ( ( _reg ) >> 25 ) & 0x3U )

#define	AARCH32_SPSR_UND_Q 0x8000000U

#define	AARCH32_SPSR_UND_V 0x10000000U

#define	AARCH32_SPSR_UND_C 0x20000000U

#define	AARCH32_SPSR_UND_Z 0x40000000U

#define	AARCH32_SPSR_UND_N 0x80000000U

#define	AARCH32_TLBIASID_ASID(_val) ( ( _val ) << 0 )

#define	AARCH32_TLBIASID_ASID_SHIFT 0

#define	AARCH32_TLBIASID_ASID_MASK 0xffU

#define	AARCH32_TLBIASID_ASID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_TLBIASIDIS_ASID(_val) ( ( _val ) << 0 )

#define	AARCH32_TLBIASIDIS_ASID_SHIFT 0

#define	AARCH32_TLBIASIDIS_ASID_MASK 0xffU

#define	AARCH32_TLBIASIDIS_ASID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_TLBIIPAS2_IPA_39_12(_val) ( ( _val ) << 0 )

#define	AARCH32_TLBIIPAS2_IPA_39_12_SHIFT 0

#define	AARCH32_TLBIIPAS2_IPA_39_12_MASK 0xfffffffU

#define	AARCH32_TLBIIPAS2_IPA_39_12_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfffffffU )

#define	AARCH32_TLBIIPAS2IS_IPA_39_12(_val) ( ( _val ) << 0 )

#define	AARCH32_TLBIIPAS2IS_IPA_39_12_SHIFT 0

#define	AARCH32_TLBIIPAS2IS_IPA_39_12_MASK 0xfffffffU

#define	AARCH32_TLBIIPAS2IS_IPA_39_12_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfffffffU )

#define	AARCH32_TLBIIPAS2L_IPA_39_12(_val) ( ( _val ) << 0 )

#define	AARCH32_TLBIIPAS2L_IPA_39_12_SHIFT 0

#define	AARCH32_TLBIIPAS2L_IPA_39_12_MASK 0xfffffffU

#define	AARCH32_TLBIIPAS2L_IPA_39_12_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfffffffU )

#define	AARCH32_TLBIIPAS2LIS_IPA_39_12(_val) ( ( _val ) << 0 )

#define	AARCH32_TLBIIPAS2LIS_IPA_39_12_SHIFT 0

#define	AARCH32_TLBIIPAS2LIS_IPA_39_12_MASK 0xfffffffU

#define	AARCH32_TLBIIPAS2LIS_IPA_39_12_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfffffffU )

#define	AARCH32_TLBIMVA_ASID(_val) ( ( _val ) << 0 )

#define	AARCH32_TLBIMVA_ASID_SHIFT 0

#define	AARCH32_TLBIMVA_ASID_MASK 0xffU

#define	AARCH32_TLBIMVA_ASID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_TLBIMVA_VA(_val) ( ( _val ) << 12 )

#define	AARCH32_TLBIMVA_VA_SHIFT 12

#define	AARCH32_TLBIMVA_VA_MASK 0xfffff000U

#define	AARCH32_TLBIMVA_VA_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffU )

#define	AARCH32_TLBIMVAA_VA(_val) ( ( _val ) << 12 )

#define	AARCH32_TLBIMVAA_VA_SHIFT 12

#define	AARCH32_TLBIMVAA_VA_MASK 0xfffff000U

#define	AARCH32_TLBIMVAA_VA_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffU )

#define	AARCH32_TLBIMVAAIS_VA(_val) ( ( _val ) << 12 )

#define	AARCH32_TLBIMVAAIS_VA_SHIFT 12

#define	AARCH32_TLBIMVAAIS_VA_MASK 0xfffff000U

#define	AARCH32_TLBIMVAAIS_VA_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffU )

#define	AARCH32_TLBIMVAAL_VA(_val) ( ( _val ) << 12 )

#define	AARCH32_TLBIMVAAL_VA_SHIFT 12

#define	AARCH32_TLBIMVAAL_VA_MASK 0xfffff000U

#define	AARCH32_TLBIMVAAL_VA_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffU )

#define	AARCH32_TLBIMVAALIS_VA(_val) ( ( _val ) << 12 )

#define	AARCH32_TLBIMVAALIS_VA_SHIFT 12

#define	AARCH32_TLBIMVAALIS_VA_MASK 0xfffff000U

#define	AARCH32_TLBIMVAALIS_VA_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffU )

#define	AARCH32_TLBIMVAH_VA(_val) ( ( _val ) << 12 )

#define	AARCH32_TLBIMVAH_VA_SHIFT 12

#define	AARCH32_TLBIMVAH_VA_MASK 0xfffff000U

#define	AARCH32_TLBIMVAH_VA_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffU )

#define	AARCH32_TLBIMVAHIS_VA(_val) ( ( _val ) << 12 )

#define	AARCH32_TLBIMVAHIS_VA_SHIFT 12

#define	AARCH32_TLBIMVAHIS_VA_MASK 0xfffff000U

#define	AARCH32_TLBIMVAHIS_VA_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffU )

#define	AARCH32_TLBIMVAIS_ASID(_val) ( ( _val ) << 0 )

#define	AARCH32_TLBIMVAIS_ASID_SHIFT 0

#define	AARCH32_TLBIMVAIS_ASID_MASK 0xffU

#define	AARCH32_TLBIMVAIS_ASID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_TLBIMVAIS_VA(_val) ( ( _val ) << 12 )

#define	AARCH32_TLBIMVAIS_VA_SHIFT 12

#define	AARCH32_TLBIMVAIS_VA_MASK 0xfffff000U

#define	AARCH32_TLBIMVAIS_VA_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffU )

#define	AARCH32_TLBIMVAL_ASID(_val) ( ( _val ) << 0 )

#define	AARCH32_TLBIMVAL_ASID_SHIFT 0

#define	AARCH32_TLBIMVAL_ASID_MASK 0xffU

#define	AARCH32_TLBIMVAL_ASID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_TLBIMVAL_VA(_val) ( ( _val ) << 12 )

#define	AARCH32_TLBIMVAL_VA_SHIFT 12

#define	AARCH32_TLBIMVAL_VA_MASK 0xfffff000U

#define	AARCH32_TLBIMVAL_VA_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffU )

#define	AARCH32_TLBIMVALH_VA(_val) ( ( _val ) << 12 )

#define	AARCH32_TLBIMVALH_VA_SHIFT 12

#define	AARCH32_TLBIMVALH_VA_MASK 0xfffff000U

#define	AARCH32_TLBIMVALH_VA_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffU )

#define	AARCH32_TLBIMVALHIS_VA(_val) ( ( _val ) << 12 )

#define	AARCH32_TLBIMVALHIS_VA_SHIFT 12

#define	AARCH32_TLBIMVALHIS_VA_MASK 0xfffff000U

#define	AARCH32_TLBIMVALHIS_VA_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffU )

#define	AARCH32_TLBIMVALIS_ASID(_val) ( ( _val ) << 0 )

#define	AARCH32_TLBIMVALIS_ASID_SHIFT 0

#define	AARCH32_TLBIMVALIS_ASID_MASK 0xffU

#define	AARCH32_TLBIMVALIS_ASID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_TLBIMVALIS_VA(_val) ( ( _val ) << 12 )

#define	AARCH32_TLBIMVALIS_VA_SHIFT 12

#define	AARCH32_TLBIMVALIS_VA_MASK 0xfffff000U

#define	AARCH32_TLBIMVALIS_VA_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffU )

#define	AARCH32_TLBTR_NU 0x1U

#define	AARCH32_TTBCR_N(_val) ( ( _val ) << 0 )

#define	AARCH32_TTBCR_N_SHIFT 0

#define	AARCH32_TTBCR_N_MASK 0x7U

#define	AARCH32_TTBCR_N_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x7U )

#define	AARCH32_TTBCR_T0SZ(_val) ( ( _val ) << 0 )

#define	AARCH32_TTBCR_T0SZ_SHIFT 0

#define	AARCH32_TTBCR_T0SZ_MASK 0x7U

#define	AARCH32_TTBCR_T0SZ_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x7U )

#define	AARCH32_TTBCR_PD0 0x10U

#define	AARCH32_TTBCR_PD1 0x20U

#define	AARCH32_TTBCR_T2E 0x40U

#define	AARCH32_TTBCR_EPD0 0x80U

#define	AARCH32_TTBCR_IRGN0(_val) ( ( _val ) << 8 )

#define	AARCH32_TTBCR_IRGN0_SHIFT 8

#define	AARCH32_TTBCR_IRGN0_MASK 0x300U

#define	AARCH32_TTBCR_IRGN0_GET(_reg) ( ( ( _reg ) >> 8 ) & 0x3U )

#define	AARCH32_TTBCR_ORGN0(_val) ( ( _val ) << 10 )

#define	AARCH32_TTBCR_ORGN0_SHIFT 10

#define	AARCH32_TTBCR_ORGN0_MASK 0xc00U

#define	AARCH32_TTBCR_ORGN0_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3U )

#define	AARCH32_TTBCR_SH0(_val) ( ( _val ) << 12 )

#define	AARCH32_TTBCR_SH0_SHIFT 12

#define	AARCH32_TTBCR_SH0_MASK 0x3000U

#define	AARCH32_TTBCR_SH0_GET(_reg) ( ( ( _reg ) >> 12 ) & 0x3U )

#define	AARCH32_TTBCR_T1SZ(_val) ( ( _val ) << 16 )

#define	AARCH32_TTBCR_T1SZ_SHIFT 16

#define	AARCH32_TTBCR_T1SZ_MASK 0x70000U

#define	AARCH32_TTBCR_T1SZ_GET(_reg) ( ( ( _reg ) >> 16 ) & 0x7U )

#define	AARCH32_TTBCR_A1 0x400000U

#define	AARCH32_TTBCR_EPD1 0x800000U

#define	AARCH32_TTBCR_IRGN1(_val) ( ( _val ) << 24 )

#define	AARCH32_TTBCR_IRGN1_SHIFT 24

#define	AARCH32_TTBCR_IRGN1_MASK 0x3000000U

#define	AARCH32_TTBCR_IRGN1_GET(_reg) ( ( ( _reg ) >> 24 ) & 0x3U )

#define	AARCH32_TTBCR_ORGN1(_val) ( ( _val ) << 26 )

#define	AARCH32_TTBCR_ORGN1_SHIFT 26

#define	AARCH32_TTBCR_ORGN1_MASK 0xc000000U

#define	AARCH32_TTBCR_ORGN1_GET(_reg) ( ( ( _reg ) >> 26 ) & 0x3U )

#define	AARCH32_TTBCR_SH1(_val) ( ( _val ) << 28 )

#define	AARCH32_TTBCR_SH1_SHIFT 28

#define	AARCH32_TTBCR_SH1_MASK 0x30000000U

#define	AARCH32_TTBCR_SH1_GET(_reg) ( ( ( _reg ) >> 28 ) & 0x3U )

#define	AARCH32_TTBCR_EAE 0x80000000U

#define	AARCH32_TTBCR2_HPD0 0x200U

#define	AARCH32_TTBCR2_HPD1 0x400U

#define	AARCH32_TTBCR2_HWU059 0x800U

#define	AARCH32_TTBCR2_HWU060 0x1000U

#define	AARCH32_TTBCR2_HWU061 0x2000U

#define	AARCH32_TTBCR2_HWU062 0x4000U

#define	AARCH32_TTBCR2_HWU159 0x8000U

#define	AARCH32_TTBCR2_HWU160 0x10000U

#define	AARCH32_TTBCR2_HWU161 0x20000U

#define	AARCH32_TTBCR2_HWU162 0x40000U

#define	AARCH32_TTBR0_CNP 0x1U

#define	AARCH32_TTBR0_IRGN_1 0x1U

#define	AARCH32_TTBR0_S 0x2U

#define	AARCH32_TTBR0_BADDR(_val) ( ( _val ) << 1 )

#define	AARCH32_TTBR0_BADDR_SHIFT 1

#define	AARCH32_TTBR0_BADDR_MASK 0xfffffffffffeULL

#define	AARCH32_TTBR0_BADDR_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL )

#define	AARCH32_TTBR0_IMP 0x4U

#define	AARCH32_TTBR0_RGN(_val) ( ( _val ) << 3 )

#define	AARCH32_TTBR0_RGN_SHIFT 3

#define	AARCH32_TTBR0_RGN_MASK 0x18U

#define	AARCH32_TTBR0_RGN_GET(_reg) ( ( ( _reg ) >> 3 ) & 0x3U )

#define	AARCH32_TTBR0_NOS 0x20U

#define	AARCH32_TTBR0_IRGN_0 0x40U

#define	AARCH32_TTBR0_TTB0(_val) ( ( _val ) << 7 )

#define	AARCH32_TTBR0_TTB0_SHIFT 7

#define	AARCH32_TTBR0_TTB0_MASK 0xffffff80U

#define	AARCH32_TTBR0_TTB0_GET(_reg) ( ( ( _reg ) >> 7 ) & 0x1ffffffU )

#define	AARCH32_TTBR0_ASID(_val) ( ( _val ) << 48 )

#define	AARCH32_TTBR0_ASID_SHIFT 48

#define	AARCH32_TTBR0_ASID_MASK 0xff000000000000ULL

#define	AARCH32_TTBR0_ASID_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xffULL )

#define	AARCH32_TTBR1_CNP 0x1U

#define	AARCH32_TTBR1_IRGN_0 0x1U

#define	AARCH32_TTBR1_S 0x2U

#define	AARCH32_TTBR1_BADDR(_val) ( ( _val ) << 1 )

#define	AARCH32_TTBR1_BADDR_SHIFT 1

#define	AARCH32_TTBR1_BADDR_MASK 0xfffffffffffeULL

#define	AARCH32_TTBR1_BADDR_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL )

#define	AARCH32_TTBR1_IMP 0x4U

#define	AARCH32_TTBR1_RGN(_val) ( ( _val ) << 3 )

#define	AARCH32_TTBR1_RGN_SHIFT 3

#define	AARCH32_TTBR1_RGN_MASK 0x18U

#define	AARCH32_TTBR1_RGN_GET(_reg) ( ( ( _reg ) >> 3 ) & 0x3U )

#define	AARCH32_TTBR1_NOS 0x20U

#define	AARCH32_TTBR1_IRGN_1 0x40U

#define	AARCH32_TTBR1_TTB1(_val) ( ( _val ) << 7 )

#define	AARCH32_TTBR1_TTB1_SHIFT 7

#define	AARCH32_TTBR1_TTB1_MASK 0xffffff80U

#define	AARCH32_TTBR1_TTB1_GET(_reg) ( ( ( _reg ) >> 7 ) & 0x1ffffffU )

#define	AARCH32_TTBR1_ASID(_val) ( ( _val ) << 48 )

#define	AARCH32_TTBR1_ASID_SHIFT 48

#define	AARCH32_TTBR1_ASID_MASK 0xff000000000000ULL

#define	AARCH32_TTBR1_ASID_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xffULL )

#define	AARCH32_VMPIDR_AFF0(_val) ( ( _val ) << 0 )

#define	AARCH32_VMPIDR_AFF0_SHIFT 0

#define	AARCH32_VMPIDR_AFF0_MASK 0xffU

#define	AARCH32_VMPIDR_AFF0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_VMPIDR_AFF1(_val) ( ( _val ) << 8 )

#define	AARCH32_VMPIDR_AFF1_SHIFT 8

#define	AARCH32_VMPIDR_AFF1_MASK 0xff00U

#define	AARCH32_VMPIDR_AFF1_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xffU )

#define	AARCH32_VMPIDR_AFF2(_val) ( ( _val ) << 16 )

#define	AARCH32_VMPIDR_AFF2_SHIFT 16

#define	AARCH32_VMPIDR_AFF2_MASK 0xff0000U

#define	AARCH32_VMPIDR_AFF2_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xffU )

#define	AARCH32_VMPIDR_MT 0x1000000U

#define	AARCH32_VMPIDR_U 0x40000000U

#define	AARCH32_VMPIDR_M 0x80000000U

#define	AARCH32_VPIDR_REVISION(_val) ( ( _val ) << 0 )

#define	AARCH32_VPIDR_REVISION_SHIFT 0

#define	AARCH32_VPIDR_REVISION_MASK 0xfU

#define	AARCH32_VPIDR_REVISION_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_VPIDR_PARTNUM(_val) ( ( _val ) << 4 )

#define	AARCH32_VPIDR_PARTNUM_SHIFT 4

#define	AARCH32_VPIDR_PARTNUM_MASK 0xfff0U

#define	AARCH32_VPIDR_PARTNUM_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfffU )

#define	AARCH32_VPIDR_ARCHITECTURE(_val) ( ( _val ) << 16 )

#define	AARCH32_VPIDR_ARCHITECTURE_SHIFT 16

#define	AARCH32_VPIDR_ARCHITECTURE_MASK 0xf0000U

#define	AARCH32_VPIDR_ARCHITECTURE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_VPIDR_VARIANT(_val) ( ( _val ) << 20 )

#define	AARCH32_VPIDR_VARIANT_SHIFT 20

#define	AARCH32_VPIDR_VARIANT_MASK 0xf00000U

#define	AARCH32_VPIDR_VARIANT_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_VPIDR_IMPLEMENTER(_val) ( ( _val ) << 24 )

#define	AARCH32_VPIDR_IMPLEMENTER_SHIFT 24

#define	AARCH32_VPIDR_IMPLEMENTER_MASK 0xff000000U

#define	AARCH32_VPIDR_IMPLEMENTER_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xffU )

#define	AARCH32_VTCR_T0SZ(_val) ( ( _val ) << 0 )

#define	AARCH32_VTCR_T0SZ_SHIFT 0

#define	AARCH32_VTCR_T0SZ_MASK 0xfU

#define	AARCH32_VTCR_T0SZ_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_VTCR_S 0x10U

#define	AARCH32_VTCR_SL0(_val) ( ( _val ) << 6 )

#define	AARCH32_VTCR_SL0_SHIFT 6

#define	AARCH32_VTCR_SL0_MASK 0xc0U

#define	AARCH32_VTCR_SL0_GET(_reg) ( ( ( _reg ) >> 6 ) & 0x3U )

#define	AARCH32_VTCR_IRGN0(_val) ( ( _val ) << 8 )

#define	AARCH32_VTCR_IRGN0_SHIFT 8

#define	AARCH32_VTCR_IRGN0_MASK 0x300U

#define	AARCH32_VTCR_IRGN0_GET(_reg) ( ( ( _reg ) >> 8 ) & 0x3U )

#define	AARCH32_VTCR_ORGN0(_val) ( ( _val ) << 10 )

#define	AARCH32_VTCR_ORGN0_SHIFT 10

#define	AARCH32_VTCR_ORGN0_MASK 0xc00U

#define	AARCH32_VTCR_ORGN0_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3U )

#define	AARCH32_VTCR_SH0(_val) ( ( _val ) << 12 )

#define	AARCH32_VTCR_SH0_SHIFT 12

#define	AARCH32_VTCR_SH0_MASK 0x3000U

#define	AARCH32_VTCR_SH0_GET(_reg) ( ( ( _reg ) >> 12 ) & 0x3U )

#define	AARCH32_VTCR_HWU59 0x2000000U

#define	AARCH32_VTCR_HWU60 0x4000000U

#define	AARCH32_VTCR_HWU61 0x8000000U

#define	AARCH32_VTCR_HWU62 0x10000000U

#define	AARCH32_VTTBR_CNP 0x1U

#define	AARCH32_VTTBR_BADDR(_val) ( ( _val ) << 1 )

#define	AARCH32_VTTBR_BADDR_SHIFT 1

#define	AARCH32_VTTBR_BADDR_MASK 0xfffffffffffeULL

#define	AARCH32_VTTBR_BADDR_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7fffffffffffULL )

#define	AARCH32_VTTBR_VMID(_val) ( ( _val ) << 48 )

#define	AARCH32_VTTBR_VMID_SHIFT 48

#define	AARCH32_VTTBR_VMID_MASK 0xff000000000000ULL

#define	AARCH32_VTTBR_VMID_GET(_reg) ( ( ( _reg ) >> 48 ) & 0xffULL )

#define	AARCH32_DBGAUTHSTATUS_NSID(_val) ( ( _val ) << 0 )

#define	AARCH32_DBGAUTHSTATUS_NSID_SHIFT 0

#define	AARCH32_DBGAUTHSTATUS_NSID_MASK 0x3U

#define	AARCH32_DBGAUTHSTATUS_NSID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3U )

#define	AARCH32_DBGAUTHSTATUS_NSNID(_val) ( ( _val ) << 2 )

#define	AARCH32_DBGAUTHSTATUS_NSNID_SHIFT 2

#define	AARCH32_DBGAUTHSTATUS_NSNID_MASK 0xcU

#define	AARCH32_DBGAUTHSTATUS_NSNID_GET(_reg) ( ( ( _reg ) >> 2 ) & 0x3U )

#define	AARCH32_DBGAUTHSTATUS_SID(_val) ( ( _val ) << 4 )

#define	AARCH32_DBGAUTHSTATUS_SID_SHIFT 4

#define	AARCH32_DBGAUTHSTATUS_SID_MASK 0x30U

#define	AARCH32_DBGAUTHSTATUS_SID_GET(_reg) ( ( ( _reg ) >> 4 ) & 0x3U )

#define	AARCH32_DBGAUTHSTATUS_SNID(_val) ( ( _val ) << 6 )

#define	AARCH32_DBGAUTHSTATUS_SNID_SHIFT 6

#define	AARCH32_DBGAUTHSTATUS_SNID_MASK 0xc0U

#define	AARCH32_DBGAUTHSTATUS_SNID_GET(_reg) ( ( ( _reg ) >> 6 ) & 0x3U )

#define	AARCH32_DBGBCR_E 0x1U

#define	AARCH32_DBGBCR_PMC(_val) ( ( _val ) << 1 )

#define	AARCH32_DBGBCR_PMC_SHIFT 1

#define	AARCH32_DBGBCR_PMC_MASK 0x6U

#define	AARCH32_DBGBCR_PMC_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x3U )

#define	AARCH32_DBGBCR_BAS(_val) ( ( _val ) << 5 )

#define	AARCH32_DBGBCR_BAS_SHIFT 5

#define	AARCH32_DBGBCR_BAS_MASK 0x1e0U

#define	AARCH32_DBGBCR_BAS_GET(_reg) ( ( ( _reg ) >> 5 ) & 0xfU )

#define	AARCH32_DBGBCR_HMC 0x2000U

#define	AARCH32_DBGBCR_SSC(_val) ( ( _val ) << 14 )

#define	AARCH32_DBGBCR_SSC_SHIFT 14

#define	AARCH32_DBGBCR_SSC_MASK 0xc000U

#define	AARCH32_DBGBCR_SSC_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U )

#define	AARCH32_DBGBCR_LBN(_val) ( ( _val ) << 16 )

#define	AARCH32_DBGBCR_LBN_SHIFT 16

#define	AARCH32_DBGBCR_LBN_MASK 0xf0000U

#define	AARCH32_DBGBCR_LBN_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_DBGBCR_BT(_val) ( ( _val ) << 20 )

#define	AARCH32_DBGBCR_BT_SHIFT 20

#define	AARCH32_DBGBCR_BT_MASK 0xf00000U

#define	AARCH32_DBGBCR_BT_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_DBGBVR_CONTEXTID(_val) ( ( _val ) << 0 )

#define	AARCH32_DBGBVR_CONTEXTID_SHIFT 0

#define	AARCH32_DBGBVR_CONTEXTID_MASK 0xffffffffU

#define	AARCH32_DBGBVR_CONTEXTID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU )

#define	AARCH32_DBGBVR_VA_31_2(_val) ( ( _val ) << 2 )

#define	AARCH32_DBGBVR_VA_31_2_SHIFT 2

#define	AARCH32_DBGBVR_VA_31_2_MASK 0xfffffffcU

#define	AARCH32_DBGBVR_VA_31_2_GET(_reg) ( ( ( _reg ) >> 2 ) & 0x3fffffffU )

#define	AARCH32_DBGBXVR_VMID_7_0(_val) ( ( _val ) << 0 )

#define	AARCH32_DBGBXVR_VMID_7_0_SHIFT 0

#define	AARCH32_DBGBXVR_VMID_7_0_MASK 0xffU

#define	AARCH32_DBGBXVR_VMID_7_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_DBGBXVR_CONTEXTID2(_val) ( ( _val ) << 0 )

#define	AARCH32_DBGBXVR_CONTEXTID2_SHIFT 0

#define	AARCH32_DBGBXVR_CONTEXTID2_MASK 0xffffffffU

#define	AARCH32_DBGBXVR_CONTEXTID2_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffU )

#define	AARCH32_DBGBXVR_VMID_15_8(_val) ( ( _val ) << 8 )

#define	AARCH32_DBGBXVR_VMID_15_8_SHIFT 8

#define	AARCH32_DBGBXVR_VMID_15_8_MASK 0xff00U

#define	AARCH32_DBGBXVR_VMID_15_8_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xffU )

#define	AARCH32_DBGCLAIMCLR_CLAIM(_val) ( ( _val ) << 0 )

#define	AARCH32_DBGCLAIMCLR_CLAIM_SHIFT 0

#define	AARCH32_DBGCLAIMCLR_CLAIM_MASK 0xffU

#define	AARCH32_DBGCLAIMCLR_CLAIM_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_DBGCLAIMSET_CLAIM(_val) ( ( _val ) << 0 )

#define	AARCH32_DBGCLAIMSET_CLAIM_SHIFT 0

#define	AARCH32_DBGCLAIMSET_CLAIM_MASK 0xffU

#define	AARCH32_DBGCLAIMSET_CLAIM_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_DBGDCCINT_TX 0x20000000U

#define	AARCH32_DBGDCCINT_RX 0x40000000U

#define	AARCH32_DBGDEVID_PCSAMPLE(_val) ( ( _val ) << 0 )

#define	AARCH32_DBGDEVID_PCSAMPLE_SHIFT 0

#define	AARCH32_DBGDEVID_PCSAMPLE_MASK 0xfU

#define	AARCH32_DBGDEVID_PCSAMPLE_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_DBGDEVID_WPADDRMASK(_val) ( ( _val ) << 4 )

#define	AARCH32_DBGDEVID_WPADDRMASK_SHIFT 4

#define	AARCH32_DBGDEVID_WPADDRMASK_MASK 0xf0U

#define	AARCH32_DBGDEVID_WPADDRMASK_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_DBGDEVID_BPADDRMASK(_val) ( ( _val ) << 8 )

#define	AARCH32_DBGDEVID_BPADDRMASK_SHIFT 8

#define	AARCH32_DBGDEVID_BPADDRMASK_MASK 0xf00U

#define	AARCH32_DBGDEVID_BPADDRMASK_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xfU )

#define	AARCH32_DBGDEVID_VECTORCATCH(_val) ( ( _val ) << 12 )

#define	AARCH32_DBGDEVID_VECTORCATCH_SHIFT 12

#define	AARCH32_DBGDEVID_VECTORCATCH_MASK 0xf000U

#define	AARCH32_DBGDEVID_VECTORCATCH_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfU )

#define	AARCH32_DBGDEVID_VIRTEXTNS(_val) ( ( _val ) << 16 )

#define	AARCH32_DBGDEVID_VIRTEXTNS_SHIFT 16

#define	AARCH32_DBGDEVID_VIRTEXTNS_MASK 0xf0000U

#define	AARCH32_DBGDEVID_VIRTEXTNS_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_DBGDEVID_DOUBLELOCK(_val) ( ( _val ) << 20 )

#define	AARCH32_DBGDEVID_DOUBLELOCK_SHIFT 20

#define	AARCH32_DBGDEVID_DOUBLELOCK_MASK 0xf00000U

#define	AARCH32_DBGDEVID_DOUBLELOCK_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_DBGDEVID_AUXREGS(_val) ( ( _val ) << 24 )

#define	AARCH32_DBGDEVID_AUXREGS_SHIFT 24

#define	AARCH32_DBGDEVID_AUXREGS_MASK 0xf000000U

#define	AARCH32_DBGDEVID_AUXREGS_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_DBGDEVID_CIDMASK(_val) ( ( _val ) << 28 )

#define	AARCH32_DBGDEVID_CIDMASK_SHIFT 28

#define	AARCH32_DBGDEVID_CIDMASK_MASK 0xf0000000U

#define	AARCH32_DBGDEVID_CIDMASK_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_DBGDEVID1_PCSROFFSET(_val) ( ( _val ) << 0 )

#define	AARCH32_DBGDEVID1_PCSROFFSET_SHIFT 0

#define	AARCH32_DBGDEVID1_PCSROFFSET_MASK 0xfU

#define	AARCH32_DBGDEVID1_PCSROFFSET_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_DBGDIDR_SE_IMP 0x1000U

#define	AARCH32_DBGDIDR_NSUHD_IMP 0x4000U

#define	AARCH32_DBGDIDR_VERSION(_val) ( ( _val ) << 16 )

#define	AARCH32_DBGDIDR_VERSION_SHIFT 16

#define	AARCH32_DBGDIDR_VERSION_MASK 0xf0000U

#define	AARCH32_DBGDIDR_VERSION_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_DBGDIDR_CTX_CMPS(_val) ( ( _val ) << 20 )

#define	AARCH32_DBGDIDR_CTX_CMPS_SHIFT 20

#define	AARCH32_DBGDIDR_CTX_CMPS_MASK 0xf00000U

#define	AARCH32_DBGDIDR_CTX_CMPS_GET(_reg) ( ( ( _reg ) >> 20 ) & 0xfU )

#define	AARCH32_DBGDIDR_BRPS(_val) ( ( _val ) << 24 )

#define	AARCH32_DBGDIDR_BRPS_SHIFT 24

#define	AARCH32_DBGDIDR_BRPS_MASK 0xf000000U

#define	AARCH32_DBGDIDR_BRPS_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xfU )

#define	AARCH32_DBGDIDR_WRPS(_val) ( ( _val ) << 28 )

#define	AARCH32_DBGDIDR_WRPS_SHIFT 28

#define	AARCH32_DBGDIDR_WRPS_MASK 0xf0000000U

#define	AARCH32_DBGDIDR_WRPS_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_DBGDRAR_VALID(_val) ( ( _val ) << 0 )

#define	AARCH32_DBGDRAR_VALID_SHIFT 0

#define	AARCH32_DBGDRAR_VALID_MASK 0x3U

#define	AARCH32_DBGDRAR_VALID_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3U )

#define	AARCH32_DBGDRAR_ROMADDR_47_12(_val) ( ( _val ) << 12 )

#define	AARCH32_DBGDRAR_ROMADDR_47_12_SHIFT 12

#define	AARCH32_DBGDRAR_ROMADDR_47_12_MASK 0xfffffffff000ULL

#define	AARCH32_DBGDRAR_ROMADDR_47_12_GET(_reg) ( ( ( _reg ) >> 12 ) & 0xfffffffffULL )

#define	AARCH32_DBGDSCREXT_MOE(_val) ( ( _val ) << 2 )

#define	AARCH32_DBGDSCREXT_MOE_SHIFT 2

#define	AARCH32_DBGDSCREXT_MOE_MASK 0x3cU

#define	AARCH32_DBGDSCREXT_MOE_GET(_reg) ( ( ( _reg ) >> 2 ) & 0xfU )

#define	AARCH32_DBGDSCREXT_ERR 0x40U

#define	AARCH32_DBGDSCREXT_UDCCDIS 0x1000U

#define	AARCH32_DBGDSCREXT_HDE 0x4000U

#define	AARCH32_DBGDSCREXT_MDBGEN 0x8000U

#define	AARCH32_DBGDSCREXT_SPIDDIS 0x10000U

#define	AARCH32_DBGDSCREXT_SPNIDDIS 0x20000U

#define	AARCH32_DBGDSCREXT_NS 0x40000U

#define	AARCH32_DBGDSCREXT_SC2 0x80000U

#define	AARCH32_DBGDSCREXT_TDA 0x200000U

#define	AARCH32_DBGDSCREXT_INTDIS(_val) ( ( _val ) << 22 )

#define	AARCH32_DBGDSCREXT_INTDIS_SHIFT 22

#define	AARCH32_DBGDSCREXT_INTDIS_MASK 0xc00000U

#define	AARCH32_DBGDSCREXT_INTDIS_GET(_reg) ( ( ( _reg ) >> 22 ) & 0x3U )

#define	AARCH32_DBGDSCREXT_TXU 0x4000000U

#define	AARCH32_DBGDSCREXT_RXO 0x8000000U

#define	AARCH32_DBGDSCREXT_TXFULL 0x20000000U

#define	AARCH32_DBGDSCREXT_RXFULL 0x40000000U

#define	AARCH32_DBGDSCREXT_TFO 0x80000000U

#define	AARCH32_DBGDSCRINT_MOE(_val) ( ( _val ) << 2 )

#define	AARCH32_DBGDSCRINT_MOE_SHIFT 2

#define	AARCH32_DBGDSCRINT_MOE_MASK 0x3cU

#define	AARCH32_DBGDSCRINT_MOE_GET(_reg) ( ( ( _reg ) >> 2 ) & 0xfU )

#define	AARCH32_DBGDSCRINT_UDCCDIS 0x1000U

#define	AARCH32_DBGDSCRINT_MDBGEN 0x8000U

#define	AARCH32_DBGDSCRINT_SPIDDIS 0x10000U

#define	AARCH32_DBGDSCRINT_SPNIDDIS 0x20000U

#define	AARCH32_DBGDSCRINT_NS 0x40000U

#define	AARCH32_DBGDSCRINT_TXFULL 0x20000000U

#define	AARCH32_DBGDSCRINT_RXFULL 0x40000000U

#define	AARCH32_DBGOSDLR_DLK 0x1U

#define	AARCH32_DBGOSLSR_OSLM_0 0x1U

#define	AARCH32_DBGOSLSR_OSLK 0x2U

#define	AARCH32_DBGOSLSR_NTT 0x4U

#define	AARCH32_DBGOSLSR_OSLM_1 0x8U

#define	AARCH32_DBGPRCR_CORENPDRQ 0x1U

#define	AARCH32_DBGVCR_SU 0x2U

#define	AARCH32_DBGVCR_U 0x2U

#define	AARCH32_DBGVCR_S 0x4U

#define	AARCH32_DBGVCR_SS 0x4U

#define	AARCH32_DBGVCR_P 0x8U

#define	AARCH32_DBGVCR_SP 0x8U

#define	AARCH32_DBGVCR_D 0x10U

#define	AARCH32_DBGVCR_SD 0x10U

#define	AARCH32_DBGVCR_I 0x40U

#define	AARCH32_DBGVCR_SI 0x40U

#define	AARCH32_DBGVCR_F 0x80U

#define	AARCH32_DBGVCR_SF 0x80U

#define	AARCH32_DBGVCR_MS 0x400U

#define	AARCH32_DBGVCR_MP 0x800U

#define	AARCH32_DBGVCR_MD 0x1000U

#define	AARCH32_DBGVCR_MI 0x4000U

#define	AARCH32_DBGVCR_MF 0x8000U

#define	AARCH32_DBGVCR_NSU 0x2000000U

#define	AARCH32_DBGVCR_NSS 0x4000000U

#define	AARCH32_DBGVCR_NSP 0x8000000U

#define	AARCH32_DBGVCR_NSD 0x10000000U

#define	AARCH32_DBGVCR_NSI 0x40000000U

#define	AARCH32_DBGVCR_NSF 0x80000000U

#define	AARCH32_DBGWCR_E 0x1U

#define	AARCH32_DBGWCR_PAC(_val) ( ( _val ) << 1 )

#define	AARCH32_DBGWCR_PAC_SHIFT 1

#define	AARCH32_DBGWCR_PAC_MASK 0x6U

#define	AARCH32_DBGWCR_PAC_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x3U )

#define	AARCH32_DBGWCR_LSC(_val) ( ( _val ) << 3 )

#define	AARCH32_DBGWCR_LSC_SHIFT 3

#define	AARCH32_DBGWCR_LSC_MASK 0x18U

#define	AARCH32_DBGWCR_LSC_GET(_reg) ( ( ( _reg ) >> 3 ) & 0x3U )

#define	AARCH32_DBGWCR_BAS(_val) ( ( _val ) << 5 )

#define	AARCH32_DBGWCR_BAS_SHIFT 5

#define	AARCH32_DBGWCR_BAS_MASK 0x1fe0U

#define	AARCH32_DBGWCR_BAS_GET(_reg) ( ( ( _reg ) >> 5 ) & 0xffU )

#define	AARCH32_DBGWCR_HMC 0x2000U

#define	AARCH32_DBGWCR_SSC(_val) ( ( _val ) << 14 )

#define	AARCH32_DBGWCR_SSC_SHIFT 14

#define	AARCH32_DBGWCR_SSC_MASK 0xc000U

#define	AARCH32_DBGWCR_SSC_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U )

#define	AARCH32_DBGWCR_LBN(_val) ( ( _val ) << 16 )

#define	AARCH32_DBGWCR_LBN_SHIFT 16

#define	AARCH32_DBGWCR_LBN_MASK 0xf0000U

#define	AARCH32_DBGWCR_LBN_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_DBGWCR_WT 0x100000U

#define	AARCH32_DBGWCR_MASK(_val) ( ( _val ) << 24 )

#define	AARCH32_DBGWCR_MASK_SHIFT 24

#define	AARCH32_DBGWCR_MASK_MASK 0x1f000000U

#define	AARCH32_DBGWCR_MASK_GET(_reg) ( ( ( _reg ) >> 24 ) & 0x1fU )

#define	AARCH32_DBGWVR_VA(_val) ( ( _val ) << 2 )

#define	AARCH32_DBGWVR_VA_SHIFT 2

#define	AARCH32_DBGWVR_VA_MASK 0xfffffffcU

#define	AARCH32_DBGWVR_VA_GET(_reg) ( ( ( _reg ) >> 2 ) & 0x3fffffffU )

#define	AARCH32_DSPSR_M_4_0(_val) ( ( _val ) << 0 )

#define	AARCH32_DSPSR_M_4_0_SHIFT 0

#define	AARCH32_DSPSR_M_4_0_MASK 0x1fU

#define	AARCH32_DSPSR_M_4_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1fU )

#define	AARCH32_DSPSR_T 0x20U

#define	AARCH32_DSPSR_F 0x40U

#define	AARCH32_DSPSR_I 0x80U

#define	AARCH32_DSPSR_A 0x100U

#define	AARCH32_DSPSR_E 0x200U

#define	AARCH32_DSPSR_IT_7_2(_val) ( ( _val ) << 10 )

#define	AARCH32_DSPSR_IT_7_2_SHIFT 10

#define	AARCH32_DSPSR_IT_7_2_MASK 0xfc00U

#define	AARCH32_DSPSR_IT_7_2_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3fU )

#define	AARCH32_DSPSR_GE(_val) ( ( _val ) << 16 )

#define	AARCH32_DSPSR_GE_SHIFT 16

#define	AARCH32_DSPSR_GE_MASK 0xf0000U

#define	AARCH32_DSPSR_GE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xfU )

#define	AARCH32_DSPSR_IL 0x100000U

#define	AARCH32_DSPSR_SS 0x200000U

#define	AARCH32_DSPSR_PAN 0x400000U

#define	AARCH32_DSPSR_SSBS 0x800000U

#define	AARCH32_DSPSR_DIT 0x1000000U

#define	AARCH32_DSPSR_IT_1_0(_val) ( ( _val ) << 25 )

#define	AARCH32_DSPSR_IT_1_0_SHIFT 25

#define	AARCH32_DSPSR_IT_1_0_MASK 0x6000000U

#define	AARCH32_DSPSR_IT_1_0_GET(_reg) ( ( ( _reg ) >> 25 ) & 0x3U )

#define	AARCH32_DSPSR_Q 0x8000000U

#define	AARCH32_DSPSR_V 0x10000000U

#define	AARCH32_DSPSR_C 0x20000000U

#define	AARCH32_DSPSR_Z 0x40000000U

#define	AARCH32_DSPSR_N 0x80000000U

#define	AARCH32_HDCR_HPMN(_val) ( ( _val ) << 0 )

#define	AARCH32_HDCR_HPMN_SHIFT 0

#define	AARCH32_HDCR_HPMN_MASK 0x1fU

#define	AARCH32_HDCR_HPMN_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1fU )

#define	AARCH32_HDCR_TPMCR 0x20U

#define	AARCH32_HDCR_TPM 0x40U

#define	AARCH32_HDCR_HPME 0x80U

#define	AARCH32_HDCR_TDE 0x100U

#define	AARCH32_HDCR_TDA 0x200U

#define	AARCH32_HDCR_TDOSA 0x400U

#define	AARCH32_HDCR_TDRA 0x800U

#define	AARCH32_HDCR_HPMD 0x20000U

#define	AARCH32_HDCR_TTRF 0x80000U

#define	AARCH32_HDCR_HCCD 0x800000U

#define	AARCH32_HDCR_HLP 0x4000000U

#define	AARCH32_HDCR_TDCC 0x8000000U

#define	AARCH32_HDCR_MTPME 0x10000000U

#define	AARCH32_HTRFCR_E0HTRE 0x1U

#define	AARCH32_HTRFCR_E2TRE 0x2U

#define	AARCH32_HTRFCR_CX 0x8U

#define	AARCH32_HTRFCR_TS(_val) ( ( _val ) << 5 )

#define	AARCH32_HTRFCR_TS_SHIFT 5

#define	AARCH32_HTRFCR_TS_MASK 0x60U

#define	AARCH32_HTRFCR_TS_GET(_reg) ( ( ( _reg ) >> 5 ) & 0x3U )

#define	AARCH32_PMMIR_SLOTS(_val) ( ( _val ) << 0 )

#define	AARCH32_PMMIR_SLOTS_SHIFT 0

#define	AARCH32_PMMIR_SLOTS_MASK 0xffU

#define	AARCH32_PMMIR_SLOTS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_SDCR_SPD(_val) ( ( _val ) << 14 )

#define	AARCH32_SDCR_SPD_SHIFT 14

#define	AARCH32_SDCR_SPD_MASK 0xc000U

#define	AARCH32_SDCR_SPD_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U )

#define	AARCH32_SDCR_SPME 0x20000U

#define	AARCH32_SDCR_STE 0x40000U

#define	AARCH32_SDCR_TTRF 0x80000U

#define	AARCH32_SDCR_EDAD 0x100000U

#define	AARCH32_SDCR_EPMAD 0x200000U

#define	AARCH32_SDCR_SCCD 0x800000U

#define	AARCH32_SDCR_TDCC 0x8000000U

#define	AARCH32_SDCR_MTPME 0x10000000U

#define	AARCH32_SDER_SUIDEN 0x1U

#define	AARCH32_SDER_SUNIDEN 0x2U

#define	AARCH32_TRFCR_E0TRE 0x1U

#define	AARCH32_TRFCR_E1TRE 0x2U

#define	AARCH32_TRFCR_TS(_val) ( ( _val ) << 5 )

#define	AARCH32_TRFCR_TS_SHIFT 5

#define	AARCH32_TRFCR_TS_MASK 0x60U

#define	AARCH32_TRFCR_TS_GET(_reg) ( ( ( _reg ) >> 5 ) & 0x3U )

#define	AARCH32_PMCCFILTR_NSH 0x8000000U

#define	AARCH32_PMCCFILTR_NSU 0x10000000U

#define	AARCH32_PMCCFILTR_NSK 0x20000000U

#define	AARCH32_PMCCFILTR_U 0x40000000U

#define	AARCH32_PMCCFILTR_P 0x80000000U

#define	AARCH32_PMCCNTR_CCNT(_val) ( ( _val ) << 0 )

#define	AARCH32_PMCCNTR_CCNT_SHIFT 0

#define	AARCH32_PMCCNTR_CCNT_MASK 0xffffffffffffffffULL

#define	AARCH32_PMCCNTR_CCNT_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffffffffffULL )

#define	AARCH32_PMCNTENCLR_C 0x80000000U

#define	AARCH32_PMCNTENSET_C 0x80000000U

#define	AARCH32_PMCR_E 0x1U

#define	AARCH32_PMCR_P 0x2U

#define	AARCH32_PMCR_C 0x4U

#define	AARCH32_PMCR_D 0x8U

#define	AARCH32_PMCR_X 0x10U

#define	AARCH32_PMCR_DP 0x20U

#define	AARCH32_PMCR_LC 0x40U

#define	AARCH32_PMCR_LP 0x80U

#define	AARCH32_PMCR_N(_val) ( ( _val ) << 11 )

#define	AARCH32_PMCR_N_SHIFT 11

#define	AARCH32_PMCR_N_MASK 0xf800U

#define	AARCH32_PMCR_N_GET(_reg) ( ( ( _reg ) >> 11 ) & 0x1fU )

#define	AARCH32_PMCR_IDCODE(_val) ( ( _val ) << 16 )

#define	AARCH32_PMCR_IDCODE_SHIFT 16

#define	AARCH32_PMCR_IDCODE_MASK 0xff0000U

#define	AARCH32_PMCR_IDCODE_GET(_reg) ( ( ( _reg ) >> 16 ) & 0xffU )

#define	AARCH32_PMCR_IMP(_val) ( ( _val ) << 24 )

#define	AARCH32_PMCR_IMP_SHIFT 24

#define	AARCH32_PMCR_IMP_MASK 0xff000000U

#define	AARCH32_PMCR_IMP_GET(_reg) ( ( ( _reg ) >> 24 ) & 0xffU )

#define	AARCH32_PMEVTYPER_EVTCOUNT_9_0(_val) ( ( _val ) << 0 )

#define	AARCH32_PMEVTYPER_EVTCOUNT_9_0_SHIFT 0

#define	AARCH32_PMEVTYPER_EVTCOUNT_9_0_MASK 0x3ffU

#define	AARCH32_PMEVTYPER_EVTCOUNT_9_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3ffU )

#define	AARCH32_PMEVTYPER_EVTCOUNT_15_10(_val) ( ( _val ) << 10 )

#define	AARCH32_PMEVTYPER_EVTCOUNT_15_10_SHIFT 10

#define	AARCH32_PMEVTYPER_EVTCOUNT_15_10_MASK 0xfc00U

#define	AARCH32_PMEVTYPER_EVTCOUNT_15_10_GET(_reg) ( ( ( _reg ) >> 10 ) & 0x3fU )

#define	AARCH32_PMEVTYPER_MT 0x2000000U

#define	AARCH32_PMEVTYPER_NSH 0x8000000U

#define	AARCH32_PMEVTYPER_NSU 0x10000000U

#define	AARCH32_PMEVTYPER_NSK 0x20000000U

#define	AARCH32_PMEVTYPER_U 0x40000000U

#define	AARCH32_PMEVTYPER_P 0x80000000U

#define	AARCH32_PMINTENCLR_C 0x80000000U

#define	AARCH32_PMINTENSET_C 0x80000000U

#define	AARCH32_PMOVSR_C 0x80000000U

#define	AARCH32_PMOVSSET_C 0x80000000U

#define	AARCH32_PMSELR_SEL(_val) ( ( _val ) << 0 )

#define	AARCH32_PMSELR_SEL_SHIFT 0

#define	AARCH32_PMSELR_SEL_MASK 0x1fU

#define	AARCH32_PMSELR_SEL_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x1fU )

#define	AARCH32_PMUSERENR_EN 0x1U

#define	AARCH32_PMUSERENR_SW 0x2U

#define	AARCH32_PMUSERENR_CR 0x4U

#define	AARCH32_PMUSERENR_ER 0x8U

#define	AARCH32_AMCFGR_N(_val) ( ( _val ) << 0 )

#define	AARCH32_AMCFGR_N_SHIFT 0

#define	AARCH32_AMCFGR_N_MASK 0xffU

#define	AARCH32_AMCFGR_N_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_AMCFGR_SIZE(_val) ( ( _val ) << 8 )

#define	AARCH32_AMCFGR_SIZE_SHIFT 8

#define	AARCH32_AMCFGR_SIZE_MASK 0x3f00U

#define	AARCH32_AMCFGR_SIZE_GET(_reg) ( ( ( _reg ) >> 8 ) & 0x3fU )

#define	AARCH32_AMCFGR_HDBG 0x1000000U

#define	AARCH32_AMCFGR_NCG(_val) ( ( _val ) << 28 )

#define	AARCH32_AMCFGR_NCG_SHIFT 28

#define	AARCH32_AMCFGR_NCG_MASK 0xf0000000U

#define	AARCH32_AMCFGR_NCG_GET(_reg) ( ( ( _reg ) >> 28 ) & 0xfU )

#define	AARCH32_AMCGCR_CG0NC(_val) ( ( _val ) << 0 )

#define	AARCH32_AMCGCR_CG0NC_SHIFT 0

#define	AARCH32_AMCGCR_CG0NC_MASK 0xffU

#define	AARCH32_AMCGCR_CG0NC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_AMCGCR_CG1NC(_val) ( ( _val ) << 8 )

#define	AARCH32_AMCGCR_CG1NC_SHIFT 8

#define	AARCH32_AMCGCR_CG1NC_MASK 0xff00U

#define	AARCH32_AMCGCR_CG1NC_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xffU )

#define	AARCH32_AMCR_HDBG 0x400U

#define	AARCH32_AMCR_CG1RZ 0x20000U

#define	AARCH32_AMEVCNTR0_ACNT(_val) ( ( _val ) << 0 )

#define	AARCH32_AMEVCNTR0_ACNT_SHIFT 0

#define	AARCH32_AMEVCNTR0_ACNT_MASK 0xffffffffffffffffULL

#define	AARCH32_AMEVCNTR0_ACNT_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffffffffffULL )

#define	AARCH32_AMEVCNTR1_ACNT(_val) ( ( _val ) << 0 )

#define	AARCH32_AMEVCNTR1_ACNT_SHIFT 0

#define	AARCH32_AMEVCNTR1_ACNT_MASK 0xffffffffffffffffULL

#define	AARCH32_AMEVCNTR1_ACNT_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffffffffffffffULL )

#define	AARCH32_AMEVTYPER0_EVTCOUNT(_val) ( ( _val ) << 0 )

#define	AARCH32_AMEVTYPER0_EVTCOUNT_SHIFT 0

#define	AARCH32_AMEVTYPER0_EVTCOUNT_MASK 0xffffU

#define	AARCH32_AMEVTYPER0_EVTCOUNT_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU )

#define	AARCH32_AMEVTYPER1_EVTCOUNT(_val) ( ( _val ) << 0 )

#define	AARCH32_AMEVTYPER1_EVTCOUNT_SHIFT 0

#define	AARCH32_AMEVTYPER1_EVTCOUNT_MASK 0xffffU

#define	AARCH32_AMEVTYPER1_EVTCOUNT_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU )

#define	AARCH32_AMUSERENR_EN 0x1U

#define	AARCH32_DISR_FS_3_0(_val) ( ( _val ) << 0 )

#define	AARCH32_DISR_FS_3_0_SHIFT 0

#define	AARCH32_DISR_FS_3_0_MASK 0xfU

#define	AARCH32_DISR_FS_3_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_DISR_DFSC(_val) ( ( _val ) << 0 )

#define	AARCH32_DISR_DFSC_SHIFT 0

#define	AARCH32_DISR_DFSC_MASK 0x3fU

#define	AARCH32_DISR_DFSC_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU )

#define	AARCH32_DISR_STATUS(_val) ( ( _val ) << 0 )

#define	AARCH32_DISR_STATUS_SHIFT 0

#define	AARCH32_DISR_STATUS_MASK 0x3fU

#define	AARCH32_DISR_STATUS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU )

#define	AARCH32_DISR_EA 0x200U

#define	AARCH32_DISR_LPAE 0x200U

#define	AARCH32_DISR_FS_4 0x400U

#define	AARCH32_DISR_AET_0(_val) ( ( _val ) << 10 )

#define	AARCH32_DISR_AET_SHIFT_0 10

#define	AARCH32_DISR_AET_MASK_0 0xc00U

#define	AARCH32_DISR_AET_GET_0(_reg) ( ( ( _reg ) >> 10 ) & 0x3U )

#define	AARCH32_DISR_EXT 0x1000U

#define	AARCH32_DISR_AET_1(_val) ( ( _val ) << 14 )

#define	AARCH32_DISR_AET_SHIFT_1 14

#define	AARCH32_DISR_AET_MASK_1 0xc000U

#define	AARCH32_DISR_AET_GET_1(_reg) ( ( ( _reg ) >> 14 ) & 0x3U )

#define	AARCH32_DISR_A 0x80000000U

#define	AARCH32_ERRIDR_NUM(_val) ( ( _val ) << 0 )

#define	AARCH32_ERRIDR_NUM_SHIFT 0

#define	AARCH32_ERRIDR_NUM_MASK 0xffffU

#define	AARCH32_ERRIDR_NUM_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU )

#define	AARCH32_ERRSELR_SEL(_val) ( ( _val ) << 0 )

#define	AARCH32_ERRSELR_SEL_SHIFT 0

#define	AARCH32_ERRSELR_SEL_MASK 0xffffU

#define	AARCH32_ERRSELR_SEL_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffffU )

#define	AARCH32_VDFSR_EXT 0x1000U

#define	AARCH32_VDFSR_AET(_val) ( ( _val ) << 14 )

#define	AARCH32_VDFSR_AET_SHIFT 14

#define	AARCH32_VDFSR_AET_MASK 0xc000U

#define	AARCH32_VDFSR_AET_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U )

#define	AARCH32_VDISR_FS_3_0(_val) ( ( _val ) << 0 )

#define	AARCH32_VDISR_FS_3_0_SHIFT 0

#define	AARCH32_VDISR_FS_3_0_MASK 0xfU

#define	AARCH32_VDISR_FS_3_0_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xfU )

#define	AARCH32_VDISR_STATUS(_val) ( ( _val ) << 0 )

#define	AARCH32_VDISR_STATUS_SHIFT 0

#define	AARCH32_VDISR_STATUS_MASK 0x3fU

#define	AARCH32_VDISR_STATUS_GET(_reg) ( ( ( _reg ) >> 0 ) & 0x3fU )

#define	AARCH32_VDISR_LPAE 0x200U

#define	AARCH32_VDISR_FS_4 0x400U

#define	AARCH32_VDISR_EXT 0x1000U

#define	AARCH32_VDISR_AET(_val) ( ( _val ) << 14 )

#define	AARCH32_VDISR_AET_SHIFT 14

#define	AARCH32_VDISR_AET_MASK 0xc000U

#define	AARCH32_VDISR_AET_GET(_reg) ( ( ( _reg ) >> 14 ) & 0x3U )

#define	AARCH32_VDISR_A 0x80000000U

#define	AARCH32_CNTHCTL_PL1PCTEN 0x1U

#define	AARCH32_CNTHCTL_PL1PCEN 0x2U

#define	AARCH32_CNTHCTL_EVNTEN 0x4U

#define	AARCH32_CNTHCTL_EVNTDIR 0x8U

#define	AARCH32_CNTHCTL_EVNTI(_val) ( ( _val ) << 4 )

#define	AARCH32_CNTHCTL_EVNTI_SHIFT 4

#define	AARCH32_CNTHCTL_EVNTI_MASK 0xf0U

#define	AARCH32_CNTHCTL_EVNTI_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_CNTHCTL_EVNTIS 0x20000U

#define	AARCH32_CNTHP_CTL_ENABLE 0x1U

#define	AARCH32_CNTHP_CTL_IMASK 0x2U

#define	AARCH32_CNTHP_CTL_ISTATUS 0x4U

#define	AARCH32_CNTHPS_CTL_ENABLE 0x1U

#define	AARCH32_CNTHPS_CTL_IMASK 0x2U

#define	AARCH32_CNTHPS_CTL_ISTATUS 0x4U

#define	AARCH32_CNTHV_CTL_ENABLE 0x1U

#define	AARCH32_CNTHV_CTL_IMASK 0x2U

#define	AARCH32_CNTHV_CTL_ISTATUS 0x4U

#define	AARCH32_CNTHVS_CTL_ENABLE 0x1U

#define	AARCH32_CNTHVS_CTL_IMASK 0x2U

#define	AARCH32_CNTHVS_CTL_ISTATUS 0x4U

#define	AARCH32_CNTKCTL_PL0PCTEN 0x1U

#define	AARCH32_CNTKCTL_PL0VCTEN 0x2U

#define	AARCH32_CNTKCTL_EVNTEN 0x4U

#define	AARCH32_CNTKCTL_EVNTDIR 0x8U

#define	AARCH32_CNTKCTL_EVNTI(_val) ( ( _val ) << 4 )

#define	AARCH32_CNTKCTL_EVNTI_SHIFT 4

#define	AARCH32_CNTKCTL_EVNTI_MASK 0xf0U

#define	AARCH32_CNTKCTL_EVNTI_GET(_reg) ( ( ( _reg ) >> 4 ) & 0xfU )

#define	AARCH32_CNTKCTL_PL0VTEN 0x100U

#define	AARCH32_CNTKCTL_PL0PTEN 0x200U

#define	AARCH32_CNTKCTL_EVNTIS 0x20000U

#define	AARCH32_CNTP_CTL_ENABLE 0x1U

#define	AARCH32_CNTP_CTL_IMASK 0x2U

#define	AARCH32_CNTP_CTL_ISTATUS 0x4U

#define	AARCH32_CNTV_CTL_ENABLE 0x1U

#define	AARCH32_CNTV_CTL_IMASK 0x2U

#define	AARCH32_CNTV_CTL_ISTATUS 0x4U

#define	AARCH32_HMPUIR_REGION(_val) ( ( _val ) << 0 )

#define	AARCH32_HMPUIR_REGION_SHIFT 0

#define	AARCH32_HMPUIR_REGION_MASK 0xffU

#define	AARCH32_HMPUIR_REGION_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_HPRBAR_XN 0x1U

#define	AARCH32_HPRBAR_AP_2_1(_val) ( ( _val ) << 1 )

#define	AARCH32_HPRBAR_AP_2_1_SHIFT 1

#define	AARCH32_HPRBAR_AP_2_1_MASK 0x6U

#define	AARCH32_HPRBAR_AP_2_1_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x3U )

#define	AARCH32_HPRBAR_SH_1_0(_val) ( ( _val ) << 3 )

#define	AARCH32_HPRBAR_SH_1_0_SHIFT 3

#define	AARCH32_HPRBAR_SH_1_0_MASK 0x18U

#define	AARCH32_HPRBAR_SH_1_0_GET(_reg) ( ( ( _reg ) >> 3 ) & 0x3U )

#define	AARCH32_HPRBAR_BASE(_val) ( ( _val ) << 6 )

#define	AARCH32_HPRBAR_BASE_SHIFT 6

#define	AARCH32_HPRBAR_BASE_MASK 0xffffffc0U

#define	AARCH32_HPRBAR_BASE_GET(_reg) ( ( ( _reg ) >> 6 ) & 0x3ffffffU )

#define	AARCH32_HPRLAR_EN 0x1U

#define	AARCH32_HPRLAR_ATTRINDX_2_0(_val) ( ( _val ) << 1 )

#define	AARCH32_HPRLAR_ATTRINDX_2_0_SHIFT 1

#define	AARCH32_HPRLAR_ATTRINDX_2_0_MASK 0xeU

#define	AARCH32_HPRLAR_ATTRINDX_2_0_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7U )

#define	AARCH32_HPRLAR_LIMIT(_val) ( ( _val ) << 6 )

#define	AARCH32_HPRLAR_LIMIT_SHIFT 6

#define	AARCH32_HPRLAR_LIMIT_MASK 0xffffffc0U

#define	AARCH32_HPRLAR_LIMIT_GET(_reg) ( ( ( _reg ) >> 6 ) & 0x3ffffffU )

#define	AARCH32_HPRSELR_REGION(_val) ( ( _val ) << 0 )

#define	AARCH32_HPRSELR_REGION_SHIFT 0

#define	AARCH32_HPRSELR_REGION_MASK 0xffU

#define	AARCH32_HPRSELR_REGION_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

#define	AARCH32_MPUIR_REGION(_val) ( ( _val ) << 8 )

#define	AARCH32_MPUIR_REGION_SHIFT 8

#define	AARCH32_MPUIR_REGION_MASK 0xff00U

#define	AARCH32_MPUIR_REGION_GET(_reg) ( ( ( _reg ) >> 8 ) & 0xffU )

#define	AARCH32_PRBAR_XN 0x1U

#define	AARCH32_PRBAR_AP_2_1(_val) ( ( _val ) << 1 )

#define	AARCH32_PRBAR_AP_2_1_SHIFT 1

#define	AARCH32_PRBAR_AP_2_1_MASK 0x6U

#define	AARCH32_PRBAR_AP_2_1_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x3U )

#define	AARCH32_PRBAR_SH_1_0(_val) ( ( _val ) << 3 )

#define	AARCH32_PRBAR_SH_1_0_SHIFT 3

#define	AARCH32_PRBAR_SH_1_0_MASK 0x18U

#define	AARCH32_PRBAR_SH_1_0_GET(_reg) ( ( ( _reg ) >> 3 ) & 0x3U )

#define	AARCH32_PRBAR_BASE(_val) ( ( _val ) << 6 )

#define	AARCH32_PRBAR_BASE_SHIFT 6

#define	AARCH32_PRBAR_BASE_MASK 0xffffffc0U

#define	AARCH32_PRBAR_BASE_GET(_reg) ( ( ( _reg ) >> 6 ) & 0x3ffffffU )

#define	AARCH32_PRLAR_EN 0x1U

#define	AARCH32_PRLAR_ATTRINDX_2_0(_val) ( ( _val ) << 1 )

#define	AARCH32_PRLAR_ATTRINDX_2_0_SHIFT 1

#define	AARCH32_PRLAR_ATTRINDX_2_0_MASK 0xeU

#define	AARCH32_PRLAR_ATTRINDX_2_0_GET(_reg) ( ( ( _reg ) >> 1 ) & 0x7U )

#define	AARCH32_PRLAR_LIMIT(_val) ( ( _val ) << 6 )

#define	AARCH32_PRLAR_LIMIT_SHIFT 6

#define	AARCH32_PRLAR_LIMIT_MASK 0xffffffc0U

#define	AARCH32_PRLAR_LIMIT_GET(_reg) ( ( ( _reg ) >> 6 ) & 0x3ffffffU )

#define	AARCH32_PRSELR_REGION(_val) ( ( _val ) << 0 )

#define	AARCH32_PRSELR_REGION_SHIFT 0

#define	AARCH32_PRSELR_REGION_MASK 0xffU

#define	AARCH32_PRSELR_REGION_GET(_reg) ( ( ( _reg ) >> 0 ) & 0xffU )

Detailed Description

This header file provides the API to read and write the AArch32 system registers.

Macros

Detailed Description