xil_cache.c File Reference

#include "xil_cache.h"
#include "xil_io.h"
#include "xpseudo_asm.h"
#include "xparameters.h"
#include "xreg_cortexa53.h"
#include "xil_exception.h"
#include "bspconfig.h"

Macros
#define	IRQ_FIQ_MASK   0xC0U /* Mask IRQ and FIQ interrupts in cpsr */

Functions
void	Xil_DCacheEnable (void)
	Enable the Data cache.
void	Xil_DCacheDisable (void)
	Disable the Data cache.
void	Xil_DCacheInvalidate (void)
	Invalidate the Data cache. The contents present in the cache are cleaned and invalidated.
void	Xil_DCacheInvalidateLine (INTPTR adr)
	Invalidate a Data cache line. The cacheline is cleaned and invalidated.
void	Xil_DCacheInvalidateRange (INTPTR adr, INTPTR len)
	Invalidate the Data cache for the given address range. The cachelines present in the adderss range are cleaned and invalidated.
void	Xil_DCacheFlush (void)
	Flush the Data cache.
void	Xil_DCacheFlushLine (INTPTR adr)
	Flush a Data cache line. If the byte specified by the address (adr) is cached by the Data cache, the cacheline containing that byte is invalidated. If the cacheline is modified (dirty), the entire contents of the cacheline are written to system memory before the line is invalidated.
void	Xil_ICacheEnable (void)
	Enable the instruction cache.
void	Xil_ICacheDisable (void)
	Disable the instruction cache.
void	Xil_ICacheInvalidate (void)
	Invalidate the entire instruction cache.
void	Xil_ICacheInvalidateLine (INTPTR adr)
	Invalidate an instruction cache line. If the instruction specified by the parameter adr is cached by the instruction cache, the cacheline containing that instruction is invalidated.
void	Xil_ICacheInvalidateRange (INTPTR adr, INTPTR len)
	Invalidate the instruction cache for the given address range. If the instructions specified by the address range are cached by the instrunction cache, the cachelines containing those instructions are invalidated.
void	Xil_ConfigureL1Prefetch (u8 num)
	Configure the maximum number of outstanding data prefetches allowed in L1 cache.

Detailed Description

Contains required functions for the ARM cache functionality.

MODIFICATION HISTORY:

Ver    Who Date     Changes
----- ---- -------- -----------------------------------------------
5.0     pkp  05/29/14 First release
5.5 pkp  04/15/16 Updated the Xil_DCacheInvalidate,
                  Xil_DCacheInvalidateLine and Xil_DCacheInvalidateRange
                  functions description for proper explanation
6.2   pkp    01/22/17 Added support for EL1 non-secure
6.2   asa  01/31/17 The existing Xil_DCacheDisable API first flushes the
                  D caches and then disables it. The problem with that is,
                  potentially there will be a small window after the cache
                  flush operation and before the we disable D caches where
                  we might have valid data in cache lines. In such a
                  scenario disabling the D cache can lead to unknown behavior.
                  The ideal solution to this is to use assembly code for
                  the complete API and avoid any memory accesses. But with
                  that we will end up having a huge amount on assembly code
                  which is not maintainable. Changes are done to use a mix
                  of assembly and C code. All local variables are put in
                  registers. Also function calls are avoided in the API to
                  avoid using stack memory.
                  These changes fix CR#966220.
6.2  mus  02/13/17  The new api Xil_ConfigureL1Prefetch is added to disable pre-fetching/configure
                    the maximum number of outstanding data prefetches allowed in
                    L1 cache system.It fixes CR#967864.
6.6  mus  02/27/18  Updated Xil_DCacheInvalidateRange and
                  Xil_ICacheInvalidateRange APIs to change the data type of
                  "cacheline" variable as "INTPTR", This change has been done
                  to avoid the truncation of upper DDR addresses to 32 bit.It
                  fixes CR#995581.
6.6  mus  03/15/18  By default CPUACTLR_EL1 is accessible only from EL3, it
                  results into abort if accessed from EL1 non secure privilege
                  level. Updated Xil_ConfigureL1Prefetch function to access
                  CPUACTLR_EL1 only for EL3.
6.8  mn   08/01/18  Optimize the Xil_DCacheInvalidateRange() function to remove
                    redundant operations
6.8  asa  09/15/18  Fix bug in the Xil_DCacheInvalidateRange API introduced while
                    making optimizations in the previous patch. This change fixes
                    CR-1008926.
7.0 mus  10/12/18  Updated Xil_DCacheInvalidateLine and Xil_DCacheInvalidateRange
                   APIs to replace IVAC instruction with CIVAC. So that, these
                   APIs will always do flush + invalidate in case of Cortexa53 as
                   well as Cortexa72 processor.
7.1 mus  09/17/19  Xil_DCacheFlushRange and Xil_DCacheInvalidateRange are executing
                   same functionality (clean + validate). Removed
                   Xil_DCacheFlushRange function implementation and defined it as
                   macro. Xil_DCacheFlushRange macro points to the
                   Xil_DCacheInvalidateRange API to avoid code duplication.