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RTEMS 6.1-rc1
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RTEMS 6.1-rc1
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PLL configuration for System. More...
#include <fsl_clock.h>
Data Fields | |
| uint8_t | loopDivider |
| uint32_t | numerator |
| uint32_t | denominator |
| uint8_t | src |
| uint16_t | ss_stop |
| uint8_t | ss_enable |
| uint16_t | ss_step |
PLL configuration for System.
| uint32_t _clock_sys_pll_config::denominator |
30 bit denominator of fractional loop divider
| uint8_t _clock_sys_pll_config::loopDivider |
PLL loop divider. Intended to be 1 (528M). 0 - Fout=Fref*20; 1 - Fout=Fref*22
| uint32_t _clock_sys_pll_config::numerator |
30 bit numerator of fractional loop divider.
| uint8_t _clock_sys_pll_config::src |
Pll clock source, reference _clock_pll_clk_src
| uint8_t _clock_sys_pll_config::ss_enable |
Enable spread spectrum modulation
| uint16_t _clock_sys_pll_config::ss_step |
Step value to get frequency change step.
| uint16_t _clock_sys_pll_config::ss_stop |
Stop value to get frequency change.
1.9.4