RTEMS 6.1-rc1
stm32h7xx_hal_smbus.h
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1
19/* Define to prevent recursive inclusion -------------------------------------*/
20#ifndef STM32H7xx_HAL_SMBUS_H
21#define STM32H7xx_HAL_SMBUS_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27/* Includes ------------------------------------------------------------------*/
28#include "stm32h7xx_hal_def.h"
29
38/* Exported types ------------------------------------------------------------*/
49typedef struct
50{
51 uint32_t Timing;
54 uint32_t AnalogFilter;
57 uint32_t OwnAddress1;
60 uint32_t AddressingMode;
63 uint32_t DualAddressMode;
66 uint32_t OwnAddress2;
69 uint32_t OwnAddress2Masks;
73 uint32_t GeneralCallMode;
76 uint32_t NoStretchMode;
79 uint32_t PacketErrorCheckMode;
82 uint32_t PeripheralMode;
85 uint32_t SMBusTimeout;
89} SMBUS_InitTypeDef;
99#define HAL_SMBUS_STATE_RESET (0x00000000U)
100#define HAL_SMBUS_STATE_READY (0x00000001U)
101#define HAL_SMBUS_STATE_BUSY (0x00000002U)
102#define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U)
103#define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U)
104#define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U)
105#define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U)
106#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U)
107#define HAL_SMBUS_STATE_ERROR (0x00000004U)
108#define HAL_SMBUS_STATE_LISTEN (0x00000008U)
118#define HAL_SMBUS_ERROR_NONE (0x00000000U)
119#define HAL_SMBUS_ERROR_BERR (0x00000001U)
120#define HAL_SMBUS_ERROR_ARLO (0x00000002U)
121#define HAL_SMBUS_ERROR_ACKF (0x00000004U)
122#define HAL_SMBUS_ERROR_OVR (0x00000008U)
123#define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U)
124#define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U)
125#define HAL_SMBUS_ERROR_ALERT (0x00000040U)
126#define HAL_SMBUS_ERROR_PECERR (0x00000080U)
127#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
128#define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U)
129#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
130#define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U)
140#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
141typedef struct __SMBUS_HandleTypeDef
142#else
143typedef struct
144#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
145{
146 I2C_TypeDef *Instance;
148 SMBUS_InitTypeDef Init;
150 uint8_t *pBuffPtr;
152 uint16_t XferSize;
154 __IO uint16_t XferCount;
156 __IO uint32_t XferOptions;
158 __IO uint32_t PreviousState;
160 HAL_LockTypeDef Lock;
162 __IO uint32_t State;
164 __IO uint32_t ErrorCode;
166#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
167 void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
169 void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
171 void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
173 void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
175 void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
177 void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
180 void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
183 void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
185 void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);
188#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
189} SMBUS_HandleTypeDef;
190
191#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
195typedef enum
196{
197 HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U,
198 HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U,
199 HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U,
200 HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U,
201 HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U,
202 HAL_SMBUS_ERROR_CB_ID = 0x05U,
204 HAL_SMBUS_MSPINIT_CB_ID = 0x06U,
205 HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U
207} HAL_SMBUS_CallbackIDTypeDef;
208
212typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus);
214typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection,
215 uint16_t AddrMatchCode);
218#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
226/* Exported constants --------------------------------------------------------*/
227
237#define SMBUS_ANALOGFILTER_ENABLE (0x00000000U)
238#define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
247#define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U)
248#define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U)
258#define SMBUS_DUALADDRESS_DISABLE (0x00000000U)
259#define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
269#define SMBUS_OA2_NOMASK ((uint8_t)0x00U)
270#define SMBUS_OA2_MASK01 ((uint8_t)0x01U)
271#define SMBUS_OA2_MASK02 ((uint8_t)0x02U)
272#define SMBUS_OA2_MASK03 ((uint8_t)0x03U)
273#define SMBUS_OA2_MASK04 ((uint8_t)0x04U)
274#define SMBUS_OA2_MASK05 ((uint8_t)0x05U)
275#define SMBUS_OA2_MASK06 ((uint8_t)0x06U)
276#define SMBUS_OA2_MASK07 ((uint8_t)0x07U)
286#define SMBUS_GENERALCALL_DISABLE (0x00000000U)
287#define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN
296#define SMBUS_NOSTRETCH_DISABLE (0x00000000U)
297#define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
306#define SMBUS_PEC_DISABLE (0x00000000U)
307#define SMBUS_PEC_ENABLE I2C_CR1_PECEN
316#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN
317#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U)
318#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN
328#define SMBUS_SOFTEND_MODE (0x00000000U)
329#define SMBUS_RELOAD_MODE I2C_CR2_RELOAD
330#define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND
331#define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE
341#define SMBUS_NO_STARTSTOP (0x00000000U)
342#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
343#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
344#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
354/* List of XferOptions in usage of :
355 * 1- Restart condition when direction change
356 * 2- No Restart condition in other use cases
357 */
358#define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE
359#define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
360#define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
361#define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE
362#define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE))
363#define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
364#define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
365
366/* List of XferOptions in usage of :
367 * 1- Restart condition in all use cases (direction change or not)
368 */
369#define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU)
370#define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U)
371#define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U)
372#define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U)
384#define SMBUS_IT_ERRI I2C_CR1_ERRIE
385#define SMBUS_IT_TCI I2C_CR1_TCIE
386#define SMBUS_IT_STOPI I2C_CR1_STOPIE
387#define SMBUS_IT_NACKI I2C_CR1_NACKIE
388#define SMBUS_IT_ADDRI I2C_CR1_ADDRIE
389#define SMBUS_IT_RXI I2C_CR1_RXIE
390#define SMBUS_IT_TXI I2C_CR1_TXIE
391#define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \
392 SMBUS_IT_NACKI | SMBUS_IT_TXI)
393#define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \
394 SMBUS_IT_RXI)
395#define SMBUS_IT_ALERT (SMBUS_IT_ERRI)
396#define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
409#define SMBUS_FLAG_TXE I2C_ISR_TXE
410#define SMBUS_FLAG_TXIS I2C_ISR_TXIS
411#define SMBUS_FLAG_RXNE I2C_ISR_RXNE
412#define SMBUS_FLAG_ADDR I2C_ISR_ADDR
413#define SMBUS_FLAG_AF I2C_ISR_NACKF
414#define SMBUS_FLAG_STOPF I2C_ISR_STOPF
415#define SMBUS_FLAG_TC I2C_ISR_TC
416#define SMBUS_FLAG_TCR I2C_ISR_TCR
417#define SMBUS_FLAG_BERR I2C_ISR_BERR
418#define SMBUS_FLAG_ARLO I2C_ISR_ARLO
419#define SMBUS_FLAG_OVR I2C_ISR_OVR
420#define SMBUS_FLAG_PECERR I2C_ISR_PECERR
421#define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT
422#define SMBUS_FLAG_ALERT I2C_ISR_ALERT
423#define SMBUS_FLAG_BUSY I2C_ISR_BUSY
424#define SMBUS_FLAG_DIR I2C_ISR_DIR
433/* Exported macros ------------------------------------------------------------*/
443#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
444#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \
445 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \
446 (__HANDLE__)->MspInitCallback = NULL; \
447 (__HANDLE__)->MspDeInitCallback = NULL; \
448 } while(0)
449#else
450#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
451#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
452
467#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
468
483#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
484
499#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
500 ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
501
525#define SMBUS_FLAG_MASK (0x0001FFFFU)
526#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \
527 (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
528 ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
529
547#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == SMBUS_FLAG_TXE) ? \
548 ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \
549 ((__HANDLE__)->Instance->ICR = (__FLAG__)))
550
555#define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
556
561#define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
562
567#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
568
574/* Private constants ---------------------------------------------------------*/
575
576/* Private macros ------------------------------------------------------------*/
582#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
583 ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
584
585#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
586
587#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
588 ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
589
590#define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
591 ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
592
593#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \
594 ((MASK) == SMBUS_OA2_MASK01) || \
595 ((MASK) == SMBUS_OA2_MASK02) || \
596 ((MASK) == SMBUS_OA2_MASK03) || \
597 ((MASK) == SMBUS_OA2_MASK04) || \
598 ((MASK) == SMBUS_OA2_MASK05) || \
599 ((MASK) == SMBUS_OA2_MASK06) || \
600 ((MASK) == SMBUS_OA2_MASK07))
601
602#define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
603 ((CALL) == SMBUS_GENERALCALL_ENABLE))
604
605#define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
606 ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
607
608#define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \
609 ((PEC) == SMBUS_PEC_ENABLE))
610
611#define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \
612 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \
613 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
614
615#define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \
616 ((MODE) == SMBUS_AUTOEND_MODE) || \
617 ((MODE) == SMBUS_SOFTEND_MODE) || \
618 ((MODE) == SMBUS_SENDPEC_MODE) || \
619 ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \
620 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \
621 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \
622 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \
623 SMBUS_RELOAD_MODE )))
624
625
626#define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \
627 ((REQUEST) == SMBUS_GENERATE_START_READ) || \
628 ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \
629 ((REQUEST) == SMBUS_NO_STARTSTOP))
630
631
632#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \
633 ((REQUEST) == SMBUS_FIRST_FRAME) || \
634 ((REQUEST) == SMBUS_NEXT_FRAME) || \
635 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \
636 ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \
637 ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \
638 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \
639 ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))
640
641#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \
642 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \
643 ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \
644 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
645
646#define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \
647 (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \
648 I2C_CR1_PECEN)))
649#define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \
650 (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \
651 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \
652 I2C_CR2_RD_WRN)))
653
654#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \
655 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
656 (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
657 (~I2C_CR2_RD_WRN)) : \
658 (uint32_t)((((uint32_t)(__ADDRESS__) & \
659 (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \
660 (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
661
662#define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
663#define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
664#define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
665#define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
666#define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
667
668#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \
669 ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)
670#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)
671
672#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
673#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
674
679/* Include SMBUS HAL Extended module */
680#include "stm32h7xx_hal_smbus_ex.h"
681
682/* Exported functions --------------------------------------------------------*/
691/* Initialization and de-initialization functions ****************************/
692HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
693HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
694void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
695void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
696HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
697HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
698
699/* Callbacks Register/UnRegister functions ***********************************/
700#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)
701HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus,
702 HAL_SMBUS_CallbackIDTypeDef CallbackID,
703 pSMBUS_CallbackTypeDef pCallback);
704HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus,
705 HAL_SMBUS_CallbackIDTypeDef CallbackID);
706
707HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus,
708 pSMBUS_AddrCallbackTypeDef pCallback);
709HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);
710#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */
719/* IO operation functions *****************************************************/
723/******* Blocking mode: Polling */
724HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials,
725 uint32_t Timeout);
733/******* Non-Blocking mode: Interrupt */
734HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
735 uint8_t *pData, uint16_t Size, uint32_t XferOptions);
736HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress,
737 uint8_t *pData, uint16_t Size, uint32_t XferOptions);
738HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
739HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
740 uint32_t XferOptions);
741HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size,
742 uint32_t XferOptions);
743
744HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
745HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
746HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
747HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
755/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
756void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
757void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
758void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
759void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
760void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
761void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
762void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
763void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
764void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
765
774/* Peripheral State and Errors functions **************************************************/
775uint32_t HAL_SMBUS_GetState(const SMBUS_HandleTypeDef *hsmbus);
776uint32_t HAL_SMBUS_GetError(const SMBUS_HandleTypeDef *hsmbus);
777
786/* Private Functions ---------------------------------------------------------*/
791/* Private functions are defined in stm32h7xx_hal_smbus.c file */
808#ifdef __cplusplus
809}
810#endif
811
812
813#endif /* STM32H7xx_HAL_SMBUS_H */
__IO
#define __IO
Definition: core_cm4.h:239
stm32h7xx_hal_def.h
This file contains HAL common defines, enumeration, macros and structures definitions.
HAL_StatusTypeDef
HAL_StatusTypeDef
HAL Status structures definition.
Definition: stm32h7xx_hal_def.h:47
HAL_LockTypeDef
HAL_LockTypeDef
HAL Lock structures definition.
Definition: stm32h7xx_hal_def.h:58
stm32h7xx_hal_smbus_ex.h
Header file of SMBUS HAL Extended module.
I2C_TypeDef
Inter-integrated Circuit Interface.
Definition: stm32h723xx.h:1133
SMBUS_HandleTypeDef
Definition: stm32h7xx_hal_smbus.h:145
SMBUS_HandleTypeDef::PreviousState
__IO uint32_t PreviousState
Definition: stm32h7xx_hal_smbus.h:158
SMBUS_HandleTypeDef::ErrorCode
__IO uint32_t ErrorCode
Definition: stm32h7xx_hal_smbus.h:164
SMBUS_HandleTypeDef::Init
SMBUS_InitTypeDef Init
Definition: stm32h7xx_hal_smbus.h:148
SMBUS_HandleTypeDef::XferSize
uint16_t XferSize
Definition: stm32h7xx_hal_smbus.h:152
SMBUS_HandleTypeDef::XferOptions
__IO uint32_t XferOptions
Definition: stm32h7xx_hal_smbus.h:156
SMBUS_HandleTypeDef::State
__IO uint32_t State
Definition: stm32h7xx_hal_smbus.h:162
SMBUS_HandleTypeDef::pBuffPtr
uint8_t * pBuffPtr
Definition: stm32h7xx_hal_smbus.h:150
SMBUS_HandleTypeDef::Lock
HAL_LockTypeDef Lock
Definition: stm32h7xx_hal_smbus.h:160
SMBUS_HandleTypeDef::XferCount
__IO uint16_t XferCount
Definition: stm32h7xx_hal_smbus.h:154
SMBUS_HandleTypeDef::Instance
I2C_TypeDef * Instance
Definition: stm32h7xx_hal_smbus.h:146
SMBUS_InitTypeDef
Definition: stm32h7xx_hal_smbus.h:50
SMBUS_InitTypeDef::OwnAddress2Masks
uint32_t OwnAddress2Masks
Definition: stm32h7xx_hal_smbus.h:69
SMBUS_InitTypeDef::Timing
uint32_t Timing
Definition: stm32h7xx_hal_smbus.h:51
SMBUS_InitTypeDef::PacketErrorCheckMode
uint32_t PacketErrorCheckMode
Definition: stm32h7xx_hal_smbus.h:79
SMBUS_InitTypeDef::AddressingMode
uint32_t AddressingMode
Definition: stm32h7xx_hal_smbus.h:60
SMBUS_InitTypeDef::SMBusTimeout
uint32_t SMBusTimeout
Definition: stm32h7xx_hal_smbus.h:85
SMBUS_InitTypeDef::AnalogFilter
uint32_t AnalogFilter
Definition: stm32h7xx_hal_smbus.h:54
SMBUS_InitTypeDef::OwnAddress2
uint32_t OwnAddress2
Definition: stm32h7xx_hal_smbus.h:66
SMBUS_InitTypeDef::GeneralCallMode
uint32_t GeneralCallMode
Definition: stm32h7xx_hal_smbus.h:73
SMBUS_InitTypeDef::DualAddressMode
uint32_t DualAddressMode
Definition: stm32h7xx_hal_smbus.h:63
SMBUS_InitTypeDef::PeripheralMode
uint32_t PeripheralMode
Definition: stm32h7xx_hal_smbus.h:82
SMBUS_InitTypeDef::NoStretchMode
uint32_t NoStretchMode
Definition: stm32h7xx_hal_smbus.h:76
SMBUS_InitTypeDef::OwnAddress1
uint32_t OwnAddress1
Definition: stm32h7xx_hal_smbus.h:57
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