CONTROL - Control register
#define	USBHSDCD_CONTROL_IACK_MASK (0x1U)

#define	USBHSDCD_CONTROL_IACK_SHIFT (0U)

#define	USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)

#define	USBHSDCD_CONTROL_IF_MASK (0x100U)

#define	USBHSDCD_CONTROL_IF_SHIFT (8U)

#define	USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)

#define	USBHSDCD_CONTROL_IE_MASK (0x10000U)

#define	USBHSDCD_CONTROL_IE_SHIFT (16U)

#define	USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)

#define	USBHSDCD_CONTROL_BC12_MASK (0x20000U)

#define	USBHSDCD_CONTROL_BC12_SHIFT (17U)

#define	USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)

#define	USBHSDCD_CONTROL_START_MASK (0x1000000U)

#define	USBHSDCD_CONTROL_START_SHIFT (24U)

#define	USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)

#define	USBHSDCD_CONTROL_SR_MASK (0x2000000U)

#define	USBHSDCD_CONTROL_SR_SHIFT (25U)

#define	USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)

CLOCK - Clock register
#define	USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)

#define	USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)

#define	USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)

#define	USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)

#define	USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)

#define	USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)

STATUS - Status register
#define	USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U)

#define	USBHSDCD_STATUS_SEQ_RES_SHIFT (16U)

#define	USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)

#define	USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U)

#define	USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U)

#define	USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)

#define	USBHSDCD_STATUS_ERR_MASK (0x100000U)

#define	USBHSDCD_STATUS_ERR_SHIFT (20U)

#define	USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)

#define	USBHSDCD_STATUS_TO_MASK (0x200000U)

#define	USBHSDCD_STATUS_TO_SHIFT (21U)

#define	USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)

#define	USBHSDCD_STATUS_ACTIVE_MASK (0x400000U)

#define	USBHSDCD_STATUS_ACTIVE_SHIFT (22U)

#define	USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)

SIGNAL_OVERRIDE - Signal Override Register
#define	USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)

#define	USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)

#define	USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)

TIMER0 - TIMER0 register
#define	USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU)

#define	USBHSDCD_TIMER0_TUNITCON_SHIFT (0U)

#define	USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)

#define	USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)

#define	USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U)

#define	USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)

TIMER1 - TIMER1 register
#define	USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)

#define	USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)

#define	USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)

#define	USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)

#define	USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U)

#define	USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)

TIMER2_BC11 - TIMER2_BC11 register
#define	USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)

#define	USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)

#define	USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)

#define	USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)

#define	USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)

#define	USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)

TIMER2_BC12 - TIMER2_BC12 register
#define	USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)

#define	USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)

#define	USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)

#define	USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)

#define	USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)

#define	USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)

CONTROL - Control register
#define	USBHSDCD_CONTROL_IACK_MASK (0x1U)

#define	USBHSDCD_CONTROL_IACK_SHIFT (0U)

#define	USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)

#define	USBHSDCD_CONTROL_IF_MASK (0x100U)

#define	USBHSDCD_CONTROL_IF_SHIFT (8U)

#define	USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)

#define	USBHSDCD_CONTROL_IE_MASK (0x10000U)

#define	USBHSDCD_CONTROL_IE_SHIFT (16U)

#define	USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)

#define	USBHSDCD_CONTROL_BC12_MASK (0x20000U)

#define	USBHSDCD_CONTROL_BC12_SHIFT (17U)

#define	USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)

#define	USBHSDCD_CONTROL_START_MASK (0x1000000U)

#define	USBHSDCD_CONTROL_START_SHIFT (24U)

#define	USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)

#define	USBHSDCD_CONTROL_SR_MASK (0x2000000U)

#define	USBHSDCD_CONTROL_SR_SHIFT (25U)

#define	USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)

CLOCK - Clock register
#define	USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)

#define	USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)

#define	USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)

#define	USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)

#define	USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)

#define	USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)

STATUS - Status register
#define	USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U)

#define	USBHSDCD_STATUS_SEQ_RES_SHIFT (16U)

#define	USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)

#define	USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U)

#define	USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U)

#define	USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)

#define	USBHSDCD_STATUS_ERR_MASK (0x100000U)

#define	USBHSDCD_STATUS_ERR_SHIFT (20U)

#define	USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)

#define	USBHSDCD_STATUS_TO_MASK (0x200000U)

#define	USBHSDCD_STATUS_TO_SHIFT (21U)

#define	USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)

#define	USBHSDCD_STATUS_ACTIVE_MASK (0x400000U)

#define	USBHSDCD_STATUS_ACTIVE_SHIFT (22U)

#define	USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)

SIGNAL_OVERRIDE - Signal Override Register
#define	USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)

#define	USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)

#define	USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)

TIMER0 - TIMER0 register
#define	USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU)

#define	USBHSDCD_TIMER0_TUNITCON_SHIFT (0U)

#define	USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)

#define	USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)

#define	USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U)

#define	USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)

TIMER1 - TIMER1 register
#define	USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)

#define	USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)

#define	USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)

#define	USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)

#define	USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U)

#define	USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)

TIMER2_BC11 - TIMER2_BC11 register
#define	USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)

#define	USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)

#define	USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)

#define	USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)

#define	USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)

#define	USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)

TIMER2_BC12 - TIMER2_BC12 register
#define	USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)

#define	USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)

#define	USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)

#define	USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)

#define	USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)

#define	USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)

Detailed Description

Macro Definition Documentation

◆ USBHSDCD_CLOCK_CLOCK_SPEED [1/2]

#define USBHSDCD_CLOCK_CLOCK_SPEED ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)

CLOCK_SPEED - Numerical Value of Clock Speed in Binary

◆ USBHSDCD_CLOCK_CLOCK_SPEED [2/2]

#define USBHSDCD_CLOCK_CLOCK_SPEED ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)

CLOCK_SPEED - Numerical Value of Clock Speed in Binary

◆ USBHSDCD_CLOCK_CLOCK_UNIT [1/2]

#define USBHSDCD_CLOCK_CLOCK_UNIT ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)

CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed 0b0..kHz Speed (between 1 kHz and 1023 kHz) 0b1..MHz Speed (between 1 MHz and 1023 MHz)

◆ USBHSDCD_CLOCK_CLOCK_UNIT [2/2]

#define USBHSDCD_CLOCK_CLOCK_UNIT ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)

CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed 0b0..kHz Speed (between 1 kHz and 1023 kHz) 0b1..MHz Speed (between 1 MHz and 1023 MHz)

◆ USBHSDCD_CONTROL_BC12 [1/2]

#define USBHSDCD_CONTROL_BC12 ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)

BC12 - BC12 0b0..Compatible with BC1.1 (default) 0b1..Compatible with BC1.2

◆ USBHSDCD_CONTROL_BC12 [2/2]

#define USBHSDCD_CONTROL_BC12 ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)

BC12 - BC12 0b0..Compatible with BC1.1 (default) 0b1..Compatible with BC1.2

◆ USBHSDCD_CONTROL_IACK [1/2]

#define USBHSDCD_CONTROL_IACK ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)

IACK - Interrupt Acknowledge 0b0..Do not clear the interrupt. 0b1..Clear the IF bit (interrupt flag).

◆ USBHSDCD_CONTROL_IACK [2/2]

#define USBHSDCD_CONTROL_IACK ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)

IACK - Interrupt Acknowledge 0b0..Do not clear the interrupt. 0b1..Clear the IF bit (interrupt flag).

◆ USBHSDCD_CONTROL_IE [1/2]

#define USBHSDCD_CONTROL_IE ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)

IE - Interrupt Enable 0b0..Disable interrupts to the system. 0b1..Enable interrupts to the system.

◆ USBHSDCD_CONTROL_IE [2/2]

#define USBHSDCD_CONTROL_IE ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)

IE - Interrupt Enable 0b0..Disable interrupts to the system. 0b1..Enable interrupts to the system.

◆ USBHSDCD_CONTROL_IF [1/2]

#define USBHSDCD_CONTROL_IF ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)

IF - Interrupt Flag 0b0..No interrupt is pending. 0b1..An interrupt is pending.

◆ USBHSDCD_CONTROL_IF [2/2]

#define USBHSDCD_CONTROL_IF ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)

IF - Interrupt Flag 0b0..No interrupt is pending. 0b1..An interrupt is pending.

◆ USBHSDCD_CONTROL_SR [1/2]

#define USBHSDCD_CONTROL_SR ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)

SR - Software Reset 0b0..Do not perform a software reset. 0b1..Perform a software reset.

◆ USBHSDCD_CONTROL_SR [2/2]

#define USBHSDCD_CONTROL_SR ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)

SR - Software Reset 0b0..Do not perform a software reset. 0b1..Perform a software reset.

◆ USBHSDCD_CONTROL_START [1/2]

#define USBHSDCD_CONTROL_START ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)

START - Start Change Detection Sequence 0b0..Do not start the sequence. Writes of this value have no effect. 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.

◆ USBHSDCD_CONTROL_START [2/2]

#define USBHSDCD_CONTROL_START ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)

START - Start Change Detection Sequence 0b0..Do not start the sequence. Writes of this value have no effect. 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.

◆ USBHSDCD_SIGNAL_OVERRIDE_PS [1/2]

#define USBHSDCD_SIGNAL_OVERRIDE_PS ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)

PS - Phase Selection 0b00..No overrides. Bit field must remain at this value during normal USB data communication to prevent unexpected conditions on USB_DP and USB_DM pins. (Default) 0b01..Reserved, not for customer use. 0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin. 0b11..Reserved, not for customer use.

◆ USBHSDCD_SIGNAL_OVERRIDE_PS [2/2]

#define USBHSDCD_SIGNAL_OVERRIDE_PS ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)

PS - Phase Selection 0b00..No overrides. Bit field must remain at this value during normal USB data communication to prevent unexpected conditions on USB_DP and USB_DM pins. (Default) 0b01..Reserved, not for customer use. 0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin. 0b11..Reserved, not for customer use.

◆ USBHSDCD_STATUS_ACTIVE [1/2]

#define USBHSDCD_STATUS_ACTIVE ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)

ACTIVE - Active Status Indicator 0b0..The sequence is not running. 0b1..The sequence is running.

◆ USBHSDCD_STATUS_ACTIVE [2/2]

#define USBHSDCD_STATUS_ACTIVE ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)

ACTIVE - Active Status Indicator 0b0..The sequence is not running. 0b1..The sequence is running.

◆ USBHSDCD_STATUS_ERR [1/2]

#define USBHSDCD_STATUS_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)

ERR - Error Flag 0b0..No sequence errors. 0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.

◆ USBHSDCD_STATUS_ERR [2/2]

#define USBHSDCD_STATUS_ERR ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)

ERR - Error Flag 0b0..No sequence errors. 0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.

◆ USBHSDCD_STATUS_SEQ_RES [1/2]

#define USBHSDCD_STATUS_SEQ_RES ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)

SEQ_RES - Charger Detection Sequence Results 0b00..No results to report. 0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected. 0b10..Attached to a charging port. The exact meaning depends on bit 18 (value 0: Attached to either a CDP or a DCP. The charger type detection has not completed. value 1: Attached to a CDP. The charger type detection has completed.) 0b11..Attached to a DCP.

◆ USBHSDCD_STATUS_SEQ_RES [2/2]

#define USBHSDCD_STATUS_SEQ_RES ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)

SEQ_RES - Charger Detection Sequence Results 0b00..No results to report. 0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected. 0b10..Attached to a charging port. The exact meaning depends on bit 18 (value 0: Attached to either a CDP or a DCP. The charger type detection has not completed. value 1: Attached to a CDP. The charger type detection has completed.) 0b11..Attached to a DCP.

◆ USBHSDCD_STATUS_SEQ_STAT [1/2]

#define USBHSDCD_STATUS_SEQ_STAT ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)

SEQ_STAT - Charger Detection Sequence Status 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected. 0b01..Data pin contact detection is complete. 0b10..Charging port detection is complete. 0b11..Charger type detection is complete.

◆ USBHSDCD_STATUS_SEQ_STAT [2/2]

#define USBHSDCD_STATUS_SEQ_STAT ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)

SEQ_STAT - Charger Detection Sequence Status 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected. 0b01..Data pin contact detection is complete. 0b10..Charging port detection is complete. 0b11..Charger type detection is complete.

◆ USBHSDCD_STATUS_TO [1/2]

#define USBHSDCD_STATUS_TO ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)

TO - Timeout Flag 0b0..The detection sequence has not been running for over 1s. 0b1..It has been over 1 s since the data pin contact was detected and debounced.

◆ USBHSDCD_STATUS_TO [2/2]

#define USBHSDCD_STATUS_TO ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)

TO - Timeout Flag 0b0..The detection sequence has not been running for over 1s. 0b1..It has been over 1 s since the data pin contact was detected and debounced.

◆ USBHSDCD_TIMER0_TSEQ_INIT [1/2]

#define USBHSDCD_TIMER0_TSEQ_INIT ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)

TSEQ_INIT - Sequence Initiation Time 0b0000000000-0b1111111111..0ms - 1023ms

◆ USBHSDCD_TIMER0_TSEQ_INIT [2/2]

#define USBHSDCD_TIMER0_TSEQ_INIT ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)

TSEQ_INIT - Sequence Initiation Time 0b0000000000-0b1111111111..0ms - 1023ms

◆ USBHSDCD_TIMER0_TUNITCON [1/2]

#define USBHSDCD_TIMER0_TUNITCON ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)

TUNITCON - Unit Connection Timer Elapse (in ms)

◆ USBHSDCD_TIMER0_TUNITCON [2/2]

#define USBHSDCD_TIMER0_TUNITCON ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)

TUNITCON - Unit Connection Timer Elapse (in ms)

◆ USBHSDCD_TIMER1_TDCD_DBNC [1/2]

#define USBHSDCD_TIMER1_TDCD_DBNC ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)

TDCD_DBNC - Time Period to Debounce D+ Signal 0b0000000001-0b1111111111..1ms - 1023ms

◆ USBHSDCD_TIMER1_TDCD_DBNC [2/2]

#define USBHSDCD_TIMER1_TDCD_DBNC ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)

TDCD_DBNC - Time Period to Debounce D+ Signal 0b0000000001-0b1111111111..1ms - 1023ms

◆ USBHSDCD_TIMER1_TVDPSRC_ON [1/2]

#define USBHSDCD_TIMER1_TVDPSRC_ON ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)

TVDPSRC_ON - Time Period Comparator Enabled 0b0000000001-0b1111111111..1ms - 1023ms

◆ USBHSDCD_TIMER1_TVDPSRC_ON [2/2]

#define USBHSDCD_TIMER1_TVDPSRC_ON ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)

TVDPSRC_ON - Time Period Comparator Enabled 0b0000000001-0b1111111111..1ms - 1023ms

◆ USBHSDCD_TIMER2_BC11_CHECK_DM [1/2]

#define USBHSDCD_TIMER2_BC11_CHECK_DM ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)

CHECK_DM - Time Before Check of D- Line 0b0001-0b1111..1ms - 15ms

◆ USBHSDCD_TIMER2_BC11_CHECK_DM [2/2]

#define USBHSDCD_TIMER2_BC11_CHECK_DM ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)

CHECK_DM - Time Before Check of D- Line 0b0001-0b1111..1ms - 15ms

◆ USBHSDCD_TIMER2_BC11_TVDPSRC_CON [1/2]

#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)

TVDPSRC_CON - Time Period Before Enabling D+ Pullup 0b0000000001-0b1111111111..1ms - 1023ms

◆ USBHSDCD_TIMER2_BC11_TVDPSRC_CON [2/2]

#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)

TVDPSRC_CON - Time Period Before Enabling D+ Pullup 0b0000000001-0b1111111111..1ms - 1023ms

◆ USBHSDCD_TIMER2_BC12_TVDMSRC_ON [1/2]

#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)

TVDMSRC_ON - TVDMSRC_ON 0b0000000000-0b0000101000..0ms - 40ms

◆ USBHSDCD_TIMER2_BC12_TVDMSRC_ON [2/2]

#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)

TVDMSRC_ON - TVDMSRC_ON 0b0000000000-0b0000101000..0ms - 40ms

◆ USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD [1/2]

#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)

TWAIT_AFTER_PRD - TWAIT_AFTER_PRD 0b0000000001-0b1111111111..1ms - 1023ms

◆ USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD [2/2]

#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD ( x ) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)

TWAIT_AFTER_PRD - TWAIT_AFTER_PRD 0b0000000001-0b1111111111..1ms - 1023ms

CONTROL - Control register

CLOCK - Clock register

STATUS - Status register

SIGNAL_OVERRIDE - Signal Override Register

TIMER0 - TIMER0 register

TIMER1 - TIMER1 register

TIMER2_BC11 - TIMER2_BC11 register

TIMER2_BC12 - TIMER2_BC12 register

CONTROL - Control register

CLOCK - Clock register

STATUS - Status register

SIGNAL_OVERRIDE - Signal Override Register

TIMER0 - TIMER0 register

TIMER1 - TIMER1 register

TIMER2_BC11 - TIMER2_BC11 register

TIMER2_BC12 - TIMER2_BC12 register

Detailed Description

Macro Definition Documentation

◆ USBHSDCD_CLOCK_CLOCK_SPEED [1/2]

◆ USBHSDCD_CLOCK_CLOCK_SPEED [2/2]

◆ USBHSDCD_CLOCK_CLOCK_UNIT [1/2]

◆ USBHSDCD_CLOCK_CLOCK_UNIT [2/2]

◆ USBHSDCD_CONTROL_BC12 [1/2]

◆ USBHSDCD_CONTROL_BC12 [2/2]

◆ USBHSDCD_CONTROL_IACK [1/2]

◆ USBHSDCD_CONTROL_IACK [2/2]

◆ USBHSDCD_CONTROL_IE [1/2]

◆ USBHSDCD_CONTROL_IE [2/2]

◆ USBHSDCD_CONTROL_IF [1/2]

◆ USBHSDCD_CONTROL_IF [2/2]

◆ USBHSDCD_CONTROL_SR [1/2]

◆ USBHSDCD_CONTROL_SR [2/2]

◆ USBHSDCD_CONTROL_START [1/2]

◆ USBHSDCD_CONTROL_START [2/2]

◆ USBHSDCD_SIGNAL_OVERRIDE_PS [1/2]

◆ USBHSDCD_SIGNAL_OVERRIDE_PS [2/2]

◆ USBHSDCD_STATUS_ACTIVE [1/2]

◆ USBHSDCD_STATUS_ACTIVE [2/2]

◆ USBHSDCD_STATUS_ERR [1/2]

◆ USBHSDCD_STATUS_ERR [2/2]

◆ USBHSDCD_STATUS_SEQ_RES [1/2]

◆ USBHSDCD_STATUS_SEQ_RES [2/2]

◆ USBHSDCD_STATUS_SEQ_STAT [1/2]

◆ USBHSDCD_STATUS_SEQ_STAT [2/2]

◆ USBHSDCD_STATUS_TO [1/2]

◆ USBHSDCD_STATUS_TO [2/2]

◆ USBHSDCD_TIMER0_TSEQ_INIT [1/2]

◆ USBHSDCD_TIMER0_TSEQ_INIT [2/2]

◆ USBHSDCD_TIMER0_TUNITCON [1/2]

◆ USBHSDCD_TIMER0_TUNITCON [2/2]

◆ USBHSDCD_TIMER1_TDCD_DBNC [1/2]

◆ USBHSDCD_TIMER1_TDCD_DBNC [2/2]

◆ USBHSDCD_TIMER1_TVDPSRC_ON [1/2]

◆ USBHSDCD_TIMER1_TVDPSRC_ON [2/2]

◆ USBHSDCD_TIMER2_BC11_CHECK_DM [1/2]

◆ USBHSDCD_TIMER2_BC11_CHECK_DM [2/2]

◆ USBHSDCD_TIMER2_BC11_TVDPSRC_CON [1/2]

◆ USBHSDCD_TIMER2_BC11_TVDPSRC_CON [2/2]

◆ USBHSDCD_TIMER2_BC12_TVDMSRC_ON [1/2]

◆ USBHSDCD_TIMER2_BC12_TVDMSRC_ON [2/2]

◆ USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD [1/2]

◆ USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD [2/2]