This group contains register bit definitions.
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#define | GRPCI2_DMACTRL_SAFE 0x80000000U |
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#define | GRPCI2_DMACTRL_CHIRQ_SHIFT 12 |
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#define | GRPCI2_DMACTRL_CHIRQ_MASK 0xff000U |
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#define | GRPCI2_DMACTRL_CHIRQ_GET(_reg) |
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#define | GRPCI2_DMACTRL_CHIRQ_SET(_reg, _val) |
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#define | GRPCI2_DMACTRL_CHIRQ(_val) |
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#define | GRPCI2_DMACTRL_MA 0x800U |
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#define | GRPCI2_DMACTRL_TA 0x400U |
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#define | GRPCI2_DMACTRL_PE 0x200U |
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#define | GRPCI2_DMACTRL_AE 0x100U |
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#define | GRPCI2_DMACTRL_DE 0x80U |
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#define | GRPCI2_DMACTRL_NUMCH_SHIFT 4 |
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#define | GRPCI2_DMACTRL_NUMCH_MASK 0x70U |
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#define | GRPCI2_DMACTRL_NUMCH_GET(_reg) |
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#define | GRPCI2_DMACTRL_NUMCH_SET(_reg, _val) |
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#define | GRPCI2_DMACTRL_NUMCH(_val) |
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#define | GRPCI2_DMACTRL_ACTIVE 0x8U |
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#define | GRPCI2_DMACTRL_DIS 0x4U |
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#define | GRPCI2_DMACTRL_IE 0x2U |
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#define | GRPCI2_DMACTRL_EN 0x1U |
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This group contains register bit definitions.
◆ GRPCI2_DMACTRL_CHIRQ
#define GRPCI2_DMACTRL_CHIRQ |
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_val | ) |
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Value: ( ( ( _val ) << GRPCI2_DMACTRL_CHIRQ_SHIFT ) & \
GRPCI2_DMACTRL_CHIRQ_MASK )
◆ GRPCI2_DMACTRL_CHIRQ_GET
#define GRPCI2_DMACTRL_CHIRQ_GET |
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_reg | ) |
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Value: ( ( ( _reg ) & GRPCI2_DMACTRL_CHIRQ_MASK ) >> \
GRPCI2_DMACTRL_CHIRQ_SHIFT )
◆ GRPCI2_DMACTRL_CHIRQ_SET
#define GRPCI2_DMACTRL_CHIRQ_SET |
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_reg, |
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_val |
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) |
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Value: ( ( ( _reg ) & ~GRPCI2_DMACTRL_CHIRQ_MASK ) | \
( ( ( _val ) << GRPCI2_DMACTRL_CHIRQ_SHIFT ) & \
GRPCI2_DMACTRL_CHIRQ_MASK ) )
◆ GRPCI2_DMACTRL_NUMCH
#define GRPCI2_DMACTRL_NUMCH |
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_val | ) |
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Value: ( ( ( _val ) << GRPCI2_DMACTRL_NUMCH_SHIFT ) & \
GRPCI2_DMACTRL_NUMCH_MASK )
◆ GRPCI2_DMACTRL_NUMCH_GET
#define GRPCI2_DMACTRL_NUMCH_GET |
( |
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_reg | ) |
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Value: ( ( ( _reg ) & GRPCI2_DMACTRL_NUMCH_MASK ) >> \
GRPCI2_DMACTRL_NUMCH_SHIFT )
◆ GRPCI2_DMACTRL_NUMCH_SET
#define GRPCI2_DMACTRL_NUMCH_SET |
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_reg, |
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_val |
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) |
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Value: ( ( ( _reg ) & ~GRPCI2_DMACTRL_NUMCH_MASK ) | \
( ( ( _val ) << GRPCI2_DMACTRL_NUMCH_SHIFT ) & \
GRPCI2_DMACTRL_NUMCH_MASK ) )