This group contains register bit definitions.
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#define | SPWTDP_CONF0_JE 0x1000000U |
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#define | SPWTDP_CONF0_ST 0x200000U |
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#define | SPWTDP_CONF0_EP 0x100000U |
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#define | SPWTDP_CONF0_ET 0x80000U |
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#define | SPWTDP_CONF0_SP 0x40000U |
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#define | SPWTDP_CONF0_SE 0x20000U |
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#define | SPWTDP_CONF0_LE 0x10000U |
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#define | SPWTDP_CONF0_AE 0x8000U |
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#define | SPWTDP_CONF0_MAPPING_SHIFT 8 |
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#define | SPWTDP_CONF0_MAPPING_MASK 0x1f00U |
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#define | SPWTDP_CONF0_MAPPING_GET(_reg) |
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#define | SPWTDP_CONF0_MAPPING_SET(_reg, _val) |
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#define | SPWTDP_CONF0_MAPPING(_val) |
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#define | SPWTDP_CONF0_TD 0x80U |
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#define | SPWTDP_CONF0_MU 0x40U |
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#define | SPWTDP_CONF0_SEL_SHIFT 4 |
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#define | SPWTDP_CONF0_SEL_MASK 0x30U |
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#define | SPWTDP_CONF0_SEL_GET(_reg) |
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#define | SPWTDP_CONF0_SEL_SET(_reg, _val) |
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#define | SPWTDP_CONF0_SEL(_val) |
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#define | SPWTDP_CONF0_ME 0x8U |
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#define | SPWTDP_CONF0_RE 0x4U |
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#define | SPWTDP_CONF0_TE 0x2U |
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#define | SPWTDP_CONF0_RS 0x1U |
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This group contains register bit definitions.
◆ SPWTDP_CONF0_MAPPING
#define SPWTDP_CONF0_MAPPING |
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_val | ) |
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Value: ( ( ( _val ) << SPWTDP_CONF0_MAPPING_SHIFT ) & \
SPWTDP_CONF0_MAPPING_MASK )
◆ SPWTDP_CONF0_MAPPING_GET
#define SPWTDP_CONF0_MAPPING_GET |
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_reg | ) |
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Value: ( ( ( _reg ) & SPWTDP_CONF0_MAPPING_MASK ) >> \
SPWTDP_CONF0_MAPPING_SHIFT )
◆ SPWTDP_CONF0_MAPPING_SET
#define SPWTDP_CONF0_MAPPING_SET |
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_reg, |
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_val |
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) |
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Value: ( ( ( _reg ) & ~SPWTDP_CONF0_MAPPING_MASK ) | \
( ( ( _val ) << SPWTDP_CONF0_MAPPING_SHIFT ) & \
SPWTDP_CONF0_MAPPING_MASK ) )
◆ SPWTDP_CONF0_SEL
#define SPWTDP_CONF0_SEL |
( |
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_val | ) |
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Value: ( ( ( _val ) << SPWTDP_CONF0_SEL_SHIFT ) & \
SPWTDP_CONF0_SEL_MASK )
◆ SPWTDP_CONF0_SEL_GET
#define SPWTDP_CONF0_SEL_GET |
( |
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_reg | ) |
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Value: ( ( ( _reg ) & SPWTDP_CONF0_SEL_MASK ) >> \
SPWTDP_CONF0_SEL_SHIFT )
◆ SPWTDP_CONF0_SEL_SET
#define SPWTDP_CONF0_SEL_SET |
( |
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_reg, |
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_val |
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) |
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Value: ( ( ( _reg ) & ~SPWTDP_CONF0_SEL_MASK ) | \
( ( ( _val ) << SPWTDP_CONF0_SEL_SHIFT ) & \
SPWTDP_CONF0_SEL_MASK ) )