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#define | L2C_310_ID_RTL_MASK 0x3f |
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#define | L2C_310_ID_PART_MASK ( 0xf << 6 ) |
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#define | L2C_310_ID_PART_L210 ( 1 << 6 ) |
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#define | L2C_310_ID_PART_L310 ( 3 << 6 ) |
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#define | L2C_310_ID_IMPL_MASK ( 0xff << 24 ) |
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#define | L2C_310_TYPE_DATA_BANKING_MASK 0x80000000 |
| 1 if data banking implemented, 0 if not
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#define | L2C_310_TYPE_CTYPE_MASK 0x1E000000 |
| 11xy, where: x=1 if pl310_LOCKDOWN_BY_MASTER is defined, otherwise 0
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#define | L2C_310_TYPE_CTYPE_SHIFT 25 |
| y=1 if pl310_LOCKDOWN_BY_LINE is defined, otherwise 0.
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#define | L2C_310_TYPE_HARVARD_MASK 0x01000000 |
| 1 for Harvard architecture, 0 for unified architecture
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#define | L2C_310_TYPE_SIZE_D_WAYS_MASK 0x00700000 |
| Data cache way size = 2 Exp(value + 2) KB.
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#define | L2C_310_TYPE_SIZE_D_WAYS_SHIFT 20 |
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#define | L2C_310_TYPE_NUM_D_WAYS_MASK 0x00040000 |
| Assoziativity aka number of data ways = (value * 8) + 8.
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#define | L2C_310_TYPE_NUM_D_WAYS_SHIFT 18 |
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#define | L2C_310_TYPE_LENGTH_D_LINE_MASK 0x00003000 |
| Data cache line length 00 - 32.
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#define | L2C_310_TYPE_LENGTH_D_LINE_SHIFT 12 |
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#define | L2C_310_TYPE_LENGTH_D_LINE_VAL_32 0x0 |
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#define | L2C_310_TYPE_SIZE_I_WAYS_MASK 0x00000700 |
| Instruction cache way size = 2 Exp(value + 2) KB.
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#define | L2C_310_TYPE_SIZE_I_WAYS_SHIFT 8 |
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#define | L2C_310_TYPE_NUM_I_WAYS_MASK 0x00000040 |
| Assoziativity aka number of instruction ways = (value * 8) + 8.
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#define | L2C_310_TYPE_NUM_I_WAYS_SHIFT 6 |
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#define | L2C_310_TYPE_LENGTH_I_LINE_MASK 0x00000003 |
| Instruction cache line length 00 - 32.
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#define | L2C_310_TYPE_LENGTH_I_LINE_SHIFT 0 |
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#define | L2C_310_TYPE_LENGTH_I_LINE_VAL_32 0x0 |
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#define | L2C_310_CTRL_ENABLE 0x00000001 |
| Enables the L2CC.
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#define | L2C_310_CTRL_EXCL_CONFIG (1 << 12) |
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#define | L2C_310_AUX_EBRESPE_MASK 0x40000000 |
| Early BRESP Enable.
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#define | L2C_310_AUX_IPFE_MASK 0x20000000 |
| Instruction Prefetch Enable.
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#define | L2C_310_AUX_DPFE_MASK 0x10000000 |
| Data Prefetch Enable.
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#define | L2C_310_AUX_NSIC_MASK 0x08000000 |
| Non-secure interrupt access control.
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#define | L2C_310_AUX_NSLE_MASK 0x04000000 |
| Non-secure lockdown enable.
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#define | L2C_310_AUX_CRP_MASK 0x02000000 |
| Cache replacement policy.
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#define | L2C_310_AUX_FWE_MASK 0x01800000 |
| Force write allocate.
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#define | L2C_310_AUX_SAOE_MASK 0x00400000 |
| Shared attribute override enable.
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#define | L2C_310_AUX_PE_MASK 0x00200000 |
| Parity enable.
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#define | L2C_310_AUX_EMBE_MASK 0x00100000 |
| Event monitor bus enable.
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#define | L2C_310_AUX_WAY_SIZE_MASK 0x000E0000 |
| Way-size.
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#define | L2C_310_AUX_WAY_SIZE_SHIFT 17 |
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#define | L2C_310_AUX_ASSOC_MASK 0x00010000 |
| Way-size.
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#define | L2C_310_AUX_SAIE_MASK 0x00002000 |
| Shared attribute invalidate enable.
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#define | L2C_310_AUX_EXCL_CACHE_MASK 0x00001000 |
| Exclusive cache configuration.
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#define | L2C_310_AUX_SBDLE_MASK 0x00000800 |
| Store buffer device limitation Enable.
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#define | L2C_310_AUX_HPSODRE_MASK 0x00000400 |
| High Priority for SO and Dev Reads Enable.
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#define | L2C_310_AUX_FLZE_MASK 0x00000001 |
| Full line of zero enable.
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#define | L2C_310_AUX_REG_DEFAULT_MASK |
| Enable all prefetching,. More...
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#define | L2C_310_AUX_REG_ZERO_MASK 0xFFF1FFFF |
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#define | L2C_310_RAM_1_CYCLE_LAT_VAL 0x00000000 |
| 1 cycle of latency, there is no additional latency fot tag RAM
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#define | L2C_310_RAM_2_CYCLE_LAT_VAL 0x00000001 |
| 2 cycles of latency for tag RAM
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#define | L2C_310_RAM_3_CYCLE_LAT_VAL 0x00000002 |
| 3 cycles of latency for tag RAM
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#define | L2C_310_RAM_4_CYCLE_LAT_VAL 0x00000003 |
| 4 cycles of latency for tag RAM
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#define | L2C_310_RAM_5_CYCLE_LAT_VAL 0x00000004 |
| 5 cycles of latency for tag RAM
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#define | L2C_310_RAM_6_CYCLE_LAT_VAL 0x00000005 |
| 6 cycles of latency for tag RAM
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#define | L2C_310_RAM_7_CYCLE_LAT_VAL 0x00000006 |
| 7 cycles of latency for tag RAM
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#define | L2C_310_RAM_8_CYCLE_LAT_VAL 0x00000007 |
| 8 cycles of latency for tag RAM
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#define | L2C_310_RAM_SETUP_SHIFT 0x00000000 |
| Shift left setup latency values by this value.
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#define | L2C_310_RAM_READ_SHIFT 0x00000004 |
| Shift left read latency values by this value.
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#define | L2C_310_RAM_WRITE_SHIFT 0x00000008 |
| Shift left write latency values by this value.
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#define | L2C_310_RAM_SETUP_LAT_MASK 0x00000007 |
| Mask for RAM setup latency.
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#define | L2C_310_RAM_READ_LAT_MASK 0x00000070 |
| Mask for RAM read latency.
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#define | L2C_310_RAM_WRITE_LAT_MASK 0x00000700 |
| Mask for RAM read latency.
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#define | L2C_310_TAG_RAM_DEFAULT_LAT |
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#define | L2C_310_DATA_RAM_DEFAULT_MASK |
| Latency for data RAM. More...
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#define | L2C_310_ADDR_FILTER_VALID_MASK 0xFFF00000 |
| Address filtering valid bits.
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#define | L2C_310_ADDR_FILTER_ENABLE_MASK 0x00000001 |
| Address filtering enable bit.
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#define | L2C_310_DEBUG_SPIDEN_MASK 0x00000004 |
| Debug SPIDEN bit.
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#define | L2C_310_DEBUG_DWB_MASK 0x00000002 |
| Debug DWB bit, forces write through.
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#define | L2C_310_DEBUG_DCL_MASK 0x00000002 |
| Debug DCL bit, disables cache line fill.
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#define | L2C_310_PREFETCH_OFFSET_MASK 0x0000001F |
| Prefetch offset.
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#define | L2C_310_ERRATA_IS_APPLICABLE_588369 |
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#define | CACHE_ARM_ERRATA_775420_HANDLER() |
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uint32_t | L2CC::cache_id |
| Cache ID.
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uint32_t | L2CC::cache_type |
| Cache type.
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uint8_t | L2CC::reserved_8 [0x100 - 8] |
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uint32_t | L2CC::ctrl |
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uint32_t | L2CC::aux_ctrl |
| Auxiliary control.
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uint32_t | L2CC::tag_ram_ctrl |
| Latency for tag RAM.
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uint32_t | L2CC::data_ram_ctrl |
| Latency for data RAM.
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uint8_t | L2CC::reserved_110 [0x200 - 0x110] |
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uint32_t | L2CC::ev_ctrl |
| Event counter control.
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uint32_t | L2CC::ev_cnt1_cfg |
| Event counter 1 configuration.
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uint32_t | L2CC::ev_cnt0_cfg |
| Event counter 0 configuration.
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uint32_t | L2CC::ev_cnt1 |
| Event counter 1 value.
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uint32_t | L2CC::ev_cnt0 |
| Event counter 0 value.
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uint32_t | L2CC::int_mask |
| Interrupt enable mask.
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uint32_t | L2CC::int_mask_status |
| Masked interrupt status (read-only)
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uint32_t | L2CC::int_raw_status |
| Unmasked interrupt status.
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uint32_t | L2CC::int_clr |
| Interrupt clear.
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uint8_t | L2CC::reserved_224 [0x730 - 0x224] |
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uint32_t | L2CC::cache_sync |
| Drain the STB.
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uint8_t | L2CC::reserved_734 [0x740 - 0x734] |
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uint32_t | L2CC::dummy_cache_sync_reg |
| ARM Errata 753970 for pl310-r3p0.
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uint8_t | L2CC::reserved_744 [0x770 - 0x744] |
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uint32_t | L2CC::inv_pa |
| Invalidate line by PA.
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uint8_t | L2CC::reserved_774 [0x77c - 0x774] |
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uint32_t | L2CC::inv_way |
| Invalidate by Way.
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uint8_t | L2CC::reserved_780 [0x7b0 - 0x780] |
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uint32_t | L2CC::clean_pa |
| Clean Line by PA.
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uint8_t | L2CC::reserved_7b4 [0x7b8 - 0x7b4] |
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uint32_t | L2CC::clean_index |
| Clean Line by Set/Way.
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uint32_t | L2CC::clean_way |
| Clean by Way.
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uint8_t | L2CC::reserved_7c0 [0x7f0 - 0x7c0] |
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uint32_t | L2CC::clean_inv_pa |
| Clean and Invalidate Line by PA.
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uint8_t | L2CC::reserved_7f4 [0x7f8 - 0x7f4] |
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uint32_t | L2CC::clean_inv_indx |
| Clean and Invalidate Line by Set/Way.
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uint32_t | L2CC::clean_inv_way |
| Clean and Invalidate by Way.
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uint32_t | L2CC::d_lockdown_0 |
| Data lock down 0.
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uint32_t | L2CC::i_lockdown_0 |
| Instruction lock down 0.
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uint32_t | L2CC::d_lockdown_1 |
| Data lock down 1.
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uint32_t | L2CC::i_lockdown_1 |
| Instruction lock down 1.
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uint32_t | L2CC::d_lockdown_2 |
| Data lock down 2.
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uint32_t | L2CC::i_lockdown_2 |
| Instruction lock down 2.
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uint32_t | L2CC::d_lockdown_3 |
| Data lock down 3.
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uint32_t | L2CC::i_lockdown_3 |
| Instruction lock down 3.
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uint32_t | L2CC::d_lockdown_4 |
| Data lock down 4.
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uint32_t | L2CC::i_lockdown_4 |
| Instruction lock down 4.
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uint32_t | L2CC::d_lockdown_5 |
| Data lock down 5.
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uint32_t | L2CC::i_lockdown_5 |
| Instruction lock down 5.
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uint32_t | L2CC::d_lockdown_6 |
| Data lock down 6.
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uint32_t | L2CC::i_lockdown_6 |
| Instruction lock down 6.
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uint32_t | L2CC::d_lockdown_7 |
| Data lock down 7.
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uint32_t | L2CC::i_lockdown_7 |
| Instruction lock down 7.
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uint8_t | L2CC::reserved_940 [0x950 - 0x940] |
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uint32_t | L2CC::lock_line_en |
| Lockdown by Line Enable.
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uint32_t | L2CC::unlock_way |
| Cache lockdown by way.
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uint8_t | L2CC::reserved_958 [0xc00 - 0x958] |
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uint32_t | L2CC::addr_filtering_start |
| Address range redirect, part 1.
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uint32_t | L2CC::addr_filtering_end |
| Address range redirect, part 2.
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uint8_t | L2CC::reserved_c08 [0xf40 - 0xc08] |
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uint32_t | L2CC::debug_ctrl |
| Debug control.
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uint8_t | L2CC::reserved_f44 [0xf60 - 0xf44] |
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uint32_t | L2CC::prefetch_ctrl |
| Purpose prefetch enables.
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uint8_t | L2CC::reserved_f64 [0xf80 - 0xf64] |
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uint32_t | L2CC::power_ctrl |
| Purpose power controls.
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rtems_interrupt_lock | l2c_310_lock |
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This group contains the L2C-310 cache support.