cache-l2c-310.c File Reference

This source file contains the implementation of the ARM L2C-310 cache controller support. More...

#include <assert.h>
#include <bsp.h>
#include <bsp/fatal.h>
#include <libcpu/arm-cp15.h>
#include <rtems/rtems/intr.h>
#include <bsp/arm-release-id.h>
#include <bsp/arm-errata.h>
#include "cache-cp15.h"
#include "../../shared/cache/cacheimpl.h"

Data Structures
struct	L2CC
	L2CC Register Offsets. More...

Macros
#define	CPU_DATA_CACHE_ALIGNMENT   ARM_CACHE_L1_CPU_DATA_ALIGNMENT
#define	CPU_INSTRUCTION_CACHE_ALIGNMENT   ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT
#define	CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
#define	CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
#define	L2C_310_DATA_LINE_MASK   ( CPU_DATA_CACHE_ALIGNMENT - 1 )
#define	L2C_310_INSTRUCTION_LINE_MASK
#define	L2C_310_NUM_WAYS   8
#define	L2C_310_WAY_MASK   ( ( 1 << L2C_310_NUM_WAYS ) - 1 )
#define	L2C_310_MIN(a, b)    ((a < b) ? (a) : (b))
#define	L2C_310_MAX_LOCKING_BYTES   (4 * 1024)
#define	L2C_310_RTL_RELEASE_R0_P0   0x0
#define	L2C_310_RTL_RELEASE_R1_P0   0x2
#define	L2C_310_RTL_RELEASE_R2_P0   0x4
#define	L2C_310_RTL_RELEASE_R3_P0   0x5
#define	L2C_310_RTL_RELEASE_R3_P1   0x6
#define	L2C_310_RTL_RELEASE_R3_P2   0x8
#define	L2C_310_RTL_RELEASE_R3_P3   0x9
#define	BSP_ARM_L2C_310_RTL_RELEASE   (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK)
#define	L2C_310_ID_RTL_MASK   0x3f
#define	L2C_310_ID_PART_MASK   ( 0xf << 6 )
#define	L2C_310_ID_PART_L210   ( 1 << 6 )
#define	L2C_310_ID_PART_L310   ( 3 << 6 )
#define	L2C_310_ID_IMPL_MASK   ( 0xff << 24 )
#define	L2C_310_TYPE_DATA_BANKING_MASK   0x80000000
	1 if data banking implemented, 0 if not
#define	L2C_310_TYPE_CTYPE_MASK   0x1E000000
	11xy, where: x=1 if pl310_LOCKDOWN_BY_MASTER is defined, otherwise 0
#define	L2C_310_TYPE_CTYPE_SHIFT   25
	y=1 if pl310_LOCKDOWN_BY_LINE is defined, otherwise 0.
#define	L2C_310_TYPE_HARVARD_MASK   0x01000000
	1 for Harvard architecture, 0 for unified architecture
#define	L2C_310_TYPE_SIZE_D_WAYS_MASK   0x00700000
	Data cache way size = 2 Exp(value + 2) KB.
#define	L2C_310_TYPE_SIZE_D_WAYS_SHIFT   20
#define	L2C_310_TYPE_NUM_D_WAYS_MASK   0x00040000
	Assoziativity aka number of data ways = (value * 8) + 8.
#define	L2C_310_TYPE_NUM_D_WAYS_SHIFT   18
#define	L2C_310_TYPE_LENGTH_D_LINE_MASK   0x00003000
	Data cache line length 00 - 32.
#define	L2C_310_TYPE_LENGTH_D_LINE_SHIFT   12
#define	L2C_310_TYPE_LENGTH_D_LINE_VAL_32   0x0
#define	L2C_310_TYPE_SIZE_I_WAYS_MASK   0x00000700
	Instruction cache way size = 2 Exp(value + 2) KB.
#define	L2C_310_TYPE_SIZE_I_WAYS_SHIFT   8
#define	L2C_310_TYPE_NUM_I_WAYS_MASK   0x00000040
	Assoziativity aka number of instruction ways = (value * 8) + 8.
#define	L2C_310_TYPE_NUM_I_WAYS_SHIFT   6
#define	L2C_310_TYPE_LENGTH_I_LINE_MASK   0x00000003
	Instruction cache line length 00 - 32.
#define	L2C_310_TYPE_LENGTH_I_LINE_SHIFT   0
#define	L2C_310_TYPE_LENGTH_I_LINE_VAL_32   0x0
#define	L2C_310_CTRL_ENABLE   0x00000001
	Enables the L2CC.
#define	L2C_310_CTRL_EXCL_CONFIG   (1 << 12)
#define	L2C_310_AUX_EBRESPE_MASK   0x40000000
	Early BRESP Enable.
#define	L2C_310_AUX_IPFE_MASK   0x20000000
	Instruction Prefetch Enable.
#define	L2C_310_AUX_DPFE_MASK   0x10000000
	Data Prefetch Enable.
#define	L2C_310_AUX_NSIC_MASK   0x08000000
	Non-secure interrupt access control.
#define	L2C_310_AUX_NSLE_MASK   0x04000000
	Non-secure lockdown enable.
#define	L2C_310_AUX_CRP_MASK   0x02000000
	Cache replacement policy.
#define	L2C_310_AUX_FWE_MASK   0x01800000
	Force write allocate.
#define	L2C_310_AUX_SAOE_MASK   0x00400000
	Shared attribute override enable.
#define	L2C_310_AUX_PE_MASK   0x00200000
	Parity enable.
#define	L2C_310_AUX_EMBE_MASK   0x00100000
	Event monitor bus enable.
#define	L2C_310_AUX_WAY_SIZE_MASK   0x000E0000
	Way-size.
#define	L2C_310_AUX_WAY_SIZE_SHIFT   17
#define	L2C_310_AUX_ASSOC_MASK   0x00010000
	Way-size.
#define	L2C_310_AUX_SAIE_MASK   0x00002000
	Shared attribute invalidate enable.
#define	L2C_310_AUX_EXCL_CACHE_MASK   0x00001000
	Exclusive cache configuration.
#define	L2C_310_AUX_SBDLE_MASK   0x00000800
	Store buffer device limitation Enable.
#define	L2C_310_AUX_HPSODRE_MASK   0x00000400
	High Priority for SO and Dev Reads Enable.
#define	L2C_310_AUX_FLZE_MASK   0x00000001
	Full line of zero enable.
#define	L2C_310_AUX_REG_DEFAULT_MASK
	Enable all prefetching,. More...
#define	L2C_310_AUX_REG_ZERO_MASK   0xFFF1FFFF
#define	L2C_310_RAM_1_CYCLE_LAT_VAL   0x00000000
	1 cycle of latency, there is no additional latency fot tag RAM
#define	L2C_310_RAM_2_CYCLE_LAT_VAL   0x00000001
	2 cycles of latency for tag RAM
#define	L2C_310_RAM_3_CYCLE_LAT_VAL   0x00000002
	3 cycles of latency for tag RAM
#define	L2C_310_RAM_4_CYCLE_LAT_VAL   0x00000003
	4 cycles of latency for tag RAM
#define	L2C_310_RAM_5_CYCLE_LAT_VAL   0x00000004
	5 cycles of latency for tag RAM
#define	L2C_310_RAM_6_CYCLE_LAT_VAL   0x00000005
	6 cycles of latency for tag RAM
#define	L2C_310_RAM_7_CYCLE_LAT_VAL   0x00000006
	7 cycles of latency for tag RAM
#define	L2C_310_RAM_8_CYCLE_LAT_VAL   0x00000007
	8 cycles of latency for tag RAM
#define	L2C_310_RAM_SETUP_SHIFT   0x00000000
	Shift left setup latency values by this value.
#define	L2C_310_RAM_READ_SHIFT   0x00000004
	Shift left read latency values by this value.
#define	L2C_310_RAM_WRITE_SHIFT   0x00000008
	Shift left write latency values by this value.
#define	L2C_310_RAM_SETUP_LAT_MASK   0x00000007
	Mask for RAM setup latency.
#define	L2C_310_RAM_READ_LAT_MASK   0x00000070
	Mask for RAM read latency.
#define	L2C_310_RAM_WRITE_LAT_MASK   0x00000700
	Mask for RAM read latency.
#define	L2C_310_TAG_RAM_DEFAULT_LAT
#define	L2C_310_DATA_RAM_DEFAULT_MASK
	Latency for data RAM. More...
#define	L2C_310_ADDR_FILTER_VALID_MASK   0xFFF00000
	Address filtering valid bits.
#define	L2C_310_ADDR_FILTER_ENABLE_MASK   0x00000001
	Address filtering enable bit.
#define	L2C_310_DEBUG_SPIDEN_MASK   0x00000004
	Debug SPIDEN bit.
#define	L2C_310_DEBUG_DWB_MASK   0x00000002
	Debug DWB bit, forces write through.
#define	L2C_310_DEBUG_DCL_MASK   0x00000002
	Debug DCL bit, disables cache line fill.
#define	L2C_310_PREFETCH_OFFSET_MASK   0x0000001F
	Prefetch offset.
#define	L2C_310_ERRATA_IS_APPLICABLE_588369
#define	CACHE_ARM_ERRATA_775420_HANDLER()
Interrupt bit masks
#define	L2C_310_INT_DECERR_MASK   0x00000100
	DECERR from L3.
#define	L2C_310_INT_SLVERR_MASK   0x00000080
	SLVERR from L3.
#define	L2C_310_INT_ERRRD_MASK   0x00000040
	Error on L2 data RAM (Read)
#define	L2C_310_INT_ERRRT_MASK   0x00000020
	Error on L2 tag RAM (Read)
#define	L2C_310_INT_ERRWD_MASK   0x00000010
	Error on L2 data RAM (Write)
#define	L2C_310_INT_ERRWT_MASK   0x00000008
	Error on L2 tag RAM (Write)
#define	L2C_310_INT_PARRD_MASK   0x00000004
	Parity Error on L2 data RAM (Read)
#define	L2C_310_INT_PARRT_MASK   0x00000002
	Parity Error on L2 tag RAM (Read)
#define	L2C_310_INT_ECNTR_MASK   0x00000001
	Event Counter1/0 Overflow Increment.

Variables
rtems_interrupt_lock	l2c_310_lock

Detailed Description

This source file contains the implementation of the ARM L2C-310 cache controller support.

Macro Definition Documentation

L2C_310_INSTRUCTION_LINE_MASK

#define L2C_310_INSTRUCTION_LINE_MASK

Value:

  ( CPU_INSTRUCTION_CACHE_ALIGNMENT \
    - 1 )