Macros
#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_COUNT (16U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_COUNT (16U)

#define	IOMUXC_LPSR_SELECT_INPUT_COUNT (24U)

#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_COUNT (16U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_COUNT (16U)

#define	IOMUXC_LPSR_SELECT_INPUT_COUNT (24U)

SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register
#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU)

#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)

#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK)

#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK (0x10U)

#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT (4U)

#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK)

SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK (0x1U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT (0U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK (0x2U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT (1U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK (0x4U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT (2U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK (0x8U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT (3U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK (0x20U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT (5U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK (0x30000000U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT (28U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK)

SELECT_INPUT - CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register..SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register
#define	IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */

#define	IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT (0U)

#define	IOMUXC_LPSR_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */

SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register
#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU)

#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)

#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK)

#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK (0x10U)

#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT (4U)

#define	IOMUXC_LPSR_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK)

SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register
#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK (0x1U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT (0U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK (0x2U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT (1U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK (0x4U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT (2U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK (0x8U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT (3U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK (0x20U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT (5U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK (0x30000000U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT (28U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK (0xC0000000U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT (30U)

#define	IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK)

SELECT_INPUT - CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register..SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register
#define	IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */

#define	IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT (0U)

#define	IOMUXC_LPSR_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */

Detailed Description

Macro Definition Documentation

◆ IOMUXC_LPSR_SELECT_INPUT_DAISY [1/2]

#define IOMUXC_LPSR_SELECT_INPUT_DAISY ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */

DAISY - Selecting Pads Involved in Daisy Chain. 0b00..Selecting Pad: GPIO_LPSR_00 for Mode: ALT6 0b01..Selecting Pad: GPIO_LPSR_06 for Mode: ALT3 0b10..Selecting Pad: GPIO_LPSR_10 for Mode: ALT8

◆ IOMUXC_LPSR_SELECT_INPUT_DAISY [2/2]

#define IOMUXC_LPSR_SELECT_INPUT_DAISY ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */

DAISY - Selecting Pads Involved in Daisy Chain. 0b00..Selecting Pad: GPIO_LPSR_00 for Mode: ALT6 0b01..Selecting Pad: GPIO_LPSR_06 for Mode: ALT3 0b10..Selecting Pad: GPIO_LPSR_10 for Mode: ALT8

◆ IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE [1/2]

#define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b1010..Select mux mode: ALT10 mux port: GPIO12_IO10 of instance: GPIO12 0b0000..Select mux mode: ALT0 mux port: JTAG_MUX_TRSTB of instance: JTAG_MUX 0b0001..Select mux mode: ALT1 mux port: LPUART11_CTS_B of instance: LPUART11 0b0010..Select mux mode: ALT2 mux port: LPI2C6_SDA of instance: LPI2C6 0b0011..Select mux mode: ALT3 mux port: MIC_BITSTREAM1 of instance: MIC 0b0100..Select mux mode: ALT4 mux port: LPSPI6_SCK of instance: LPSPI6 0b0101..Select mux mode: ALT5 mux port: GPIO_MUX6_IO10 of instance: GPIO_MUX6 0b0110..Select mux mode: ALT6 mux port: LPI2C5_SCLS of instance: LPI2C5 0b0111..Select mux mode: ALT7 mux port: SAI4_TX_SYNC of instance: SAI4 0b1000..Select mux mode: ALT8 mux port: LPUART12_TXD of instance: LPUART12

◆ IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE [2/2]

#define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK)

MUX_MODE - MUX Mode Select Field. 0b1010..Select mux mode: ALT10 mux port: GPIO12_IO10 of instance: GPIO12 0b0000..Select mux mode: ALT0 mux port: JTAG_MUX_TRSTB of instance: JTAG_MUX 0b0001..Select mux mode: ALT1 mux port: LPUART11_CTS_B of instance: LPUART11 0b0010..Select mux mode: ALT2 mux port: LPI2C6_SDA of instance: LPI2C6 0b0011..Select mux mode: ALT3 mux port: MIC_BITSTREAM1 of instance: MIC 0b0100..Select mux mode: ALT4 mux port: LPSPI6_SCK of instance: LPSPI6 0b0101..Select mux mode: ALT5 mux port: GPIO_MUX6_IO10 of instance: GPIO_MUX6 0b0110..Select mux mode: ALT6 mux port: LPI2C5_SCLS of instance: LPI2C5 0b0111..Select mux mode: ALT7 mux port: SAI4_TX_SYNC of instance: SAI4 0b1000..Select mux mode: ALT8 mux port: LPUART12_TXD of instance: LPUART12

◆ IOMUXC_LPSR_SW_MUX_CTL_PAD_SION [1/2]

#define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_LPSR_00 0b0..Input Path is determined by functionality

◆ IOMUXC_LPSR_SW_MUX_CTL_PAD_SION [2/2]

#define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK)

SION - Software Input On Field. 0b1..Force input path of pad GPIO_LPSR_00 0b0..Input Path is determined by functionality

◆ IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE [1/2]

#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE [2/2]

#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK)

DSE - Drive Strength Field 0b0..normal driver 0b1..high driver

◆ IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP [1/2]

#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP [2/2]

#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK)

DWP - Domain write protection 0b00..Both cores are allowed 0b01..CM7 is forbidden 0b10..CM4 is forbidden 0b11..Both cores are forbidden

◆ IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK [1/2]

#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK [2/2]

#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK)

DWP_LOCK - Domain write protection lock 0b00..Neither of DWP bits is locked 0b01..The lower DWP bit is locked 0b10..The higher DWP bit is locked 0b11..Both DWP bits are locked

◆ IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR [1/2]

#define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK)

ODE_LPSR - Open Drain LPSR Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR [2/2]

#define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK)

ODE_LPSR - Open Drain LPSR Field 0b0..Disabled 0b1..Enabled

◆ IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE [1/2]

#define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE ( x ) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK)

PUE - Pull / Keep Select Field 0b0..Pull Disable 0b1..Pull Enable

◆ IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE [2/2]