Macros
#define	RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI

#define	RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI

#define	HAL_RCC_CCSCallback HAL_RCC_CSSCallback

#define	HAL_RC48_EnableBuffer_Cmd(cmd)

#define	__ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE

#define	__ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE

#define	__ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE

#define	__ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE

#define	__ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET

#define	__ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET

#define	__ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE

#define	__ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE

#define	__ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET

#define	__ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET

#define	__ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE

#define	__ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE

#define	__ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE

#define	__ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE

#define	__ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET

#define	__ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET

#define	__ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE

#define	__ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE

#define	__ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET

#define	__ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET

#define	__AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE

#define	__AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE

#define	__AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE

#define	__AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE

#define	__AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET

#define	__AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET

#define	__CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE

#define	__CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE

#define	__CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE

#define	__CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE

#define	__CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET

#define	__CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET

#define	__AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE

#define	__AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE

#define	__AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET

#define	__AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET

#define	__AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET

#define	__AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET

#define	__AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET

#define	__AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET

#define	__AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET

#define	__AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET

#define	__AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET

#define	__AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET

#define	__APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET

#define	__APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET

#define	__APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET

#define	__APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET

#define	__BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE

#define	__BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE

#define	__BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET

#define	__BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET

#define	__CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE

#define	__CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE

#define	__CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE

#define	__CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE

#define	__CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET

#define	__CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET

#define	__CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE

#define	__CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE

#define	__CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET

#define	__CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET

#define	__CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE

#define	__CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE

#define	__CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET

#define	__CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET

#define	__CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE

#define	__CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE

#define	__COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE

#define	__COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE

#define	__COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET

#define	__COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET

#define	__COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE

#define	__COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE

#define	__CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET

#define	__CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET

#define	__CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE

#define	__CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE

#define	__CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE

#define	__CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE

#define	__CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET

#define	__CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET

#define	__DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE

#define	__DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE

#define	__DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET

#define	__DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET

#define	__DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE

#define	__DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE

#define	__DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE

#define	__DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE

#define	__DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET

#define	__DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET

#define	__DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE

#define	__DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE

#define	__DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET

#define	__DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET

#define	__DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE

#define	__DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE

#define	__DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE

#define	__DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE

#define	__DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET

#define	__DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET

#define	__DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE

#define	__DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE

#define	__DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE

#define	__DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE

#define	__DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET

#define	__DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET

#define	__DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE

#define	__DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE

#define	__DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE

#define	__DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE

#define	__DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET

#define	__DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET

#define	__ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE

#define	__ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE

#define	__ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET

#define	__ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET

#define	__ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE

#define	__ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE

#define	__ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE

#define	__ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE

#define	__FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE

#define	__FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE

#define	__FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE

#define	__FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE

#define	__FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE

#define	__FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE

#define	__FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET

#define	__FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET

#define	__FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE

#define	__FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE

#define	__FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET

#define	__FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET

#define	__FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE

#define	__FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE

#define	__FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE

#define	__FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE

#define	__FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE

#define	__FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE

#define	__FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET

#define	__FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET

#define	__FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE

#define	__FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE

#define	__GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE

#define	__GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE

#define	__GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE

#define	__GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE

#define	__GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET

#define	__GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET

#define	__GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE

#define	__GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE

#define	__GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE

#define	__GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE

#define	__GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET

#define	__GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET

#define	__GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE

#define	__GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE

#define	__GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE

#define	__GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE

#define	__GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET

#define	__GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET

#define	__GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE

#define	__GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE

#define	__GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE

#define	__GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE

#define	__GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET

#define	__GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET

#define	__GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE

#define	__GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE

#define	__GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE

#define	__GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE

#define	__GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET

#define	__GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET

#define	__GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE

#define	__GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE

#define	__GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE

#define	__GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE

#define	__GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET

#define	__GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET

#define	__GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE

#define	__GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE

#define	__GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE

#define	__GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE

#define	__GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET

#define	__GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET

#define	__GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE

#define	__GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE

#define	__GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE

#define	__GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE

#define	__GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET

#define	__GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET

#define	__I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE

#define	__I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE

#define	__I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE

#define	__I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE

#define	__I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET

#define	__I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET

#define	__I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE

#define	__I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE

#define	__I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE

#define	__I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE

#define	__I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET

#define	__I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET

#define	__I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE

#define	__I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE

#define	__I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE

#define	__I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE

#define	__I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET

#define	__I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET

#define	__LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE

#define	__LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE

#define	__LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE

#define	__LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE

#define	__LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET

#define	__LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET

#define	__LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE

#define	__LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE

#define	__LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE

#define	__LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE

#define	__LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET

#define	__LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET

#define	__LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE

#define	__LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE

#define	__LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE

#define	__LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE

#define	__LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET

#define	__LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET

#define	__LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE

#define	__LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE

#define	__LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE

#define	__LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE

#define	__LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET

#define	__LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET

#define	__OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE

#define	__OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE

#define	__OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE

#define	__OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE

#define	__OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET

#define	__OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET

#define	__OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE

#define	__OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE

#define	__OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE

#define	__OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE

#define	__OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET

#define	__OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET

#define	__PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE

#define	__PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE

#define	__PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE

#define	__PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE

#define	__PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET

#define	__PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET

#define	__QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE

#define	__QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE

#define	__QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE

#define	__QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE

#define	__QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET

#define	__QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET

#define	__RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE

#define	__RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE

#define	__RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE

#define	__RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE

#define	__RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET

#define	__RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET

#define	__SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE

#define	__SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE

#define	__SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE

#define	__SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE

#define	__SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET

#define	__SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET

#define	__SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE

#define	__SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE

#define	__SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE

#define	__SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE

#define	__SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET

#define	__SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET

#define	__SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE

#define	__SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE

#define	__SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE

#define	__SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE

#define	__SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE

#define	__SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE

#define	__SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET

#define	__SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET

#define	__SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE

#define	__SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE

#define	__SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE

#define	__SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE

#define	__SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET

#define	__SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET

#define	__SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE

#define	__SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE

#define	__SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE

#define	__SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE

#define	__SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET

#define	__SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET

#define	__SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE

#define	__SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE

#define	__SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE

#define	__SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE

#define	__SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET

#define	__SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET

#define	__SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE

#define	__SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE

#define	__SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE

#define	__SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE

#define	__SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE

#define	__SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE

#define	__SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE

#define	__SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE

#define	__SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE

#define	__SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE

#define	__SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET

#define	__SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET

#define	__SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE

#define	__SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE

#define	__SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE

#define	__SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE

#define	__SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET

#define	__SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET

#define	__TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE

#define	__TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE

#define	__TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE

#define	__TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE

#define	__TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET

#define	__TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET

#define	__TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE

#define	__TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE

#define	__TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET

#define	__TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET

#define	__TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE

#define	__TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE

#define	__TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET

#define	__TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET

#define	__TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE

#define	__TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE

#define	__TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET

#define	__TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET

#define	__TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE

#define	__TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE

#define	__TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET

#define	__TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET

#define	__TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE

#define	__TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE

#define	__TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET

#define	__TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET

#define	__TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE

#define	__TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE

#define	__TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE

#define	__TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE

#define	__TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET

#define	__TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET

#define	__TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE

#define	__TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE

#define	__TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE

#define	__TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE

#define	__TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET

#define	__TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET

#define	__TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE

#define	__TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE

#define	__TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE

#define	__TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE

#define	__TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET

#define	__TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET

#define	__TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE

#define	__TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE

#define	__TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE

#define	__TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE

#define	__TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET

#define	__TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET

#define	__TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE

#define	__TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE

#define	__TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE

#define	__TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE

#define	__TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET

#define	__TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET

#define	__TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE

#define	__TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE

#define	__TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE

#define	__TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE

#define	__TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET

#define	__TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET

#define	__TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE

#define	__TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE

#define	__TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE

#define	__TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE

#define	__TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET

#define	__TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET

#define	__TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE

#define	__TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE

#define	__TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE

#define	__TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE

#define	__TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET

#define	__TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET

#define	__TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE

#define	__TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE

#define	__TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE

#define	__TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE

#define	__TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET

#define	__TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET

#define	__TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE

#define	__TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE

#define	__TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE

#define	__TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE

#define	__TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET

#define	__TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET

#define	__TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE

#define	__TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE

#define	__TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET

#define	__TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET

#define	__TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE

#define	__TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE

#define	__TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE

#define	__TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE

#define	__TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET

#define	__TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET

#define	__UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE

#define	__UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE

#define	__UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE

#define	__UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE

#define	__UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET

#define	__UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET

#define	__UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE

#define	__UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE

#define	__UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE

#define	__UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE

#define	__UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET

#define	__UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET

#define	__USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE

#define	__USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE

#define	__USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE

#define	__USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE

#define	__USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET

#define	__USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET

#define	__USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE

#define	__USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE

#define	__USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE

#define	__USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE

#define	__USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET

#define	__USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET

#define	__USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE

#define	__USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE

#define	__USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE

#define	__USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE

#define	__USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET

#define	__USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET

#define	__USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE

#define	__USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE

#define	__USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE

#define	__USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE

#define	__USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET

#define	__USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET

#define	__USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE

#define	__USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE

#define	__USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE

#define	__USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE

#define	__USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET

#define	__USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET

#define	__USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE

#define	__USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE

#define	__USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET

#define	__USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET

#define	__USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE

#define	__USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE

#define	__USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET

#define	__USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET

#define	__USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE

#define	__USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE

#define	__USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET

#define	__USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE

#define	__USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE

#define	__USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE

#define	__USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE

#define	__USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET

#define	__WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE

#define	__WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE

#define	__WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE

#define	__WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE

#define	__WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET

#define	__WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET

#define	__TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE

#define	__TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE

#define	__TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET

#define	__TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET

#define	__TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE

#define	__TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE

#define	__TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE

#define	__TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE

#define	__TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET

#define	__TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET

#define	__TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE

#define	__TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE

#define	__CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE

#define	__CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE

#define	__CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE

#define	__CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE

#define	__CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET

#define	__CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET

#define	__RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE

#define	__RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE

#define	__USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET

#define	__USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET

#define	__USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE

#define	__USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE

#define	__USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE

#define	__USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE

#define	__USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE

#define	__USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE

#define	__TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE

#define	__TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE

#define	__TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE

#define	__TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE

#define	__TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE

#define	__TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE

#define	__ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE

#define	__ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE

#define	__ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE

#define	__ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE

#define	__HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE

#define	__HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET

#define	__HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET

#define	__HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE

#define	__HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE

#define	__HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE

#define	__SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE

#define	__SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE

#define	__SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET

#define	__SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET

#define	__SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE

#define	__SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE

#define	__SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE

#define	__SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE

#define	__SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET

#define	__SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET

#define	__SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE

#define	__SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE

#define	__LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE

#define	__LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE

#define	__LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET

#define	__LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET

#define	__LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE

#define	__ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE

#define	__ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE

#define	__ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE

#define	__ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE

#define	__ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE

#define	__ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE

#define	__TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE

#define	__TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE

#define	__TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE

#define	__TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE

#define	__TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE

#define	__TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE

#define	__BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE

#define	__BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE

#define	__BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE

#define	__BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE

#define	__CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE

#define	__CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE

#define	__USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE

#define	__USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE

#define	__USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET

#define	__USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET

#define	__USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE

#define	__USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE

#define	__SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE

#define	__SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE

#define	__SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET

#define	__SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET

#define	__SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE

#define	__SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE

#define	__GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE

#define	__GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE

#define	__GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET

#define	__GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET

#define	__GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE

#define	__GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE

#define	__GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE

#define	__GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE

#define	__GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET

#define	__GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET

#define	__GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE

#define	__GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE

#define	__GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE

#define	__GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE

#define	__GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET

#define	__GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE

#define	__GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE

#define	__ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE

#define	__ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE

#define	__DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE

#define	__DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE

#define	__DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET

#define	__DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET

#define	__DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE

#define	__DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE

#define	__UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE

#define	__UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE

#define	__UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET

#define	__UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET

#define	__UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE

#define	__UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE

#define	__UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE

#define	__UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE

#define	__UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET

#define	__UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET

#define	__UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE

#define	__UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE

#define	__OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE

#define	__OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE

#define	__OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET

#define	__OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET

#define	__OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE

#define	__OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE

#define	__HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE

#define	__HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE

#define	__HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED

#define	__HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED

#define	__HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET

#define	__HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET

#define	__HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE

#define	__HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE

#define	__HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED

#define	__HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED

#define	__SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE

#define	__CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE

#define	__CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE

#define	__DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE

#define	__DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE

#define	__ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE

#define	__ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE

#define	__ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE

#define	__ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE

#define	__FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET

#define	__FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET

#define	__FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE

#define	__FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE

#define	__SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET

#define	__SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET

#define	__SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE

#define	__SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE

#define	__DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE

#define	__DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE

#define	__DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET

#define	__DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET

#define	__DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE

#define	__DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE

#define	__HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET

#define	__HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET

#define	__ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE

#define	__ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE

#define	__ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE

#define	__ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE

#define	__DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE

#define	__DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE

#define	__TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE

#define	__TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE

#define	__TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE

#define	__TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE

#define	__TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE

#define	__TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE

#define	__HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE

#define	__HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE

#define	__SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE

#define	__SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE

#define	__SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE

#define	__SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE

#define	__SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE

#define	__SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE

#define	__ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET

#define	__ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET

#define	__ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET

#define	__ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET

#define	__DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET

#define	__DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET

#define	__TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET

#define	__TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET

#define	__TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET

#define	__TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET

#define	__TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET

#define	__TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET

#define	__HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET

#define	__HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET

#define	__SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET

#define	__SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET

#define	__SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET

#define	__SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET

#define	__SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET

#define	__SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET

#define	__ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED

#define	__ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED

#define	__ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED

#define	__ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED

#define	__ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED

#define	__ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED

#define	__CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED

#define	__CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED

#define	__CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED

#define	__CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED

#define	__DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED

#define	__DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED

#define	__DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED

#define	__DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED

#define	__DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED

#define	__DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED

#define	__DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED

#define	__DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED

#define	__FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED

#define	__FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED

#define	__FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED

#define	__FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED

#define	__GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED

#define	__GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED

#define	__GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED

#define	__GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED

#define	__GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED

#define	__GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED

#define	__GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED

#define	__GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED

#define	__GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED

#define	__GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED

#define	__GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED

#define	__GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED

#define	__GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED

#define	__GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED

#define	__GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED

#define	__GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED

#define	__HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED

#define	__HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED

#define	__I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED

#define	__I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED

#define	__I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED

#define	__I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED

#define	__I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED

#define	__I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED

#define	__PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED

#define	__PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED

#define	__SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED

#define	__SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED

#define	__SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED

#define	__SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED

#define	__SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED

#define	__SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED

#define	__SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED

#define	__SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED

#define	__SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED

#define	__SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED

#define	__SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED

#define	__SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED

#define	__SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED

#define	__SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED

#define	__SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED

#define	__SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED

#define	__SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED

#define	__SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED

#define	__TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED

#define	__TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED

#define	__TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED

#define	__TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED

#define	__TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED

#define	__TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED

#define	__TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED

#define	__TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED

#define	__TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED

#define	__TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED

#define	__TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED

#define	__TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED

#define	__TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED

#define	__TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED

#define	__TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED

#define	__TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED

#define	__TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED

#define	__TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED

#define	__TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED

#define	__TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED

#define	__TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED

#define	__TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED

#define	__TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED

#define	__TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED

#define	__TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED

#define	__TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED

#define	__TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED

#define	__TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED

#define	__TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED

#define	__TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED

#define	__TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED

#define	__TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED

#define	__TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED

#define	__TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED

#define	__TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED

#define	__TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED

#define	__UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED

#define	__UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED

#define	__UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED

#define	__UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED

#define	__USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED

#define	__USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED

#define	__USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED

#define	__USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED

#define	__USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED

#define	__USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED

#define	__USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED

#define	__USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED

#define	__WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED

#define	__WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED

#define	__HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG

#define	__HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG

#define	__RCC_PLLSRC RCC_GET_PLL_OSCSOURCE

#define	IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE

#define	IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE

#define	IS_RCC_SYSCLK_DIV IS_RCC_HCLK

#define	IS_RCC_HCLK_DIV IS_RCC_PCLK

#define	IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK

#define	RCC_IT_HSI14 RCC_IT_HSI14RDY

#define	RCC_IT_CSSLSE RCC_IT_LSECSS

#define	RCC_IT_CSSHSE RCC_IT_CSS

#define	RCC_PLLMUL_3 RCC_PLL_MUL3

#define	RCC_PLLMUL_4 RCC_PLL_MUL4

#define	RCC_PLLMUL_6 RCC_PLL_MUL6

#define	RCC_PLLMUL_8 RCC_PLL_MUL8

#define	RCC_PLLMUL_12 RCC_PLL_MUL12

#define	RCC_PLLMUL_16 RCC_PLL_MUL16

#define	RCC_PLLMUL_24 RCC_PLL_MUL24

#define	RCC_PLLMUL_32 RCC_PLL_MUL32

#define	RCC_PLLMUL_48 RCC_PLL_MUL48

#define	RCC_PLLDIV_2 RCC_PLL_DIV2

#define	RCC_PLLDIV_3 RCC_PLL_DIV3

#define	RCC_PLLDIV_4 RCC_PLL_DIV4

#define	IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE

#define	__HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG

#define	RCC_MCO_NODIV RCC_MCODIV_1

#define	RCC_MCO_DIV1 RCC_MCODIV_1

#define	RCC_MCO_DIV2 RCC_MCODIV_2

#define	RCC_MCO_DIV4 RCC_MCODIV_4

#define	RCC_MCO_DIV8 RCC_MCODIV_8

#define	RCC_MCO_DIV16 RCC_MCODIV_16

#define	RCC_MCO_DIV32 RCC_MCODIV_32

#define	RCC_MCO_DIV64 RCC_MCODIV_64

#define	RCC_MCO_DIV128 RCC_MCODIV_128

#define	RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK

#define	RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI

#define	RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE

#define	RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK

#define	RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI

#define	RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14

#define	RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48

#define	RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE

#define	RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK

#define	RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK

#define	RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2

#define	RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK

#define	RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1

#define	RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL

#define	RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI

#define	RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL

#define	RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL

#define	RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5

#define	RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2

#define	RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3

#define	HSION_BitNumber RCC_HSION_BIT_NUMBER

#define	HSION_BITNUMBER RCC_HSION_BIT_NUMBER

#define	HSEON_BitNumber RCC_HSEON_BIT_NUMBER

#define	HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER

#define	MSION_BITNUMBER RCC_MSION_BIT_NUMBER

#define	CSSON_BitNumber RCC_CSSON_BIT_NUMBER

#define	CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER

#define	PLLON_BitNumber RCC_PLLON_BIT_NUMBER

#define	PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER

#define	PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER

#define	I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER

#define	RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER

#define	RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER

#define	BDRST_BitNumber RCC_BDRST_BIT_NUMBER

#define	BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER

#define	RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER

#define	LSION_BitNumber RCC_LSION_BIT_NUMBER

#define	LSION_BITNUMBER RCC_LSION_BIT_NUMBER

#define	LSEON_BitNumber RCC_LSEON_BIT_NUMBER

#define	LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER

#define	LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER

#define	PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER

#define	TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER

#define	RMVF_BitNumber RCC_RMVF_BIT_NUMBER

#define	RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER

#define	RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER

#define	CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS

#define	CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS

#define	CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS

#define	BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS

#define	DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE

#define	LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE

#define	CR_HSION_BB RCC_CR_HSION_BB

#define	CR_CSSON_BB RCC_CR_CSSON_BB

#define	CR_PLLON_BB RCC_CR_PLLON_BB

#define	CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB

#define	CR_MSION_BB RCC_CR_MSION_BB

#define	CSR_LSION_BB RCC_CSR_LSION_BB

#define	CSR_LSEON_BB RCC_CSR_LSEON_BB

#define	CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB

#define	CSR_RTCEN_BB RCC_CSR_RTCEN_BB

#define	CSR_RTCRST_BB RCC_CSR_RTCRST_BB

#define	CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB

#define	BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB

#define	BDCR_BDRST_BB RCC_BDCR_BDRST_BB

#define	CR_HSEON_BB RCC_CR_HSEON_BB

#define	CSR_RMVF_BB RCC_CSR_RMVF_BB

#define	CR_PLLSAION_BB RCC_CR_PLLSAION_BB

#define	DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB

#define	__HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE

#define	__HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE

#define	__HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE

#define	__HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE

#define	__HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE

#define	__HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT

#define	RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN

#define	RCC_CRS_TRIMOV RCC_CRS_TRIMOVF

#define	RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48

#define	RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ

#define	RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP

#define	RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ

#define	IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE

#define	RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48

#define	__HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE

#define	__HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE

#define	__HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED

#define	__HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED

#define	__HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET

#define	__HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET

#define	__HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE

#define	__HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE

#define	__HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED

#define	__HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED

#define	DfsdmClockSelection Dfsdm1ClockSelection

#define	RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1

#define	RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2

#define	RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK

#define	__HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG

#define	__HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE

#define	RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2

#define	RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1

#define	RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1

#define	RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1

#define	RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1

#define	RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2

#define	RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1

#define	RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2

#define	RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2

#define	RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2

#define	RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1

Detailed Description

Macro Definition Documentation

◆ HAL_RC48_EnableBuffer_Cmd

#define HAL_RC48_EnableBuffer_Cmd ( cmd )

Value:

(((cmd\

)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())

Macros

Detailed Description

Macro Definition Documentation

◆ HAL_RC48_EnableBuffer_Cmd