RTEMS 6.1-rc1
Modules | Macros

Modules

 RCCEx CRS Extended Features
 

Macros

#define __HAL_RCC_PLL2_ENABLE()   SET_BIT(RCC->CR, RCC_CR_PLL2ON)
 Macros to enable or disable PLL2. More...
 
#define __HAL_RCC_PLL2_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)
 
#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
 Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) More...
 
#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__)   CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))
 
#define __HAL_RCC_PLL2FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
 Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO. More...
 
#define __HAL_RCC_PLL2FRACN_DISABLE()   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)
 
#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__)
 Macro to configures the PLL2 multiplication and division factors. More...
 
#define __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__)    MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))
 Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor. More...
 
#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__)    MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))
 Macro to select the PLL2 reference frequency range. More...
 
#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__)    MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))
 Macro to select the PLL2 reference frequency range. More...
 
#define __HAL_RCC_PLL3_ENABLE()   SET_BIT(RCC->CR, RCC_CR_PLL3ON)
 Macros to enable or disable the main PLL3. More...
 
#define __HAL_RCC_PLL3_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)
 
#define __HAL_RCC_PLL3FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
 Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO. More...
 
#define __HAL_RCC_PLL3FRACN_DISABLE()   CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)
 
#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
 Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) More...
 
#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__)   CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))
 
#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__)
 Macro to configures the PLL3 multiplication and division factors. More...
 
#define __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__)   MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)
 Macro to configures PLL3 clock Fractional Part of The Multiplication Factor. More...
 
#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__)    MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))
 Macro to select the PLL3 reference frequency range. More...
 
#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__)    MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))
 Macro to select the PLL3 reference frequency range. More...
 
#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__)    MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))
 Macro to Configure the SAI1 clock source. More...
 
#define __HAL_RCC_GET_SAI1_SOURCE()   ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))
 Macro to get the SAI1 clock source. More...
 
#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__)    MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))
 Macro to Configure the SPDIFRX clock source. More...
 
#define __HAL_RCC_GET_SPDIFRX_SOURCE()   ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))
 Macro to get the SPDIFRX clock source. More...
 
#define __HAL_RCC_I2C1235_CONFIG(__I2C1235CLKSource__)    MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__))
 macro to configure the I2C1/2/3/5* clock (I2C123CLK). More...
 
#define __HAL_RCC_I2C123_CONFIG   __HAL_RCC_I2C1235_CONFIG
 
#define __HAL_RCC_GET_I2C1235_SOURCE()   ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL)))
 macro to get the I2C1/2/3/5* clock source. More...
 
#define __HAL_RCC_GET_I2C123_SOURCE   __HAL_RCC_GET_I2C1235_SOURCE
 
#define __HAL_RCC_I2C1_CONFIG   __HAL_RCC_I2C123_CONFIG
 macro to configure the I2C1 clock (I2C1CLK). More...
 
#define __HAL_RCC_GET_I2C1_SOURCE   __HAL_RCC_GET_I2C123_SOURCE
 macro to get the I2C1 clock source. More...
 
#define __HAL_RCC_I2C2_CONFIG   __HAL_RCC_I2C123_CONFIG
 macro to configure the I2C2 clock (I2C2CLK). More...
 
#define __HAL_RCC_GET_I2C2_SOURCE   __HAL_RCC_GET_I2C123_SOURCE
 macro to get the I2C2 clock source. More...
 
#define __HAL_RCC_I2C3_CONFIG   __HAL_RCC_I2C123_CONFIG
 macro to configure the I2C3 clock (I2C3CLK). More...
 
#define __HAL_RCC_GET_I2C3_SOURCE   __HAL_RCC_GET_I2C123_SOURCE
 macro to get the I2C3 clock source. More...
 
#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__)    MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))
 macro to configure the I2C4 clock (I2C4CLK). More...
 
#define __HAL_RCC_GET_I2C4_SOURCE()   ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL)))
 macro to get the I2C4 clock source. More...
 
#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__)    MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))
 macro to configure the USART1/6/9* /10* clock (USART16CLK). More...
 
#define __HAL_RCC_USART16_CONFIG   __HAL_RCC_USART16910_CONFIG
 
#define __HAL_RCC_GET_USART16910_SOURCE()   ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL)))
 macro to get the USART1/6/9* /10* clock source. More...
 
#define __HAL_RCC_GET_USART16_SOURCE   __HAL_RCC_GET_USART16910_SOURCE
 
#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__)    MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))
 macro to configure the USART234578 clock (USART234578CLK). More...
 
#define __HAL_RCC_GET_USART234578_SOURCE()   ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))
 macro to get the USART2/3/4/5/7/8 clock source. More...
 
#define __HAL_RCC_USART1_CONFIG   __HAL_RCC_USART16_CONFIG
 macro to configure the USART1 clock (USART1CLK). More...
 
#define __HAL_RCC_GET_USART1_SOURCE   __HAL_RCC_GET_USART16_SOURCE
 macro to get the USART1 clock source. More...
 
#define __HAL_RCC_USART2_CONFIG   __HAL_RCC_USART234578_CONFIG
 macro to configure the USART2 clock (USART2CLK). More...
 
#define __HAL_RCC_GET_USART2_SOURCE   __HAL_RCC_GET_USART234578_SOURCE
 macro to get the USART2 clock source. More...
 
#define __HAL_RCC_USART3_CONFIG   __HAL_RCC_USART234578_CONFIG
 macro to configure the USART3 clock (USART3CLK). More...
 
#define __HAL_RCC_GET_USART3_SOURCE   __HAL_RCC_GET_USART234578_SOURCE
 macro to get the USART3 clock source. More...
 
#define __HAL_RCC_UART4_CONFIG   __HAL_RCC_USART234578_CONFIG
 macro to configure the UART4 clock (UART4CLK). More...
 
#define __HAL_RCC_GET_UART4_SOURCE   __HAL_RCC_GET_USART234578_SOURCE
 macro to get the UART4 clock source. More...
 
#define __HAL_RCC_UART5_CONFIG   __HAL_RCC_USART234578_CONFIG
 macro to configure the UART5 clock (UART5CLK). More...
 
#define __HAL_RCC_GET_UART5_SOURCE   __HAL_RCC_GET_USART234578_SOURCE
 macro to get the UART5 clock source. More...
 
#define __HAL_RCC_USART6_CONFIG   __HAL_RCC_USART16_CONFIG
 macro to configure the USART6 clock (USART6CLK). More...
 
#define __HAL_RCC_GET_USART6_SOURCE   __HAL_RCC_GET_USART16_SOURCE
 macro to get the USART6 clock source. More...
 
#define __HAL_RCC_UART7_CONFIG   __HAL_RCC_USART234578_CONFIG
 macro to configure the UART5 clock (UART7CLK). More...
 
#define __HAL_RCC_GET_UART7_SOURCE   __HAL_RCC_GET_USART234578_SOURCE
 macro to get the UART7 clock source. More...
 
#define __HAL_RCC_UART8_CONFIG   __HAL_RCC_USART234578_CONFIG
 macro to configure the UART8 clock (UART8CLK). More...
 
#define __HAL_RCC_GET_UART8_SOURCE   __HAL_RCC_GET_USART234578_SOURCE
 macro to get the UART8 clock source. More...
 
#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__)    MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
 macro to configure the LPUART1 clock (LPUART1CLK). More...
 
#define __HAL_RCC_GET_LPUART1_SOURCE()   ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))
 macro to get the LPUART1 clock source. More...
 
#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__)    MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
 macro to configure the LPTIM1 clock source. More...
 
#define __HAL_RCC_GET_LPTIM1_SOURCE()   ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))
 macro to get the LPTIM1 clock source. More...
 
#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__)    MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))
 macro to configure the LPTIM2 clock source. More...
 
#define __HAL_RCC_GET_LPTIM2_SOURCE()   ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))
 macro to get the LPTIM2 clock source. More...
 
#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__)    MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__))
 macro to configure the LPTIM3/4/5 clock source. More...
 
#define __HAL_RCC_GET_LPTIM345_SOURCE()   ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))
 macro to get the LPTIM3/4/5 clock source. More...
 
#define __HAL_RCC_LPTIM3_CONFIG   __HAL_RCC_LPTIM345_CONFIG
 macro to configure the LPTIM3 clock source. More...
 
#define __HAL_RCC_GET_LPTIM3_SOURCE   __HAL_RCC_GET_LPTIM345_SOURCE
 macro to get the LPTIM3 clock source. More...
 
#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__)    MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))
 macro to configure the FMC clock source. More...
 
#define __HAL_RCC_GET_FMC_SOURCE()   ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))
 macro to get the FMC clock source. More...
 
#define __HAL_RCC_USB_CONFIG(__USBCLKSource__)    MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))
 Macro to configure the USB clock (USBCLK). More...
 
#define __HAL_RCC_GET_USB_SOURCE()   ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))
 Macro to get the USB clock source. More...
 
#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__)    MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))
 Macro to configure the ADC clock. More...
 
#define __HAL_RCC_GET_ADC_SOURCE()   ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))
 Macro to get the ADC clock source. More...
 
#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__)    MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))
 Macro to configure the SWPMI1 clock. More...
 
#define __HAL_RCC_GET_SWPMI1_SOURCE()   ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))
 Macro to get the SWPMI1 clock source. More...
 
#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__)    MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))
 Macro to configure the DFSDM1 clock. More...
 
#define __HAL_RCC_GET_DFSDM1_SOURCE()   ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))
 Macro to get the DFSDM1 clock source. More...
 
#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__)    MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))
 macro to configure the CEC clock (CECCLK). More...
 
#define __HAL_RCC_GET_CEC_SOURCE()   ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))
 macro to get the CEC clock source. More...
 
#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__)    MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))
 Macro to configure the CLKP : Oscillator clock for peripheral. More...
 
#define __HAL_RCC_GET_CLKP_SOURCE()   ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))
 Macro to get the Oscillator clock for peripheral source. More...
 
#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__)    MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))
 Macro to Configure the SPI1/2/3 clock source. More...
 
#define __HAL_RCC_GET_SPI123_SOURCE()   ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))
 Macro to get the SPI1/2/3 clock source. More...
 
#define __HAL_RCC_SPI1_CONFIG   __HAL_RCC_SPI123_CONFIG
 Macro to Configure the SPI1 clock source. More...
 
#define __HAL_RCC_GET_SPI1_SOURCE   __HAL_RCC_GET_SPI123_SOURCE
 Macro to get the SPI1 clock source. More...
 
#define __HAL_RCC_SPI2_CONFIG   __HAL_RCC_SPI123_CONFIG
 Macro to Configure the SPI2 clock source. More...
 
#define __HAL_RCC_GET_SPI2_SOURCE   __HAL_RCC_GET_SPI123_SOURCE
 Macro to get the SPI2 clock source. More...
 
#define __HAL_RCC_SPI3_CONFIG   __HAL_RCC_SPI123_CONFIG
 Macro to Configure the SPI3 clock source. More...
 
#define __HAL_RCC_GET_SPI3_SOURCE   __HAL_RCC_GET_SPI123_SOURCE
 Macro to get the SPI3 clock source. More...
 
#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__)    MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))
 Macro to Configure the SPI4/5 clock source. More...
 
#define __HAL_RCC_GET_SPI45_SOURCE()   ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))
 Macro to get the SPI4/5 clock source. More...
 
#define __HAL_RCC_SPI4_CONFIG   __HAL_RCC_SPI45_CONFIG
 Macro to Configure the SPI4 clock source. More...
 
#define __HAL_RCC_GET_SPI4_SOURCE   __HAL_RCC_GET_SPI45_SOURCE
 Macro to get the SPI4 clock source. More...
 
#define __HAL_RCC_SPI5_CONFIG   __HAL_RCC_SPI45_CONFIG
 Macro to Configure the SPI5 clock source. More...
 
#define __HAL_RCC_GET_SPI5_SOURCE   __HAL_RCC_GET_SPI45_SOURCE
 Macro to get the SPI5 clock source. More...
 
#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__)    MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))
 Macro to Configure the SPI6 clock source. More...
 
#define __HAL_RCC_GET_SPI6_SOURCE()   ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))
 Macro to get the SPI6 clock source. More...
 
#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__)    MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))
 Macro to configure the SDMMC clock. More...
 
#define __HAL_RCC_GET_SDMMC_SOURCE()   ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))
 Macro to get the SDMMC clock.
 
#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__)    MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))
 macro to configure the RNG clock (RNGCLK). More...
 
#define __HAL_RCC_GET_RNG_SOURCE()   ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))
 macro to get the RNG clock source. More...
 
#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__)
 Macro to configure the Timers clocks prescalers. More...
 
#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()   SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
 Enable the RCC LSE CSS Extended Interrupt Line. More...
 
#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()   CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)
 Disable the RCC LSE CSS Extended Interrupt Line. More...
 
#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
 Enable the RCC LSE CSS Event Line. More...
 
#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()   CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)
 Disable the RCC LSE CSS Event Line. More...
 
#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
 Enable the RCC LSE CSS Extended Interrupt Falling Trigger. More...
 
#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()   CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)
 Disable the RCC LSE CSS Extended Interrupt Falling Trigger. More...
 
#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
 Enable the RCC LSE CSS Extended Interrupt Rising Trigger. More...
 
#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)
 Disable the RCC LSE CSS Extended Interrupt Rising Trigger. More...
 
#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()
 Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. More...
 
#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()
 Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger. More...
 
#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()   (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)
 Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not. More...
 
#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()   WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)
 Clear the RCC LSE CSS EXTI flag. More...
 
#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()   SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)
 Generate a Software interrupt on the RCC LSE CSS EXTI line. More...
 
#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))
 Enable the specified CRS interrupts. More...
 
#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)   CLEAR_BIT(CRS->CR, (__INTERRUPT__))
 Disable the specified CRS interrupts. More...
 
#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)   ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)
 Check whether the CRS interrupt has occurred or not. More...
 
#define RCC_CRS_IT_ERROR_MASK   ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
 Clear the CRS interrupt pending bits. More...
 
#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)
 
#define __HAL_RCC_CRS_GET_FLAG(__FLAG__)   (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))
 Check whether the specified CRS flag is set or not. More...
 
#define RCC_CRS_FLAG_ERROR_MASK   ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
 Clear the CRS specified FLAG. More...
 
#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)
 

Detailed Description

Macro Definition Documentation

◆ __HAL_RCC_ADC_CONFIG

#define __HAL_RCC_ADC_CONFIG (   __ADCCLKSource__)     MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))

Macro to configure the ADC clock.

Parameters
__ADCCLKSource__specifies the ADC digital interface clock source. This parameter can be one of the following values:
  • RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock

◆ __HAL_RCC_CEC_CONFIG

#define __HAL_RCC_CEC_CONFIG (   __CECCLKSource__)     MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))

macro to configure the CEC clock (CECCLK).

Parameters
__CECCLKSource__specifies the CEC clock source. This parameter can be one of the following values:
  • RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
  • RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
  • RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock

◆ __HAL_RCC_CLKP_CONFIG

#define __HAL_RCC_CLKP_CONFIG (   __CLKPSource__)     MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))

Macro to configure the CLKP : Oscillator clock for peripheral.

Parameters
__CLKPSource__specifies Oscillator clock for peripheral This parameter can be one of the following values:
  • RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
  • RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
  • RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral

◆ __HAL_RCC_CRS_CLEAR_FLAG

#define __HAL_RCC_CRS_CLEAR_FLAG (   __FLAG__)
Value:
do { \
if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \
{ \
WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \
} \
else \
{ \
WRITE_REG(CRS->ICR, (__FLAG__)); \
} \
} while(0)
#define CRS_ICR_ERRC
Definition: stm32h723xx.h:5889
#define RCC_CRS_FLAG_ERROR_MASK
Clear the CRS specified FLAG.
Definition: stm32h7xx_hal_rcc_ex.h:3910

◆ __HAL_RCC_CRS_CLEAR_IT

#define __HAL_RCC_CRS_CLEAR_IT (   __INTERRUPT__)
Value:
do { \
if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \
{ \
WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \
} \
else \
{ \
WRITE_REG(CRS->ICR, (__INTERRUPT__)); \
} \
} while(0)
#define RCC_CRS_IT_ERROR_MASK
Clear the CRS interrupt pending bits.
Definition: stm32h7xx_hal_rcc_ex.h:3866

◆ __HAL_RCC_CRS_DISABLE_IT

#define __HAL_RCC_CRS_DISABLE_IT (   __INTERRUPT__)    CLEAR_BIT(CRS->CR, (__INTERRUPT__))

Disable the specified CRS interrupts.

Parameters
__INTERRUPT__specifies the CRS interrupt sources to be disabled. This parameter can be any combination of the following values:
Return values
None

◆ __HAL_RCC_CRS_ENABLE_IT

#define __HAL_RCC_CRS_ENABLE_IT (   __INTERRUPT__)    SET_BIT(CRS->CR, (__INTERRUPT__))

Enable the specified CRS interrupts.

Parameters
__INTERRUPT__specifies the CRS interrupt sources to be enabled. This parameter can be any combination of the following values:
Return values
None

◆ __HAL_RCC_CRS_GET_FLAG

#define __HAL_RCC_CRS_GET_FLAG (   __FLAG__)    (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))

Check whether the specified CRS flag is set or not.

Parameters
__FLAG__specifies the flag to check. This parameter can be one of the following values:
Return values
Thenew state of FLAG (TRUE or FALSE).

◆ __HAL_RCC_CRS_GET_IT_SOURCE

#define __HAL_RCC_CRS_GET_IT_SOURCE (   __INTERRUPT__)    ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)

Check whether the CRS interrupt has occurred or not.

Parameters
__INTERRUPT__specifies the CRS interrupt source to check. This parameter can be one of the following values:
Return values
Thenew state of INTERRUPT (SET or RESET).

◆ __HAL_RCC_DFSDM1_CONFIG

#define __HAL_RCC_DFSDM1_CONFIG (   __DFSDM1CLKSource__)     MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))

Macro to configure the DFSDM1 clock.

Parameters
__DFSDM1CLKSource__specifies the DFSDM1 clock source. This parameter can be one of the following values:
  • RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
  • RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock

◆ __HAL_RCC_FMC_CONFIG

#define __HAL_RCC_FMC_CONFIG (   __FMCCLKSource__)     MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))

macro to configure the FMC clock source.

Parameters
__FMCCLKSource__specifies the FMC clock source.
  • RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock

◆ __HAL_RCC_GET_ADC_SOURCE

#define __HAL_RCC_GET_ADC_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))

Macro to get the ADC clock source.

Return values
Theclock source can be one of the following values:
  • RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock
  • RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock

◆ __HAL_RCC_GET_CEC_SOURCE

#define __HAL_RCC_GET_CEC_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))

macro to get the CEC clock source.

Return values
Theclock source can be one of the following values:
  • RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
  • RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock
  • RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock

◆ __HAL_RCC_GET_CLKP_SOURCE

#define __HAL_RCC_GET_CLKP_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))

Macro to get the Oscillator clock for peripheral source.

Return values
Theclock source can be one of the following values:
  • RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral
  • RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral
  • RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral

◆ __HAL_RCC_GET_DFSDM1_SOURCE

#define __HAL_RCC_GET_DFSDM1_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))

Macro to get the DFSDM1 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_DFSDM1CLKSOURCE_D2PCLK: D2PCLK Clock selected as DFSDM1 clock
  • RCC_DFSDM1CLKSOURCE_SYS: System Clock selected as DFSDM1 clock

◆ __HAL_RCC_GET_FMC_SOURCE

#define __HAL_RCC_GET_FMC_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))

macro to get the FMC clock source.

Return values
Theclock source can be one of the following values:
  • RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_PLL : PLL1_Q Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_PLL2 : PLL2_R Clock selected as FMC clock
  • RCC_RCC_FMCCLKSOURCE_CLKP CLKP selected as FMC clock

◆ __HAL_RCC_GET_I2C1235_SOURCE

#define __HAL_RCC_GET_I2C1235_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL)))

macro to get the I2C1/2/3/5* clock source.

Return values
Theclock source can be one of the following values:
  • RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock
  • RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock
  • RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock
  • RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock
(**): Available on stm32h72xxx and stm32h73xxx family lines.

◆ __HAL_RCC_GET_I2C1_SOURCE

#define __HAL_RCC_GET_I2C1_SOURCE   __HAL_RCC_GET_I2C123_SOURCE

macro to get the I2C1 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock

◆ __HAL_RCC_GET_I2C2_SOURCE

#define __HAL_RCC_GET_I2C2_SOURCE   __HAL_RCC_GET_I2C123_SOURCE

macro to get the I2C2 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock

◆ __HAL_RCC_GET_I2C3_SOURCE

#define __HAL_RCC_GET_I2C3_SOURCE   __HAL_RCC_GET_I2C123_SOURCE

macro to get the I2C3 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock

◆ __HAL_RCC_GET_I2C4_SOURCE

#define __HAL_RCC_GET_I2C4_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL)))

macro to get the I2C4 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock

◆ __HAL_RCC_GET_LPTIM1_SOURCE

#define __HAL_RCC_GET_LPTIM1_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))

macro to get the LPTIM1 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock

◆ __HAL_RCC_GET_LPTIM2_SOURCE

#define __HAL_RCC_GET_LPTIM2_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))

macro to get the LPTIM2 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock

◆ __HAL_RCC_GET_LPTIM345_SOURCE

#define __HAL_RCC_GET_LPTIM345_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))

macro to get the LPTIM3/4/5 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock

◆ __HAL_RCC_GET_LPTIM3_SOURCE

#define __HAL_RCC_GET_LPTIM3_SOURCE   __HAL_RCC_GET_LPTIM345_SOURCE

macro to get the LPTIM3 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock

◆ __HAL_RCC_GET_LPUART1_SOURCE

#define __HAL_RCC_GET_LPUART1_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))

macro to get the LPUART1 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock

◆ __HAL_RCC_GET_RNG_SOURCE

#define __HAL_RCC_GET_RNG_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))

macro to get the RNG clock source.

Return values
Theclock source can be one of the following values:
  • RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
  • RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
  • RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
  • RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock

◆ __HAL_RCC_GET_SAI1_SOURCE

#define __HAL_RCC_GET_SAI1_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))

Macro to get the SAI1 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
  • RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
  • RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
  • RCC_SAI1CLKSOURCE_CLKP: SAI1 clock = CLKP
  • RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock

◆ __HAL_RCC_GET_SPDIFRX_SOURCE

#define __HAL_RCC_GET_SPDIFRX_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))

Macro to get the SPDIFRX clock source.

Return values
None

◆ __HAL_RCC_GET_SPI123_SOURCE

#define __HAL_RCC_GET_SPI123_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))

Macro to get the SPI1/2/3 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
  • RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
  • RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
  • RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
  • RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock

◆ __HAL_RCC_GET_SPI1_SOURCE

#define __HAL_RCC_GET_SPI1_SOURCE   __HAL_RCC_GET_SPI123_SOURCE

Macro to get the SPI1 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
  • RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
  • RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
  • RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP
  • RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock

◆ __HAL_RCC_GET_SPI2_SOURCE

#define __HAL_RCC_GET_SPI2_SOURCE   __HAL_RCC_GET_SPI123_SOURCE

Macro to get the SPI2 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
  • RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
  • RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
  • RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP
  • RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock

◆ __HAL_RCC_GET_SPI3_SOURCE

#define __HAL_RCC_GET_SPI3_SOURCE   __HAL_RCC_GET_SPI123_SOURCE

Macro to get the SPI3 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
  • RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
  • RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
  • RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP
  • RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock

◆ __HAL_RCC_GET_SPI45_SOURCE

#define __HAL_RCC_GET_SPI45_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))

Macro to get the SPI4/5 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2
  • RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
  • RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
  • RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
  • RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
  • RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE

◆ __HAL_RCC_GET_SPI4_SOURCE

#define __HAL_RCC_GET_SPI4_SOURCE   __HAL_RCC_GET_SPI45_SOURCE

Macro to get the SPI4 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2
  • RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
  • RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
  • RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
  • RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
  • RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE

◆ __HAL_RCC_GET_SPI5_SOURCE

#define __HAL_RCC_GET_SPI5_SOURCE   __HAL_RCC_GET_SPI45_SOURCE

Macro to get the SPI5 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2
  • RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
  • RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
  • RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
  • RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
  • RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE

◆ __HAL_RCC_GET_SPI6_SOURCE

#define __HAL_RCC_GET_SPI6_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))

Macro to get the SPI6 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
  • RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
  • RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
  • RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
  • RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
  • RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
  • RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN

◆ __HAL_RCC_GET_SWPMI1_SOURCE

#define __HAL_RCC_GET_SWPMI1_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))

Macro to get the SWPMI1 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
  • RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock

◆ __HAL_RCC_GET_UART4_SOURCE

#define __HAL_RCC_GET_UART4_SOURCE   __HAL_RCC_GET_USART234578_SOURCE

macro to get the UART4 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
  • RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

◆ __HAL_RCC_GET_UART5_SOURCE

#define __HAL_RCC_GET_UART5_SOURCE   __HAL_RCC_GET_USART234578_SOURCE

macro to get the UART5 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
  • RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

◆ __HAL_RCC_GET_UART7_SOURCE

#define __HAL_RCC_GET_UART7_SOURCE   __HAL_RCC_GET_USART234578_SOURCE

macro to get the UART7 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
  • RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

◆ __HAL_RCC_GET_UART8_SOURCE

#define __HAL_RCC_GET_UART8_SOURCE   __HAL_RCC_GET_USART234578_SOURCE

macro to get the UART8 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
  • RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

◆ __HAL_RCC_GET_USART16910_SOURCE

#define __HAL_RCC_GET_USART16910_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL)))

macro to get the USART1/6/9* /10* clock source.

Return values
Theclock source can be one of the following values:
  • RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
(*) : Available on some STM32H7 lines only.

◆ __HAL_RCC_GET_USART1_SOURCE

#define __HAL_RCC_GET_USART1_SOURCE   __HAL_RCC_GET_USART16_SOURCE

macro to get the USART1 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

◆ __HAL_RCC_GET_USART234578_SOURCE

#define __HAL_RCC_GET_USART234578_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))

macro to get the USART2/3/4/5/7/8 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock

◆ __HAL_RCC_GET_USART2_SOURCE

#define __HAL_RCC_GET_USART2_SOURCE   __HAL_RCC_GET_USART234578_SOURCE

macro to get the USART2 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock

◆ __HAL_RCC_GET_USART3_SOURCE

#define __HAL_RCC_GET_USART3_SOURCE   __HAL_RCC_GET_USART234578_SOURCE

macro to get the USART3 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock

◆ __HAL_RCC_GET_USART6_SOURCE

#define __HAL_RCC_GET_USART6_SOURCE   __HAL_RCC_GET_USART16_SOURCE

macro to get the USART6 clock source.

Return values
Theclock source can be one of the following values:
  • RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
  • RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock

◆ __HAL_RCC_GET_USB_SOURCE

#define __HAL_RCC_GET_USB_SOURCE ( )    ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))

Macro to get the USB clock source.

Return values
Theclock source can be one of the following values:
  • RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
  • RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
  • RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock

◆ __HAL_RCC_I2C1235_CONFIG

#define __HAL_RCC_I2C1235_CONFIG (   __I2C1235CLKSource__)     MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C1235SEL, (uint32_t)(__I2C1235CLKSource__))

macro to configure the I2C1/2/3/5* clock (I2C123CLK).

Parameters
__I2C1235CLKSource__specifies the I2C1/2/3/5* clock source. This parameter can be one of the following values:
  • RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3/5* clock
  • RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3/5* clock
  • RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3/5* clock
  • RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3/5* clock
(**): Available on stm32h72xxx and stm32h73xxx family lines.

◆ __HAL_RCC_I2C1_CONFIG

#define __HAL_RCC_I2C1_CONFIG   __HAL_RCC_I2C123_CONFIG

macro to configure the I2C1 clock (I2C1CLK).

Parameters
__I2C1CLKSource__specifies the I2C1 clock source. This parameter can be one of the following values:
  • RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
  • RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock

◆ __HAL_RCC_I2C2_CONFIG

#define __HAL_RCC_I2C2_CONFIG   __HAL_RCC_I2C123_CONFIG

macro to configure the I2C2 clock (I2C2CLK).

Parameters
__I2C2CLKSource__specifies the I2C2 clock source. This parameter can be one of the following values:
  • RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
  • RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock

◆ __HAL_RCC_I2C3_CONFIG

#define __HAL_RCC_I2C3_CONFIG   __HAL_RCC_I2C123_CONFIG

macro to configure the I2C3 clock (I2C3CLK).

Parameters
__I2C3CLKSource__specifies the I2C3 clock source. This parameter can be one of the following values:
  • RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
  • RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock

◆ __HAL_RCC_I2C4_CONFIG

#define __HAL_RCC_I2C4_CONFIG (   __I2C4CLKSource__)     MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))

macro to configure the I2C4 clock (I2C4CLK).

Parameters
__I2C4CLKSource__specifies the I2C4 clock source. This parameter can be one of the following values:
  • RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
  • RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock

◆ __HAL_RCC_LPTIM1_CONFIG

#define __HAL_RCC_LPTIM1_CONFIG (   __LPTIM1CLKSource__)     MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))

macro to configure the LPTIM1 clock source.

Parameters
__LPTIM1CLKSource__specifies the LPTIM1 clock source. This parameter can be one of the following values:
  • RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock
  • RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock

◆ __HAL_RCC_LPTIM2_CONFIG

#define __HAL_RCC_LPTIM2_CONFIG (   __LPTIM2CLKSource__)     MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))

macro to configure the LPTIM2 clock source.

Parameters
__LPTIM2CLKSource__specifies the LPTIM2 clock source. This parameter can be one of the following values:
  • RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock
  • RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock

◆ __HAL_RCC_LPTIM345_CONFIG

#define __HAL_RCC_LPTIM345_CONFIG (   __LPTIM345CLKSource__)     MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM345CLKSource__))

macro to configure the LPTIM3/4/5 clock source.

Parameters
__LPTIM345CLKSource__specifies the LPTIM3/4/5 clock source.
  • RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock
  • RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock

◆ __HAL_RCC_LPTIM3_CONFIG

#define __HAL_RCC_LPTIM3_CONFIG   __HAL_RCC_LPTIM345_CONFIG

macro to configure the LPTIM3 clock source.

Parameters
__LPTIM3CLKSource__specifies the LPTIM3 clock source.
  • RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock
  • RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock

◆ __HAL_RCC_LPUART1_CONFIG

#define __HAL_RCC_LPUART1_CONFIG (   __LPUART1CLKSource__)     MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))

macro to configure the LPUART1 clock (LPUART1CLK).

Parameters
__LPUART1CLKSource__specifies the LPUART1 clock source. This parameter can be one of the following values:
  • RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock
  • RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock

◆ __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG

#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG ( )    WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)

Clear the RCC LSE CSS EXTI flag.

Return values
None.

◆ __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT

#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT ( )    CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Event Line.

Return values
None.

◆ __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE

#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE ( )    CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt Falling Trigger.

Return values
None.

◆ __HAL_RCC_LSECSS_EXTI_DISABLE_IT

#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT ( )    CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt Line.

Return values
None

◆ __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE

#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE ( )    CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)

Disable the RCC LSE CSS Extended Interrupt Rising Trigger.

Return values
None.

◆ __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE

#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE ( )
Value:
do { \
__HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE(); \
__HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)

Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.

Return values
None.

◆ __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT

#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT ( )    SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Event Line.

Return values
None.

◆ __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE

#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE ( )    SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt Falling Trigger.

Return values
None.

◆ __HAL_RCC_LSECSS_EXTI_ENABLE_IT

#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT ( )    SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt Line.

Return values
None

◆ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE

#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE ( )    SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)

Enable the RCC LSE CSS Extended Interrupt Rising Trigger.

Return values
None.

◆ __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE

#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE ( )
Value:
do { \
__HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); \
__HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)

Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.

Return values
None.

◆ __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT

#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT ( )    SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)

Generate a Software interrupt on the RCC LSE CSS EXTI line.

Return values
None.

◆ __HAL_RCC_LSECSS_EXTI_GET_FLAG

#define __HAL_RCC_LSECSS_EXTI_GET_FLAG ( )    (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)

Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.

Return values
EXTIRCC LSE CSS Line Status.

◆ __HAL_RCC_PLL2_CONFIG

#define __HAL_RCC_PLL2_CONFIG (   __PLL2M__,
  __PLL2N__,
  __PLL2P__,
  __PLL2Q__,
  __PLL2R__ 
)
Value:
do{ \
MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U)); \
WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \
((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \
} while(0)

Macro to configures the PLL2 multiplication and division factors.

Note
This function must be used only when PLL2 is disabled.
Parameters
__PLL2M__specifies the division factor for PLL2 VCO input clock This parameter must be a number between 1 and 63.
Note
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.
Parameters
__PLL2N__specifies the multiplication factor for PLL2 VCO output clock This parameter must be a number between 4 and 512 or between 8 and 420(*).
Note
You have to set the PLL2N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
Parameters
__PLL2P__specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.
__PLL2Q__specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.
__PLL2R__specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128.
Note
To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible value to PLL2P, PLL2Q or PLL2R parameters.
Return values
None

(*) : For stm32h7a3xx and stm32h7b3xx family lines.

◆ __HAL_RCC_PLL2_ENABLE

#define __HAL_RCC_PLL2_ENABLE ( )    SET_BIT(RCC->CR, RCC_CR_PLL2ON)

Macros to enable or disable PLL2.

Note
After enabling PLL2, the application software should wait on PLL2RDY flag to be set indicating that PLL2 clock is stable and can be used as kernel clock source.
PLL2 is disabled by hardware when entering STOP and STANDBY modes.

◆ __HAL_RCC_PLL2_VCIRANGE

#define __HAL_RCC_PLL2_VCIRANGE (   __RCC_PLL2VCIRange__)     MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))

Macro to select the PLL2 reference frequency range.

Parameters
__RCC_PLL2VCIRange__specifies the PLL2 input frequency range This parameter can be one of the following values:
  • RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz
  • RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz
  • RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz
  • RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz
Return values
None

◆ __HAL_RCC_PLL2_VCORANGE

#define __HAL_RCC_PLL2_VCORANGE (   __RCC_PLL2VCORange__)     MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))

Macro to select the PLL2 reference frequency range.

Parameters
__RCC_PLL2VCORange__Specifies the PLL2 input frequency range This parameter can be one of the following values:
  • RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
  • RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz
(*) : For stm32h7a3xx and stm32h7b3xx family lines.
Return values
None

◆ __HAL_RCC_PLL2CLKOUT_ENABLE

#define __HAL_RCC_PLL2CLKOUT_ENABLE (   __RCC_PLL2ClockOut__)    SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))

Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)

Note
Enabling/disabling those Clocks can be done only when the PLL2 is disabled, This is mainly used to save Power.
Parameters
__RCC_PLL2ClockOut__Specifies the PLL2 clock to be outputted This parameter can be one of the following values:
  • RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
  • RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
  • RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
(*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
Return values
None

◆ __HAL_RCC_PLL2FRACN_CONFIG

#define __HAL_RCC_PLL2FRACN_CONFIG (   __RCC_PLL2FRACN__)     MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))

Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor.

Note
These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO
Parameters
__RCC_PLL2FRACN__Specifies Fractional Part Of The Multiplication factor for PLL2 VCO It should be a value between 0 and 8191
Note
Warning: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0 150 to 420 MHz if PLL2VCOSEL = 1.

(*) : For stm32h7a3xx and stm32h7b3xx family lines.

Return values
None

◆ __HAL_RCC_PLL2FRACN_ENABLE

#define __HAL_RCC_PLL2FRACN_ENABLE ( )    SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)

Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO.

Note
Enabling/disabling Fractional Part can be any time without the need to stop the PLL2
Return values
None

◆ __HAL_RCC_PLL3_CONFIG

#define __HAL_RCC_PLL3_CONFIG (   __PLL3M__,
  __PLL3N__,
  __PLL3P__,
  __PLL3Q__,
  __PLL3R__ 
)
Value:
do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U)); \
WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \
((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \
} while(0)

Macro to configures the PLL3 multiplication and division factors.

Note
This function must be used only when PLL3 is disabled.
Parameters
__PLL3M__specifies the division factor for PLL3 VCO input clock This parameter must be a number between 1 and 63.
Note
You have to set the PLLM parameter correctly to ensure that the VCO input frequency ranges from 1 to 16 MHz.
Parameters
__PLL3N__specifies the multiplication factor for PLL3 VCO output clock This parameter must be a number between 4 and 512.
Note
You have to set the PLL3N parameter correctly to ensure that the VCO output frequency is between 150 and 420 MHz (when in medium VCO range) or between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)
Parameters
__PLL3P__specifies the division factor for peripheral kernel clocks This parameter must be a number between 2 and 128 (where odd numbers not allowed)
__PLL3Q__specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
__PLL3R__specifies the division factor for peripheral kernel clocks This parameter must be a number between 1 and 128
Note
To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR) is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible value to PLL3P, PLL3Q or PLL3R parameters.
Return values
None

(*) : For stm32h7a3xx and stm32h7b3xx family lines.

◆ __HAL_RCC_PLL3_ENABLE

#define __HAL_RCC_PLL3_ENABLE ( )    SET_BIT(RCC->CR, RCC_CR_PLL3ON)

Macros to enable or disable the main PLL3.

Note
After enabling PLL3, the application software should wait on PLL3RDY flag to be set indicating that PLL3 clock is stable and can be used as kernel clock source.
PLL3 is disabled by hardware when entering STOP and STANDBY modes.

◆ __HAL_RCC_PLL3_VCIRANGE

#define __HAL_RCC_PLL3_VCIRANGE (   __RCC_PLL3VCIRange__)     MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))

Macro to select the PLL3 reference frequency range.

Parameters
__RCC_PLL3VCIRange__specifies the PLL1 input frequency range This parameter can be one of the following values:
  • RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz
  • RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz
  • RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz
  • RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz
Return values
None

◆ __HAL_RCC_PLL3_VCORANGE

#define __HAL_RCC_PLL3_VCORANGE (   __RCC_PLL3VCORange__)     MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))

Macro to select the PLL3 reference frequency range.

Parameters
__RCC_PLL3VCORange__specifies the PLL1 input frequency range This parameter can be one of the following values:
  • RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)
  • RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz
(*) : For stm32h7a3xx and stm32h7b3xx family lines.
Return values
None

◆ __HAL_RCC_PLL3CLKOUT_ENABLE

#define __HAL_RCC_PLL3CLKOUT_ENABLE (   __RCC_PLL3ClockOut__)    SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))

Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)

Note
Enabling/disabling those Clocks can be done only when the PLL3 is disabled, This is mainly used to save Power.
Parameters
__RCC_PLL3ClockOut__specifies the PLL3 clock to be outputted This parameter can be one of the following values:
  • RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
  • RCC_PLL3_DIVQ: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
  • RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 550MHZ(*), 480MHZ(**) or 280MHZ(***)
(*) : For stm32h72xxx and stm32h73xxx family lines and requires to enable the CPU_FREQ_BOOST flash option byte, 520MHZ otherwise. (**) : For stm32h74xx and stm32h75xx family lines and requires the board to be connected on LDO regulator not SMPS, 400MHZ otherwise. (***): For stm32h7a3xx, stm32h7b3xx and stm32h7b0xx family lines.
Return values
None

◆ __HAL_RCC_PLL3FRACN_CONFIG

#define __HAL_RCC_PLL3FRACN_CONFIG (   __RCC_PLL3FRACN__)    MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)

Macro to configures PLL3 clock Fractional Part of The Multiplication Factor.

Note
These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO
Parameters
__RCC_PLL3FRACN__specifies Fractional Part Of The Multiplication Factor for PLL3 VCO It should be a value between 0 and 8191
Note
Warning: the software has to set correctly these bits to insure that the VCO output frequency is between its valid frequency range, which is: 192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0 150 to 420 MHz if PLL3VCOSEL = 1.

(*) : For stm32h7a3xx and stm32h7b3xx family lines.

Return values
None

◆ __HAL_RCC_PLL3FRACN_ENABLE

#define __HAL_RCC_PLL3FRACN_ENABLE ( )    SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)

Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO.

Note
Enabling/disabling Fractional Part can be any time without the need to stop the PLL3
Return values
None

◆ __HAL_RCC_RNG_CONFIG

#define __HAL_RCC_RNG_CONFIG (   __RNGCLKSource__)     MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))

macro to configure the RNG clock (RNGCLK).

Parameters
__RNGCLKSource__specifies the RNG clock source. This parameter can be one of the following values:
  • RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
  • RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock
  • RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock
  • RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock

◆ __HAL_RCC_SAI1_CONFIG

#define __HAL_RCC_SAI1_CONFIG (   __RCC_SAI1CLKSource__)     MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))

Macro to Configure the SAI1 clock source.

Parameters
__RCC_SAI1CLKSource__defines the SAI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL
  • RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2
  • RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3
  • RCC_SAI1CLKSOURCE_OSC: SAI1 clock = OSC
  • RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock
Return values
None

◆ __HAL_RCC_SDMMC_CONFIG

#define __HAL_RCC_SDMMC_CONFIG (   __SDMMCCLKSource__)     MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))

Macro to configure the SDMMC clock.

Parameters
__SDMMCCLKSource__specifies clock source for SDMMC This parameter can be one of the following values:
  • RCC_SDMMCCLKSOURCE_PLL: PLLQ selected as SDMMC clock
  • RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock

◆ __HAL_RCC_SPDIFRX_CONFIG

#define __HAL_RCC_SPDIFRX_CONFIG (   __RCC_SPDIFCLKSource__)     MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))

Macro to Configure the SPDIFRX clock source.

Parameters
__RCC_SPDIFCLKSource__defines the SPDIFRX clock source. This clock is derived from system PLL, PLL2, PLL3, or internal OSC clock This parameter can be one of the following values:
  • RCC_SPDIFRXCLKSOURCE_PLL: SPDIFRX clock = PLL
  • RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2
  • RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3
  • RCC_SPDIFRXCLKSOURCE_HSI: SPDIFRX clock = HSI
Return values
None

◆ __HAL_RCC_SPI123_CONFIG

#define __HAL_RCC_SPI123_CONFIG (   __RCC_SPI123CLKSource__)     MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))

Macro to Configure the SPI1/2/3 clock source.

Parameters
__RCC_SPI123CLKSource__defines the SPI1/2/3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL
  • RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2
  • RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3
  • RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock = CLKP
  • RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock
Return values
None

◆ __HAL_RCC_SPI1_CONFIG

#define __HAL_RCC_SPI1_CONFIG   __HAL_RCC_SPI123_CONFIG

Macro to Configure the SPI1 clock source.

Parameters
__RCC_SPI1CLKSource__defines the SPI1 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL
  • RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2
  • RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3
  • RCC_SPI1CLKSOURCE_CLKP: SPI1 clock = CLKP
  • RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock
Return values
None

◆ __HAL_RCC_SPI2_CONFIG

#define __HAL_RCC_SPI2_CONFIG   __HAL_RCC_SPI123_CONFIG

Macro to Configure the SPI2 clock source.

Parameters
__RCC_SPI2CLKSource__defines the SPI2 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL
  • RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2
  • RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3
  • RCC_SPI2CLKSOURCE_CLKP: SPI2 clock = CLKP
  • RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock
Return values
None

◆ __HAL_RCC_SPI3_CONFIG

#define __HAL_RCC_SPI3_CONFIG   __HAL_RCC_SPI123_CONFIG

Macro to Configure the SPI3 clock source.

Parameters
__RCC_SPI3CLKSource__defines the SPI3 clock source. This clock is derived from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN) This parameter can be one of the following values:
  • RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL
  • RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2
  • RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3
  • RCC_SPI3CLKSOURCE_CLKP: SPI3 clock = CLKP
  • RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock
Return values
None

◆ __HAL_RCC_SPI45_CONFIG

#define __HAL_RCC_SPI45_CONFIG (   __RCC_SPI45CLKSource__)     MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))

Macro to Configure the SPI4/5 clock source.

Parameters
__RCC_SPI45CLKSource__defines the SPI4/5 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values:
  • RCC_SPI45CLKSOURCE_D2PCLK2:SPI4/5 clock = D2PCLK2
  • RCC_SPI45CLKSOURCE_PLL2: SPI4/5 clock = PLL2
  • RCC_SPI45CLKSOURCE_PLL3: SPI4/5 clock = PLL3
  • RCC_SPI45CLKSOURCE_HSI: SPI4/5 clock = HSI
  • RCC_SPI45CLKSOURCE_CSI: SPI4/5 clock = CSI
  • RCC_SPI45CLKSOURCE_HSE: SPI4/5 clock = HSE
Return values
None

◆ __HAL_RCC_SPI4_CONFIG

#define __HAL_RCC_SPI4_CONFIG   __HAL_RCC_SPI45_CONFIG

Macro to Configure the SPI4 clock source.

Parameters
__RCC_SPI4CLKSource__defines the SPI4 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values:
  • RCC_SPI4CLKSOURCE_D2PCLK2:SPI4 clock = D2PCLK2
  • RCC_SPI4CLKSOURCE_PLL2: SPI4 clock = PLL2
  • RCC_SPI4CLKSOURCE_PLL3: SPI4 clock = PLL3
  • RCC_SPI4CLKSOURCE_HSI: SPI4 clock = HSI
  • RCC_SPI4CLKSOURCE_CSI: SPI4 clock = CSI
  • RCC_SPI4CLKSOURCE_HSE: SPI4 clock = HSE
Return values
None

◆ __HAL_RCC_SPI5_CONFIG

#define __HAL_RCC_SPI5_CONFIG   __HAL_RCC_SPI45_CONFIG

Macro to Configure the SPI5 clock source.

Parameters
__RCC_SPI5CLKSource__defines the SPI5 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values:
  • RCC_SPI5CLKSOURCE_D2PCLK2:SPI5 clock = D2PCLK2
  • RCC_SPI5CLKSOURCE_PLL2: SPI5 clock = PLL2
  • RCC_SPI5CLKSOURCE_PLL3: SPI5 clock = PLL3
  • RCC_SPI5CLKSOURCE_HSI: SPI5 clock = HSI
  • RCC_SPI5CLKSOURCE_CSI: SPI5 clock = CSI
  • RCC_SPI5CLKSOURCE_HSE: SPI5 clock = HSE
Return values
None

◆ __HAL_RCC_SPI6_CONFIG

#define __HAL_RCC_SPI6_CONFIG (   __RCC_SPI6CLKSource__)     MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))

Macro to Configure the SPI6 clock source.

Parameters
__RCC_SPI6CLKSource__defines the SPI6 clock source. This clock is derived from system PCLK, PLL2, PLL3, OSC This parameter can be one of the following values:
  • RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1
  • RCC_SPI6CLKSOURCE_PLL2: SPI6 clock = PLL2
  • RCC_SPI6CLKSOURCE_PLL3: SPI6 clock = PLL3
  • RCC_SPI6CLKSOURCE_HSI: SPI6 clock = HSI
  • RCC_SPI6CLKSOURCE_CSI: SPI6 clock = CSI
  • RCC_SPI6CLKSOURCE_HSE: SPI6 clock = HSE
  • RCC_SPI6CLKSOURCE_PIN: SPI6 clock = I2S_CKIN (*)
Return values
None

(*) : Available on stm32h7a3xx and stm32h7b3xx family lines.

◆ __HAL_RCC_SWPMI1_CONFIG

#define __HAL_RCC_SWPMI1_CONFIG (   __SWPMI1CLKSource__)     MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))

Macro to configure the SWPMI1 clock.

Parameters
__SWPMI1CLKSource__specifies the SWPMI1 clock source. This parameter can be one of the following values:
  • RCC_SWPMI1CLKSOURCE_D2PCLK1: D2PCLK1 Clock selected as SWPMI1 clock
  • RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock

◆ __HAL_RCC_TIMCLKPRESCALER

#define __HAL_RCC_TIMCLKPRESCALER (   __PRESC__)
Value:
do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\
RCC->CFGR |= (__PRESC__); \
}while(0)
#define RCC_CFGR_TIMPRE
Definition: stm32h723xx.h:14552

Macro to configure the Timers clocks prescalers.

Parameters
__PRESC__specifies the Timers clocks prescalers selection This parameter can be one of the following values:
  • RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2, else it is equal to 2 x Frcc_pclkx_d2 (default after reset)
  • RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4, else it is equal to 4 x Frcc_pclkx_d2

◆ __HAL_RCC_UART4_CONFIG

#define __HAL_RCC_UART4_CONFIG   __HAL_RCC_USART234578_CONFIG

macro to configure the UART4 clock (UART4CLK).

Parameters
__UART4CLKSource__specifies the UART4 clock source. This parameter can be one of the following values:
  • RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
  • RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock
  • RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

◆ __HAL_RCC_UART5_CONFIG

#define __HAL_RCC_UART5_CONFIG   __HAL_RCC_USART234578_CONFIG

macro to configure the UART5 clock (UART5CLK).

Parameters
__UART5CLKSource__specifies the UART5 clock source. This parameter can be one of the following values:
  • RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
  • RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock
  • RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

◆ __HAL_RCC_UART7_CONFIG

#define __HAL_RCC_UART7_CONFIG   __HAL_RCC_USART234578_CONFIG

macro to configure the UART5 clock (UART7CLK).

Parameters
__UART7CLKSource__specifies the UART7 clock source. This parameter can be one of the following values:
  • RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
  • RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock
  • RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

◆ __HAL_RCC_UART8_CONFIG

#define __HAL_RCC_UART8_CONFIG   __HAL_RCC_USART234578_CONFIG

macro to configure the UART8 clock (UART8CLK).

Parameters
__UART8CLKSource__specifies the UART8 clock source. This parameter can be one of the following values:
  • RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
  • RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock
  • RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

◆ __HAL_RCC_USART16910_CONFIG

#define __HAL_RCC_USART16910_CONFIG (   __USART16910CLKSource__)     MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))

macro to configure the USART1/6/9* /10* clock (USART16CLK).

Parameters
__USART16910CLKSource__specifies the USART1/6/9* /10* clock source. This parameter can be one of the following values:
  • RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock
  • RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock
(*) : Available on some STM32H7 lines only.

◆ __HAL_RCC_USART1_CONFIG

#define __HAL_RCC_USART1_CONFIG   __HAL_RCC_USART16_CONFIG

macro to configure the USART1 clock (USART1CLK).

Parameters
__USART1CLKSource__specifies the USART1 clock source. This parameter can be one of the following values:
  • RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
  • RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock
  • RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

◆ __HAL_RCC_USART234578_CONFIG

#define __HAL_RCC_USART234578_CONFIG (   __USART234578CLKSource__)     MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))

macro to configure the USART234578 clock (USART234578CLK).

Parameters
__USART234578CLKSource__specifies the USART2/3/4/5/7/8 clock source. This parameter can be one of the following values:
  • RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock
  • RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock

◆ __HAL_RCC_USART2_CONFIG

#define __HAL_RCC_USART2_CONFIG   __HAL_RCC_USART234578_CONFIG

macro to configure the USART2 clock (USART2CLK).

Parameters
__USART2CLKSource__specifies the USART2 clock source. This parameter can be one of the following values:
  • RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
  • RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock
  • RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock

◆ __HAL_RCC_USART3_CONFIG

#define __HAL_RCC_USART3_CONFIG   __HAL_RCC_USART234578_CONFIG

macro to configure the USART3 clock (USART3CLK).

Parameters
__USART3CLKSource__specifies the USART3 clock source. This parameter can be one of the following values:
  • RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
  • RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock
  • RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock

◆ __HAL_RCC_USART6_CONFIG

#define __HAL_RCC_USART6_CONFIG   __HAL_RCC_USART16_CONFIG

macro to configure the USART6 clock (USART6CLK).

Parameters
__USART6CLKSource__specifies the USART6 clock source. This parameter can be one of the following values:
  • RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
  • RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock
  • RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock

◆ __HAL_RCC_USB_CONFIG

#define __HAL_RCC_USB_CONFIG (   __USBCLKSource__)     MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))

Macro to configure the USB clock (USBCLK).

Parameters
__USBCLKSource__specifies the USB clock source. This parameter can be one of the following values:
  • RCC_USBCLKSOURCE_PLL: PLL1Q selected as USB clock
  • RCC_USBCLKSOURCE_PLL3: PLL3Q Clock selected as USB clock
  • RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock

◆ RCC_CRS_FLAG_ERROR_MASK

#define RCC_CRS_FLAG_ERROR_MASK   ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))

Clear the CRS specified FLAG.

Parameters
__FLAG__specifies the flag to clear. This parameter can be one of the following values:
Note
RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR
Return values
None

◆ RCC_CRS_IT_ERROR_MASK

#define RCC_CRS_IT_ERROR_MASK   ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))

Clear the CRS interrupt pending bits.

Parameters
__INTERRUPT__specifies the interrupt pending bit to clear. This parameter can be any combination of the following values: