fsl_enet.h

/*
 * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
 * Copyright 2016-2022 NXP
 * All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */
#ifndef _FSL_ENET_H_
#define _FSL_ENET_H_
 
#include "fsl_common.h"
#if defined(FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET) && FSL_FEATURE_MEMORY_HAS_ADDRESS_OFFSET
#include "fsl_memory.h"
#endif
/*******************************************************************************
 * Definitions
 ******************************************************************************/
 
#define FSL_ENET_DRIVER_VERSION (MAKE_VERSION(2, 6, 3))
#ifndef FSL_FEATURE_ENET_QUEUE
#define FSL_FEATURE_ENET_QUEUE 1 /* Singal queue for previous IP. */
#endif
#define ENET_BUFFDESCRIPTOR_RX_EMPTY_MASK       0x8000U 
#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER1_MASK  0x4000U 
#define ENET_BUFFDESCRIPTOR_RX_WRAP_MASK        0x2000U 
#define ENET_BUFFDESCRIPTOR_RX_SOFTOWNER2_Mask  0x1000U 
#define ENET_BUFFDESCRIPTOR_RX_LAST_MASK        0x0800U 
#define ENET_BUFFDESCRIPTOR_RX_MISS_MASK        0x0100U 
#define ENET_BUFFDESCRIPTOR_RX_BROADCAST_MASK   0x0080U 
#define ENET_BUFFDESCRIPTOR_RX_MULTICAST_MASK   0x0040U 
#define ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK 0x0020U 
#define ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK     0x0010U 
#define ENET_BUFFDESCRIPTOR_RX_CRC_MASK         0x0004U 
#define ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK     0x0002U 
#define ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK       0x0001U 
 
#define ENET_BUFFDESCRIPTOR_TX_READY_MASK       0x8000U 
#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER1_MASK 0x4000U 
#define ENET_BUFFDESCRIPTOR_TX_WRAP_MASK        0x2000U 
#define ENET_BUFFDESCRIPTOR_TX_SOFTOWENER2_MASK 0x1000U 
#define ENET_BUFFDESCRIPTOR_TX_LAST_MASK        0x0800U 
#define ENET_BUFFDESCRIPTOR_TX_TRANMITCRC_MASK  0x0400U 
 
/* Extended control regions for enhanced buffer descriptors. */
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
#define ENET_BUFFDESCRIPTOR_RX_IPV4_MASK             0x0001U 
#define ENET_BUFFDESCRIPTOR_RX_IPV6_MASK             0x0002U 
#define ENET_BUFFDESCRIPTOR_RX_VLAN_MASK             0x0004U 
#define ENET_BUFFDESCRIPTOR_RX_PROTOCOLCHECKSUM_MASK 0x0010U 
#define ENET_BUFFDESCRIPTOR_RX_IPHEADCHECKSUM_MASK   0x0020U 
 
#define ENET_BUFFDESCRIPTOR_RX_INTERRUPT_MASK 0x0080U 
#define ENET_BUFFDESCRIPTOR_RX_UNICAST_MASK   0x0100U 
#define ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK 0x0200U 
#define ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK    0x0400U 
#define ENET_BUFFDESCRIPTOR_RX_MACERR_MASK    0x8000U 
 
#define ENET_BUFFDESCRIPTOR_TX_ERR_MASK              0x8000U 
#define ENET_BUFFDESCRIPTOR_TX_UNDERFLOWERR_MASK     0x2000U 
#define ENET_BUFFDESCRIPTOR_TX_EXCCOLLISIONERR_MASK  0x1000U 
#define ENET_BUFFDESCRIPTOR_TX_FRAMEERR_MASK         0x0800U 
#define ENET_BUFFDESCRIPTOR_TX_LATECOLLISIONERR_MASK 0x0400U 
#define ENET_BUFFDESCRIPTOR_TX_OVERFLOWERR_MASK      0x0200U 
#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMPERR_MASK     0x0100U 
 
#define ENET_BUFFDESCRIPTOR_TX_INTERRUPT_MASK     0x4000U 
#define ENET_BUFFDESCRIPTOR_TX_TIMESTAMP_MASK     0x2000U 
#define ENET_BUFFDESCRIPTOR_TX_PROTOCHECKSUM_MASK 0x1000U 
#define ENET_BUFFDESCRIPTOR_TX_IPCHECKSUM_MASK    0x0800U 
#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
#define ENET_BUFFDESCRIPTOR_TX_USETXLAUNCHTIME_MASK 0x0100U 
#define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK       0x00F0U 
#define ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT      4U      
#define ENET_BD_FTYPE(n) \
    (((uint32_t)(n) << ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_SHIFT) & ENET_BUFFDESCRIPTOR_TX_FRAMETYPE_MASK)
#endif /* FSL_FEATURE_ENET_HAS_AVB */
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
#define ENET_BUFFDESCRIPTOR_RX_ERR_MASK                                        \
    (ENET_BUFFDESCRIPTOR_RX_TRUNC_MASK | ENET_BUFFDESCRIPTOR_RX_OVERRUN_MASK | \
     ENET_BUFFDESCRIPTOR_RX_LENVLIOLATE_MASK | ENET_BUFFDESCRIPTOR_RX_NOOCTET_MASK | ENET_BUFFDESCRIPTOR_RX_CRC_MASK)
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
#define ENET_BUFFDESCRIPTOR_RX_EXT_ERR_MASK \
    (ENET_BUFFDESCRIPTOR_RX_MACERR_MASK | ENET_BUFFDESCRIPTOR_RX_PHYERR_MASK | ENET_BUFFDESCRIPTOR_RX_COLLISION_MASK)
#endif
 
#define ENET_FRAME_MAX_FRAMELEN 1518U 
#define ENET_FRAME_VLAN_TAGLEN  4U    
#define ENET_FRAME_CRC_LEN      4U    
#define ENET_FRAME_TX_LEN_LIMITATION(x) \
    ((((x)->RCR & ENET_RCR_MAX_FL_MASK) >> ENET_RCR_MAX_FL_SHIFT) - ENET_FRAME_CRC_LEN)
 
#define ENET_FIFO_MIN_RX_FULL  5U                                        
#define ENET_RX_MIN_BUFFERSIZE 256U                                      
#define ENET_PHY_MAXADDRESS    (ENET_MMFR_PA_MASK >> ENET_MMFR_PA_SHIFT) 
#if FSL_FEATURE_ENET_QUEUE > 1
#define ENET_TX_INTERRUPT                                                                                       \
    ((uint32_t)kENET_TxFrameInterrupt | (uint32_t)kENET_TxBufferInterrupt | (uint32_t)kENET_TxFrame1Interrupt | \
     (uint32_t)kENET_TxBuffer1Interrupt | (uint32_t)kENET_TxFrame2Interrupt |                                   \
     (uint32_t)kENET_TxBuffer2Interrupt) 
#define ENET_RX_INTERRUPT                                                                                       \
    ((uint32_t)kENET_RxFrameInterrupt | (uint32_t)kENET_RxBufferInterrupt | (uint32_t)kENET_RxFrame1Interrupt | \
     (uint32_t)kENET_RxBuffer1Interrupt | (uint32_t)kENET_RxFrame2Interrupt |                                   \
     (uint32_t)kENET_RxBuffer2Interrupt) 
#else
#define ENET_TX_INTERRUPT \
    ((uint32_t)kENET_TxFrameInterrupt | (uint32_t)kENET_TxBufferInterrupt) 
#define ENET_RX_INTERRUPT \
    ((uint32_t)kENET_RxFrameInterrupt | (uint32_t)kENET_RxBufferInterrupt) 
#endif                                                                     /* FSL_FEATURE_ENET_QUEUE > 1 */
#define ENET_TS_INTERRUPT \
    ((uint32_t)kENET_TsTimerInterrupt | (uint32_t)kENET_TsAvailInterrupt) 
#define ENET_ERR_INTERRUPT                                                                             \
    ((uint32_t)kENET_BabrInterrupt | (uint32_t)kENET_BabtInterrupt | (uint32_t)kENET_EBusERInterrupt | \
     (uint32_t)kENET_LateCollisionInterrupt | (uint32_t)kENET_RetryLimitInterrupt |                    \
     (uint32_t)kENET_UnderrunInterrupt | (uint32_t)kENET_PayloadRxInterrupt) 
 
enum
{
    kStatus_ENET_InitMemoryFail =
        MAKE_STATUS(kStatusGroup_ENET, 0U), 
    kStatus_ENET_RxFrameError = MAKE_STATUS(kStatusGroup_ENET, 1U), 
    kStatus_ENET_RxFrameFail  = MAKE_STATUS(kStatusGroup_ENET, 2U), 
    kStatus_ENET_RxFrameEmpty = MAKE_STATUS(kStatusGroup_ENET, 3U), 
    kStatus_ENET_RxFrameDrop  = MAKE_STATUS(kStatusGroup_ENET, 4U), 
    kStatus_ENET_TxFrameOverLen = MAKE_STATUS(kStatusGroup_ENET, 5U), 
    kStatus_ENET_TxFrameBusy    = MAKE_STATUS(kStatusGroup_ENET, 6U), 
    kStatus_ENET_TxFrameFail    = MAKE_STATUS(kStatusGroup_ENET, 7U), 
};
 
typedef enum _enet_mii_mode
{
    kENET_MiiMode  = 0U, 
    kENET_RmiiMode = 1U, 
#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
    kENET_RgmiiMode = 2U 
#endif                   /* FSL_FEATURE_ENET_HAS_AVB */
} enet_mii_mode_t;
 
typedef enum _enet_mii_speed
{
    kENET_MiiSpeed10M  = 0U, 
    kENET_MiiSpeed100M = 1U, 
#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
    kENET_MiiSpeed1000M = 2U 
#endif                       /* FSL_FEATURE_ENET_HAS_AVB */
} enet_mii_speed_t;
 
typedef enum _enet_mii_duplex
{
    kENET_MiiHalfDuplex = 0U, 
    kENET_MiiFullDuplex       
} enet_mii_duplex_t;
 
typedef enum _enet_mii_write
{
    kENET_MiiWriteNoCompliant = 0U, 
    kENET_MiiWriteValidFrame        
} enet_mii_write_t;
 
typedef enum _enet_mii_read
{
    kENET_MiiReadValidFrame  = 2U, 
    kENET_MiiReadNoCompliant = 3U  
} enet_mii_read_t;
 
#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO
typedef enum _enet_mii_extend_opcode
{
    kENET_MiiAddrWrite_C45  = 0U, 
    kENET_MiiWriteFrame_C45 = 1U, 
    kENET_MiiReadFrame_C45  = 3U  
} enet_mii_extend_opcode;
#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */
 
typedef enum _enet_special_control_flag
{
    kENET_ControlFlowControlEnable       = 0x0001U, 
    kENET_ControlRxPayloadCheckEnable    = 0x0002U, 
    kENET_ControlRxPadRemoveEnable       = 0x0004U, 
    kENET_ControlRxBroadCastRejectEnable = 0x0008U, 
    kENET_ControlMacAddrInsert           = 0x0010U, 
    kENET_ControlStoreAndFwdDisable      = 0x0020U, 
    kENET_ControlSMIPreambleDisable      = 0x0040U, 
    kENET_ControlPromiscuousEnable       = 0x0080U, 
    kENET_ControlMIILoopEnable           = 0x0100U, 
    kENET_ControlVLANTagEnable           = 0x0200U, 
#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
    kENET_ControlSVLANEnable      = 0x0400U, 
    kENET_ControlVLANUseSecondTag = 0x0800U  
#endif                                       /* FSL_FEATURE_ENET_HAS_AVB */
} enet_special_control_flag_t;
 
typedef enum _enet_interrupt_enable
{
    kENET_BabrInterrupt          = ENET_EIR_BABR_MASK,   
    kENET_BabtInterrupt          = ENET_EIR_BABT_MASK,   
    kENET_GraceStopInterrupt     = ENET_EIR_GRA_MASK,    
    kENET_TxFrameInterrupt       = ENET_EIR_TXF_MASK,    
    kENET_TxBufferInterrupt      = ENET_EIR_TXB_MASK,    
    kENET_RxFrameInterrupt       = ENET_EIR_RXF_MASK,    
    kENET_RxBufferInterrupt      = ENET_EIR_RXB_MASK,    
    kENET_MiiInterrupt           = ENET_EIR_MII_MASK,    
    kENET_EBusERInterrupt        = ENET_EIR_EBERR_MASK,  
    kENET_LateCollisionInterrupt = ENET_EIR_LC_MASK,     
    kENET_RetryLimitInterrupt    = ENET_EIR_RL_MASK,     
    kENET_UnderrunInterrupt      = ENET_EIR_UN_MASK,     
    kENET_PayloadRxInterrupt     = ENET_EIR_PLR_MASK,    
    kENET_WakeupInterrupt        = ENET_EIR_WAKEUP_MASK, 
#if FSL_FEATURE_ENET_QUEUE > 1
    kENET_RxFlush2Interrupt  = ENET_EIR_RXFLUSH_2_MASK, 
    kENET_RxFlush1Interrupt  = ENET_EIR_RXFLUSH_1_MASK, 
    kENET_RxFlush0Interrupt  = ENET_EIR_RXFLUSH_0_MASK, 
    kENET_TxFrame2Interrupt  = ENET_EIR_TXF2_MASK,      
    kENET_TxBuffer2Interrupt = ENET_EIR_TXB2_MASK,      
    kENET_RxFrame2Interrupt  = ENET_EIR_RXF2_MASK,      
    kENET_RxBuffer2Interrupt = ENET_EIR_RXB2_MASK,      
    kENET_TxFrame1Interrupt  = ENET_EIR_TXF1_MASK,      
    kENET_TxBuffer1Interrupt = ENET_EIR_TXB1_MASK,      
    kENET_RxFrame1Interrupt  = ENET_EIR_RXF1_MASK,      
    kENET_RxBuffer1Interrupt = ENET_EIR_RXB1_MASK,      
#endif                                                  /* FSL_FEATURE_ENET_QUEUE > 1 */
    kENET_TsAvailInterrupt = ENET_EIR_TS_AVAIL_MASK,    
    kENET_TsTimerInterrupt = ENET_EIR_TS_TIMER_MASK     
} enet_interrupt_enable_t;
 
typedef enum _enet_event
{
    kENET_RxEvent,            
    kENET_TxEvent,            
    kENET_ErrEvent,           
    kENET_WakeUpEvent,        
    kENET_TimeStampEvent,     
    kENET_TimeStampAvailEvent 
} enet_event_t;
 
#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
typedef enum _enet_idle_slope
{
    kENET_IdleSlope1    = 1U,    
    kENET_IdleSlope2    = 2U,    
    kENET_IdleSlope4    = 4U,    
    kENET_IdleSlope8    = 8U,    
    kENET_IdleSlope16   = 16U,   
    kENET_IdleSlope32   = 32U,   
    kENET_IdleSlope64   = 64U,   
    kENET_IdleSlope128  = 128U,  
    kENET_IdleSlope256  = 256U,  
    kENET_IdleSlope384  = 384U,  
    kENET_IdleSlope512  = 512U,  
    kENET_IdleSlope640  = 640U,  
    kENET_IdleSlope768  = 768U,  
    kENET_IdleSlope896  = 896U,  
    kENET_IdleSlope1024 = 1024U, 
    kENET_IdleSlope1152 = 1152U, 
    kENET_IdleSlope1280 = 1280U, 
    kENET_IdleSlope1408 = 1408U, 
    kENET_IdleSlope1536 = 1536U  
} enet_idle_slope_t;
#endif /* FSL_FEATURE_ENET_HAS_AVB */
 
typedef enum _enet_tx_accelerator
{
    kENET_TxAccelIsShift16Enabled  = ENET_TACC_SHIFT16_MASK, 
    kENET_TxAccelIpCheckEnabled    = ENET_TACC_IPCHK_MASK,   
    kENET_TxAccelProtoCheckEnabled = ENET_TACC_PROCHK_MASK   
} enet_tx_accelerator_t;
 
typedef enum _enet_rx_accelerator
{
    kENET_RxAccelPadRemoveEnabled  = ENET_RACC_PADREM_MASK,  
    kENET_RxAccelIpCheckEnabled    = ENET_RACC_IPDIS_MASK,   
    kENET_RxAccelProtoCheckEnabled = ENET_RACC_PRODIS_MASK,  
    kENET_RxAccelMacCheckEnabled   = ENET_RACC_LINEDIS_MASK, 
    kENET_RxAccelisShift16Enabled  = ENET_RACC_SHIFT16_MASK  
} enet_rx_accelerator_t;
 
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
typedef enum _enet_ptp_event_type
{
    kENET_PtpEventMsgType = 3U,   
    kENET_PtpSrcPortIdLen = 10U,  
    kENET_PtpEventPort    = 319U, 
    kENET_PtpGnrlPort     = 320U  
} enet_ptp_event_type_t;
 
typedef enum _enet_ptp_timer_channel
{
    kENET_PtpTimerChannel1 = 0U, 
    kENET_PtpTimerChannel2,      
    kENET_PtpTimerChannel3,      
    kENET_PtpTimerChannel4       
} enet_ptp_timer_channel_t;
 
typedef enum _enet_ptp_timer_channel_mode
{
    kENET_PtpChannelDisable                 = 0U,  
    kENET_PtpChannelRisingCapture           = 1U,  
    kENET_PtpChannelFallingCapture          = 2U,  
    kENET_PtpChannelBothCapture             = 3U,  
    kENET_PtpChannelSoftCompare             = 4U,  
    kENET_PtpChannelToggleCompare           = 5U,  
    kENET_PtpChannelClearCompare            = 6U,  
    kENET_PtpChannelSetCompare              = 7U,  
    kENET_PtpChannelClearCompareSetOverflow = 10U, 
    kENET_PtpChannelSetCompareClearOverflow = 11U, 
    kENET_PtpChannelPulseLowonCompare       = 14U, 
    kENET_PtpChannelPulseHighonCompare      = 15U  
} enet_ptp_timer_channel_mode_t;
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
typedef struct _enet_rx_bd_struct
{
    uint16_t length;  
    uint16_t control; 
    uint32_t buffer;  
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
    uint16_t controlExtend0;  
    uint16_t controlExtend1;  
    uint16_t payloadCheckSum; 
    uint8_t headerLength;     
    uint8_t protocolTyte;     
    uint16_t reserved0;
    uint16_t controlExtend2; 
    uint32_t timestamp;      
    uint16_t reserved1;
    uint16_t reserved2;
    uint16_t reserved3;
    uint16_t reserved4;
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
} enet_rx_bd_struct_t;
 
typedef struct _enet_tx_bd_struct
{
    uint16_t length;  
    uint16_t control; 
    uint32_t buffer;  
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
    uint16_t controlExtend0; 
    uint16_t controlExtend1; 
#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
    uint16_t txLaunchTimeLow;  
    uint16_t txLaunchTimeHigh; 
#else
    uint16_t reserved0;
    uint16_t reserved1;
#endif /* FSL_FEATURE_ENET_HAS_AVB */
    uint16_t reserved2;
    uint16_t controlExtend2; 
    uint32_t timestamp;      
    uint16_t reserved3;
    uint16_t reserved4;
    uint16_t reserved5;
    uint16_t reserved6;
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
} enet_tx_bd_struct_t;
 
typedef struct _enet_data_error_stats
{
    uint32_t statsRxLenGreaterErr; 
    uint32_t statsRxAlignErr;      
    uint32_t statsRxFcsErr;        
    uint32_t statsRxOverRunErr;    
    uint32_t statsRxTruncateErr;   
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
    uint32_t statsRxProtocolChecksumErr; 
    uint32_t statsRxIpHeadChecksumErr;   
    uint32_t statsRxMacErr;              
    uint32_t statsRxPhyErr;              
    uint32_t statsRxCollisionErr;        
    uint32_t statsTxErr;                 
    uint32_t statsTxFrameErr;            
    uint32_t statsTxOverFlowErr;         
    uint32_t statsTxLateCollisionErr;    
    uint32_t statsTxExcessCollisionErr;  
    uint32_t statsTxUnderFlowErr;        
    uint32_t statsTxTsErr;               
#endif                                   /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
} enet_data_error_stats_t;
 
typedef struct _enet_rx_frame_error
{
    bool statsRxTruncateErr : 1; 
    bool statsRxOverRunErr : 1;  
    bool statsRxFcsErr : 1;      
    bool : 1;
    bool statsRxAlignErr : 1;      
    bool statsRxLenGreaterErr : 1; 
    uint32_t : 19;
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
    bool statsRxCollisionErr : 1; 
    bool statsRxPhyErr : 1;       
    uint8_t : 4;
    bool statsRxMacErr : 1; 
#endif                      /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
} enet_rx_frame_error_t;
 
typedef struct _enet_transfer_stats
{
    uint32_t statsRxFrameCount;      
    uint32_t statsRxFrameOk;         
    uint32_t statsRxCrcErr;          
    uint32_t statsRxAlignErr;        
    uint32_t statsRxDropInvalidSFD;  
    uint32_t statsRxFifoOverflowErr; 
    uint32_t statsTxFrameCount;      
    uint32_t statsTxFrameOk;         
    uint32_t statsTxCrcAlignErr;     
    uint32_t statsTxFifoUnderRunErr; 
} enet_transfer_stats_t;
 
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
typedef struct _enet_ptp_time
{
    uint64_t second;     
    uint32_t nanosecond; 
} enet_ptp_time_t;
 
typedef struct _enet_ptp_time_data
{
    uint8_t version;                             
    uint8_t sourcePortId[kENET_PtpSrcPortIdLen]; 
    uint16_t sequenceId;                         
    uint8_t messageType;                         
    enet_ptp_time_t timeStamp;                   
} enet_ptp_time_data_t;
 
typedef struct _enet_ptp_config
{
    enet_ptp_timer_channel_t channel; 
    uint32_t ptp1588ClockSrc_Hz;      
} enet_ptp_config_t;
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
typedef struct enet_frame_info
{
    void *context; 
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
    bool isTsAvail;            
    enet_ptp_time_t timeStamp; 
#endif
} enet_frame_info_t;
 
typedef struct _enet_tx_dirty_ring
{
    enet_frame_info_t *txDirtyBase; 
    uint16_t txGenIdx;              
    uint16_t txConsumIdx;           
    uint16_t txRingLen;             
    bool isFull;                    
} enet_tx_dirty_ring_t;
 
typedef void *(*enet_rx_alloc_callback_t)(ENET_Type *base, void *userData, uint8_t ringId);
 
typedef void (*enet_rx_free_callback_t)(ENET_Type *base, void *buffer, void *userData, uint8_t ringId);
 
typedef struct _enet_buffer_config
{
    uint16_t rxBdNumber;      
    uint16_t txBdNumber;      
    uint16_t rxBuffSizeAlign; 
    uint16_t txBuffSizeAlign; 
    volatile enet_rx_bd_struct_t
        *rxBdStartAddrAlign; 
    volatile enet_tx_bd_struct_t
        *txBdStartAddrAlign;        
    uint8_t *rxBufferAlign;         
    uint8_t *txBufferAlign;         
    bool rxMaintainEnable;          
    bool txMaintainEnable;          
    enet_frame_info_t *txFrameInfo; 
} enet_buffer_config_t;
 
#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE
typedef struct _enet_intcoalesce_config
{
    uint8_t txCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; 
    uint16_t txCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; 
    uint8_t rxCoalesceFrameCount[FSL_FEATURE_ENET_QUEUE]; 
    uint16_t rxCoalesceTimeCount[FSL_FEATURE_ENET_QUEUE]; 
} enet_intcoalesce_config_t;
#endif /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */
 
#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
typedef struct _enet_avb_config
{
    uint16_t rxClassifyMatch[FSL_FEATURE_ENET_QUEUE - 1];    
    enet_idle_slope_t idleSlope[FSL_FEATURE_ENET_QUEUE - 1]; 
} enet_avb_config_t;
#endif /* FSL_FEATURE_ENET_HAS_AVB */
 
/* Forward declaration of the handle typedef. */
typedef struct _enet_handle enet_handle_t;
 
typedef void (*enet_callback_t)(ENET_Type *base,
                                enet_handle_t *handle,
#if FSL_FEATURE_ENET_QUEUE > 1
                                uint32_t ringId,
#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
                                enet_event_t event,
                                enet_frame_info_t *frameInfo,
                                void *userData);
 
typedef struct _enet_config
{
    uint32_t macSpecialConfig;    
    uint32_t interrupt;           
    uint16_t rxMaxFrameLen;       
    enet_mii_mode_t miiMode;      
    enet_mii_speed_t miiSpeed;    
    enet_mii_duplex_t miiDuplex;  
    uint8_t rxAccelerConfig;      
    uint8_t txAccelerConfig;      
    uint16_t pauseDuration;       
    uint8_t rxFifoEmptyThreshold; 
#if defined(FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD) && FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD
    uint8_t rxFifoStatEmptyThreshold; 
#endif                                /* FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD */
    uint8_t rxFifoFullThreshold;      
    uint8_t txFifoWatermark;          
#if defined(FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE) && FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE
    enet_intcoalesce_config_t *intCoalesceCfg; 
#endif                                         /* FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE */
    uint8_t ringNum;                           
    enet_rx_alloc_callback_t rxBuffAlloc; 
    enet_rx_free_callback_t rxBuffFree;   
    enet_callback_t callback;             
    void *userData;                       
} enet_config_t;
 
typedef struct _enet_tx_bd_ring
{
    volatile enet_tx_bd_struct_t *txBdBase; 
    uint16_t txGenIdx;                      
    uint16_t txConsumIdx;                   
    volatile uint16_t txDescUsed;           
    uint16_t txRingLen;                     
} enet_tx_bd_ring_t;
 
typedef struct _enet_rx_bd_ring
{
    volatile enet_rx_bd_struct_t *rxBdBase; 
    uint16_t rxGenIdx;                      
    uint16_t rxRingLen;                     
} enet_rx_bd_ring_t;
 
struct _enet_handle
{
    enet_rx_bd_ring_t rxBdRing[FSL_FEATURE_ENET_QUEUE];       
    enet_tx_bd_ring_t txBdRing[FSL_FEATURE_ENET_QUEUE];       
    uint16_t rxBuffSizeAlign[FSL_FEATURE_ENET_QUEUE];         
    uint16_t txBuffSizeAlign[FSL_FEATURE_ENET_QUEUE];         
    bool rxMaintainEnable[FSL_FEATURE_ENET_QUEUE];            
    bool txMaintainEnable[FSL_FEATURE_ENET_QUEUE];            
    uint8_t ringNum;                                          
    enet_callback_t callback;                                 
    void *userData;                                           
    enet_tx_dirty_ring_t txDirtyRing[FSL_FEATURE_ENET_QUEUE]; 
    bool txReclaimEnable[FSL_FEATURE_ENET_QUEUE];             
    enet_rx_alloc_callback_t rxBuffAlloc; 
    enet_rx_free_callback_t rxBuffFree;   
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
    volatile enet_tx_bd_struct_t
        *txBdDirtyStatic[FSL_FEATURE_ENET_QUEUE]; 
    uint64_t msTimerSecond;                       
#endif
    uint8_t multicastCount[64]; 
#if defined(FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID) && FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID
    uint32_t enetClock;    
    uint32_t tsDelayCount; 
#endif
};
 
typedef struct _enet_buffer_struct
{
    void *buffer;    
    uint16_t length; 
} enet_buffer_struct_t;
 
typedef struct _enet_rx_frame_attribute_struct
{
    bool promiscuous; 
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
    uint32_t timestamp; 
#endif
} enet_rx_frame_attribute_t;
 
typedef struct _enet_rx_frame_struct
{
    enet_buffer_struct_t *rxBuffArray;     
    uint16_t totLen;                       
    enet_rx_frame_attribute_t rxAttribute; 
    enet_rx_frame_error_t rxFrameError;    
} enet_rx_frame_struct_t;
 
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
typedef struct _enet_tx_config_struct
{
    bool intEnable : 1;
    bool tsEnable : 1;
    bool autoProtocolChecksum : 1;
    bool autoIPChecksum : 1;
    uint8_t AVBFrameType : 4; 
    bool tltEnable : 1;       
    uint16_t tltLow;          
    uint16_t tltHigh;         
} enet_tx_config_struct_t;
#endif
 
typedef struct _enet_tx_frame_struct
{
    enet_buffer_struct_t *txBuffArray; 
    uint32_t txBuffNum;                
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
    enet_tx_config_struct_t txConfig; 
#endif
    void *context; 
} enet_tx_frame_struct_t;
 
#if FSL_FEATURE_ENET_QUEUE > 1
typedef void (*enet_isr_ring_t)(ENET_Type *base, enet_handle_t *handle, uint32_t ringId);
#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
typedef void (*enet_isr_t)(ENET_Type *base, enet_handle_t *handle);
 
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
extern const clock_ip_name_t s_enetClock[];
#if defined(FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE) && FSL_FEATURE_ENET_HAS_EXTRA_CLOCK_GATE
extern const clock_ip_name_t s_enetExtraClock[];
#endif
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
/*******************************************************************************
 * API
 ******************************************************************************/
 
#if defined(__cplusplus)
extern "C" {
#endif
 
uint32_t ENET_GetInstance(ENET_Type *base);
 
void ENET_GetDefaultConfig(enet_config_t *config);
 
status_t ENET_Up(ENET_Type *base,
                 enet_handle_t *handle,
                 const enet_config_t *config,
                 const enet_buffer_config_t *bufferConfig,
                 uint8_t *macAddr,
                 uint32_t srcClock_Hz);
 
status_t ENET_Init(ENET_Type *base,
                   enet_handle_t *handle,
                   const enet_config_t *config,
                   const enet_buffer_config_t *bufferConfig,
                   uint8_t *macAddr,
                   uint32_t srcClock_Hz);
 
void ENET_Down(ENET_Type *base);
 
void ENET_Deinit(ENET_Type *base);
 
static inline void ENET_Reset(ENET_Type *base)
{
    base->ECR |= ENET_ECR_RESET_MASK;
}
 
/* @} */
 
void ENET_SetMII(ENET_Type *base, enet_mii_speed_t speed, enet_mii_duplex_t duplex);
 
void ENET_SetSMI(ENET_Type *base, uint32_t srcClock_Hz, bool isPreambleDisabled);
 
static inline bool ENET_GetSMI(ENET_Type *base)
{
    return (0U != (base->MSCR & 0x7EU));
}
 
static inline uint32_t ENET_ReadSMIData(ENET_Type *base)
{
    return (uint32_t)((base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT);
}
 
static inline void ENET_StartSMIWrite(
    ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, enet_mii_write_t operation, uint16_t data)
{
    base->MMFR = ENET_MMFR_ST(1U) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(regAddr) |
                 ENET_MMFR_TA(2U) | data;
}
 
static inline void ENET_StartSMIRead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, enet_mii_read_t operation)
{
    base->MMFR =
        ENET_MMFR_ST(1U) | ENET_MMFR_OP(operation) | ENET_MMFR_PA(phyAddr) | ENET_MMFR_RA(regAddr) | ENET_MMFR_TA(2U);
}
 
status_t ENET_MDIOWrite(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t data);
 
status_t ENET_MDIORead(ENET_Type *base, uint8_t phyAddr, uint8_t regAddr, uint16_t *pData);
 
#if defined(FSL_FEATURE_ENET_HAS_EXTEND_MDIO) && FSL_FEATURE_ENET_HAS_EXTEND_MDIO
static inline void ENET_StartExtC45SMIWriteReg(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr)
{
    base->MMFR = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiAddrWrite_C45) | ENET_MMFR_PA(portAddr) |
                 ENET_MMFR_RA(devAddr) | ENET_MMFR_TA(2) | ENET_MMFR_DATA(regAddr);
}
 
static inline void ENET_StartExtC45SMIWriteData(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t data)
{
    base->MMFR = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiWriteFrame_C45) | ENET_MMFR_PA(portAddr) |
                 ENET_MMFR_RA(devAddr) | ENET_MMFR_TA(2) | ENET_MMFR_DATA(data);
}
 
static inline void ENET_StartExtC45SMIReadData(ENET_Type *base, uint8_t portAddr, uint8_t devAddr)
{
    base->MMFR = ENET_MMFR_ST(0) | ENET_MMFR_OP(kENET_MiiReadFrame_C45) | ENET_MMFR_PA(portAddr) |
                 ENET_MMFR_RA(devAddr) | ENET_MMFR_TA(2);
}
 
status_t ENET_MDIOC45Write(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t data);
 
status_t ENET_MDIOC45Read(ENET_Type *base, uint8_t portAddr, uint8_t devAddr, uint16_t regAddr, uint16_t *pData);
#endif /* FSL_FEATURE_ENET_HAS_EXTEND_MDIO */
 
#if ((defined(FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY) || \
     (defined(FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY))
static inline void ENET_SetRGMIIClockDelay(ENET_Type *base, bool txEnabled, bool rxEnabled)
{
    uint32_t ecrReg = base->ECR;
 
#if defined(FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY
    /* Set for transmit clock delay. */
    if (txEnabled)
    {
        ecrReg |= ENET_ECR_TXC_DLY_MASK;
    }
    else
    {
        ecrReg &= ~ENET_ECR_TXC_DLY_MASK;
    }
#endif /* FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY */
 
#if defined(FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY) && FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY
    /* Set for receive clock delay. */
    if (rxEnabled)
    {
        ecrReg |= ENET_ECR_RXC_DLY_MASK;
    }
    else
    {
        ecrReg &= ~ENET_ECR_RXC_DLY_MASK;
    }
#endif /* FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY */
    base->ECR = ecrReg;
}
#endif
 
/* @} */
 
void ENET_SetMacAddr(ENET_Type *base, uint8_t *macAddr);
 
void ENET_GetMacAddr(ENET_Type *base, uint8_t *macAddr);
 
void ENET_AddMulticastGroup(ENET_Type *base, uint8_t *address);
 
void ENET_LeaveMulticastGroup(ENET_Type *base, uint8_t *address);
 
/* @} */
 
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
#if defined(FSL_FEATURE_ENET_HAS_AVB) && FSL_FEATURE_ENET_HAS_AVB
void ENET_AVBConfigure(ENET_Type *base, enet_handle_t *handle, const enet_avb_config_t *config);
#endif /* FSL_FEATURE_ENET_HAS_AVB */
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE  */
 
static inline void ENET_ActiveRead(ENET_Type *base)
{
    base->RDAR = ENET_RDAR_RDAR_MASK;
#if FSL_FEATURE_ENET_QUEUE > 1
    if (FSL_FEATURE_ENET_INSTANCE_QUEUEn(base) > 1)
    {
        base->RDAR1 = ENET_RDAR1_RDAR_MASK;
        base->RDAR2 = ENET_RDAR2_RDAR_MASK;
    }
#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
}
 
static inline void ENET_EnableSleepMode(ENET_Type *base, bool enable)
{
    if (enable)
    {
        /* When this field is set, MAC enters sleep mode. */
        base->ECR |= ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK;
    }
    else
    { /* MAC exits sleep mode. */
        base->ECR &= ~(ENET_ECR_SLEEP_MASK | ENET_ECR_MAGICEN_MASK);
    }
}
 
static inline void ENET_GetAccelFunction(ENET_Type *base, uint32_t *txAccelOption, uint32_t *rxAccelOption)
{
    assert(txAccelOption != NULL);
    assert(txAccelOption != NULL);
 
    *txAccelOption = base->TACC;
    *rxAccelOption = base->RACC;
}
 
/* @} */
 
static inline void ENET_EnableInterrupts(ENET_Type *base, uint32_t mask)
{
    base->EIMR |= mask;
}
 
static inline void ENET_DisableInterrupts(ENET_Type *base, uint32_t mask)
{
    base->EIMR &= ~mask;
}
 
static inline uint32_t ENET_GetInterruptStatus(ENET_Type *base)
{
    return base->EIR;
}
 
static inline void ENET_ClearInterruptStatus(ENET_Type *base, uint32_t mask)
{
    base->EIR = mask;
}
 
#if FSL_FEATURE_ENET_QUEUE > 1
void ENET_SetRxISRHandler(ENET_Type *base, enet_isr_ring_t ISRHandler);
 
void ENET_SetTxISRHandler(ENET_Type *base, enet_isr_ring_t ISRHandler);
 
#else
void ENET_SetRxISRHandler(ENET_Type *base, enet_isr_t ISRHandler);
 
void ENET_SetTxISRHandler(ENET_Type *base, enet_isr_t ISRHandler);
#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
 
void ENET_SetErrISRHandler(ENET_Type *base, enet_isr_t ISRHandler);
 
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
void ENET_SetTsISRHandler(ENET_Type *base, enet_isr_t ISRHandler);
 
void ENET_Set1588TimerISRHandler(ENET_Type *base, enet_isr_t ISRHandler);
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
/* @} */
 
void ENET_SetCallback(enet_handle_t *handle, enet_callback_t callback, void *userData);
 
void ENET_GetRxErrBeforeReadFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, uint8_t ringId);
 
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
status_t ENET_GetTxErrAfterSendFrame(enet_handle_t *handle, enet_data_error_stats_t *eErrorStatic, uint8_t ringId);
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
void ENET_GetStatistics(ENET_Type *base, enet_transfer_stats_t *statistics);
 
status_t ENET_GetRxFrameSize(enet_handle_t *handle, uint32_t *length, uint8_t ringId);
 
status_t ENET_ReadFrame(
    ENET_Type *base, enet_handle_t *handle, uint8_t *data, uint32_t length, uint8_t ringId, uint32_t *ts);
 
status_t ENET_SendFrame(ENET_Type *base,
                        enet_handle_t *handle,
                        const uint8_t *data,
                        uint32_t length,
                        uint8_t ringId,
                        bool tsFlag,
                        void *context);
 
status_t ENET_SetTxReclaim(enet_handle_t *handle, bool isEnable, uint8_t ringId);
 
void ENET_ReclaimTxDescriptor(ENET_Type *base, enet_handle_t *handle, uint8_t ringId);
 
status_t ENET_GetRxBuffer(ENET_Type *base,
                          enet_handle_t *handle,
                          void **buffer,
                          uint32_t *length,
                          uint8_t ringId,
                          bool *isLastBuff,
                          uint32_t *ts);
 
void ENET_ReleaseRxBuffer(ENET_Type *base, enet_handle_t *handle, void *buffer, uint8_t ringId);
 
status_t ENET_GetRxFrame(ENET_Type *base, enet_handle_t *handle, enet_rx_frame_struct_t *rxFrame, uint8_t ringId);
 
status_t ENET_StartTxFrame(ENET_Type *base, enet_handle_t *handle, enet_tx_frame_struct_t *txFrame, uint8_t ringId);
 
status_t ENET_SendFrameZeroCopy(ENET_Type *base,
                                enet_handle_t *handle,
                                const uint8_t *data,
                                uint32_t length,
                                uint8_t ringId,
                                bool tsFlag,
                                void *context);
 
#if FSL_FEATURE_ENET_QUEUE > 1
void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId);
 
void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle, uint32_t ringId);
 
void ENET_CommonFrame1IRQHandler(ENET_Type *base);
 
void ENET_CommonFrame2IRQHandler(ENET_Type *base);
#else
void ENET_TransmitIRQHandler(ENET_Type *base, enet_handle_t *handle);
 
void ENET_ReceiveIRQHandler(ENET_Type *base, enet_handle_t *handle);
#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
 
void ENET_ErrorIRQHandler(ENET_Type *base, enet_handle_t *handle);
 
void ENET_Ptp1588IRQHandler(ENET_Type *base);
 
void ENET_CommonFrame0IRQHandler(ENET_Type *base);
/* @} */
 
#ifdef ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
void ENET_Ptp1588ConfigureHandler(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig);
 
void ENET_Ptp1588Configure(ENET_Type *base, enet_handle_t *handle, enet_ptp_config_t *ptpConfig);
 
void ENET_Ptp1588StartTimer(ENET_Type *base, uint32_t ptpClkSrc);
 
static inline void ENET_Ptp1588StopTimer(ENET_Type *base)
{
    /* Disable PTP timer and reset the timer. */
    base->ATCR &= ~ENET_ATCR_EN_MASK;
    base->ATCR |= ENET_ATCR_RESTART_MASK;
}
 
void ENET_Ptp1588AdjustTimer(ENET_Type *base, uint32_t corrIncrease, uint32_t corrPeriod);
 
static inline void ENET_Ptp1588SetChannelMode(ENET_Type *base,
                                              enet_ptp_timer_channel_t channel,
                                              enet_ptp_timer_channel_mode_t mode,
                                              bool intEnable)
{
    uint32_t tcrReg = 0;
 
    tcrReg = ENET_TCSR_TMODE(mode) | (intEnable ? ENET_TCSR_TIE_MASK : 0U);
 
    /* Disable channel mode first. */
    base->CHANNEL[channel].TCSR = 0;
    base->CHANNEL[channel].TCSR = tcrReg;
}
 
#if defined(FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL) && FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL
static inline void ENET_Ptp1588SetChannelOutputPulseWidth(
    ENET_Type *base, enet_ptp_timer_channel_t channel, bool isOutputLow, uint8_t pulseWidth, bool intEnable)
{
    uint32_t tcrReg;
 
    tcrReg = ENET_TCSR_TIE(intEnable) | ENET_TCSR_TPWC(pulseWidth);
 
    if (isOutputLow)
    {
        tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseLowonCompare);
    }
    else
    {
        tcrReg |= ENET_TCSR_TMODE(kENET_PtpChannelPulseHighonCompare);
    }
 
    /* Disable channel mode first. */
    base->CHANNEL[channel].TCSR = 0;
    base->CHANNEL[channel].TCSR = tcrReg;
}
#endif /* FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL */
 
static inline void ENET_Ptp1588SetChannelCmpValue(ENET_Type *base, enet_ptp_timer_channel_t channel, uint32_t cmpValue)
{
    base->CHANNEL[channel].TCCR = cmpValue;
}
 
static inline bool ENET_Ptp1588GetChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel)
{
    return (0U != (base->CHANNEL[channel].TCSR & ENET_TCSR_TF_MASK));
}
 
static inline void ENET_Ptp1588ClearChannelStatus(ENET_Type *base, enet_ptp_timer_channel_t channel)
{
    base->CHANNEL[channel].TCSR |= ENET_TCSR_TF_MASK;
    base->TGSR = (1UL << (uint32_t)channel);
}
 
static inline uint32_t ENET_Ptp1588GetGlobalStatus(ENET_Type *base)
{
    return base->TGSR;
}
 
void ENET_Ptp1588GetTimerNoIrqDisable(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime);
 
void ENET_Ptp1588GetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime);
 
void ENET_Ptp1588SetTimer(ENET_Type *base, enet_handle_t *handle, enet_ptp_time_t *ptpTime);
 
void ENET_TimeStampIRQHandler(ENET_Type *base, enet_handle_t *handle);
 
/* @} */
 
#endif /* ENET_ENHANCEDBUFFERDESCRIPTOR_MODE */
 
#if defined(__cplusplus)
}
#endif
 
#endif /* _FSL_ENET_H_ */