at91rm9200_mem.h File Reference

AT91RM9200 Memory Controller definitions. More...

Go to the source code of this file.

Macros
#define	EBI_CSA   0x00
#define	EBI_CFGR   0x04
#define	EBI_CSA_CS4_CF   BIT4
#define	EBI_CSA_CS3_SMM   BIT3
#define	EBI_CSA_CS1_SDRAM   BIT1
#define	EBI_CSA_CS0_BF   BIT0
#define	EBI_CFGR_DBPU   BIT0
#define	SMC_CSR0   0x00
#define	SMC_CSR1   0x04
#define	SMC_CSR2   0x08
#define	SMC_CSR3   0x0C
#define	SMC_CSR4   0x10
#define	SMC_CSR5   0x14
#define	SMC_CSR6   0x18
#define	SMC_CSR7   0x1C
#define	SMC_CSR_RWHOLD(_x_)
#define	SMC_CSR_RWSETUP(_x_)
#define	SMC_CSR_ACSS_0   (0 << 16)
#define	SMC_CSR_ACSS_1   (1 << 16)
#define	SMC_CSR_ACSS_2   (2 << 16)
#define	SMC_CSR_ACSS_3   (3 << 16)
#define	SMC_CSR_DRP_NORMAL   0
#define	SMC_CSR_DRP_EARLY   BIT15
#define	SMC_CSR_DBW_16   (1 << 13)
#define	SMC_CSR_DBW_8   (2 << 13)
#define	SMC_CSR_BAT_16_1   0
#define	SMC_CSR_BAT_16_2   BIT12
#define	SMC_CSR_TDF(_x_)
#define	SMC_CSR_WSEN   BIT7
#define	SMC_CSR_NWS(_x_)
#define	SDRC_MR   0x00
#define	SDRC_TR   0x04
#define	SDRC_CR   0x08
#define	SDRC_SRR   0x0C
#define	SDRC_LPR   0x10
#define	SDRC_IER   0x14
#define	SDRC_IDR   0x18
#define	SDRC_IMR   0x1C
#define	SDRC_ISR   0x20
#define	SDRC_MR_DBW_16   BIT4
#define	SDRC_MR_NORM   (0 << 0)
#define	SDRC_MR_NOP   (1 << 0)
#define	SDRC_MR_PRE   (2 << 0)
#define	SDRC_MR_MRS   (3 << 0)
#define	SDRC_MR_REF   (4 << 0)
#define	SDRC_TR_COUNT(_x_)
#define	SDRC_CR_TXSR(_x_)
#define	SDRC_CR_TRAS(_x_)
#define	SDRC_CR_TRCD(_x_)
#define	SDRC_CR_TRP(_x_)
#define	SDRC_CR_TRC(_x_)
#define	SDRC_CR_TWR(_x_)
#define	SDRC_CR_CAS_2   (2 << 5)
#define	SDRC_CR_NB_2   0
#define	SDRC_CR_NB_4   BIT4
#define	SDRC_CR_NR_11   (0 << 2)
#define	SDRC_CR_NR_12   (1 << 2)
#define	SDRC_CR_NR_13   (2 << 2)
#define	SDRC_CR_NC_8   (0 << 0)
#define	SDRC_CR_NC_9   (1 << 0)
#define	SDRC_CR_NC_10   (2 << 0)
#define	SDRC_CR_NC_11   (3 << 0)
#define	SDRC_SRR_SRCB   BIT0
#define	SDRC_LPR_LPCB   BIT0
#define	SDRC_INT_RES   BIT0

Detailed Description

AT91RM9200 Memory Controller definitions.

Macro Definition Documentation

SDRC_CR_TRAS

#define SDRC_CR_TRAS

(

_x_

)

Value:

((_x_ & 0xf) << 23)

SDRC_CR_TRC

#define SDRC_CR_TRC

(

_x_

)

Value:

((_x_ & 0xf) << 11)

SDRC_CR_TRCD

#define SDRC_CR_TRCD

(

_x_

)

Value:

((_x_ & 0xf) << 19)

SDRC_CR_TRP

#define SDRC_CR_TRP

(

_x_

)

Value:

((_x_ & 0xf) << 15)

SDRC_CR_TWR

#define SDRC_CR_TWR

(

_x_

)

Value:

((_x_ & 0xf) << 7)

SDRC_CR_TXSR

#define SDRC_CR_TXSR

(

_x_

)

Value:

((_x_ & 0xf) << 27)

SDRC_TR_COUNT

#define SDRC_TR_COUNT

(

_x_

)

Value:

((_x_ & 0xfff) << 0)

SMC_CSR_NWS

#define SMC_CSR_NWS

(

_x_

)

Value:

((_x_ & 0x7f) << 0)

SMC_CSR_RWHOLD

#define SMC_CSR_RWHOLD

(

_x_

)

Value:

((_x_ & 0x3) << 28)

SMC_CSR_RWSETUP

#define SMC_CSR_RWSETUP

(

_x_

)

Value:

((_x_ & 0x3) << 24)

SMC_CSR_TDF

#define SMC_CSR_TDF

(

_x_

)

Value:

((_x_ & 0xf) << 8)