Atmel AT91RM9200 EMAC Register definitions.
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#define | EMAC_CTL 0x00 |
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#define | EMAC_CFG 0x04 |
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#define | EMAC_SR 0x08 |
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#define | EMAC_TAR 0x0C |
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#define | EMAC_TCR 0x10 |
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#define | EMAC_TSR 0x14 |
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#define | EMAC_RBQP 0x18 |
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#define | EMAC_RSR 0x20 |
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#define | EMAC_ISR 0x24 |
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#define | EMAC_IER 0x28 |
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#define | EMAC_IDR 0x2C |
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#define | EMAC_IMR 0x30 |
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#define | EMAC_MAN 0x34 |
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#define | EMAC_FRA 0x40 |
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#define | EMAC_SCOL 0x44 |
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#define | EMAC_MCOL 0x48 |
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#define | EMAC_OK 0x4C |
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#define | EMAC_SEQE 0x50 |
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#define | EMAC_ALE 0x54 |
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#define | EMAC_DTE 0x58 |
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#define | EMAC_LCOL 0x5C |
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#define | EMAC_ECOL 0x60 |
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#define | EMAC_CSE 0x64 |
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#define | EMAC_TUE 0x68 |
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#define | EMAC_CDE 0x6C |
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#define | EMAC_ELR 0x70 |
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#define | EMAC_RJB 0x74 |
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#define | EMAC_USF 0x78 |
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#define | EMAC_SQEE 0x7C |
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#define | EMAC_DRFC 0x80 |
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#define | EMAC_HSH 0x90 |
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#define | EMAC_HSL 0x94 |
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#define | EMAC_SA1L 0x98 |
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#define | EMAC_SA1H 0x9C |
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#define | EMAC_SA2L 0xA0 |
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#define | EMAC_SA2H 0xA4 |
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#define | EMAC_SA3L 0xA8 |
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#define | EMAC_SA3H 0xAC |
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#define | EMAC_SA4L 0xB0 |
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#define | EMAC_SA4H 0xB4 |
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#define | EMAC_CTL_LB BIT0 |
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#define | EMAC_CTL_LBL BIT1 |
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#define | EMAC_CTL_RE BIT2 |
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#define | EMAC_CTL_TE BIT3 |
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#define | EMAC_CTL_MPE BIT4 |
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#define | EMAC_CTL_CSR BIT5 |
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#define | EMAC_CTL_ISR BIT6 |
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#define | EMAC_CTL_WES BIT7 |
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#define | EMAC_CTL_BP BIT8 |
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#define | EMAC_CFG_SPD BIT0 |
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#define | EMAC_CFG_FD BIT1 |
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#define | EMAC_CFG_BR BIT2 |
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#define | EMAC_CFG_CAF BIT4 |
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#define | EMAC_CFG_NBC BIT5 |
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#define | EMAC_CFG_MTI BIT6 |
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#define | EMAC_CFG_UNI BIT7 |
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#define | EMAC_CFG_BIG BIT8 |
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#define | EMAC_CFG_EAE BIT9 |
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#define | EMAC_CFG_CLK_8 (0 << 10) |
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#define | EMAC_CFG_CLK_16 (1 << 10) |
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#define | EMAC_CFG_CLK_32 (2 << 10) |
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#define | EMAC_CFG_CLK_64 (3 << 10) |
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#define | EMAC_CFG_CLK_MASK (3 << 10) |
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#define | EMAC_CFG_RTY BIT12 |
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#define | EMAC_CFG_RMII BIT13 |
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#define | EMAC_LINK BIT0 |
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#define | EMAC_MDIO BIT1 |
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#define | EMAC_IDLE BIT2 |
| #define | EMAC_TCR_LEN(_x_) |
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#define | EMAC_TCR_NCRC BIT15 |
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#define | EMAC_TSR_OVR BIT0 |
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#define | EMAC_TSR_COL BIT1 |
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#define | EMAC_TSR_RLE BIT2 |
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#define | EMAC_TSR_TXIDLE BIT3 |
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#define | EMAC_TSR_BNQ BIT4 |
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#define | EMAC_TSR_COMP BIT5 |
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#define | EMAC_TSR_UND BIT6 |
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#define | EMAC_RSR_BNA BIT0 |
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#define | EMAC_RSR_REC BIT1 |
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#define | EMAC_RSR_OVR BIT2 |
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#define | EMAC_INT_DONE BIT0 |
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#define | EMAC_INT_RCOM BIT1 |
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#define | EMAC_INT_RBNA BIT2 |
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#define | EMAC_INT_TOVR BIT3 |
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#define | EMAC_INT_TUND BIT4 |
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#define | EMAC_INT_RTRY BIT5 |
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#define | EMAC_INT_TBRE BIT6 |
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#define | EMAC_INT_TCOM BIT7 |
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#define | EMAC_INT_TIDLE BIT8 |
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#define | EMAC_INT_LINK BIT9 |
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#define | EMAC_INT_ROVR BIT10 |
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#define | EMAC_INT_ABT BIT11 |
| #define | EMAC_MAN_DATA(_x_) |
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#define | EMAC_MAN_CODE (0x2 << 16) |
| #define | EMAC_MAN_REGA(_x_) |
| #define | EMAC_MAN_PHYA(_x_) |
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#define | EMAC_MAN_WRITE (0x1 << 28) |
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#define | EMAC_MAN_READ (0x2 << 28) |
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#define | EMAC_MAN_HIGH BIT30 |
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#define | EMAC_MAN_LOW BIT31 |
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#define | RXBUF_ADD_BASE_MASK 0xfffffffc |
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#define | RXBUF_ADD_WRAP BIT1 |
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#define | RXBUF_ADD_OWNED BIT0 |
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#define | RXBUF_STAT_BCAST BIT31 |
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#define | RXBUF_STAT_MULTI BIT30 |
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#define | RXBUF_STAT_UNI BIT29 |
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#define | RXBUF_STAT_EXT BIT28 |
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#define | RXBUF_STAT_UNK BIT27 |
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#define | RXBUF_STAT_LOC1 BIT26 |
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#define | RXBUF_STAT_LOC2 BIT25 |
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#define | RXBUF_STAT_LOC3 BIT24 |
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#define | RXBUF_STAT_LOC4 BIT23 |
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#define | RXBUF_STAT_LEN_MASK 0x7ff |
Atmel AT91RM9200 EMAC Register definitions.
◆ EMAC_MAN_DATA
| #define EMAC_MAN_DATA |
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| _x_ | ) |
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◆ EMAC_MAN_PHYA
| #define EMAC_MAN_PHYA |
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| _x_ | ) |
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◆ EMAC_MAN_REGA
| #define EMAC_MAN_REGA |
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| _x_ | ) |
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◆ EMAC_TCR_LEN
| #define EMAC_TCR_LEN |
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| _x_ | ) |
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