RTEMS  5.1
timer-defs.h
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1 
9 /*
10  * Copyright (c) 2014 Taller Technologies.
11  *
12  * @author Boretto Martin (martin.boretto@tallertechnologies.com)
13  * @author Diaz Marcos (marcos.diaz@tallertechnologies.com)
14  * @author Lenarduzzi Federico (federico.lenarduzzi@tallertechnologies.com)
15  * @author Daniel Chicco (daniel.chicco@tallertechnologies.com)
16  *
17  * The license and distribution terms for this file may be
18  * found in the file LICENSE in this distribution or at
19  * http://www.rtems.org/license/LICENSE.
20  */
21 
22 #ifndef LIBBSP_ARM_LPC176X_TIMER_DEFS_H
23 #define LIBBSP_ARM_LPC176X_TIMER_DEFS_H
24 
25 #include <bsp/common-types.h>
26 
27 #ifdef __cplusplus
28 extern "C" {
29 #endif /* __cplusplus */
30 
31 /* Timer 0 */
32 #define LPC176X_TMR0_BASE_ADDR 0x40004000U
33 
34 #define LPC176X_T0IR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
35  0x00U ) )
36 #define LPC176X_T0TCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
37  0x04U ) )
38 #define LPC176X_T0TC ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
39  0x08U ) )
40 #define LPC176X_T0PR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
41  0x0CU ) )
42 #define LPC176X_T0PC ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
43  0x10U ) )
44 #define LPC176X_T0MCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
45  0x14U ) )
46 #define LPC176X_T0MR0 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
47  0x18U ) )
48 #define LPC176X_T0MR1 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
49  0x1CU ) )
50 #define LPC176X_T0MR2 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
51  0x20U ) )
52 #define LPC176X_T0MR3 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
53  0x24U ) )
54 #define LPC176X_T0CCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
55  0x28U ) )
56 #define LPC176X_T0CR0 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
57  0x2CU ) )
58 #define LPC176X_T0CR1 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
59  0x30U ) )
60 #define LPC176X_T0CR2 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
61  0x34U ) )
62 #define LPC176X_T0CR3 ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
63  0x38U ) )
64 #define LPC176X_T0EMR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
65  0x3CU ) )
66 #define LPC176X_T0CTCR ( *(volatile uint32_t *) ( LPC176X_TMR0_BASE_ADDR + \
67  0x70U ) )
68 
69 /* Timer 1 */
70 #define LPC176X_TMR1_BASE_ADDR 0x40008000U
71 
72 #define LPC176X_T1IR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
73  0x00U ) )
74 #define LPC176X_T1TCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
75  0x04U ) )
76 #define LPC176X_T1TC ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
77  0x08U ) )
78 #define LPC176X_T1PR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
79  0x0CU ) )
80 #define LPC176X_T1PC ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
81  0x10U ) )
82 #define LPC176X_T1MCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
83  0x14U ) )
84 #define LPC176X_T1MR0 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
85  0x18U ) )
86 #define LPC176X_T1MR1 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
87  0x1CU ) )
88 #define LPC176X_T1MR2 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
89  0x20U ) )
90 #define LPC176X_T1MR3 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
91  0x24U ) )
92 #define LPC176X_T1CCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
93  0x28U ) )
94 #define LPC176X_T1CR0 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
95  0x2CU ) )
96 #define LPC176X_T1CR1 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
97  0x30U ) )
98 #define LPC176X_T1CR2 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
99  0x34U ) )
100 #define LPC176X_T1CR3 ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
101  0x38U ) )
102 #define LPC176X_T1EMR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
103  0x3CU ) )
104 #define LPC176X_T1CTCR ( *(volatile uint32_t *) ( LPC176X_TMR1_BASE_ADDR + \
105  0x70U ) )
106 
107 /* Timer 2 */
108 #define LPC176X_TMR2_BASE_ADDR 0x40090000U
109 
110 #define LPC176X_T2IR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
111  0x00U ) )
112 #define LPC176X_T2TCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
113  0x04U ) )
114 #define LPC176X_T2TC ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
115  0x08U ) )
116 #define LPC176X_T2PR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
117  0x0CU ) )
118 #define LPC176X_T2PC ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
119  0x10U ) )
120 #define LPC176X_T2MCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
121  0x14U ) )
122 #define LPC176X_T2MR0 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
123  0x18U ) )
124 #define LPC176X_T2MR1 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
125  0x1CU ) )
126 #define LPC176X_T2MR2 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
127  0x20U ) )
128 #define LPC176X_T2MR3 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
129  0x24U ) )
130 #define LPC176X_T2CCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
131  0x28U ) )
132 #define LPC176X_T2CR0 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
133  0x2CU ) )
134 #define LPC176X_T2CR1 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
135  0x30U ) )
136 #define LPC176X_T2CR2 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
137  0x34U ) )
138 #define LPC176X_T2CR3 ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
139  0x38U ) )
140 #define LPC176X_T2EMR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
141  0x3CU ) )
142 #define LPC176X_T2CTCR ( *(volatile uint32_t *) ( LPC176X_TMR2_BASE_ADDR + \
143  0x70U ) )
144 
145 /* Timer 3 */
146 #define LPC176X_TMR3_BASE_ADDR 0x40094000U
147 
148 #define LPC176X_T3IR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
149  0x00U ) )
150 #define LPC176X_T3TCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
151  0x04U ) )
152 #define LPC176X_T3TC ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
153  0x08U ) )
154 #define LPC176X_T3PR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
155  0x0CU ) )
156 #define LPC176X_T3PC ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
157  0x10U ) )
158 #define LPC176X_T3MCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
159  0x14U ) )
160 #define LPC176X_T3MR0 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
161  0x18U ) )
162 #define LPC176X_T3MR1 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
163  0x1CU ) )
164 #define LPC176X_T3MR2 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
165  0x20U ) )
166 #define LPC176X_T3MR3 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
167  0x24U ) )
168 #define LPC176X_T3CCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
169  0x28U ) )
170 #define LPC176X_T3CR0 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
171  0x2CU ) )
172 #define LPC176X_T3CR1 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
173  0x30U ) )
174 #define LPC176X_T3CR2 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
175  0x34U ) )
176 #define LPC176X_T3CR3 ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
177  0x38U ) )
178 #define LPC176X_T3EMR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
179  0x3CU ) )
180 #define LPC176X_T3CTCR ( *(volatile uint32_t *) ( LPC176X_TMR3_BASE_ADDR + \
181  0x70U ) )
182 
186 typedef struct {
190  volatile uint32_t IR;
194  volatile uint32_t TCR;
198  volatile uint32_t TC;
202  volatile uint32_t PR;
206  volatile uint32_t PC;
210  volatile uint32_t MCR;
214  volatile uint32_t MR[ 4 ];
218  volatile uint32_t CCR;
222  volatile uint32_t CR[ 2 ];
223  volatile uint32_t reserved0;
224  volatile uint32_t reserved1;
228  volatile uint32_t EMR;
229  volatile uint32_t reserved2[ 12 ];
233  volatile uint32_t CTCR;
234 } lpc176x_timer_device;
235 
236 #define LPC176X_PIN_SELECT_TIMER 3U
237 #define LPC176X_PINSEL_NO_PORT 999U
238 
239 #define LPC176X_TIMER_RESET ( 1U << 1U )
240 #define LPC176X_TIMER_START 1U
241 #define LPC176X_TIMER_MODE_COUNTER_SOURCE_CAP0 0U
242 #define LPC176X_TIMER_MODE_COUNTER_SOURCE_CAP1 ( 1U << 2U )
243 #define LPC176X_TIMER0_CAPTURE_PORTS { 58U, 59U }
244 #define LPC176X_TIMER1_CAPTURE_PORTS { 50U, 51U }
245 #define LPC176X_TIMER2_CAPTURE_PORTS { 4U, 5U }
246 #define LPC176X_TIMER3_CAPTURE_PORTS { 23U, 24U }
247 #define LPC176X_TIMER0_EMATCH_PORTS { 60U, \
248  61U, \
249  LPC176X_PINSEL_NO_PORT, \
250  LPC176X_PINSEL_NO_PORT }
251 #define LPC176X_TIMER1_EMATCH_PORTS { 54U, \
252  57U, \
253  LPC176X_PINSEL_NO_PORT, \
254  LPC176X_PINSEL_NO_PORT }
255 #define LPC176X_TIMER2_EMATCH_PORTS { 6U, 7U, 8U, 9U }
256 #define LPC176X_TIMER3_EMATCH_PORTS { 10U, \
257  11U, \
258  LPC176X_PINSEL_NO_PORT, \
259  LPC176X_PINSEL_NO_PORT }
260 #define LPC176X_TIMER_DEFAULT_RESOLUTION 1U
261 #define LPC176X_TIMER_MCR_MASK 7U
262 #define LPC176X_TIMER_MCR_MASK_SIZE 3U
263 #define LPC176X_TIMER_CCR_MASK 7U
264 #define LPC176X_TIMER_CCR_MASK_SIZE 3U
265 #define LPC176X_TIMER_EMR_MASK 3U
266 #define LPC176X_TIMER_EMR_MASK_SIZE 2U
267 #define LPC176X_TIMER_EMR_MASK_OFFSET 4U
268 #define LPC176X_TIMER_CLEAR_FUNCTION 0U
269 #define LPC176X_TIMER_PRESCALER_DIVISOR 1000000U
270 #define LPC176X_TIMER_VECTOR_NUMBER( timernumber ) ( timernumber + 1U )
271 #define LPC176X_TIMER_INTERRUPT_SOURCE_BIT( i ) ( 1U << i )
272 #define LPC176X_TIMER_MATCH_FUNCTION_COUNT 8U
273 #define LPC176X_TIMER_CAPTURE_FUNCTION_COUNT 8U
274 
275 #define LPC176X_ISR_NAME_STRING_SIZE 10U
276 
277 #define LPC176X_SET_MCR( mcr, match_port, function ) \
278  SET_FIELD( mcr, \
279  function, \
280  ( 0x7U << ( 3U * match_port ) ), \
281  ( 3U * match_port ) )
282 #define LPC176X_SET_CCR( mcr, capture_port, function ) \
283  SET_FIELD( mcr, function, ( 0x7U << ( 3U * capture_port ) ), \
284  ( 3U * capture_port ) )
285 #define LPC176X_SET_EMR( mcr, match_port, function ) \
286  SET_FIELD( mcr, function, ( 0x3U << ( 2U * match_port + 4U ) ), \
287  ( 2U * match_port + 4U ) )
288 
294 typedef enum {
295  LPC176X_CAPn_0,
296  LPC176X_CAPn_1,
297  LPC176X_CAPTURE_PORTS_COUNT
298 } lpc176x_capture_port;
299 
305 typedef enum {
306  LPC176X_MATn_0,
307  LPC176X_MATn_1,
308  LPC176X_MATn_2,
309  LPC176X_MATn_3,
310  LPC176X_EMATCH_PORTS_COUNT
311 } lpc176x_match_port;
312 
318 typedef enum {
319  LPC176X_TIMER_MODE_TIMER,
320  LPC176X_TIMER_MODE_COUNTER_RISING_CAP0,
321  LPC176X_TIMER_MODE_COUNTER_FALLING_CAP0,
322  LPC176X_TIMER_MODE_COUNTER_BOTH_CAP0,
323  LPC176X_TIMER_MODE_COUNTER_RISING_CAP1 = ( 1U & ( 1U << 2U ) ),
324  LPC176X_TIMER_MODE_COUNTER_FALLING_CAP1 = ( 2U & ( 1U << 2U ) ),
325  LPC176X_TIMER_MODE_COUNTER_BOTH_CAP1 = ( 3U & ( 1U << 2U ) ),
326 } lpc176x_timer_mode;
327 
333 typedef enum {
334  LPC176X_TIMER_0,
335  LPC176X_TIMER_1,
336  LPC176X_TIMER_2,
337  LPC176X_TIMER_3,
338  LPC176X_TIMER_COUNT
339 } lpc176x_timer_number;
340 
347 typedef enum {
348  LPC176X_MAT0_ISR_FUNCTION,
349  LPC176X_MAT1_ISR_FUNCTION,
350  LPC176X_MAT2_ISR_FUNCTION,
351  LPC176X_MAT3_ISR_FUNCTION,
352  LPC176X_CAP0_ISR_FUNCTION,
353  LPC176X_CAP1_ISR_FUNCTION,
354  LPC176X_ISR_FUNCTIONS_COUNT
355 } lpc176x_isr_function;
356 
364 typedef enum {
365  LPC176X_TIMER_MATCH_FUNCTION_NONE = 0U,
366  LPC176X_TIMER_MATCH_FUNCTION_INTERRUPT = 1U,
367  LPC176X_TIMER_MATCH_FUNCTION_RESET = ( 1U << 1U ),
368  LPC176X_TIMER_MATCH_FUNCTION_STOP = ( 1U << 2U )
369 } lpc176x_match_function;
370 
378 typedef enum {
379  LPC176X_TIMER_CAPTURE_FUNCTION_NONE = 0U,
380  LPC176X_TIMER_CAPTURE_FUNCTION_RISING = 1U,
381  LPC176X_TIMER_CAPTURE_FUNCTION_FALLING = ( 1U << 1U ),
382  LPC176X_TIMER_CAPTURE_FUNCTION_INTERRUPT = ( 1U << 2U )
383 } lpc176x_capture_function;
384 
391 typedef enum {
392  LPC176X_TIMER_EXTMATCH_FUNCTION_NONE,
393  LPC176X_TIMER_EXTMATCH_FUNCTION_CLEAR,
394  LPC176X_TIMER_EXTMATCH_FUNCTION_SET,
395  LPC176X_TIMER_EXTMATCH_FUNCTION_TOGGLE
396 } lpc176x_ext_match_function;
397 
404 typedef void (*lpc176x_isr_funct) ( const lpc176x_timer_number tnumber );
405 
410 typedef lpc176x_isr_funct const lpc176x_isr_funct_vector[
411  LPC176X_ISR_FUNCTIONS_COUNT ];
412 
416 typedef struct {
420  lpc176x_timer_device *const device;
424  const lpc176x_module module;
428  const lpc176x_pin_number pinselcap[ LPC176X_CAPTURE_PORTS_COUNT ];
432  const lpc176x_pin_number pinselemat[ LPC176X_EMATCH_PORTS_COUNT ];
433 } lpc176x_timer;
434 
438 typedef struct {
442  const lpc176x_isr_funct_vector *funct_vector;
443 } lpc176x_timer_functions;
444 
445 #ifdef __cplusplus
446 }
447 #endif /* __cplusplus */
448 
449 #endif /* LIBBSP_ARM_LPC176X_TIMER_DEFS_H */
lpc176x_timer_device::PR
volatile uint32_t PR
Prescale Register.
Definition: timer-defs.h:202
lpc176x_timer_mode
lpc176x_timer_mode
Timer modes of a timer.
Definition: timer-defs.h:318
lpc176x_timer_device::MCR
volatile uint32_t MCR
Match Control Register.
Definition: timer-defs.h:210
lpc176x_timer_number
lpc176x_timer_number
The timer devices in the board.
Definition: timer-defs.h:333
lpc176x_match_port
lpc176x_match_port
Match ports of a timer.
Definition: timer-defs.h:305
lpc176x_ext_match_function
lpc176x_ext_match_function
The possible functions at match, for the external ports.
Definition: timer-defs.h:391
lpc176x_timer::module
const lpc176x_module module
The module for the RTEMS module starting (power and clock).
Definition: timer-defs.h:424
lpc176x_timer_device::TC
volatile uint32_t TC
Timer Counter.
Definition: timer-defs.h:198
lpc176x_isr_function
lpc176x_isr_function
The index for the isr_funct_vector representing the functions that attends each possible interrupt so...
Definition: timer-defs.h:347
lpc176x_timer::device
lpc176x_timer_device *const device
The address of the controlling registers for the timer.
Definition: timer-defs.h:420
lpc176x_match_function
lpc176x_match_function
The possible functions at match. This options could be used together.
Definition: timer-defs.h:364
lpc176x_timer_device::CTCR
volatile uint32_t CTCR
Count Control Register.
Definition: timer-defs.h:233
lpc176x_timer_device::IR
volatile uint32_t IR
Interrupt Register.
Definition: timer-defs.h:190
lpc176x_timer_device::PC
volatile uint32_t PC
Prescale Counter.
Definition: timer-defs.h:206
lpc176x_timer_device::CCR
volatile uint32_t CCR
Capture Control Register.
Definition: timer-defs.h:218
lpc176x_timer
The Timer device representation.
Definition: timer-defs.h:416
lpc176x_isr_funct_vector
lpc176x_isr_funct const lpc176x_isr_funct_vector[LPC176X_ISR_FUNCTIONS_COUNT]
The vector of functions that attends each possible interrupt source for a timer.
Definition: timer-defs.h:411
lpc176x_timer_device::EMR
volatile uint32_t EMR
External Match Register.
Definition: timer-defs.h:228
lpc176x_timer_device
Represents the timer device registers.
Definition: timer-defs.h:186
lpc176x_capture_port
lpc176x_capture_port
Capture ports of a timer.
Definition: timer-defs.h:294
common-types.h
Definitions types used by some devices in common.
lpc176x_module
lpc176x_module
lpc176x module representation.
Definition: common-types.h:44
lpc176x_timer_device::TCR
volatile uint32_t TCR
Timer Control Register.
Definition: timer-defs.h:194
lpc176x_isr_funct
void(* lpc176x_isr_funct)(const lpc176x_timer_number tnumber)
A function that attends an interruption for a timer.
Definition: timer-defs.h:404
lpc176x_timer_functions::funct_vector
const lpc176x_isr_funct_vector * funct_vector
The vector of isr functions for this timer.
Definition: timer-defs.h:442
lpc176x_pin_number
uint32_t lpc176x_pin_number
A pin of the board.
Definition: common-types.h:32
lpc176x_timer_functions
The Timer functions.
Definition: timer-defs.h:438
lpc176x_capture_function
lpc176x_capture_function
The possible functions at capture. This options could be used together.
Definition: timer-defs.h:378
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