RTEMS
5.1
|
Data Fields | |
__IO uint32_t | XDMAC_GTYPE |
(Xdmac Offset: 0x00) Global Type Register | |
__I uint32_t | XDMAC_GCFG |
(Xdmac Offset: 0x04) Global Configuration Register | |
__IO uint32_t | XDMAC_GWAC |
(Xdmac Offset: 0x08) Global Weighted Arbiter Configuration Register | |
__O uint32_t | XDMAC_GIE |
(Xdmac Offset: 0x0C) Global Interrupt Enable Register | |
__O uint32_t | XDMAC_GID |
(Xdmac Offset: 0x10) Global Interrupt Disable Register | |
__I uint32_t | XDMAC_GIM |
(Xdmac Offset: 0x14) Global Interrupt Mask Register | |
__I uint32_t | XDMAC_GIS |
(Xdmac Offset: 0x18) Global Interrupt Status Register | |
__O uint32_t | XDMAC_GE |
(Xdmac Offset: 0x1C) Global Channel Enable Register | |
__O uint32_t | XDMAC_GD |
(Xdmac Offset: 0x20) Global Channel Disable Register | |
__I uint32_t | XDMAC_GS |
(Xdmac Offset: 0x24) Global Channel Status Register | |
__IO uint32_t | XDMAC_GRS |
(Xdmac Offset: 0x28) Global Channel Read Suspend Register | |
__IO uint32_t | XDMAC_GWS |
(Xdmac Offset: 0x2C) Global Channel Write Suspend Register | |
__O uint32_t | XDMAC_GRWS |
(Xdmac Offset: 0x30) Global Channel Read Write Suspend Register | |
__O uint32_t | XDMAC_GRWR |
(Xdmac Offset: 0x34) Global Channel Read Write Resume Register | |
__O uint32_t | XDMAC_GSWR |
(Xdmac Offset: 0x38) Global Channel Software Request Register | |
__I uint32_t | XDMAC_GSWS |
(Xdmac Offset: 0x3C) Global Channel Software Request Status Register | |
__O uint32_t | XDMAC_GSWF |
(Xdmac Offset: 0x40) Global Channel Software Flush Request Register | |
__I uint32_t | Reserved1 [3] |
XdmacChid | XDMAC_CHID [XDMACCHID_NUMBER] |
(Xdmac Offset: 0x50) chid = 0 .. 23 | |
__I uint32_t | Reserved2 [619] |
__IO uint32_t | XDMAC_VERSION |
(Xdmac Offset: 0xFFC) XDMAC Version Register | |