Sdramc hardware registers. More...

Data Fields
__IO uint32_t	SDRAMC_MR
	(Sdramc Offset: 0x00) SDRAMC Mode Register

__IO uint32_t	SDRAMC_TR
	(Sdramc Offset: 0x04) SDRAMC Refresh Timer Register

__IO uint32_t	SDRAMC_CR
	(Sdramc Offset: 0x08) SDRAMC Configuration Register

__I uint32_t	Reserved1 [1]

__IO uint32_t	SDRAMC_LPR
	(Sdramc Offset: 0x10) SDRAMC Low Power Register

__O uint32_t	SDRAMC_IER
	(Sdramc Offset: 0x14) SDRAMC Interrupt Enable Register

__O uint32_t	SDRAMC_IDR
	(Sdramc Offset: 0x18) SDRAMC Interrupt Disable Register

__I uint32_t	SDRAMC_IMR
	(Sdramc Offset: 0x1C) SDRAMC Interrupt Mask Register

__I uint32_t	SDRAMC_ISR
	(Sdramc Offset: 0x20) SDRAMC Interrupt Status Register

__IO uint32_t	SDRAMC_MDR
	(Sdramc Offset: 0x24) SDRAMC Memory Device Register

__IO uint32_t	SDRAMC_CFR1
	(Sdramc Offset: 0x28) SDRAMC Configuration Register 1

__IO uint32_t	SDRAMC_OCMS
	(Sdramc Offset: 0x2C) SDRAMC OCMS Register

__O uint32_t	SDRAMC_OCMS_KEY1
	(Sdramc Offset: 0x30) SDRAMC OCMS KEY1 Register

__O uint32_t	SDRAMC_OCMS_KEY2
	(Sdramc Offset: 0x34) SDRAMC OCMS KEY2 Register

__I uint32_t	Reserved2 [49]

__I uint32_t	SDRAMC_VERSION
	(Sdramc Offset: 0xFC) SDRAMC Version Register

Detailed Description

Sdramc hardware registers.

The documentation for this struct was generated from the following file:

Data Fields