Hsmci hardware registers. More...

Data Fields
__O uint32_t	HSMCI_CR
	(Hsmci Offset: 0x00) Control Register

__IO uint32_t	HSMCI_MR
	(Hsmci Offset: 0x04) Mode Register

__IO uint32_t	HSMCI_DTOR
	(Hsmci Offset: 0x08) Data Timeout Register

__IO uint32_t	HSMCI_SDCR
	(Hsmci Offset: 0x0C) SD/SDIO Card Register

__IO uint32_t	HSMCI_ARGR
	(Hsmci Offset: 0x10) Argument Register

__O uint32_t	HSMCI_CMDR
	(Hsmci Offset: 0x14) Command Register

__IO uint32_t	HSMCI_BLKR
	(Hsmci Offset: 0x18) Block Register

__IO uint32_t	HSMCI_CSTOR
	(Hsmci Offset: 0x1C) Completion Signal Timeout Register

__I uint32_t	HSMCI_RSPR [4]
	(Hsmci Offset: 0x20) Response Register

__I uint32_t	HSMCI_RDR
	(Hsmci Offset: 0x30) Receive Data Register

__O uint32_t	HSMCI_TDR
	(Hsmci Offset: 0x34) Transmit Data Register

__I uint32_t	Reserved1 [2]

__I uint32_t	HSMCI_SR
	(Hsmci Offset: 0x40) Status Register

__O uint32_t	HSMCI_IER
	(Hsmci Offset: 0x44) Interrupt Enable Register

__O uint32_t	HSMCI_IDR
	(Hsmci Offset: 0x48) Interrupt Disable Register

__I uint32_t	HSMCI_IMR
	(Hsmci Offset: 0x4C) Interrupt Mask Register

__IO uint32_t	HSMCI_DMA
	(Hsmci Offset: 0x50) DMA Configuration Register

__IO uint32_t	HSMCI_CFG
	(Hsmci Offset: 0x54) Configuration Register

__I uint32_t	Reserved2 [35]

__IO uint32_t	HSMCI_WPMR
	(Hsmci Offset: 0xE4) Write Protection Mode Register

__I uint32_t	HSMCI_WPSR
	(Hsmci Offset: 0xE8) Write Protection Status Register

__I uint32_t	Reserved3 [69]

__IO uint32_t	HSMCI_FIFO [256]
	(Hsmci Offset: 0x200) FIFO Memory Aperture0

__I uint32_t	HSMCI_VERSION
	(Hsmci Offset: 0xFC) Version Register

__I uint32_t	Reserved4 [64]

Detailed Description

Hsmci hardware registers.

The documentation for this struct was generated from the following file:

Data Fields